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Removed state counter reset
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@ -60,9 +60,7 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
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inout [7:0] D = DOE ? Dout : 8'bZ;
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inout [7:0] D = DOE ? Dout : 8'bZ;
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/* Inhibit output */
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/* Inhibit output */
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wire AROMSEL;
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output nINH = 1'bZ;
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LCELL AROMSEL_MC (.in(/*(A[15:12]==4'hD | A[15:12]==4'hE | A[15:12]==4'hF) & nWE & ~MODE*/0), .out(AROMSEL));
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output nINH = AROMSEL ? 1'b0 : 1'bZ;
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/* DRAM and ROM Control Signals */
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/* DRAM and ROM Control Signals */
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output nRCS = ~((~nIOSEL | (~nIOSTRB & IOROMEN)) & CSDBEN); // ROM chip select
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output nRCS = ~((~nIOSEL | (~nIOSTRB & IOROMEN)) & CSDBEN); // ROM chip select
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@ -108,15 +106,6 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
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// 1st rising edge of C7M in PHI0 (S3)
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// 1st rising edge of C7M in PHI0 (S3)
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always @(posedge C7M, negedge nRES) begin
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always @(posedge C7M, negedge nRES) begin
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if (~nRES) begin // Reset
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PHI1reg <= 0;
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PHI0seen <= 0;
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S <= 0;
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Ref <= 0;
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REGEN <= 0;
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IOROMEN <= 0;
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CSDBEN <= 0;
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end else begin
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// Synchronize state counter to S1 when just entering PHI1
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// Synchronize state counter to S1 when just entering PHI1
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PHI1reg <= PHI1; // Save old PHI1
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PHI1reg <= PHI1; // Save old PHI1
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if (~PHI1) PHI0seen <= 1; // PHI0seen set in PHI0
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if (~PHI1) PHI0seen <= 1; // PHI0seen set in PHI0
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@ -127,6 +116,20 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
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// Refresh counter allows DRAM refresh once every 13 cycles
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// Refresh counter allows DRAM refresh once every 13 cycles
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if (S==3) Ref <= (Ref[3:2]==2'b11) ? 4'h0 : Ref+1;
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if (S==3) Ref <= (Ref[3:2]==2'b11) ? 4'h0 : Ref+1;
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// Only drive Apple II data bus after state 4 to avoid bus fight.
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// Thus we wait 1.5 7M cycles (210 ns) into PHI0 before driving.
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// Same for driving the ROM/SRAM data bus (RD).
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// Similarly, only select the ROM chip starting at the end of S4.
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// This provides address setup time for write operations and
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// minimizes power consumption.
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CSDBEN <= S==4 | S==5 | S==6 | S==7;
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end
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always @(posedge C7M, negedge nRES) begin
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if (~nRES) begin
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REGEN <= 0;
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IOROMEN <= 0;
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end else begin
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// Disable IOSTRB ROM when accessing 0xCFFF.
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// Disable IOSTRB ROM when accessing 0xCFFF.
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if (S==3 & ~nIOSTRB & A[10:0]==11'h7FF) IOROMEN <= 1'b0;
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if (S==3 & ~nIOSTRB & A[10:0]==11'h7FF) IOROMEN <= 1'b0;
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@ -135,14 +138,6 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
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// Enable IOSTRB ROM when accessing CnXX in IOSEL ROM.
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// Enable IOSTRB ROM when accessing CnXX in IOSEL ROM.
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if (S==4 & ~nIOSEL) IOROMEN <= 1'b1;
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if (S==4 & ~nIOSEL) IOROMEN <= 1'b1;
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// Only drive Apple II data bus after state 4 to avoid bus fight.
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// Thus we wait 1.5 7M cycles (210 ns) into PHI0 before driving.
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// Same for driving the ROM/SRAM data bus (RD).
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// Similarly, only select the ROM chip starting at the end of S4.
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// This provides address setup time for write operations and
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// minimizes power consumption.
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CSDBEN <= S==4 | S==5 | S==6 | S==7;
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end
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end
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end
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end
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@ -189,9 +184,6 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
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/* DRAM RAS/CAS */
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/* DRAM RAS/CAS */
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always @(posedge C7M, negedge nRES) begin
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always @(posedge C7M, negedge nRES) begin
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if (~nRES) begin
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RASr <= 1'b0; ASel <= 1'b0; CASr <= 1'b0;
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end else begin
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RASr <= (S==1 & Ref==0) | // Refresh
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RASr <= (S==1 & Ref==0) | // Refresh
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(S==4 & RAMSEL & nWE) | // Read: Early RAS
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(S==4 & RAMSEL & nWE) | // Read: Early RAS
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(S==5 & RAMSEL & ~nWE); // Write: Late RAS
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(S==5 & RAMSEL & ~nWE); // Write: Late RAS
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@ -203,10 +195,7 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
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// Read: long, early CAS, gated later by RAMSEL
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// Read: long, early CAS, gated later by RAMSEL
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CASr <= (RAMSEL & ~nWE & (S==5 | S==6 | S==7));
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CASr <= (RAMSEL & ~nWE & (S==5 | S==6 | S==7));
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end
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end
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end
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always @(negedge C7M, negedge nRES) begin
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always @(negedge C7M, negedge nRES) begin
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if (~nRES) begin RASf <= 1'b0; CAS0f <= 1'b0; CAS1f <= 1'b0;
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end else begin
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RASf <= (S==4 & RAMSEL & nWE) | // Read: Early RAS
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RASf <= (S==4 & RAMSEL & nWE) | // Read: Early RAS
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(S==5 & RAMSEL & ~nWE); // Write: Late RAS
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(S==5 & RAMSEL & ~nWE); // Write: Late RAS
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@ -215,5 +204,4 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
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CAS1f <= (S==1 & Ref==0) | // Refresh
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CAS1f <= (S==1 & Ref==0) | // Refresh
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(S==6 & RAMSEL & Addr[22] & ~nWE); // Write: Late CAS
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(S==6 & RAMSEL & Addr[22] & ~nWE); // Write: Late CAS
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end
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end
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end
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endmodule
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endmodule
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