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This commit is contained in:
Zane Kaminski 2024-03-12 21:05:32 -04:00
parent c3716ebb82
commit 866dd401f1
81 changed files with 207899 additions and 422923 deletions
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14
.gitignore vendored
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@ -14,7 +14,6 @@ _autosave-*
*-save.pro
*-save.kicad_pcb
fp-info-cache
GR8RAM-backups/*
# Netlist files (exported from Eeschema)
*.net
@ -25,6 +24,13 @@ GR8RAM-backups/*
*.DS_Store
*.kicad_prl
cpld/db/*
cpld/incremental_db/*
cpld/GR8RAM.qws
CPLD/MAXII/db/*
CPLD/MAXII/incremental_db/*
CPLD/MAXII/GR8RAM.qws
CPLD/MAXV/db/*
CPLD/MAXV/incremental_db/*
CPLD/MAXV/GR8RAM.qws
/Hardware/MAX/GR8RAM-backups/*
/Hardware/LCMXO/GR8RAM-backups/*

568
CPLD/GR8RAM-old.v Normal file
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@ -0,0 +1,568 @@
module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
INTin, INTout, DMAin, DMAout,
nNMIout, nIRQout, nRDYout, nINHout, RWout, nDMAout,
RA, nWE, RD, RAdir, RDdir, nIOSEL, nDEVSEL, nIOSTRB,
SBA, SA, nRCS, nRAS, nCAS, nSWE, DQML, DQMH, RCKE, SD,
nFCS, FCK, MISO, MOSI);
/* Clock signals */
input C25M, PHI0;
reg PHI0r1, PHI0r2;
always @(posedge C25M) begin PHI0r1 <= PHI0; PHI0r2 <= PHI0r1; end
/* Reset filter */
input nRES;
reg [3:0] nRESf = 0;
reg nRESr = 0;
always @(posedge C25M) begin
nRESf[3:0] <= { nRESf[2:0], nRES };
nRESr <= nRESf[3] || nRESf[2] || nRESf[1] || nRESf[0];
end
/* Firmware select */
input [1:0] SetFW;
reg [1:0] SetFWr;
reg SetFWLoaded = 0;
always @(posedge C25M) begin
if (!SetFWLoaded) begin
SetFWLoaded <= 1;
SetFWr[1:0] <= SetFW[1:0];
end
end
wire [1:0] SetROM = ~SetFWr[1:0];
wire SetEN16MB = SetROM[1:0]==2'b11;
wire SetEN24bit = SetROM[1];
/* State counter from PHI0 rising edge */
reg [3:0] PS = 0;
wire PSStart = PS==0 && PHI0r1 && !PHI0r2;
always @(posedge C25M) begin
if (PSStart) PS <= 1;
else if (PS==0) PS <= 0;
else PS <= PS+1;
end
/* Long state counter: counts from 0 to $3FFF */
reg [13:0] LS = 0;
always @(posedge C25M) begin if (PS==15) LS <= LS+1; end
/* Init state */
output reg nRESout = 0;
reg [2:0] IS = 0;
always @(posedge C25M) begin
if (IS==7) nRESout <= 1;
else if (PS==15) begin
if (LS==14'h1FCE) IS <= 1; // PC all + load mode
else if (LS==14'h1FCF) IS <= 4; // AREF pause, SPI select
else if (LS==14'h1FFA) IS <= 5; // SPI flash command
else if (LS==14'h1FFF) IS <= 6; // Flash load driver
else if (LS==14'h3FFF) IS <= 7; // Operating mode
end
end
/* Apple IO area select signals */
input nIOSEL, nDEVSEL, nIOSTRB;
/* Apple address bus */
input [15:0] RA; input nWE;
reg [11:0] RAr; reg nWEr;
reg CXXXr;
always @(posedge PHI0) begin
CXXXr <= RA[15:12]==4'hC;
RAr[11:0] <= RA[11:0];
nWEr <= nWE;
end
/* Apple select signals */
wire ROMSpecRD = CXXXr && RAr[11:8]!=4'h0 && nWEr && ((RAr[11] && IOROMEN) || (!RAr[11]));
wire REGSpecSEL = CXXXr && RAr[11:8]==4'h0 && RAr[7] && REGEN;
wire BankSpecSEL = REGSpecSEL && RAr[3:0]==4'hF;
wire RAMRegSpecSEL = REGSpecSEL && RAr[3:0]==4'h3;
wire RAMSpecSEL = RAMRegSpecSEL && (!SetEN24bit || SetEN16MB || !Addr[23]);
wire AddrHSpecSEL = REGSpecSEL && RAr[3:0]==4'h2;
wire AddrMSpecSEL = REGSpecSEL && RAr[3:0]==4'h1;
wire AddrLSpecSEL = REGSpecSEL && RAr[3:0]==4'h0;
wire BankSEL = REGEN && !nDEVSEL && BankSpecSEL;
wire RAMRegSEL = !nDEVSEL && RAMRegSpecSEL;
wire RAMSEL = !nDEVSEL && RAMSpecSEL;
wire RAMWR = RAMSEL && !nWEr;
wire AddrHSEL = REGEN && !nDEVSEL && AddrHSpecSEL;
wire AddrMSEL = REGEN && !nDEVSEL && AddrMSpecSEL;
wire AddrLSEL = REGEN && !nDEVSEL && AddrLSpecSEL;
/* IOROMEN and REGEN control */
reg IOROMEN = 0;
reg REGEN = 0;
reg nIOSTRBr;
wire IOROMRES = RAr[10:0]==11'h7FF && !nIOSTRB && !nIOSTRBr;
always @(posedge C25M, negedge nRESr) begin
if (!nRESr) REGEN <= 0;
else if (PS==8 && !nIOSEL) REGEN <= 1;
end
always @(posedge C25M) begin
nIOSTRBr <= nIOSTRB;
if (!nRESr) IOROMEN <= 0;
else if (PS==8 && IOROMRES) IOROMEN <= 0;
else if (PS==8 && !nIOSEL) IOROMEN <= 1;
end
/* Apple data bus */
inout [7:0] RD = RDdir ? 8'bZ : RDD[7:0];
reg [7:0] RDD;
output RDdir = !(PHI0r2 && nWE && PHI0 &&
(!nDEVSEL || !nIOSEL || (!nIOSTRB && IOROMEN && RA[10:0]!=11'h7FF)));
/* Slinky address registers */
reg [23:0] Addr = 0;
reg AddrIncL = 0;
reg AddrIncM = 0;
reg AddrIncH = 0;
always @(posedge C25M, negedge nRESr) begin
if (!nRESr) begin
Addr[23:0] <= 24'h000000;
AddrIncL <= 0;
AddrIncM <= 0;
AddrIncH <= 0;
end else begin
if (PS==8 && RAMRegSEL) AddrIncL <= 1;
else AddrIncL <= 0;
if (PS==8 && AddrLSEL && !nWEr) begin
Addr[7:0] <= RD[7:0];
AddrIncM <= Addr[7] && !RD[7];
end else if (AddrIncL) begin
Addr[7:0] <= Addr[7:0]+1;
AddrIncM <= Addr[7:0]==8'hFF;
end else AddrIncM <= 0;
if (PS==8 && AddrMSEL && !nWEr) begin
Addr[15:8] <= RD[7:0];
AddrIncH <= Addr[15] && !RD[7];
end else if (AddrIncM) begin
Addr[15:8] <= Addr[15:8]+1;
AddrIncH <= Addr[15:8]==8'hFF;
end else AddrIncH <= 0;
if (PS==8 && AddrHSEL && !nWEr) begin
Addr[23:16] <= RD[7:0];
end else if (AddrIncH) begin
Addr[23:16] <= Addr[23:16]+1;
end
end
end
/* ROM bank register */
reg Bank = 0;
always @(posedge C25M, negedge nRESr) begin
if (!nRESr) Bank <= 0;
else if (PS==8 && BankSEL && !nWEr) begin
Bank <= RD[0];
end
end
/* SPI flash control signals */
output nFCS = FCKOE ? !FCS : 1'bZ;
reg FCS = 0;
output FCK = FCKOE ? FCKout : 1'bZ;
reg FCKOE = 0;
reg FCKout = 0;
inout MOSI = MOSIOE ? MOSIout : 1'bZ;
reg MOSIOE = 0;
input MISO;
always @(posedge C25M) begin
case (PS[3:0])
0: begin // NOP CKE
FCKout <= 1'b1;
end 1: begin // ACT
FCKout <= !(IS==5 || IS==6);
end 2: begin // RD
FCKout <= 1'b1;
end 3: begin // NOP CKE
FCKout <= !(IS==5 || IS==6);
end 4: begin // NOP CKE
FCKout <= 1'b1;
end 5: begin // NOP CKE
FCKout <= !(IS==5 || IS==6);
end 6: begin // NOP CKE
FCKout <= 1'b1;
end 7: begin // NOP CKE
FCKout <= !(IS==5 || IS==6);
end 8: begin // WR AP
FCKout <= 1'b1;
end 9: begin // NOP CKE
FCKout <= !(IS==5);
end 10: begin // PC all
FCKout <= 1'b1;
end 11: begin // AREF
FCKout <= !(IS==5);
end 12: begin // NOP CKE
FCKout <= 1'b1;
end 13: begin // NOP CKE
FCKout <= !(IS==5);
end 14: begin // NOP CKE
FCKout <= 1'b1;
end 15: begin // NOP CKE
FCKout <= !(IS==5);
end
endcase
FCS <= IS==4 || IS==5 || IS==6;
MOSIOE <= IS==5;
FCKOE <= IS==1 || IS==4 || IS==5 || IS==6 || IS==7;
end
/* SPI flash MOSI control */
reg MOSIout = 0;
always @(posedge C25M) begin
case (PS[3:0])
1: begin
case (LS[2:0])
3'h3: MOSIout <= 1'b0; // Command bit 7
3'h4: MOSIout <= 1'b0; // Address bit 23
3'h5: MOSIout <= 1'b0; // Address bit 15
3'h6: MOSIout <= 1'b0; // Address bit 7
default MOSIout <= 1'b0;
endcase
end 3: begin
case (LS[2:0])
3'h3: MOSIout <= 1'b0; // Command bit 6
3'h4: MOSIout <= 1'b0; // Address bit 22
3'h5: MOSIout <= SetROM[1]; // Address bit 14
3'h6: MOSIout <= 1'b0; // Address bit 6
default MOSIout <= 1'b0;
endcase
end 5: begin
case (LS[2:0])
3'h3: MOSIout <= 1'b1; // Command bit 5
3'h4: MOSIout <= 1'b0; // Address bit 21
3'h5: MOSIout <= SetROM[0]; // Address bit 13
3'h6: MOSIout <= 1'b0; // Address bit 5
default MOSIout <= 1'b0;
endcase
end 7: begin
case (LS[2:0])
3'h3: MOSIout <= 1'b1; // Command bit 4
3'h4: MOSIout <= 1'b0; // Address bit 20
3'h5: MOSIout <= 1'b0; // Address bit 12
3'h6: MOSIout <= 1'b0; // Address bit 4
default MOSIout <= 1'b0;
endcase
end 9: begin
case (LS[2:0])
3'h3: MOSIout <= 1'b1; // Command bit 3
3'h4: MOSIout <= 1'b0; // Address bit 19
3'h5: MOSIout <= 1'b0; // Address bit 11
3'h6: MOSIout <= 1'b0; // Address bit 3
default MOSIout <= 1'b0;
endcase
end 11: begin
case (LS[2:0])
3'h3: MOSIout <= 1'b0; // Command bit 2
3'h4: MOSIout <= 1'b0; // Address bit 18
3'h5: MOSIout <= 1'b0; // Address bit 10
3'h6: MOSIout <= 1'b0; // Address bit 2
default MOSIout <= 1'b0;
endcase
end 13: begin
case (LS[2:0])
3'h3: MOSIout <= 1'b1; // Command bit 1
3'h4: MOSIout <= 1'b0; // Address bit 16
3'h5: MOSIout <= 1'b0; // Address bit 9
3'h6: MOSIout <= 1'b0; // Address bit 1
default MOSIout <= 1'b0;
endcase
end 15: begin
case (LS[2:0])
3'h3: MOSIout <= 1'b1; // Command bit 0
3'h4: MOSIout <= 1'b0; // Address bit 15
3'h5: MOSIout <= 1'b0; // Address bit 7
3'h6: MOSIout <= 1'b0; // Address bit 0
default MOSIout <= 1'b0;
endcase
end
endcase
end
/* SDRAM data bus */
inout [7:0] SD = SDOE ? WRD[7:0] : 8'bZ;
reg [7:0] WRD;
reg SDOE = 0;
always @(posedge C25M) begin
case (PS[3:0])
0: begin // NOP CKE
if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
else WRD[7:0] <= RD[7:0];
end 1: begin // ACT
end 2: begin // RD
if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
else WRD[7:0] <= RD[7:0];
end 3: begin // NOP CKE
end 4: begin // NOP CKE
if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
else WRD[7:0] <= RD[7:0];
end 5: begin // NOP CKE
end 6: begin // NOP CKE
if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
else WRD[7:0] <= RD[7:0];
end 7: begin // NOP CKE
end 8: begin // WR AP
if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
else WRD[7:0] <= RD[7:0];
end 9: begin // NOP CKE
end 10: begin // PC all
if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
else WRD[7:0] <= RD[7:0];
end 11: begin // AREF
end 12: begin // NOP CKE
if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
else WRD[7:0] <= RD[7:0];
end 13: begin // NOP CKE
end 14: begin // NOP CKE
if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
else WRD[7:0] <= RD[7:0];
end 15: begin // NOP CKE
end
endcase
end
/* Apple data bus from SDRAM */
always @(negedge C25M) begin
if (PS==5) begin
if (AddrLSpecSEL) RDD[7:0] <= Addr[7:0];
else if (AddrMSpecSEL) RDD[7:0] <= Addr[15:8];
else if (AddrHSpecSEL) RDD[7:0] <= { SetEN24bit ? Addr[23:20] : 4'hF, Addr[19:16] };
else RDD[7:0] <= SD[7:0];
end
end
/* SDRAM command */
output reg RCKE = 1;
output reg nRCS = 1;
output reg nRAS = 1;
output reg nCAS = 1;
output reg nSWE = 1;
wire RefReqd = LS[1:0] == 2'b11;
always @(posedge C25M) begin
case (PS[3:0])
0: begin // NOP CKE / NOP CKD
RCKE <= PSStart && (IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL)));
nRCS <= 1;
nRAS <= 1;
nCAS <= 1;
nSWE <= 1;
SDOE <= 0;
end 1: begin // ACT CKE / NOP CKD (ACT)
RCKE <= IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL));
nRCS <= !(IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL)));
nRAS <= 0;
nCAS <= 1;
nSWE <= 1;
SDOE <= 0;
end 2: begin // RD CKE / NOP CKD (RD)
RCKE <= IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL);
nRCS <= !(IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL));
nRAS <= 1;
nCAS <= 0;
nSWE <= 1;
SDOE <= 0;
end 3: begin // NOP CKE / CKD
RCKE <= IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL);
nRCS <= 1;
nRAS <= 1;
nCAS <= 1;
nSWE <= 1;
SDOE <= 0;
end 4: begin // NOP CKD
RCKE <= 0;
nRCS <= 1;
nRAS <= 1;
nCAS <= 1;
nSWE <= 1;
SDOE <= 0;
end 5: begin // NOP CKD
RCKE <= 0;
nRCS <= 1;
nRAS <= 1;
nCAS <= 1;
nSWE <= 1;
SDOE <= 0;
end 6: begin // NOP CKD
RCKE <= 0;
nRCS <= 1;
nRAS <= 1;
nCAS <= 1;
nSWE <= 1;
SDOE <= 0;
end 7: begin // NOP CKE / CKD
RCKE <= IS==6 || (RAMWR && IS==7);
nRCS <= 1;
nRAS <= 1;
nCAS <= 1;
nSWE <= 1;
SDOE <= 0;
end 8: begin // WR AP CKE / NOP CKD (WR AP)
RCKE <= IS==6 || (RAMWR && IS==7);
nRCS <= !(IS==6 || (RAMWR && IS==7));
nRAS <= 1;
nCAS <= 0;
nSWE <= 0;
SDOE <= IS==6 || (RAMWR && IS==7);
end 9: begin // NOP CKE / NOP CKD
RCKE <= 1;
nRCS <= 1;
nRAS <= 1;
nCAS <= 1;
nSWE <= 1;
SDOE <= 0;
end 10: begin // PC all CKE / PC all CKD
RCKE <= IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd);
nRCS <= 0;
nRAS <= 0;
nCAS <= 1;
nSWE <= 0;
SDOE <= 0;
end 11: begin // LDM CKE / AREF CKE / NOP CKD
RCKE <= IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd);
nRCS <= !(IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd));
nRAS <= 0;
nCAS <= 0;
nSWE <= !(IS==1);
SDOE <= 0;
end default: begin // NOP CKD
RCKE <= 0;
nRCS <= 1;
nRAS <= 1;
nCAS <= 1;
nSWE <= 1;
SDOE <= 0;
end
endcase
end
/* SDRAM address */
output reg DQML = 1;
output reg DQMH = 1;
output reg [1:0] SBA;
output reg [12:0] SA;
always @(posedge C25M) begin
case (PS[3:0])
0: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 1: begin // ACT
DQML <= 1'b1;
DQMH <= 1'b1;
if (IS==6) begin
SBA[1:0] <= { 2'b10 };
SA[12:0] <= { 10'b0011000100, LS[12:10] };
end else if (RAMSpecSEL) begin
SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
SA[12:10] <= SetEN24bit ? Addr[22:20] : 3'b000;
SA[9:0] <= Addr[19:10];
end else begin
SBA[1:0] <= 2'b10;
SA[12:0] <= { 10'b0011000100, Bank, RAr[11:10] };
end
end 2: begin // RD
if (RAMSpecSEL) begin
SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
SA[12:0] <= { 4'b0011, Addr[9:1] };
DQML <= Addr[0];
DQMH <= !Addr[0];
end else begin
SBA[1:0] <= 2'b10;
SA[12:0] <= { 4'b0011, RAr[9:1]};
DQML <= RAr[0];
DQMH <= !RAr[0];
end
end 3: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 4: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 5: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 6: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 7: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 8: begin // WR AP
if (IS==6) begin
SBA[1:0] <= 2'b10;
SA[12:0] <= { 4'b0011, LS[9:1] };
DQML <= LS[0];
DQMH <= !LS[0];
end else begin
SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
SA[12:0] <= { 4'b0011, Addr[9:1] };
DQML <= Addr[0];
DQMH <= !Addr[0];
end
end 9: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 10: begin // PC all
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 11: begin // AREF / load mode
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0001000100000;
end 12: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 13: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 14: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 15: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end
endcase
end
/* DMA/INT in/out */
input INTin, DMAin;
output INTout = INTin;
output DMAout = DMAin;
/* Unused Pins */
output RAdir = 1;
output nDMAout = 1;
output nNMIout = 1;
output nINHout = 1;
output nRDYout = 1;
output nIRQout = 1;
output RWout = 1;
endmodule

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cpld/output_files/GR8RAM.sld → CPLD/MAXII/output_files/GR8RAM.sld
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0
cpld/output_files/GR8RAM.sta.rpt → CPLD/MAXII/output_files/GR8RAM.sta.rpt
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0
cpld/output_files/GR8RAM.sta.summary → CPLD/MAXII/output_files/GR8RAM.sta.summary
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0
cpld/output_files/GR8RAM.svf → CPLD/MAXII/output_files/GR8RAM.svf
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2750
Docs.kicad_sch
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4345
Documentation/Assembly.html
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13
Documentation/Initialization Sequence
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Init sequence
LS SDRAM Flash IS
-------------------------------------------------------------------
$0000-$1FCE Nothing Nothing 0
$1FCF Init: Precharge Nothing 1
$1FD0-$1FFA Init: AREF Pause SPI Select 4
$1FFB Init: AREF Pause Dual Read (0x3B) 5
$1FFC Init: AREF Pause A[23:16] (0) 5
$1FFD Init: AREF Pause A[15:08] (FW in 14:13) 5
$1FFE Init: AREF Pause A[07:00] (0) 5
$1FFF Init: AREF Pause Dummy 5
$2000-$3FFF Init: Write ROM Shift MISO into WRD 6

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GR8RAM.kicad_pcb
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75
GR8RAM.kicad_prl
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0
GR8RAM → Hardware/LCMXO2/GR8RAM
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Hardware/LCMXO2/GR8RAM-backups/GR8RAM-2024-03-09_222908.zip Normal file
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0
GR8RAM-cache.lib → Hardware/LCMXO2/GR8RAM-cache.lib
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94834
Hardware/LCMXO2/GR8RAM.kicad_pcb Normal file
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538
Hardware/LCMXO2/GR8RAM.kicad_pro Normal file
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10176
Hardware/LCMXO2/GR8RAM.kicad_sch Normal file
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4
Hardware/LCMXO2/fp-lib-table Normal file
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@ -0,0 +1,4 @@
(fp_lib_table
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(lib (name "stdpads")(type "KiCad")(uri "$(KIPRJMOD)/../../../stdpads.pretty")(options "")(descr ""))
)

7
Hardware/LCMXO2/sym-lib-table Normal file
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@ -0,0 +1,7 @@
(sym_lib_table
(version 7)
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(lib (name "GW_PLD")(type "KiCad")(uri "${KIPRJMOD}/../../../GW_Parts/GW_PLD.kicad_sym")(options "")(descr ""))
(lib (name "GW_Logic")(type "KiCad")(uri "${KIPRJMOD}/../../../GW_Parts/GW_Logic.kicad_sym")(options "")(descr ""))
(lib (name "GW_Power")(type "KiCad")(uri "${KIPRJMOD}/../../../GW_Parts/GW_Power.kicad_sym")(options "")(descr ""))
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1
Hardware/LCMXO2/~GR8RAM.kicad_sch.lck Normal file
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@ -0,0 +1 @@
{"hostname":"ZaneMac","username":"zane"}

0
gerber/GR8RAM-BOM.csv → Hardware/MAX/GR8RAM
View File

661
Hardware/MAX/GR8RAM-cache.lib Normal file
View File

@ -0,0 +1,661 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Connector_Generic_Conn_02x05_Odd_Even
#
DEF Connector_Generic_Conn_02x05_Odd_Even J 0 40 Y N 1 F N
F0 "J" 50 300 50 H V C CNN
F1 "Connector_Generic_Conn_02x05_Odd_Even" 50 -300 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_2x??_*
$ENDFPLIST
DRAW
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 250 150 -250 1 1 10 f
S 150 -195 100 -205 1 1 6 N
S 150 -95 100 -105 1 1 6 N
S 150 5 100 -5 1 1 6 N
S 150 105 100 95 1 1 6 N
S 150 205 100 195 1 1 6 N
X Pin_1 1 -200 200 150 R 50 50 1 1 P
X Pin_10 10 300 -200 150 L 50 50 1 1 P
X Pin_2 2 300 200 150 L 50 50 1 1 P
X Pin_3 3 -200 100 150 R 50 50 1 1 P
X Pin_4 4 300 100 150 L 50 50 1 1 P
X Pin_5 5 -200 0 150 R 50 50 1 1 P
X Pin_6 6 300 0 150 L 50 50 1 1 P
X Pin_7 7 -200 -100 150 R 50 50 1 1 P
X Pin_8 8 300 -100 150 L 50 50 1 1 P
X Pin_9 9 -200 -200 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Connector_Generic_Conn_02x25_Counter_Clockwise
#
DEF Connector_Generic_Conn_02x25_Counter_Clockwise J 0 40 Y N 1 F N
F0 "J" 50 1300 50 H V C CNN
F1 "Connector_Generic_Conn_02x25_Counter_Clockwise" 50 -1300 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_2x??_*
$ENDFPLIST
DRAW
S -50 -1195 0 -1205 1 1 6 N
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S -50 -995 0 -1005 1 1 6 N
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S -50 5 0 -5 1 1 6 N
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S -50 305 0 295 1 1 6 N
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S -50 1250 150 -1250 1 1 10 f
S 150 -1195 100 -1205 1 1 6 N
S 150 -1095 100 -1105 1 1 6 N
S 150 -995 100 -1005 1 1 6 N
S 150 -895 100 -905 1 1 6 N
S 150 -795 100 -805 1 1 6 N
S 150 -695 100 -705 1 1 6 N
S 150 -595 100 -605 1 1 6 N
S 150 -495 100 -505 1 1 6 N
S 150 -395 100 -405 1 1 6 N
S 150 -295 100 -305 1 1 6 N
S 150 -195 100 -205 1 1 6 N
S 150 -95 100 -105 1 1 6 N
S 150 5 100 -5 1 1 6 N
S 150 105 100 95 1 1 6 N
S 150 205 100 195 1 1 6 N
S 150 305 100 295 1 1 6 N
S 150 405 100 395 1 1 6 N
S 150 505 100 495 1 1 6 N
S 150 605 100 595 1 1 6 N
S 150 705 100 695 1 1 6 N
S 150 805 100 795 1 1 6 N
S 150 905 100 895 1 1 6 N
S 150 1005 100 995 1 1 6 N
S 150 1105 100 1095 1 1 6 N
S 150 1205 100 1195 1 1 6 N
X Pin_1 1 -200 1200 150 R 50 50 1 1 P
X Pin_10 10 -200 300 150 R 50 50 1 1 P
X Pin_11 11 -200 200 150 R 50 50 1 1 P
X Pin_12 12 -200 100 150 R 50 50 1 1 P
X Pin_13 13 -200 0 150 R 50 50 1 1 P
X Pin_14 14 -200 -100 150 R 50 50 1 1 P
X Pin_15 15 -200 -200 150 R 50 50 1 1 P
X Pin_16 16 -200 -300 150 R 50 50 1 1 P
X Pin_17 17 -200 -400 150 R 50 50 1 1 P
X Pin_18 18 -200 -500 150 R 50 50 1 1 P
X Pin_19 19 -200 -600 150 R 50 50 1 1 P
X Pin_2 2 -200 1100 150 R 50 50 1 1 P
X Pin_20 20 -200 -700 150 R 50 50 1 1 P
X Pin_21 21 -200 -800 150 R 50 50 1 1 P
X Pin_22 22 -200 -900 150 R 50 50 1 1 P
X Pin_23 23 -200 -1000 150 R 50 50 1 1 P
X Pin_24 24 -200 -1100 150 R 50 50 1 1 P
X Pin_25 25 -200 -1200 150 R 50 50 1 1 P
X Pin_26 26 300 -1200 150 L 50 50 1 1 P
X Pin_27 27 300 -1100 150 L 50 50 1 1 P
X Pin_28 28 300 -1000 150 L 50 50 1 1 P
X Pin_29 29 300 -900 150 L 50 50 1 1 P
X Pin_3 3 -200 1000 150 R 50 50 1 1 P
X Pin_30 30 300 -800 150 L 50 50 1 1 P
X Pin_31 31 300 -700 150 L 50 50 1 1 P
X Pin_32 32 300 -600 150 L 50 50 1 1 P
X Pin_33 33 300 -500 150 L 50 50 1 1 P
X Pin_34 34 300 -400 150 L 50 50 1 1 P
X Pin_35 35 300 -300 150 L 50 50 1 1 P
X Pin_36 36 300 -200 150 L 50 50 1 1 P
X Pin_37 37 300 -100 150 L 50 50 1 1 P
X Pin_38 38 300 0 150 L 50 50 1 1 P
X Pin_39 39 300 100 150 L 50 50 1 1 P
X Pin_4 4 -200 900 150 R 50 50 1 1 P
X Pin_40 40 300 200 150 L 50 50 1 1 P
X Pin_41 41 300 300 150 L 50 50 1 1 P
X Pin_42 42 300 400 150 L 50 50 1 1 P
X Pin_43 43 300 500 150 L 50 50 1 1 P
X Pin_44 44 300 600 150 L 50 50 1 1 P
X Pin_45 45 300 700 150 L 50 50 1 1 P
X Pin_46 46 300 800 150 L 50 50 1 1 P
X Pin_47 47 300 900 150 L 50 50 1 1 P
X Pin_48 48 300 1000 150 L 50 50 1 1 P
X Pin_49 49 300 1100 150 L 50 50 1 1 P
X Pin_5 5 -200 800 150 R 50 50 1 1 P
X Pin_50 50 300 1200 150 L 50 50 1 1 P
X Pin_6 6 -200 700 150 R 50 50 1 1 P
X Pin_7 7 -200 600 150 R 50 50 1 1 P
X Pin_8 8 -200 500 150 R 50 50 1 1 P
X Pin_9 9 -200 400 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_C_Small
#
DEF Device_C_Small C 0 10 N N 1 F N
F0 "C" 10 70 50 H V L CNN
F1 "Device_C_Small" 10 -80 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
C_*
$ENDFPLIST
DRAW
P 2 0 1 13 -60 -20 60 -20 N
P 2 0 1 12 -60 20 60 20 N
X ~ 1 0 100 80 D 50 50 1 1 P
X ~ 2 0 -100 80 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R_Pack04
#
DEF Device_R_Pack04 RN 0 0 Y N 1 F N
F0 "RN" -300 0 50 V V C CNN
F1 "Device_R_Pack04" 200 0 50 V V C CNN
F2 "" 275 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
DIP*
SOIC*
$ENDFPLIST
DRAW
S -250 -95 150 95 0 1 10 f
S -225 75 -175 -75 0 1 10 N
S -125 75 -75 -75 0 1 10 N
S -25 75 25 -75 0 1 10 N
S 75 75 125 -75 0 1 10 N
P 2 0 1 0 -200 -100 -200 -75 N
P 2 0 1 0 -200 75 -200 100 N
P 2 0 1 0 -100 -100 -100 -75 N
P 2 0 1 0 -100 75 -100 100 N
P 2 0 1 0 0 -100 0 -75 N
P 2 0 1 0 0 75 0 100 N
P 2 0 1 0 100 -100 100 -75 N
P 2 0 1 0 100 75 100 100 N
X R1.1 1 -200 -200 100 U 50 50 1 1 P
X R2.1 2 -100 -200 100 U 50 50 1 1 P
X R3.1 3 0 -200 100 U 50 50 1 1 P
X R4.1 4 100 -200 100 U 50 50 1 1 P
X R4.2 5 100 200 100 D 50 50 1 1 P
X R3.2 6 0 200 100 D 50 50 1 1 P
X R2.2 7 -100 200 100 D 50 50 1 1 P
X R1.2 8 -200 200 100 D 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R_Small
#
DEF Device_R_Small R 0 10 N N 1 F N
F0 "R" 30 20 50 H V L CNN
F1 "Device_R_Small" 30 -40 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
$ENDFPLIST
DRAW
S -30 70 30 -70 0 1 8 N
X ~ 1 0 100 30 D 50 50 1 1 P
X ~ 2 0 -100 30 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# GW_Logic_741G125GW
#
DEF GW_Logic_741G125GW U 0 40 Y Y 1 F N
F0 "U" 0 250 50 H V C CNN
F1 "GW_Logic_741G125GW" 0 -250 50 H V C CNN
F2 "stdpads:SOT-353" 0 -300 50 H I C TNN
F3 "" 0 -200 60 H I C CNN
DRAW
S 200 -200 -200 200 0 1 10 f
X ~OE~ 1 -400 100 200 R 50 50 1 1 I
X A 2 -400 0 200 R 50 50 1 1 I
X GND 3 -400 -100 200 R 50 50 1 1 W
X Y 4 400 -100 200 L 50 50 1 1 O
X Vcc 5 400 100 200 L 50 50 1 1 W
ENDDRAW
ENDDEF
#
# GW_Logic_74245
#
DEF GW_Logic_74245 U 0 40 Y Y 1 F N
F0 "U" 0 600 50 H V C CNN
F1 "GW_Logic_74245" 0 -600 50 H V C CNN
F2 "" 0 -650 50 H I C TNN
F3 "" 0 100 60 H I C CNN
DRAW
S -200 550 200 -550 0 1 10 f
X AtoB 1 -400 450 200 R 50 50 1 1 I
X GND 10 -400 -450 200 R 50 50 1 1 W
X B7 11 400 -450 200 L 50 50 1 1 B
X B6 12 400 -350 200 L 50 50 1 1 B
X B5 13 400 -250 200 L 50 50 1 1 B
X B4 14 400 -150 200 L 50 50 1 1 B
X B3 15 400 -50 200 L 50 50 1 1 B
X B2 16 400 50 200 L 50 50 1 1 B
X B1 17 400 150 200 L 50 50 1 1 B
X B0 18 400 250 200 L 50 50 1 1 B
X ~OE~ 19 400 350 200 L 50 50 1 1 I
X A0 2 -400 350 200 R 50 50 1 1 B
X Vcc 20 400 450 200 L 50 50 1 1 W
X A1 3 -400 250 200 R 50 50 1 1 B
X A2 4 -400 150 200 R 50 50 1 1 B
X A3 5 -400 50 200 R 50 50 1 1 B
X A4 6 -400 -50 200 R 50 50 1 1 B
X A5 7 -400 -150 200 R 50 50 1 1 B
X A6 8 -400 -250 200 R 50 50 1 1 B
X A7 9 -400 -350 200 R 50 50 1 1 B
ENDDRAW
ENDDEF
#
# GW_Logic_Oscillator_4P
#
DEF GW_Logic_Oscillator_4P U 0 40 Y Y 1 F N
F0 "U" 0 250 50 H V C CNN
F1 "GW_Logic_Oscillator_4P" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
S -250 200 250 -100 0 1 10 f
X EN 1 -350 100 100 R 50 50 1 1 I
X GND 2 -350 0 100 R 50 50 1 1 W
X Output 3 350 0 100 L 50 50 1 1 O
X Vdd 4 350 100 100 L 50 50 1 1 W
ENDDRAW
ENDDEF
#
# GW_PLD_EPM240T100
#
DEF GW_PLD_EPM240T100 U 0 40 Y Y 1 F N
F0 "U" 0 50 50 H V C CNN
F1 "GW_PLD_EPM240T100" 0 -50 50 H V C CNN
F2 "stdpads:TQFP-100_14x14mm_P0.5mm" 0 -100 20 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
*QFP*P0.5mm*
$ENDFPLIST
DRAW
S -800 2200 800 -2200 1 1 10 f
X IO2_1 1 1000 2100 200 L 50 50 1 1 B
X GNDIO 10 -200 -2400 200 U 50 50 1 1 W
X IO2_100 100 1000 -2000 200 L 50 50 1 1 B
X GNDINT 11 -400 -2400 200 U 50 50 1 1 W
X IO1_12/GCLK0 12 -1000 1400 200 R 50 50 1 1 B C
X VCCINT 13 -400 2400 200 D 50 50 1 1 W
X IO1_14/GCLK1 14 -1000 1300 200 R 50 50 1 1 B C
X IO1_15 15 -1000 1200 200 R 50 50 1 1 B
X IO1_16 16 -1000 1100 200 R 50 50 1 1 B
X IO1_17 17 -1000 1000 200 R 50 50 1 1 B
X IO1_18 18 -1000 900 200 R 50 50 1 1 B
X IO1_19 19 -1000 800 200 R 50 50 1 1 B
X IO1_2 2 -1000 2100 200 R 50 50 1 1 B
X IO1_20 20 -1000 700 200 R 50 50 1 1 B
X IO1_21 21 -1000 600 200 R 50 50 1 1 B
X TMS 22 -1000 -1700 200 R 50 50 1 1 I
X TDI 23 -1000 -1800 200 R 50 50 1 1 I
X TCK 24 -1000 -1900 200 R 50 50 1 1 I C
X TDO 25 -1000 -2000 200 R 50 50 1 1 O
X IO1_26 26 -1000 500 200 R 50 50 1 1 B
X IO1_27 27 -1000 400 200 R 50 50 1 1 B
X IO1_28 28 -1000 300 200 R 50 50 1 1 B
X IO1_29 29 -1000 200 200 R 50 50 1 1 B
X IO1_3 3 -1000 2000 200 R 50 50 1 1 B
X IO1_30 30 -1000 100 200 R 50 50 1 1 B
X VCCIO1 31 -100 2400 200 D 50 50 1 1 W
X GNDIO 32 -100 -2400 200 U 50 50 1 1 W
X IO1_33 33 -1000 0 200 R 50 50 1 1 B
X IO1_34 34 -1000 -100 200 R 50 50 1 1 B
X IO1_35 35 -1000 -200 200 R 50 50 1 1 B
X IO1_36 36 -1000 -300 200 R 50 50 1 1 B
X IO1_37 37 -1000 -400 200 R 50 50 1 1 B
X IO1_38 38 -1000 -500 200 R 50 50 1 1 B
X IO1_39 39 -1000 -600 200 R 50 50 1 1 B
X IO1_4 4 -1000 1900 200 R 50 50 1 1 B
X IO1_40 40 -1000 -700 200 R 50 50 1 1 B
X IO1_41 41 -1000 -800 200 R 50 50 1 1 B
X IO1_42 42 -1000 -900 200 R 50 50 1 1 B
X IO1_43/DEV_OE 43 -1000 -1000 200 R 50 50 1 1 B
X IO1_44/DEV_CLRn 44 -1000 -1100 200 R 50 50 1 1 B
X VCCIO1 45 0 2400 200 D 50 50 1 1 W
X GNDIO 46 0 -2400 200 U 50 50 1 1 W
X IO1_47 47 -1000 -1200 200 R 50 50 1 1 B
X IO1_48 48 -1000 -1300 200 R 50 50 1 1 B
X IO1_49 49 -1000 -1400 200 R 50 50 1 1 B
X IO1_5 5 -1000 1800 200 R 50 50 1 1 B
X IO1_50 50 -1000 -1500 200 R 50 50 1 1 B
X IO1_51 51 -1000 -1600 200 R 50 50 1 1 B
X IO2_52 52 1000 2000 200 L 50 50 1 1 B
X IO2_53 53 1000 1900 200 L 50 50 1 1 B
X IO2_54 54 1000 1800 200 L 50 50 1 1 B
X IO2_55 55 1000 1700 200 L 50 50 1 1 B
X IO2_56 56 1000 1600 200 L 50 50 1 1 B
X IO2_57 57 1000 1500 200 L 50 50 1 1 B
X IO2_58 58 1000 1400 200 L 50 50 1 1 B
X VCCIO2 59 100 2400 200 D 50 50 1 1 W
X IO1_6 6 -1000 1700 200 R 50 50 1 1 B
X GNDIO 60 100 -2400 200 U 50 50 1 1 W
X IO2_61 61 1000 1300 200 L 50 50 1 1 B
X IO2_62/GCLK2 62 1000 1200 200 L 50 50 1 1 B C
X VCCINT 63 -300 2400 200 D 50 50 1 1 W
X IO2_64/GCLK3 64 1000 1100 200 L 50 50 1 1 B C
X GNDINT 65 -300 -2400 200 U 50 50 1 1 W
X IO2_66 66 1000 1000 200 L 50 50 1 1 B
X IO2_67 67 1000 900 200 L 50 50 1 1 B
X IO2_68 68 1000 800 200 L 50 50 1 1 B
X IO2_69 69 1000 700 200 L 50 50 1 1 B
X IO1_7 7 -1000 1600 200 R 50 50 1 1 B
X IO2_70 70 1000 600 200 L 50 50 1 1 B
X IO2_71 71 1000 500 200 L 50 50 1 1 B
X IO2_72 72 1000 400 200 L 50 50 1 1 B
X IO2_73 73 1000 300 200 L 50 50 1 1 B
X IO2_74 74 1000 200 200 L 50 50 1 1 B
X IO2_75 75 1000 100 200 L 50 50 1 1 B
X IO2_76 76 1000 0 200 L 50 50 1 1 B
X IO2_77 77 1000 -100 200 L 50 50 1 1 B
X IO2_78 78 1000 -200 200 L 50 50 1 1 B
X GNDIO 79 200 -2400 200 U 50 50 1 1 W
X IO1_8 8 -1000 1500 200 R 50 50 1 1 B
X VCCIO2 80 200 2400 200 D 50 50 1 1 W
X IO2_81 81 1000 -300 200 L 50 50 1 1 B
X IO2_82 82 1000 -400 200 L 50 50 1 1 B
X IO2_83 83 1000 -500 200 L 50 50 1 1 B
X IO2_84 84 1000 -600 200 L 50 50 1 1 B
X IO2_85 85 1000 -700 200 L 50 50 1 1 B
X IO2_86 86 1000 -800 200 L 50 50 1 1 B
X IO2_87 87 1000 -900 200 L 50 50 1 1 B
X IO2_88 88 1000 -1000 200 L 50 50 1 1 B
X IO2_89 89 1000 -1100 200 L 50 50 1 1 B
X VCCIO1 9 -200 2400 200 D 50 50 1 1 W
X IO2_90 90 1000 -1200 200 L 50 50 1 1 B
X IO2_91 91 1000 -1300 200 L 50 50 1 1 B
X IO2_92 92 1000 -1400 200 L 50 50 1 1 B
X GNDIO 93 300 -2400 200 U 50 50 1 1 W
X VCCIO2 94 300 2400 200 D 50 50 1 1 W
X IO2_95 95 1000 -1500 200 L 50 50 1 1 B
X IO2_96 96 1000 -1600 200 L 50 50 1 1 B
X IO2_97 97 1000 -1700 200 L 50 50 1 1 B
X IO2_98 98 1000 -1800 200 L 50 50 1 1 B
X IO2_99 99 1000 -1900 200 L 50 50 1 1 B
ENDDRAW
ENDDEF
#
# GW_Power_AP2125
#
DEF GW_Power_AP2125 U 0 40 Y Y 1 F N
F0 "U" 0 250 50 H V C CNN
F1 "GW_Power_AP2125" 0 -250 50 H V C CNN
F2 "stdpads:SOT-23" 0 -300 50 H I C TNN
F3 "" 0 -100 60 H I C CNN
DRAW
S -250 200 250 -200 0 1 10 f
X GND 1 -450 -100 200 R 50 50 1 1 W
X Vout 2 450 100 200 L 50 50 1 1 w
X Vin 3 -450 100 200 R 50 50 1 1 W
ENDDRAW
ENDDEF
#
# GW_RAM_SDRAM-16Mx16-TSOP2-54
#
DEF GW_RAM_SDRAM-16Mx16-TSOP2-54 U 0 40 Y Y 1 F N
F0 "U" 0 1150 50 H V C CNN
F1 "GW_RAM_SDRAM-16Mx16-TSOP2-54" 0 0 50 V V C CNN
F2 "stdpads:Winbond_TSOPII-54" 0 -1650 50 H I C CIN
F3 "" 0 -250 50 H I C CNN
DRAW
S -300 1100 300 -1400 0 1 10 f
X VDD 1 -500 1000 200 R 50 50 1 1 W
X DQ5 10 500 500 200 L 50 50 1 1 B
X DQ6 11 500 400 200 L 50 50 1 1 B
X VSSQ 12 -500 -1300 200 R 50 50 1 1 W N
X DQ7 13 500 300 200 L 50 50 1 1 B
X VDD 14 -500 1000 200 R 50 50 1 1 W N
X DQML 15 500 -600 200 L 50 50 1 1 I
X ~WE~ 16 500 -1100 200 L 50 50 1 1 I
X ~CAS~ 17 500 -1200 200 L 50 50 1 1 I
X ~RAS~ 18 500 -1300 200 L 50 50 1 1 I
X ~CS~ 19 500 -1000 200 L 50 50 1 1 I
X DQ0 2 500 1000 200 L 50 50 1 1 B
X BA0 20 -500 -600 200 R 50 50 1 1 I
X BA1 21 -500 -700 200 R 50 50 1 1 I
X A10 22 -500 -300 200 R 50 50 1 1 I
X A0 23 -500 700 200 R 50 50 1 1 I
X A1 24 -500 600 200 R 50 50 1 1 I
X A2 25 -500 500 200 R 50 50 1 1 I
X A3 26 -500 400 200 R 50 50 1 1 I
X VDD 27 -500 1000 200 R 50 50 1 1 W N
X VSS 28 -500 -1200 200 R 50 50 1 1 W
X A4 29 -500 300 200 R 50 50 1 1 I
X VDDQ 3 -500 900 200 R 50 50 1 1 W
X A5 30 -500 200 200 R 50 50 1 1 I
X A6 31 -500 100 200 R 50 50 1 1 I
X A7 32 -500 0 200 R 50 50 1 1 I
X A8 33 -500 -100 200 R 50 50 1 1 I
X A9 34 -500 -200 200 R 50 50 1 1 I
X A11 35 -500 -400 200 R 50 50 1 1 I
X A12 36 -500 -500 200 R 50 50 1 1 I
X CKE 37 -500 -900 200 R 50 50 1 1 I
X CLK 38 -500 -1000 200 R 50 50 1 1 I
X DQMH 39 500 -700 200 L 50 50 1 1 I
X DQ1 4 500 900 200 L 50 50 1 1 B
X VSS 41 -500 -1200 200 R 50 50 1 1 W N
X DQ8 42 500 200 200 L 50 50 1 1 B
X VDDQ 43 -500 900 200 R 50 50 1 1 W N
X DQ9 44 500 100 200 L 50 50 1 1 B
X DQ10 45 500 0 200 L 50 50 1 1 B
X VSSQ 46 -500 -1300 200 R 50 50 1 1 W N
X DQ11 47 500 -100 200 L 50 50 1 1 B
X DQ12 48 500 -200 200 L 50 50 1 1 B
X VDDQ 49 -500 900 200 R 50 50 1 1 W N
X DQ2 5 500 800 200 L 50 50 1 1 B
X DQ13 50 500 -300 200 L 50 50 1 1 B
X DQ14 51 500 -400 200 L 50 50 1 1 B
X VSSQ 52 -500 -1300 200 R 50 50 1 1 W N
X DQ15 53 500 -500 200 L 50 50 1 1 B
X VSS 54 -500 -1200 200 R 50 50 1 1 W N
X VSSQ 6 -500 -1300 200 R 50 50 1 1 W
X DQ3 7 500 700 200 L 50 50 1 1 B
X DQ4 8 500 600 200 L 50 50 1 1 B
X VDDQ 9 -500 900 200 R 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# GW_RAM_SPIFlash-SO-8
#
DEF GW_RAM_SPIFlash-SO-8 U 0 40 Y Y 1 F N
F0 "U" 0 350 50 H V C CNN
F1 "GW_RAM_SPIFlash-SO-8" 0 -250 50 H V C CNN
F2 "stdpads:Hybrid_SPIFlash_SOIC-8_SOIC-16" 0 -300 50 H I C TNN
F3 "" 0 0 50 H I C TNN
DRAW
S -350 300 350 -200 0 1 10 f
X ~CS~ 1 -550 200 200 R 50 50 1 1 I
X DO/IO1 2 -550 100 200 R 50 50 1 1 B
X ~WP~/IO2 3 -550 0 200 R 50 50 1 1 B
X GND 4 -550 -100 200 R 50 50 1 1 W
X DI/IO0 5 550 -100 200 L 50 50 1 1 B
X CLK 6 550 0 200 L 50 50 1 1 I
X ~HLD~/IO3 7 550 100 200 L 50 50 1 1 B
X Vcc 8 550 200 200 L 50 50 1 1 W
ENDDRAW
ENDDEF
#
# Mechanical_Fiducial
#
DEF Mechanical_Fiducial FID 0 20 Y Y 1 F N
F0 "FID" 0 200 50 H V C CNN
F1 "Mechanical_Fiducial" 0 125 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Fiducial*
$ENDFPLIST
DRAW
C 0 0 50 0 1 20 f
ENDDRAW
ENDDEF
#
# Mechanical_MountingHole
#
DEF Mechanical_MountingHole H 0 40 Y Y 1 F N
F0 "H" 0 200 50 H V C CNN
F1 "Mechanical_MountingHole" 0 125 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
MountingHole*
$ENDFPLIST
DRAW
C 0 0 50 0 1 50 N
ENDDRAW
ENDDEF
#
# Mechanical_MountingHole_Pad
#
DEF Mechanical_MountingHole_Pad H 0 40 N N 1 F N
F0 "H" 0 250 50 H V C CNN
F1 "Mechanical_MountingHole_Pad" 0 175 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
MountingHole*Pad*
$ENDFPLIST
DRAW
C 0 50 50 0 1 50 N
X 1 1 0 -100 100 U 50 50 1 1 I
ENDDRAW
ENDDEF
#
# Switch_SW_DIP_x02
#
DEF Switch_SW_DIP_x02 SW 0 0 Y N 1 F N
F0 "SW" 0 250 50 H V C CNN
F1 "Switch_SW_DIP_x02" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
SW?DIP?x2*
$ENDFPLIST
DRAW
C -80 0 20 0 0 0 N
C -80 100 20 0 0 0 N
C 80 0 20 0 0 0 N
C 80 100 20 0 0 0 N
S -150 200 150 -100 0 1 10 f
P 2 0 0 0 -60 5 93 46 N
P 2 0 0 0 -60 105 93 146 N
X ~ 1 -300 100 200 R 50 50 1 1 P
X ~ 2 -300 0 200 R 50 50 1 1 P
X ~ 3 300 0 200 L 50 50 1 1 P
X ~ 4 300 100 200 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# power_+12V
#
DEF power_+12V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+12V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +12V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_+3V3
#
DEF power_+3V3 #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+3V3" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS +3.3V
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +3V3 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_+5V
#
DEF power_+5V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+5V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +5V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_-12V
#
DEF power_-12V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 100 50 H I C CNN
F1 "power_-12V" 0 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 50 30 50 0 100 -30 50 0 50 F
X -12V 1 0 0 0 U 50 50 0 0 W N
ENDDRAW
ENDDEF
#
# power_-5V
#
DEF power_-5V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 100 50 H I C CNN
F1 "power_-5V" 0 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 50 30 50 0 100 -30 50 0 50 F
X -5V 1 0 0 0 U 50 50 0 0 W N
ENDDRAW
ENDDEF
#
# power_GND
#
DEF power_GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library

95936
Hardware/MAX/GR8RAM.kicad_pcb Normal file
View File

File diff suppressed because it is too large Load Diff

127
GR8RAM.kicad_pro → Hardware/MAX/GR8RAM.kicad_pro
View File

@ -1,9 +1,10 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.15,
"copper_line_width": 0.15,
"copper_line_width": 0.15239999999999998,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
@ -48,7 +49,13 @@
"min_clearance": 0.15239999999999998
}
},
"diff_pair_dimensions": [],
"diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [],
"meta": {
"filename": "board_design_settings.json",
@ -57,32 +64,43 @@
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"courtyards_overlap": "error",
"copper_sliver": "error",
"courtyards_overlap": "warning",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"duplicate_footprints": "error",
"extra_footprint": "error",
"footprint": "error",
"footprint_type_mismatch": "error",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "ignore",
"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"missing_footprint": "error",
"net_conflict": "error",
"npth_inside_courtyard": "ignore",
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"solder_mask_bridge": "ignore",
"starved_thermal": "error",
"text_height": "warning",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
@ -91,7 +109,6 @@
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zone_has_empty_net": "error",
"zones_intersect": "error"
},
"rule_severitieslegacy_courtyards_overlap": true,
@ -100,21 +117,67 @@
"allow_blind_buried_vias": false,
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.0,
"min_copper_edge_clearance": 0.075,
"min_clearance": 0.15,
"min_connection": 0.12,
"min_copper_edge_clearance": 0.4064,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
"min_hole_to_hole": 0.254,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_through_hole_diameter": 0.19999999999999998,
"min_text_height": 0.7999999999999999,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.15,
"min_via_annular_width": 0.049999999999999996,
"min_via_annular_width": 0.09999999999999999,
"min_via_diameter": 0.5,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"teardrop_options": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 5,
"td_on_pad_in_zone": false,
"td_onpadsmd": true,
"td_onroundshapesonly": false,
"td_ontrackend": false,
"td_onviapad": true
}
],
"teardrop_parameters": [
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_round_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_rect_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_track_end",
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [
0.0,
0.15,
0.2,
0.25,
0.3,
@ -123,7 +186,6 @@
0.45,
0.5,
0.6,
0.762,
0.8,
1.0,
1.27,
@ -134,6 +196,10 @@
"diameter": 0.0,
"drill": 0.0
},
{
"diameter": 0.5,
"drill": 0.3
},
{
"diameter": 0.6,
"drill": 0.3
@ -154,7 +220,8 @@
"zones_allow_external_fillets": false,
"zones_use_no_outline": true
},
"layer_presets": []
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
@ -338,18 +405,23 @@
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"conflicting_netclasses": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"endpoint_off_grid": "warning",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"missing_bidi_pin": "warning",
"missing_input_pin": "warning",
"missing_power_pin": "error",
"missing_unit": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
@ -359,6 +431,7 @@
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"simulation_model_issue": "ignore",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
@ -376,7 +449,7 @@
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"bus_width": 12,
"clearance": 0.15,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
@ -389,14 +462,16 @@
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.15,
"via_diameter": 0.5,
"via_drill": 0.2,
"wire_width": 6.0
"via_drill": 0.3,
"wire_width": 6
}
],
"meta": {
"version": 2
"version": 3
},
"net_colors": null
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
},
"pcbnew": {
"last_paths": {
@ -412,6 +487,8 @@
"schematic": {
"annotate_start_num": 0,
"drawing": {
"dashed_lines_dash_length_ratio": 12.0,
"dashed_lines_gap_length_ratio": 3.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"field_names": [],
@ -443,7 +520,11 @@
"page_layout_descr_file": "",
"plot_directory": "",
"spice_adjust_passive_values": false,
"spice_current_sheet_as_root": false,
"spice_external_command": "spice \"%I\"",
"spice_model_current_sheet_as_root": true,
"spice_save_all_currents": false,
"spice_save_all_voltages": false,
"subpart_first_id": 65,
"subpart_id_separator": 0
},
@ -451,10 +532,6 @@
[
"a29f8df0-3fae-4edf-8d9c-bd5a875b13e3",
""
],
[
"00000000-0000-0000-0000-00005d4d21a0",
"Docs"
]
],
"text_variables": {}

7467
GR8RAM.kicad_sch → Hardware/MAX/GR8RAM.kicad_sch
View File

File diff suppressed because it is too large Load Diff

4
Hardware/MAX/fp-lib-table Normal file
View File

@ -0,0 +1,4 @@
(fp_lib_table
(version 7)
(lib (name "stdpads")(type "KiCad")(uri "$(KIPRJMOD)/../../../stdpads.pretty")(options "")(descr ""))
)

7
Hardware/MAX/sym-lib-table Normal file
View File

@ -0,0 +1,7 @@
(sym_lib_table
(version 7)
(lib (name "GW_RAM")(type "KiCad")(uri "${KIPRJMOD}/../../../GW_Parts/GW_RAM.kicad_sym")(options "")(descr ""))
(lib (name "GW_PLD")(type "KiCad")(uri "${KIPRJMOD}/../../../GW_Parts/GW_PLD.kicad_sym")(options "")(descr ""))
(lib (name "GW_Logic")(type "KiCad")(uri "${KIPRJMOD}/../../../GW_Parts/GW_Logic.kicad_sym")(options "")(descr ""))
(lib (name "GW_Power")(type "KiCad")(uri "${KIPRJMOD}/../../../GW_Parts/GW_Power.kicad_sym")(options "")(descr ""))
)

67
Makefile Normal file
View File

@ -0,0 +1,67 @@
KICAD = /Applications/KiCad/KiCad.app/Contents/MacOS/kicad-cli
LAYERS = F.Cu,In1.Cu,In2.Cu,B.Cu,F.Paste,F.SilkS,B.SilkS,F.Mask,B.Mask,Edge.Cuts
CHIPTYPE = $(shell echo $@ | cut -f2 -d"/")
PYTHON = python3
BOM_SCRIPT = ../GW_KiCADBuild/export_bom.py
F_PCB = $@/../GR8RAM.kicad_pcb
F_SCH = $@/../GR8RAM.kicad_sch
F_NETLIST = $@/GR8RAM-NET.xml
F_BOM = $@/GR8RAM-BOM.csv
F_POS_N = $@/GR8RAM-top-pos
F_POS = $(F_POS_N).csv
F_POS_VCORE = $(F_POS_N).VCORE.csv
F_POS_JUMPER = $(F_POS_N).JUMPER.csv
F_ZIP = $@/GR8RAM.4205B.$(CHIPTYPE)-gerber.zip
F_SCHPDF = $@/GR8RAM.4205B.$(CHIPTYPE)-Schematic.pdf
F_PCBPDF = $@/GR8RAM.4205B.$(CHIPTYPE)-Placement.pdf
OPT_GERBER = -l $(LAYERS) --subtract-soldermask --no-netlist --no-x2
CMD_GERBER = pcb export gerbers $(OPT_GERBER) -o $@/ $(F_PCB)
CMD_DRILL = pcb export drill -o $@/ $(F_PCB)
CMD_NETLIST = sch export netlist --format kicadxml -o $(F_NETLIST) $(F_SCH)
OPT_POS = --smd-only --units mm --side front --format csv
CMD_POS = pcb export pos $(OPT_POS) -o $(F_POS) $(F_PCB)
CMD_SCHPDF = sch export pdf --black-and-white --no-background-color -o $(F_SCHPDF) $(F_SCH)
CMD_PCBPDF = pcb export pdf --black-and-white -l F.Fab,Edge.Cuts -o $(F_PCBPDF) $(F_PCB)
.PHONY: all clean \
Hardware/MAX Hardware/MAX/gerber Hardware/MAX/Documentation \
Hardware/LCMXO2 Hardware/LCMXO2/gerber Hardware/LCMXO2/Documentation
all: Hardware/MAX Hardware/LCMXO2
clean:
rm -fr Hardware/MAX/gerber/ Hardware/MAX/Documentation/
rm -fr Hardware/LCMXO2/gerber/ Hardware/LCMXO2/Documentation/
Hardware/MAX: Hardware/MAX/gerber Hardware/MAX/Documentation
Hardware/LCMXO2: Hardware/LCMXO2/gerber Hardware/LCMXO2/Documentation
Hardware/MAX/gerber Hardware/LCMXO2/gerber:
mkdir -p $@
$(KICAD) $(CMD_GERBER)
$(KICAD) $(CMD_DRILL)
$(KICAD) $(CMD_POS)
$(KICAD) $(CMD_NETLIST)
sed -i '' 's/PosX/MidX/g' $(F_POS)
sed -i '' 's/PosY/MidY/g' $(F_POS)
sed -i '' 's/Rot/Rotation/g' $(F_POS)
$(PYTHON) $(BOM_SCRIPT) $(F_NETLIST) $(F_BOM)
cp $(F_POS) $(F_POS_VCORE)
cp $(F_POS) $(F_POS_JUMPER)
sed -i '' '/"R1"/d' $(F_POS_VCORE)
sed -i '' '/"U10"/d' $(F_POS_JUMPER)
rm -f $(F_ZIP)
zip -r $(F_ZIP) $@/
Hardware/MAX/Documentation Hardware/LCMXO2/Documentation:
mkdir -p $@
$(KICAD) $(CMD_SCHPDF)
$(KICAD) $(CMD_PCBPDF)

736
cpld/GR8RAM.v
View File

@ -1,23 +1,46 @@
module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
INTin, INTout, DMAin, DMAout,
nNMIout, nIRQout, nRDYout, nINHout, RWout, nDMAout,
RA, nWE, RD, RAdir, RDdir, nIOSEL, nDEVSEL, nIOSTRB,
SBA, SA, nRCS, nRAS, nCAS, nSWE, DQML, DQMH, RCKE, SD,
nFCS, FCK, MISO, MOSI);
module GR8RAM2(
/* Clock signals */
input C25M, PHI0;
reg PHI0r1, PHI0r2;
always @(posedge C25M) begin PHI0r1 <= PHI0; PHI0r2 <= PHI0r1; end
input C25M,
input PHI0,
input nRESin,
output reg nRESout,
input [1:0] SetFW,
output reg nIRQout,
input [15:0] BA,
input nWE,
inout [7:0] BD,
output BDdir,
/* Card select signals */
input nIOSEL,
input nDEVSEL,
input nIOSTRB,
/* SDRAM bus */
output reg [1:0] RBA,
output reg [12:0] RA,
output nRCS,
output reg nRAS,
output reg nCAS,
output reg nRWE,
output reg DQML,
output reg DQMH,
output reg RCKE,
output reg [7:0] RD,
/* SPI NOR flash */
output reg nFCS,
output reg FCK,
inout MISO,
inout MOSI);
/* PHI0 synchronization signals */
reg PHI0r0, PHI0r1;
always @(negedge C25M) begin PHI0r0 <= PHI0; end
always @(posedge C25M) begin PHI0r1 <= PHI0r0; end
/* Reset filter */
input nRES;
reg [3:0] nRESf = 0;
reg nRESr = 0;
always @(posedge C25M) begin
nRESf[3:0] <= { nRESf[2:0], nRES };
nRESr <= nRESf[3] || nRESf[2] || nRESf[1] || nRESf[0];
end
/* Reset synchronization */
reg nRESr0, nRESr;
always @(negedge C25M) nRESr0 <= nRESin;
always @(posedge C25M) nRESr <= nRESr0;
wire RES = RES;
/* Firmware select */
input [1:0] SetFW;
@ -31,86 +54,91 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
end
wire [1:0] SetROM = ~SetFWr[1:0];
wire SetEN16MB = SetROM[1:0]==2'b11;
wire SetEN24bit = SetROM[1];
wire SetEN24b = SetROM[1];
/* State counter from PHI0 rising edge */
reg [3:0] PS = 0;
wire PSStart = PS==0 && PHI0r1 && !PHI0r2;
always @(posedge C25M) begin
if (PSStart) PS <= 1;
else if (PS==0) PS <= 0;
else PS <= PS+1;
end
/* Long state counter: counts from 0 to $3FFF */
reg [13:0] LS = 0;
always @(posedge C25M) begin if (PS==15) LS <= LS+1; end
/* Init state */
output reg nRESout = 0;
/* State counters */
reg [2:0] IS = 0;
reg [24:0] S = 0;
wire Ready = IS[2];
/* Reset output disable */
assign nRESout = Ready;
/* Init state counter control */
// IS 0 - wait and issue NOP CKE (ends at S[19:0]==20'hFFFFF)
// IS 1 - Load mode and AREF, issue SPI NOR read (ends at S[4:0]==5'h3F)
// IS 2 - Write driver (ends at S[16:0]==17'h1FFFF)
// IS 3 - Write image (ends at S[24:0]==25'h1FFFFFF)
// IS 7 - Operating mode
always @(posedge C25M) begin
if (IS==7) nRESout <= 1;
else if (PS==15) begin
if (LS==14'h1FCE) IS <= 1; // PC all + load mode
else if (LS==14'h1FCF) IS <= 4; // AREF pause, SPI select
else if (LS==14'h1FFA) IS <= 5; // SPI flash command
else if (LS==14'h1FFF) IS <= 6; // Flash load driver
else if (LS==14'h3FFF) IS <= 7; // Operating mode
case (IS[2:0]) begin
3'h0: if (S[19:0]== 20'hFFFFF) IS[2:0] <= 3'h1;
3'h1: if (S[19:0]== 5'h3F) IS[2:0] <= 3'h2;
3'h2: if (S[19:0]== 17'h1FFFF) IS[2:0] <= 3'h3;
3'h3: if (S[19:0]==25'h1FFFFFF) IS[2:0] <= 3'h7;
end
end
/* Apple IO area select signals */
input nIOSEL, nDEVSEL, nIOSTRB;
/* Apple address bus */
input [15:0] RA; input nWE;
reg [11:0] RAr; reg nWEr;
reg CXXXr;
always @(posedge PHI0) begin
CXXXr <= RA[15:12]==4'hC;
RAr[11:0] <= RA[11:0];
nWEr <= nWE;
end
/* Apple select signals */
wire ROMSpecRD = CXXXr && RAr[11:8]!=4'h0 && nWEr && ((RAr[11] && IOROMEN) || (!RAr[11]));
wire REGSpecSEL = CXXXr && RAr[11:8]==4'h0 && RAr[7] && REGEN;
wire BankSpecSEL = REGSpecSEL && RAr[3:0]==4'hF;
wire RAMRegSpecSEL = REGSpecSEL && RAr[3:0]==4'h3;
wire RAMSpecSEL = RAMRegSpecSEL && (!SetEN24bit || SetEN16MB || !Addr[23]);
wire AddrHSpecSEL = REGSpecSEL && RAr[3:0]==4'h2;
wire AddrMSpecSEL = REGSpecSEL && RAr[3:0]==4'h1;
wire AddrLSpecSEL = REGSpecSEL && RAr[3:0]==4'h0;
wire BankSEL = REGEN && !nDEVSEL && BankSpecSEL;
wire RAMRegSEL = !nDEVSEL && RAMRegSpecSEL;
wire RAMSEL = !nDEVSEL && RAMSpecSEL;
wire RAMWR = RAMSEL && !nWEr;
wire AddrHSEL = REGEN && !nDEVSEL && AddrHSpecSEL;
wire AddrMSEL = REGEN && !nDEVSEL && AddrMSpecSEL;
wire AddrLSEL = REGEN && !nDEVSEL && AddrLSpecSEL;
/* IOROMEN and REGEN control */
reg IOROMEN = 0;
reg REGEN = 0;
reg nIOSTRBr;
wire IOROMRES = RAr[10:0]==11'h7FF && !nIOSTRB && !nIOSTRBr;
always @(posedge C25M, negedge nRESr) begin
if (!nRESr) REGEN <= 0;
else if (PS==8 && !nIOSEL) REGEN <= 1;
end
/* RAM state counter control */
always @(posedge C25M) begin
nIOSTRBr <= nIOSTRB;
if (!nRESr) IOROMEN <= 0;
else if (PS==8 && IOROMRES) IOROMEN <= 0;
else if (PS==8 && !nIOSEL) IOROMEN <= 1;
if (IS[2:0]==3'h0 && S[19:0]== 20'hFFFFF ||
IS[2:0]==3'h1 && S[19:0]== 5'h3F ||
IS[2:0]==3'h2 && S[19:0]== 17'h1FFFF ||
IS[2:0]==3'h3 && S[19:0]==25'h1FFFFFF) S <= 0;
else if (Ready) begin
S[24:4] <= 0;
if (S[3:0]==0 && PHI0r1) S[2:0] <= 4'h1;
else if (S[3:0]!=0) S[3:0] <= S[3:0]+4'h1;
end else S[24:0] <= S[24:0]+25'h1;
end
/* Apple data bus */
inout [7:0] RD = RDdir ? 8'bZ : RDD[7:0];
reg [7:0] RDD;
output RDdir = !(PHI0r2 && nWE && PHI0 &&
(!nDEVSEL || !nIOSEL || (!nIOSTRB && IOROMEN && RA[10:0]!=11'h7FF)));
/* IOROMEN control */
reg IOROMEN = 0;
always @(posedge C25M) begin
if (RES) IOROMEN <= 0;
else if (S[2:0]==3'h2) begin
if (!nIOSTRB && BA[10:0]==11'h7FF) IOROMEN <= 0;
else if (!nIOSEL) IOROMEN <= 1;
end
end
/* RegEN control */
reg RegEN = 0;
always @(posedge C25M) begin
if (RES) RegEN <= 0;
else if (S[2:0]==3'h2 && !nIOSEL) RegEN <= 1;
end
/* ROM bank register */
reg Bank = 0;
always @(posedge C25M, negedge nRESr) begin
if (RES) Bank <= 0;
else if (S[2:0]==3'h4 && BankSEL && !nWEr) begin
Bank <= RD[0];
end
end
/* RAMROMCS command signal */
reg RAMROMCS;
always @(posedge C25M) begin
if (S[3:0]==4'h0) RAMROMCS <= !RES &&PHI0r1 && BA[15:12]==4'hC;
else if S[3:0]==4'h1) begin
RAMROMCS <= !RES && (
(!nIOSEL) ||
(!nIOSTRB && IOROMEN) ||
(!nDEVSEL && RegEN && A[3:0]==4'h3));
end else if (S[3:0]==4'h9) RAMROMCS <= !RES && RefC[2:0]==0;
end
/* Register select command signals */
reg RAMRegSEL;
reg AddrHWR, AddrMWR, AddrLWR;
always @(posedge C25M) begin
RAMRegSEL <= !RES && S[3:0]==4'h6 !nDEVSEL && BA[3:0]==4'h3;
AddrHWR <= !RES && S[3:0]==4'h6 !nDEVSEL && BA[3:0]==4'h2;
AddrMWR <= !RES && S[3:0]==4'h6 !nDEVSEL && BA[3:0]==4'h1;
AddrLWR <= !RES && S[3:0]==4'h6 !nDEVSEL && BA[3:0]==4'h0;
end
/* Slinky address registers */
reg [23:0] Addr = 0;
@ -118,16 +146,16 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
reg AddrIncM = 0;
reg AddrIncH = 0;
always @(posedge C25M, negedge nRESr) begin
if (!nRESr) begin
Addr[23:0] <= 24'h000000;
if (RES) begin
Addr[23:0] <= 0;
AddrIncL <= 0;
AddrIncM <= 0;
AddrIncH <= 0;
end else begin
if (PS==8 && RAMRegSEL) AddrIncL <= 1;
if (RAMRegSEL) AddrIncL <= 1;
else AddrIncL <= 0;
if (PS==8 && AddrLSEL && !nWEr) begin
if (AddrLWR) begin
Addr[7:0] <= RD[7:0];
AddrIncM <= Addr[7] && !RD[7];
end else if (AddrIncL) begin
@ -135,7 +163,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
AddrIncM <= Addr[7:0]==8'hFF;
end else AddrIncM <= 0;
if (PS==8 && AddrMSEL && !nWEr) begin
if (AddrMWR) begin
Addr[15:8] <= RD[7:0];
AddrIncH <= Addr[15] && !RD[7];
end else if (AddrIncM) begin
@ -143,7 +171,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
AddrIncH <= Addr[15:8]==8'hFF;
end else AddrIncH <= 0;
if (PS==8 && AddrHSEL && !nWEr) begin
if (AddrHWR) begin
Addr[23:16] <= RD[7:0];
end else if (AddrIncH) begin
Addr[23:16] <= Addr[23:16]+1;
@ -151,404 +179,142 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
end
end
/* ROM bank register */
reg Bank = 0;
always @(posedge C25M, negedge nRESr) begin
if (!nRESr) Bank <= 0;
else if (PS==8 && BankSEL && !nWEr) begin
Bank <= RD[0];
end
end
/* SPI flash control signals */
output nFCS = FCKOE ? !FCS : 1'bZ;
reg FCS = 0;
output FCK = FCKOE ? FCKout : 1'bZ;
reg FCKOE = 0;
reg FCKout = 0;
inout MOSI = MOSIOE ? MOSIout : 1'bZ;
reg MOSIOE = 0;
input MISO;
always @(posedge C25M) begin
case (PS[3:0])
0: begin // NOP CKE
FCKout <= 1'b1;
end 1: begin // ACT
FCKout <= !(IS==5 || IS==6);
end 2: begin // RD
FCKout <= 1'b1;
end 3: begin // NOP CKE
FCKout <= !(IS==5 || IS==6);
end 4: begin // NOP CKE
FCKout <= 1'b1;
end 5: begin // NOP CKE
FCKout <= !(IS==5 || IS==6);
end 6: begin // NOP CKE
FCKout <= 1'b1;
end 7: begin // NOP CKE
FCKout <= !(IS==5 || IS==6);
end 8: begin // WR AP
FCKout <= 1'b1;
end 9: begin // NOP CKE
FCKout <= !(IS==5);
end 10: begin // PC all
FCKout <= 1'b1;
end 11: begin // AREF
FCKout <= !(IS==5);
end 12: begin // NOP CKE
FCKout <= 1'b1;
end 13: begin // NOP CKE
FCKout <= !(IS==5);
end 14: begin // NOP CKE
FCKout <= 1'b1;
end 15: begin // NOP CKE
FCKout <= !(IS==5);
end
endcase
FCS <= IS==4 || IS==5 || IS==6;
MOSIOE <= IS==5;
FCKOE <= IS==1 || IS==4 || IS==5 || IS==6 || IS==7;
end
/* SPI flash MOSI control */
reg MOSIout = 0;
always @(posedge C25M) begin
case (PS[3:0])
1: begin
case (LS[2:0])
3'h3: MOSIout <= 1'b0; // Command bit 7
3'h4: MOSIout <= 1'b0; // Address bit 23
3'h5: MOSIout <= 1'b0; // Address bit 15
3'h6: MOSIout <= 1'b0; // Address bit 7
default MOSIout <= 1'b0;
endcase
end 3: begin
case (LS[2:0])
3'h3: MOSIout <= 1'b0; // Command bit 6
3'h4: MOSIout <= 1'b0; // Address bit 22
3'h5: MOSIout <= SetROM[1]; // Address bit 14
3'h6: MOSIout <= 1'b0; // Address bit 6
default MOSIout <= 1'b0;
endcase
end 5: begin
case (LS[2:0])
3'h3: MOSIout <= 1'b1; // Command bit 5
3'h4: MOSIout <= 1'b0; // Address bit 21
3'h5: MOSIout <= SetROM[0]; // Address bit 13
3'h6: MOSIout <= 1'b0; // Address bit 5
default MOSIout <= 1'b0;
endcase
end 7: begin
case (LS[2:0])
3'h3: MOSIout <= 1'b1; // Command bit 4
3'h4: MOSIout <= 1'b0; // Address bit 20
3'h5: MOSIout <= 1'b0; // Address bit 12
3'h6: MOSIout <= 1'b0; // Address bit 4
default MOSIout <= 1'b0;
endcase
end 9: begin
case (LS[2:0])
3'h3: MOSIout <= 1'b1; // Command bit 3
3'h4: MOSIout <= 1'b0; // Address bit 19
3'h5: MOSIout <= 1'b0; // Address bit 11
3'h6: MOSIout <= 1'b0; // Address bit 3
default MOSIout <= 1'b0;
endcase
end 11: begin
case (LS[2:0])
3'h3: MOSIout <= 1'b0; // Command bit 2
3'h4: MOSIout <= 1'b0; // Address bit 18
3'h5: MOSIout <= 1'b0; // Address bit 10
3'h6: MOSIout <= 1'b0; // Address bit 2
default MOSIout <= 1'b0;
endcase
end 13: begin
case (LS[2:0])
3'h3: MOSIout <= 1'b1; // Command bit 1
3'h4: MOSIout <= 1'b0; // Address bit 16
3'h5: MOSIout <= 1'b0; // Address bit 9
3'h6: MOSIout <= 1'b0; // Address bit 1
default MOSIout <= 1'b0;
endcase
end 15: begin
case (LS[2:0])
3'h3: MOSIout <= 1'b1; // Command bit 0
3'h4: MOSIout <= 1'b0; // Address bit 15
3'h5: MOSIout <= 1'b0; // Address bit 7
3'h6: MOSIout <= 1'b0; // Address bit 0
default MOSIout <= 1'b0;
endcase
end
endcase
end
/* SDRAM data bus */
inout [7:0] SD = SDOE ? WRD[7:0] : 8'bZ;
reg [7:0] WRD;
reg SDOE = 0;
always @(posedge C25M) begin
case (PS[3:0])
0: begin // NOP CKE
if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
else WRD[7:0] <= RD[7:0];
end 1: begin // ACT
end 2: begin // RD
if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
else WRD[7:0] <= RD[7:0];
end 3: begin // NOP CKE
end 4: begin // NOP CKE
if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
else WRD[7:0] <= RD[7:0];
end 5: begin // NOP CKE
end 6: begin // NOP CKE
if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
else WRD[7:0] <= RD[7:0];
end 7: begin // NOP CKE
end 8: begin // WR AP
if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
else WRD[7:0] <= RD[7:0];
end 9: begin // NOP CKE
end 10: begin // PC all
if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
else WRD[7:0] <= RD[7:0];
end 11: begin // AREF
end 12: begin // NOP CKE
if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
else WRD[7:0] <= RD[7:0];
end 13: begin // NOP CKE
end 14: begin // NOP CKE
if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
else WRD[7:0] <= RD[7:0];
end 15: begin // NOP CKE
end
endcase
end
/* Apple data bus from SDRAM */
/* Apple II data output latch */
reg [7:0] BDout;
always @(negedge C25M) begin
if (PS==5) begin
if (AddrLSpecSEL) RDD[7:0] <= Addr[7:0];
else if (AddrMSpecSEL) RDD[7:0] <= Addr[15:8];
else if (AddrHSpecSEL) RDD[7:0] <= { SetEN24bit ? Addr[23:20] : 4'hF, Addr[19:16] };
else RDD[7:0] <= SD[7:0];
if (S[2:0]==4'h6) begin
if (!nDEVSEL) case (BA[1:0])
4'h3: BDout[7:0] <= RD[7:0];
4'h2: BDout[7:0] <= SetEN24b ? Addr[23:16] { 4'hF, Addr[19:16] };
4'h1: BDout[7:0] <= Addr[15:8];
4'h0: BDout[7:0] <= Addr[7:0];
defaut: BDout[7:0] <= 0;
endcase else BDout[7:0] <= RD[7:0];
end
end
/* SDRAM command */
output reg RCKE = 1;
output reg nRCS = 1;
output reg nRAS = 1;
output reg nCAS = 1;
output reg nSWE = 1;
wire RefReqd = LS[1:0] == 2'b11;
always @(posedge C25M) begin
case (PS[3:0])
0: begin // NOP CKE / NOP CKD
RCKE <= PSStart && (IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL)));
nRCS <= 1;
nRAS <= 1;
nCAS <= 1;
nSWE <= 1;
SDOE <= 0;
end 1: begin // ACT CKE / NOP CKD (ACT)
RCKE <= IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL));
nRCS <= !(IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL)));
nRAS <= 0;
nCAS <= 1;
nSWE <= 1;
SDOE <= 0;
end 2: begin // RD CKE / NOP CKD (RD)
RCKE <= IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL);
nRCS <= !(IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL));
nRAS <= 1;
nCAS <= 0;
nSWE <= 1;
SDOE <= 0;
end 3: begin // NOP CKE / CKD
RCKE <= IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL);
nRCS <= 1;
nRAS <= 1;
nCAS <= 1;
nSWE <= 1;
SDOE <= 0;
end 4: begin // NOP CKD
RCKE <= 0;
nRCS <= 1;
nRAS <= 1;
nCAS <= 1;
nSWE <= 1;
SDOE <= 0;
end 5: begin // NOP CKD
RCKE <= 0;
nRCS <= 1;
nRAS <= 1;
nCAS <= 1;
nSWE <= 1;
SDOE <= 0;
end 6: begin // NOP CKD
RCKE <= 0;
nRCS <= 1;
nRAS <= 1;
nCAS <= 1;
nSWE <= 1;
SDOE <= 0;
end 7: begin // NOP CKE / CKD
RCKE <= IS==6 || (RAMWR && IS==7);
nRCS <= 1;
nRAS <= 1;
nCAS <= 1;
nSWE <= 1;
SDOE <= 0;
end 8: begin // WR AP CKE / NOP CKD (WR AP)
RCKE <= IS==6 || (RAMWR && IS==7);
nRCS <= !(IS==6 || (RAMWR && IS==7));
nRAS <= 1;
nCAS <= 0;
nSWE <= 0;
SDOE <= IS==6 || (RAMWR && IS==7);
end 9: begin // NOP CKE / NOP CKD
RCKE <= 1;
nRCS <= 1;
nRAS <= 1;
nCAS <= 1;
nSWE <= 1;
SDOE <= 0;
end 10: begin // PC all CKE / PC all CKD
RCKE <= IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd);
nRCS <= 0;
nRAS <= 0;
nCAS <= 1;
nSWE <= 0;
SDOE <= 0;
end 11: begin // LDM CKE / AREF CKE / NOP CKD
RCKE <= IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd);
nRCS <= !(IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd));
nRAS <= 0;
nCAS <= 0;
nSWE <= !(IS==1);
SDOE <= 0;
end default: begin // NOP CKD
RCKE <= 0;
nRCS <= 1;
nRAS <= 1;
nCAS <= 1;
nSWE <= 1;
SDOE <= 0;
end
endcase
end
/* SDRAM address */
output reg DQML = 1;
output reg DQMH = 1;
output reg [1:0] SBA;
output reg [12:0] SA;
always @(posedge C25M) begin
case (PS[3:0])
0: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 1: begin // ACT
DQML <= 1'b1;
DQMH <= 1'b1;
if (IS==6) begin
SBA[1:0] <= { 2'b10 };
SA[12:0] <= { 10'b0011000100, LS[12:10] };
end else if (RAMSpecSEL) begin
SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
SA[12:10] <= SetEN24bit ? Addr[22:20] : 3'b000;
SA[9:0] <= Addr[19:10];
end else begin
SBA[1:0] <= 2'b10;
SA[12:0] <= { 10'b0011000100, Bank, RAr[11:10] };
case (IS[2:0])
3'h0: begin
// NOP CKE
end 3'h1: case (S[4:0])
5'h00: begin
// PC all CKE
end 5'h08: begin
// LDM CKE
end 5'h10, 5'h12, 5'h14, 5'h16,
5'h18, 5'h1A, 5'h1C, 5'h1E: begin
// AREF CKE
end default: begin
// NOP CKE
end
end 2: begin // RD
if (RAMSpecSEL) begin
SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
SA[12:0] <= { 4'b0011, Addr[9:1] };
DQML <= Addr[0];
DQMH <= !Addr[0];
end else begin
SBA[1:0] <= 2'b10;
SA[12:0] <= { 4'b0011, RAr[9:1]};
DQML <= RAr[0];
DQMH <= !RAr[0];
endcase 3'h2, 3'h3: case (S[2:0])
3'h0: begin
// NOP CKE
end 3'h1: begin
// AREF CKE
end 3'h2: begin
// NOP CKE
end 3'h3: begin
// ACT CKE
end 3'h4: begin
// WR CKE
end 3'h5: begin
// WR CKE
end 3'h6: begin
// NOP CKE
end 3'h7: begin
// PC all CKD
end
end 3: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 4: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 5: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 6: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 7: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 8: begin // WR AP
if (IS==6) begin
SBA[1:0] <= 2'b10;
SA[12:0] <= { 4'b0011, LS[9:1] };
DQML <= LS[0];
DQMH <= !LS[0];
end else begin
SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
SA[12:0] <= { 4'b0011, Addr[9:1] };
DQML <= Addr[0];
DQMH <= !Addr[0];
endcase default: case (S[3:0])
4'h1: begin
if (!RAMROMCS) begin
// NOP CKD
end else if (nWE) begin
// NOP CKE
end else begin
// NOP CKD
end
end 4'h2: begin
if (!RAMROMCS) begin
// NOP CKD
end else if (nWE) begin
// ACT CKE
end else begin
// NOP CKD
end
end 4'h3: begin
if (!RAMROMCS) begin
// NOP CKD
end else if (nWE) begin
// RD CKE
end else begin
// NOP CKD
end
end 4'h4: begin
if (!RAMROMCS) begin
// NOP CKD
end else if (nWE) begin
// PC all CKE
end else begin
// NOP CKD
end
end 4'h5: begin
if (!RAMROMCS) begin
// NOP CKD
end else if (nWE) begin
// NOP CKD
end else begin
// NOP CKE
end
end 4'h6: begin
if (!RAMROMCS) begin
// NOP CKD
end else if (nWE) begin
// NOP CKD
end else begin
// ACT CKE
end
end 4'h7: begin
if (!RAMROMCS) begin
// NOP CKD
end else if (nWE) begin
// NOP CKD
end else begin
// WR CKE
end
end 4'h8: begin
if (!RAMROMCS) begin
// NOP CKD
end else if (nWE) begin
// NOP CKD
end else begin
// NOP CKE
end
end 4'h9: begin
if (!RAMROMCS) begin
// NOP CKD
end else if (nWE) begin
// NOP CKD
end else begin
// PC all CKD
end
end 4'hA: begin
if (!RAMROMCS) begin
// NOP CKD
end else begin
// NOP CKE
end
end 4'hB: begin
if (!RAMROMCS) begin
// NOP CKD
end else begin
// AREF CKE
end
end default: begin
// NOP CKD
end
end 9: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 10: begin // PC all
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 11: begin // AREF / load mode
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0001000100000;
end 12: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 13: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 14: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 15: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end
endcase
endcase
end

3
fp-lib-table
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@ -1,3 +0,0 @@
(fp_lib_table
(lib (name stdpads)(type KiCad)(uri "$(KIPRJMOD)/../stdpads.pretty")(options "")(descr ""))
)

17657
gerber/GR8RAM-B_Cu.gbl
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2588
gerber/GR8RAM-B_Mask.gbs
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1889
gerber/GR8RAM-B_SilkS.gbo
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61
gerber/GR8RAM-Edge_Cuts.gm1
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@ -1,61 +0,0 @@
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.5-0-10_14)*
G04 #@! TF.CreationDate,2021-04-19T04:27:15-04:00*
G04 #@! TF.ProjectId,GR8RAM,47523852-414d-42e6-9b69-6361645f7063,0.9*
G04 #@! TF.SameCoordinates,Original*
G04 #@! TF.FileFunction,Profile,NP*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW (5.1.5-0-10_14)) date 2021-04-19 04:27:15*
%MOMM*%
%LPD*%
G04 APERTURE LIST*
%ADD10C,0.150000*%
G04 APERTURE END LIST*
D10*
X57785000Y-80391000D02*
X46101001Y-92074999D01*
X57785000Y-80391000D02*
G75*
G02X59309000Y-79883000I1524000J-2032000D01*
G01*
X46101001Y-92074999D02*
G75*
G03X45593000Y-93599000I2031999J-1524001D01*
G01*
X48133000Y-132080000D02*
X73914000Y-132080000D01*
X59309000Y-79883000D02*
X143002000Y-79883000D01*
X143002000Y-79883000D02*
G75*
G02X145542000Y-82423000I0J-2540000D01*
G01*
X138938000Y-139700000D02*
X74422000Y-139700000D01*
X145542000Y-129540000D02*
X145542000Y-82423000D01*
X74422000Y-139700000D02*
G75*
G02X73914000Y-139192000I0J508000D01*
G01*
X139446000Y-139192000D02*
G75*
G02X138938000Y-139700000I-508000J0D01*
G01*
X73914000Y-132080000D02*
X73914000Y-139192000D01*
X45593000Y-129540000D02*
X45593000Y-93599000D01*
X48133000Y-132080000D02*
G75*
G02X45593000Y-129540000I0J2540000D01*
G01*
X143002000Y-132080000D02*
X139446000Y-132080000D01*
X139446000Y-132080000D02*
X139446000Y-139192000D01*
X145542000Y-129540000D02*
G75*
G02X143002000Y-132080000I-2540000J0D01*
G01*
M02*

67267
gerber/GR8RAM-F_Cu.gtl
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17736
gerber/GR8RAM-F_Mask.gts
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26728
gerber/GR8RAM-F_Paste.gtp
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30245
gerber/GR8RAM-F_SilkS.gto
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59308
gerber/GR8RAM-In1_Cu.g2
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76650
gerber/GR8RAM-In2_Cu.g3
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1
gerber/GR8RAM-bottom-pos.csv
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@ -1 +0,0 @@
Ref,Val,Package,MidX,MidY,Rot,Side
1 Ref Val Package MidX MidY Rot Side

6
gerber/GR8RAM-bottom.pos
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@ -1,6 +0,0 @@
### Module positions - created on Monday, April 19, 2021 at 04:27:25 AM ###
### Printed by Pcbnew version kicad (5.1.5-0-10_14)
## Unit = mm, Angle = deg.
## Side : bottom
# Ref Val Package PosX PosY Rot Side
## End

9585
gerber/GR8RAM-drl_map.ps
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60
gerber/GR8RAM-top-pos.csv
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@ -1,60 +0,0 @@
Ref,Val,Package,MidX,MidY,Rot,Side
"C1","10u","C_0805",136.310000,-128.270000,180.000000,top
"C2","10u","C_0805",119.976000,-128.270000,180.000000,top
"C3","10u","C_0805",116.244000,-128.270000,0.000000,top
"C4","10u","C_0805",75.350000,-128.270000,180.000000,top
"C5","2u2","C_0603",113.650000,-90.750000,180.000000,top
"C7","10u","C_0805",140.100000,-124.200000,90.000000,top
"C10","10u","C_0805",132.750000,-124.200000,90.000000,top
"C11","10u","C_0805",130.350000,-124.200000,90.000000,top
"C12","2u2","C_0603",123.650000,-90.750000,180.000000,top
"C13","2u2","C_0603",76.600000,-119.800000,270.000000,top
"C14","2u2","C_0603",85.800000,-119.800000,270.000000,top
"C15","2u2","C_0603",95.000000,-119.800000,270.000000,top
"C16","2u2","C_0603",104.200000,-119.800000,270.000000,top
"C18","2u2","C_0603",82.800000,-103.551000,90.000000,top
"C19","2u2","C_0603",84.350000,-98.000000,90.000000,top
"C20","2u2","C_0603",84.350000,-100.900000,90.000000,top
"C21","2u2","C_0603",90.800000,-111.100000,0.000000,top
"C22","2u2","C_0603",97.800000,-111.100000,0.000000,top
"C23","2u2","C_0603",103.750000,-104.300000,270.000000,top
"C24","2u2","C_0603",103.750000,-100.900000,90.000000,top
"C25","2u2","C_0603",97.150000,-91.700000,180.000000,top
"C26","2u2","C_0603",90.150000,-91.700000,180.000000,top
"C27","2u2","C_0603",105.950000,-98.750000,270.000000,top
"C28","2u2","C_0603",123.650000,-115.350000,180.000000,top
"C29","2u2","C_0603",126.450000,-112.600000,270.000000,top
"C30","2u2","C_0603",126.450000,-107.800000,270.000000,top
"C31","2u2","C_0603",126.450000,-103.800000,270.000000,top
"C32","2u2","C_0603",126.450000,-93.400000,270.000000,top
"C33","2u2","C_0603",110.800000,-104.050000,90.000000,top
"C34","2u2","C_0603",110.850000,-108.700000,90.000000,top
"C35","2u2","C_0603",113.650000,-115.350000,180.000000,top
"C42","2u2","C_0603",117.800000,-122.100000,90.000000,top
"C43","2u2","C_0603",104.800000,-112.250000,0.000000,top
"C44","2u2","C_0603",69.000000,-100.650000,270.000000,top
"FID1","Fiducial","Fiducial",143.002000,-82.423000,270.000000,top
"FID2","Fiducial","Fiducial",48.133000,-93.599000,90.000000,top
"FID3","Fiducial","Fiducial",58.801000,-82.931000,90.000000,top
"FID4","Fiducial","Fiducial",143.002000,-129.540000,0.000000,top
"FID5","Fiducial","Fiducial",48.133000,-129.540000,0.000000,top
"R22","33","R_0603",115.800000,-124.200000,180.000000,top
"R28","22k","R_0603",70.550000,-110.650000,0.000000,top
"R29","22k","R_0603",70.550000,-112.100000,180.000000,top
"R31","33","R_0603",80.950000,-108.500000,90.000000,top
"RN1","4x33","R4_0402",108.200000,-95.150000,0.000000,top
"RN2","4x33","R4_0402",108.450000,-106.250000,270.000000,top
"RN3","4x33","R4_0402",108.450000,-110.650000,270.000000,top
"RN5","4x10k","R4_0402",69.100000,-96.450000,90.000000,top
"SW1","FW","SW_DIP_SPSTx02_Slide_DSHP02TS_P1.27mm",135.763000,-95.885000,0.000000,top
"U1","EPM240T100C5N","TQFP-100_14x14mm_P0.5mm",94.050000,-101.400000,270.000000,top
"U2","W9825","TSOP-II-54_22.2x10.16mm_P0.8mm",118.650000,-103.050000,180.000000,top
"U3","W25Q128JVSIQ","SOIC-8_5.3mm",79.121000,-100.711000,180.000000,top
"U4","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",90.225000,-122.000000,0.000000,top
"U5","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",108.625000,-122.000000,0.000000,top
"U6","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",81.025000,-122.000000,0.000000,top
"U8","XC6206P332MR","SOT-23",136.250000,-124.200000,180.000000,top
"U9","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",99.425000,-122.000000,0.000000,top
"U13","25M","Crystal_SMD_3225-4Pin_3.2x2.5mm",107.100000,-102.500000,0.000000,top
"U14","74LVC1G125GW","SOT-353",115.650000,-121.850000,90.000000,top
"U16","74LVC1G125GW","SOT-353",108.200000,-98.850000,270.000000,top
1 Ref Val Package MidX MidY Rot Side
2 C1 10u C_0805 136.310000 -128.270000 180.000000 top
3 C2 10u C_0805 119.976000 -128.270000 180.000000 top
4 C3 10u C_0805 116.244000 -128.270000 0.000000 top
5 C4 10u C_0805 75.350000 -128.270000 180.000000 top
6 C5 2u2 C_0603 113.650000 -90.750000 180.000000 top
7 C7 10u C_0805 140.100000 -124.200000 90.000000 top
8 C10 10u C_0805 132.750000 -124.200000 90.000000 top
9 C11 10u C_0805 130.350000 -124.200000 90.000000 top
10 C12 2u2 C_0603 123.650000 -90.750000 180.000000 top
11 C13 2u2 C_0603 76.600000 -119.800000 270.000000 top
12 C14 2u2 C_0603 85.800000 -119.800000 270.000000 top
13 C15 2u2 C_0603 95.000000 -119.800000 270.000000 top
14 C16 2u2 C_0603 104.200000 -119.800000 270.000000 top
15 C18 2u2 C_0603 82.800000 -103.551000 90.000000 top
16 C19 2u2 C_0603 84.350000 -98.000000 90.000000 top
17 C20 2u2 C_0603 84.350000 -100.900000 90.000000 top
18 C21 2u2 C_0603 90.800000 -111.100000 0.000000 top
19 C22 2u2 C_0603 97.800000 -111.100000 0.000000 top
20 C23 2u2 C_0603 103.750000 -104.300000 270.000000 top
21 C24 2u2 C_0603 103.750000 -100.900000 90.000000 top
22 C25 2u2 C_0603 97.150000 -91.700000 180.000000 top
23 C26 2u2 C_0603 90.150000 -91.700000 180.000000 top
24 C27 2u2 C_0603 105.950000 -98.750000 270.000000 top
25 C28 2u2 C_0603 123.650000 -115.350000 180.000000 top
26 C29 2u2 C_0603 126.450000 -112.600000 270.000000 top
27 C30 2u2 C_0603 126.450000 -107.800000 270.000000 top
28 C31 2u2 C_0603 126.450000 -103.800000 270.000000 top
29 C32 2u2 C_0603 126.450000 -93.400000 270.000000 top
30 C33 2u2 C_0603 110.800000 -104.050000 90.000000 top
31 C34 2u2 C_0603 110.850000 -108.700000 90.000000 top
32 C35 2u2 C_0603 113.650000 -115.350000 180.000000 top
33 C42 2u2 C_0603 117.800000 -122.100000 90.000000 top
34 C43 2u2 C_0603 104.800000 -112.250000 0.000000 top
35 C44 2u2 C_0603 69.000000 -100.650000 270.000000 top
36 FID1 Fiducial Fiducial 143.002000 -82.423000 270.000000 top
37 FID2 Fiducial Fiducial 48.133000 -93.599000 90.000000 top
38 FID3 Fiducial Fiducial 58.801000 -82.931000 90.000000 top
39 FID4 Fiducial Fiducial 143.002000 -129.540000 0.000000 top
40 FID5 Fiducial Fiducial 48.133000 -129.540000 0.000000 top
41 R22 33 R_0603 115.800000 -124.200000 180.000000 top
42 R28 22k R_0603 70.550000 -110.650000 0.000000 top
43 R29 22k R_0603 70.550000 -112.100000 180.000000 top
44 R31 33 R_0603 80.950000 -108.500000 90.000000 top
45 RN1 4x33 R4_0402 108.200000 -95.150000 0.000000 top
46 RN2 4x33 R4_0402 108.450000 -106.250000 270.000000 top
47 RN3 4x33 R4_0402 108.450000 -110.650000 270.000000 top
48 RN5 4x10k R4_0402 69.100000 -96.450000 90.000000 top
49 SW1 FW SW_DIP_SPSTx02_Slide_DSHP02TS_P1.27mm 135.763000 -95.885000 0.000000 top
50 U1 EPM240T100C5N TQFP-100_14x14mm_P0.5mm 94.050000 -101.400000 270.000000 top
51 U2 W9825 TSOP-II-54_22.2x10.16mm_P0.8mm 118.650000 -103.050000 180.000000 top
52 U3 W25Q128JVSIQ SOIC-8_5.3mm 79.121000 -100.711000 180.000000 top
53 U4 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 90.225000 -122.000000 0.000000 top
54 U5 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 108.625000 -122.000000 0.000000 top
55 U6 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 81.025000 -122.000000 0.000000 top
56 U8 XC6206P332MR SOT-23 136.250000 -124.200000 180.000000 top
57 U9 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 99.425000 -122.000000 0.000000 top
58 U13 25M Crystal_SMD_3225-4Pin_3.2x2.5mm 107.100000 -102.500000 0.000000 top
59 U14 74LVC1G125GW SOT-353 115.650000 -121.850000 90.000000 top
60 U16 74LVC1G125GW SOT-353 108.200000 -98.850000 270.000000 top

65
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View File

@ -1,65 +0,0 @@
### Module positions - created on Monday, April 19, 2021 at 04:27:25 AM ###
### Printed by Pcbnew version kicad (5.1.5-0-10_14)
## Unit = mm, Angle = deg.
## Side : top
# Ref Val Package PosX PosY Rot Side
C1 10u C_0805 136.3100 -128.2700 180.0000 top
C2 10u C_0805 119.9760 -128.2700 180.0000 top
C3 10u C_0805 116.2440 -128.2700 0.0000 top
C4 10u C_0805 75.3500 -128.2700 180.0000 top
C5 2u2 C_0603 113.6500 -90.7500 180.0000 top
C7 10u C_0805 140.1000 -124.2000 90.0000 top
C10 10u C_0805 132.7500 -124.2000 90.0000 top
C11 10u C_0805 130.3500 -124.2000 90.0000 top
C12 2u2 C_0603 123.6500 -90.7500 180.0000 top
C13 2u2 C_0603 76.6000 -119.8000 270.0000 top
C14 2u2 C_0603 85.8000 -119.8000 270.0000 top
C15 2u2 C_0603 95.0000 -119.8000 270.0000 top
C16 2u2 C_0603 104.2000 -119.8000 270.0000 top
C18 2u2 C_0603 82.8000 -103.5510 90.0000 top
C19 2u2 C_0603 84.3500 -98.0000 90.0000 top
C20 2u2 C_0603 84.3500 -100.9000 90.0000 top
C21 2u2 C_0603 90.8000 -111.1000 0.0000 top
C22 2u2 C_0603 97.8000 -111.1000 0.0000 top
C23 2u2 C_0603 103.7500 -104.3000 270.0000 top
C24 2u2 C_0603 103.7500 -100.9000 90.0000 top
C25 2u2 C_0603 97.1500 -91.7000 180.0000 top
C26 2u2 C_0603 90.1500 -91.7000 180.0000 top
C27 2u2 C_0603 105.9500 -98.7500 270.0000 top
C28 2u2 C_0603 123.6500 -115.3500 180.0000 top
C29 2u2 C_0603 126.4500 -112.6000 270.0000 top
C30 2u2 C_0603 126.4500 -107.8000 270.0000 top
C31 2u2 C_0603 126.4500 -103.8000 270.0000 top
C32 2u2 C_0603 126.4500 -93.4000 270.0000 top
C33 2u2 C_0603 110.8000 -104.0500 90.0000 top
C34 2u2 C_0603 110.8500 -108.7000 90.0000 top
C35 2u2 C_0603 113.6500 -115.3500 180.0000 top
C42 2u2 C_0603 117.8000 -122.1000 90.0000 top
C43 2u2 C_0603 104.8000 -112.2500 0.0000 top
C44 2u2 C_0603 69.0000 -100.6500 270.0000 top
FID1 Fiducial Fiducial 143.0020 -82.4230 270.0000 top
FID2 Fiducial Fiducial 48.1330 -93.5990 90.0000 top
FID3 Fiducial Fiducial 58.8010 -82.9310 90.0000 top
FID4 Fiducial Fiducial 143.0020 -129.5400 0.0000 top
FID5 Fiducial Fiducial 48.1330 -129.5400 0.0000 top
R22 33 R_0603 115.8000 -124.2000 180.0000 top
R28 22k R_0603 70.5500 -110.6500 0.0000 top
R29 22k R_0603 70.5500 -112.1000 180.0000 top
R31 33 R_0603 80.9500 -108.5000 90.0000 top
RN1 4x33 R4_0402 108.2000 -95.1500 0.0000 top
RN2 4x33 R4_0402 108.4500 -106.2500 270.0000 top
RN3 4x33 R4_0402 108.4500 -110.6500 270.0000 top
RN5 4x10k R4_0402 69.1000 -96.4500 90.0000 top
SW1 FW SW_DIP_SPSTx02_Slide_DSHP02TS_P1.27mm 135.7630 -95.8850 0.0000 top
U1 EPM240T100C5N TQFP-100_14x14mm_P0.5mm 94.0500 -101.4000 270.0000 top
U2 W9825 TSOP-II-54_22.2x10.16mm_P0.8mm 118.6500 -103.0500 180.0000 top
U3 W25Q128JVSIQ SOIC-8_5.3mm 79.1210 -100.7110 180.0000 top
U4 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 90.2250 -122.0000 0.0000 top
U5 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 108.6250 -122.0000 0.0000 top
U6 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 81.0250 -122.0000 0.0000 top
U8 XC6206P332MR SOT-23 136.2500 -124.2000 180.0000 top
U9 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 99.4250 -122.0000 0.0000 top
U13 25M Crystal_SMD_3225-4Pin_3.2x2.5mm 107.1000 -102.5000 0.0000 top
U14 74LVC1G125GW SOT-353 115.6500 -121.8500 90.0000 top
U16 74LVC1G125GW SOT-353 108.2000 -98.8500 270.0000 top
## End

759
gerber/GR8RAM.drl
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@ -1,759 +0,0 @@
M48
; DRILL file {KiCad (5.1.5-0-10_14)} date Monday, April 19, 2021 at 04:27:16 AM
; FORMAT={-:-/ absolute / inch / decimal}
; #@! TF.CreationDate,2021-04-19T04:27:16-04:00
; #@! TF.GenerationSoftware,Kicad,Pcbnew,(5.1.5-0-10_14)
FMAT,2
INCH
T1C0.0079
T2C0.0118
T3C0.0150
T4C0.0157
T5C0.0300
T6C0.0400
T7C0.0433
T8C0.0390
T9C0.0454
T10C0.0935
%
G90
G05
T1
X1.825Y-3.68
X1.825Y-3.915
X1.825Y-4.115
X1.825Y-4.315
X1.825Y-4.515
X1.825Y-4.715
X1.825Y-4.915
X1.825Y-5.1
X1.895Y-5.17
X1.925Y-3.575
X1.925Y-4.015
X1.925Y-4.215
X1.925Y-4.415
X1.925Y-4.615
X1.925Y-4.815
X2.025Y-3.475
X2.025Y-3.715
X2.025Y-3.915
X2.025Y-4.115
X2.025Y-4.315
X2.025Y-4.515
X2.025Y-4.715
X2.025Y-4.915
X2.025Y-5.17
X2.12Y-5.04
X2.125Y-3.375
X2.125Y-3.615
X2.125Y-3.815
X2.125Y-4.015
X2.125Y-4.215
X2.125Y-4.415
X2.125Y-4.615
X2.125Y-4.815
X2.2Y-3.485
X2.22Y-4.515
X2.22Y-4.715
X2.22Y-4.915
X2.2205Y-3.915
X2.2205Y-4.115
X2.2205Y-4.315
X2.225Y-3.275
X2.225Y-3.715
X2.225Y-5.17
X2.2598Y-4.3327
X2.2598Y-4.878
X2.28Y-3.4
X2.2854Y-4.5354
X2.29Y-3.585
X2.313Y-4.876
X2.32Y-5.04
X2.33Y-3.175
X2.345Y-3.475
X2.345Y-3.675
X2.36Y-3.32
X2.3701Y-4.2067
X2.415Y-4.6375
X2.4225Y-4.91
X2.425Y-5.17
X2.445Y-3.175
X2.445Y-3.375
X2.445Y-3.575
X2.465Y-4.7525
X2.4775Y-4.6075
X2.4843Y-4.5728
X2.495Y-4.6325
X2.5075Y-4.53
X2.52Y-5.04
X2.525Y-4.79
X2.525Y-4.82
X2.5433Y-4.498
X2.545Y-3.275
X2.545Y-3.475
X2.545Y-3.675
X2.59Y-4.185
X2.59Y-4.24
X2.6025Y-4.91
X2.625Y-5.17
X2.6299Y-3.9921
X2.6299Y-4.3327
X2.645Y-3.175
X2.645Y-3.375
X2.645Y-3.575
X2.6732Y-3.7972
X2.6831Y-3.939
X2.6831Y-3.9862
X2.6909Y-4.3937
X2.7028Y-4.2953
X2.7028Y-4.3504
X2.7165Y-3.9016
X2.7165Y-4.0236
X2.72Y-5.04
X2.725Y-4.615
X2.725Y-4.815
X2.7402Y-3.7421
X2.7402Y-3.8524
X2.745Y-3.275
X2.745Y-3.475
X2.745Y-3.675
X2.7461Y-4.3228
X2.7461Y-4.4469
X2.75Y-3.939
X2.75Y-3.9862
X2.825Y-4.515
X2.825Y-4.715
X2.825Y-4.915
X2.825Y-5.17
X2.8366Y-4.3563
X2.8386Y-4.4134
X2.845Y-3.175
X2.845Y-3.175
X2.845Y-3.375
X2.845Y-3.375
X2.845Y-3.575
X2.925Y-4.615
X2.925Y-4.815
X2.945Y-3.275
X2.945Y-3.475
X2.9803Y-4.002
X3.0059Y-4.122
X3.01Y-3.8225
X3.025Y-4.515
X3.04Y-3.7725
X3.04Y-3.87
X3.04Y-4.06
X3.045Y-3.175
X3.045Y-3.375
X3.05Y-5.17
X3.0502Y-4.687
X3.0502Y-4.7461
X3.065Y-5.0079
X3.0709Y-4.2224
X3.0748Y-4.6437
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X3.0748Y-4.874
X3.0787Y-4.1713
X3.0825Y-3.77
X3.09Y-4.06
X3.1004Y-4.9646
X3.1024Y-4.6437
X3.126Y-4.9941
X3.14Y-4.06
X3.1417Y-4.2776
X3.145Y-3.275
X3.145Y-3.475
X3.1475Y-3.77
X3.1476Y-5.0531
X3.15Y-5.17
X3.1516Y-4.2382
X3.1516Y-4.9646
X3.1772Y-4.9941
X3.1791Y-5.1142
X3.19Y-3.77
X3.19Y-4.1575
X3.2028Y-4.9646
X3.22Y-5.0925
X3.2264Y-4.0472
X3.2264Y-4.1063
X3.2283Y-4.9941
X3.2362Y-4.2992
X3.245Y-3.175
X3.245Y-3.375
X3.248Y-3.8504
X3.25Y-5.17
X3.2539Y-4.9646
X3.2559Y-4.2638
X3.2598Y-4.0157
X3.2598Y-4.1378
X3.2657Y-3.9154
X3.2736Y-3.6929
X3.2756Y-4.2992
X3.2795Y-4.9941
X3.2874Y-3.8346
X3.2874Y-3.8819
X3.2874Y-3.9488
X3.2874Y-3.9961
X3.2933Y-4.0472
X3.3051Y-4.874
X3.3051Y-4.9646
X3.313Y-4.2677
X3.3169Y-4.0335
X3.3209Y-4.2283
X3.3268Y-4.4783
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X3.3445Y-4.6909
X3.345Y-3.31
X3.345Y-3.48
X3.35Y-5.17
X3.3524Y-4.1201
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X3.3642Y-4.2736
X3.4016Y-3.7185
X3.4016Y-4.3228
X3.4114Y-4.7461
X3.4124Y-4.687
X3.4193Y-5.1161
X3.4213Y-4.9685
X3.4311Y-3.6575
X3.437Y-4.6437
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X3.437Y-4.874
X3.4409Y-4.3996
X3.4449Y-3.9114
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X3.4449Y-3.9921
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X3.4469Y-4.0709
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X3.4567Y-4.189
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X3.4823Y-4.0118
X3.4843Y-3.9232
X3.5039Y-3.7638
X3.5157Y-3.6437
X3.5197Y-5.1122
X3.5217Y-4.0984
X3.545Y-3.3
X3.5453Y-3.7539
X3.5453Y-4.2087
X3.55Y-5.17
X3.5551Y-5.0925
X3.5591Y-4.3386
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X3.6398Y-4.4449
X3.6437Y-5.0374
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X3.745Y-3.3
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X3.75Y-5.17
X3.7746Y-4.687
X3.7746Y-4.7461
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X3.8268Y-3.815
X3.8268Y-4.6437
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X3.9193Y-5.061
X3.9213Y-4.0335
X3.9213Y-4.0945
X3.9232Y-3.7362
X3.9232Y-3.9331
X3.9232Y-3.9724
X3.9272Y-4.2264
X3.9272Y-4.5217
X3.939Y-3.6457
X3.939Y-4.4449
X3.945Y-3.305
X3.945Y-3.475
X3.95Y-5.17
X3.9567Y-4.1142
X3.9587Y-3.7756
X3.9587Y-3.815
X3.9587Y-3.8543
X3.9587Y-3.8937
X3.9587Y-3.9528
X3.9587Y-3.9921
X3.9587Y-4.0472
X3.9587Y-4.0748
X3.9764Y-4.3917
X3.9823Y-3.6614
X4.0197Y-5.1063
X4.0256Y-4.3071
X4.0295Y-4.874
X4.0295Y-4.9646
X4.0354Y-4.6299
X4.045Y-3.175
X4.045Y-3.405
X4.045Y-3.575
X4.0492Y-3.7559
X4.0492Y-3.7953
X4.0492Y-3.8346
X4.0492Y-3.874
X4.0492Y-3.9134
X4.0492Y-3.9528
X4.0492Y-3.9921
X4.0492Y-4.0453
X4.0492Y-4.0768
X4.05Y-5.17
X4.0502Y-4.1398
X4.0551Y-4.9193
X4.061Y-5.0827
X4.065Y-4.4193
X4.0689Y-4.6909
X4.0846Y-4.1673
X4.0925Y-4.5079
X4.0945Y-4.2549
X4.1024Y-4.3858
X4.1024Y-4.4528
X4.122Y-3.9449
X4.124Y-4.0394
X4.1358Y-3.8957
X4.1358Y-4.7461
X4.1368Y-4.687
X4.1417Y-5.0669
X4.1437Y-4.3346
X4.145Y-3.305
X4.145Y-3.475
X4.1496Y-4.3858
X4.1496Y-4.4528
X4.15Y-5.17
X4.1614Y-4.6437
X4.1614Y-4.7303
X4.1614Y-4.874
X4.1713Y-3.8189
X4.1732Y-3.9488
X4.187Y-4.4193
X4.187Y-4.7303
X4.187Y-4.8445
X4.189Y-4.6437
X4.1929Y-4.1555
X4.2028Y-3.8189
X4.2067Y-3.9173
X4.2087Y-4.9921
X4.2106Y-3.8583
X4.2126Y-4.874
X4.2205Y-5.0551
X4.2343Y-3.8228
X4.2343Y-3.9587
X4.2382Y-4.8445
X4.245Y-3.175
X4.245Y-3.405
X4.245Y-3.575
X4.25Y-5.17
X4.2539Y-4.1083
X4.2559Y-4.2697
X4.2598Y-3.8484
X4.2638Y-4.874
X4.2854Y-3.9587
X4.2874Y-4.4646
X4.2874Y-4.9921
X4.2894Y-4.128
X4.2894Y-4.2382
X4.2894Y-4.3012
X4.2894Y-4.4114
X4.2894Y-4.8445
X4.3071Y-3.9252
X4.3189Y-4.1634
X4.3189Y-4.2028
X4.3189Y-4.3366
X4.3189Y-4.376
X4.3228Y-3.7598
X4.3287Y-4.1201
X4.3287Y-4.25
X4.3346Y-5.0571
X4.3406Y-4.9646
X4.345Y-3.305
X4.345Y-3.475
X4.35Y-5.17
X4.3602Y-3.7972
X4.3661Y-3.9291
X4.3917Y-4.874
X4.3917Y-4.9646
X4.3996Y-3.6417
X4.3996Y-4.0571
X4.3996Y-4.1201
X4.3996Y-4.3091
X4.3996Y-4.4035
X4.3996Y-4.4665
X4.4173Y-4.9193
X4.4449Y-4.4902
X4.445Y-3.175
X4.445Y-3.405
X4.45Y-5.17
X4.4547Y-5.0374
X4.455Y-4.875
X4.4902Y-3.6476
X4.4902Y-3.7106
X4.4902Y-3.7736
X4.4902Y-3.8366
X4.4902Y-3.8996
X4.4902Y-3.9941
X4.4902Y-4.0571
X4.4902Y-4.1201
X4.4902Y-4.2146
X4.4902Y-4.3091
X4.4902Y-4.4035
X4.4902Y-4.4665
X4.5039Y-4.7638
X4.5157Y-3.6791
X4.5157Y-3.7421
X4.5157Y-3.8051
X4.5157Y-3.8681
X4.5157Y-3.9311
X4.5177Y-4.0886
X4.5177Y-4.1476
X4.5177Y-4.187
X4.5177Y-4.2421
X4.5177Y-4.2815
X4.5177Y-4.3366
X4.5177Y-4.376
X4.5177Y-4.435
X4.5276Y-4.7283
X4.545Y-3.305
X4.545Y-3.475
X4.55Y-5.17
X4.555Y-4.675
X4.5787Y-4.7283
X4.5906Y-4.937
X4.6004Y-4.8307
X4.6043Y-4.7835
X4.624Y-4.0571
X4.6378Y-4.7461
X4.6378Y-4.8681
X4.645Y-3.175
X4.645Y-3.405
X4.645Y-3.575
X4.645Y-4.575
X4.65Y-5.17
X4.6713Y-4.1201
X4.6713Y-4.1673
X4.6713Y-4.2146
X4.6713Y-4.2618
X4.6713Y-4.3091
X4.6713Y-4.3563
X4.6713Y-4.4035
X4.6713Y-4.4665
X4.6713Y-4.7835
X4.6713Y-4.8307
X4.7185Y-4.0571
X4.745Y-3.275
X4.745Y-3.475
X4.745Y-4.675
X4.745Y-4.875
X4.75Y-5.17
X4.8012Y-3.6791
X4.8248Y-4.0886
X4.8248Y-4.1476
X4.8248Y-4.187
X4.8248Y-4.2421
X4.8248Y-4.2815
X4.8248Y-4.3366
X4.8248Y-4.376
X4.8248Y-4.435
X4.8268Y-3.7106
X4.8268Y-3.7736
X4.8268Y-3.8366
X4.8268Y-3.8996
X4.8268Y-3.9626
X4.8268Y-4.0256
X4.845Y-3.175
X4.845Y-3.375
X4.845Y-4.775
X4.845Y-4.975
X4.85Y-5.17
X4.8524Y-3.6476
X4.8524Y-3.7421
X4.8524Y-3.8051
X4.8524Y-3.8681
X4.8524Y-3.9311
X4.8524Y-3.9941
X4.8524Y-4.0571
X4.8524Y-4.1201
X4.8524Y-4.2146
X4.8524Y-4.3091
X4.8524Y-4.4035
X4.8524Y-4.4665
X4.8976Y-3.6201
X4.8976Y-4.4902
X4.9429Y-3.6476
X4.9429Y-4.0571
X4.9429Y-4.1201
X4.9429Y-4.2146
X4.9429Y-4.4035
X4.9429Y-4.4508
X4.9449Y-3.7067
X4.945Y-3.275
X4.945Y-3.475
X4.945Y-4.675
X4.945Y-4.875
X4.945Y-5.075
X4.95Y-5.17
X5.045Y-3.175
X5.045Y-3.375
X5.045Y-3.575
X5.045Y-3.775
X5.045Y-3.975
X5.045Y-4.575
X5.045Y-4.775
X5.045Y-4.975
X5.05Y-5.17
X5.145Y-3.275
X5.145Y-3.475
X5.145Y-3.675
X5.145Y-3.875
X5.145Y-4.475
X5.145Y-4.675
X5.145Y-5.075
X5.15Y-5.17
X5.2Y-5.165
X5.245Y-3.175
X5.245Y-3.375
X5.245Y-3.575
X5.245Y-3.775
X5.245Y-3.975
X5.245Y-4.575
X5.25Y-5.17
X5.3Y-5.165
X5.3Y-5.165
X5.32Y-3.58
X5.32Y-3.97
X5.345Y-3.275
X5.345Y-3.475
X5.345Y-3.675
X5.345Y-3.875
X5.345Y-4.475
X5.345Y-4.675
X5.35Y-5.17
X5.37Y-3.58
X5.37Y-3.97
X5.445Y-3.175
X5.445Y-3.375
X5.445Y-3.575
X5.445Y-3.775
X5.445Y-3.975
X5.445Y-4.575
X5.445Y-4.775
X5.45Y-5.17
X5.545Y-3.475
X5.545Y-3.675
X5.545Y-3.875
X5.545Y-4.475
X5.545Y-4.675
X5.63Y-3.175
X5.63Y-5.17
X5.645Y-3.375
X5.645Y-3.575
X5.645Y-3.775
X5.645Y-3.975
X5.645Y-4.175
X5.645Y-4.575
X5.645Y-4.775
X5.7Y-3.245
X5.7Y-3.475
X5.7Y-3.675
X5.7Y-3.875
X5.7Y-4.075
X5.7Y-4.275
X5.7Y-4.475
X5.7Y-4.475
X5.7Y-4.675
X5.7Y-4.875
X5.7Y-5.1
T2
X2.9803Y-4.6929
X2.9803Y-4.7402
X3.0157Y-4.6535
X3.0157Y-4.7795
X3.3425Y-4.7402
X3.378Y-4.7795
X3.4862Y-3.6102
X3.5118Y-4.374
X3.5256Y-3.5748
X3.5512Y-4.4094
X3.5728Y-3.5748
X3.5984Y-4.4094
X3.6378Y-4.374
X3.7047Y-4.7402
X3.7402Y-4.7795
X3.7618Y-3.6102
X3.7874Y-4.374
X3.8012Y-3.5748
X3.8268Y-4.4094
X3.8484Y-3.5748
X3.874Y-4.4094
X3.8878Y-3.6102
X3.9134Y-4.374
X4.0669Y-4.7402
X4.1024Y-4.7795
X4.1201Y-4.1358
X4.3622Y-4.0335
X4.4114Y-3.5728
X4.4114Y-4.5413
X4.4449Y-3.6201
X4.4508Y-3.5374
X4.4508Y-4.5768
X4.498Y-3.5374
X4.498Y-3.6083
X4.498Y-4.5059
X4.498Y-4.5768
X4.5374Y-3.5728
X4.5374Y-4.5413
X4.8051Y-3.5728
X4.8051Y-4.5413
X4.8445Y-3.5374
X4.8445Y-3.6083
X4.8445Y-4.5059
X4.8445Y-4.5768
X4.8917Y-3.5374
X4.8917Y-4.5768
X4.9311Y-3.5728
X4.9311Y-4.5413
X4.9783Y-3.6142
X4.9783Y-4.1496
X4.9783Y-4.1811
X4.9783Y-4.3701
X5.0138Y-4.4094
X5.0138Y-4.4567
T3
X4.9783Y-4.311
X5.0177Y-4.0669
X5.0177Y-4.1063
T4
X2.89Y-5.06
X2.935Y-5.1
X3.0Y-5.1
X3.045Y-5.05
X3.378Y-4.6496
X3.7402Y-4.6496
X4.0846Y-4.0394
X4.1024Y-4.6496
X4.124Y-4.002
X4.124Y-4.0768
X4.3091Y-4.0689
X4.3642Y-4.1575
X4.3642Y-4.2126
X4.3642Y-4.3484
X4.5Y-5.05
X4.545Y-5.1
X4.61Y-5.1
X4.69Y-5.1
X4.755Y-5.1
X4.7975Y-5.05
X4.9783Y-3.7441
X4.9783Y-4.0197
X4.9783Y-4.5
X5.0177Y-3.6575
X5.0177Y-3.6969
X5.0177Y-4.2244
X5.0177Y-4.2638
X5.0846Y-4.8563
X5.0846Y-4.9154
X5.1319Y-4.815
X5.1319Y-4.9646
X5.1791Y-4.8642
X5.1791Y-4.9154
X5.2264Y-4.815
X5.2264Y-4.9646
X5.2756Y-4.8622
X5.2756Y-4.9173
X5.29Y-5.05
X5.3228Y-4.815
X5.3228Y-4.9626
X5.335Y-5.0
X5.335Y-5.1
X5.4Y-5.0
X5.445Y-5.05
X5.4685Y-4.8602
X5.5157Y-4.815
X5.563Y-4.8642
T5
X5.4Y-5.11
T6
X2.425Y-3.86
X2.425Y-3.96
X2.425Y-4.06
X2.425Y-4.16
X2.425Y-4.26
X2.525Y-3.86
X2.525Y-3.96
X2.525Y-4.06
X2.525Y-4.16
X2.525Y-4.26
T7
X5.53Y-5.1
T8
X2.365Y-4.695
X2.665Y-4.655
X2.665Y-4.735
X2.365Y-4.695
X2.665Y-4.655
X2.665Y-4.735
T9
X1.895Y-5.0
X2.245Y-3.335
X5.53Y-3.245
X5.63Y-5.0
X1.895Y-3.785
T10
X2.365Y-4.595
X2.365Y-4.795
X2.59Y-4.595
X2.59Y-4.795
X2.365Y-4.595
X2.365Y-4.795
X2.59Y-4.595
X2.59Y-4.795
T0
M30

6
sym-lib-table
View File

@ -1,6 +0,0 @@
(sym_lib_table
(lib (name GW_RAM)(type Legacy)(uri ${KIPRJMOD}/../GW_Parts/GW_RAM.lib)(options "")(descr ""))
(lib (name GW_PLD)(type Legacy)(uri ${KIPRJMOD}/../GW_Parts/GW_PLD.lib)(options "")(descr ""))
(lib (name GW_Logic)(type Legacy)(uri ${KIPRJMOD}/../GW_Parts/GW_Logic.lib)(options "")(descr ""))
(lib (name GW_Power)(type Legacy)(uri ${KIPRJMOD}/../GW_Parts/GW_Power.lib)(options "")(descr ""))
)