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https://github.com/garrettsworkshop/GR8RAM.git
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Add SPI
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78ff51995b
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106
cpld/GR8RAM.v
106
cpld/GR8RAM.v
@ -19,7 +19,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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/* Firmware select */
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input [1:0] SetFW;
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wire [1:0] SetROM = ~SetFW[1:0];
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wire SetEN16MB = 0;//SetROM[1:0]==2'b11;
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wire SetENRestore = SetROM[1:0]==1'b11;
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wire SetEN24bit = SetROM[1];
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/* State counter from PHI0 rising edge */
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@ -58,12 +58,14 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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always @(posedge PHI0) CXXXr <= RA[15:12]==4'hC;
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/* Apple select signals */
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wire RAMExists = (~SetEN24bit || SetEN16MB || ~Addr[23]);
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wire BankSEL = REGEN && !nDEVSEL && RA[3:0]==4'hF;
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wire RAMSEL = REGEN && !nDEVSEL && RA[3:0]==4'h3;
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wire AddrHSEL = REGEN && !nDEVSEL && RA[3:0]==4'h2;
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wire AddrMSEL = REGEN && !nDEVSEL && RA[3:0]==4'h1;
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wire AddrLSEL = REGEN && !nDEVSEL && RA[3:0]==4'h0;
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wire RAMExists = (!SetEN24bit || !Addr[23] || Addr[22] || Addr[21]);
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wire BankSEL = REGEN && !nDEVSEL && RA[3:0]==4'hF;
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wire SPITX1SEL = REGEN && !nDEVSEL && RA[3:0]==4'hD;
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wire SPITX0SEL = REGEN && !nDEVSEL && RA[3:0]==4'hC;
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wire RAMSEL = REGEN && !nDEVSEL && RA[3:0]==4'h3;
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wire AddrHSEL = REGEN && !nDEVSEL && RA[3:0]==4'h2;
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wire AddrMSEL = REGEN && !nDEVSEL && RA[3:0]==4'h1;
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wire AddrLSEL = REGEN && !nDEVSEL && RA[3:0]==4'h0;
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/* IOROMEN control */
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reg IOROMEN = 0;
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@ -78,7 +80,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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reg REGEN = 0;
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always @(posedge C25M, negedge nRESr) begin
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if (!nRESr) REGEN <= 0;
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else if (!nIOSEL) REGEN <= 1;
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else if (PS==8 && !nIOSEL) REGEN <= 1;
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end
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/* Apple data bus */
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@ -104,7 +106,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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if (PS==8 && AddrLSEL && !nWE) begin
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Addr[7:0] <= RD[7:0];
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AddrIncM <= Addr[7] && ~RD[7];
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AddrIncM <= Addr[7] && !RD[7];
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end else if (AddrIncL) begin
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Addr[7:0] <= Addr[7:0]+1;
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AddrIncM <= Addr[7:0]==8'hFF;
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@ -112,7 +114,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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if (PS==8 && AddrMSEL && !nWE) begin
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Addr[15:8] <= RD[7:0];
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AddrIncH <= Addr[15] && ~RD[7];
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AddrIncH <= Addr[15] && !RD[7];
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end else if (AddrIncM) begin
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Addr[15:8] <= Addr[15:8]+1;
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AddrIncH <= Addr[15:8]==8'hFF;
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@ -126,22 +128,27 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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end
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end
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/* ROM bank register and restore state */
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reg Bank = 0;
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reg RestoreDone = 0;
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/* ROM bank register */
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reg Bank;
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always @(posedge C25M, negedge nRESr) begin
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if (~nRESr) Bank <= 0;
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if (!nRESr) Bank <= 0;
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else if (PS==8 && BankSEL && !nWE) begin
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Bank <= RD[0];
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if (RD[0]) RestoreDone <= 1;
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end
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end
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/* Restore state */
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reg RestoreDone = 0;
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always @(posedge C25M) begin
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if (!SetENRestore) RestoreDone <= 1;
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else if (PS==8 && BankSEL && !nWE) begin
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if (RD[1:0]==2'b11) RestoreDone <= 1;
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end
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end
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/* SPI flash control signals */
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output nFCS = FCKOE ? ~FCS : 1'bZ;
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reg FCS = 0;
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output FCK = FCKOE ? FCKout : 1'bZ;
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reg FCKOE = 0;
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output reg nFCS = 1;
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output FCK = FCKout;
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reg FCKout = 0;
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inout MOSI = MOSIOE ? MOSIout : 1'bZ;
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reg MOSIOE = 0;
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@ -151,40 +158,39 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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0: begin // NOP CKE
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FCKout <= 1'b1;
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end 1: begin // ACT
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FCKout <= ~(IS==5 || IS==6);
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FCKout <= !(IS==5 || IS==6);
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end 2: begin // RD
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FCKout <= 1'b1;
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end 3: begin // NOP CKE
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FCKout <= ~(IS==5 || IS==6);
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FCKout <= !(IS==5 || IS==6);
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end 4: begin // NOP CKE
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FCKout <= 1'b1;
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end 5: begin // NOP CKE
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FCKout <= ~(IS==5 || IS==6);
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FCKout <= !(IS==5 || IS==6);
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end 6: begin // NOP CKE
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FCKout <= 1'b1;
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end 7: begin // NOP CKE
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FCKout <= ~(IS==5 || IS==6);
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FCKout <= !(IS==5 || IS==6 || (!RestoreDone && SetENRestore && (SPITX0SEL || SPITX1SEL)));
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end 8: begin // WR AP
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FCKout <= 1'b1;
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end 9: begin // NOP CKE
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FCKout <= ~(IS==5);
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FCKout <= !(IS==5);
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end 10: begin // PC all
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FCKout <= 1'b1;
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end 11: begin // AREF
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FCKout <= ~(IS==5);
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FCKout <= !(IS==5);
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end 12: begin // NOP CKE
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FCKout <= 1'b1;
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end 13: begin // NOP CKE
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FCKout <= ~(IS==5);
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FCKout <= !(IS==5);
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end 14: begin // NOP CKE
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FCKout <= 1'b1;
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end 15: begin // NOP CKE
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FCKout <= ~(IS==5);
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FCKout <= !(IS==5);
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end
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endcase
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FCS <= IS==4 || IS==5 || IS==6;
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nFCS <= !(IS==4 || IS==5 || IS==6);
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MOSIOE <= IS==5;
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FCKOE <= IS==1 || IS==4 || IS==5 || IS==6 || IS==7;
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end
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/* SPI flash MOSI control */
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@ -216,13 +222,13 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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default MOSIout <= 1'b0;
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endcase
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end 7: begin
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case (LS[2:0])
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3'h3: MOSIout <= 1'b1; // Command bit 4
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3'h4: MOSIout <= 1'b0; // Address bit 20
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3'h5: MOSIout <= 1'b0; // Address bit 12
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3'h6: MOSIout <= 1'b0; // Address bit 4
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default MOSIout <= 1'b0;
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endcase
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if (nRESout) case (LS[2:0])
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3'h3: MOSIout <= 1'b1; // Command bit 4
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3'h4: MOSIout <= 1'b0; // Address bit 20
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3'h5: MOSIout <= 1'b0; // Address bit 12
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3'h6: MOSIout <= 1'b0; // Address bit 4
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default MOSIout <= 1'b0;
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endcase else MOSIout <= RA[0];
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end 9: begin
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case (LS[2:0])
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3'h3: MOSIout <= 1'b1; // Command bit 3
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@ -309,6 +315,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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4'h1: RDD[7:0] <= Addr[15:8];
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4'h2: RDD[7:0] <= { SetEN24bit ? Addr[23:20] : 4'hF, Addr[19:16] };
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4'h3: RDD[7:0] <= SD[7:0];
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4'hF: RDD[7:0] <= { MISO, SD[6:0] };
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default: RDD[7:0] <= SD[7:0];
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endcase else RDD[7:0] <= SD[7:0];
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end
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@ -405,7 +412,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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nRCS <= !RCKE;
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nRAS <= 0;
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nCAS <= 0;
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nSWE <= ~(IS==1);
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nSWE <= !(IS==1);
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SDOE <= 0;
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end default: begin // NOP CKD
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RCKE <= 0;
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@ -434,27 +441,30 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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DQML <= 1'b1;
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DQMH <= 1'b1;
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if (IS==6) begin
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SBA[1:0] <= { 2'b10 };
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SBA[1:0] <= 2'b10;
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SA[12:0] <= { 10'b0011000100, LS[12:10] };
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end else if (nIOSEL && nIOSTRB) begin
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SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
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SA[12:10] <= SetEN24bit ? Addr[22:20] : 3'b000;
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SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[22] : 1'b0 };
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SA[12:10] <= SetEN24bit ? { Addr[23], Addr[21:20] } : 3'b000;
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SA[9:0] <= Addr[19:10];
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end else begin
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end else if (!nIOSTRB) begin
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SBA[1:0] <= 2'b10;
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SA[12:0] <= { 10'b0011000100, Bank, RA[11:10] };
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SA[12:0] <= { 10'b0011000100, Bank, 1'b1, RA[10] };
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end else begin // IOSEL
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SBA[1:0] <= 2'b10;
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SA[12:0] <= { 10'b0011000100, !RestoreDone, 1'b0, RA[10] };
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end
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end 2: begin // RD
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if (nIOSEL && nIOSTRB) begin
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SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
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SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[22] : 1'b0 };
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SA[12:0] <= { 4'b0011, Addr[9:1] };
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DQML <= Addr[0];
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DQMH <= ~Addr[0];
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DQMH <= !Addr[0];
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end else begin
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SBA[1:0] <= 2'b10;
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SA[12:0] <= { 4'b0011, RA[9:1]};
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DQML <= RA[0];
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DQMH <= ~RA[0];
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DQMH <= !RA[0];
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end
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end 3: begin // NOP CKE
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DQML <= 1'b1;
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@ -486,12 +496,12 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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SBA[1:0] <= 2'b10;
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SA[12:0] <= { 4'b0011, LS[9:1] };
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DQML <= LS[0];
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DQMH <= ~LS[0];
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DQMH <= !LS[0];
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end else begin
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SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
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SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[22] : 1'b0 };
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SA[12:0] <= { 4'b0011, Addr[9:1] };
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DQML <= Addr[0];
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DQMH <= ~Addr[0];
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DQMH <= !Addr[0];
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end
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end 9: begin // NOP CKE
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DQML <= 1'b1;
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