Apple-2-HW/GR8RAM
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Add SPI

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This commit is contained in:
Zane Kaminski 2023-04-14 01:53:39 -04:00
parent 78ff51995b
commit b406b1da16
1 changed files with 58 additions and 48 deletions
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86
cpld/GR8RAM.v
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@ -19,7 +19,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
/* Firmware select */
input [1:0] SetFW;
wire [1:0] SetROM = ~SetFW[1:0];
wire SetEN16MB = 0;//SetROM[1:0]==2'b11;
wire SetENRestore = SetROM[1:0]==1'b11;
wire SetEN24bit = SetROM[1];
/* State counter from PHI0 rising edge */
@ -58,8 +58,10 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
always @(posedge PHI0) CXXXr <= RA[15:12]==4'hC;
/* Apple select signals */
wire RAMExists = (~SetEN24bit || SetEN16MB || ~Addr[23]);
wire RAMExists = (!SetEN24bit || !Addr[23] || Addr[22] || Addr[21]);
wire BankSEL = REGEN && !nDEVSEL && RA[3:0]==4'hF;
wire SPITX1SEL = REGEN && !nDEVSEL && RA[3:0]==4'hD;
wire SPITX0SEL = REGEN && !nDEVSEL && RA[3:0]==4'hC;
wire RAMSEL = REGEN && !nDEVSEL && RA[3:0]==4'h3;
wire AddrHSEL = REGEN && !nDEVSEL && RA[3:0]==4'h2;
wire AddrMSEL = REGEN && !nDEVSEL && RA[3:0]==4'h1;
@ -78,7 +80,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
reg REGEN = 0;
always @(posedge C25M, negedge nRESr) begin
if (!nRESr) REGEN <= 0;
else if (!nIOSEL) REGEN <= 1;
else if (PS==8 && !nIOSEL) REGEN <= 1;
end
/* Apple data bus */
@ -104,7 +106,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
if (PS==8 && AddrLSEL && !nWE) begin
Addr[7:0] <= RD[7:0];
AddrIncM <= Addr[7] && ~RD[7];
AddrIncM <= Addr[7] && !RD[7];
end else if (AddrIncL) begin
Addr[7:0] <= Addr[7:0]+1;
AddrIncM <= Addr[7:0]==8'hFF;
@ -112,7 +114,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
if (PS==8 && AddrMSEL && !nWE) begin
Addr[15:8] <= RD[7:0];
AddrIncH <= Addr[15] && ~RD[7];
AddrIncH <= Addr[15] && !RD[7];
end else if (AddrIncM) begin
Addr[15:8] <= Addr[15:8]+1;
AddrIncH <= Addr[15:8]==8'hFF;
@ -126,22 +128,27 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
end
end
/* ROM bank register and restore state */
reg Bank = 0;
reg RestoreDone = 0;
/* ROM bank register */
reg Bank;
always @(posedge C25M, negedge nRESr) begin
if (~nRESr) Bank <= 0;
if (!nRESr) Bank <= 0;
else if (PS==8 && BankSEL && !nWE) begin
Bank <= RD[0];
if (RD[0]) RestoreDone <= 1;
end
end
/* Restore state */
reg RestoreDone = 0;
always @(posedge C25M) begin
if (!SetENRestore) RestoreDone <= 1;
else if (PS==8 && BankSEL && !nWE) begin
if (RD[1:0]==2'b11) RestoreDone <= 1;
end
end
/* SPI flash control signals */
output nFCS = FCKOE ? ~FCS : 1'bZ;
reg FCS = 0;
output FCK = FCKOE ? FCKout : 1'bZ;
reg FCKOE = 0;
output reg nFCS = 1;
output FCK = FCKout;
reg FCKout = 0;
inout MOSI = MOSIOE ? MOSIout : 1'bZ;
reg MOSIOE = 0;
@ -151,40 +158,39 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
0: begin // NOP CKE
FCKout <= 1'b1;
end 1: begin // ACT
FCKout <= ~(IS==5 || IS==6);
FCKout <= !(IS==5 || IS==6);
end 2: begin // RD
FCKout <= 1'b1;
end 3: begin // NOP CKE
FCKout <= ~(IS==5 || IS==6);
FCKout <= !(IS==5 || IS==6);
end 4: begin // NOP CKE
FCKout <= 1'b1;
end 5: begin // NOP CKE
FCKout <= ~(IS==5 || IS==6);
FCKout <= !(IS==5 || IS==6);
end 6: begin // NOP CKE
FCKout <= 1'b1;
end 7: begin // NOP CKE
FCKout <= ~(IS==5 || IS==6);
FCKout <= !(IS==5 || IS==6 || (!RestoreDone && SetENRestore && (SPITX0SEL || SPITX1SEL)));
end 8: begin // WR AP
FCKout <= 1'b1;
end 9: begin // NOP CKE
FCKout <= ~(IS==5);
FCKout <= !(IS==5);
end 10: begin // PC all
FCKout <= 1'b1;
end 11: begin // AREF
FCKout <= ~(IS==5);
FCKout <= !(IS==5);
end 12: begin // NOP CKE
FCKout <= 1'b1;
end 13: begin // NOP CKE
FCKout <= ~(IS==5);
FCKout <= !(IS==5);
end 14: begin // NOP CKE
FCKout <= 1'b1;
end 15: begin // NOP CKE
FCKout <= ~(IS==5);
FCKout <= !(IS==5);
end
endcase
FCS <= IS==4 || IS==5 || IS==6;
nFCS <= !(IS==4 || IS==5 || IS==6);
MOSIOE <= IS==5;
FCKOE <= IS==1 || IS==4 || IS==5 || IS==6 || IS==7;
end
/* SPI flash MOSI control */
@ -216,13 +222,13 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
default MOSIout <= 1'b0;
endcase
end 7: begin
case (LS[2:0])
if (nRESout) case (LS[2:0])
3'h3: MOSIout <= 1'b1; // Command bit 4
3'h4: MOSIout <= 1'b0; // Address bit 20
3'h5: MOSIout <= 1'b0; // Address bit 12
3'h6: MOSIout <= 1'b0; // Address bit 4
default MOSIout <= 1'b0;
endcase
endcase else MOSIout <= RA[0];
end 9: begin
case (LS[2:0])
3'h3: MOSIout <= 1'b1; // Command bit 3
@ -309,6 +315,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
4'h1: RDD[7:0] <= Addr[15:8];
4'h2: RDD[7:0] <= { SetEN24bit ? Addr[23:20] : 4'hF, Addr[19:16] };
4'h3: RDD[7:0] <= SD[7:0];
4'hF: RDD[7:0] <= { MISO, SD[6:0] };
default: RDD[7:0] <= SD[7:0];
endcase else RDD[7:0] <= SD[7:0];
end
@ -405,7 +412,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
nRCS <= !RCKE;
nRAS <= 0;
nCAS <= 0;
nSWE <= ~(IS==1);
nSWE <= !(IS==1);
SDOE <= 0;
end default: begin // NOP CKD
RCKE <= 0;
@ -434,27 +441,30 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
DQML <= 1'b1;
DQMH <= 1'b1;
if (IS==6) begin
SBA[1:0] <= { 2'b10 };
SBA[1:0] <= 2'b10;
SA[12:0] <= { 10'b0011000100, LS[12:10] };
end else if (nIOSEL && nIOSTRB) begin
SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
SA[12:10] <= SetEN24bit ? Addr[22:20] : 3'b000;
SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[22] : 1'b0 };
SA[12:10] <= SetEN24bit ? { Addr[23], Addr[21:20] } : 3'b000;
SA[9:0] <= Addr[19:10];
end else begin
end else if (!nIOSTRB) begin
SBA[1:0] <= 2'b10;
SA[12:0] <= { 10'b0011000100, Bank, RA[11:10] };
SA[12:0] <= { 10'b0011000100, Bank, 1'b1, RA[10] };
end else begin // IOSEL
SBA[1:0] <= 2'b10;
SA[12:0] <= { 10'b0011000100, !RestoreDone, 1'b0, RA[10] };
end
end 2: begin // RD
if (nIOSEL && nIOSTRB) begin
SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[22] : 1'b0 };
SA[12:0] <= { 4'b0011, Addr[9:1] };
DQML <= Addr[0];
DQMH <= ~Addr[0];
DQMH <= !Addr[0];
end else begin
SBA[1:0] <= 2'b10;
SA[12:0] <= { 4'b0011, RA[9:1]};
DQML <= RA[0];
DQMH <= ~RA[0];
DQMH <= !RA[0];
end
end 3: begin // NOP CKE
DQML <= 1'b1;
@ -486,12 +496,12 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
SBA[1:0] <= 2'b10;
SA[12:0] <= { 4'b0011, LS[9:1] };
DQML <= LS[0];
DQMH <= ~LS[0];
DQMH <= !LS[0];
end else begin
SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[22] : 1'b0 };
SA[12:0] <= { 4'b0011, Addr[9:1] };
DQML <= Addr[0];
DQMH <= ~Addr[0];
DQMH <= !Addr[0];
end
end 9: begin // NOP CKE
DQML <= 1'b1;