Apple-2-HW/GR8RAM
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4 Commits

Author SHA1 Message Date
Zane Kaminski
79dd794f45 New PLD revision 
For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
 2019-10-18 15:07:38 -04:00
Zane Kaminski
1bf5ce4be3 New schematic revision 2019-10-13 01:40:49 -04:00
Zane Kaminski
029354ce8e Submitted to JLCPCB 2019-07-30 17:11:31 -04:00
Zane Kaminski
fb35d7bd9b Release candidate PCB 2019-07-21 17:53:22 -04:00