mirror of
https://github.com/garrettsworkshop/GR8RAM.git
synced 2024-05-31 17:41:34 +00:00
541 lines
14 KiB
Verilog
541 lines
14 KiB
Verilog
module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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INTin, INTout, DMAin, DMAout,
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GNDout1, GNDout2, nIRQout, RWout, nDMAout,
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RA, PU, nWE, RD, RAdir, RDdir, nIOSEL, nDEVSEL, nIOSTRB,
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SBA, SA, nRCS, nRAS, nCAS, nSWE, DQML, DQMH, RCKE, SD,
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nFCS, FCK, MISO, MOSI);
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/* Clock signals */
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input C25M, PHI0;
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/* PHI0 synchronization to 25 MHz clock */
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reg [2:0] PHI0r;
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always @(posedge C25M) PHI0r <= { PHI0r[1:0], PHI0 };
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/* Reset synchronization */
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input nRES; reg nRESr = 0;
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always @(posedge C25M) begin
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if (PS==15) nRESr <= nRES;
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end
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/* Firmware select */
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input [1:0] SetFW;
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wire [1:0] SetROM = ~SetFW[1:0];
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wire SetENRestore = SetROM[1:0]==2'b11;
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wire SetEN24bit = SetROM[1];
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/* State counter from PHI0 rising edge */
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reg [3:0] PS = 0;
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wire PSStart = PS==0 && PHI0r[0] && !PHI0r[1];
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always @(posedge C25M) begin
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if (PSStart) PS <= 1;
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else if (PS==0) PS <= 0;
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else PS <= PS+1;
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end
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/* Long state counter: counts from 0 to $3FFF */
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reg [13:0] LS = 0;
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always @(posedge C25M) begin if (PS==15) LS <= LS+1; end
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/* Init state */
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output reg nRESout = 0;
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reg [2:0] IS = 0;
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always @(posedge C25M) begin
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if (IS==7) nRESout <= 1;
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else if (PS==15) begin
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if (LS==14'h1FCE) IS <= 1; // PC all + load mode
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else if (LS==14'h1FCF) IS <= 4; // AREF pause, SPI select
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else if (LS==14'h1FFA) IS <= 5; // SPI flash command
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else if (LS==14'h1FFF) IS <= 6; // Flash load driver
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else if (LS==14'h3FFF) IS <= 7; // Operating mode
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end
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end
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/* Apple IO area select signals */
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input nIOSEL, nDEVSEL, nIOSTRB;
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/* Apple address bus */
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input [15:0] RA;
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input nWE;
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input PU;
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wire RA4 = RA[4] && PU;
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/* Apple select signals */
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wire RAMExists = !SetEN24bit || !Addr[23] ;
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wire BankSEL = REGEN && !nDEVSEL && RA[3:0]==4'hF;
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wire SPITXSEL = REGEN && !nDEVSEL && (RA[3:0]==4'hC || RA[3:0]==4'hD) &&
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!RestoreDone && SetENRestore;
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wire RAMSEL = REGEN && !nDEVSEL && RA[3:0]==4'h3;
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wire AddrHSEL = REGEN && !nDEVSEL && RA[3:0]==4'h2;
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wire AddrMSEL = REGEN && !nDEVSEL && RA[3:0]==4'h1;
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wire AddrLSEL = REGEN && !nDEVSEL && RA[3:0]==4'h0;
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/* Slot number detect */
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reg SlotKnown = 0;
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reg [2:0] Slot;
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always @(negedge PHI0) begin
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if (!nIOSEL) begin
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SlotKnown <= 1;
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Slot <= RA[10:8];
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end
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end
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/* RAM/ROM speculative select */
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wire RAMSpecSEL = RA[15:8]==8'hC0 && RA[7] && RA[3:0]==4'h3 && REGEN;
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wire IOSELSpecSEL = RA[15:12]==4'hC && !RA[11] && (RA[10:8]==Slot[2:0] || !SlotKnown);
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wire IOSTRBSpecSEL = RA[15:12]==4'hC && RA[11] && IOROMEN;
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wire RAMROMSpecSEL = RAMSpecSEL || IOSELSpecSEL || IOSTRBSpecSEL;
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reg RAMROMSpecSELr; always @(posedge PHI0) RAMROMSpecSELr <= RAMROMSpecSEL;
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/* IOROMEN control */
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reg IOROMEN = 0;
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wire IOROMRES = !nIOSTRB && RA[10:0]==11'h7FF;
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always @(posedge C25M, posedge IOROMRES) begin
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if (IOROMRES) IOROMEN <= 0;
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else if (!nRESr) IOROMEN <= 0;
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else if (!nIOSEL) IOROMEN <= 1;
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end
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/* REGEN control */
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reg REGEN = 0;
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always @(posedge C25M, negedge nRESr) begin
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if (!nRESr) REGEN <= 0;
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else if (PS==8 && !nIOSEL) REGEN <= 1;
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end
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/* Apple data bus */
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wire RDOEbase = PHI0 && nWE &&
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((!nDEVSEL && RAMExists) || !nIOSEL || (!nIOSTRB && IOROMEN));
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reg [7:0] RDD;
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inout [7:0] RD = (RDOEbase && PHI0r[2]) ? RDD[7:0] : 8'bZ;
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output RDdir = !(RDOEbase && PHI0r[1]);
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/* Slinky address registers */
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reg [23:0] Addr = 0;
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reg AddrIncL = 0;
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reg AddrIncM = 0;
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reg AddrIncH = 0;
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always @(posedge C25M, negedge nRESr) begin
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if (!nRESr) begin
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Addr[23:0] <= 24'h000000;
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end else begin
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if (PS==8 && RAMSEL) AddrIncL <= 1;
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else AddrIncL <= 0;
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if (PS==8 && AddrLSEL && !nWE) begin
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Addr[7:0] <= RD[7:0];
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AddrIncM <= Addr[7] && !RD[7];
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end else if (AddrIncL) begin
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Addr[7:0] <= Addr[7:0]+1;
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AddrIncM <= Addr[7:0]==8'hFF;
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end else AddrIncM <= 0;
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if (PS==8 && AddrMSEL && !nWE) begin
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Addr[15:8] <= RD[7:0];
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AddrIncH <= Addr[15] && !RD[7];
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end else if (AddrIncM) begin
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Addr[15:8] <= Addr[15:8]+1;
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AddrIncH <= Addr[15:8]==8'hFF;
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end else AddrIncH <= 0;
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if (PS==8 && AddrHSEL && !nWE) begin
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Addr[23:16] <= RD[7:0];
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end else if (AddrIncH) begin
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Addr[23:16] <= Addr[23:16]+1;
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end
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end
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end
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/* ROM bank register */
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reg Bank;
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always @(negedge PHI0, negedge nRESr) begin
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if (!nRESr) Bank <= 0;
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else if (BankSEL && !nWE) Bank <= RD[0];
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end
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/* Restore state */
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reg RestoreDone = 0;
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always @(negedge PHI0, negedge SetENRestore) begin
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if (!SetENRestore) RestoreDone <= 1;
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else if (BankSEL && !nWE && RD[1]) RestoreDone <= 1;
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end
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/* Flash chip select register */
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reg FCS = 0;
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always @(negedge PHI0, posedge RestoreDone) begin
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if (RestoreDone) FCS <= 0;
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else if (BankSEL && !nWE) FCS <= RD[0];
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end
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/* SPI flash control signals */
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output reg nFCS = 1;
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reg FCKout; output FCK = FCKout;
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inout MOSI = MOSIOE ? MOSIout : 1'bZ;
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reg MOSIOE;
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input MISO;
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always @(posedge C25M) begin
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case (PS[3:0])
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0: FCKout <= 1'b1; // NOP CKE
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1: FCKout <= !(IS==5 || IS==6); // ACT
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2: FCKout <= 1'b1; // RD
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3: FCKout <= !(IS==5 || IS==6); // NOP CKE
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4: FCKout <= 1'b1; // NOP CKE
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5: FCKout <= !(IS==5 || IS==6); // NOP CKE
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6: FCKout <= 1'b1; // NOP CKE
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7: FCKout <= !(IS==5 || IS==6 || SPITXSEL); // NOP CKE
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8: FCKout <= 1'b1; // WR AP
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9: FCKout <= !(IS==5); // NOP CKE
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10: FCKout <= 1'b1; // PC all
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11: FCKout <= !(IS==5); // AREF
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12: FCKout <= 1'b1; // NOP CKE
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13: FCKout <= !(IS==5); // NOP CKE
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14: FCKout <= 1'b1; // NOP CKE
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15: FCKout <= !(IS==5); // NOP CKE
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endcase
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nFCS <= !(IS==4 || IS==5 || IS==6 || FCS);
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MOSIOE <= IS==5 || (IS==7 && SetENRestore && !RestoreDone);
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end
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/* SPI flash MOSI control */
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reg MOSIout = 0;
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always @(posedge C25M) begin
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case (PS[3:0])
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1: case (LS[1:0])
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2'h3: MOSIout <= 1'b0; // Command bit 7
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2'h0: MOSIout <= 1'b0; // Address bit 23
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2'h1: MOSIout <= 1'b0; // Address bit 15
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2'h2: MOSIout <= 1'b0; // Address bit 7
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endcase 3: case (LS[1:0])
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2'h3: MOSIout <= 1'b0; // Command bit 6
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2'h0: MOSIout <= 1'b0; // Address bit 22
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2'h1: MOSIout <= SetROM[1]; // Address bit 14
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2'h2: MOSIout <= 1'b0; // Address bit 6
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endcase 5: case (LS[1:0])
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2'h3: MOSIout <= 1'b1; // Command bit 5
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2'h0: MOSIout <= 1'b0; // Address bit 21
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2'h1: MOSIout <= SetROM[0]; // Address bit 13
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2'h2: MOSIout <= 1'b0; // Address bit 5
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endcase 7: begin
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if (!nRESout) case (LS[1:0])
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2'h3: MOSIout <= 1'b1; // Command bit 4
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2'h0: MOSIout <= 1'b0; // Address bit 20
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2'h1: MOSIout <= 1'b0; // Address bit 12
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2'h2: MOSIout <= 1'b0; // Address bit 4
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endcase else MOSIout <= RA[0];
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end 9: case (LS[1:0])
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2'h3: MOSIout <= 1'b1; // Command bit 3
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2'h0: MOSIout <= 1'b0; // Address bit 19
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2'h1: MOSIout <= 1'b0; // Address bit 11
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2'h2: MOSIout <= 1'b0; // Address bit 3
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endcase 11: case (LS[1:0])
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2'h3: MOSIout <= 1'b0; // Command bit 2
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2'h0: MOSIout <= 1'b0; // Address bit 18
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2'h1: MOSIout <= 1'b0; // Address bit 10
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2'h2: MOSIout <= 1'b0; // Address bit 2
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endcase 13: case (LS[1:0])
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2'h3: MOSIout <= 1'b1; // Command bit 1
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2'h0: MOSIout <= 1'b0; // Address bit 16
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2'h1: MOSIout <= 1'b0; // Address bit 9
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2'h2: MOSIout <= 1'b0; // Address bit 1
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endcase 15: case (LS[1:0])
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2'h3: MOSIout <= 1'b1; // Command bit 0
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2'h0: MOSIout <= 1'b0; // Address bit 15
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2'h1: MOSIout <= 1'b0; // Address bit 7
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2'h2: MOSIout <= 1'b0; // Address bit 0
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endcase
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endcase
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end
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/* SDRAM data bus */
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inout [7:0] SD = SDOE ? WRD[7:0] : 8'bZ;
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reg [7:0] WRD;
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reg SDOE = 0;
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always @(posedge C25M) begin
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case (PS[3:0])
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0: begin // NOP CKE
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if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
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else WRD[7:0] <= RD[7:0];
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end 1: begin // ACT
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end 2: begin // RD
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if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
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else WRD[7:0] <= RD[7:0];
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end 3: begin // NOP CKE
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end 4: begin // NOP CKE
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if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
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else WRD[7:0] <= RD[7:0];
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end 5: begin // NOP CKE
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end 6: begin // NOP CKE
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if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
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else WRD[7:0] <= RD[7:0];
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end 7: begin // NOP CKE
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end 8: begin // WR AP
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if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
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else WRD[7:0] <= RD[7:0];
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end 9: begin // NOP CKE
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end 10: begin // PC all
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if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
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else WRD[7:0] <= RD[7:0];
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end 11: begin // AREF
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end 12: begin // NOP CKE
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if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
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else WRD[7:0] <= RD[7:0];
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end 13: begin // NOP CKE
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end 14: begin // NOP CKE
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if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
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else WRD[7:0] <= RD[7:0];
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end 15: begin // NOP CKE
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end
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endcase
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end
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/* Apple data bus from SDRAM */
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always @(negedge C25M) begin
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if (PS==5) begin
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if (!nDEVSEL) case (RA[3:0])
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4'h0: RDD[7:0] <= Addr[7:0];
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4'h1: RDD[7:0] <= Addr[15:8];
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4'h2: RDD[7:0] <= { SetEN24bit ? Addr[23:20] : 4'hF, Addr[19:16] };
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4'h3: RDD[7:0] <= SD[7:0];
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4'hF: RDD[7:0] <= { MISO, SD[6:0] };
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default: RDD[7:0] <= SD[7:0];
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endcase else RDD[7:0] <= SD[7:0];
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end
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end
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/* SDRAM command */
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output reg RCKE = 1;
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output reg nRCS = 1;
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output reg nRAS = 1;
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output reg nCAS = 1;
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output reg nSWE = 1;
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wire RefReqd = LS[1:0] == 2'b11;
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always @(posedge C25M) begin
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case (PS[3:0])
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0: begin // NOP CKE / NOP CKD
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RCKE <= PSStart && (IS==6 || (IS==7 && RAMROMSpecSELr));
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nRCS <= 1;
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nRAS <= 1;
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nCAS <= 1;
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nSWE <= 1;
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SDOE <= 0;
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end 1: begin // ACT CKE / NOP CKD (ACT)
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RCKE <= RCKE;
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nRCS <= !RCKE;
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nRAS <= 0;
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nCAS <= 1;
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nSWE <= 1;
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SDOE <= 0;
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end 2: begin // RD CKE / NOP CKD (RD)
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RCKE <= RCKE;
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nRCS <= !RCKE;
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nRAS <= 1;
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nCAS <= 0;
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nSWE <= 1;
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SDOE <= 0;
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end 3: begin // NOP CKE / CKD
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RCKE <= RCKE;
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nRCS <= 1;
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nRAS <= 1;
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nCAS <= 1;
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nSWE <= 1;
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SDOE <= 0;
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end 4: begin // NOP CKD
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RCKE <= 0;
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nRCS <= 1;
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nRAS <= 1;
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nCAS <= 1;
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nSWE <= 1;
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SDOE <= 0;
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end 5: begin // NOP CKD
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RCKE <= 0;
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nRCS <= 1;
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nRAS <= 1;
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nCAS <= 1;
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nSWE <= 1;
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SDOE <= 0;
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end 6: begin // NOP CKD
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RCKE <= 0;
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nRCS <= 1;
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nRAS <= 1;
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nCAS <= 1;
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nSWE <= 1;
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SDOE <= 0;
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end 7: begin // NOP CKE / CKD
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RCKE <= IS==6 || (RAMSEL && !nWE && IS==7);
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nRCS <= 1;
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nRAS <= 1;
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nCAS <= 1;
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nSWE <= 1;
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SDOE <= 0;
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end 8: begin // WR AP CKE / NOP CKD (WR AP)
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RCKE <= RCKE;
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nRCS <= !RCKE;
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nRAS <= 1;
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nCAS <= 0;
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nSWE <= 0;
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SDOE <= RCKE;
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end 9: begin // NOP CKE / NOP CKD
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RCKE <= 1;
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nRCS <= 1;
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nRAS <= 1;
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nCAS <= 1;
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nSWE <= 1;
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SDOE <= 0;
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end 10: begin // PC all CKE / PC all CKD
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RCKE <= IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd);
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nRCS <= 0;
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nRAS <= 0;
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nCAS <= 1;
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nSWE <= 0;
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SDOE <= 0;
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end 11: begin // LDM CKE / AREF CKE / NOP CKD
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RCKE <= RCKE;
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nRCS <= !RCKE;
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nRAS <= 0;
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nCAS <= 0;
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nSWE <= !(IS==1);
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SDOE <= 0;
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end default: begin // NOP CKD
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RCKE <= 0;
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nRCS <= 1;
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nRAS <= 1;
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nCAS <= 1;
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nSWE <= 1;
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SDOE <= 0;
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end
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endcase
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end
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/* SDRAM address */
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output reg DQML = 1;
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output reg DQMH = 1;
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output reg [1:0] SBA;
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output reg [12:0] SA;
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always @(posedge C25M) begin
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case (PS[3:0])
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0: begin // NOP CKE
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DQML <= 1'b1;
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DQMH <= 1'b1;
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SBA[1:0] <= 2'b00;
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SA[12:0] <= 13'b0011000100000;
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end 1: begin // ACT
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DQML <= 1'b1;
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DQMH <= 1'b1;
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if (IS==6) begin
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SBA[1:0] <= 2'b10;
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SA[12:0] <= { 10'b0011000100, LS[12:10] };
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end else if (nIOSEL && nIOSTRB) begin
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SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[22] : 1'b0 };
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SA[12:10] <= SetEN24bit ? { 1'b0, Addr[21:20] } : 3'b000;
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SA[9:0] <= Addr[19:10];
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end else if (!nIOSTRB) begin
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SBA[1:0] <= 2'b10;
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|
SA[12:0] <= { 10'b0011000100, Bank, 1'b1, RA[10] };
|
|
end else begin // IOSEL
|
|
SBA[1:0] <= 2'b10;
|
|
SA[12:0] <= { 10'b0011000100, !RestoreDone, 1'b0, RA[10] };
|
|
end
|
|
end 2: begin // RD
|
|
if (nIOSEL && nIOSTRB) begin
|
|
SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[22] : 1'b0 };
|
|
SA[12:0] <= { 4'b0011, Addr[9:1] };
|
|
DQML <= Addr[0];
|
|
DQMH <= !Addr[0];
|
|
end else begin
|
|
SBA[1:0] <= 2'b10;
|
|
SA[12:0] <= { 4'b0011, RA[9:5], RA4, RA[3:1]};
|
|
DQML <= RA[0];
|
|
DQMH <= !RA[0];
|
|
end
|
|
end 3: begin // NOP CKE
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= 13'b0011000100000;
|
|
end 4: begin // NOP CKE
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= 13'b0011000100000;
|
|
end 5: begin // NOP CKE
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= 13'b0011000100000;
|
|
end 6: begin // NOP CKE
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= 13'b0011000100000;
|
|
end 7: begin // NOP CKE
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= 13'b0011000100000;
|
|
end 8: begin // WR AP
|
|
if (IS==6) begin
|
|
SBA[1:0] <= 2'b10;
|
|
SA[12:0] <= { 4'b0011, LS[9:1] };
|
|
DQML <= LS[0];
|
|
DQMH <= !LS[0];
|
|
end else begin
|
|
SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[22] : 1'b0 };
|
|
SA[12:0] <= { 4'b0011, Addr[9:1] };
|
|
DQML <= Addr[0];
|
|
DQMH <= !Addr[0];
|
|
end
|
|
end 9: begin // NOP CKE
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= 13'b0011000100000;
|
|
end 10: begin // PC all
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= 13'b0011000100000;
|
|
end 11: begin // AREF / load mode
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= 13'b0001000100000;
|
|
end 12: begin // NOP CKE
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= 13'b0011000100000;
|
|
end 13: begin // NOP CKE
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= 13'b0011000100000;
|
|
end 14: begin // NOP CKE
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= 13'b0011000100000;
|
|
end 15: begin // NOP CKE
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= 13'b0011000100000;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
/* DMA/INT in/out */
|
|
input INTin, DMAin;
|
|
output INTout = INTin;
|
|
output DMAout = DMAin;
|
|
|
|
/* Unused Pins */
|
|
output RAdir = 1;
|
|
output nDMAout = 1;
|
|
output nIRQout = 1;
|
|
output RWout = 1;
|
|
|
|
/* Grounds next to PU */
|
|
output GNDout1 = 0;
|
|
output GNDout2 = 0;
|
|
endmodule
|