GR8RAM/cpld/output_files/GR8RAM.flow.rpt
2023-02-28 11:23:37 -05:00

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Flow report for GR8RAM
Tue Feb 28 11:21:31 2023
Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
8. Flow Messages
9. Flow Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2022 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
+------------------------------------------------------------------------+
; Flow Summary ;
+-----------------------+------------------------------------------------+
; Flow Status ; Successful - Tue Feb 28 11:21:31 2023 ;
; Quartus Prime Version ; 22.1std.0 Build 915 10/25/2022 SC Lite Edition ;
; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ;
; Family ; MAX II ;
; Device ; EPM240T100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 233 / 240 ( 97 % ) ;
; Total pins ; 80 / 80 ( 100 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
+-----------------------+------------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 02/28/2023 11:20:54 ;
; Main task ; Compilation ;
; Revision Name ; GR8RAM ;
+-------------------+---------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+---------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+---------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; COMPILER_SIGNATURE_ID ; 121381084694.167760125411500 ; -- ; -- ; -- ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ;
; EDA_NETLIST_WRITER_OUTPUT_DIR ; simulation/questa ; -- ; -- ; eda_simulation ;
; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ;
; EDA_SIMULATION_TOOL ; Questa Intel FPGA (Verilog) ; <None> ; -- ; -- ;
; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
; IOBANK_VCCIO ; -- (Not supported for targeted family) ; -- ; -- ; 1 ;
; IOBANK_VCCIO ; -- (Not supported for targeted family) ; -- ; -- ; 2 ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
+---------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
+--------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:23 ; 1.0 ; 13114 MB ; 00:00:48 ;
; Fitter ; 00:00:06 ; 1.0 ; 13746 MB ; 00:00:05 ;
; Assembler ; 00:00:01 ; 1.0 ; 13099 MB ; 00:00:01 ;
; Timing Analyzer ; 00:00:02 ; 1.0 ; 13081 MB ; 00:00:01 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 13024 MB ; 00:00:01 ;
; Total ; 00:00:33 ; -- ; -- ; 00:00:56 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
+------------------------------------------------------------------------------------+
; Flow OS Summary ;
+----------------------+------------------+------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+----------------------+------------------+------------+------------+----------------+
; Analysis & Synthesis ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ;
; Fitter ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ;
; Assembler ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ;
; Timing Analyzer ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ;
; EDA Netlist Writer ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ;
+----------------------+------------------+------------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
quartus_sta GR8RAM -c GR8RAM
quartus_eda --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM