Apple-2-HW/GR8RAM
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GR8RAM/cpld/output_files
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Zane Kaminski 79dd794f45 New PLD revision 
For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 15:07:38 -04:00
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GR8RAM.asm.rpt New PLD revision 2019-10-18 15:07:38 -04:00
GR8RAM.cdf 1MB CPLD design seems to work, fails Apple BIST 2019-09-01 21:18:44 -04:00
GR8RAM.done New PLD revision 2019-10-18 15:07:38 -04:00
GR8RAM.fit.rpt New PLD revision 2019-10-18 15:07:38 -04:00
GR8RAM.fit.summary New PLD revision 2019-10-18 15:07:38 -04:00
GR8RAM.flow.rpt New PLD revision 2019-10-18 15:07:38 -04:00
GR8RAM.jdi New PLD revision 2019-10-18 15:07:38 -04:00
GR8RAM.map.rpt New PLD revision 2019-10-18 15:07:38 -04:00
GR8RAM.map.smsg New PLD revision 2019-10-18 15:07:38 -04:00
GR8RAM.map.summary New PLD revision 2019-10-18 15:07:38 -04:00
GR8RAM.pin New PLD revision 2019-10-18 15:07:38 -04:00
GR8RAM.pof New PLD revision 2019-10-18 15:07:38 -04:00
GR8RAM.sta.rpt New PLD revision 2019-10-18 15:07:38 -04:00
GR8RAM.sta.summary New PLD revision 2019-10-18 15:07:38 -04:00