mirror of
https://github.com/garrettsworkshop/GR8RAM.git
synced 2024-09-08 02:54:41 +00:00
79dd794f45
For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
8 lines
255 B
Plaintext
Executable File
8 lines
255 B
Plaintext
Executable File
Analysis & Synthesis Status : Successful - Fri Oct 18 15:01:54 2019
|
|
Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
|
|
Revision Name : GR8RAM
|
|
Top-level Entity Name : GR8RAM
|
|
Family : MAX7000S
|
|
Total macrocells : 105
|
|
Total pins : 61
|