mirror of
https://github.com/garrettsworkshop/GR8RAM.git
synced 2024-09-08 02:54:41 +00:00
228 lines
4.9 KiB
Plaintext
Executable File
228 lines
4.9 KiB
Plaintext
Executable File
|GR8RAM
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C25M => SA[0]~reg0.CLK
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C25M => SA[1]~reg0.CLK
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C25M => SA[2]~reg0.CLK
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C25M => SA[3]~reg0.CLK
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C25M => SA[4]~reg0.CLK
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C25M => SA[5]~reg0.CLK
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C25M => SA[6]~reg0.CLK
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C25M => SA[7]~reg0.CLK
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C25M => SA[8]~reg0.CLK
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C25M => SA[9]~reg0.CLK
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C25M => SA[10]~reg0.CLK
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C25M => SA[11]~reg0.CLK
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C25M => SA[12]~reg0.CLK
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C25M => SBA[0]~reg0.CLK
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C25M => SBA[1]~reg0.CLK
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C25M => DQMH~reg0.CLK
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C25M => DQML~reg0.CLK
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C25M => SDOE.CLK
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C25M => nSWE~reg0.CLK
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C25M => nCAS~reg0.CLK
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C25M => nRAS~reg0.CLK
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C25M => nRCS~reg0.CLK
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C25M => RCKE~reg0.CLK
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C25M => PS[0].CLK
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C25M => PS[1].CLK
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C25M => PS[2].CLK
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C25M => PS[3].CLK
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C25M => RDD[0].CLK
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C25M => RDD[1].CLK
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C25M => RDD[2].CLK
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C25M => RDD[3].CLK
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C25M => RDD[4].CLK
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C25M => RDD[5].CLK
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C25M => RDD[6].CLK
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C25M => RDD[7].CLK
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C25M => WRD[0].CLK
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C25M => WRD[1].CLK
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C25M => WRD[2].CLK
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C25M => WRD[3].CLK
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C25M => WRD[4].CLK
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C25M => WRD[5].CLK
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C25M => WRD[6].CLK
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C25M => WRD[7].CLK
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C25M => MOSIout.CLK
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C25M => FCKOE.CLK
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C25M => MOSIOE.CLK
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C25M => FCS.CLK
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C25M => FCKout.CLK
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C25M => Bank.CLK
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C25M => AddrIncH.CLK
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C25M => AddrIncM.CLK
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C25M => AddrIncL.CLK
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C25M => Addr[0].CLK
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C25M => Addr[1].CLK
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C25M => Addr[2].CLK
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C25M => Addr[3].CLK
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C25M => Addr[4].CLK
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C25M => Addr[5].CLK
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C25M => Addr[6].CLK
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C25M => Addr[7].CLK
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C25M => Addr[8].CLK
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C25M => Addr[9].CLK
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C25M => Addr[10].CLK
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C25M => Addr[11].CLK
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C25M => Addr[12].CLK
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C25M => Addr[13].CLK
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C25M => Addr[14].CLK
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C25M => Addr[15].CLK
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C25M => Addr[16].CLK
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C25M => Addr[17].CLK
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C25M => Addr[18].CLK
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C25M => Addr[19].CLK
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C25M => Addr[20].CLK
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C25M => Addr[21].CLK
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C25M => Addr[22].CLK
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C25M => Addr[23].CLK
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C25M => REGEN.CLK
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C25M => IOROMEN.CLK
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C25M => nRESout~reg0.CLK
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C25M => LS[0].CLK
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C25M => LS[1].CLK
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C25M => LS[2].CLK
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C25M => LS[3].CLK
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C25M => LS[4].CLK
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C25M => LS[5].CLK
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C25M => LS[6].CLK
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C25M => LS[7].CLK
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C25M => LS[8].CLK
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C25M => LS[9].CLK
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C25M => LS[10].CLK
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C25M => LS[11].CLK
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C25M => LS[12].CLK
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C25M => LS[13].CLK
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C25M => nRESr.CLK
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C25M => nRESr0.CLK
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C25M => PHI0r2.CLK
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C25M => PHI0r1.CLK
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C25M => IS~7.DATAIN
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PHI0 => comb.IN1
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PHI0 => nWEr.CLK
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PHI0 => RAMSpecSELr.CLK
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PHI0 => ROMSpecRDr.CLK
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PHI0 => PHI0r1.DATAIN
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nRES => nRESr0.DATAIN
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nRESout <= nRESout~reg0.DB_MAX_OUTPUT_PORT_TYPE
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SetFW[0] => ~NO_FANOUT~
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SetFW[1] => ~NO_FANOUT~
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RAdir <= <VCC>
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INTin => INTout.DATAIN
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INTout <= INTin.DB_MAX_OUTPUT_PORT_TYPE
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DMAin => DMAout.DATAIN
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DMAout <= DMAin.DB_MAX_OUTPUT_PORT_TYPE
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nDMAout <= <VCC>
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nNMIout <= <VCC>
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nIRQout <= <VCC>
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nRDYout <= <VCC>
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nINHout <= <VCC>
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RWout <= <VCC>
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nIOSEL => comb.IN0
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nIOSEL => always5.IN1
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nDEVSEL => comb.IN1
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nDEVSEL => RAMSEL.IN1
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nDEVSEL => comb.IN1
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nIOSTRB => comb.IN1
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nIOSTRB => always5.IN1
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RA[0] => DQML.DATAA
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RA[0] => Equal6.IN3
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RA[0] => Equal9.IN1
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RA[0] => Equal10.IN3
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RA[0] => Equal11.IN0
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RA[0] => Equal12.IN3
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RA[0] => Equal13.IN10
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RA[0] => DQMH.DATAA
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RA[1] => SA.DATAA
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RA[1] => Equal6.IN2
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RA[1] => Equal9.IN0
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RA[1] => Equal10.IN0
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RA[1] => Equal11.IN3
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RA[1] => Equal12.IN2
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RA[1] => Equal13.IN9
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RA[2] => SA.DATAA
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RA[2] => Equal6.IN1
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RA[2] => Equal9.IN3
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RA[2] => Equal10.IN2
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RA[2] => Equal11.IN2
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RA[2] => Equal12.IN1
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RA[2] => Equal13.IN8
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RA[3] => SA.DATAA
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RA[3] => Equal6.IN0
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RA[3] => Equal9.IN2
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RA[3] => Equal10.IN1
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RA[3] => Equal11.IN1
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RA[3] => Equal12.IN0
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RA[3] => Equal13.IN7
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RA[4] => SA.DATAA
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RA[4] => Equal13.IN6
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RA[5] => SA.DATAA
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RA[5] => Equal13.IN5
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RA[6] => SA.DATAA
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RA[6] => Equal13.IN4
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RA[7] => comb.IN1
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RA[7] => SA.DATAA
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RA[7] => Equal13.IN3
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RA[8] => SA.DATAA
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RA[8] => Equal8.IN3
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RA[8] => Equal13.IN2
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RA[9] => SA.DATAA
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RA[9] => Equal8.IN2
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RA[9] => Equal13.IN1
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RA[10] => SA.DATAA
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RA[10] => Equal8.IN1
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RA[10] => Equal13.IN0
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RA[11] => SA.DATAA
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RA[11] => Equal8.IN0
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RA[12] => Equal7.IN3
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RA[13] => Equal7.IN2
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RA[14] => Equal7.IN1
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RA[15] => Equal7.IN0
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nWE => ROMSpecRD.IN1
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nWE => comb.IN1
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nWE => nWEr.DATAIN
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RD[0] <> RD[0]
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RD[1] <> RD[1]
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RD[2] <> RD[2]
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RD[3] <> RD[3]
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RD[4] <> RD[4]
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RD[5] <> RD[5]
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RD[6] <> RD[6]
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RD[7] <> RD[7]
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RDdir <= comb.DB_MAX_OUTPUT_PORT_TYPE
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SBA[0] <= SBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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SBA[1] <= SBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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SA[0] <= SA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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SA[1] <= SA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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SA[2] <= SA[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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SA[3] <= SA[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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SA[4] <= SA[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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SA[5] <= SA[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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SA[6] <= SA[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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SA[7] <= SA[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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SA[8] <= SA[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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SA[9] <= SA[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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SA[10] <= SA[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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SA[11] <= SA[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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SA[12] <= SA[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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nRCS <= nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE
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nRAS <= nRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
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nCAS <= nCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
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nSWE <= nSWE~reg0.DB_MAX_OUTPUT_PORT_TYPE
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DQML <= DQML~reg0.DB_MAX_OUTPUT_PORT_TYPE
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DQMH <= DQMH~reg0.DB_MAX_OUTPUT_PORT_TYPE
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RCKE <= RCKE~reg0.DB_MAX_OUTPUT_PORT_TYPE
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SD[0] <> SD[0]
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SD[1] <> SD[1]
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SD[2] <> SD[2]
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SD[3] <> SD[3]
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SD[4] <> SD[4]
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SD[5] <> SD[5]
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SD[6] <> SD[6]
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SD[7] <> SD[7]
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nFCS <= nFCS.DB_MAX_OUTPUT_PORT_TYPE
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FCK <= FCK.DB_MAX_OUTPUT_PORT_TYPE
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MISO => WRD.DATAB
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MOSI <> MOSI
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