mirror of
https://github.com/garrettsworkshop/GR8RAM.git
synced 2024-11-04 14:05:00 +00:00
323 lines
24 KiB
Plaintext
Executable File
323 lines
24 KiB
Plaintext
Executable File
Analysis & Synthesis report for GR8RAM
|
|
Tue Apr 20 04:19:44 2021
|
|
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
|
|
|
|
|
---------------------
|
|
; Table of Contents ;
|
|
---------------------
|
|
1. Legal Notice
|
|
2. Analysis & Synthesis Summary
|
|
3. Analysis & Synthesis Settings
|
|
4. Parallel Compilation
|
|
5. Analysis & Synthesis Source Files Read
|
|
6. Analysis & Synthesis Resource Usage Summary
|
|
7. Analysis & Synthesis Resource Utilization by Entity
|
|
8. State Machine - |GR8RAM|IS
|
|
9. Registers Removed During Synthesis
|
|
10. General Register Statistics
|
|
11. Inverted Register Statistics
|
|
12. Multiplexer Restructuring Statistics (Restructuring Performed)
|
|
13. Analysis & Synthesis Messages
|
|
14. Analysis & Synthesis Suppressed Messages
|
|
|
|
|
|
|
|
----------------
|
|
; Legal Notice ;
|
|
----------------
|
|
Copyright (C) 1991-2013 Altera Corporation
|
|
Your use of Altera Corporation's design tools, logic functions
|
|
and other software and tools, and its AMPP partner logic
|
|
functions, and any output files from any of the foregoing
|
|
(including device programming or simulation files), and any
|
|
associated documentation or information are expressly subject
|
|
to the terms and conditions of the Altera Program License
|
|
Subscription Agreement, Altera MegaCore Function License
|
|
Agreement, or other applicable license agreement, including,
|
|
without limitation, that your use is for the sole purpose of
|
|
programming logic devices manufactured by Altera and sold by
|
|
Altera or its authorized distributors. Please refer to the
|
|
applicable agreement for further details.
|
|
|
|
|
|
|
|
+-------------------------------------------------------------------------------+
|
|
; Analysis & Synthesis Summary ;
|
|
+-----------------------------+-------------------------------------------------+
|
|
; Analysis & Synthesis Status ; Successful - Tue Apr 20 04:19:44 2021 ;
|
|
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
|
|
; Revision Name ; GR8RAM ;
|
|
; Top-level Entity Name ; GR8RAM ;
|
|
; Family ; MAX II ;
|
|
; Total logic elements ; 241 ;
|
|
; Total pins ; 80 ;
|
|
; Total virtual pins ; 0 ;
|
|
; UFM blocks ; 0 / 1 ( 0 % ) ;
|
|
+-----------------------------+-------------------------------------------------+
|
|
|
|
|
|
+----------------------------------------------------------------------------------------------------------------------+
|
|
; Analysis & Synthesis Settings ;
|
|
+----------------------------------------------------------------------------+--------------------+--------------------+
|
|
; Option ; Setting ; Default Value ;
|
|
+----------------------------------------------------------------------------+--------------------+--------------------+
|
|
; Device ; EPM240T100C5 ; ;
|
|
; Top-level entity name ; GR8RAM ; GR8RAM ;
|
|
; Family name ; MAX II ; Cyclone IV GX ;
|
|
; Restructure Multiplexers ; On ; Auto ;
|
|
; State Machine Processing ; Minimal Bits ; Auto ;
|
|
; Remove Redundant Logic Cells ; On ; Off ;
|
|
; Optimization Technique ; Area ; Balanced ;
|
|
; Perform WYSIWYG Primitive Resynthesis ; On ; Off ;
|
|
; Allow Shift Register Merging across Hierarchies ; Always ; Auto ;
|
|
; Auto Resource Sharing ; On ; Off ;
|
|
; Synthesis Seed ; 123 ; 1 ;
|
|
; Use smart compilation ; Off ; Off ;
|
|
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
|
|
; Enable compact report table ; Off ; Off ;
|
|
; Create Debugging Nodes for IP Cores ; Off ; Off ;
|
|
; Preserve fewer node names ; On ; On ;
|
|
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
|
|
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
|
|
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
|
|
; Safe State Machine ; Off ; Off ;
|
|
; Extract Verilog State Machines ; On ; On ;
|
|
; Extract VHDL State Machines ; On ; On ;
|
|
; Ignore Verilog initial constructs ; Off ; Off ;
|
|
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
|
|
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
|
|
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
|
|
; Infer RAMs from Raw Logic ; On ; On ;
|
|
; Parallel Synthesis ; On ; On ;
|
|
; NOT Gate Push-Back ; On ; On ;
|
|
; Power-Up Don't Care ; On ; On ;
|
|
; Remove Duplicate Registers ; On ; On ;
|
|
; Ignore CARRY Buffers ; Off ; Off ;
|
|
; Ignore CASCADE Buffers ; Off ; Off ;
|
|
; Ignore GLOBAL Buffers ; Off ; Off ;
|
|
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
|
|
; Ignore LCELL Buffers ; Off ; Off ;
|
|
; Ignore SOFT Buffers ; On ; On ;
|
|
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
|
|
; Carry Chain Length ; 70 ; 70 ;
|
|
; Auto Carry Chains ; On ; On ;
|
|
; Auto Open-Drain Pins ; On ; On ;
|
|
; Auto Shift Register Replacement ; Auto ; Auto ;
|
|
; Auto Clock Enable Replacement ; On ; On ;
|
|
; Allow Synchronous Control Signals ; On ; On ;
|
|
; Force Use of Synchronous Clear Signals ; Off ; Off ;
|
|
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
|
|
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
|
|
; Report Parameter Settings ; On ; On ;
|
|
; Report Source Assignments ; On ; On ;
|
|
; Report Connectivity Checks ; On ; On ;
|
|
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
|
|
; Synchronization Register Chain Length ; 2 ; 2 ;
|
|
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
|
|
; HDL message level ; Level2 ; Level2 ;
|
|
; Suppress Register Optimization Related Messages ; Off ; Off ;
|
|
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
|
|
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
|
|
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
|
|
; Clock MUX Protection ; On ; On ;
|
|
; Block Design Naming ; Auto ; Auto ;
|
|
; Synthesis Effort ; Auto ; Auto ;
|
|
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
|
|
; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
|
|
; Analysis & Synthesis Message Level ; Medium ; Medium ;
|
|
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
|
|
+----------------------------------------------------------------------------+--------------------+--------------------+
|
|
|
|
|
|
+------------------------------------------+
|
|
; Parallel Compilation ;
|
|
+----------------------------+-------------+
|
|
; Processors ; Number ;
|
|
+----------------------------+-------------+
|
|
; Number detected on machine ; 2 ;
|
|
; Maximum allowed ; 2 ;
|
|
; ; ;
|
|
; Average used ; 1.00 ;
|
|
; Maximum used ; 1 ;
|
|
; ; ;
|
|
; Usage by Processor ; % Time Used ;
|
|
; Processor 1 ; 100.0% ;
|
|
; Processor 2 ; 0.0% ;
|
|
+----------------------------+-------------+
|
|
|
|
|
|
+-----------------------------------------------------------------------------------------------------------------------+
|
|
; Analysis & Synthesis Source Files Read ;
|
|
+----------------------------------+-----------------+------------------------+-------------------------------+---------+
|
|
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
|
|
+----------------------------------+-----------------+------------------------+-------------------------------+---------+
|
|
; GR8RAM.v ; yes ; User Verilog HDL File ; Z:/Repos/GR8RAM/cpld/GR8RAM.v ; ;
|
|
+----------------------------------+-----------------+------------------------+-------------------------------+---------+
|
|
|
|
|
|
+-----------------------------------------------------+
|
|
; Analysis & Synthesis Resource Usage Summary ;
|
|
+---------------------------------------------+-------+
|
|
; Resource ; Usage ;
|
|
+---------------------------------------------+-------+
|
|
; Total logic elements ; 241 ;
|
|
; -- Combinational with no register ; 132 ;
|
|
; -- Register only ; 12 ;
|
|
; -- Combinational with a register ; 97 ;
|
|
; ; ;
|
|
; Logic element usage by number of LUT inputs ; ;
|
|
; -- 4 input functions ; 119 ;
|
|
; -- 3 input functions ; 38 ;
|
|
; -- 2 input functions ; 69 ;
|
|
; -- 1 input functions ; 0 ;
|
|
; -- 0 input functions ; 3 ;
|
|
; ; ;
|
|
; Logic elements by mode ; ;
|
|
; -- normal mode ; 208 ;
|
|
; -- arithmetic mode ; 33 ;
|
|
; -- qfbk mode ; 0 ;
|
|
; -- register cascade mode ; 0 ;
|
|
; -- synchronous clear/load mode ; 44 ;
|
|
; -- asynchronous clear/load mode ; 30 ;
|
|
; ; ;
|
|
; Total registers ; 109 ;
|
|
; Total logic cells in carry chains ; 37 ;
|
|
; I/O pins ; 80 ;
|
|
; Maximum fan-out node ; C25M ;
|
|
; Maximum fan-out ; 106 ;
|
|
; Total fan-out ; 1044 ;
|
|
; Average fan-out ; 3.25 ;
|
|
+---------------------------------------------+-------+
|
|
|
|
|
|
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Analysis & Synthesis Resource Utilization by Entity ;
|
|
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
|
|
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
|
|
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
|
|
; |GR8RAM ; 241 (241) ; 109 ; 0 ; 80 ; 0 ; 132 (132) ; 12 (12) ; 97 (97) ; 37 (37) ; 0 (0) ; |GR8RAM ; work ;
|
|
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
|
|
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
|
|
|
|
|
Encoding Type: Minimal Bits
|
|
+-----------------------------------------------------------+
|
|
; State Machine - |GR8RAM|IS ;
|
|
+--------+----------------+----------------+----------------+
|
|
; Name ; IS.state_bit_2 ; IS.state_bit_1 ; IS.state_bit_0 ;
|
|
+--------+----------------+----------------+----------------+
|
|
; IS.000 ; 0 ; 0 ; 0 ;
|
|
; IS.001 ; 0 ; 0 ; 1 ;
|
|
; IS.100 ; 1 ; 0 ; 0 ;
|
|
; IS.101 ; 1 ; 0 ; 1 ;
|
|
; IS.110 ; 0 ; 1 ; 0 ;
|
|
; IS.111 ; 0 ; 1 ; 1 ;
|
|
+--------+----------------+----------------+----------------+
|
|
|
|
|
|
+------------------------------------------------------------+
|
|
; Registers Removed During Synthesis ;
|
|
+---------------------------------------+--------------------+
|
|
; Register name ; Reason for Removal ;
|
|
+---------------------------------------+--------------------+
|
|
; IS~10 ; Lost fanout ;
|
|
; Total Number of Removed Registers = 1 ; ;
|
|
+---------------------------------------+--------------------+
|
|
|
|
|
|
+------------------------------------------------------+
|
|
; General Register Statistics ;
|
|
+----------------------------------------------+-------+
|
|
; Statistic ; Value ;
|
|
+----------------------------------------------+-------+
|
|
; Total registers ; 109 ;
|
|
; Number of registers using Synchronous Clear ; 11 ;
|
|
; Number of registers using Synchronous Load ; 33 ;
|
|
; Number of registers using Asynchronous Clear ; 30 ;
|
|
; Number of registers using Asynchronous Load ; 0 ;
|
|
; Number of registers using Clock Enable ; 26 ;
|
|
; Number of registers using Preset ; 0 ;
|
|
+----------------------------------------------+-------+
|
|
|
|
|
|
+--------------------------------------------------+
|
|
; Inverted Register Statistics ;
|
|
+----------------------------------------+---------+
|
|
; Inverted Register ; Fan out ;
|
|
+----------------------------------------+---------+
|
|
; nRCS~reg0 ; 1 ;
|
|
; nRAS~reg0 ; 1 ;
|
|
; nCAS~reg0 ; 1 ;
|
|
; nSWE~reg0 ; 1 ;
|
|
; DQML~reg0 ; 1 ;
|
|
; DQMH~reg0 ; 1 ;
|
|
; RCKE~reg0 ; 1 ;
|
|
; Total number of inverted registers = 7 ; ;
|
|
+----------------------------------------+---------+
|
|
|
|
|
|
+------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
|
|
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
|
|
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
|
|
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
|
|
; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |GR8RAM|PS[2] ;
|
|
; 5:1 ; 2 bits ; 6 LEs ; 2 LEs ; 4 LEs ; Yes ; |GR8RAM|SA[11]~reg0 ;
|
|
; 20:1 ; 6 bits ; 78 LEs ; 24 LEs ; 54 LEs ; Yes ; |GR8RAM|SA[3]~reg0 ;
|
|
; 20:1 ; 3 bits ; 39 LEs ; 18 LEs ; 21 LEs ; Yes ; |GR8RAM|SA[0]~reg0 ;
|
|
; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |GR8RAM|WRD[7] ;
|
|
; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |GR8RAM|RDD[1] ;
|
|
; 5:1 ; 4 bits ; 12 LEs ; 8 LEs ; 4 LEs ; Yes ; |GR8RAM|RDD[4] ;
|
|
; 18:1 ; 2 bits ; 24 LEs ; 8 LEs ; 16 LEs ; Yes ; |GR8RAM|DQMH~reg0 ;
|
|
; 8:1 ; 5 bits ; 25 LEs ; 20 LEs ; 5 LEs ; No ; |GR8RAM|IS ;
|
|
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
|
|
|
|
|
|
+-------------------------------+
|
|
; Analysis & Synthesis Messages ;
|
|
+-------------------------------+
|
|
Info: *******************************************************************
|
|
Info: Running Quartus II 32-bit Analysis & Synthesis
|
|
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
|
Info: Processing started: Tue Apr 20 04:19:39 2021
|
|
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
|
|
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
|
|
Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v
|
|
Info (12023): Found entity 1: GR8RAM
|
|
Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy
|
|
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(42): truncated value with size 32 to match size of target (4)
|
|
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(47): truncated value with size 32 to match size of target (14)
|
|
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(130): truncated value with size 32 to match size of target (8)
|
|
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(138): truncated value with size 32 to match size of target (8)
|
|
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(145): truncated value with size 32 to match size of target (8)
|
|
Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "area" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched
|
|
Warning (13024): Output pins are stuck at VCC or GND
|
|
Warning (13410): Pin "nNMIout" is stuck at VCC
|
|
Warning (13410): Pin "nIRQout" is stuck at VCC
|
|
Warning (13410): Pin "nRDYout" is stuck at VCC
|
|
Warning (13410): Pin "nINHout" is stuck at VCC
|
|
Warning (13410): Pin "RWout" is stuck at VCC
|
|
Warning (13410): Pin "nDMAout" is stuck at VCC
|
|
Warning (13410): Pin "RAdir" is stuck at VCC
|
|
Info (17049): 1 registers lost all their fanouts during netlist optimizations.
|
|
Info (21057): Implemented 321 device resources after synthesis - the final resource count might be different
|
|
Info (21058): Implemented 28 input pins
|
|
Info (21059): Implemented 35 output pins
|
|
Info (21060): Implemented 17 bidirectional pins
|
|
Info (21061): Implemented 241 logic cells
|
|
Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg
|
|
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 13 warnings
|
|
Info: Peak virtual memory: 301 megabytes
|
|
Info: Processing ended: Tue Apr 20 04:19:44 2021
|
|
Info: Elapsed time: 00:00:05
|
|
Info: Total CPU time (on all processors): 00:00:04
|
|
|
|
|
|
+------------------------------------------+
|
|
; Analysis & Synthesis Suppressed Messages ;
|
|
+------------------------------------------+
|
|
The suppressed messages can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg.
|
|
|
|
|