<?xml version="1.0" encoding="UTF-8"?>
<BaliProject version="3.2" title="RAM2E_LCMXO2_640HC" device="LCMXO2-640HC-4TG100C" default_implementation="impl1">
    <Options/>
    <Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
        <Options def_top="RAM2E" top="RAM2E"/>
        <Source name="../RAM2E.v" type="Verilog" type_short="Verilog">
            <Options top_module="RAM2E"/>
        </Source>
        <Source name="../UFM-LCMXO2.v" type="Verilog" type_short="Verilog">
            <Options/>
        </Source>
        <Source name="REFB.v" type="Verilog" type_short="Verilog">
            <Options/>
        </Source>
        <Source name="../RAM2E-LCMXO2.lpf" type="Logic Preference" type_short="LPF">
            <Options/>
        </Source>
        <Source name="../RAM2E.sdc" type="Synplify Design Constraints File" type_short="SDC">
            <Options/>
        </Source>
    </Implementation>
    <Strategy name="Strategy1" file="RAM2E_LCMXO2_640HC1.sty"/>
</BaliProject>
