set_global_assignment -name IP_TOOL_NAME "ALTUFM_NONE Intel FPGA IP"
set_global_assignment -name IP_TOOL_VERSION "19.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX V}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "UFM.v"]
