2023-12-29 04:12:12 +00:00
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module RAM2E_UFM(C14M, S, FS, CS, Ready,
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2023-12-27 06:09:54 +00:00
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RWSel, D,
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RWMask, LEDEN,
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CmdRWMaskSet, CmdLEDSet,
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CmdSetRWBankFFChip);
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input C14M;
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input [3:0] S;
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input [15:0] FS;
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2023-12-29 04:12:12 +00:00
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input [2:0] CS;
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input Ready;
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2023-12-27 06:09:54 +00:00
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input RWSel;
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input [7:0] D;
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output reg [7:0] RWMask;
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output reg LEDEN;
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input CmdRWMaskSet;
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input CmdLEDSet;
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output reg CmdSetRWBankFFChip;
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/* RAMWorks register control - Lattice MachXO2 */
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reg CmdBitbangMXO2 = 0;
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reg CmdExecMXO2 = 0;
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always @(posedge C14M) begin
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if (S==4'hC && RWSel) begin
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if (CS==3'h6) begin // Recognize and submit command in CS6
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// Chip detection commands
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//CmdSetRWBankFFChip <= D[7:0]==8'hFF; // MAX
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//CmdSetRWBankFFChip <= D[7:0]==8'hFE; // SPI
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CmdSetRWBankFFChip <= D[7:0]==8'hFD; // MachXO2
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// Altera MAX II/V commands
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//CmdBitbangMAX <= D[7:0]==8'hEA;
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//if (!CmdEraseMAX && !CmdPrgmMAX) begin
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// if (D[7:0]==8'hEE) CmdEraseMAX <= 1;
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// if (D[7:0]==8'hEF) CmdPrgmMAX <= 1;
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//end
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// SPI commands
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//CmdBitbangSPI <= D[7:0]==8'hEB;
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// MachXO2 commands
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CmdBitbangMXO2 <= D[7:0]==8'hEC;
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CmdExecMXO2 <= D[7:0]==8'hED;
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end else begin // Reset command triggers
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CmdSetRWBankFFChip <= 0;
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CmdBitbangMXO2 <= 0;
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CmdExecMXO2 <= 0;
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end
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end
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end
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/* UFM Interface */
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reg wb_rst;
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reg wb_cyc_stb;
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reg wb_req;
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reg wb_we;
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reg [7:0] wb_adr;
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reg [7:0] wb_dati;
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wire wb_ack;
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wire [7:0] wb_dato;
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wire ufm_irq;
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REFB ufmefb(
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.wb_clk_i(C14M),
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.wb_rst_i(wb_rst),
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.wb_cyc_i(wb_cyc_stb),
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.wb_stb_i(wb_cyc_stb),
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.wb_we_i(wb_we),
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.wb_adr_i(wb_adr),
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.wb_dat_i(wb_dati),
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.wb_dat_o(wb_dato),
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.wb_ack_o(wb_ack),
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.wbc_ufm_irq(ufm_irq));
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/* UFM Control */
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always @(posedge C14M) begin
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if (S==4'h0) begin
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if (FS[15:14]==2'b00) wb_rst <= 1'b1;
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else if (FS[15:14]==2'b01) wb_rst <= 1'b0;
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else if (FS[15:14]==2'b10) begin
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wb_rst <= 1'b0;
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if (wb_ack || (FS[7:0]==0)) wb_cyc_stb <= 0;
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else if ((FS[7:0]==1) && wb_req) wb_cyc_stb <= 1;
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case (FS[13:8])
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0: begin // Open frame
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h80;
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wb_req <= 1;
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end 1: begin // Enable configuration interface - command
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h74;
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wb_req <= 1;
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end 2: begin // Enable configuration interface - operand 1/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h08;
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wb_req <= 1;
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end 3: begin // Enable configuration interface - operand 2/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 4: begin // Enable configuration interface - operand 3/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 5: begin // Close frame
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 6: begin // Open frame
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h80;
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wb_req <= 1;
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end 7: begin // Poll status register - command
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h3C;
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wb_req <= 1;
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end 8: begin // Poll status register - operand 1/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 9: begin // Poll status register - operand 2/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 10: begin // Poll status register - operand 3/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 11, 12, 13, 14: begin // Read status register 1-4
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wb_we <= 1'b0;
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wb_adr[7:0] <= 8'h73;
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wb_dati[7:0] <= 8'h3C;
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wb_req <= 1;
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end 15: begin // Close frame
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 16: begin // Open frame
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h80;
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wb_req <= 1;
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end 17: begin // Set UFM address - command
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'hB4;
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wb_req <= 1;
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end 18: begin // Set UFM address - operand 1/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 19: begin // Set UFM address - operand 2/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 20: begin // Set UFM address - operand 3/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 21: begin // Set UFM address - data 1/4
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h40;
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wb_req <= 1;
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end 22: begin // Set UFM address - data 2/4
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 23: begin // Set UFM address - data 3/4
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 24: begin // Set UFM address - data 4/4
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 190;
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wb_req <= 1;
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end 25: begin // Close frame
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 26: begin // Open frame
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h80;
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wb_req <= 1;
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end 27: begin // Read UFM page - command
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'hCA;
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wb_req <= 1;
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end 28: begin // Read UFM page - operand 1/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h10;
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wb_req <= 1;
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end 29: begin // Read UFM page - operand 2/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 30: begin // Read UFM page - operand 3/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h01;
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wb_req <= 1;
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end 31: begin // Read UFM page - data 0
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wb_we <= 1'b0;
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wb_adr[7:0] <= 8'h73;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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if (wb_ack) RWMask[7:0] <= wb_dato[7:0];
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end 32: begin // Read UFM page - data 1
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wb_we <= 1'b0;
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wb_adr[7:0] <= 8'h73;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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if (wb_ack) LEDEN <= wb_dato[0];
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end 33, 34,
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35, 36, 37, 38,
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39, 40, 41, 42,
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43, 44, 45, 46: begin // Read UFM page - data 2-15
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wb_we <= 1'b0;
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wb_adr[7:0] <= 8'h73;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 47: begin // Close frame
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 48: begin // Open frame
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h80;
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wb_req <= 1;
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end 49: begin // Disable configuration interface - command
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h26;
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wb_req <= 1;
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end 50: begin // Disable configuration interface - operand 1/2
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 51: begin // Disable configuration interface - operand 2/2
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 52: begin // Close frame
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 53: begin // Open frame
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h80;
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wb_req <= 1;
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end 54: begin // Bypass - command
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'hFF;
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wb_req <= 1;
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end 55: begin // Close frame
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end default: begin
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wb_we <= 1'b0;
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|
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wb_adr[7:0] <= 8'h70;
|
|
|
|
|
wb_dati[7:0] <= 8'h00;
|
|
|
|
|
wb_req <= 0;
|
|
|
|
|
end
|
|
|
|
|
endcase
|
|
|
|
|
end else begin
|
|
|
|
|
wb_rst <= 1'b0;
|
|
|
|
|
wb_cyc_stb <= 1'b0;
|
|
|
|
|
wb_req <= 1'b0;
|
|
|
|
|
wb_we <= 1'b0;
|
|
|
|
|
wb_adr[7:0] <= 8'h00;
|
|
|
|
|
wb_dati[7:0] <= 8'h00;
|
|
|
|
|
end
|
|
|
|
|
end else begin
|
|
|
|
|
// UFM bitbang control
|
|
|
|
|
wb_rst <= 1'b0;
|
|
|
|
|
wb_req <= 1'b0;
|
|
|
|
|
|
|
|
|
|
if (RWSel && S==4'hC) begin
|
|
|
|
|
// LED control
|
|
|
|
|
if (CmdLEDSet) LEDEN <= D[0];
|
|
|
|
|
|
|
|
|
|
// Set capacity mask
|
|
|
|
|
if (CmdRWMaskSet) RWMask[7:0] <= {D[7], ~D[6:0]};
|
|
|
|
|
|
|
|
|
|
// Set EFB address
|
|
|
|
|
if (CmdBitbangMXO2) begin
|
|
|
|
|
wb_adr[7:0] <= D[7:0];
|
|
|
|
|
wb_dati[7:0] <= wb_adr[7:0];
|
|
|
|
|
end
|
|
|
|
|
|
|
|
|
|
// Excecute EFB R/W cycle
|
|
|
|
|
if (CmdExecMXO2) begin
|
|
|
|
|
wb_we <= D[0];
|
|
|
|
|
wb_cyc_stb <= 1;
|
|
|
|
|
end else if (wb_ack) wb_cyc_stb <= 0;
|
|
|
|
|
end
|
|
|
|
|
end
|
|
|
|
|
end
|
|
|
|
|
endmodule
|
