diff --git a/CPLD/MAXII/RAM2E.qsf b/CPLD/MAXII/RAM2E.qsf index 78f57a3..1cbc2e6 100644 --- a/CPLD/MAXII/RAM2E.qsf +++ b/CPLD/MAXII/RAM2E.qsf @@ -42,7 +42,7 @@ set_global_assignment -name DEVICE EPM240T100C5 set_global_assignment -name TOP_LEVEL_ENTITY RAM2E set_global_assignment -name ORIGINAL_QUARTUS_VERSION 19.1.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "07:26:23 AUGUST 20, 2023" -set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 SP0.02std Lite Edition" +set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 diff --git a/CPLD/MAXII/RAM2E.qws b/CPLD/MAXII/RAM2E.qws index a885882..6f6550b 100644 Binary files a/CPLD/MAXII/RAM2E.qws and b/CPLD/MAXII/RAM2E.qws differ diff --git a/CPLD/MAXII/output_files/RAM2E.asm.rpt b/CPLD/MAXII/output_files/RAM2E.asm.rpt index d8ba547..aac89fe 100644 --- a/CPLD/MAXII/output_files/RAM2E.asm.rpt +++ b/CPLD/MAXII/output_files/RAM2E.asm.rpt @@ -1,6 +1,6 @@ Assembler report for RAM2E -Wed Jan 31 09:41:40 2024 -Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition +Wed Feb 07 19:21:24 2024 +Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition --------------------- @@ -10,7 +10,7 @@ Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Editio 2. Assembler Summary 3. Assembler Settings 4. Assembler Generated Files - 5. Assembler Device Options: Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof + 5. Assembler Device Options: /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof 6. Assembler Messages @@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Wed Jan 31 09:41:40 2024 ; +; Assembler Status ; Successful - Wed Feb 07 19:21:24 2024 ; ; Revision Name ; RAM2E ; ; Top-level Entity Name ; RAM2E ; ; Family ; MAX II ; @@ -53,23 +53,23 @@ https://fpgasoftware.intel.com/eula. +--------+---------+---------------+ -+--------------------------------------------------+ -; Assembler Generated Files ; -+--------------------------------------------------+ -; File Name ; -+--------------------------------------------------+ -; Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof ; -+--------------------------------------------------+ ++------------------------------------------------+ +; Assembler Generated Files ; ++------------------------------------------------+ +; File Name ; ++------------------------------------------------+ +; /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof ; ++------------------------------------------------+ -+----------------------------------------------------------------------------+ -; Assembler Device Options: Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof ; -+----------------+-----------------------------------------------------------+ -; Option ; Setting ; -+----------------+-----------------------------------------------------------+ -; JTAG usercode ; 0x00164C1D ; -; Checksum ; 0x00165015 ; -+----------------+-----------------------------------------------------------+ ++--------------------------------------------------------------------------+ +; Assembler Device Options: /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof ; ++----------------+---------------------------------------------------------+ +; Option ; Setting ; ++----------------+---------------------------------------------------------+ +; JTAG usercode ; 0x00164C1D ; +; Checksum ; 0x00165015 ; ++----------------+---------------------------------------------------------+ +--------------------+ @@ -77,14 +77,14 @@ https://fpgasoftware.intel.com/eula. +--------------------+ Info: ******************************************************************* Info: Running Quartus Prime Assembler - Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition - Info: Processing started: Wed Jan 31 09:41:39 2024 + Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition + Info: Processing started: Wed Feb 07 19:21:23 2024 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E-MAXII -c RAM2E Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 13075 megabytes - Info: Processing ended: Wed Jan 31 09:41:40 2024 + Info: Peak virtual memory: 13061 megabytes + Info: Processing ended: Wed Feb 07 19:21:24 2024 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/CPLD/MAXII/output_files/RAM2E.done b/CPLD/MAXII/output_files/RAM2E.done index 490a939..76f8d8f 100644 --- a/CPLD/MAXII/output_files/RAM2E.done +++ b/CPLD/MAXII/output_files/RAM2E.done @@ -1 +1 @@ -Wed Jan 31 09:41:44 2024 +Wed Feb 07 19:21:30 2024 diff --git a/CPLD/MAXII/output_files/RAM2E.fit.rpt b/CPLD/MAXII/output_files/RAM2E.fit.rpt index cd4a059..70b8364 100644 --- a/CPLD/MAXII/output_files/RAM2E.fit.rpt +++ b/CPLD/MAXII/output_files/RAM2E.fit.rpt @@ -1,6 +1,6 @@ Fitter report for RAM2E -Wed Jan 31 09:41:38 2024 -Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition +Wed Feb 07 19:21:16 2024 +Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition --------------------- @@ -54,21 +54,21 @@ https://fpgasoftware.intel.com/eula. -+-------------------------------------------------------------------------------------+ -; Fitter Summary ; -+-----------------------+-------------------------------------------------------------+ -; Fitter Status ; Successful - Wed Jan 31 09:41:38 2024 ; -; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ; -; Revision Name ; RAM2E ; -; Top-level Entity Name ; RAM2E ; -; Family ; MAX II ; -; Device ; EPM240T100C5 ; -; Timing Models ; Final ; -; Total logic elements ; 238 / 240 ( 99 % ) ; -; Total pins ; 70 / 80 ( 88 % ) ; -; Total virtual pins ; 0 ; -; UFM blocks ; 1 / 1 ( 100 % ) ; -+-----------------------+-------------------------------------------------------------+ ++---------------------------------------------------------------------+ +; Fitter Summary ; ++-----------------------+---------------------------------------------+ +; Fitter Status ; Successful - Wed Feb 07 19:21:16 2024 ; +; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; +; Revision Name ; RAM2E ; +; Top-level Entity Name ; RAM2E ; +; Family ; MAX II ; +; Device ; EPM240T100C5 ; +; Timing Models ; Final ; +; Total logic elements ; 238 / 240 ( 99 % ) ; +; Total pins ; 70 / 80 ( 88 % ) ; +; Total virtual pins ; 0 ; +; UFM blocks ; 1 / 1 ( 100 % ) ; ++-----------------------+---------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------+ @@ -129,20 +129,20 @@ https://fpgasoftware.intel.com/eula. ; Number detected on machine ; 4 ; ; Maximum allowed ; 4 ; ; ; ; -; Average used ; 1.04 ; +; Average used ; 1.02 ; ; Maximum used ; 4 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 1.4% ; -; Processors 3-4 ; 1.1% ; +; Processor 2 ; 1.0% ; +; Processors 3-4 ; 0.6% ; +----------------------------+-------------+ +--------------+ ; Pin-Out File ; +--------------+ -The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pin. +The pin-out file can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pin. +---------------------------------------------------------------------+ @@ -710,23 +710,23 @@ Info (332111): Found 3 clocks Info (332111): 200.000 ram2e_ufm|ARCLK|regout Info (332111): 200.000 ram2e_ufm|DRCLK|regout Info (186079): Completed User Assigned Global Signals Promotion Operation -Info (186215): Automatically promoted signal "C14M" to use Global clock in PIN 12 File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 8 -Info (186216): Automatically promoted some destinations of signal "PHI1" to use Global clock File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 8 - Info (186217): Destination "PHI1r" may be non-global or may not use global clock File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 20 - Info (186217): Destination "S~0" may be non-global or may not use global clock File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 19 -Info (186228): Pin "PHI1" drives global clock, but is not placed in a dedicated clock pin position File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 8 +Info (186215): Automatically promoted signal "C14M" to use Global clock in PIN 12 File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 8 +Info (186216): Automatically promoted some destinations of signal "PHI1" to use Global clock File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 8 + Info (186217): Destination "PHI1r" may be non-global or may not use global clock File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 20 + Info (186217): Destination "S~0" may be non-global or may not use global clock File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 19 +Info (186228): Pin "PHI1" drives global clock, but is not placed in a dedicated clock pin position File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 8 Info (186079): Completed Auto Global Promotion Operation Info (176234): Starting register packing Info (186468): Started processing fast register assignments Warning (186473): Ignored the FAST_OUTPUT_REGISTER assignment made to the following nodes - Warning (186484): Ignored assignment to node "RAout[0]" because node "RAr[0]", which is feeding it, is not a register File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 86 - Warning (186484): Ignored assignment to node "RAout[1]" because node "RAr[1]", which is feeding it, is not a register File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 86 - Warning (186484): Ignored assignment to node "RAout[2]" because node "RAr[2]", which is feeding it, is not a register File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 86 - Warning (186484): Ignored assignment to node "RAout[3]" because node "RAr[3]", which is feeding it, is not a register File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 86 - Warning (186484): Ignored assignment to node "RAout[4]" because node "RAr[4]", which is feeding it, is not a register File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 86 - Warning (186484): Ignored assignment to node "RAout[5]" because node "RAr[5]", which is feeding it, is not a register File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 86 - Warning (186484): Ignored assignment to node "RAout[6]" because node "RAr[6]", which is feeding it, is not a register File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 86 - Warning (186484): Ignored assignment to node "RAout[7]" because node "RAr[7]", which is feeding it, is not a register File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 86 + Warning (186484): Ignored assignment to node "RAout[0]" because node "RAr[0]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 86 + Warning (186484): Ignored assignment to node "RAout[1]" because node "RAr[1]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 86 + Warning (186484): Ignored assignment to node "RAout[2]" because node "RAr[2]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 86 + Warning (186484): Ignored assignment to node "RAout[3]" because node "RAr[3]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 86 + Warning (186484): Ignored assignment to node "RAout[4]" because node "RAr[4]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 86 + Warning (186484): Ignored assignment to node "RAout[5]" because node "RAr[5]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 86 + Warning (186484): Ignored assignment to node "RAout[6]" because node "RAr[6]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 86 + Warning (186484): Ignored assignment to node "RAout[7]" because node "RAr[7]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 86 Info (186469): Finished processing fast register assignments Info (176235): Finished register packing Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 @@ -742,19 +742,19 @@ Info (170195): Router estimated average interconnect usage is 26% of the availab Info (170196): Router estimated peak interconnect usage is 26% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 Info (170202): The Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and routability requirements required full optimization. Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 -Info (11888): Total time spent on timing analysis during the Fitter is 0.46 seconds. +Info (11888): Total time spent on timing analysis during the Fitter is 0.52 seconds. Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 -Info (144001): Generated suppressed messages file Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.fit.smsg +Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.fit.smsg Info: Quartus Prime Fitter was successful. 0 errors, 11 warnings - Info: Peak virtual memory: 13751 megabytes - Info: Processing ended: Wed Jan 31 09:41:38 2024 - Info: Elapsed time: 00:00:05 - Info: Total CPU time (on all processors): 00:00:04 + Info: Peak virtual memory: 13729 megabytes + Info: Processing ended: Wed Feb 07 19:21:16 2024 + Info: Elapsed time: 00:00:16 + Info: Total CPU time (on all processors): 00:00:05 +----------------------------+ ; Fitter Suppressed Messages ; +----------------------------+ -The suppressed messages can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.fit.smsg. +The suppressed messages can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.fit.smsg. diff --git a/CPLD/MAXII/output_files/RAM2E.fit.summary b/CPLD/MAXII/output_files/RAM2E.fit.summary index ba82dae..47e5dbe 100644 --- a/CPLD/MAXII/output_files/RAM2E.fit.summary +++ b/CPLD/MAXII/output_files/RAM2E.fit.summary @@ -1,5 +1,5 @@ -Fitter Status : Successful - Wed Jan 31 09:41:38 2024 -Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition +Fitter Status : Successful - Wed Feb 07 19:21:16 2024 +Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition Revision Name : RAM2E Top-level Entity Name : RAM2E Family : MAX II diff --git a/CPLD/MAXII/output_files/RAM2E.flow.rpt b/CPLD/MAXII/output_files/RAM2E.flow.rpt index 15b1fab..7729fdc 100644 --- a/CPLD/MAXII/output_files/RAM2E.flow.rpt +++ b/CPLD/MAXII/output_files/RAM2E.flow.rpt @@ -1,6 +1,6 @@ Flow report for RAM2E -Wed Jan 31 09:41:43 2024 -Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition +Wed Feb 07 19:21:29 2024 +Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition --------------------- @@ -38,21 +38,21 @@ https://fpgasoftware.intel.com/eula. -+-------------------------------------------------------------------------------------+ -; Flow Summary ; -+-----------------------+-------------------------------------------------------------+ -; Flow Status ; Successful - Wed Jan 31 09:41:40 2024 ; -; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ; -; Revision Name ; RAM2E ; -; Top-level Entity Name ; RAM2E ; -; Family ; MAX II ; -; Device ; EPM240T100C5 ; -; Timing Models ; Final ; -; Total logic elements ; 238 / 240 ( 99 % ) ; -; Total pins ; 70 / 80 ( 88 % ) ; -; Total virtual pins ; 0 ; -; UFM blocks ; 1 / 1 ( 100 % ) ; -+-----------------------+-------------------------------------------------------------+ ++---------------------------------------------------------------------+ +; Flow Summary ; ++-----------------------+---------------------------------------------+ +; Flow Status ; Successful - Wed Feb 07 19:21:24 2024 ; +; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; +; Revision Name ; RAM2E ; +; Top-level Entity Name ; RAM2E ; +; Family ; MAX II ; +; Device ; EPM240T100C5 ; +; Timing Models ; Final ; +; Total logic elements ; 238 / 240 ( 99 % ) ; +; Total pins ; 70 / 80 ( 88 % ) ; +; Total virtual pins ; 0 ; +; UFM blocks ; 1 / 1 ( 100 % ) ; ++-----------------------+---------------------------------------------+ +-----------------------------------------+ @@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 01/31/2024 09:41:02 ; +; Start date & time ; 02/07/2024 19:20:29 ; ; Main task ; Compilation ; ; Revision Name ; RAM2E ; +-------------------+---------------------+ @@ -71,7 +71,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------+------------------------------+---------------+-------------+------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +---------------------------------------+------------------------------+---------------+-------------+------------+ -; COMPILER_SIGNATURE_ID ; 121381084694.170671206206856 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 121380219419.170735162907620 ; -- ; -- ; -- ; ; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; ; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; ; NUM_PARALLEL_PROCESSORS ; 4 ; -- ; -- ; -- ; @@ -86,11 +86,11 @@ https://fpgasoftware.intel.com/eula. +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:30 ; 1.0 ; 13129 MB ; 00:00:53 ; -; Fitter ; 00:00:05 ; 1.0 ; 13751 MB ; 00:00:04 ; -; Assembler ; 00:00:01 ; 1.0 ; 13071 MB ; 00:00:01 ; -; Timing Analyzer ; 00:00:01 ; 1.0 ; 13071 MB ; 00:00:01 ; -; Total ; 00:00:37 ; -- ; -- ; 00:00:59 ; +; Analysis & Synthesis ; 00:00:31 ; 1.0 ; 13109 MB ; 00:00:43 ; +; Fitter ; 00:00:16 ; 1.0 ; 13729 MB ; 00:00:05 ; +; Assembler ; 00:00:01 ; 1.0 ; 13057 MB ; 00:00:01 ; +; Timing Analyzer ; 00:00:03 ; 1.0 ; 13073 MB ; 00:00:02 ; +; Total ; 00:00:51 ; -- ; -- ; 00:00:51 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/CPLD/MAXII/output_files/RAM2E.jdi b/CPLD/MAXII/output_files/RAM2E.jdi index dad2d4f..eb86129 100644 --- a/CPLD/MAXII/output_files/RAM2E.jdi +++ b/CPLD/MAXII/output_files/RAM2E.jdi @@ -1,6 +1,6 @@ - + diff --git a/CPLD/MAXII/output_files/RAM2E.map.rpt b/CPLD/MAXII/output_files/RAM2E.map.rpt index 7d9ecb9..761a538 100644 --- a/CPLD/MAXII/output_files/RAM2E.map.rpt +++ b/CPLD/MAXII/output_files/RAM2E.map.rpt @@ -1,6 +1,6 @@ Analysis & Synthesis report for RAM2E -Wed Jan 31 09:41:31 2024 -Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition +Wed Feb 07 19:20:58 2024 +Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition --------------------- @@ -43,19 +43,19 @@ https://fpgasoftware.intel.com/eula. -+-------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Summary ; -+-----------------------------+-------------------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Wed Jan 31 09:41:31 2024 ; -; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ; -; Revision Name ; RAM2E ; -; Top-level Entity Name ; RAM2E ; -; Family ; MAX II ; -; Total logic elements ; 252 ; -; Total pins ; 70 ; -; Total virtual pins ; 0 ; -; UFM blocks ; 1 / 1 ( 100 % ) ; -+-----------------------------+-------------------------------------------------------------+ ++---------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++-----------------------------+---------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Wed Feb 07 19:20:58 2024 ; +; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; +; Revision Name ; RAM2E ; +; Top-level Entity Name ; RAM2E ; +; Family ; MAX II ; +; Total logic elements ; 252 ; +; Total pins ; 70 ; +; Total virtual pins ; 0 ; +; UFM blocks ; 1 / 1 ( 100 % ) ; ++-----------------------------+---------------------------------------------+ +------------------------------------------------------------------------------------------------------------+ @@ -146,16 +146,16 @@ https://fpgasoftware.intel.com/eula. +----------------------------+-------------+ -+-----------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Source Files Read ; -+----------------------------------+-----------------+----------------------------------+---------------------------------+---------+ -; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; -+----------------------------------+-----------------+----------------------------------+---------------------------------+---------+ -; ../RAM2E.v ; yes ; User Verilog HDL File ; Y:/Repos/RAM2E/CPLD/RAM2E.v ; ; -; ../UFM-MAX.v ; yes ; User Verilog HDL File ; Y:/Repos/RAM2E/CPLD/UFM-MAX.v ; ; -; UFM.v ; yes ; User Wizard-Generated File ; Y:/Repos/RAM2E/CPLD/MAXII/UFM.v ; ; -; ../RAM2E.mif ; yes ; User Memory Initialization File ; Y:/Repos/RAM2E/CPLD/RAM2E.mif ; ; -+----------------------------------+-----------------+----------------------------------+---------------------------------+---------+ ++-------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+----------------------------------+-----------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+----------------------------------+-----------------------------------------+---------+ +; ../RAM2E.v ; yes ; User Verilog HDL File ; //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v ; ; +; ../UFM-MAX.v ; yes ; User Verilog HDL File ; //Mac/Home/Repos/RAM2E/CPLD/UFM-MAX.v ; ; +; UFM.v ; yes ; User Wizard-Generated File ; //Mac/Home/Repos/RAM2E/CPLD/MAXII/UFM.v ; ; +; ../RAM2E.mif ; yes ; User Memory Initialization File ; //Mac/Home/Repos/RAM2E/CPLD/RAM2E.mif ; ; ++----------------------------------+-----------------+----------------------------------+-----------------------------------------+---------+ +-----------------------------------------------------+ @@ -281,50 +281,50 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-------------------------------+ Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis - Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition - Info: Processing started: Wed Jan 31 09:41:01 2024 + Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition + Info: Processing started: Wed Feb 07 19:20:27 2024 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E-MAXII -c RAM2E Info (20032): Parallel compilation is enabled and will use up to 4 processors -Info (12021): Found 1 design units, including 1 entities, in source file /repos/ram2e/cpld/ram2e.v - Info (12023): Found entity 1: RAM2E File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 1 -Info (12021): Found 1 design units, including 1 entities, in source file /repos/ram2e/cpld/ufm-max.v - Info (12023): Found entity 1: RAM2E_UFM File: Y:/Repos/RAM2E/CPLD/UFM-MAX.v Line: 1 +Info (12021): Found 1 design units, including 1 entities, in source file //mac/home/repos/ram2e/cpld/ram2e.v + Info (12023): Found entity 1: RAM2E File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 1 +Info (12021): Found 1 design units, including 1 entities, in source file //mac/home/repos/ram2e/cpld/ufm-max.v + Info (12023): Found entity 1: RAM2E_UFM File: //Mac/Home/Repos/RAM2E/CPLD/UFM-MAX.v Line: 1 Info (12021): Found 2 design units, including 2 entities, in source file ufm.v - Info (12023): Found entity 1: UFM_altufm_none_lbr File: Y:/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 47 - Info (12023): Found entity 2: UFM File: Y:/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 166 + Info (12023): Found entity 1: UFM_altufm_none_lbr File: //Mac/Home/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 47 + Info (12023): Found entity 2: UFM File: //Mac/Home/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 166 Info (12127): Elaborating entity "RAM2E" for the top level hierarchy -Info (12128): Elaborating entity "RAM2E_UFM" for hierarchy "RAM2E_UFM:ram2e_ufm" File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 137 -Info (12128): Elaborating entity "UFM" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst" File: Y:/Repos/RAM2E/CPLD/UFM-MAX.v Line: 78 -Info (12128): Elaborating entity "UFM_altufm_none_lbr" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component" File: Y:/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 217 +Info (12128): Elaborating entity "RAM2E_UFM" for hierarchy "RAM2E_UFM:ram2e_ufm" File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 137 +Info (12128): Elaborating entity "UFM" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst" File: //Mac/Home/Repos/RAM2E/CPLD/UFM-MAX.v Line: 78 +Info (12128): Elaborating entity "UFM_altufm_none_lbr" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component" File: //Mac/Home/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 217 Warning (13024): Output pins are stuck at VCC or GND - Warning (13410): Pin "nCSout" is stuck at GND File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 76 -Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 50 -Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 50 -Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 50 -Warning (14632): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 50 -Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 50 -Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 50 -Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 50 -Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 50 + Warning (13410): Pin "nCSout" is stuck at GND File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 76 +Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50 +Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50 +Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50 +Warning (14632): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50 +Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50 +Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50 +Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50 +Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50 Warning (21074): Design contains 1 input pin(s) that do not drive logic - Warning (15610): No output dependent on input pin "nWE80" File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 11 + Warning (15610): No output dependent on input pin "nWE80" File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 11 Info (21057): Implemented 323 device resources after synthesis - the final resource count might be different Info (21058): Implemented 22 input pins Info (21059): Implemented 40 output pins Info (21060): Implemented 8 bidirectional pins Info (21061): Implemented 252 logic cells Info (21070): Implemented 1 User Flash Memory blocks -Info (144001): Generated suppressed messages file Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.map.smsg +Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.map.smsg Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings - Info: Peak virtual memory: 13129 megabytes - Info: Processing ended: Wed Jan 31 09:41:31 2024 - Info: Elapsed time: 00:00:30 - Info: Total CPU time (on all processors): 00:00:53 + Info: Peak virtual memory: 13109 megabytes + Info: Processing ended: Wed Feb 07 19:20:58 2024 + Info: Elapsed time: 00:00:31 + Info: Total CPU time (on all processors): 00:00:43 +------------------------------------------+ ; Analysis & Synthesis Suppressed Messages ; +------------------------------------------+ -The suppressed messages can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.map.smsg. +The suppressed messages can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.map.smsg. diff --git a/CPLD/MAXII/output_files/RAM2E.map.smsg b/CPLD/MAXII/output_files/RAM2E.map.smsg index 4a387fe..d2971d0 100644 --- a/CPLD/MAXII/output_files/RAM2E.map.smsg +++ b/CPLD/MAXII/output_files/RAM2E.map.smsg @@ -1,3 +1,3 @@ -Warning (10273): Verilog HDL warning at RAM2E.v(73): extended using "x" or "z" File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 73 -Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: Y:/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 73 -Warning (10463): Verilog HDL Declaration warning at UFM.v(189): "program" is SystemVerilog-2005 keyword File: Y:/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 189 +Warning (10273): Verilog HDL warning at RAM2E.v(73): extended using "x" or "z" File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 73 +Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: //Mac/Home/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 73 +Warning (10463): Verilog HDL Declaration warning at UFM.v(189): "program" is SystemVerilog-2005 keyword File: //Mac/Home/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 189 diff --git a/CPLD/MAXII/output_files/RAM2E.map.summary b/CPLD/MAXII/output_files/RAM2E.map.summary index 5e7bac2..c3d39e5 100644 --- a/CPLD/MAXII/output_files/RAM2E.map.summary +++ b/CPLD/MAXII/output_files/RAM2E.map.summary @@ -1,5 +1,5 @@ -Analysis & Synthesis Status : Successful - Wed Jan 31 09:41:31 2024 -Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition +Analysis & Synthesis Status : Successful - Wed Feb 07 19:20:58 2024 +Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition Revision Name : RAM2E Top-level Entity Name : RAM2E Family : MAX II diff --git a/CPLD/MAXII/output_files/RAM2E.pin b/CPLD/MAXII/output_files/RAM2E.pin index 3f032f5..10edbd1 100644 --- a/CPLD/MAXII/output_files/RAM2E.pin +++ b/CPLD/MAXII/output_files/RAM2E.pin @@ -58,7 +58,7 @@ -- Pin directions (input, output or bidir) are based on device operating in user mode. --------------------------------------------------------------------------------- -Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition +Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition CHIP "RAM2E" ASSIGNED TO AN: EPM240T100C5 Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment diff --git a/CPLD/MAXII/output_files/RAM2E.pof b/CPLD/MAXII/output_files/RAM2E.pof index f756468..bd2e74b 100644 Binary files a/CPLD/MAXII/output_files/RAM2E.pof and b/CPLD/MAXII/output_files/RAM2E.pof differ diff --git a/CPLD/MAXII/output_files/RAM2E.sta.rpt b/CPLD/MAXII/output_files/RAM2E.sta.rpt index 9a522b2..5676687 100644 --- a/CPLD/MAXII/output_files/RAM2E.sta.rpt +++ b/CPLD/MAXII/output_files/RAM2E.sta.rpt @@ -1,6 +1,6 @@ Timing Analyzer report for RAM2E -Wed Jan 31 09:41:43 2024 -Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition +Wed Feb 07 19:21:29 2024 +Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition --------------------- @@ -57,18 +57,18 @@ https://fpgasoftware.intel.com/eula. -+---------------------------------------------------------------------------------------------+ -; Timing Analyzer Summary ; -+-----------------------+---------------------------------------------------------------------+ -; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ; -; Timing Analyzer ; Legacy Timing Analyzer ; -; Revision Name ; RAM2E ; -; Device Family ; MAX II ; -; Device Name ; EPM240T100C5 ; -; Timing Models ; Final ; -; Delay Model ; Slow Model ; -; Rise/Fall Delays ; Unavailable ; -+-----------------------+---------------------------------------------------------------------+ ++-----------------------------------------------------------------------------+ +; Timing Analyzer Summary ; ++-----------------------+-----------------------------------------------------+ +; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; +; Timing Analyzer ; Legacy Timing Analyzer ; +; Revision Name ; RAM2E ; +; Device Family ; MAX II ; +; Device Name ; EPM240T100C5 ; +; Timing Models ; Final ; +; Delay Model ; Slow Model ; +; Rise/Fall Delays ; Unavailable ; ++-----------------------+-----------------------------------------------------+ +------------------------------------------+ @@ -84,7 +84,7 @@ https://fpgasoftware.intel.com/eula. ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 0.2% ; +; Processor 2 ; 0.4% ; +----------------------------+-------------+ @@ -93,8 +93,8 @@ https://fpgasoftware.intel.com/eula. +------------------+--------+--------------------------+ ; SDC File Path ; Status ; Read at ; +------------------+--------+--------------------------+ -; ../RAM2E.sdc ; OK ; Wed Jan 31 09:41:43 2024 ; -; ../RAM2E-MAX.sdc ; OK ; Wed Jan 31 09:41:43 2024 ; +; ../RAM2E.sdc ; OK ; Wed Feb 07 19:21:29 2024 ; +; ../RAM2E-MAX.sdc ; OK ; Wed Feb 07 19:21:29 2024 ; +------------------+--------+--------------------------+ @@ -679,8 +679,8 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi +--------------------------+ Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer - Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition - Info: Processing started: Wed Jan 31 09:41:42 2024 + Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition + Info: Processing started: Wed Feb 07 19:21:26 2024 Info: Command: quartus_sta RAM2E-MAXII -c RAM2E Info: qsta_default_script.tcl version: #1 Info (20032): Parallel compilation is enabled and will use up to 4 processors @@ -718,14 +718,12 @@ Info (332146): Worst-case minimum pulse width slack is 34.654 Info (332119): 70.000 0.000 ram2e_ufm|ARCLK|regout Info (332119): 70.000 0.000 ram2e_ufm|DRCLK|regout Info (332001): The selected device family is not supported by the report_metastability command. -Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|ARCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. -Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|DRCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements -Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings - Info: Peak virtual memory: 13071 megabytes - Info: Processing ended: Wed Jan 31 09:41:43 2024 - Info: Elapsed time: 00:00:01 - Info: Total CPU time (on all processors): 00:00:01 +Info: Quartus Prime Timing Analyzer was successful. 0 errors, 4 warnings + Info: Peak virtual memory: 13073 megabytes + Info: Processing ended: Wed Feb 07 19:21:29 2024 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:02 diff --git a/CPLD/MAXV/RAM2E.qsf b/CPLD/MAXV/RAM2E.qsf index 5838302..8c2f03c 100644 --- a/CPLD/MAXV/RAM2E.qsf +++ b/CPLD/MAXV/RAM2E.qsf @@ -42,7 +42,7 @@ set_global_assignment -name DEVICE 5M240ZT100C5 set_global_assignment -name TOP_LEVEL_ENTITY RAM2E set_global_assignment -name ORIGINAL_QUARTUS_VERSION 19.1.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "07:27:32 AUGUST 20, 2023" -set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 SP0.02std Lite Edition" +set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 diff --git a/CPLD/MAXV/RAM2E.qws b/CPLD/MAXV/RAM2E.qws index a445aab..6f6550b 100644 Binary files a/CPLD/MAXV/RAM2E.qws and b/CPLD/MAXV/RAM2E.qws differ diff --git a/CPLD/MAXV/output_files/RAM2E.asm.rpt b/CPLD/MAXV/output_files/RAM2E.asm.rpt index fc19e2f..65366ef 100644 --- a/CPLD/MAXV/output_files/RAM2E.asm.rpt +++ b/CPLD/MAXV/output_files/RAM2E.asm.rpt @@ -1,6 +1,6 @@ Assembler report for RAM2E -Wed Jan 31 09:41:40 2024 -Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition +Wed Feb 07 19:21:24 2024 +Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition --------------------- @@ -10,7 +10,7 @@ Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Editio 2. Assembler Summary 3. Assembler Settings 4. Assembler Generated Files - 5. Assembler Device Options: Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pof + 5. Assembler Device Options: /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pof 6. Assembler Messages @@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Wed Jan 31 09:41:40 2024 ; +; Assembler Status ; Successful - Wed Feb 07 19:21:24 2024 ; ; Revision Name ; RAM2E ; ; Top-level Entity Name ; RAM2E ; ; Family ; MAX V ; @@ -53,23 +53,23 @@ https://fpgasoftware.intel.com/eula. +--------+---------+---------------+ -+-------------------------------------------------+ -; Assembler Generated Files ; -+-------------------------------------------------+ -; File Name ; -+-------------------------------------------------+ -; Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pof ; -+-------------------------------------------------+ ++-----------------------------------------------+ +; Assembler Generated Files ; ++-----------------------------------------------+ +; File Name ; ++-----------------------------------------------+ +; /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pof ; ++-----------------------------------------------+ -+---------------------------------------------------------------------------+ -; Assembler Device Options: Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pof ; -+----------------+----------------------------------------------------------+ -; Option ; Setting ; -+----------------+----------------------------------------------------------+ -; JTAG usercode ; 0x001651A3 ; -; Checksum ; 0x00165523 ; -+----------------+----------------------------------------------------------+ ++-------------------------------------------------------------------------+ +; Assembler Device Options: /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pof ; ++----------------+--------------------------------------------------------+ +; Option ; Setting ; ++----------------+--------------------------------------------------------+ +; JTAG usercode ; 0x001651A3 ; +; Checksum ; 0x00165523 ; ++----------------+--------------------------------------------------------+ +--------------------+ @@ -77,14 +77,14 @@ https://fpgasoftware.intel.com/eula. +--------------------+ Info: ******************************************************************* Info: Running Quartus Prime Assembler - Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition - Info: Processing started: Wed Jan 31 09:41:39 2024 + Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition + Info: Processing started: Wed Feb 07 19:21:23 2024 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E-MAXV -c RAM2E Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 13073 megabytes - Info: Processing ended: Wed Jan 31 09:41:40 2024 + Info: Peak virtual memory: 13069 megabytes + Info: Processing ended: Wed Feb 07 19:21:24 2024 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/CPLD/MAXV/output_files/RAM2E.done b/CPLD/MAXV/output_files/RAM2E.done index 490a939..76f8d8f 100644 --- a/CPLD/MAXV/output_files/RAM2E.done +++ b/CPLD/MAXV/output_files/RAM2E.done @@ -1 +1 @@ -Wed Jan 31 09:41:44 2024 +Wed Feb 07 19:21:30 2024 diff --git a/CPLD/MAXV/output_files/RAM2E.fit.rpt b/CPLD/MAXV/output_files/RAM2E.fit.rpt index 7a3d6e3..8b7c649 100644 --- a/CPLD/MAXV/output_files/RAM2E.fit.rpt +++ b/CPLD/MAXV/output_files/RAM2E.fit.rpt @@ -1,6 +1,6 @@ Fitter report for RAM2E -Wed Jan 31 09:41:38 2024 -Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition +Wed Feb 07 19:21:16 2024 +Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition --------------------- @@ -54,21 +54,21 @@ https://fpgasoftware.intel.com/eula. -+-------------------------------------------------------------------------------------+ -; Fitter Summary ; -+-----------------------+-------------------------------------------------------------+ -; Fitter Status ; Successful - Wed Jan 31 09:41:38 2024 ; -; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ; -; Revision Name ; RAM2E ; -; Top-level Entity Name ; RAM2E ; -; Family ; MAX V ; -; Device ; 5M240ZT100C5 ; -; Timing Models ; Final ; -; Total logic elements ; 238 / 240 ( 99 % ) ; -; Total pins ; 70 / 79 ( 89 % ) ; -; Total virtual pins ; 0 ; -; UFM blocks ; 1 / 1 ( 100 % ) ; -+-----------------------+-------------------------------------------------------------+ ++---------------------------------------------------------------------+ +; Fitter Summary ; ++-----------------------+---------------------------------------------+ +; Fitter Status ; Successful - Wed Feb 07 19:21:16 2024 ; +; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; +; Revision Name ; RAM2E ; +; Top-level Entity Name ; RAM2E ; +; Family ; MAX V ; +; Device ; 5M240ZT100C5 ; +; Timing Models ; Final ; +; Total logic elements ; 238 / 240 ( 99 % ) ; +; Total pins ; 70 / 79 ( 89 % ) ; +; Total virtual pins ; 0 ; +; UFM blocks ; 1 / 1 ( 100 % ) ; ++-----------------------+---------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------+ @@ -129,20 +129,20 @@ https://fpgasoftware.intel.com/eula. ; Number detected on machine ; 4 ; ; Maximum allowed ; 4 ; ; ; ; -; Average used ; 1.04 ; +; Average used ; 1.02 ; ; Maximum used ; 4 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 1.6% ; -; Processors 3-4 ; 1.3% ; +; Processor 2 ; 0.9% ; +; Processors 3-4 ; 0.6% ; +----------------------------+-------------+ +--------------+ ; Pin-Out File ; +--------------+ -The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin. +The pin-out file can be found in /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin. +---------------------------------------------------------------------+ @@ -718,23 +718,23 @@ Info (332111): Found 3 clocks Info (332111): 200.000 ram2e_ufm|ARCLK|regout Info (332111): 200.000 ram2e_ufm|DRCLK|regout Info (186079): Completed User Assigned Global Signals Promotion Operation -Info (186215): Automatically promoted signal "C14M" to use Global clock in PIN 12 File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 8 -Info (186216): Automatically promoted some destinations of signal "PHI1" to use Global clock File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 8 - Info (186217): Destination "PHI1r" may be non-global or may not use global clock File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 20 - Info (186217): Destination "S~0" may be non-global or may not use global clock File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 19 -Info (186228): Pin "PHI1" drives global clock, but is not placed in a dedicated clock pin position File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 8 +Info (186215): Automatically promoted signal "C14M" to use Global clock in PIN 12 File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 8 +Info (186216): Automatically promoted some destinations of signal "PHI1" to use Global clock File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 8 + Info (186217): Destination "PHI1r" may be non-global or may not use global clock File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 20 + Info (186217): Destination "S~0" may be non-global or may not use global clock File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 19 +Info (186228): Pin "PHI1" drives global clock, but is not placed in a dedicated clock pin position File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 8 Info (186079): Completed Auto Global Promotion Operation Info (176234): Starting register packing Info (186468): Started processing fast register assignments Warning (186473): Ignored the FAST_OUTPUT_REGISTER assignment made to the following nodes - Warning (186484): Ignored assignment to node "RAout[0]" because node "RAr[0]", which is feeding it, is not a register File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 86 - Warning (186484): Ignored assignment to node "RAout[1]" because node "RAr[1]", which is feeding it, is not a register File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 86 - Warning (186484): Ignored assignment to node "RAout[2]" because node "RAr[2]", which is feeding it, is not a register File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 86 - Warning (186484): Ignored assignment to node "RAout[3]" because node "RAr[3]", which is feeding it, is not a register File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 86 - Warning (186484): Ignored assignment to node "RAout[4]" because node "RAr[4]", which is feeding it, is not a register File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 86 - Warning (186484): Ignored assignment to node "RAout[5]" because node "RAr[5]", which is feeding it, is not a register File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 86 - Warning (186484): Ignored assignment to node "RAout[6]" because node "RAr[6]", which is feeding it, is not a register File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 86 - Warning (186484): Ignored assignment to node "RAout[7]" because node "RAr[7]", which is feeding it, is not a register File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 86 + Warning (186484): Ignored assignment to node "RAout[0]" because node "RAr[0]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 86 + Warning (186484): Ignored assignment to node "RAout[1]" because node "RAr[1]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 86 + Warning (186484): Ignored assignment to node "RAout[2]" because node "RAr[2]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 86 + Warning (186484): Ignored assignment to node "RAout[3]" because node "RAr[3]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 86 + Warning (186484): Ignored assignment to node "RAout[4]" because node "RAr[4]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 86 + Warning (186484): Ignored assignment to node "RAout[5]" because node "RAr[5]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 86 + Warning (186484): Ignored assignment to node "RAout[6]" because node "RAr[6]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 86 + Warning (186484): Ignored assignment to node "RAout[7]" because node "RAr[7]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 86 Info (186469): Finished processing fast register assignments Info (176235): Finished register packing Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 @@ -750,19 +750,19 @@ Info (170195): Router estimated average interconnect usage is 25% of the availab Info (170196): Router estimated peak interconnect usage is 25% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 Info (170202): The Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and routability requirements required full optimization. Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 -Info (11888): Total time spent on timing analysis during the Fitter is 0.48 seconds. +Info (11888): Total time spent on timing analysis during the Fitter is 0.50 seconds. Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 -Info (144001): Generated suppressed messages file Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.fit.smsg +Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.fit.smsg Info: Quartus Prime Fitter was successful. 0 errors, 11 warnings - Info: Peak virtual memory: 13750 megabytes - Info: Processing ended: Wed Jan 31 09:41:38 2024 - Info: Elapsed time: 00:00:05 - Info: Total CPU time (on all processors): 00:00:04 + Info: Peak virtual memory: 13731 megabytes + Info: Processing ended: Wed Feb 07 19:21:16 2024 + Info: Elapsed time: 00:00:16 + Info: Total CPU time (on all processors): 00:00:05 +----------------------------+ ; Fitter Suppressed Messages ; +----------------------------+ -The suppressed messages can be found in Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.fit.smsg. +The suppressed messages can be found in /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.fit.smsg. diff --git a/CPLD/MAXV/output_files/RAM2E.fit.summary b/CPLD/MAXV/output_files/RAM2E.fit.summary index 37d3872..c2414e6 100644 --- a/CPLD/MAXV/output_files/RAM2E.fit.summary +++ b/CPLD/MAXV/output_files/RAM2E.fit.summary @@ -1,5 +1,5 @@ -Fitter Status : Successful - Wed Jan 31 09:41:38 2024 -Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition +Fitter Status : Successful - Wed Feb 07 19:21:16 2024 +Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition Revision Name : RAM2E Top-level Entity Name : RAM2E Family : MAX V diff --git a/CPLD/MAXV/output_files/RAM2E.flow.rpt b/CPLD/MAXV/output_files/RAM2E.flow.rpt index 7393793..d18520c 100644 --- a/CPLD/MAXV/output_files/RAM2E.flow.rpt +++ b/CPLD/MAXV/output_files/RAM2E.flow.rpt @@ -1,6 +1,6 @@ Flow report for RAM2E -Wed Jan 31 09:41:43 2024 -Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition +Wed Feb 07 19:21:29 2024 +Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition --------------------- @@ -38,21 +38,21 @@ https://fpgasoftware.intel.com/eula. -+-------------------------------------------------------------------------------------+ -; Flow Summary ; -+-----------------------+-------------------------------------------------------------+ -; Flow Status ; Successful - Wed Jan 31 09:41:40 2024 ; -; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ; -; Revision Name ; RAM2E ; -; Top-level Entity Name ; RAM2E ; -; Family ; MAX V ; -; Device ; 5M240ZT100C5 ; -; Timing Models ; Final ; -; Total logic elements ; 238 / 240 ( 99 % ) ; -; Total pins ; 70 / 79 ( 89 % ) ; -; Total virtual pins ; 0 ; -; UFM blocks ; 1 / 1 ( 100 % ) ; -+-----------------------+-------------------------------------------------------------+ ++---------------------------------------------------------------------+ +; Flow Summary ; ++-----------------------+---------------------------------------------+ +; Flow Status ; Successful - Wed Feb 07 19:21:24 2024 ; +; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; +; Revision Name ; RAM2E ; +; Top-level Entity Name ; RAM2E ; +; Family ; MAX V ; +; Device ; 5M240ZT100C5 ; +; Timing Models ; Final ; +; Total logic elements ; 238 / 240 ( 99 % ) ; +; Total pins ; 70 / 79 ( 89 % ) ; +; Total virtual pins ; 0 ; +; UFM blocks ; 1 / 1 ( 100 % ) ; ++-----------------------+---------------------------------------------+ +-----------------------------------------+ @@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 01/31/2024 09:40:55 ; +; Start date & time ; 02/07/2024 19:20:29 ; ; Main task ; Compilation ; ; Revision Name ; RAM2E ; +-------------------+---------------------+ @@ -71,7 +71,7 @@ https://fpgasoftware.intel.com/eula. +-------------------------------+------------------------------+---------------+-------------+------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +-------------------------------+------------------------------+---------------+-------------+------------+ -; COMPILER_SIGNATURE_ID ; 121381084694.170671205502908 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 121380219419.170735162902460 ; -- ; -- ; -- ; ; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; ; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; ; NUM_PARALLEL_PROCESSORS ; 4 ; -- ; -- ; -- ; @@ -85,11 +85,11 @@ https://fpgasoftware.intel.com/eula. +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:37 ; 1.0 ; 13129 MB ; 00:00:51 ; -; Fitter ; 00:00:05 ; 1.0 ; 13750 MB ; 00:00:04 ; -; Assembler ; 00:00:01 ; 1.0 ; 13072 MB ; 00:00:01 ; -; Timing Analyzer ; 00:00:01 ; 1.0 ; 13073 MB ; 00:00:02 ; -; Total ; 00:00:44 ; -- ; -- ; 00:00:58 ; +; Analysis & Synthesis ; 00:00:31 ; 1.0 ; 13110 MB ; 00:00:42 ; +; Fitter ; 00:00:16 ; 1.0 ; 13731 MB ; 00:00:05 ; +; Assembler ; 00:00:01 ; 1.0 ; 13065 MB ; 00:00:01 ; +; Timing Analyzer ; 00:00:03 ; 1.0 ; 13075 MB ; 00:00:02 ; +; Total ; 00:00:51 ; -- ; -- ; 00:00:50 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/CPLD/MAXV/output_files/RAM2E.jdi b/CPLD/MAXV/output_files/RAM2E.jdi index 60ebd55..bec8212 100644 --- a/CPLD/MAXV/output_files/RAM2E.jdi +++ b/CPLD/MAXV/output_files/RAM2E.jdi @@ -1,6 +1,6 @@ - + diff --git a/CPLD/MAXV/output_files/RAM2E.map.rpt b/CPLD/MAXV/output_files/RAM2E.map.rpt index 4b9606a..db621d9 100644 --- a/CPLD/MAXV/output_files/RAM2E.map.rpt +++ b/CPLD/MAXV/output_files/RAM2E.map.rpt @@ -1,6 +1,6 @@ Analysis & Synthesis report for RAM2E -Wed Jan 31 09:41:31 2024 -Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition +Wed Feb 07 19:20:58 2024 +Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition --------------------- @@ -43,19 +43,19 @@ https://fpgasoftware.intel.com/eula. -+-------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Summary ; -+-----------------------------+-------------------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Wed Jan 31 09:41:31 2024 ; -; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ; -; Revision Name ; RAM2E ; -; Top-level Entity Name ; RAM2E ; -; Family ; MAX V ; -; Total logic elements ; 252 ; -; Total pins ; 70 ; -; Total virtual pins ; 0 ; -; UFM blocks ; 1 / 1 ( 100 % ) ; -+-----------------------------+-------------------------------------------------------------+ ++---------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++-----------------------------+---------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Wed Feb 07 19:20:58 2024 ; +; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; +; Revision Name ; RAM2E ; +; Top-level Entity Name ; RAM2E ; +; Family ; MAX V ; +; Total logic elements ; 252 ; +; Total pins ; 70 ; +; Total virtual pins ; 0 ; +; UFM blocks ; 1 / 1 ( 100 % ) ; ++-----------------------------+---------------------------------------------+ +------------------------------------------------------------------------------------------------------------+ @@ -146,16 +146,16 @@ https://fpgasoftware.intel.com/eula. +----------------------------+-------------+ -+----------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Source Files Read ; -+----------------------------------+-----------------+----------------------------------+--------------------------------+---------+ -; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; -+----------------------------------+-----------------+----------------------------------+--------------------------------+---------+ -; ../RAM2E.v ; yes ; User Verilog HDL File ; Y:/Repos/RAM2E/CPLD/RAM2E.v ; ; -; ../UFM-MAX.v ; yes ; User Verilog HDL File ; Y:/Repos/RAM2E/CPLD/UFM-MAX.v ; ; -; UFM.v ; yes ; User Wizard-Generated File ; Y:/Repos/RAM2E/CPLD/MAXV/UFM.v ; ; -; ../RAM2E.mif ; yes ; User Memory Initialization File ; Y:/Repos/RAM2E/CPLD/RAM2E.mif ; ; -+----------------------------------+-----------------+----------------------------------+--------------------------------+---------+ ++------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+----------------------------------+----------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+----------------------------------+----------------------------------------+---------+ +; ../RAM2E.v ; yes ; User Verilog HDL File ; //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v ; ; +; ../UFM-MAX.v ; yes ; User Verilog HDL File ; //Mac/Home/Repos/RAM2E/CPLD/UFM-MAX.v ; ; +; UFM.v ; yes ; User Wizard-Generated File ; //Mac/Home/Repos/RAM2E/CPLD/MAXV/UFM.v ; ; +; ../RAM2E.mif ; yes ; User Memory Initialization File ; //Mac/Home/Repos/RAM2E/CPLD/RAM2E.mif ; ; ++----------------------------------+-----------------+----------------------------------+----------------------------------------+---------+ +-----------------------------------------------------+ @@ -281,50 +281,50 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-------------------------------+ Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis - Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition - Info: Processing started: Wed Jan 31 09:40:54 2024 + Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition + Info: Processing started: Wed Feb 07 19:20:27 2024 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E-MAXV -c RAM2E Info (20032): Parallel compilation is enabled and will use up to 4 processors -Info (12021): Found 1 design units, including 1 entities, in source file /repos/ram2e/cpld/ram2e.v - Info (12023): Found entity 1: RAM2E File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 1 -Info (12021): Found 1 design units, including 1 entities, in source file /repos/ram2e/cpld/ufm-max.v - Info (12023): Found entity 1: RAM2E_UFM File: Y:/Repos/RAM2E/CPLD/UFM-MAX.v Line: 1 +Info (12021): Found 1 design units, including 1 entities, in source file //mac/home/repos/ram2e/cpld/ram2e.v + Info (12023): Found entity 1: RAM2E File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 1 +Info (12021): Found 1 design units, including 1 entities, in source file //mac/home/repos/ram2e/cpld/ufm-max.v + Info (12023): Found entity 1: RAM2E_UFM File: //Mac/Home/Repos/RAM2E/CPLD/UFM-MAX.v Line: 1 Info (12021): Found 2 design units, including 2 entities, in source file ufm.v - Info (12023): Found entity 1: UFM_altufm_none_p8r File: Y:/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 47 - Info (12023): Found entity 2: UFM File: Y:/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 166 + Info (12023): Found entity 1: UFM_altufm_none_p8r File: //Mac/Home/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 47 + Info (12023): Found entity 2: UFM File: //Mac/Home/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 166 Info (12127): Elaborating entity "RAM2E" for the top level hierarchy -Info (12128): Elaborating entity "RAM2E_UFM" for hierarchy "RAM2E_UFM:ram2e_ufm" File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 137 -Info (12128): Elaborating entity "UFM" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst" File: Y:/Repos/RAM2E/CPLD/UFM-MAX.v Line: 78 -Info (12128): Elaborating entity "UFM_altufm_none_p8r" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component" File: Y:/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 217 +Info (12128): Elaborating entity "RAM2E_UFM" for hierarchy "RAM2E_UFM:ram2e_ufm" File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 137 +Info (12128): Elaborating entity "UFM" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst" File: //Mac/Home/Repos/RAM2E/CPLD/UFM-MAX.v Line: 78 +Info (12128): Elaborating entity "UFM_altufm_none_p8r" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component" File: //Mac/Home/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 217 Warning (13024): Output pins are stuck at VCC or GND - Warning (13410): Pin "nCSout" is stuck at GND File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 76 -Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 50 -Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 50 -Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 50 -Warning (14632): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 50 -Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 50 -Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 50 -Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 50 -Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 50 + Warning (13410): Pin "nCSout" is stuck at GND File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 76 +Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50 +Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50 +Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50 +Warning (14632): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50 +Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50 +Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50 +Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50 +Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50 Warning (21074): Design contains 1 input pin(s) that do not drive logic - Warning (15610): No output dependent on input pin "nWE80" File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 11 + Warning (15610): No output dependent on input pin "nWE80" File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 11 Info (21057): Implemented 323 device resources after synthesis - the final resource count might be different Info (21058): Implemented 22 input pins Info (21059): Implemented 40 output pins Info (21060): Implemented 8 bidirectional pins Info (21061): Implemented 252 logic cells Info (21070): Implemented 1 User Flash Memory blocks -Info (144001): Generated suppressed messages file Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.map.smsg +Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.map.smsg Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings - Info: Peak virtual memory: 13129 megabytes - Info: Processing ended: Wed Jan 31 09:41:31 2024 - Info: Elapsed time: 00:00:37 - Info: Total CPU time (on all processors): 00:00:51 + Info: Peak virtual memory: 13110 megabytes + Info: Processing ended: Wed Feb 07 19:20:58 2024 + Info: Elapsed time: 00:00:31 + Info: Total CPU time (on all processors): 00:00:42 +------------------------------------------+ ; Analysis & Synthesis Suppressed Messages ; +------------------------------------------+ -The suppressed messages can be found in Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.map.smsg. +The suppressed messages can be found in /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.map.smsg. diff --git a/CPLD/MAXV/output_files/RAM2E.map.smsg b/CPLD/MAXV/output_files/RAM2E.map.smsg index 6bbfb1f..0ea9ac4 100644 --- a/CPLD/MAXV/output_files/RAM2E.map.smsg +++ b/CPLD/MAXV/output_files/RAM2E.map.smsg @@ -1,3 +1,3 @@ -Warning (10273): Verilog HDL warning at RAM2E.v(73): extended using "x" or "z" File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 73 -Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: Y:/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 73 -Warning (10463): Verilog HDL Declaration warning at UFM.v(189): "program" is SystemVerilog-2005 keyword File: Y:/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 189 +Warning (10273): Verilog HDL warning at RAM2E.v(73): extended using "x" or "z" File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 73 +Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: //Mac/Home/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 73 +Warning (10463): Verilog HDL Declaration warning at UFM.v(189): "program" is SystemVerilog-2005 keyword File: //Mac/Home/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 189 diff --git a/CPLD/MAXV/output_files/RAM2E.map.summary b/CPLD/MAXV/output_files/RAM2E.map.summary index 4204589..001a682 100644 --- a/CPLD/MAXV/output_files/RAM2E.map.summary +++ b/CPLD/MAXV/output_files/RAM2E.map.summary @@ -1,5 +1,5 @@ -Analysis & Synthesis Status : Successful - Wed Jan 31 09:41:31 2024 -Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition +Analysis & Synthesis Status : Successful - Wed Feb 07 19:20:58 2024 +Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition Revision Name : RAM2E Top-level Entity Name : RAM2E Family : MAX V diff --git a/CPLD/MAXV/output_files/RAM2E.pin b/CPLD/MAXV/output_files/RAM2E.pin index 2236865..f8d5ceb 100644 --- a/CPLD/MAXV/output_files/RAM2E.pin +++ b/CPLD/MAXV/output_files/RAM2E.pin @@ -58,7 +58,7 @@ -- Pin directions (input, output or bidir) are based on device operating in user mode. --------------------------------------------------------------------------------- -Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition +Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition CHIP "RAM2E" ASSIGNED TO AN: 5M240ZT100C5 Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment diff --git a/CPLD/MAXV/output_files/RAM2E.pof b/CPLD/MAXV/output_files/RAM2E.pof index f6f6d32..fbf99ed 100644 Binary files a/CPLD/MAXV/output_files/RAM2E.pof and b/CPLD/MAXV/output_files/RAM2E.pof differ diff --git a/CPLD/MAXV/output_files/RAM2E.sta.rpt b/CPLD/MAXV/output_files/RAM2E.sta.rpt index 3a33edc..e022f78 100644 --- a/CPLD/MAXV/output_files/RAM2E.sta.rpt +++ b/CPLD/MAXV/output_files/RAM2E.sta.rpt @@ -1,6 +1,6 @@ Timing Analyzer report for RAM2E -Wed Jan 31 09:41:44 2024 -Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition +Wed Feb 07 19:21:29 2024 +Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition --------------------- @@ -57,18 +57,18 @@ https://fpgasoftware.intel.com/eula. -+---------------------------------------------------------------------------------------------+ -; Timing Analyzer Summary ; -+-----------------------+---------------------------------------------------------------------+ -; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ; -; Timing Analyzer ; Legacy Timing Analyzer ; -; Revision Name ; RAM2E ; -; Device Family ; MAX V ; -; Device Name ; 5M240ZT100C5 ; -; Timing Models ; Final ; -; Delay Model ; Slow Model ; -; Rise/Fall Delays ; Unavailable ; -+-----------------------+---------------------------------------------------------------------+ ++-----------------------------------------------------------------------------+ +; Timing Analyzer Summary ; ++-----------------------+-----------------------------------------------------+ +; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; +; Timing Analyzer ; Legacy Timing Analyzer ; +; Revision Name ; RAM2E ; +; Device Family ; MAX V ; +; Device Name ; 5M240ZT100C5 ; +; Timing Models ; Final ; +; Delay Model ; Slow Model ; +; Rise/Fall Delays ; Unavailable ; ++-----------------------+-----------------------------------------------------+ +------------------------------------------+ @@ -84,7 +84,7 @@ https://fpgasoftware.intel.com/eula. ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 0.0% ; +; Processor 2 ; 0.1% ; +----------------------------+-------------+ @@ -93,8 +93,8 @@ https://fpgasoftware.intel.com/eula. +------------------+--------+--------------------------+ ; SDC File Path ; Status ; Read at ; +------------------+--------+--------------------------+ -; ../RAM2E-MAX.sdc ; OK ; Wed Jan 31 09:41:43 2024 ; -; ../RAM2E.sdc ; OK ; Wed Jan 31 09:41:43 2024 ; +; ../RAM2E-MAX.sdc ; OK ; Wed Feb 07 19:21:29 2024 ; +; ../RAM2E.sdc ; OK ; Wed Feb 07 19:21:29 2024 ; +------------------+--------+--------------------------+ @@ -679,8 +679,8 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi +--------------------------+ Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer - Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition - Info: Processing started: Wed Jan 31 09:41:42 2024 + Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition + Info: Processing started: Wed Feb 07 19:21:26 2024 Info: Command: quartus_sta RAM2E-MAXV -c RAM2E Info: qsta_default_script.tcl version: #1 Info (20032): Parallel compilation is enabled and will use up to 4 processors @@ -718,14 +718,12 @@ Info (332146): Worst-case minimum pulse width slack is 34.581 Info (332119): 70.000 0.000 ram2e_ufm|ARCLK|regout Info (332119): 70.000 0.000 ram2e_ufm|DRCLK|regout Info (332001): The selected device family is not supported by the report_metastability command. -Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|ARCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. -Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|DRCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements -Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings - Info: Peak virtual memory: 13073 megabytes - Info: Processing ended: Wed Jan 31 09:41:43 2024 - Info: Elapsed time: 00:00:01 +Info: Quartus Prime Timing Analyzer was successful. 0 errors, 4 warnings + Info: Peak virtual memory: 13075 megabytes + Info: Processing ended: Wed Feb 07 19:21:29 2024 + Info: Elapsed time: 00:00:03 Info: Total CPU time (on all processors): 00:00:02