diff --git a/CPLD/MAXII/RAM2E.qws b/CPLD/MAXII/RAM2E.qws
index 0056834..6672e6a 100644
Binary files a/CPLD/MAXII/RAM2E.qws and b/CPLD/MAXII/RAM2E.qws differ
diff --git a/CPLD/MAXII/output_files/RAM2E.asm.rpt b/CPLD/MAXII/output_files/RAM2E.asm.rpt
index 11f86d4..8eb1daa 100644
--- a/CPLD/MAXII/output_files/RAM2E.asm.rpt
+++ b/CPLD/MAXII/output_files/RAM2E.asm.rpt
@@ -1,5 +1,5 @@
 Assembler report for RAM2E
-Mon Feb 12 17:00:22 2024
+Thu Feb 15 04:16:27 2024
 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
 
 
@@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula.
 +---------------------------------------------------------------+
 ; Assembler Summary                                             ;
 +-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Mon Feb 12 17:00:22 2024 ;
+; Assembler Status      ; Successful - Thu Feb 15 04:16:27 2024 ;
 ; Revision Name         ; RAM2E                                 ;
 ; Top-level Entity Name ; RAM2E                                 ;
 ; Family                ; MAX II                                ;
@@ -78,14 +78,14 @@ https://fpgasoftware.intel.com/eula.
 Info: *******************************************************************
 Info: Running Quartus Prime Assembler
     Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
-    Info: Processing started: Mon Feb 12 17:00:21 2024
+    Info: Processing started: Thu Feb 15 04:16:25 2024
 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E-MAXII -c RAM2E
 Info (115031): Writing out detailed assembly data for power analysis
 Info (115030): Assembler is generating device programming files
 Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
-    Info: Peak virtual memory: 13104 megabytes
-    Info: Processing ended: Mon Feb 12 17:00:22 2024
-    Info: Elapsed time: 00:00:01
+    Info: Peak virtual memory: 13103 megabytes
+    Info: Processing ended: Thu Feb 15 04:16:27 2024
+    Info: Elapsed time: 00:00:02
     Info: Total CPU time (on all processors): 00:00:01
 
 
diff --git a/CPLD/MAXII/output_files/RAM2E.done b/CPLD/MAXII/output_files/RAM2E.done
index c5630c1..a2717e2 100644
--- a/CPLD/MAXII/output_files/RAM2E.done
+++ b/CPLD/MAXII/output_files/RAM2E.done
@@ -1 +1 @@
-Mon Feb 12 17:00:25 2024
+Thu Feb 15 04:16:32 2024
diff --git a/CPLD/MAXII/output_files/RAM2E.fit.rpt b/CPLD/MAXII/output_files/RAM2E.fit.rpt
index f416ed2..5edf267 100644
--- a/CPLD/MAXII/output_files/RAM2E.fit.rpt
+++ b/CPLD/MAXII/output_files/RAM2E.fit.rpt
@@ -1,5 +1,5 @@
 Fitter report for RAM2E
-Mon Feb 12 17:00:20 2024
+Thu Feb 15 04:16:23 2024
 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
 
 
@@ -57,7 +57,7 @@ https://fpgasoftware.intel.com/eula.
 +---------------------------------------------------------------------+
 ; Fitter Summary                                                      ;
 +-----------------------+---------------------------------------------+
-; Fitter Status         ; Successful - Mon Feb 12 17:00:20 2024       ;
+; Fitter Status         ; Successful - Thu Feb 15 04:16:23 2024       ;
 ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
 ; Revision Name         ; RAM2E                                       ;
 ; Top-level Entity Name ; RAM2E                                       ;
@@ -129,13 +129,13 @@ https://fpgasoftware.intel.com/eula.
 ; Number detected on machine ; 4           ;
 ; Maximum allowed            ; 4           ;
 ;                            ;             ;
-; Average used               ; 1.04        ;
+; Average used               ; 1.03        ;
 ; Maximum used               ; 4           ;
 ;                            ;             ;
 ; Usage by Processor         ; % Time Used ;
 ;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;   1.6%      ;
-;     Processors 3-4         ;   1.2%      ;
+;     Processor 2            ;   1.2%      ;
+;     Processors 3-4         ;   1.0%      ;
 +----------------------------+-------------+
 
 
@@ -732,23 +732,23 @@ Info (176235): Finished register packing
 Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
 Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
 Info (170189): Fitter placement preparation operations beginning
-Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
 Info (170191): Fitter placement operations beginning
 Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:02
 Info (170193): Fitter routing operations beginning
 Info (170089): 5e+01 ns of routing delay (approximately 3.3% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report.
 Info (170195): Router estimated average interconnect usage is 26% of the available device resources
     Info (170196): Router estimated peak interconnect usage is 26% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
 Info (170202): The Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and routability requirements required full optimization.
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
-Info (11888): Total time spent on timing analysis during the Fitter is 0.38 seconds.
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
+Info (11888): Total time spent on timing analysis during the Fitter is 0.97 seconds.
 Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
 Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.fit.smsg
 Info: Quartus Prime Fitter was successful. 0 errors, 11 warnings
-    Info: Peak virtual memory: 13771 megabytes
-    Info: Processing ended: Mon Feb 12 17:00:20 2024
-    Info: Elapsed time: 00:00:03
+    Info: Peak virtual memory: 13770 megabytes
+    Info: Processing ended: Thu Feb 15 04:16:23 2024
+    Info: Elapsed time: 00:00:08
     Info: Total CPU time (on all processors): 00:00:04
 
 
diff --git a/CPLD/MAXII/output_files/RAM2E.fit.summary b/CPLD/MAXII/output_files/RAM2E.fit.summary
index 76f88c0..c933a9a 100644
--- a/CPLD/MAXII/output_files/RAM2E.fit.summary
+++ b/CPLD/MAXII/output_files/RAM2E.fit.summary
@@ -1,4 +1,4 @@
-Fitter Status : Successful - Mon Feb 12 17:00:20 2024
+Fitter Status : Successful - Thu Feb 15 04:16:23 2024
 Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
 Revision Name : RAM2E
 Top-level Entity Name : RAM2E
diff --git a/CPLD/MAXII/output_files/RAM2E.flow.rpt b/CPLD/MAXII/output_files/RAM2E.flow.rpt
index ef43b45..44e71e3 100644
--- a/CPLD/MAXII/output_files/RAM2E.flow.rpt
+++ b/CPLD/MAXII/output_files/RAM2E.flow.rpt
@@ -1,5 +1,5 @@
 Flow report for RAM2E
-Mon Feb 12 17:00:24 2024
+Thu Feb 15 04:16:31 2024
 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
 
 
@@ -41,7 +41,7 @@ https://fpgasoftware.intel.com/eula.
 +---------------------------------------------------------------------+
 ; Flow Summary                                                        ;
 +-----------------------+---------------------------------------------+
-; Flow Status           ; Successful - Mon Feb 12 17:00:22 2024       ;
+; Flow Status           ; Successful - Thu Feb 15 04:16:27 2024       ;
 ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
 ; Revision Name         ; RAM2E                                       ;
 ; Top-level Entity Name ; RAM2E                                       ;
@@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula.
 +-------------------+---------------------+
 ; Option            ; Setting             ;
 +-------------------+---------------------+
-; Start date & time ; 02/12/2024 16:59:52 ;
+; Start date & time ; 02/15/2024 04:15:27 ;
 ; Main task         ; Compilation         ;
 ; Revision Name     ; RAM2E               ;
 +-------------------+---------------------+
@@ -71,7 +71,7 @@ https://fpgasoftware.intel.com/eula.
 +---------------------------------------+------------------------------+---------------+-------------+------------+
 ; Assignment Name                       ; Value                        ; Default Value ; Entity Name ; Section Id ;
 +---------------------------------------+------------------------------+---------------+-------------+------------+
-; COMPILER_SIGNATURE_ID                 ; 121380219419.170777519203424 ; --            ; --          ; --         ;
+; COMPILER_SIGNATURE_ID                 ; 121380219419.170798852707820 ; --            ; --          ; --         ;
 ; MAX_CORE_JUNCTION_TEMP                ; 85                           ; --            ; --          ; --         ;
 ; MIN_CORE_JUNCTION_TEMP                ; 0                            ; --            ; --          ; --         ;
 ; NUM_PARALLEL_PROCESSORS               ; 4                            ; --            ; --          ; --         ;
@@ -86,11 +86,11 @@ https://fpgasoftware.intel.com/eula.
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
 ; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:24     ; 1.0                     ; 13133 MB            ; 00:00:40                           ;
-; Fitter               ; 00:00:03     ; 1.0                     ; 13771 MB            ; 00:00:04                           ;
-; Assembler            ; 00:00:01     ; 1.0                     ; 13100 MB            ; 00:00:01                           ;
-; Timing Analyzer      ; 00:00:01     ; 1.0                     ; 13090 MB            ; 00:00:01                           ;
-; Total                ; 00:00:29     ; --                      ; --                  ; 00:00:46                           ;
+; Analysis & Synthesis ; 00:00:47     ; 1.0                     ; 13146 MB            ; 00:00:47                           ;
+; Fitter               ; 00:00:08     ; 1.0                     ; 13770 MB            ; 00:00:04                           ;
+; Assembler            ; 00:00:02     ; 1.0                     ; 13099 MB            ; 00:00:01                           ;
+; Timing Analyzer      ; 00:00:02     ; 1.0                     ; 13089 MB            ; 00:00:02                           ;
+; Total                ; 00:00:59     ; --                      ; --                  ; 00:00:54                           ;
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
 
 
diff --git a/CPLD/MAXII/output_files/RAM2E.map.rpt b/CPLD/MAXII/output_files/RAM2E.map.rpt
index 2d5584d..850260b 100644
--- a/CPLD/MAXII/output_files/RAM2E.map.rpt
+++ b/CPLD/MAXII/output_files/RAM2E.map.rpt
@@ -1,5 +1,5 @@
 Analysis & Synthesis report for RAM2E
-Mon Feb 12 17:00:15 2024
+Thu Feb 15 04:16:13 2024
 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
 
 
@@ -46,7 +46,7 @@ https://fpgasoftware.intel.com/eula.
 +---------------------------------------------------------------------------+
 ; Analysis & Synthesis Summary                                              ;
 +-----------------------------+---------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Mon Feb 12 17:00:15 2024       ;
+; Analysis & Synthesis Status ; Successful - Thu Feb 15 04:16:13 2024       ;
 ; Quartus Prime Version       ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
 ; Revision Name               ; RAM2E                                       ;
 ; Top-level Entity Name       ; RAM2E                                       ;
@@ -282,7 +282,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 Info: *******************************************************************
 Info: Running Quartus Prime Analysis & Synthesis
     Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
-    Info: Processing started: Mon Feb 12 16:59:51 2024
+    Info: Processing started: Thu Feb 15 04:15:26 2024
 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E-MAXII -c RAM2E
 Info (20032): Parallel compilation is enabled and will use up to 4 processors
 Info (12021): Found 1 design units, including 1 entities, in source file //mac/home/repos/ram2e/cpld/ram2e.v
@@ -294,7 +294,7 @@ Info (12021): Found 2 design units, including 2 entities, in source file ufm.v
     Info (12023): Found entity 2: UFM File: //Mac/Home/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 166
 Info (12127): Elaborating entity "RAM2E" for the top level hierarchy
 Info (12128): Elaborating entity "RAM2E_UFM" for hierarchy "RAM2E_UFM:ram2e_ufm" File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 136
-Info (12128): Elaborating entity "UFM" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst" File: //Mac/Home/Repos/RAM2E/CPLD/UFM-MAX.v Line: 78
+Info (12128): Elaborating entity "UFM" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst" File: //Mac/Home/Repos/RAM2E/CPLD/UFM-MAX.v Line: 77
 Info (12128): Elaborating entity "UFM_altufm_none_lbr" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component" File: //Mac/Home/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 217
 Warning (13024): Output pins are stuck at VCC or GND
     Warning (13410): Pin "nCSout" is stuck at GND File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 75
@@ -316,10 +316,10 @@ Info (21057): Implemented 323 device resources after synthesis - the final resou
     Info (21070): Implemented 1 User Flash Memory blocks
 Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.map.smsg
 Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings
-    Info: Peak virtual memory: 13133 megabytes
-    Info: Processing ended: Mon Feb 12 17:00:15 2024
-    Info: Elapsed time: 00:00:24
-    Info: Total CPU time (on all processors): 00:00:40
+    Info: Peak virtual memory: 13146 megabytes
+    Info: Processing ended: Thu Feb 15 04:16:13 2024
+    Info: Elapsed time: 00:00:47
+    Info: Total CPU time (on all processors): 00:00:47
 
 
 +------------------------------------------+
diff --git a/CPLD/MAXII/output_files/RAM2E.map.summary b/CPLD/MAXII/output_files/RAM2E.map.summary
index ce1b771..18d0796 100644
--- a/CPLD/MAXII/output_files/RAM2E.map.summary
+++ b/CPLD/MAXII/output_files/RAM2E.map.summary
@@ -1,4 +1,4 @@
-Analysis & Synthesis Status : Successful - Mon Feb 12 17:00:15 2024
+Analysis & Synthesis Status : Successful - Thu Feb 15 04:16:13 2024
 Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
 Revision Name : RAM2E
 Top-level Entity Name : RAM2E
diff --git a/CPLD/MAXII/output_files/RAM2E.sta.rpt b/CPLD/MAXII/output_files/RAM2E.sta.rpt
index 6953afd..d12f129 100644
--- a/CPLD/MAXII/output_files/RAM2E.sta.rpt
+++ b/CPLD/MAXII/output_files/RAM2E.sta.rpt
@@ -1,5 +1,5 @@
 Timing Analyzer report for RAM2E
-Mon Feb 12 17:00:24 2024
+Thu Feb 15 04:16:31 2024
 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
 
 
@@ -93,8 +93,8 @@ https://fpgasoftware.intel.com/eula.
 +------------------+--------+--------------------------+
 ; SDC File Path    ; Status ; Read at                  ;
 +------------------+--------+--------------------------+
-; ../RAM2E.sdc     ; OK     ; Mon Feb 12 17:00:24 2024 ;
-; ../RAM2E-MAX.sdc ; OK     ; Mon Feb 12 17:00:24 2024 ;
+; ../RAM2E.sdc     ; OK     ; Thu Feb 15 04:16:31 2024 ;
+; ../RAM2E-MAX.sdc ; OK     ; Thu Feb 15 04:16:31 2024 ;
 +------------------+--------+--------------------------+
 
 
@@ -680,7 +680,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 Info: *******************************************************************
 Info: Running Quartus Prime Timing Analyzer
     Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
-    Info: Processing started: Mon Feb 12 17:00:23 2024
+    Info: Processing started: Thu Feb 15 04:16:29 2024
 Info: Command: quartus_sta RAM2E-MAXII -c RAM2E
 Info: qsta_default_script.tcl version: #1
 Info (20032): Parallel compilation is enabled and will use up to 4 processors
@@ -721,9 +721,9 @@ Info (332001): The selected device family is not supported by the report_metasta
 Info (332102): Design is not fully constrained for setup requirements
 Info (332102): Design is not fully constrained for hold requirements
 Info: Quartus Prime Timing Analyzer was successful. 0 errors, 4 warnings
-    Info: Peak virtual memory: 13090 megabytes
-    Info: Processing ended: Mon Feb 12 17:00:24 2024
-    Info: Elapsed time: 00:00:01
-    Info: Total CPU time (on all processors): 00:00:01
+    Info: Peak virtual memory: 13089 megabytes
+    Info: Processing ended: Thu Feb 15 04:16:31 2024
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:02
 
 
diff --git a/CPLD/MAXV/RAM2E.qws b/CPLD/MAXV/RAM2E.qws
index 9421479..589ae2b 100644
Binary files a/CPLD/MAXV/RAM2E.qws and b/CPLD/MAXV/RAM2E.qws differ
diff --git a/CPLD/MAXV/output_files/RAM2E.asm.rpt b/CPLD/MAXV/output_files/RAM2E.asm.rpt
index 3ddc06b..c432024 100644
--- a/CPLD/MAXV/output_files/RAM2E.asm.rpt
+++ b/CPLD/MAXV/output_files/RAM2E.asm.rpt
@@ -1,5 +1,5 @@
 Assembler report for RAM2E
-Mon Feb 12 17:00:20 2024
+Thu Feb 15 04:16:27 2024
 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
 
 
@@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula.
 +---------------------------------------------------------------+
 ; Assembler Summary                                             ;
 +-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Mon Feb 12 17:00:20 2024 ;
+; Assembler Status      ; Successful - Thu Feb 15 04:16:27 2024 ;
 ; Revision Name         ; RAM2E                                 ;
 ; Top-level Entity Name ; RAM2E                                 ;
 ; Family                ; MAX V                                 ;
@@ -78,14 +78,14 @@ https://fpgasoftware.intel.com/eula.
 Info: *******************************************************************
 Info: Running Quartus Prime Assembler
     Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
-    Info: Processing started: Mon Feb 12 17:00:19 2024
+    Info: Processing started: Thu Feb 15 04:16:25 2024
 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E-MAXV -c RAM2E
 Info (115031): Writing out detailed assembly data for power analysis
 Info (115030): Assembler is generating device programming files
 Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
-    Info: Peak virtual memory: 13104 megabytes
-    Info: Processing ended: Mon Feb 12 17:00:20 2024
-    Info: Elapsed time: 00:00:01
+    Info: Peak virtual memory: 13095 megabytes
+    Info: Processing ended: Thu Feb 15 04:16:27 2024
+    Info: Elapsed time: 00:00:02
     Info: Total CPU time (on all processors): 00:00:01
 
 
diff --git a/CPLD/MAXV/output_files/RAM2E.done b/CPLD/MAXV/output_files/RAM2E.done
index f6da932..92f137e 100644
--- a/CPLD/MAXV/output_files/RAM2E.done
+++ b/CPLD/MAXV/output_files/RAM2E.done
@@ -1 +1 @@
-Mon Feb 12 17:00:24 2024
+Thu Feb 15 04:16:33 2024
diff --git a/CPLD/MAXV/output_files/RAM2E.fit.rpt b/CPLD/MAXV/output_files/RAM2E.fit.rpt
index 85088e4..4c2311a 100644
--- a/CPLD/MAXV/output_files/RAM2E.fit.rpt
+++ b/CPLD/MAXV/output_files/RAM2E.fit.rpt
@@ -1,5 +1,5 @@
 Fitter report for RAM2E
-Mon Feb 12 17:00:18 2024
+Thu Feb 15 04:16:23 2024
 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
 
 
@@ -57,7 +57,7 @@ https://fpgasoftware.intel.com/eula.
 +---------------------------------------------------------------------+
 ; Fitter Summary                                                      ;
 +-----------------------+---------------------------------------------+
-; Fitter Status         ; Successful - Mon Feb 12 17:00:18 2024       ;
+; Fitter Status         ; Successful - Thu Feb 15 04:16:23 2024       ;
 ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
 ; Revision Name         ; RAM2E                                       ;
 ; Top-level Entity Name ; RAM2E                                       ;
@@ -129,13 +129,13 @@ https://fpgasoftware.intel.com/eula.
 ; Number detected on machine ; 4           ;
 ; Maximum allowed            ; 4           ;
 ;                            ;             ;
-; Average used               ; 1.04        ;
+; Average used               ; 1.03        ;
 ; Maximum used               ; 4           ;
 ;                            ;             ;
 ; Usage by Processor         ; % Time Used ;
 ;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;   1.7%      ;
-;     Processors 3-4         ;   1.2%      ;
+;     Processor 2            ;   1.1%      ;
+;     Processors 3-4         ;   0.9%      ;
 +----------------------------+-------------+
 
 
@@ -743,21 +743,21 @@ Info (170189): Fitter placement preparation operations beginning
 Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
 Info (170191): Fitter placement operations beginning
 Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:02
 Info (170193): Fitter routing operations beginning
 Info (170089): 2e+01 ns of routing delay (approximately 1.1% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report.
 Info (170195): Router estimated average interconnect usage is 25% of the available device resources
     Info (170196): Router estimated peak interconnect usage is 25% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
 Info (170202): The Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and routability requirements required full optimization.
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
-Info (11888): Total time spent on timing analysis during the Fitter is 0.42 seconds.
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
+Info (11888): Total time spent on timing analysis during the Fitter is 0.84 seconds.
 Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
 Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.fit.smsg
 Info: Quartus Prime Fitter was successful. 0 errors, 11 warnings
-    Info: Peak virtual memory: 13772 megabytes
-    Info: Processing ended: Mon Feb 12 17:00:18 2024
-    Info: Elapsed time: 00:00:03
-    Info: Total CPU time (on all processors): 00:00:04
+    Info: Peak virtual memory: 13771 megabytes
+    Info: Processing ended: Thu Feb 15 04:16:23 2024
+    Info: Elapsed time: 00:00:08
+    Info: Total CPU time (on all processors): 00:00:05
 
 
 +----------------------------+
diff --git a/CPLD/MAXV/output_files/RAM2E.fit.summary b/CPLD/MAXV/output_files/RAM2E.fit.summary
index 6945252..0cdbb60 100644
--- a/CPLD/MAXV/output_files/RAM2E.fit.summary
+++ b/CPLD/MAXV/output_files/RAM2E.fit.summary
@@ -1,4 +1,4 @@
-Fitter Status : Successful - Mon Feb 12 17:00:18 2024
+Fitter Status : Successful - Thu Feb 15 04:16:23 2024
 Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
 Revision Name : RAM2E
 Top-level Entity Name : RAM2E
diff --git a/CPLD/MAXV/output_files/RAM2E.flow.rpt b/CPLD/MAXV/output_files/RAM2E.flow.rpt
index 1181004..5f4307d 100644
--- a/CPLD/MAXV/output_files/RAM2E.flow.rpt
+++ b/CPLD/MAXV/output_files/RAM2E.flow.rpt
@@ -1,5 +1,5 @@
 Flow report for RAM2E
-Mon Feb 12 17:00:23 2024
+Thu Feb 15 04:16:32 2024
 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
 
 
@@ -41,7 +41,7 @@ https://fpgasoftware.intel.com/eula.
 +---------------------------------------------------------------------+
 ; Flow Summary                                                        ;
 +-----------------------+---------------------------------------------+
-; Flow Status           ; Successful - Mon Feb 12 17:00:20 2024       ;
+; Flow Status           ; Successful - Thu Feb 15 04:16:27 2024       ;
 ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
 ; Revision Name         ; RAM2E                                       ;
 ; Top-level Entity Name ; RAM2E                                       ;
@@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula.
 +-------------------+---------------------+
 ; Option            ; Setting             ;
 +-------------------+---------------------+
-; Start date & time ; 02/12/2024 16:59:50 ;
+; Start date & time ; 02/15/2024 04:15:29 ;
 ; Main task         ; Compilation         ;
 ; Revision Name     ; RAM2E               ;
 +-------------------+---------------------+
@@ -71,7 +71,7 @@ https://fpgasoftware.intel.com/eula.
 +-------------------------------+------------------------------+---------------+-------------+------------+
 ; Assignment Name               ; Value                        ; Default Value ; Entity Name ; Section Id ;
 +-------------------------------+------------------------------+---------------+-------------+------------+
-; COMPILER_SIGNATURE_ID         ; 121380219419.170777519012180 ; --            ; --          ; --         ;
+; COMPILER_SIGNATURE_ID         ; 121380219419.170798852904876 ; --            ; --          ; --         ;
 ; MAX_CORE_JUNCTION_TEMP        ; 85                           ; --            ; --          ; --         ;
 ; MIN_CORE_JUNCTION_TEMP        ; 0                            ; --            ; --          ; --         ;
 ; NUM_PARALLEL_PROCESSORS       ; 4                            ; --            ; --          ; --         ;
@@ -85,11 +85,11 @@ https://fpgasoftware.intel.com/eula.
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
 ; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:24     ; 1.0                     ; 13131 MB            ; 00:00:39                           ;
-; Fitter               ; 00:00:03     ; 1.0                     ; 13772 MB            ; 00:00:04                           ;
-; Assembler            ; 00:00:01     ; 1.0                     ; 13100 MB            ; 00:00:01                           ;
-; Timing Analyzer      ; 00:00:02     ; 1.0                     ; 13094 MB            ; 00:00:01                           ;
-; Total                ; 00:00:30     ; --                      ; --                  ; 00:00:45                           ;
+; Analysis & Synthesis ; 00:00:45     ; 1.0                     ; 13146 MB            ; 00:00:47                           ;
+; Fitter               ; 00:00:08     ; 1.0                     ; 13771 MB            ; 00:00:05                           ;
+; Assembler            ; 00:00:02     ; 1.0                     ; 13091 MB            ; 00:00:01                           ;
+; Timing Analyzer      ; 00:00:03     ; 1.0                     ; 13093 MB            ; 00:00:02                           ;
+; Total                ; 00:00:58     ; --                      ; --                  ; 00:00:55                           ;
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
 
 
diff --git a/CPLD/MAXV/output_files/RAM2E.map.rpt b/CPLD/MAXV/output_files/RAM2E.map.rpt
index 12bf9de..e734fd8 100644
--- a/CPLD/MAXV/output_files/RAM2E.map.rpt
+++ b/CPLD/MAXV/output_files/RAM2E.map.rpt
@@ -1,5 +1,5 @@
 Analysis & Synthesis report for RAM2E
-Mon Feb 12 17:00:14 2024
+Thu Feb 15 04:16:13 2024
 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
 
 
@@ -46,7 +46,7 @@ https://fpgasoftware.intel.com/eula.
 +---------------------------------------------------------------------------+
 ; Analysis & Synthesis Summary                                              ;
 +-----------------------------+---------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Mon Feb 12 17:00:14 2024       ;
+; Analysis & Synthesis Status ; Successful - Thu Feb 15 04:16:13 2024       ;
 ; Quartus Prime Version       ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
 ; Revision Name               ; RAM2E                                       ;
 ; Top-level Entity Name       ; RAM2E                                       ;
@@ -282,7 +282,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 Info: *******************************************************************
 Info: Running Quartus Prime Analysis & Synthesis
     Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
-    Info: Processing started: Mon Feb 12 16:59:50 2024
+    Info: Processing started: Thu Feb 15 04:15:28 2024
 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E-MAXV -c RAM2E
 Info (20032): Parallel compilation is enabled and will use up to 4 processors
 Info (12021): Found 1 design units, including 1 entities, in source file //mac/home/repos/ram2e/cpld/ram2e.v
@@ -294,7 +294,7 @@ Info (12021): Found 2 design units, including 2 entities, in source file ufm.v
     Info (12023): Found entity 2: UFM File: //Mac/Home/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 166
 Info (12127): Elaborating entity "RAM2E" for the top level hierarchy
 Info (12128): Elaborating entity "RAM2E_UFM" for hierarchy "RAM2E_UFM:ram2e_ufm" File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 136
-Info (12128): Elaborating entity "UFM" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst" File: //Mac/Home/Repos/RAM2E/CPLD/UFM-MAX.v Line: 78
+Info (12128): Elaborating entity "UFM" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst" File: //Mac/Home/Repos/RAM2E/CPLD/UFM-MAX.v Line: 77
 Info (12128): Elaborating entity "UFM_altufm_none_p8r" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component" File: //Mac/Home/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 217
 Warning (13024): Output pins are stuck at VCC or GND
     Warning (13410): Pin "nCSout" is stuck at GND File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 75
@@ -316,10 +316,10 @@ Info (21057): Implemented 323 device resources after synthesis - the final resou
     Info (21070): Implemented 1 User Flash Memory blocks
 Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.map.smsg
 Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings
-    Info: Peak virtual memory: 13131 megabytes
-    Info: Processing ended: Mon Feb 12 17:00:14 2024
-    Info: Elapsed time: 00:00:24
-    Info: Total CPU time (on all processors): 00:00:39
+    Info: Peak virtual memory: 13146 megabytes
+    Info: Processing ended: Thu Feb 15 04:16:13 2024
+    Info: Elapsed time: 00:00:45
+    Info: Total CPU time (on all processors): 00:00:47
 
 
 +------------------------------------------+
diff --git a/CPLD/MAXV/output_files/RAM2E.map.summary b/CPLD/MAXV/output_files/RAM2E.map.summary
index b9089fc..a0d20be 100644
--- a/CPLD/MAXV/output_files/RAM2E.map.summary
+++ b/CPLD/MAXV/output_files/RAM2E.map.summary
@@ -1,4 +1,4 @@
-Analysis & Synthesis Status : Successful - Mon Feb 12 17:00:14 2024
+Analysis & Synthesis Status : Successful - Thu Feb 15 04:16:13 2024
 Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
 Revision Name : RAM2E
 Top-level Entity Name : RAM2E
diff --git a/CPLD/MAXV/output_files/RAM2E.sta.rpt b/CPLD/MAXV/output_files/RAM2E.sta.rpt
index de4820b..c4a4926 100644
--- a/CPLD/MAXV/output_files/RAM2E.sta.rpt
+++ b/CPLD/MAXV/output_files/RAM2E.sta.rpt
@@ -1,5 +1,5 @@
 Timing Analyzer report for RAM2E
-Mon Feb 12 17:00:23 2024
+Thu Feb 15 04:16:32 2024
 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
 
 
@@ -93,8 +93,8 @@ https://fpgasoftware.intel.com/eula.
 +------------------+--------+--------------------------+
 ; SDC File Path    ; Status ; Read at                  ;
 +------------------+--------+--------------------------+
-; ../RAM2E.sdc     ; OK     ; Mon Feb 12 17:00:23 2024 ;
-; ../RAM2E-MAX.sdc ; OK     ; Mon Feb 12 17:00:23 2024 ;
+; ../RAM2E.sdc     ; OK     ; Thu Feb 15 04:16:31 2024 ;
+; ../RAM2E-MAX.sdc ; OK     ; Thu Feb 15 04:16:31 2024 ;
 +------------------+--------+--------------------------+
 
 
@@ -680,7 +680,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 Info: *******************************************************************
 Info: Running Quartus Prime Timing Analyzer
     Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
-    Info: Processing started: Mon Feb 12 17:00:21 2024
+    Info: Processing started: Thu Feb 15 04:16:29 2024
 Info: Command: quartus_sta RAM2E-MAXV -c RAM2E
 Info: qsta_default_script.tcl version: #1
 Info (20032): Parallel compilation is enabled and will use up to 4 processors
@@ -721,9 +721,9 @@ Info (332001): The selected device family is not supported by the report_metasta
 Info (332102): Design is not fully constrained for setup requirements
 Info (332102): Design is not fully constrained for hold requirements
 Info: Quartus Prime Timing Analyzer was successful. 0 errors, 4 warnings
-    Info: Peak virtual memory: 13094 megabytes
-    Info: Processing ended: Mon Feb 12 17:00:23 2024
-    Info: Elapsed time: 00:00:02
-    Info: Total CPU time (on all processors): 00:00:01
+    Info: Peak virtual memory: 13093 megabytes
+    Info: Processing ended: Thu Feb 15 04:16:32 2024
+    Info: Elapsed time: 00:00:03
+    Info: Total CPU time (on all processors): 00:00:02
 
 
diff --git a/CPLD/RAM2E.v b/CPLD/RAM2E.v
index 216047b..e54abcf 100644
--- a/CPLD/RAM2E.v
+++ b/CPLD/RAM2E.v
@@ -66,7 +66,7 @@ module RAM2E(C14M, PHI1, LED,
     inout [7:0] RD;
     wire [7:0] RDout = Ready ? Din[7:0] : 8'h00;
     reg RDOE;
-    always @(posedge C14M) begin 
+    always @(posedge C14M) begin
         RDOE <= (!Ready) || (!nEN80 && !nWE && (S==4'hA || S==4'hB));
     end
     assign RD[7:0] = RDOE ? RDout[7:0] : 8'bZ;
@@ -129,7 +129,7 @@ module RAM2E(C14M, PHI1, LED,
     /* Chip-specific UFM interface */
     wire [7:0] ChipCmdNum;
     RAM2E_UFM ram2e_ufm (
-        .C14M(C14M), .S(S), .FS(FS), .CS(CS), .Ready(Ready),
+        .C14M(C14M), .S(S), .FS(FS), .CS(CS),
         .RWSel(RWSel), .D(Din),
         .RWMask(RWMask), .LEDEN(LEDEN),
         .CmdRWMaskSet(CmdRWMaskSet), .CmdLEDSet(CmdLEDSet),
@@ -148,11 +148,11 @@ module RAM2E(C14M, PHI1, LED,
                 // Chip detection command
                 CmdSetRWBankFFChip <= Din[7:0]==ChipCmdNum[7:0];
                 // LED exists detect command
-                CmdSetRWBankFFLED <= Din[7:0]==8'hF0;
+                CmdSetRWBankFFLED <=  Din[7:0]==8'hF0;
                 // Volatile settings commands
-                CmdRWMaskSet <=      Din[7:0]==8'hE0;
-                CmdLEDSet <=         Din[7:0]==8'hE2;
-                CmdLEDGet <=         Din[7:0]==8'hE3;
+                CmdRWMaskSet <=       Din[7:0]==8'hE0;
+                CmdLEDSet <=          Din[7:0]==8'hE2;
+                CmdLEDGet <=          Din[7:0]==8'hE3;
             end else begin // Reset command triggers
                 CmdSetRWBankFFChip <= 0;
                 CmdSetRWBankFFLED <= 0;
@@ -216,10 +216,10 @@ module RAM2E(C14M, PHI1, LED,
                     nRWE <= 1'b0;
                 end
             endcase
+            BA[1:0] <= 2'b00;
             case (FS[4:3])
                 2'b00, 2'b01: begin
                     // Mode register contents
-                    BA[1:0] <= 2'b00;   // Reserved
                     RA[11] <= 1'b0;     // Reserved
                     RA[10] <= !FS[1];   // reserved / "all"
                     RA[9] <= 1'b1;      // "1" for single write mode
@@ -229,11 +229,9 @@ module RAM2E(C14M, PHI1, LED,
                     RA[3] <= 1'b0;      // "0" for sequential burst (not used)
                     RA[2:0] <= 3'b000;  // "0" for burst length 1 (no burst)
                 end 2'b10: begin
-                    BA[1:0] <= 2'b00;
                     RA[11:8] <= 4'h0;
                     RA[7:0] <= FS[14:7];
                 end 2'b11: begin
-                    BA[1:0] <= 2'b00;
                     RA[11:3] <= 9'h000;
                     RA[2:1] <= FS[6:5];
                     RA[0] <= FS[1];
diff --git a/CPLD/UFM-LCMXO2.v b/CPLD/UFM-LCMXO2.v
index 36a175a..f0d76c8 100644
--- a/CPLD/UFM-LCMXO2.v
+++ b/CPLD/UFM-LCMXO2.v
@@ -1,4 +1,4 @@
-module RAM2E_UFM(C14M, S, FS, CS, Ready,
+module RAM2E_UFM(C14M, S, FS, CS,
                  RWSel, D,
                  RWMask, LEDEN,
                  CmdRWMaskSet, CmdLEDSet,
@@ -7,7 +7,6 @@ module RAM2E_UFM(C14M, S, FS, CS, Ready,
     input [3:0] S;
     input [15:0] FS;
     input [2:0] CS;
-	input Ready;
     input RWSel;
     input [7:0] D;
     output reg [7:0] RWMask;
diff --git a/CPLD/UFM-MAX.v b/CPLD/UFM-MAX.v
index a4ff3eb..0b78452 100644
--- a/CPLD/UFM-MAX.v
+++ b/CPLD/UFM-MAX.v
@@ -1,4 +1,4 @@
-module RAM2E_UFM(C14M, S, FS, CS, Ready,
+module RAM2E_UFM(C14M, S, FS, CS,
                  RWSel, D,
                  RWMask, LEDEN,
 				 CmdRWMaskSet, CmdLEDSet,
@@ -7,7 +7,6 @@ module RAM2E_UFM(C14M, S, FS, CS, Ready,
 	input [3:0] S;
     input [15:0] FS;
     input [2:0] CS;
-    input Ready;
 	input RWSel;
 	input [7:0] D;
     output reg [7:0] RWMask;