From 520e7edbdfdaa981e3843a81cb53f3f1d6f3dff1 Mon Sep 17 00:00:00 2001
From: Zane Kaminski <zanekaminski@gmail.com>
Date: Thu, 11 Jan 2024 09:34:47 -0500
Subject: [PATCH] MAX II/V 2.1 RC1

---
 CPLD/MAXII/RAM2E.qws                      | Bin 619 -> 619 bytes
 CPLD/MAXII/output_files/RAM2E.asm.rpt     |  10 +++++-----
 CPLD/MAXII/output_files/RAM2E.done        |   2 +-
 CPLD/MAXII/output_files/RAM2E.fit.rpt     |  20 ++++++++++----------
 CPLD/MAXII/output_files/RAM2E.fit.summary |   2 +-
 CPLD/MAXII/output_files/RAM2E.flow.rpt    |  18 +++++++++---------
 CPLD/MAXII/output_files/RAM2E.map.rpt     |  14 +++++++-------
 CPLD/MAXII/output_files/RAM2E.map.summary |   2 +-
 CPLD/MAXII/output_files/RAM2E.sta.rpt     |  17 +++++++++--------
 CPLD/MAXV/RAM2E.qws                       | Bin 619 -> 619 bytes
 CPLD/MAXV/output_files/RAM2E.asm.rpt      |  10 +++++-----
 CPLD/MAXV/output_files/RAM2E.done         |   2 +-
 CPLD/MAXV/output_files/RAM2E.fit.rpt      |  20 ++++++++++----------
 CPLD/MAXV/output_files/RAM2E.fit.summary  |   2 +-
 CPLD/MAXV/output_files/RAM2E.flow.rpt     |  18 +++++++++---------
 CPLD/MAXV/output_files/RAM2E.map.rpt      |  14 +++++++-------
 CPLD/MAXV/output_files/RAM2E.map.summary  |   2 +-
 CPLD/MAXV/output_files/RAM2E.sta.rpt      |  14 +++++++-------
 18 files changed, 84 insertions(+), 83 deletions(-)

diff --git a/CPLD/MAXII/RAM2E.qws b/CPLD/MAXII/RAM2E.qws
index 07ba2044a4ba1c71d762bdeda4996750b6788d1c..e99fdcd84f187d47f6f5f1b9e5273783401459eb 100644
GIT binary patch
delta 57
zcmaFO@|tDBBF4yxi>(DC85kH682<nN&%nUQ#K6E5x$%7}qj&^R6byh8|3DbTVPXIP
DF+vk;

delta 57
zcmaFO@|tDBB1W!>i>(E@7#J8582<nN&%nUQ#K6GBwefu_qc|r}6byh8|3DbTVPXIP
D1LYDh

diff --git a/CPLD/MAXII/output_files/RAM2E.asm.rpt b/CPLD/MAXII/output_files/RAM2E.asm.rpt
index 6d4d777..32f5068 100644
--- a/CPLD/MAXII/output_files/RAM2E.asm.rpt
+++ b/CPLD/MAXII/output_files/RAM2E.asm.rpt
@@ -1,5 +1,5 @@
 Assembler report for RAM2E
-Thu Dec 28 23:09:46 2023
+Thu Jan 11 09:29:25 2024
 Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
 
 
@@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula.
 +---------------------------------------------------------------+
 ; Assembler Summary                                             ;
 +-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Thu Dec 28 23:09:46 2023 ;
+; Assembler Status      ; Successful - Thu Jan 11 09:29:25 2024 ;
 ; Revision Name         ; RAM2E                                 ;
 ; Top-level Entity Name ; RAM2E                                 ;
 ; Family                ; MAX II                                ;
@@ -78,13 +78,13 @@ https://fpgasoftware.intel.com/eula.
 Info: *******************************************************************
 Info: Running Quartus Prime Assembler
     Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
-    Info: Processing started: Thu Dec 28 23:09:46 2023
+    Info: Processing started: Thu Jan 11 09:29:24 2024
 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E-MAXII -c RAM2E
 Info (115031): Writing out detailed assembly data for power analysis
 Info (115030): Assembler is generating device programming files
 Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
-    Info: Peak virtual memory: 13071 megabytes
-    Info: Processing ended: Thu Dec 28 23:09:47 2023
+    Info: Peak virtual memory: 13074 megabytes
+    Info: Processing ended: Thu Jan 11 09:29:25 2024
     Info: Elapsed time: 00:00:01
     Info: Total CPU time (on all processors): 00:00:01
 
diff --git a/CPLD/MAXII/output_files/RAM2E.done b/CPLD/MAXII/output_files/RAM2E.done
index b88a509..6247ee1 100644
--- a/CPLD/MAXII/output_files/RAM2E.done
+++ b/CPLD/MAXII/output_files/RAM2E.done
@@ -1 +1 @@
-Thu Dec 28 23:09:51 2023
+Thu Jan 11 09:29:29 2024
diff --git a/CPLD/MAXII/output_files/RAM2E.fit.rpt b/CPLD/MAXII/output_files/RAM2E.fit.rpt
index 972e71e..7bdb5cd 100644
--- a/CPLD/MAXII/output_files/RAM2E.fit.rpt
+++ b/CPLD/MAXII/output_files/RAM2E.fit.rpt
@@ -1,5 +1,5 @@
 Fitter report for RAM2E
-Thu Dec 28 23:09:44 2023
+Thu Jan 11 09:29:23 2024
 Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
 
 
@@ -57,7 +57,7 @@ https://fpgasoftware.intel.com/eula.
 +-------------------------------------------------------------------------------------+
 ; Fitter Summary                                                                      ;
 +-----------------------+-------------------------------------------------------------+
-; Fitter Status         ; Successful - Thu Dec 28 23:09:44 2023                       ;
+; Fitter Status         ; Successful - Thu Jan 11 09:29:23 2024                       ;
 ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
 ; Revision Name         ; RAM2E                                                       ;
 ; Top-level Entity Name ; RAM2E                                                       ;
@@ -129,13 +129,13 @@ https://fpgasoftware.intel.com/eula.
 ; Number detected on machine ; 4           ;
 ; Maximum allowed            ; 4           ;
 ;                            ;             ;
-; Average used               ; 1.03        ;
+; Average used               ; 1.04        ;
 ; Maximum used               ; 4           ;
 ;                            ;             ;
 ; Usage by Processor         ; % Time Used ;
 ;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;   1.1%      ;
-;     Processors 3-4         ;   1.0%      ;
+;     Processor 2            ;   1.8%      ;
+;     Processors 3-4         ;   1.3%      ;
 +----------------------------+-------------+
 
 
@@ -728,14 +728,14 @@ Info (170089): 5e+01 ns of routing delay (approximately 3.0% of available device
 Info (170195): Router estimated average interconnect usage is 24% of the available device resources
     Info (170196): Router estimated peak interconnect usage is 24% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
 Info (170202): The Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and routability requirements required full optimization.
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
-Info (11888): Total time spent on timing analysis during the Fitter is 0.84 seconds.
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
+Info (11888): Total time spent on timing analysis during the Fitter is 0.44 seconds.
 Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
 Info (144001): Generated suppressed messages file Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.fit.smsg
 Info: Quartus Prime Fitter was successful. 0 errors, 1 warning
-    Info: Peak virtual memory: 13747 megabytes
-    Info: Processing ended: Thu Dec 28 23:09:44 2023
-    Info: Elapsed time: 00:00:04
+    Info: Peak virtual memory: 13748 megabytes
+    Info: Processing ended: Thu Jan 11 09:29:23 2024
+    Info: Elapsed time: 00:00:03
     Info: Total CPU time (on all processors): 00:00:04
 
 
diff --git a/CPLD/MAXII/output_files/RAM2E.fit.summary b/CPLD/MAXII/output_files/RAM2E.fit.summary
index 304f616..dedcf93 100644
--- a/CPLD/MAXII/output_files/RAM2E.fit.summary
+++ b/CPLD/MAXII/output_files/RAM2E.fit.summary
@@ -1,4 +1,4 @@
-Fitter Status : Successful - Thu Dec 28 23:09:44 2023
+Fitter Status : Successful - Thu Jan 11 09:29:23 2024
 Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
 Revision Name : RAM2E
 Top-level Entity Name : RAM2E
diff --git a/CPLD/MAXII/output_files/RAM2E.flow.rpt b/CPLD/MAXII/output_files/RAM2E.flow.rpt
index 3d4dbde..9fab878 100644
--- a/CPLD/MAXII/output_files/RAM2E.flow.rpt
+++ b/CPLD/MAXII/output_files/RAM2E.flow.rpt
@@ -1,5 +1,5 @@
 Flow report for RAM2E
-Thu Dec 28 23:09:50 2023
+Thu Jan 11 09:29:28 2024
 Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
 
 
@@ -41,7 +41,7 @@ https://fpgasoftware.intel.com/eula.
 +-------------------------------------------------------------------------------------+
 ; Flow Summary                                                                        ;
 +-----------------------+-------------------------------------------------------------+
-; Flow Status           ; Successful - Thu Dec 28 23:09:46 2023                       ;
+; Flow Status           ; Successful - Thu Jan 11 09:29:25 2024                       ;
 ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
 ; Revision Name         ; RAM2E                                                       ;
 ; Top-level Entity Name ; RAM2E                                                       ;
@@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula.
 +-------------------+---------------------+
 ; Option            ; Setting             ;
 +-------------------+---------------------+
-; Start date & time ; 12/28/2023 23:09:12 ;
+; Start date & time ; 01/11/2024 09:28:55 ;
 ; Main task         ; Compilation         ;
 ; Revision Name     ; RAM2E               ;
 +-------------------+---------------------+
@@ -71,7 +71,7 @@ https://fpgasoftware.intel.com/eula.
 +---------------------------------------+------------------------------+---------------+-------------+------------+
 ; Assignment Name                       ; Value                        ; Default Value ; Entity Name ; Section Id ;
 +---------------------------------------+------------------------------+---------------+-------------+------------+
-; COMPILER_SIGNATURE_ID                 ; 121381084694.170382295203604 ; --            ; --          ; --         ;
+; COMPILER_SIGNATURE_ID                 ; 121381084694.170498333501484 ; --            ; --          ; --         ;
 ; MAX_CORE_JUNCTION_TEMP                ; 85                           ; --            ; --          ; --         ;
 ; MIN_CORE_JUNCTION_TEMP                ; 0                            ; --            ; --          ; --         ;
 ; NUM_PARALLEL_PROCESSORS               ; 4                            ; --            ; --          ; --         ;
@@ -86,11 +86,11 @@ https://fpgasoftware.intel.com/eula.
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
 ; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:28     ; 1.0                     ; 13113 MB            ; 00:00:42                           ;
-; Fitter               ; 00:00:04     ; 1.0                     ; 13747 MB            ; 00:00:04                           ;
-; Assembler            ; 00:00:00     ; 1.0                     ; 13067 MB            ; 00:00:01                           ;
-; Timing Analyzer      ; 00:00:02     ; 1.0                     ; 13064 MB            ; 00:00:02                           ;
-; Total                ; 00:00:34     ; --                      ; --                  ; 00:00:49                           ;
+; Analysis & Synthesis ; 00:00:25     ; 1.0                     ; 13116 MB            ; 00:00:41                           ;
+; Fitter               ; 00:00:03     ; 1.0                     ; 13748 MB            ; 00:00:04                           ;
+; Assembler            ; 00:00:01     ; 1.0                     ; 13070 MB            ; 00:00:01                           ;
+; Timing Analyzer      ; 00:00:02     ; 1.0                     ; 13066 MB            ; 00:00:01                           ;
+; Total                ; 00:00:31     ; --                      ; --                  ; 00:00:47                           ;
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
 
 
diff --git a/CPLD/MAXII/output_files/RAM2E.map.rpt b/CPLD/MAXII/output_files/RAM2E.map.rpt
index d5d2070..f932d7f 100644
--- a/CPLD/MAXII/output_files/RAM2E.map.rpt
+++ b/CPLD/MAXII/output_files/RAM2E.map.rpt
@@ -1,5 +1,5 @@
 Analysis & Synthesis report for RAM2E
-Thu Dec 28 23:09:39 2023
+Thu Jan 11 09:29:19 2024
 Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
 
 
@@ -46,7 +46,7 @@ https://fpgasoftware.intel.com/eula.
 +-------------------------------------------------------------------------------------------+
 ; Analysis & Synthesis Summary                                                              ;
 +-----------------------------+-------------------------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Thu Dec 28 23:09:39 2023                       ;
+; Analysis & Synthesis Status ; Successful - Thu Jan 11 09:29:19 2024                       ;
 ; Quartus Prime Version       ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
 ; Revision Name               ; RAM2E                                                       ;
 ; Top-level Entity Name       ; RAM2E                                                       ;
@@ -281,7 +281,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 Info: *******************************************************************
 Info: Running Quartus Prime Analysis & Synthesis
     Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
-    Info: Processing started: Thu Dec 28 23:09:11 2023
+    Info: Processing started: Thu Jan 11 09:28:54 2024
 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E-MAXII -c RAM2E
 Info (20032): Parallel compilation is enabled and will use up to 4 processors
 Info (12021): Found 1 design units, including 1 entities, in source file /repos/ram2e/cpld/ram2e.v
@@ -315,10 +315,10 @@ Info (21057): Implemented 315 device resources after synthesis - the final resou
     Info (21070): Implemented 1 User Flash Memory blocks
 Info (144001): Generated suppressed messages file Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.map.smsg
 Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings
-    Info: Peak virtual memory: 13113 megabytes
-    Info: Processing ended: Thu Dec 28 23:09:39 2023
-    Info: Elapsed time: 00:00:28
-    Info: Total CPU time (on all processors): 00:00:42
+    Info: Peak virtual memory: 13116 megabytes
+    Info: Processing ended: Thu Jan 11 09:29:19 2024
+    Info: Elapsed time: 00:00:25
+    Info: Total CPU time (on all processors): 00:00:41
 
 
 +------------------------------------------+
diff --git a/CPLD/MAXII/output_files/RAM2E.map.summary b/CPLD/MAXII/output_files/RAM2E.map.summary
index 0d1b334..ce6c7eb 100644
--- a/CPLD/MAXII/output_files/RAM2E.map.summary
+++ b/CPLD/MAXII/output_files/RAM2E.map.summary
@@ -1,4 +1,4 @@
-Analysis & Synthesis Status : Successful - Thu Dec 28 23:09:39 2023
+Analysis & Synthesis Status : Successful - Thu Jan 11 09:29:19 2024
 Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
 Revision Name : RAM2E
 Top-level Entity Name : RAM2E
diff --git a/CPLD/MAXII/output_files/RAM2E.sta.rpt b/CPLD/MAXII/output_files/RAM2E.sta.rpt
index c4c394c..baa9ce5 100644
--- a/CPLD/MAXII/output_files/RAM2E.sta.rpt
+++ b/CPLD/MAXII/output_files/RAM2E.sta.rpt
@@ -1,5 +1,5 @@
 Timing Analyzer report for RAM2E
-Thu Dec 28 23:09:50 2023
+Thu Jan 11 09:29:28 2024
 Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
 
 
@@ -80,10 +80,11 @@ https://fpgasoftware.intel.com/eula.
 ; Maximum allowed            ; 4           ;
 ;                            ;             ;
 ; Average used               ; 1.00        ;
-; Maximum used               ; 1           ;
+; Maximum used               ; 2           ;
 ;                            ;             ;
 ; Usage by Processor         ; % Time Used ;
 ;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   0.1%      ;
 +----------------------------+-------------+
 
 
@@ -92,8 +93,8 @@ https://fpgasoftware.intel.com/eula.
 +------------------+--------+--------------------------+
 ; SDC File Path    ; Status ; Read at                  ;
 +------------------+--------+--------------------------+
-; ../RAM2E.sdc     ; OK     ; Thu Dec 28 23:09:50 2023 ;
-; ../RAM2E-MAX.sdc ; OK     ; Thu Dec 28 23:09:50 2023 ;
+; ../RAM2E.sdc     ; OK     ; Thu Jan 11 09:29:28 2024 ;
+; ../RAM2E-MAX.sdc ; OK     ; Thu Jan 11 09:29:28 2024 ;
 +------------------+--------+--------------------------+
 
 
@@ -678,7 +679,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 Info: *******************************************************************
 Info: Running Quartus Prime Timing Analyzer
     Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
-    Info: Processing started: Thu Dec 28 23:09:48 2023
+    Info: Processing started: Thu Jan 11 09:29:26 2024
 Info: Command: quartus_sta RAM2E-MAXII -c RAM2E
 Info: qsta_default_script.tcl version: #1
 Info (20032): Parallel compilation is enabled and will use up to 4 processors
@@ -719,9 +720,9 @@ Warning (332009): The launch and latch times for the relationship between source
 Info (332102): Design is not fully constrained for setup requirements
 Info (332102): Design is not fully constrained for hold requirements
 Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
-    Info: Peak virtual memory: 13064 megabytes
-    Info: Processing ended: Thu Dec 28 23:09:50 2023
+    Info: Peak virtual memory: 13066 megabytes
+    Info: Processing ended: Thu Jan 11 09:29:28 2024
     Info: Elapsed time: 00:00:02
-    Info: Total CPU time (on all processors): 00:00:02
+    Info: Total CPU time (on all processors): 00:00:01
 
 
diff --git a/CPLD/MAXV/RAM2E.qws b/CPLD/MAXV/RAM2E.qws
index f6f69ce180188e29d6210913345135901ddd90b8..e99fdcd84f187d47f6f5f1b9e5273783401459eb 100644
GIT binary patch
delta 57
zcmaFO@|tDBBF4yxi>(DC85kH682<nN&%nUQ#K6E5x$%7}qj&^R6byh8|3DbTVPXIP
DF+vk;

delta 57
zcmaFO@|tDBB1Z0si>(E@85kH682<nN&%nUQ#K6GBz43i2qc|5(6byh8|3DbTVPXIP
D1b7lO

diff --git a/CPLD/MAXV/output_files/RAM2E.asm.rpt b/CPLD/MAXV/output_files/RAM2E.asm.rpt
index ecac003..6b6f25c 100644
--- a/CPLD/MAXV/output_files/RAM2E.asm.rpt
+++ b/CPLD/MAXV/output_files/RAM2E.asm.rpt
@@ -1,5 +1,5 @@
 Assembler report for RAM2E
-Thu Dec 28 23:09:48 2023
+Thu Jan 11 09:29:26 2024
 Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
 
 
@@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula.
 +---------------------------------------------------------------+
 ; Assembler Summary                                             ;
 +-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Thu Dec 28 23:09:48 2023 ;
+; Assembler Status      ; Successful - Thu Jan 11 09:29:26 2024 ;
 ; Revision Name         ; RAM2E                                 ;
 ; Top-level Entity Name ; RAM2E                                 ;
 ; Family                ; MAX V                                 ;
@@ -78,13 +78,13 @@ https://fpgasoftware.intel.com/eula.
 Info: *******************************************************************
 Info: Running Quartus Prime Assembler
     Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
-    Info: Processing started: Thu Dec 28 23:09:47 2023
+    Info: Processing started: Thu Jan 11 09:29:25 2024
 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E-MAXV -c RAM2E
 Info (115031): Writing out detailed assembly data for power analysis
 Info (115030): Assembler is generating device programming files
 Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
-    Info: Peak virtual memory: 13070 megabytes
-    Info: Processing ended: Thu Dec 28 23:09:48 2023
+    Info: Peak virtual memory: 13073 megabytes
+    Info: Processing ended: Thu Jan 11 09:29:26 2024
     Info: Elapsed time: 00:00:01
     Info: Total CPU time (on all processors): 00:00:01
 
diff --git a/CPLD/MAXV/output_files/RAM2E.done b/CPLD/MAXV/output_files/RAM2E.done
index aacbb63..6247ee1 100644
--- a/CPLD/MAXV/output_files/RAM2E.done
+++ b/CPLD/MAXV/output_files/RAM2E.done
@@ -1 +1 @@
-Thu Dec 28 23:09:52 2023
+Thu Jan 11 09:29:29 2024
diff --git a/CPLD/MAXV/output_files/RAM2E.fit.rpt b/CPLD/MAXV/output_files/RAM2E.fit.rpt
index 4ec5759..11be2c7 100644
--- a/CPLD/MAXV/output_files/RAM2E.fit.rpt
+++ b/CPLD/MAXV/output_files/RAM2E.fit.rpt
@@ -1,5 +1,5 @@
 Fitter report for RAM2E
-Thu Dec 28 23:09:45 2023
+Thu Jan 11 09:29:24 2024
 Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
 
 
@@ -57,7 +57,7 @@ https://fpgasoftware.intel.com/eula.
 +-------------------------------------------------------------------------------------+
 ; Fitter Summary                                                                      ;
 +-----------------------+-------------------------------------------------------------+
-; Fitter Status         ; Successful - Thu Dec 28 23:09:45 2023                       ;
+; Fitter Status         ; Successful - Thu Jan 11 09:29:24 2024                       ;
 ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
 ; Revision Name         ; RAM2E                                                       ;
 ; Top-level Entity Name ; RAM2E                                                       ;
@@ -129,13 +129,13 @@ https://fpgasoftware.intel.com/eula.
 ; Number detected on machine ; 4           ;
 ; Maximum allowed            ; 4           ;
 ;                            ;             ;
-; Average used               ; 1.03        ;
+; Average used               ; 1.04        ;
 ; Maximum used               ; 4           ;
 ;                            ;             ;
 ; Usage by Processor         ; % Time Used ;
 ;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;   1.0%      ;
-;     Processors 3-4         ;   0.9%      ;
+;     Processor 2            ;   1.6%      ;
+;     Processors 3-4         ;   1.2%      ;
 +----------------------------+-------------+
 
 
@@ -720,7 +720,7 @@ Info (176234): Starting register packing
 Info (186468): Started processing fast register assignments
 Info (186469): Finished processing fast register assignments
 Info (176235): Finished register packing
-Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
 Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
 Info (170189): Fitter placement preparation operations beginning
 Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
@@ -732,13 +732,13 @@ Info (170195): Router estimated average interconnect usage is 23% of the availab
     Info (170196): Router estimated peak interconnect usage is 23% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
 Info (170202): The Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and routability requirements required full optimization.
 Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
-Info (11888): Total time spent on timing analysis during the Fitter is 0.67 seconds.
+Info (11888): Total time spent on timing analysis during the Fitter is 0.40 seconds.
 Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
 Info (144001): Generated suppressed messages file Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.fit.smsg
 Info: Quartus Prime Fitter was successful. 0 errors, 1 warning
-    Info: Peak virtual memory: 13748 megabytes
-    Info: Processing ended: Thu Dec 28 23:09:45 2023
-    Info: Elapsed time: 00:00:04
+    Info: Peak virtual memory: 13751 megabytes
+    Info: Processing ended: Thu Jan 11 09:29:24 2024
+    Info: Elapsed time: 00:00:03
     Info: Total CPU time (on all processors): 00:00:04
 
 
diff --git a/CPLD/MAXV/output_files/RAM2E.fit.summary b/CPLD/MAXV/output_files/RAM2E.fit.summary
index 0ef0041..5e8be28 100644
--- a/CPLD/MAXV/output_files/RAM2E.fit.summary
+++ b/CPLD/MAXV/output_files/RAM2E.fit.summary
@@ -1,4 +1,4 @@
-Fitter Status : Successful - Thu Dec 28 23:09:45 2023
+Fitter Status : Successful - Thu Jan 11 09:29:24 2024
 Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
 Revision Name : RAM2E
 Top-level Entity Name : RAM2E
diff --git a/CPLD/MAXV/output_files/RAM2E.flow.rpt b/CPLD/MAXV/output_files/RAM2E.flow.rpt
index 13640c2..4e4737d 100644
--- a/CPLD/MAXV/output_files/RAM2E.flow.rpt
+++ b/CPLD/MAXV/output_files/RAM2E.flow.rpt
@@ -1,5 +1,5 @@
 Flow report for RAM2E
-Thu Dec 28 23:09:52 2023
+Thu Jan 11 09:29:29 2024
 Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
 
 
@@ -41,7 +41,7 @@ https://fpgasoftware.intel.com/eula.
 +-------------------------------------------------------------------------------------+
 ; Flow Summary                                                                        ;
 +-----------------------+-------------------------------------------------------------+
-; Flow Status           ; Successful - Thu Dec 28 23:09:48 2023                       ;
+; Flow Status           ; Successful - Thu Jan 11 09:29:26 2024                       ;
 ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
 ; Revision Name         ; RAM2E                                                       ;
 ; Top-level Entity Name ; RAM2E                                                       ;
@@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula.
 +-------------------+---------------------+
 ; Option            ; Setting             ;
 +-------------------+---------------------+
-; Start date & time ; 12/28/2023 23:09:13 ;
+; Start date & time ; 01/11/2024 09:28:56 ;
 ; Main task         ; Compilation         ;
 ; Revision Name     ; RAM2E               ;
 +-------------------+---------------------+
@@ -71,7 +71,7 @@ https://fpgasoftware.intel.com/eula.
 +-------------------------------+------------------------------+---------------+-------------+------------+
 ; Assignment Name               ; Value                        ; Default Value ; Entity Name ; Section Id ;
 +-------------------------------+------------------------------+---------------+-------------+------------+
-; COMPILER_SIGNATURE_ID         ; 121381084694.170382295304664 ; --            ; --          ; --         ;
+; COMPILER_SIGNATURE_ID         ; 121381084694.170498333604684 ; --            ; --          ; --         ;
 ; MAX_CORE_JUNCTION_TEMP        ; 85                           ; --            ; --          ; --         ;
 ; MIN_CORE_JUNCTION_TEMP        ; 0                            ; --            ; --          ; --         ;
 ; NUM_PARALLEL_PROCESSORS       ; 4                            ; --            ; --          ; --         ;
@@ -85,11 +85,11 @@ https://fpgasoftware.intel.com/eula.
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
 ; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:28     ; 1.0                     ; 13113 MB            ; 00:00:41                           ;
-; Fitter               ; 00:00:04     ; 1.0                     ; 13748 MB            ; 00:00:04                           ;
-; Assembler            ; 00:00:01     ; 1.0                     ; 13069 MB            ; 00:00:01                           ;
-; Timing Analyzer      ; 00:00:03     ; 1.0                     ; 13067 MB            ; 00:00:02                           ;
-; Total                ; 00:00:36     ; --                      ; --                  ; 00:00:48                           ;
+; Analysis & Synthesis ; 00:00:23     ; 1.0                     ; 13116 MB            ; 00:00:40                           ;
+; Fitter               ; 00:00:03     ; 1.0                     ; 13751 MB            ; 00:00:04                           ;
+; Assembler            ; 00:00:01     ; 1.0                     ; 13072 MB            ; 00:00:01                           ;
+; Timing Analyzer      ; 00:00:02     ; 1.0                     ; 13069 MB            ; 00:00:01                           ;
+; Total                ; 00:00:29     ; --                      ; --                  ; 00:00:46                           ;
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
 
 
diff --git a/CPLD/MAXV/output_files/RAM2E.map.rpt b/CPLD/MAXV/output_files/RAM2E.map.rpt
index 51a17f5..ce00533 100644
--- a/CPLD/MAXV/output_files/RAM2E.map.rpt
+++ b/CPLD/MAXV/output_files/RAM2E.map.rpt
@@ -1,5 +1,5 @@
 Analysis & Synthesis report for RAM2E
-Thu Dec 28 23:09:40 2023
+Thu Jan 11 09:29:19 2024
 Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
 
 
@@ -46,7 +46,7 @@ https://fpgasoftware.intel.com/eula.
 +-------------------------------------------------------------------------------------------+
 ; Analysis & Synthesis Summary                                                              ;
 +-----------------------------+-------------------------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Thu Dec 28 23:09:40 2023                       ;
+; Analysis & Synthesis Status ; Successful - Thu Jan 11 09:29:19 2024                       ;
 ; Quartus Prime Version       ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
 ; Revision Name               ; RAM2E                                                       ;
 ; Top-level Entity Name       ; RAM2E                                                       ;
@@ -281,7 +281,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 Info: *******************************************************************
 Info: Running Quartus Prime Analysis & Synthesis
     Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
-    Info: Processing started: Thu Dec 28 23:09:12 2023
+    Info: Processing started: Thu Jan 11 09:28:56 2024
 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E-MAXV -c RAM2E
 Info (20032): Parallel compilation is enabled and will use up to 4 processors
 Info (12021): Found 1 design units, including 1 entities, in source file /repos/ram2e/cpld/ram2e.v
@@ -315,10 +315,10 @@ Info (21057): Implemented 315 device resources after synthesis - the final resou
     Info (21070): Implemented 1 User Flash Memory blocks
 Info (144001): Generated suppressed messages file Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.map.smsg
 Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings
-    Info: Peak virtual memory: 13113 megabytes
-    Info: Processing ended: Thu Dec 28 23:09:40 2023
-    Info: Elapsed time: 00:00:28
-    Info: Total CPU time (on all processors): 00:00:41
+    Info: Peak virtual memory: 13116 megabytes
+    Info: Processing ended: Thu Jan 11 09:29:19 2024
+    Info: Elapsed time: 00:00:23
+    Info: Total CPU time (on all processors): 00:00:40
 
 
 +------------------------------------------+
diff --git a/CPLD/MAXV/output_files/RAM2E.map.summary b/CPLD/MAXV/output_files/RAM2E.map.summary
index 83dcb8d..788b915 100644
--- a/CPLD/MAXV/output_files/RAM2E.map.summary
+++ b/CPLD/MAXV/output_files/RAM2E.map.summary
@@ -1,4 +1,4 @@
-Analysis & Synthesis Status : Successful - Thu Dec 28 23:09:40 2023
+Analysis & Synthesis Status : Successful - Thu Jan 11 09:29:19 2024
 Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
 Revision Name : RAM2E
 Top-level Entity Name : RAM2E
diff --git a/CPLD/MAXV/output_files/RAM2E.sta.rpt b/CPLD/MAXV/output_files/RAM2E.sta.rpt
index d19a1c7..b54d01f 100644
--- a/CPLD/MAXV/output_files/RAM2E.sta.rpt
+++ b/CPLD/MAXV/output_files/RAM2E.sta.rpt
@@ -1,5 +1,5 @@
 Timing Analyzer report for RAM2E
-Thu Dec 28 23:09:52 2023
+Thu Jan 11 09:29:29 2024
 Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
 
 
@@ -93,8 +93,8 @@ https://fpgasoftware.intel.com/eula.
 +------------------+--------+--------------------------+
 ; SDC File Path    ; Status ; Read at                  ;
 +------------------+--------+--------------------------+
-; ../RAM2E.sdc     ; OK     ; Thu Dec 28 23:09:51 2023 ;
-; ../RAM2E-MAX.sdc ; OK     ; Thu Dec 28 23:09:51 2023 ;
+; ../RAM2E.sdc     ; OK     ; Thu Jan 11 09:29:28 2024 ;
+; ../RAM2E-MAX.sdc ; OK     ; Thu Jan 11 09:29:28 2024 ;
 +------------------+--------+--------------------------+
 
 
@@ -679,7 +679,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 Info: *******************************************************************
 Info: Running Quartus Prime Timing Analyzer
     Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
-    Info: Processing started: Thu Dec 28 23:09:49 2023
+    Info: Processing started: Thu Jan 11 09:29:27 2024
 Info: Command: quartus_sta RAM2E-MAXV -c RAM2E
 Info: qsta_default_script.tcl version: #1
 Info (20032): Parallel compilation is enabled and will use up to 4 processors
@@ -720,9 +720,9 @@ Warning (332009): The launch and latch times for the relationship between source
 Info (332102): Design is not fully constrained for setup requirements
 Info (332102): Design is not fully constrained for hold requirements
 Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
-    Info: Peak virtual memory: 13067 megabytes
-    Info: Processing ended: Thu Dec 28 23:09:52 2023
-    Info: Elapsed time: 00:00:03
+    Info: Peak virtual memory: 13069 megabytes
+    Info: Processing ended: Thu Jan 11 09:29:29 2024
+    Info: Elapsed time: 00:00:02
     Info: Total CPU time (on all processors): 00:00:02