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Working on MAX V

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This commit is contained in:
Zane Kaminski 2020-09-09 16:35:14 -04:00
parent aa58ecc4d9
commit 91544eb60d
52 changed files with 1203 additions and 993 deletions
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5
cpld/RAM2E.qsf
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@ -36,8 +36,8 @@
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX II"
set_global_assignment -name DEVICE EPM240T100C5
set_global_assignment -name FAMILY "MAX V"
set_global_assignment -name DEVICE 5M240ZT100C5
set_global_assignment -name TOP_LEVEL_ENTITY RAM2E
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:58:44 MAY 05, 2020"
@ -49,7 +49,6 @@ set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"
set_global_assignment -name VERILOG_FILE RAM2E.v
set_global_assignment -name SDC_FILE constraints.sdc

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1591131665199 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1591131665199 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jun 02 17:01:05 2020 " "Processing started: Tue Jun 02 17:01:05 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1591131665199 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1591131665199 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1591131665200 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1591131665391 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1591131665396 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4523 " "Peak virtual memory: 4523 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1591131665549 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 02 17:01:05 2020 " "Processing ended: Tue Jun 02 17:01:05 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1591131665549 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1591131665549 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1591131665549 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1591131665549 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1599607698989 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1599607698989 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 08 19:28:18 2020 " "Processing started: Tue Sep 08 19:28:18 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1599607698989 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1599607698989 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1599607698989 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1599607699289 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1599607699299 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4524 " "Peak virtual memory: 4524 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1599607699479 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 08 19:28:19 2020 " "Processing ended: Tue Sep 08 19:28:19 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1599607699479 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1599607699479 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1599607699479 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1599607699479 ""}

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cpld/db/RAM2E.db_info
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Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Version_Index = 302049280
Creation_Time = Tue Jun 02 17:00:54 2020
Creation_Time = Tue Sep 08 19:25:14 2020

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cpld/db/RAM2E.fit.qmsg
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@ -1,39 +1,38 @@
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1591131663188 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2E EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM2E\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1591131663191 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1591131663220 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1591131663220 ""}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1591131663252 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1591131663258 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1591131663331 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1591131663331 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1591131663331 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1591131663331 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1591131663331 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1591131663331 ""}
{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1591131663392 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DRCLK " "Node: DRCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1591131663402 "|RAM2E|DRCLK"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ARCLK " "Node: ARCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1591131663402 "|RAM2E|ARCLK"}
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1591131663404 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1591131663404 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1591131663404 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 69.841 C14M " " 69.841 C14M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1591131663404 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1591131663404 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1591131663406 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1591131663406 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1591131663409 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C14M Global clock in PIN 12 " "Automatically promoted signal \"C14M\" to use Global clock in PIN 12" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 8 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1591131663413 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1591131663413 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1591131663415 ""}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1591131663434 ""}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1591131663434 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1591131663465 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1591131663466 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1591131663466 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1591131663466 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1591131663490 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1591131663565 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1591131663722 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1591131663728 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1591131663956 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1591131663956 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1591131663986 ""}
{ "Info" "IFITAPI_FITAPI_VPR_STATUS_DELAY_ADDED_FOR_HOLD" "4e+01 ns 2.7% " "4e+01 ns of routing delay (approximately 2.7% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." { } { } 0 170089 "%1!s! of routing delay (approximately %2!s! of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." 0 0 "Fitter" 0 -1 1591131664101 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "19 " "Router estimated average interconnect usage is 19% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "19 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1591131664119 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1591131664119 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1591131664186 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.14 " "Total time spent on timing analysis during the Fitter is 0.14 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1591131664192 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1591131664195 ""}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1591131664216 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.fit.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1591131664260 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4772 " "Peak virtual memory: 4772 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1591131664332 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 02 17:01:04 2020 " "Processing ended: Tue Jun 02 17:01:04 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1591131664332 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1591131664332 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1591131664332 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1591131664332 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1599607695785 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2E 5M240ZT100C5 " "Selected device 5M240ZT100C5 for design \"RAM2E\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1599607695785 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1599607695835 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1599607695835 ""}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1599607696066 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1599607696086 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100C5 " "Device 5M80ZT100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1599607696246 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100I5 " "Device 5M80ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1599607696246 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100C5 " "Device 5M160ZT100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1599607696246 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100I5 " "Device 5M160ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1599607696246 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M240ZT100I5 " "Device 5M240ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1599607696246 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100C5 " "Device 5M570ZT100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1599607696246 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100I5 " "Device 5M570ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1599607696246 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1599607696246 ""}
{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1599607696496 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DRCLK " "Node: DRCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1599607696506 "|RAM2E|DRCLK"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ARCLK " "Node: ARCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1599607696506 "|RAM2E|ARCLK"}
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1599607696516 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1599607696516 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1599607696516 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 69.841 C14M " " 69.841 C14M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1599607696516 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1599607696516 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1599607696526 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1599607696526 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1599607696526 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C14M Global clock in PIN 12 " "Automatically promoted signal \"C14M\" to use Global clock in PIN 12" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 8 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1599607696536 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1599607696536 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1599607696546 ""}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1599607696566 ""}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1599607696566 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1599607696606 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1599607696606 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1599607696606 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1599607696606 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1599607696666 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1599607697106 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1599607697246 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1599607697256 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1599607697511 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1599607697511 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1599607697541 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "17 " "Router estimated average interconnect usage is 17% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "17 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 17% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 17% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 17% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1599607697709 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1599607697709 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1599607697869 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.13 " "Total time spent on timing analysis during the Fitter is 0.13 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1599607697879 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1599607697879 ""}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1599607697909 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.fit.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1599607697979 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4771 " "Peak virtual memory: 4771 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1599607698049 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 08 19:28:18 2020 " "Processing ended: Tue Sep 08 19:28:18 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1599607698049 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1599607698049 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1599607698049 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1599607698049 ""}

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1591131661124 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1591131661125 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jun 02 17:01:01 2020 " "Processing started: Tue Jun 02 17:01:01 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1591131661125 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1591131661125 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1591131661125 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1591131661364 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2E.v(37) " "Verilog HDL warning at RAM2E.v(37): extended using \"x\" or \"z\"" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 37 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1591131661398 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram2e.v 1 1 " "Found 1 design units, including 1 entities, in source file ram2e.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2E " "Found entity 1: RAM2E" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1591131661400 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1591131661400 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1591131661445 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1591131661445 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_a7r " "Found entity 1: UFM_altufm_none_a7r" { } { { "UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1591131661445 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1591131661445 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1591131661445 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2E " "Elaborating entity \"RAM2E\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1591131661478 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 RAM2E.v(99) " "Verilog HDL assignment warning at RAM2E.v(99): truncated value with size 32 to match size of target (16)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 99 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1591131661481 "|RAM2E"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2E.v(102) " "Verilog HDL assignment warning at RAM2E.v(102): truncated value with size 32 to match size of target (4)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 102 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1591131661481 "|RAM2E"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 RAM2E.v(504) " "Verilog HDL assignment warning at RAM2E.v(504): truncated value with size 32 to match size of target (3)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 504 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1591131661481 "|RAM2E"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 RAM2E.v(521) " "Verilog HDL assignment warning at RAM2E.v(521): truncated value with size 32 to match size of target (3)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 521 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1591131661481 "|RAM2E"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "RAM2E.v" "UFM_inst" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 78 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1591131661483 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_a7r UFM:UFM_inst\|UFM_altufm_none_a7r:UFM_altufm_none_a7r_component " "Elaborating entity \"UFM_altufm_none_a7r\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_a7r:UFM_altufm_none_a7r_component\"" { } { { "UFM.v" "UFM_altufm_none_a7r_component" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1591131661485 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "263 " "Implemented 263 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "22 " "Implemented 22 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1591131662068 ""} { "Info" "ICUT_CUT_TM_OPINS" "39 " "Implemented 39 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1591131662068 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1591131662068 ""} { "Info" "ICUT_CUT_TM_LCELLS" "193 " "Implemented 193 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1591131662068 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1591131662068 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1591131662068 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1591131662109 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4574 " "Peak virtual memory: 4574 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1591131662156 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 02 17:01:02 2020 " "Processing ended: Tue Jun 02 17:01:02 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1591131662156 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1591131662156 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1591131662156 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1591131662156 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1599607693606 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1599607693606 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 08 19:28:13 2020 " "Processing started: Tue Sep 08 19:28:13 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1599607693606 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1599607693606 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1599607693606 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1599607693837 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2E.v(37) " "Verilog HDL warning at RAM2E.v(37): extended using \"x\" or \"z\"" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 37 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1599607693867 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram2e.v 1 1 " "Found 1 design units, including 1 entities, in source file ram2e.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2E " "Found entity 1: RAM2E" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1599607693867 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1599607693867 ""}
{ "Warning" "WSGN_OUTDATED_CLEARBOX" "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v C:/Users/Zane/Documents/GitHub/RAM2E/cpld/db/UFM.v " "Clear box output file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v is not compatible with the current compile. Used regenerated output file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/db/UFM.v for elaboration" { } { } 0 12136 "Clear box output file %1!s! is not compatible with the current compile. Used regenerated output file %2!s! for elaboration" 0 0 "Quartus II" 0 -1 1599607693927 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "db/UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/db/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1599607693927 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "db/UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/db/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1599607693935 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file db/ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_a7r " "Found entity 1: UFM_altufm_none_a7r" { } { { "db/UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/db/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1599607693935 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "db/UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/db/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1599607693935 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1599607693935 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2E " "Elaborating entity \"RAM2E\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1599607693955 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 RAM2E.v(99) " "Verilog HDL assignment warning at RAM2E.v(99): truncated value with size 32 to match size of target (16)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 99 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1599607693963 "|RAM2E"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2E.v(102) " "Verilog HDL assignment warning at RAM2E.v(102): truncated value with size 32 to match size of target (4)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 102 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1599607693963 "|RAM2E"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 RAM2E.v(504) " "Verilog HDL assignment warning at RAM2E.v(504): truncated value with size 32 to match size of target (3)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 504 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1599607693963 "|RAM2E"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 RAM2E.v(521) " "Verilog HDL assignment warning at RAM2E.v(521): truncated value with size 32 to match size of target (3)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 521 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1599607693963 "|RAM2E"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "RAM2E.v" "UFM_inst" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 78 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1599607693965 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_a7r UFM:UFM_inst\|UFM_altufm_none_a7r:UFM_altufm_none_a7r_component " "Elaborating entity \"UFM_altufm_none_a7r\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_a7r:UFM_altufm_none_a7r_component\"" { } { { "db/UFM.v" "UFM_altufm_none_a7r_component" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/db/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1599607693965 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "263 " "Implemented 263 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "22 " "Implemented 22 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1599607694566 ""} { "Info" "ICUT_CUT_TM_OPINS" "39 " "Implemented 39 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1599607694566 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1599607694566 ""} { "Info" "ICUT_CUT_TM_LCELLS" "193 " "Implemented 193 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1599607694566 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1599607694566 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1599607694566 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1599607694614 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4577 " "Peak virtual memory: 4577 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1599607694716 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 08 19:28:14 2020 " "Processing ended: Tue Sep 08 19:28:14 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1599607694716 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1599607694716 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1599607694716 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1599607694716 ""}

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1591131666606 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1591131666607 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jun 02 17:01:06 2020 " "Processing started: Tue Jun 02 17:01:06 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1591131666607 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1591131666607 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2E -c RAM2E " "Command: quartus_sta RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1591131666607 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1591131666668 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1591131666769 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1591131666805 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1591131666805 ""}
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1591131666836 ""}
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1591131666999 ""}
{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1591131667120 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DRCLK " "Node: DRCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1591131667127 "|RAM2E|DRCLK"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ARCLK " "Node: ARCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1591131667127 "|RAM2E|ARCLK"}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1591131667130 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 28.330 " "Worst-case setup slack is 28.330" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1591131667154 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1591131667154 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 28.330 0.000 C14M " " 28.330 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1591131667154 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1591131667154 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.425 " "Worst-case hold slack is 1.425" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1591131667160 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1591131667160 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.425 0.000 C14M " " 1.425 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1591131667160 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1591131667160 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1591131667167 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1591131667172 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 34.654 " "Worst-case minimum pulse width slack is 34.654" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1591131667178 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1591131667178 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 34.654 0.000 C14M " " 34.654 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1591131667178 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1591131667178 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1591131667220 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1591131667245 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1591131667246 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4522 " "Peak virtual memory: 4522 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1591131667319 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 02 17:01:07 2020 " "Processing ended: Tue Jun 02 17:01:07 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1591131667319 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1591131667319 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1591131667319 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1591131667319 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1599607700619 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1599607700619 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 08 19:28:20 2020 " "Processing started: Tue Sep 08 19:28:20 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1599607700619 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1599607700619 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2E -c RAM2E " "Command: quartus_sta RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1599607700620 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1599607700695 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1599607700791 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1599607700831 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1599607700831 ""}
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1599607700861 ""}
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1599607701084 ""}
{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1599607701152 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DRCLK " "Node: DRCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1599607701162 "|RAM2E|DRCLK"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ARCLK " "Node: ARCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1599607701162 "|RAM2E|ARCLK"}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1599607701162 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 22.276 " "Worst-case setup slack is 22.276" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1599607701200 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1599607701200 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 22.276 0.000 C14M " " 22.276 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1599607701200 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1599607701200 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 3.130 " "Worst-case hold slack is 3.130" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1599607701210 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1599607701210 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.130 0.000 C14M " " 3.130 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1599607701210 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1599607701210 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1599607701220 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1599607701220 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 34.581 " "Worst-case minimum pulse width slack is 34.581" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1599607701230 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1599607701230 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 34.581 0.000 C14M " " 34.581 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1599607701230 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1599607701230 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1599607701290 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1599607701310 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1599607701310 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4528 " "Peak virtual memory: 4528 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1599607701390 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 08 19:28:21 2020 " "Processing ended: Tue Sep 08 19:28:21 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1599607701390 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1599607701390 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1599607701390 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1599607701390 ""}

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cpld/db/RAM2E.tmw_info
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start_full_compilation:s:00:00:07
start_full_compilation:s:00:00:08
start_analysis_synthesis:s:00:00:02-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:02-start_full_compilation
start_fitter:s:00:00:03-start_full_compilation
start_assembler:s:00:00:02-start_full_compilation
start_timing_analyzer:s:00:00:01-start_full_compilation

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// megafunction wizard: %ALTUFM_NONE%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTUFM_NONE
// ============================================================
// File Name: UFM.v
// Megafunction Name(s):
// ALTUFM_NONE
//
// Simulation Library Files(s):
// maxii
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altufm_none CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="MAX V" ERASE_TIME=500000000 LPM_FILE="RAM2E.mif" OSC_FREQUENCY=180000 PORT_ARCLKENA="PORT_UNUSED" PORT_DRCLKENA="PORT_UNUSED" PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 arclk ardin arshft busy drclk drdin drdout drshft erase osc oscena program rtpbusy
//VERSION_BEGIN 13.0 cbx_a_gray2bin 2013:06:12:18:03:43:SJ cbx_a_graycounter 2013:06:12:18:03:43:SJ cbx_altufm_none 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_maxii 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = maxv_ufm 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module UFM_altufm_none_a7r
(
arclk,
ardin,
arshft,
busy,
drclk,
drdin,
drdout,
drshft,
erase,
osc,
oscena,
program,
rtpbusy) ;
input arclk;
input ardin;
input arshft;
output busy;
input drclk;
input drdin;
output drdout;
input drshft;
input erase;
output osc;
input oscena;
input program;
output rtpbusy;
wire wire_maxii_ufm_block1_bgpbusy;
wire wire_maxii_ufm_block1_busy;
wire wire_maxii_ufm_block1_drdout;
wire wire_maxii_ufm_block1_osc;
wire ufm_arclk;
wire ufm_ardin;
wire ufm_arshft;
wire ufm_bgpbusy;
wire ufm_busy;
wire ufm_drclk;
wire ufm_drdin;
wire ufm_drdout;
wire ufm_drshft;
wire ufm_erase;
wire ufm_osc;
wire ufm_oscena;
wire ufm_program;
maxv_ufm maxii_ufm_block1
(
.arclk(ufm_arclk),
.ardin(ufm_ardin),
.arshft(ufm_arshft),
.bgpbusy(wire_maxii_ufm_block1_bgpbusy),
.busy(wire_maxii_ufm_block1_busy),
.drclk(ufm_drclk),
.drdin(ufm_drdin),
.drdout(wire_maxii_ufm_block1_drdout),
.drshft(ufm_drshft),
.erase(ufm_erase),
.osc(wire_maxii_ufm_block1_osc),
.oscena(ufm_oscena),
.program(ufm_program)
// synopsys translate_off
,
.ctrl_bgpbusy(1'b0),
.devclrn(1'b1),
.devpor(1'b1),
.sbdin(1'b0),
.sbdout()
// synopsys translate_on
);
defparam
maxii_ufm_block1.address_width = 9,
maxii_ufm_block1.erase_time = 500000000,
maxii_ufm_block1.init_file = "RAM2E.mif",
maxii_ufm_block1.mem1 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem10 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem11 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem12 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem13 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem14 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem15 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem16 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem2 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem3 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem4 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem5 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem6 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem7 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem8 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem9 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.osc_sim_setting = 180000,
maxii_ufm_block1.program_time = 1600000,
maxii_ufm_block1.lpm_type = "maxv_ufm";
assign
busy = ufm_busy,
drdout = ufm_drdout,
osc = ufm_osc,
rtpbusy = ufm_bgpbusy,
ufm_arclk = arclk,
ufm_ardin = ardin,
ufm_arshft = arshft,
ufm_bgpbusy = wire_maxii_ufm_block1_bgpbusy,
ufm_busy = wire_maxii_ufm_block1_busy,
ufm_drclk = drclk,
ufm_drdin = drdin,
ufm_drdout = wire_maxii_ufm_block1_drdout,
ufm_drshft = drshft,
ufm_erase = erase,
ufm_osc = wire_maxii_ufm_block1_osc,
ufm_oscena = oscena,
ufm_program = program;
endmodule //UFM_altufm_none_a7r
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module UFM (
arclk,
ardin,
arshft,
drclk,
drdin,
drshft,
erase,
oscena,
program,
busy,
drdout,
osc,
rtpbusy);
input arclk;
input ardin;
input arshft;
input drclk;
input drdin;
input drshft;
input erase;
input oscena;
input program;
output busy;
output drdout;
output osc;
output rtpbusy;
wire sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire sub_wire3;
wire osc = sub_wire0;
wire rtpbusy = sub_wire1;
wire drdout = sub_wire2;
wire busy = sub_wire3;
UFM_altufm_none_a7r UFM_altufm_none_a7r_component (
.arshft (arshft),
.drclk (drclk),
.erase (erase),
.program (program),
.arclk (arclk),
.drdin (drdin),
.oscena (oscena),
.ardin (ardin),
.drshft (drshft),
.osc (sub_wire0),
.rtpbusy (sub_wire1),
.drdout (sub_wire2),
.busy (sub_wire3));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX II"
// Retrieval info: CONSTANT: ERASE_TIME NUMERIC "500000000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX II"
// Retrieval info: CONSTANT: LPM_FILE STRING "RAM2E.mif"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altufm_none"
// Retrieval info: CONSTANT: OSC_FREQUENCY NUMERIC "180000"
// Retrieval info: CONSTANT: PORT_ARCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_DRCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PROGRAM_TIME NUMERIC "1600000"
// Retrieval info: CONSTANT: WIDTH_UFM_ADDRESS NUMERIC "9"
// Retrieval info: USED_PORT: arclk 0 0 0 0 INPUT NODEFVAL "arclk"
// Retrieval info: CONNECT: @arclk 0 0 0 0 arclk 0 0 0 0
// Retrieval info: USED_PORT: ardin 0 0 0 0 INPUT NODEFVAL "ardin"
// Retrieval info: CONNECT: @ardin 0 0 0 0 ardin 0 0 0 0
// Retrieval info: USED_PORT: arshft 0 0 0 0 INPUT NODEFVAL "arshft"
// Retrieval info: CONNECT: @arshft 0 0 0 0 arshft 0 0 0 0
// Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
// Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
// Retrieval info: USED_PORT: drclk 0 0 0 0 INPUT NODEFVAL "drclk"
// Retrieval info: CONNECT: @drclk 0 0 0 0 drclk 0 0 0 0
// Retrieval info: USED_PORT: drdin 0 0 0 0 INPUT NODEFVAL "drdin"
// Retrieval info: CONNECT: @drdin 0 0 0 0 drdin 0 0 0 0
// Retrieval info: USED_PORT: drdout 0 0 0 0 OUTPUT NODEFVAL "drdout"
// Retrieval info: CONNECT: drdout 0 0 0 0 @drdout 0 0 0 0
// Retrieval info: USED_PORT: drshft 0 0 0 0 INPUT NODEFVAL "drshft"
// Retrieval info: CONNECT: @drshft 0 0 0 0 drshft 0 0 0 0
// Retrieval info: USED_PORT: erase 0 0 0 0 INPUT NODEFVAL "erase"
// Retrieval info: CONNECT: @erase 0 0 0 0 erase 0 0 0 0
// Retrieval info: USED_PORT: osc 0 0 0 0 OUTPUT NODEFVAL "osc"
// Retrieval info: CONNECT: osc 0 0 0 0 @osc 0 0 0 0
// Retrieval info: USED_PORT: oscena 0 0 0 0 INPUT NODEFVAL "oscena"
// Retrieval info: CONNECT: @oscena 0 0 0 0 oscena 0 0 0 0
// Retrieval info: USED_PORT: program 0 0 0 0 INPUT NODEFVAL "program"
// Retrieval info: CONNECT: @program 0 0 0 0 program 0 0 0 0
// Retrieval info: USED_PORT: rtpbusy 0 0 0 0 OUTPUT NODEFVAL "rtpbusy"
// Retrieval info: CONNECT: rtpbusy 0 0 0 0 @rtpbusy 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.bsf TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM_inst.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM_bb.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.inc FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.cmp FALSE TRUE
// Retrieval info: LIB_FILE: maxii

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1591130186751 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1591130186751 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jun 02 16:36:26 2020 " "Processing started: Tue Jun 02 16:36:26 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1591130186751 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1591130186751 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1591130186751 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1591130186989 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2E.v(37) " "Verilog HDL warning at RAM2E.v(37): extended using \"x\" or \"z\"" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 37 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1591130187024 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram2e.v 1 1 " "Found 1 design units, including 1 entities, in source file ram2e.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2E " "Found entity 1: RAM2E" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1591130187026 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1591130187026 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1591130187073 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1591130187073 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_a7r " "Found entity 1: UFM_altufm_none_a7r" { } { { "UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1591130187074 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1591130187074 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1591130187074 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2E " "Elaborating entity \"RAM2E\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1591130187100 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 RAM2E.v(99) " "Verilog HDL assignment warning at RAM2E.v(99): truncated value with size 32 to match size of target (16)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 99 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1591130187102 "|RAM2E"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2E.v(102) " "Verilog HDL assignment warning at RAM2E.v(102): truncated value with size 32 to match size of target (4)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 102 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1591130187103 "|RAM2E"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 RAM2E.v(504) " "Verilog HDL assignment warning at RAM2E.v(504): truncated value with size 32 to match size of target (3)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 504 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1591130187103 "|RAM2E"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 RAM2E.v(521) " "Verilog HDL assignment warning at RAM2E.v(521): truncated value with size 32 to match size of target (3)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 521 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1591130187103 "|RAM2E"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "RAM2E.v" "UFM_inst" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 78 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1591130187105 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_a7r UFM:UFM_inst\|UFM_altufm_none_a7r:UFM_altufm_none_a7r_component " "Elaborating entity \"UFM_altufm_none_a7r\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_a7r:UFM_altufm_none_a7r_component\"" { } { { "UFM.v" "UFM_altufm_none_a7r_component" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1591130187107 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "263 " "Implemented 263 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "22 " "Implemented 22 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1591130187693 ""} { "Info" "ICUT_CUT_TM_OPINS" "39 " "Implemented 39 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1591130187693 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1591130187693 ""} { "Info" "ICUT_CUT_TM_LCELLS" "193 " "Implemented 193 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1591130187693 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1591130187693 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1591130187693 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1591130187733 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4574 " "Peak virtual memory: 4574 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1591130187791 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 02 16:36:27 2020 " "Processing ended: Tue Jun 02 16:36:27 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1591130187791 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1591130187791 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1591130187791 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1591130187791 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1591130188731 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1591130188731 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jun 02 16:36:28 2020 " "Processing started: Tue Jun 02 16:36:28 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1591130188731 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1591130188731 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_fit --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1591130188732 ""}
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1591130188787 ""}
{ "Info" "0" "" "Project = RAM2E" { } { } 0 0 "Project = RAM2E" 0 0 "Fitter" 0 0 1591130188787 ""}
{ "Info" "0" "" "Revision = RAM2E" { } { } 0 0 "Revision = RAM2E" 0 0 "Fitter" 0 0 1591130188787 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1591130188833 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2E EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM2E\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1591130188835 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1591130188865 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1591130188865 ""}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1591130188895 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1591130188902 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1591130188974 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1591130188974 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1591130188974 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1591130188974 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1591130188974 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1591130188974 ""}
{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1591130189041 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DRCLK " "Node: DRCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1591130189050 "|RAM2E|DRCLK"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ARCLK " "Node: ARCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1591130189050 "|RAM2E|ARCLK"}
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1591130189052 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1591130189052 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1591130189052 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 69.841 C14M " " 69.841 C14M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1591130189052 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1591130189052 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1591130189054 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1591130189054 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1591130189056 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C14M Global clock in PIN 12 " "Automatically promoted signal \"C14M\" to use Global clock in PIN 12" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 8 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1591130189061 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1591130189061 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1591130189062 ""}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1591130189081 ""}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1591130189081 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1591130189106 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1591130189107 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1591130189107 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1591130189108 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1591130189130 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1591130189205 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1591130189362 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1591130189368 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1591130189607 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1591130189607 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1591130189635 ""}
{ "Info" "IFITAPI_FITAPI_VPR_STATUS_DELAY_ADDED_FOR_HOLD" "4e+01 ns 2.7% " "4e+01 ns of routing delay (approximately 2.7% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." { } { } 0 170089 "%1!s! of routing delay (approximately %2!s! of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." 0 0 "Fitter" 0 -1 1591130189752 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "19 " "Router estimated average interconnect usage is 19% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "19 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1591130189771 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1591130189771 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1591130189837 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.13 " "Total time spent on timing analysis during the Fitter is 0.13 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1591130189843 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1591130189845 ""}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1591130189866 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.fit.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1591130189912 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4772 " "Peak virtual memory: 4772 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1591130189970 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 02 16:36:29 2020 " "Processing ended: Tue Jun 02 16:36:29 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1591130189970 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1591130189970 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1591130189970 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1591130189970 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1591130190809 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1591130190809 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jun 02 16:36:30 2020 " "Processing started: Tue Jun 02 16:36:30 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1591130190809 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1591130190809 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1591130190809 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1591130191004 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1591130191009 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4523 " "Peak virtual memory: 4523 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1591130191163 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 02 16:36:31 2020 " "Processing ended: Tue Jun 02 16:36:31 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1591130191163 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1591130191163 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1591130191163 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1591130191163 ""}
{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1591130191797 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1591130192156 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1591130192157 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jun 02 16:36:31 2020 " "Processing started: Tue Jun 02 16:36:31 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1591130192157 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1591130192157 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2E -c RAM2E " "Command: quartus_sta RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1591130192157 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1591130192219 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1591130192319 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1591130192349 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1591130192349 ""}
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1591130192381 ""}
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1591130192555 ""}
{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1591130192622 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DRCLK " "Node: DRCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1591130192632 "|RAM2E|DRCLK"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ARCLK " "Node: ARCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1591130192632 "|RAM2E|ARCLK"}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1591130192635 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 28.330 " "Worst-case setup slack is 28.330" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1591130192660 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1591130192660 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 28.330 0.000 C14M " " 28.330 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1591130192660 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1591130192660 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.425 " "Worst-case hold slack is 1.425" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1591130192666 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1591130192666 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.425 0.000 C14M " " 1.425 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1591130192666 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1591130192666 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1591130192674 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1591130192680 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 34.654 " "Worst-case minimum pulse width slack is 34.654" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1591130192686 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1591130192686 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 34.654 0.000 C14M " " 34.654 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1591130192686 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1591130192686 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1591130192729 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1591130192753 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1591130192754 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4522 " "Peak virtual memory: 4522 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1591130192909 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 02 16:36:32 2020 " "Processing ended: Tue Jun 02 16:36:32 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1591130192909 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1591130192909 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1591130192909 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1591130192909 ""}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 13 s " "Quartus II Full Compilation was successful. 0 errors, 13 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1591130193511 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1599607628183 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1599607628185 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 08 19:27:08 2020 " "Processing started: Tue Sep 08 19:27:08 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1599607628185 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1599607628185 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1599607628185 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1599607628412 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2E.v(37) " "Verilog HDL warning at RAM2E.v(37): extended using \"x\" or \"z\"" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 37 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1599607628450 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram2e.v 1 1 " "Found 1 design units, including 1 entities, in source file ram2e.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2E " "Found entity 1: RAM2E" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1599607628450 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1599607628450 ""}
{ "Warning" "WSGN_OUTDATED_CLEARBOX" "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v C:/Users/Zane/Documents/GitHub/RAM2E/cpld/db/UFM.v " "Clear box output file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v is not compatible with the current compile. Used regenerated output file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/db/UFM.v for elaboration" { } { } 0 12136 "Clear box output file %1!s! is not compatible with the current compile. Used regenerated output file %2!s! for elaboration" 0 0 "Quartus II" 0 -1 1599607628500 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "db/UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/db/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1599607628500 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "db/UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/db/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1599607628500 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file db/ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_a7r " "Found entity 1: UFM_altufm_none_a7r" { } { { "db/UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/db/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1599607628500 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "db/UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/db/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1599607628500 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1599607628500 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2E " "Elaborating entity \"RAM2E\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1599607628530 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 RAM2E.v(99) " "Verilog HDL assignment warning at RAM2E.v(99): truncated value with size 32 to match size of target (16)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 99 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1599607628530 "|RAM2E"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2E.v(102) " "Verilog HDL assignment warning at RAM2E.v(102): truncated value with size 32 to match size of target (4)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 102 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1599607628530 "|RAM2E"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 RAM2E.v(504) " "Verilog HDL assignment warning at RAM2E.v(504): truncated value with size 32 to match size of target (3)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 504 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1599607628530 "|RAM2E"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 RAM2E.v(521) " "Verilog HDL assignment warning at RAM2E.v(521): truncated value with size 32 to match size of target (3)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 521 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1599607628530 "|RAM2E"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "RAM2E.v" "UFM_inst" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 78 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1599607628530 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_a7r UFM:UFM_inst\|UFM_altufm_none_a7r:UFM_altufm_none_a7r_component " "Elaborating entity \"UFM_altufm_none_a7r\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_a7r:UFM_altufm_none_a7r_component\"" { } { { "db/UFM.v" "UFM_altufm_none_a7r_component" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/db/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1599607628540 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "263 " "Implemented 263 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "22 " "Implemented 22 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1599607629190 ""} { "Info" "ICUT_CUT_TM_OPINS" "39 " "Implemented 39 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1599607629190 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1599607629190 ""} { "Info" "ICUT_CUT_TM_LCELLS" "193 " "Implemented 193 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1599607629190 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1599607629190 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1599607629190 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1599607629240 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4577 " "Peak virtual memory: 4577 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1599607629280 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 08 19:27:09 2020 " "Processing ended: Tue Sep 08 19:27:09 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1599607629280 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1599607629280 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1599607629280 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1599607629280 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1599607630188 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1599607630189 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 08 19:27:09 2020 " "Processing started: Tue Sep 08 19:27:09 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1599607630189 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1599607630189 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_fit --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1599607630189 ""}
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1599607630242 ""}
{ "Info" "0" "" "Project = RAM2E" { } { } 0 0 "Project = RAM2E" 0 0 "Fitter" 0 0 1599607630242 ""}
{ "Info" "0" "" "Revision = RAM2E" { } { } 0 0 "Revision = RAM2E" 0 0 "Fitter" 0 0 1599607630242 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1599607630292 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2E 5M240ZT100C5 " "Selected device 5M240ZT100C5 for design \"RAM2E\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1599607630292 ""}
{ "Error" "ECUT_CUT_INVALID_SUPPLY_VOLTAGE_VALUE" "3.3V VCCINT " "Supply voltage value 3.3V set to the 'VCCINT' power rail is illegal for the selected device." { } { } 0 21191 "Supply voltage value %1!s! set to the '%2!s!' power rail is illegal for the selected device." 0 0 "Fitter" 0 -1 1599607630326 ""}
{ "Error" "EQEXE_ERROR_COUNT" "Fitter 1 1 Quartus II 64-Bit " "Quartus II 64-Bit Fitter was unsuccessful. 1 error, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "4685 " "Peak virtual memory: 4685 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1599607630446 ""} { "Error" "EQEXE_END_BANNER_TIME" "Tue Sep 08 19:27:10 2020 " "Processing ended: Tue Sep 08 19:27:10 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1599607630446 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1599607630446 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1599607630446 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1599607630446 ""}
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 3 s 7 s " "Quartus II Full Compilation was unsuccessful. 3 errors, 7 warnings" { } { } 0 293001 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1599607631016 ""}

BIN
cpld/incremental_db/compiled_partitions/RAM2E.root_partition.map.kpt
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Binary file not shown.

22
cpld/output_files/RAM2E.asm.rpt
View File

@ -1,5 +1,5 @@
Assembler report for RAM2E
Tue Jun 02 17:01:05 2020
Tue Sep 08 19:28:19 2020
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -37,11 +37,11 @@ applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Tue Jun 02 17:01:05 2020 ;
; Assembler Status ; Successful - Tue Sep 08 19:28:19 2020 ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX II ;
; Device ; EPM240T100C5 ;
; Family ; MAX V ;
; Device ; 5M240ZT100C5 ;
+-----------------------+---------------------------------------+
@ -89,9 +89,9 @@ applicable agreement for further details.
+----------------+---------------------------------------------------------------------------+
; Option ; Setting ;
+----------------+---------------------------------------------------------------------------+
; Device ; EPM240T100C5 ;
; JTAG usercode ; 0x00170AEE ;
; Checksum ; 0x00170D6E ;
; Device ; 5M240ZT100C5 ;
; JTAG usercode ; 0x0016F835 ;
; Checksum ; 0x0016FC1D ;
+----------------+---------------------------------------------------------------------------+
@ -101,14 +101,14 @@ applicable agreement for further details.
Info: *******************************************************************
Info: Running Quartus II 64-Bit Assembler
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Tue Jun 02 17:01:05 2020
Info: Processing started: Tue Sep 08 19:28:18 2020
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 4523 megabytes
Info: Processing ended: Tue Jun 02 17:01:05 2020
Info: Elapsed time: 00:00:00
Info: Peak virtual memory: 4524 megabytes
Info: Processing ended: Tue Sep 08 19:28:19 2020
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:00

2
cpld/output_files/RAM2E.cdf
View File

@ -4,7 +4,7 @@ JedecChain;
DefaultMfr(6E);
P ActionCode(Cfg)
Device PartName(EPM240T100) Path("C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/") File("RAM2E.pof") MfrSpec(OpMask(3) SEC_Device(EPM240T100) Child_OpMask(2 3 3));
Device PartName(5M240ZT100) Path("C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/") File("RAM2E.pof") MfrSpec(OpMask(3) SEC_Device(5M240ZT100) Child_OpMask(2 3 3));
ChainEnd;

2
cpld/output_files/RAM2E.done
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@ -1 +1 @@
Tue Jun 02 17:01:07 2020
Tue Sep 08 19:28:22 2020

379
cpld/output_files/RAM2E.fit.rpt
View File

@ -1,5 +1,5 @@
Fitter report for RAM2E
Tue Jun 02 17:01:04 2020
Tue Sep 08 19:28:17 2020
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -57,15 +57,15 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------+
; Fitter Summary ;
+---------------------------+-------------------------------------------------+
; Fitter Status ; Successful - Tue Jun 02 17:01:04 2020 ;
; Fitter Status ; Successful - Tue Sep 08 19:28:17 2020 ;
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX II ;
; Device ; EPM240T100C5 ;
; Family ; MAX V ;
; Device ; 5M240ZT100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 184 / 240 ( 77 % ) ;
; Total pins ; 69 / 80 ( 86 % ) ;
; Total pins ; 69 / 79 ( 87 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+---------------------------+-------------------------------------------------+
@ -76,7 +76,7 @@ applicable agreement for further details.
+----------------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device ; EPM240T100C5 ; ;
; Device ; 5M240ZT100C5 ; ;
; Minimum Core Junction Temperature ; 0 ; ;
; Maximum Core Junction Temperature ; 85 ; ;
; Fit Attempts to Skip ; 0 ; 0.0 ;
@ -159,22 +159,22 @@ The pin-out file can be found in C:/Users/Zane/Documents/GitHub/RAM2E/cpld/outpu
; -- arithmetic mode ; 14 ;
; -- qfbk mode ; 9 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 12 ;
; -- synchronous clear/load mode ; 13 ;
; -- asynchronous clear/load mode ; 0 ;
; ; ;
; Total registers ; 106 / 240 ( 44 % ) ;
; Total LABs ; 23 / 24 ( 96 % ) ;
; Total LABs ; 22 / 24 ( 92 % ) ;
; Logic elements in carry chains ; 15 ;
; Virtual pins ; 0 ;
; I/O pins ; 69 / 80 ( 86 % ) ;
; I/O pins ; 69 / 79 ( 87 % ) ;
; -- Clock pins ; 3 / 4 ( 75 % ) ;
; ; ;
; Global signals ; 1 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
; Global clocks ; 1 / 4 ( 25 % ) ;
; JTAGs ; 0 / 1 ( 0 % ) ;
; Average interconnect usage (total/H/V) ; 21% / 21% / 21% ;
; Peak interconnect usage (total/H/V) ; 21% / 21% / 21% ;
; Average interconnect usage (total/H/V) ; 23% / 23% / 22% ;
; Peak interconnect usage (total/H/V) ; 23% / 23% / 22% ;
; Maximum fan-out ; 106 ;
; Highest non-global fan-out ; 33 ;
; Total fan-out ; 793 ;
@ -218,9 +218,9 @@ The pin-out file can be found in C:/Users/Zane/Documents/GitHub/RAM2E/cpld/outpu
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
; BA[0] ; 6 ; 1 ; 1 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; BA[1] ; 14 ; 1 ; 1 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; BA[1] ; 14 ; 1 ; 1 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; CKE ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; DQMH ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; DQMH ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; DQML ; 98 ; 2 ; 2 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Dout[0] ; 77 ; 2 ; 7 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Dout[1] ; 76 ; 2 ; 7 ; 5 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
@ -281,116 +281,116 @@ The pin-out file can be found in C:/Users/Zane/Documents/GitHub/RAM2E/cpld/outpu
; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
+----------+-------------------+---------------+--------------+
; 1 ; 38 / 38 ( 100 % ) ; 3.3V ; -- ;
; 2 ; 31 / 42 ( 74 % ) ; 3.3V ; -- ;
; 2 ; 31 / 41 ( 76 % ) ; 3.3V ; -- ;
+----------+-------------------+---------------+--------------+
+------------------------------------------------------------------------------------------------------------------------------------------------+
; All Package Pins ;
+----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+
; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
+----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+
; 1 ; 83 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 2 ; 0 ; 1 ; nRWE ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 3 ; 1 ; 1 ; nCAS ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 4 ; 2 ; 1 ; CKE ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 5 ; 3 ; 1 ; nRAS ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 6 ; 4 ; 1 ; BA[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 7 ; 5 ; 1 ; RA[11] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 8 ; 6 ; 1 ; nCS ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 9 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 10 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 11 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ;
; 12 ; 7 ; 1 ; C14M ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 13 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ;
; 14 ; 8 ; 1 ; BA[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 15 ; 9 ; 1 ; RA[9] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 16 ; 10 ; 1 ; RA[10] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 17 ; 11 ; 1 ; RA[8] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 18 ; 12 ; 1 ; RA[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 19 ; 13 ; 1 ; RA[7] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 20 ; 14 ; 1 ; RA[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 21 ; 15 ; 1 ; RA[6] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 22 ; 16 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
; 23 ; 17 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
; 24 ; 18 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
; 25 ; 19 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
; 26 ; 20 ; 1 ; RA[4] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 27 ; 21 ; 1 ; RA[3] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 28 ; 22 ; 1 ; nEN80 ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 29 ; 23 ; 1 ; RA[5] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 30 ; 24 ; 1 ; RA[2] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 31 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 32 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 33 ; 25 ; 1 ; nWE80 ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 34 ; 26 ; 1 ; Ain[5] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 35 ; 27 ; 1 ; Din[7] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 36 ; 28 ; 1 ; Din[6] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 37 ; 29 ; 1 ; PHI1 ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 38 ; 30 ; 1 ; Din[0] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 39 ; 31 ; 1 ; Ain[6] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 40 ; 32 ; 1 ; Din[1] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 41 ; 33 ; 1 ; Din[3] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 42 ; 34 ; 1 ; Din[2] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 43 ; 35 ; 1 ; Ain[2] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 44 ; 36 ; 1 ; Ain[4] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 45 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 46 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 47 ; 37 ; 1 ; Ain[3] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 48 ; 38 ; 1 ; Din[4] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 49 ; 39 ; 1 ; Din[5] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 50 ; 40 ; 1 ; nVOE ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 51 ; 41 ; 1 ; nWE ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 52 ; 42 ; 2 ; nC07X ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 53 ; 43 ; 2 ; Ain[7] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 54 ; 44 ; 2 ; Ain[1] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 55 ; 45 ; 2 ; nDOE ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 56 ; 46 ; 2 ; Ain[0] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 57 ; 47 ; 2 ; Vout[7] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 58 ; 48 ; 2 ; Vout[6] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 59 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 60 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 61 ; 49 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 62 ; 50 ; 2 ; Vout[3] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 63 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ;
; 64 ; 51 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 65 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ;
; 66 ; 52 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 67 ; 53 ; 2 ; Vout[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 68 ; 54 ; 2 ; Vout[5] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 69 ; 55 ; 2 ; Vout[2] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 70 ; 56 ; 2 ; Vout[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 71 ; 57 ; 2 ; Vout[4] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 72 ; 58 ; 2 ; Dout[5] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 73 ; 59 ; 2 ; Dout[4] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 74 ; 60 ; 2 ; Dout[2] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 75 ; 61 ; 2 ; Dout[3] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 76 ; 62 ; 2 ; Dout[1] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 77 ; 63 ; 2 ; Dout[0] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 78 ; 64 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 79 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 80 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 81 ; 65 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 82 ; 66 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 83 ; 67 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 84 ; 68 ; 2 ; Dout[6] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 85 ; 69 ; 2 ; Dout[7] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 86 ; 70 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 87 ; 71 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 88 ; 72 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 89 ; 73 ; 2 ; RD[3] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 90 ; 74 ; 2 ; RD[1] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 91 ; 75 ; 2 ; RD[4] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 92 ; 76 ; 2 ; RD[5] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 93 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 94 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 95 ; 77 ; 2 ; RD[6] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 96 ; 78 ; 2 ; RD[7] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 97 ; 79 ; 2 ; RD[0] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 98 ; 80 ; 2 ; DQML ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 99 ; 81 ; 2 ; RD[2] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 100 ; 82 ; 2 ; DQMH ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
+----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+
+----------------------------------------------------------------------------------------------------------------------------------------------+
; All Package Pins ;
+----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+----------+--------------+
; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
+----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+----------+--------------+
; 1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 2 ; 0 ; 1 ; nRWE ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 3 ; 1 ; 1 ; nCAS ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 4 ; 2 ; 1 ; CKE ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 5 ; 3 ; 1 ; nRAS ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 6 ; 4 ; 1 ; BA[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 7 ; 5 ; 1 ; RA[11] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 8 ; 6 ; 1 ; nCS ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 9 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 12 ; 7 ; 1 ; C14M ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 13 ; ; ; VCCINT ; power ; ; 1.8V ; -- ; ; -- ; -- ;
; 14 ; 8 ; 1 ; BA[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 15 ; 9 ; 1 ; RA[9] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 16 ; 10 ; 1 ; RA[10] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 17 ; 11 ; 1 ; RA[8] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 18 ; 12 ; 1 ; RA[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 19 ; 13 ; 1 ; RA[7] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 20 ; 14 ; 1 ; RA[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 21 ; 15 ; 1 ; RA[6] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 22 ; 16 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
; 23 ; 17 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
; 24 ; 18 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
; 25 ; 19 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
; 26 ; 20 ; 1 ; RA[4] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 27 ; 21 ; 1 ; RA[3] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 28 ; 22 ; 1 ; nEN80 ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 29 ; 23 ; 1 ; RA[5] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 30 ; 24 ; 1 ; RA[2] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 31 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 32 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 33 ; 25 ; 1 ; nWE80 ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 34 ; 26 ; 1 ; Ain[5] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 35 ; 27 ; 1 ; Din[7] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 36 ; 28 ; 1 ; Din[6] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 37 ; 29 ; 1 ; PHI1 ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 38 ; 30 ; 1 ; Din[0] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 39 ; 31 ; 1 ; Ain[6] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 40 ; 32 ; 1 ; Din[1] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 41 ; 33 ; 1 ; Din[3] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 42 ; 34 ; 1 ; Din[2] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 43 ; 35 ; 1 ; Ain[2] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 44 ; 36 ; 1 ; Ain[4] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 45 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 46 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 47 ; 37 ; 1 ; Ain[3] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 48 ; 38 ; 1 ; Din[4] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 49 ; 39 ; 1 ; Din[5] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 50 ; 40 ; 1 ; nVOE ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 51 ; 41 ; 1 ; nWE ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 52 ; 42 ; 2 ; nC07X ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 53 ; 43 ; 2 ; Ain[7] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 54 ; 44 ; 2 ; Ain[1] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 55 ; 45 ; 2 ; nDOE ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 56 ; 46 ; 2 ; Ain[0] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 57 ; 47 ; 2 ; Vout[7] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 58 ; 48 ; 2 ; Vout[6] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 59 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 60 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 61 ; 49 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 62 ; 50 ; 2 ; Vout[3] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 63 ; ; ; VCCINT ; power ; ; 1.8V ; -- ; ; -- ; -- ;
; 64 ; 51 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 65 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 66 ; 52 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 67 ; 53 ; 2 ; Vout[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 68 ; 54 ; 2 ; Vout[5] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 69 ; 55 ; 2 ; Vout[2] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 70 ; 56 ; 2 ; Vout[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 71 ; 57 ; 2 ; Vout[4] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 72 ; 58 ; 2 ; Dout[5] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 73 ; 59 ; 2 ; Dout[4] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 74 ; 60 ; 2 ; Dout[2] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 75 ; 61 ; 2 ; Dout[3] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 76 ; 62 ; 2 ; Dout[1] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 77 ; 63 ; 2 ; Dout[0] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 78 ; 64 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 79 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 80 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 81 ; 65 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 82 ; 66 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 83 ; 67 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 84 ; 68 ; 2 ; Dout[6] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 85 ; 69 ; 2 ; Dout[7] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 86 ; 70 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 87 ; 71 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 88 ; 72 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 89 ; 73 ; 2 ; RD[3] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 90 ; 74 ; 2 ; RD[1] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 91 ; 75 ; 2 ; RD[4] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 92 ; 76 ; 2 ; RD[5] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 93 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 94 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 95 ; 77 ; 2 ; RD[6] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 96 ; 78 ; 2 ; RD[7] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 97 ; 79 ; 2 ; RD[0] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 98 ; 80 ; 2 ; DQML ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 99 ; 81 ; 2 ; RD[2] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 100 ; 82 ; 2 ; DQMH ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
+----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+----------+--------------+
Note: Pin directions (input, output or bidir) are based on device operating in user mode.
@ -406,6 +406,9 @@ Note: Pin directions (input, output or bidir) are based on device operating in u
; 1.5 V ; 10 pF ; Not Available ;
; 3.3V Schmitt Trigger Input ; 10 pF ; Not Available ;
; 2.5V Schmitt Trigger Input ; 10 pF ; Not Available ;
; 1.2 V ; 10 pF ; Not Available ;
; LVDS_E_3R ; 10 pF ; Not Available ;
; RSDS_E_3R ; 10 pF ; Not Available ;
+----------------------------+-------+------------------------+
Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
@ -505,15 +508,15 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
+-------------+-------------+---------+---------------+--------+----------------------+------------------+
; C14M ; PIN_12 ; 106 ; Clock ; yes ; Global Clock ; GCLK0 ;
; CS[0]~2 ; LC_X5_Y4_N1 ; 3 ; Clock enable ; no ; -- ; -- ;
; Equal9~0 ; LC_X7_Y4_N6 ; 14 ; Clock enable ; no ; -- ; -- ;
; Equal9~1 ; LC_X6_Y2_N6 ; 8 ; Clock enable ; no ; -- ; -- ;
; RA[4]~1 ; LC_X2_Y2_N0 ; 8 ; Clock enable ; no ; -- ; -- ;
; RDOE ; LC_X2_Y4_N6 ; 8 ; Output enable ; no ; -- ; -- ;
; RWBank[4]~1 ; LC_X5_Y4_N7 ; 13 ; Clock enable ; no ; -- ; -- ;
; RWMask[4]~2 ; LC_X5_Y2_N2 ; 8 ; Clock enable ; no ; -- ; -- ;
; S[2] ; LC_X6_Y2_N7 ; 19 ; Sync. clear ; no ; -- ; -- ;
; UFMD[8]~5 ; LC_X4_Y2_N6 ; 7 ; Clock enable ; no ; -- ; -- ;
; CS[0]~2 ; LC_X7_Y3_N9 ; 3 ; Clock enable ; no ; -- ; -- ;
; Equal9~0 ; LC_X6_Y3_N7 ; 14 ; Clock enable ; no ; -- ; -- ;
; Equal9~1 ; LC_X6_Y3_N5 ; 8 ; Clock enable ; no ; -- ; -- ;
; RA[4]~1 ; LC_X2_Y2_N7 ; 8 ; Clock enable ; no ; -- ; -- ;
; RDOE ; LC_X2_Y2_N1 ; 8 ; Output enable ; no ; -- ; -- ;
; RWBank[4]~1 ; LC_X5_Y3_N1 ; 13 ; Clock enable ; no ; -- ; -- ;
; RWMask[4]~2 ; LC_X4_Y2_N8 ; 8 ; Clock enable ; no ; -- ; -- ;
; S[2] ; LC_X6_Y3_N0 ; 19 ; Sync. clear ; no ; -- ; -- ;
; UFMD[8]~5 ; LC_X4_Y4_N3 ; 7 ; Clock enable ; no ; -- ; -- ;
+-------------+-------------+---------+---------------+--------+----------------------+------------------+
@ -789,62 +792,62 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-----------------------------+--------------------+
; Other Routing Resource Type ; Usage ;
+-----------------------------+--------------------+
; C4s ; 135 / 784 ( 17 % ) ;
; Direct links ; 50 / 888 ( 6 % ) ;
; C4s ; 146 / 784 ( 19 % ) ;
; Direct links ; 53 / 888 ( 6 % ) ;
; Global clocks ; 1 / 4 ( 25 % ) ;
; LAB clocks ; 6 / 32 ( 19 % ) ;
; LUT chains ; 13 / 216 ( 6 % ) ;
; Local interconnects ; 270 / 888 ( 30 % ) ;
; R4s ; 120 / 704 ( 17 % ) ;
; LUT chains ; 16 / 216 ( 7 % ) ;
; Local interconnects ; 281 / 888 ( 32 % ) ;
; R4s ; 132 / 704 ( 19 % ) ;
+-----------------------------+--------------------+
+---------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+------------------------------+
; Number of Logic Elements (Average = 8.00) ; Number of LABs (Total = 23) ;
; Number of Logic Elements (Average = 8.36) ; Number of LABs (Total = 22) ;
+--------------------------------------------+------------------------------+
; 1 ; 2 ;
; 2 ; 1 ;
; 2 ; 0 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 1 ;
; 6 ; 0 ;
; 7 ; 1 ;
; 8 ; 1 ;
; 9 ; 3 ;
; 10 ; 13 ;
; 7 ; 0 ;
; 8 ; 3 ;
; 9 ; 0 ;
; 10 ; 15 ;
+--------------------------------------------+------------------------------+
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 1.39) ; Number of LABs (Total = 23) ;
; LAB-wide Signals (Average = 1.45) ; Number of LABs (Total = 22) ;
+------------------------------------+------------------------------+
; 1 Clock ; 20 ;
; 1 Clock enable ; 11 ;
; 2 Clock enables ; 1 ;
; 1 Clock ; 21 ;
; 1 Clock enable ; 7 ;
; 2 Clock enables ; 4 ;
+------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 8.39) ; Number of LABs (Total = 23) ;
; Number of Signals Sourced (Average = 8.77) ; Number of LABs (Total = 22) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 2 ;
; 2 ; 1 ;
; 2 ; 0 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 1 ;
; 6 ; 0 ;
; 7 ; 1 ;
; 8 ; 1 ;
; 9 ; 3 ;
; 10 ; 10 ;
; 11 ; 1 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 0 ;
; 8 ; 3 ;
; 9 ; 0 ;
; 10 ; 13 ;
; 11 ; 0 ;
; 12 ; 1 ;
; 13 ; 0 ;
; 14 ; 0 ;
@ -856,49 +859,50 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 6.17) ; Number of LABs (Total = 23) ;
; Number of Signals Sourced Out (Average = 6.50) ; Number of LABs (Total = 22) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 2 ;
; 2 ; 1 ;
; 2 ; 0 ;
; 3 ; 1 ;
; 4 ; 2 ;
; 5 ; 2 ;
; 5 ; 1 ;
; 6 ; 3 ;
; 7 ; 5 ;
; 8 ; 1 ;
; 9 ; 4 ;
; 7 ; 4 ;
; 8 ; 6 ;
; 9 ; 0 ;
; 10 ; 2 ;
; 11 ; 1 ;
+-------------------------------------------------+------------------------------+
+-----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+----------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 10.57) ; Number of LABs (Total = 23) ;
; Number of Distinct Inputs (Average = 11.05) ; Number of LABs (Total = 22) ;
+----------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 3 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 2 ;
; 2 ; 2 ;
; 3 ; 2 ;
; 4 ; 1 ;
; 5 ; 1 ;
; 6 ; 0 ;
; 7 ; 1 ;
; 8 ; 1 ;
; 9 ; 3 ;
; 10 ; 0 ;
; 8 ; 0 ;
; 9 ; 1 ;
; 10 ; 1 ;
; 11 ; 2 ;
; 12 ; 3 ;
; 13 ; 0 ;
; 13 ; 1 ;
; 14 ; 1 ;
; 15 ; 1 ;
; 15 ; 0 ;
; 16 ; 1 ;
; 17 ; 0 ;
; 18 ; 0 ;
; 19 ; 2 ;
; 20 ; 1 ;
; 21 ; 1 ;
; 18 ; 2 ;
; 19 ; 1 ;
; 20 ; 0 ;
; 21 ; 2 ;
+----------------------------------------------+------------------------------+
@ -921,17 +925,19 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Fitter Messages ;
+-----------------+
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (119006): Selected device EPM240T100C5 for design "RAM2E"
Info (119006): Selected device 5M240ZT100C5 for design "RAM2E"
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (171004): Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info (176445): Device EPM240T100I5 is compatible
Info (176445): Device EPM240T100A5 is compatible
Info (176445): Device EPM570T100C5 is compatible
Info (176445): Device EPM570T100I5 is compatible
Info (176445): Device EPM570T100A5 is compatible
Info (176445): Device 5M80ZT100C5 is compatible
Info (176445): Device 5M80ZT100I5 is compatible
Info (176445): Device 5M160ZT100C5 is compatible
Info (176445): Device 5M160ZT100I5 is compatible
Info (176445): Device 5M240ZT100I5 is compatible
Info (176445): Device 5M570ZT100C5 is compatible
Info (176445): Device 5M570ZT100I5 is compatible
Info (332104): Reading SDC File: 'constraints.sdc'
Warning (332060): Node: DRCLK was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: ARCLK was determined to be a clock but was found without an associated clock assignment.
@ -955,19 +961,18 @@ Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
Info (170193): Fitter routing operations beginning
Info (170089): 4e+01 ns of routing delay (approximately 2.7% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report.
Info (170195): Router estimated average interconnect usage is 19% of the available device resources
Info (170196): Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
Info (170195): Router estimated average interconnect usage is 17% of the available device resources
Info (170196): Router estimated peak interconnect usage is 17% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
Info (11888): Total time spent on timing analysis during the Fitter is 0.14 seconds.
Info (11888): Total time spent on timing analysis during the Fitter is 0.13 seconds.
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info (144001): Generated suppressed messages file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.fit.smsg
Info: Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings
Info: Peak virtual memory: 4772 megabytes
Info: Processing ended: Tue Jun 02 17:01:04 2020
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:01
Info: Peak virtual memory: 4771 megabytes
Info: Processing ended: Tue Sep 08 19:28:18 2020
Info: Elapsed time: 00:00:03
Info: Total CPU time (on all processors): 00:00:02
+----------------------------+

8
cpld/output_files/RAM2E.fit.summary
View File

@ -1,11 +1,11 @@
Fitter Status : Successful - Tue Jun 02 17:01:04 2020
Fitter Status : Successful - Tue Sep 08 19:28:17 2020
Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : RAM2E
Top-level Entity Name : RAM2E
Family : MAX II
Device : EPM240T100C5
Family : MAX V
Device : 5M240ZT100C5
Timing Models : Final
Total logic elements : 184 / 240 ( 77 % )
Total pins : 69 / 80 ( 86 % )
Total pins : 69 / 79 ( 87 % )
Total virtual pins : 0
UFM blocks : 1 / 1 ( 100 % )

69
cpld/output_files/RAM2E.flow.rpt
View File

@ -1,5 +1,5 @@
Flow report for RAM2E
Tue Jun 02 17:01:07 2020
Tue Sep 08 19:28:21 2020
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -40,15 +40,15 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------+
; Flow Summary ;
+---------------------------+-------------------------------------------------+
; Flow Status ; Successful - Tue Jun 02 17:01:05 2020 ;
; Flow Status ; Successful - Tue Sep 08 19:28:19 2020 ;
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX II ;
; Device ; EPM240T100C5 ;
; Family ; MAX V ;
; Device ; 5M240ZT100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 184 / 240 ( 77 % ) ;
; Total pins ; 69 / 80 ( 86 % ) ;
; Total pins ; 69 / 79 ( 87 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+---------------------------+-------------------------------------------------+
@ -59,36 +59,35 @@ applicable agreement for further details.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 06/02/2020 17:01:01 ;
; Start date & time ; 09/08/2020 19:28:13 ;
; Main task ; Compilation ;
; Revision Name ; RAM2E ;
+-------------------+---------------------+
+--------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+---------------------------------------+---------------------------------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+---------------------------------------+---------------------------------+---------------+-------------+------------+
; ALLOW_POWER_UP_DONT_CARE ; Off ; On ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 207120313862967.159113166102372 ; -- ; -- ; -- ;
; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ;
; IP_TOOL_NAME ; ALTUFM_NONE ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 13.0 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; MISC_FILE ; UFM.bsf ; -- ; -- ; -- ;
; MISC_FILE ; UFM_bb.v ; -- ; -- ; -- ;
; OPTIMIZE_MULTI_CORNER_TIMING ; On ; Off ; -- ; -- ;
; PARALLEL_SYNTHESIS ; Off ; On ; -- ; -- ;
; POWER_DEFAULT_INPUT_IO_TOGGLE_RATE ; 12.5 % ; 12.5% ; -- ; -- ;
; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ;
; POWER_PRESET_COOLING_SOLUTION ; No Heat Sink With Still Air ; -- ; -- ; -- ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
; SAFE_STATE_MACHINE ; On ; Off ; -- ; -- ;
; SYNTH_MESSAGE_LEVEL ; High ; Medium ; -- ; -- ;
; SYNTH_TIMING_DRIVEN_SYNTHESIS ; Off ; -- ; -- ; -- ;
+---------------------------------------+---------------------------------+---------------+-------------+------------+
+-----------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+------------------------------------+---------------------------------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+------------------------------------+---------------------------------+---------------+-------------+------------+
; ALLOW_POWER_UP_DONT_CARE ; Off ; On ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 207120313862967.159960769334468 ; -- ; -- ; -- ;
; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ;
; IP_TOOL_NAME ; ALTUFM_NONE ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 13.0 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; MISC_FILE ; UFM.bsf ; -- ; -- ; -- ;
; MISC_FILE ; UFM_bb.v ; -- ; -- ; -- ;
; OPTIMIZE_MULTI_CORNER_TIMING ; On ; Off ; -- ; -- ;
; PARALLEL_SYNTHESIS ; Off ; On ; -- ; -- ;
; POWER_DEFAULT_INPUT_IO_TOGGLE_RATE ; 12.5 % ; 12.5% ; -- ; -- ;
; POWER_PRESET_COOLING_SOLUTION ; No Heat Sink With Still Air ; -- ; -- ; -- ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
; SAFE_STATE_MACHINE ; On ; Off ; -- ; -- ;
; SYNTH_MESSAGE_LEVEL ; High ; Medium ; -- ; -- ;
; SYNTH_TIMING_DRIVEN_SYNTHESIS ; Off ; -- ; -- ; -- ;
+------------------------------------+---------------------------------+---------------+-------------+------------+
+-------------------------------------------------------------------------------------------------------------------------------+
@ -96,11 +95,11 @@ applicable agreement for further details.
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 4574 MB ; 00:00:01 ;
; Fitter ; 00:00:02 ; 1.0 ; 4772 MB ; 00:00:01 ;
; Assembler ; 00:00:00 ; 1.0 ; 4523 MB ; 00:00:00 ;
; TimeQuest Timing Analyzer ; 00:00:01 ; 1.0 ; 4522 MB ; 00:00:01 ;
; Total ; 00:00:04 ; -- ; -- ; 00:00:03 ;
; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 4577 MB ; 00:00:01 ;
; Fitter ; 00:00:02 ; 1.0 ; 4771 MB ; 00:00:02 ;
; Assembler ; 00:00:01 ; 1.0 ; 4524 MB ; 00:00:00 ;
; TimeQuest Timing Analyzer ; 00:00:01 ; 1.0 ; 4528 MB ; 00:00:01 ;
; Total ; 00:00:05 ; -- ; -- ; 00:00:04 ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+

4
cpld/output_files/RAM2E.jdi
View File

@ -1,8 +1,8 @@
<sld_project_info>
<project>
<hash md5_digest_80b="630f733e3f02bcb8a3ce"/>
<hash md5_digest_80b="56678bba3097e929c412"/>
</project>
<file_info>
<file device="EPM240T100C5" path="RAM2E.sof" usercode="0xFFFFFFFF"/>
<file device="5M240ZT100C5" path="RAM2E.sof" usercode="0xFFFFFFFF"/>
</file_info>
</sld_project_info>

37
cpld/output_files/RAM2E.map.rpt
View File

@ -1,5 +1,5 @@
Analysis & Synthesis report for RAM2E
Tue Jun 02 17:01:02 2020
Tue Sep 08 19:28:14 2020
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -45,11 +45,11 @@ applicable agreement for further details.
+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Jun 02 17:01:02 2020 ;
; Analysis & Synthesis Status ; Successful - Tue Sep 08 19:28:14 2020 ;
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX II ;
; Family ; MAX V ;
; Total logic elements ; 193 ;
; Total pins ; 69 ;
; Total virtual pins ; 0 ;
@ -62,9 +62,9 @@ applicable agreement for further details.
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device ; EPM240T100C5 ; ;
; Device ; 5M240ZT100C5 ; ;
; Top-level entity name ; RAM2E ; RAM2E ;
; Family name ; MAX II ; Cyclone IV GX ;
; Family name ; MAX V ; Cyclone IV GX ;
; Safe State Machine ; On ; Off ;
; Parallel Synthesis ; Off ; On ;
; Power-Up Don't Care ; Off ; On ;
@ -147,7 +147,7 @@ Parallel compilation was disabled, but you have multiple processors available. E
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+----------------------------------+-----------------------------------------------------+---------+
; RAM2E.v ; yes ; User Verilog HDL File ; C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v ; ;
; UFM.v ; yes ; User Wizard-Generated File ; C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v ; ;
; db/UFM.v ; yes ; Auto-Generated Megafunction ; C:/Users/Zane/Documents/GitHub/RAM2E/cpld/db/UFM.v ; ;
; RAM2E.mif ; yes ; User Memory Initialization File ; C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.mif ; ;
+----------------------------------+-----------------+----------------------------------+-----------------------------------------------------+---------+
@ -200,13 +200,13 @@ Parallel compilation was disabled, but you have multiple processors available. E
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+---------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary ;
+--------+--------------+---------+--------------+--------------+---------------------+-------------------------------------------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ;
+--------+--------------+---------+--------------+--------------+---------------------+-------------------------------------------------+
; Altera ; ALTUFM_NONE ; 13.0 ; N/A ; N/A ; |RAM2E|UFM:UFM_inst ; C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v ;
+--------+--------------+---------+--------------+--------------+---------------------+-------------------------------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary ;
+--------+--------------+---------+--------------+--------------+---------------------+----------------------------------------------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ;
+--------+--------------+---------+--------------+--------------+---------------------+----------------------------------------------------+
; Altera ; ALTUFM_NONE ; 13.0 ; N/A ; N/A ; |RAM2E|UFM:UFM_inst ; C:/Users/Zane/Documents/GitHub/RAM2E/cpld/db/UFM.v ;
+--------+--------------+---------+--------------+--------------+---------------------+----------------------------------------------------+
+------------------------------------------------------+
@ -268,12 +268,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Tue Jun 02 17:01:01 2020
Info: Processing started: Tue Sep 08 19:28:13 2020
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 1 design units, including 1 entities, in source file ram2e.v
Info (12023): Found entity 1: RAM2E
Info (12021): Found 2 design units, including 2 entities, in source file ufm.v
Warning (12136): Clear box output file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v is not compatible with the current compile. Used regenerated output file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/db/UFM.v for elaboration
Info (12021): Found 2 design units, including 2 entities, in source file db/ufm.v
Info (12023): Found entity 1: UFM_altufm_none_a7r
Info (12023): Found entity 2: UFM
Info (12127): Elaborating entity "RAM2E" for the top level hierarchy
@ -290,9 +291,9 @@ Info (21057): Implemented 263 device resources after synthesis - the final resou
Info (21061): Implemented 193 logic cells
Info (21070): Implemented 1 User Flash Memory blocks
Info (144001): Generated suppressed messages file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 5 warnings
Info: Peak virtual memory: 4574 megabytes
Info: Processing ended: Tue Jun 02 17:01:02 2020
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 6 warnings
Info: Peak virtual memory: 4577 megabytes
Info: Processing ended: Tue Sep 08 19:28:14 2020
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01

4
cpld/output_files/RAM2E.map.summary
View File

@ -1,8 +1,8 @@
Analysis & Synthesis Status : Successful - Tue Jun 02 17:01:02 2020
Analysis & Synthesis Status : Successful - Tue Sep 08 19:28:14 2020
Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : RAM2E
Top-level Entity Name : RAM2E
Family : MAX II
Family : MAX V
Total logic elements : 193
Total pins : 69
Total virtual pins : 0

26
cpld/output_files/RAM2E.pin
View File

@ -23,7 +23,7 @@
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- DNU : Do Not Use. This pin MUST NOT be connected.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (2.5V/3.3V).
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.8V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 1: 3.3V
@ -58,11 +58,11 @@
---------------------------------------------------------------------------------
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
CHIP "RAM2E" ASSIGNED TO AN: EPM240T100C5
CHIP "RAM2E" ASSIGNED TO AN: 5M240ZT100C5
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
GND* : 1 : : : : 2 :
GND : 1 : gnd : : : :
nRWE : 2 : output : 3.3-V LVCMOS : : 1 : Y
nCAS : 3 : output : 3.3-V LVCMOS : : 1 : Y
CKE : 4 : output : 3.3-V LVCMOS : : 1 : Y
@ -71,10 +71,10 @@ BA[0] : 6 : output : 3.3-V LVCMOS :
RA[11] : 7 : output : 3.3-V LVCMOS : : 1 : Y
nCS : 8 : output : 3.3-V LVCMOS : : 1 : Y
VCCIO1 : 9 : power : : 3.3V : 1 :
GNDIO : 10 : gnd : : : :
GNDINT : 11 : gnd : : : :
GND : 10 : gnd : : : :
GND : 11 : gnd : : : :
C14M : 12 : input : 3.3-V LVCMOS : : 1 : Y
VCCINT : 13 : power : : 2.5V/3.3V : :
VCCINT : 13 : power : : 1.8V : :
BA[1] : 14 : output : 3.3-V LVCMOS : : 1 : Y
RA[9] : 15 : output : 3.3-V LVCMOS : : 1 : Y
RA[10] : 16 : output : 3.3-V LVCMOS : : 1 : Y
@ -93,7 +93,7 @@ nEN80 : 28 : input : 3.3-V LVCMOS :
RA[5] : 29 : output : 3.3-V LVCMOS : : 1 : Y
RA[2] : 30 : output : 3.3-V LVCMOS : : 1 : Y
VCCIO1 : 31 : power : : 3.3V : 1 :
GNDIO : 32 : gnd : : : :
GND : 32 : gnd : : : :
nWE80 : 33 : input : 3.3-V LVCMOS : : 1 : Y
Ain[5] : 34 : input : 3.3-V LVCMOS : : 1 : Y
Din[7] : 35 : input : 3.3-V LVCMOS : : 1 : Y
@ -107,7 +107,7 @@ Din[2] : 42 : input : 3.3-V LVCMOS :
Ain[2] : 43 : input : 3.3-V LVCMOS : : 1 : Y
Ain[4] : 44 : input : 3.3-V LVCMOS : : 1 : Y
VCCIO1 : 45 : power : : 3.3V : 1 :
GNDIO : 46 : gnd : : : :
GND : 46 : gnd : : : :
Ain[3] : 47 : input : 3.3-V LVCMOS : : 1 : Y
Din[4] : 48 : input : 3.3-V LVCMOS : : 1 : Y
Din[5] : 49 : input : 3.3-V LVCMOS : : 1 : Y
@ -121,12 +121,12 @@ Ain[0] : 56 : input : 3.3-V LVCMOS :
Vout[7] : 57 : output : 3.3-V LVCMOS : : 2 : Y
Vout[6] : 58 : output : 3.3-V LVCMOS : : 2 : Y
VCCIO2 : 59 : power : : 3.3V : 2 :
GNDIO : 60 : gnd : : : :
GND : 60 : gnd : : : :
GND* : 61 : : : : 2 :
Vout[3] : 62 : output : 3.3-V LVCMOS : : 2 : Y
VCCINT : 63 : power : : 2.5V/3.3V : :
VCCINT : 63 : power : : 1.8V : :
GND* : 64 : : : : 2 :
GNDINT : 65 : gnd : : : :
GND : 65 : gnd : : : :
GND* : 66 : : : : 2 :
Vout[1] : 67 : output : 3.3-V LVCMOS : : 2 : Y
Vout[5] : 68 : output : 3.3-V LVCMOS : : 2 : Y
@ -140,7 +140,7 @@ Dout[3] : 75 : output : 3.3-V LVCMOS :
Dout[1] : 76 : output : 3.3-V LVCMOS : : 2 : Y
Dout[0] : 77 : output : 3.3-V LVCMOS : : 2 : Y
GND* : 78 : : : : 2 :
GNDIO : 79 : gnd : : : :
GND : 79 : gnd : : : :
VCCIO2 : 80 : power : : 3.3V : 2 :
GND* : 81 : : : : 2 :
GND* : 82 : : : : 2 :
@ -154,7 +154,7 @@ RD[3] : 89 : bidir : 3.3-V LVCMOS :
RD[1] : 90 : bidir : 3.3-V LVCMOS : : 2 : Y
RD[4] : 91 : bidir : 3.3-V LVCMOS : : 2 : Y
RD[5] : 92 : bidir : 3.3-V LVCMOS : : 2 : Y
GNDIO : 93 : gnd : : : :
GND : 93 : gnd : : : :
VCCIO2 : 94 : power : : 3.3V : 2 :
RD[6] : 95 : bidir : 3.3-V LVCMOS : : 2 : Y
RD[7] : 96 : bidir : 3.3-V LVCMOS : : 2 : Y

BIN
cpld/output_files/RAM2E.pof
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1060
cpld/output_files/RAM2E.sta.rpt
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File diff suppressed because it is too large Load Diff

6
cpld/output_files/RAM2E.sta.summary
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@ -3,15 +3,15 @@ TimeQuest Timing Analyzer Summary
------------------------------------------------------------
Type : Setup 'C14M'
Slack : 28.330
Slack : 22.276
TNS : 0.000
Type : Hold 'C14M'
Slack : 1.425
Slack : 3.130
TNS : 0.000
Type : Minimum Pulse Width 'C14M'
Slack : 34.654
Slack : 34.581
TNS : 0.000
------------------------------------------------------------