Place & Route TRACE Report

Loading design for application trce from file ram2e_lcmxo2_640hc_impl1.ncd.
Design name: RAM2E
NCD version: 3.3
Vendor:      LATTICE
Device:      LCMXO2-640HC
Package:     TQFP100
Performance: 4
Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status:                     Final          Version 1.39.
Performance Hardware Data Status:   Final          Version 34.4.
Setup and Hold Report

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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
Thu Dec 28 23:23:44 2023

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
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Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2E_LCMXO2_640HC_impl1.twr -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf 
Design file:     ram2e_lcmxo2_640hc_impl1.ncd
Preference file: ram2e_lcmxo2_640hc_impl1.prf
Device,speed:    LCMXO2-640HC,4
Report level:    verbose report, limited to 10 items per preference
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Preference Summary

  • FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)
  • 1611 items scored, 0 timing errors detected. Report: 83.389MHz is the maximum frequency for this preference. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY PORT "C14M" 14.300000 MHz ; 1611 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 57.938ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q S[0] (from C14M_c +) Destination: FF Data in ram2e_ufm/wb_adr[0] (to C14M_c +) Delay: 11.826ns (24.8% logic, 75.2% route), 6 logic levels. Constraint Details: 11.826ns physical path delay SLICE_33 to ram2e_ufm/SLICE_47 meets 69.930ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 69.764ns) by 57.938ns Physical Path Details: Data path SLICE_33 to ram2e_ufm/SLICE_47: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R6C10C.CLK to R6C10C.Q0 SLICE_33 (from C14M_c) ROUTE 37 2.491 R6C10C.Q0 to R6C9B.D1 S[0] CTOF_DEL --- 0.495 R6C9B.D1 to R6C9B.F1 ram2e_ufm/SLICE_80 ROUTE 8 2.866 R6C9B.F1 to R3C5B.B1 ram2e_ufm/N_777 CTOF_DEL --- 0.495 R3C5B.B1 to R3C5B.F1 ram2e_ufm/SLICE_89 ROUTE 6 1.040 R3C5B.F1 to R4C5C.B1 ram2e_ufm/N_783 CTOF_DEL --- 0.495 R4C5C.B1 to R4C5C.F1 ram2e_ufm/SLICE_68 ROUTE 1 0.967 R4C5C.F1 to R4C5A.A0 ram2e_ufm/wb_adr_7_i_i_3[0] CTOF_DEL --- 0.495 R4C5A.A0 to R4C5A.F0 ram2e_ufm/SLICE_86 ROUTE 1 1.535 R4C5A.F0 to R3C6C.B0 ram2e_ufm/wb_adr_7_i_i_4[0] CTOF_DEL --- 0.495 R3C6C.B0 to R3C6C.F0 ram2e_ufm/SLICE_47 ROUTE 1 0.000 R3C6C.F0 to R3C6C.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c) -------- 11.826 (24.8% logic, 75.2% route), 6 logic levels. Clock Skew Details: Source Clock Path C14M to SLICE_33: Name Fanout Delay (ns) Site Resource ROUTE 89 3.070 62.PADDI to R6C10C.CLK C14M_c -------- 3.070 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to ram2e_ufm/SLICE_47: Name Fanout Delay (ns) Site Resource ROUTE 89 3.070 62.PADDI to R3C6C.CLK C14M_c -------- 3.070 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 57.944ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q S[3] (from C14M_c +) Destination: FF Data in ram2e_ufm/wb_adr[0] (to C14M_c +) Delay: 11.820ns (29.0% logic, 71.0% route), 7 logic levels. Constraint Details: 11.820ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets 69.930ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 69.764ns) by 57.944ns Physical Path Details: Data path SLICE_34 to ram2e_ufm/SLICE_47: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R6C10D.CLK to R6C10D.Q1 SLICE_34 (from C14M_c) ROUTE 45 1.001 R6C10D.Q1 to R6C10A.A0 S[3] CTOF_DEL --- 0.495 R6C10A.A0 to R6C10A.F0 SLICE_35 ROUTE 7 0.989 R6C10A.F0 to R6C9B.A1 N_551 CTOF_DEL --- 0.495 R6C9B.A1 to R6C9B.F1 ram2e_ufm/SLICE_80 ROUTE 8 2.866 R6C9B.F1 to R3C5B.B1 ram2e_ufm/N_777 CTOF_DEL --- 0.495 R3C5B.B1 to R3C5B.F1 ram2e_ufm/SLICE_89 ROUTE 6 1.040 R3C5B.F1 to R4C5C.B1 ram2e_ufm/N_783 CTOF_DEL --- 0.495 R4C5C.B1 to R4C5C.F1 ram2e_ufm/SLICE_68 ROUTE 1 0.967 R4C5C.F1 to R4C5A.A0 ram2e_ufm/wb_adr_7_i_i_3[0] CTOF_DEL --- 0.495 R4C5A.A0 to R4C5A.F0 ram2e_ufm/SLICE_86 ROUTE 1 1.535 R4C5A.F0 to R3C6C.B0 ram2e_ufm/wb_adr_7_i_i_4[0] CTOF_DEL --- 0.495 R3C6C.B0 to R3C6C.F0 ram2e_ufm/SLICE_47 ROUTE 1 0.000 R3C6C.F0 to R3C6C.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c) -------- 11.820 (29.0% logic, 71.0% route), 7 logic levels. Clock Skew Details: Source Clock Path C14M to SLICE_34: Name Fanout Delay (ns) Site Resource ROUTE 89 3.070 62.PADDI to R6C10D.CLK C14M_c -------- 3.070 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to ram2e_ufm/SLICE_47: Name Fanout Delay (ns) Site Resource ROUTE 89 3.070 62.PADDI to R3C6C.CLK C14M_c -------- 3.070 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 58.190ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[15] (from C14M_c +) Destination: FF Data in ram2e_ufm/wb_adr[0] (to C14M_c +) Delay: 11.574ns (25.3% logic, 74.7% route), 6 logic levels. Constraint Details: 11.574ns physical path delay SLICE_1 to ram2e_ufm/SLICE_47 meets 69.930ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.190ns Physical Path Details: Data path SLICE_1 to ram2e_ufm/SLICE_47: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R2C11A.CLK to R2C11A.Q0 SLICE_1 (from C14M_c) ROUTE 9 2.239 R2C11A.Q0 to R6C9B.C1 FS[15] CTOF_DEL --- 0.495 R6C9B.C1 to R6C9B.F1 ram2e_ufm/SLICE_80 ROUTE 8 2.866 R6C9B.F1 to R3C5B.B1 ram2e_ufm/N_777 CTOF_DEL --- 0.495 R3C5B.B1 to R3C5B.F1 ram2e_ufm/SLICE_89 ROUTE 6 1.040 R3C5B.F1 to R4C5C.B1 ram2e_ufm/N_783 CTOF_DEL --- 0.495 R4C5C.B1 to R4C5C.F1 ram2e_ufm/SLICE_68 ROUTE 1 0.967 R4C5C.F1 to R4C5A.A0 ram2e_ufm/wb_adr_7_i_i_3[0] CTOF_DEL --- 0.495 R4C5A.A0 to R4C5A.F0 ram2e_ufm/SLICE_86 ROUTE 1 1.535 R4C5A.F0 to R3C6C.B0 ram2e_ufm/wb_adr_7_i_i_4[0] CTOF_DEL --- 0.495 R3C6C.B0 to R3C6C.F0 ram2e_ufm/SLICE_47 ROUTE 1 0.000 R3C6C.F0 to R3C6C.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c) -------- 11.574 (25.3% logic, 74.7% route), 6 logic levels. Clock Skew Details: Source Clock Path C14M to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 89 3.070 62.PADDI to R2C11A.CLK C14M_c -------- 3.070 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to ram2e_ufm/SLICE_47: Name Fanout Delay (ns) Site Resource ROUTE 89 3.070 62.PADDI to R3C6C.CLK C14M_c -------- 3.070 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 58.271ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q S[2] (from C14M_c +) Destination: FF Data in ram2e_ufm/wb_adr[0] (to C14M_c +) Delay: 11.493ns (29.8% logic, 70.2% route), 7 logic levels. Constraint Details: 11.493ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets 69.930ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.271ns Physical Path Details: Data path SLICE_34 to ram2e_ufm/SLICE_47: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R6C10D.CLK to R6C10D.Q0 SLICE_34 (from C14M_c) ROUTE 50 0.674 R6C10D.Q0 to R6C10A.D0 S[2] CTOF_DEL --- 0.495 R6C10A.D0 to R6C10A.F0 SLICE_35 ROUTE 7 0.989 R6C10A.F0 to R6C9B.A1 N_551 CTOF_DEL --- 0.495 R6C9B.A1 to R6C9B.F1 ram2e_ufm/SLICE_80 ROUTE 8 2.866 R6C9B.F1 to R3C5B.B1 ram2e_ufm/N_777 CTOF_DEL --- 0.495 R3C5B.B1 to R3C5B.F1 ram2e_ufm/SLICE_89 ROUTE 6 1.040 R3C5B.F1 to R4C5C.B1 ram2e_ufm/N_783 CTOF_DEL --- 0.495 R4C5C.B1 to R4C5C.F1 ram2e_ufm/SLICE_68 ROUTE 1 0.967 R4C5C.F1 to R4C5A.A0 ram2e_ufm/wb_adr_7_i_i_3[0] CTOF_DEL --- 0.495 R4C5A.A0 to R4C5A.F0 ram2e_ufm/SLICE_86 ROUTE 1 1.535 R4C5A.F0 to R3C6C.B0 ram2e_ufm/wb_adr_7_i_i_4[0] CTOF_DEL --- 0.495 R3C6C.B0 to R3C6C.F0 ram2e_ufm/SLICE_47 ROUTE 1 0.000 R3C6C.F0 to R3C6C.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c) -------- 11.493 (29.8% logic, 70.2% route), 7 logic levels. Clock Skew Details: Source Clock Path C14M to SLICE_34: Name Fanout Delay (ns) Site Resource ROUTE 89 3.070 62.PADDI to R6C10D.CLK C14M_c -------- 3.070 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to ram2e_ufm/SLICE_47: Name Fanout Delay (ns) Site Resource ROUTE 89 3.070 62.PADDI to R3C6C.CLK C14M_c -------- 3.070 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 58.733ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q S[0] (from C14M_c +) Destination: FF Data in ram2e_ufm/wb_dati[2] (to C14M_c +) Delay: 11.031ns (26.5% logic, 73.5% route), 6 logic levels. Constraint Details: 11.031ns physical path delay SLICE_33 to ram2e_ufm/SLICE_53 meets 69.930ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.733ns Physical Path Details: Data path SLICE_33 to ram2e_ufm/SLICE_53: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R6C10C.CLK to R6C10C.Q0 SLICE_33 (from C14M_c) ROUTE 37 2.491 R6C10C.Q0 to R6C9B.D1 S[0] CTOF_DEL --- 0.495 R6C9B.D1 to R6C9B.F1 ram2e_ufm/SLICE_80 ROUTE 8 1.621 R6C9B.F1 to R2C7D.D1 ram2e_ufm/N_777 CTOF_DEL --- 0.495 R2C7D.D1 to R2C7D.F1 ram2e_ufm/SLICE_70 ROUTE 3 0.981 R2C7D.F1 to R2C6D.A1 ram2e_ufm/N_807 CTOF_DEL --- 0.495 R2C6D.A1 to R2C6D.F1 ram2e_ufm/SLICE_111 ROUTE 3 2.253 R2C6D.F1 to R3C4C.A1 ram2e_ufm/N_611 CTOF_DEL --- 0.495 R3C4C.A1 to R3C4C.F1 ram2e_ufm/SLICE_73 ROUTE 2 0.758 R3C4C.F1 to R2C4B.C0 ram2e_ufm/wb_dati_7_0_0_o3_0[2] CTOF_DEL --- 0.495 R2C4B.C0 to R2C4B.F0 ram2e_ufm/SLICE_53 ROUTE 1 0.000 R2C4B.F0 to R2C4B.DI0 ram2e_ufm/wb_dati_7[2] (to C14M_c) -------- 11.031 (26.5% logic, 73.5% route), 6 logic levels. Clock Skew Details: Source Clock Path C14M to SLICE_33: Name Fanout Delay (ns) Site Resource ROUTE 89 3.070 62.PADDI to R6C10C.CLK C14M_c -------- 3.070 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to ram2e_ufm/SLICE_53: Name Fanout Delay (ns) Site Resource ROUTE 89 3.070 62.PADDI to R2C4B.CLK C14M_c -------- 3.070 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 58.733ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q S[0] (from C14M_c +) Destination: FF Data in ram2e_ufm/wb_dati[5] (to C14M_c +) Delay: 11.031ns (26.5% logic, 73.5% route), 6 logic levels. Constraint Details: 11.031ns physical path delay SLICE_33 to ram2e_ufm/SLICE_54 meets 69.930ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.733ns Physical Path Details: Data path SLICE_33 to ram2e_ufm/SLICE_54: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R6C10C.CLK to R6C10C.Q0 SLICE_33 (from C14M_c) ROUTE 37 2.491 R6C10C.Q0 to R6C9B.D1 S[0] CTOF_DEL --- 0.495 R6C9B.D1 to R6C9B.F1 ram2e_ufm/SLICE_80 ROUTE 8 1.621 R6C9B.F1 to R2C7D.D1 ram2e_ufm/N_777 CTOF_DEL --- 0.495 R2C7D.D1 to R2C7D.F1 ram2e_ufm/SLICE_70 ROUTE 3 0.981 R2C7D.F1 to R2C6D.A1 ram2e_ufm/N_807 CTOF_DEL --- 0.495 R2C6D.A1 to R2C6D.F1 ram2e_ufm/SLICE_111 ROUTE 3 2.253 R2C6D.F1 to R3C4C.A1 ram2e_ufm/N_611 CTOF_DEL --- 0.495 R3C4C.A1 to R3C4C.F1 ram2e_ufm/SLICE_73 ROUTE 2 0.758 R3C4C.F1 to R2C4D.C1 ram2e_ufm/wb_dati_7_0_0_o3_0[2] CTOF_DEL --- 0.495 R2C4D.C1 to R2C4D.F1 ram2e_ufm/SLICE_54 ROUTE 1 0.000 R2C4D.F1 to R2C4D.DI1 ram2e_ufm/wb_dati_7[5] (to C14M_c) -------- 11.031 (26.5% logic, 73.5% route), 6 logic levels. Clock Skew Details: Source Clock Path C14M to SLICE_33: Name Fanout Delay (ns) Site Resource ROUTE 89 3.070 62.PADDI to R6C10C.CLK C14M_c -------- 3.070 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to ram2e_ufm/SLICE_54: Name Fanout Delay (ns) Site Resource ROUTE 89 3.070 62.PADDI to R2C4D.CLK C14M_c -------- 3.070 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 58.739ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q S[3] (from C14M_c +) Destination: FF Data in ram2e_ufm/wb_dati[5] (to C14M_c +) Delay: 11.025ns (31.0% logic, 69.0% route), 7 logic levels. Constraint Details: 11.025ns physical path delay SLICE_34 to ram2e_ufm/SLICE_54 meets 69.930ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.739ns Physical Path Details: Data path SLICE_34 to ram2e_ufm/SLICE_54: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R6C10D.CLK to R6C10D.Q1 SLICE_34 (from C14M_c) ROUTE 45 1.001 R6C10D.Q1 to R6C10A.A0 S[3] CTOF_DEL --- 0.495 R6C10A.A0 to R6C10A.F0 SLICE_35 ROUTE 7 0.989 R6C10A.F0 to R6C9B.A1 N_551 CTOF_DEL --- 0.495 R6C9B.A1 to R6C9B.F1 ram2e_ufm/SLICE_80 ROUTE 8 1.621 R6C9B.F1 to R2C7D.D1 ram2e_ufm/N_777 CTOF_DEL --- 0.495 R2C7D.D1 to R2C7D.F1 ram2e_ufm/SLICE_70 ROUTE 3 0.981 R2C7D.F1 to R2C6D.A1 ram2e_ufm/N_807 CTOF_DEL --- 0.495 R2C6D.A1 to R2C6D.F1 ram2e_ufm/SLICE_111 ROUTE 3 2.253 R2C6D.F1 to R3C4C.A1 ram2e_ufm/N_611 CTOF_DEL --- 0.495 R3C4C.A1 to R3C4C.F1 ram2e_ufm/SLICE_73 ROUTE 2 0.758 R3C4C.F1 to R2C4D.C1 ram2e_ufm/wb_dati_7_0_0_o3_0[2] CTOF_DEL --- 0.495 R2C4D.C1 to R2C4D.F1 ram2e_ufm/SLICE_54 ROUTE 1 0.000 R2C4D.F1 to R2C4D.DI1 ram2e_ufm/wb_dati_7[5] (to C14M_c) -------- 11.025 (31.0% logic, 69.0% route), 7 logic levels. Clock Skew Details: Source Clock Path C14M to SLICE_34: Name Fanout Delay (ns) Site Resource ROUTE 89 3.070 62.PADDI to R6C10D.CLK C14M_c -------- 3.070 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to ram2e_ufm/SLICE_54: Name Fanout Delay (ns) Site Resource ROUTE 89 3.070 62.PADDI to R2C4D.CLK C14M_c -------- 3.070 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 58.739ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q S[3] (from C14M_c +) Destination: FF Data in ram2e_ufm/wb_dati[2] (to C14M_c +) Delay: 11.025ns (31.0% logic, 69.0% route), 7 logic levels. Constraint Details: 11.025ns physical path delay SLICE_34 to ram2e_ufm/SLICE_53 meets 69.930ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.739ns Physical Path Details: Data path SLICE_34 to ram2e_ufm/SLICE_53: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R6C10D.CLK to R6C10D.Q1 SLICE_34 (from C14M_c) ROUTE 45 1.001 R6C10D.Q1 to R6C10A.A0 S[3] CTOF_DEL --- 0.495 R6C10A.A0 to R6C10A.F0 SLICE_35 ROUTE 7 0.989 R6C10A.F0 to R6C9B.A1 N_551 CTOF_DEL --- 0.495 R6C9B.A1 to R6C9B.F1 ram2e_ufm/SLICE_80 ROUTE 8 1.621 R6C9B.F1 to R2C7D.D1 ram2e_ufm/N_777 CTOF_DEL --- 0.495 R2C7D.D1 to R2C7D.F1 ram2e_ufm/SLICE_70 ROUTE 3 0.981 R2C7D.F1 to R2C6D.A1 ram2e_ufm/N_807 CTOF_DEL --- 0.495 R2C6D.A1 to R2C6D.F1 ram2e_ufm/SLICE_111 ROUTE 3 2.253 R2C6D.F1 to R3C4C.A1 ram2e_ufm/N_611 CTOF_DEL --- 0.495 R3C4C.A1 to R3C4C.F1 ram2e_ufm/SLICE_73 ROUTE 2 0.758 R3C4C.F1 to R2C4B.C0 ram2e_ufm/wb_dati_7_0_0_o3_0[2] CTOF_DEL --- 0.495 R2C4B.C0 to R2C4B.F0 ram2e_ufm/SLICE_53 ROUTE 1 0.000 R2C4B.F0 to R2C4B.DI0 ram2e_ufm/wb_dati_7[2] (to C14M_c) -------- 11.025 (31.0% logic, 69.0% route), 7 logic levels. Clock Skew Details: Source Clock Path C14M to SLICE_34: Name Fanout Delay (ns) Site Resource ROUTE 89 3.070 62.PADDI to R6C10D.CLK C14M_c -------- 3.070 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to ram2e_ufm/SLICE_53: Name Fanout Delay (ns) Site Resource ROUTE 89 3.070 62.PADDI to R2C4B.CLK C14M_c -------- 3.070 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 58.780ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q S[0] (from C14M_c +) Destination: FF Data in ram2e_ufm/wb_adr[0] (to C14M_c +) Delay: 10.984ns (26.6% logic, 73.4% route), 6 logic levels. Constraint Details: 10.984ns physical path delay SLICE_33 to ram2e_ufm/SLICE_47 meets 69.930ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.780ns Physical Path Details: Data path SLICE_33 to ram2e_ufm/SLICE_47: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R6C10C.CLK to R6C10C.Q0 SLICE_33 (from C14M_c) ROUTE 37 2.491 R6C10C.Q0 to R6C9B.D1 S[0] CTOF_DEL --- 0.495 R6C9B.D1 to R6C9B.F1 ram2e_ufm/SLICE_80 ROUTE 8 2.182 R6C9B.F1 to R2C5A.C1 ram2e_ufm/N_777 CTOF_DEL --- 0.495 R2C5A.C1 to R2C5A.F1 ram2e_ufm/SLICE_98 ROUTE 5 1.413 R2C5A.F1 to R4C5B.D0 ram2e_ufm/N_781 CTOF_DEL --- 0.495 R4C5B.D0 to R4C5B.F0 ram2e_ufm/SLICE_126 ROUTE 1 0.436 R4C5B.F0 to R4C5A.C0 ram2e_ufm/N_753 CTOF_DEL --- 0.495 R4C5A.C0 to R4C5A.F0 ram2e_ufm/SLICE_86 ROUTE 1 1.535 R4C5A.F0 to R3C6C.B0 ram2e_ufm/wb_adr_7_i_i_4[0] CTOF_DEL --- 0.495 R3C6C.B0 to R3C6C.F0 ram2e_ufm/SLICE_47 ROUTE 1 0.000 R3C6C.F0 to R3C6C.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c) -------- 10.984 (26.6% logic, 73.4% route), 6 logic levels. Clock Skew Details: Source Clock Path C14M to SLICE_33: Name Fanout Delay (ns) Site Resource ROUTE 89 3.070 62.PADDI to R6C10C.CLK C14M_c -------- 3.070 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to ram2e_ufm/SLICE_47: Name Fanout Delay (ns) Site Resource ROUTE 89 3.070 62.PADDI to R3C6C.CLK C14M_c -------- 3.070 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 58.786ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q S[3] (from C14M_c +) Destination: FF Data in ram2e_ufm/wb_adr[0] (to C14M_c +) Delay: 10.978ns (31.2% logic, 68.8% route), 7 logic levels. Constraint Details: 10.978ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets 69.930ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.786ns Physical Path Details: Data path SLICE_34 to ram2e_ufm/SLICE_47: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R6C10D.CLK to R6C10D.Q1 SLICE_34 (from C14M_c) ROUTE 45 1.001 R6C10D.Q1 to R6C10A.A0 S[3] CTOF_DEL --- 0.495 R6C10A.A0 to R6C10A.F0 SLICE_35 ROUTE 7 0.989 R6C10A.F0 to R6C9B.A1 N_551 CTOF_DEL --- 0.495 R6C9B.A1 to R6C9B.F1 ram2e_ufm/SLICE_80 ROUTE 8 2.182 R6C9B.F1 to R2C5A.C1 ram2e_ufm/N_777 CTOF_DEL --- 0.495 R2C5A.C1 to R2C5A.F1 ram2e_ufm/SLICE_98 ROUTE 5 1.413 R2C5A.F1 to R4C5B.D0 ram2e_ufm/N_781 CTOF_DEL --- 0.495 R4C5B.D0 to R4C5B.F0 ram2e_ufm/SLICE_126 ROUTE 1 0.436 R4C5B.F0 to R4C5A.C0 ram2e_ufm/N_753 CTOF_DEL --- 0.495 R4C5A.C0 to R4C5A.F0 ram2e_ufm/SLICE_86 ROUTE 1 1.535 R4C5A.F0 to R3C6C.B0 ram2e_ufm/wb_adr_7_i_i_4[0] CTOF_DEL --- 0.495 R3C6C.B0 to R3C6C.F0 ram2e_ufm/SLICE_47 ROUTE 1 0.000 R3C6C.F0 to R3C6C.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c) -------- 10.978 (31.2% logic, 68.8% route), 7 logic levels. Clock Skew Details: Source Clock Path C14M to SLICE_34: Name Fanout Delay (ns) Site Resource ROUTE 89 3.070 62.PADDI to R6C10D.CLK C14M_c -------- 3.070 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to ram2e_ufm/SLICE_47: Name Fanout Delay (ns) Site Resource ROUTE 89 3.070 62.PADDI to R3C6C.CLK C14M_c -------- 3.070 (0.0% logic, 100.0% route), 0 logic levels. Report: 83.389MHz is the maximum frequency for this preference. Report Summary -------------- ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY PORT "C14M" 14.300000 MHz ; | 14.300 MHz| 83.389 MHz| 6 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: C14M_c Source: C14M.PAD Loads: 89 Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ; Timing summary (Setup): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 Thu Dec 28 23:23:44 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2E_LCMXO2_640HC_impl1.twr -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf Design file: ram2e_lcmxo2_640hc_impl1.ncd Preference file: ram2e_lcmxo2_640hc_impl1.prf Device,speed: LCMXO2-640HC,m Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- Preference Summary
  • FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)
  • 1611 items scored, 0 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY PORT "C14M" 14.300000 MHz ; 1611 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[15] (from C14M_c +) Destination: FF Data in FS[15] (to C14M_c +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay SLICE_1 to SLICE_1 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path SLICE_1 to SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R2C11A.CLK to R2C11A.Q0 SLICE_1 (from C14M_c) ROUTE 9 0.132 R2C11A.Q0 to R2C11A.A0 FS[15] CTOF_DEL --- 0.101 R2C11A.A0 to R2C11A.F0 SLICE_1 ROUTE 1 0.000 R2C11A.F0 to R2C11A.DI0 FS_s[15] (to C14M_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path C14M to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 89 1.059 62.PADDI to R2C11A.CLK C14M_c -------- 1.059 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 89 1.059 62.PADDI to R2C11A.CLK C14M_c -------- 1.059 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CmdTout[2] (from C14M_c +) Destination: FF Data in CmdTout[2] (to C14M_c +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay SLICE_18 to SLICE_18 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path SLICE_18 to SLICE_18: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C9B.CLK to R5C9B.Q1 SLICE_18 (from C14M_c) ROUTE 2 0.132 R5C9B.Q1 to R5C9B.A1 CmdTout[2] CTOF_DEL --- 0.101 R5C9B.A1 to R5C9B.F1 SLICE_18 ROUTE 1 0.000 R5C9B.F1 to R5C9B.DI1 N_369_i (to C14M_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path C14M to SLICE_18: Name Fanout Delay (ns) Site Resource ROUTE 89 1.059 62.PADDI to R5C9B.CLK C14M_c -------- 1.059 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to SLICE_18: Name Fanout Delay (ns) Site Resource ROUTE 89 1.059 62.PADDI to R5C9B.CLK C14M_c -------- 1.059 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CmdTout[1] (from C14M_c +) Destination: FF Data in CmdTout[1] (to C14M_c +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay SLICE_18 to SLICE_18 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path SLICE_18 to SLICE_18: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C9B.CLK to R5C9B.Q0 SLICE_18 (from C14M_c) ROUTE 3 0.132 R5C9B.Q0 to R5C9B.A0 CmdTout[1] CTOF_DEL --- 0.101 R5C9B.A0 to R5C9B.F0 SLICE_18 ROUTE 1 0.000 R5C9B.F0 to R5C9B.DI0 N_368_i (to C14M_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path C14M to SLICE_18: Name Fanout Delay (ns) Site Resource ROUTE 89 1.059 62.PADDI to R5C9B.CLK C14M_c -------- 1.059 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to SLICE_18: Name Fanout Delay (ns) Site Resource ROUTE 89 1.059 62.PADDI to R5C9B.CLK C14M_c -------- 1.059 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[13] (from C14M_c +) Destination: FF Data in FS[13] (to C14M_c +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay SLICE_2 to SLICE_2 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path SLICE_2 to SLICE_2: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R2C10D.CLK to R2C10D.Q0 SLICE_2 (from C14M_c) ROUTE 19 0.132 R2C10D.Q0 to R2C10D.A0 FS[13] CTOF_DEL --- 0.101 R2C10D.A0 to R2C10D.F0 SLICE_2 ROUTE 1 0.000 R2C10D.F0 to R2C10D.DI0 FS_s[13] (to C14M_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path C14M to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 89 1.059 62.PADDI to R2C10D.CLK C14M_c -------- 1.059 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 89 1.059 62.PADDI to R2C10D.CLK C14M_c -------- 1.059 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RA[9] (from C14M_c +) Destination: FF Data in RA[9] (to C14M_c +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay SLICE_24 to SLICE_24 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path SLICE_24 to SLICE_24: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C11A.CLK to R5C11A.Q1 SLICE_24 (from C14M_c) ROUTE 2 0.132 R5C11A.Q1 to R5C11A.A1 RA[9] CTOF_DEL --- 0.101 R5C11A.A1 to R5C11A.F1 SLICE_24 ROUTE 1 0.000 R5C11A.F1 to R5C11A.DI1 RA_35[9] (to C14M_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path C14M to SLICE_24: Name Fanout Delay (ns) Site Resource ROUTE 89 1.059 62.PADDI to R5C11A.CLK C14M_c -------- 1.059 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to SLICE_24: Name Fanout Delay (ns) Site Resource ROUTE 89 1.059 62.PADDI to R5C11A.CLK C14M_c -------- 1.059 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RA[11] (from C14M_c +) Destination: FF Data in RA[11] (to C14M_c +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay SLICE_25 to SLICE_25 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path SLICE_25 to SLICE_25: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C10B.CLK to R5C10B.Q1 SLICE_25 (from C14M_c) ROUTE 2 0.132 R5C10B.Q1 to R5C10B.A1 RA[11] CTOF_DEL --- 0.101 R5C10B.A1 to R5C10B.F1 SLICE_25 ROUTE 1 0.000 R5C10B.F1 to R5C10B.DI1 RA_35[11] (to C14M_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path C14M to SLICE_25: Name Fanout Delay (ns) Site Resource ROUTE 89 1.059 62.PADDI to R5C10B.CLK C14M_c -------- 1.059 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to SLICE_25: Name Fanout Delay (ns) Site Resource ROUTE 89 1.059 62.PADDI to R5C10B.CLK C14M_c -------- 1.059 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[12] (from C14M_c +) Destination: FF Data in FS[12] (to C14M_c +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay SLICE_3 to SLICE_3 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path SLICE_3 to SLICE_3: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R2C10C.CLK to R2C10C.Q1 SLICE_3 (from C14M_c) ROUTE 24 0.132 R2C10C.Q1 to R2C10C.A1 FS[12] CTOF_DEL --- 0.101 R2C10C.A1 to R2C10C.F1 SLICE_3 ROUTE 1 0.000 R2C10C.F1 to R2C10C.DI1 FS_s[12] (to C14M_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path C14M to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 89 1.059 62.PADDI to R2C10C.CLK C14M_c -------- 1.059 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 89 1.059 62.PADDI to R2C10C.CLK C14M_c -------- 1.059 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[10] (from C14M_c +) Destination: FF Data in FS[10] (to C14M_c +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay SLICE_4 to SLICE_4 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path SLICE_4 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R2C10B.CLK to R2C10B.Q1 SLICE_4 (from C14M_c) ROUTE 19 0.132 R2C10B.Q1 to R2C10B.A1 FS[10] CTOF_DEL --- 0.101 R2C10B.A1 to R2C10B.F1 SLICE_4 ROUTE 1 0.000 R2C10B.F1 to R2C10B.DI1 FS_s[10] (to C14M_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path C14M to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 89 1.059 62.PADDI to R2C10B.CLK C14M_c -------- 1.059 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 89 1.059 62.PADDI to R2C10B.CLK C14M_c -------- 1.059 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[7] (from C14M_c +) Destination: FF Data in FS[7] (to C14M_c +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay SLICE_5 to SLICE_5 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path SLICE_5 to SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R2C10A.CLK to R2C10A.Q0 SLICE_5 (from C14M_c) ROUTE 4 0.132 R2C10A.Q0 to R2C10A.A0 FS[7] CTOF_DEL --- 0.101 R2C10A.A0 to R2C10A.F0 SLICE_5 ROUTE 1 0.000 R2C10A.F0 to R2C10A.DI0 FS_s[7] (to C14M_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path C14M to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 89 1.059 62.PADDI to R2C10A.CLK C14M_c -------- 1.059 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 89 1.059 62.PADDI to R2C10A.CLK C14M_c -------- 1.059 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[6] (from C14M_c +) Destination: FF Data in FS[6] (to C14M_c +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay SLICE_6 to SLICE_6 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path SLICE_6 to SLICE_6: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R2C9D.CLK to R2C9D.Q1 SLICE_6 (from C14M_c) ROUTE 4 0.132 R2C9D.Q1 to R2C9D.A1 FS[6] CTOF_DEL --- 0.101 R2C9D.A1 to R2C9D.F1 SLICE_6 ROUTE 1 0.000 R2C9D.F1 to R2C9D.DI1 FS_s[6] (to C14M_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path C14M to SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 89 1.059 62.PADDI to R2C9D.CLK C14M_c -------- 1.059 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 89 1.059 62.PADDI to R2C9D.CLK C14M_c -------- 1.059 (0.0% logic, 100.0% route), 0 logic levels. Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY PORT "C14M" 14.300000 MHz ; | -| -| 2 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: C14M_c Source: C14M.PAD Loads: 89 Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ; Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 0 (setup), 0 (hold) Score: 0 (setup), 0 (hold) Cumulative negative slack: 0 (0+0) -------------------------------------------------------------------------------- --------------------------------------------------------------------------------