    PAR: Place And Route Diamond (64-bit) 3.12.1.454.
    Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
    Copyright (c) 1995 AT&T Corp.   All rights reserved.
    Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
    Copyright (c) 2001 Agere Systems   All rights reserved.
    Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
    Sat Nov 18 02:05:57 2023

    C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_1200HC_impl1.p2t
    RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir
    RAM2GS_LCMXO2_1200HC_impl1.prf -gui -msgset
    //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml

    Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf.

    Cost Table Summary
    Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
    Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
    ----------   --------     -----        ------       -----------  -----------  ----         ------
    5_1   *      0            6.215        0            0.304        0            15           Completed
    * : Design saved.

    Total (real) run time for 1-seed: 15 secs

    par done!

    Note: user must run 'Trace' for timing closure signoff.

    Lattice Place and Route Report for Design "RAM2GS_LCMXO2_1200HC_impl1_map.ncd"
    Sat Nov 18 02:05:57 2023

    Best Par Run
    PAR: Place And Route Diamond (64-bit) 3.12.1.454.
    Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
    Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf.
    Placement level-cost: 5-1.
    Routing Iterations: 6

    Loading design for application par from file RAM2GS_LCMXO2_1200HC_impl1_map.ncd.
    Design name: RAM2GS
    NCD version: 3.3
    Vendor:      LATTICE
    Device:      LCMXO2-1200HC
    Package:     TQFP100
    Performance: 4
    Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
    Package Status:                     Final          Version 1.44.
    Performance Hardware Data Status:   Final          Version 34.4.
    License checked out.

    Ignore Preference Error(s):  True

    Device utilization summary:

       PIO (prelim)   64+4(JTAG)/108     63% used
                      64+4(JTAG)/80      85% bonded
       IOLOGIC           26/108          24% used

       SLICE            120/640          18% used

       EFB                1/1           100% used

    Number of Signals: 389
    Number of Connections: 1011

    Pin Constraint Summary:
       64 out of 64 pins locked (100% locked).

    The following 2 signals are selected to use the primary clock routing resources:
        RCLK_c (driver: RCLK, clk load #: 48)
        PHI2_c (driver: PHI2, clk load #: 20)

    WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.

    The following 2 signals are selected to use the secondary clock routing resources:
        nCRAS_c (driver: nCRAS, clk load #: 9, sr load #: 0, ce load #: 0)
        nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0)

    WARNING - par: Signal "nCRAS_c" is selected to use Secondary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
    WARNING - par: Signal "nCCAS_c" is selected to use Secondary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
    No signal is selected as Global Set/Reset.
    Starting Placer Phase 0.
    .........
    Finished Placer Phase 0.  REAL time: 0 secs

    Starting Placer Phase 1.
    ....................
    Placer score = 71673.
    Finished Placer Phase 1.  REAL time: 8 secs

    Starting Placer Phase 2.
    .
    Placer score =  70957
    Finished Placer Phase 2.  REAL time: 8 secs

    Clock Report

    Global Clock Resources:
      CLK_PIN    : 1 out of 8 (12%)
      General PIO: 3 out of 108 (2%)
      PLL        : 0 out of 1 (0%)
      DCM        : 0 out of 2 (0%)
      DCC        : 0 out of 8 (0%)

    Global Clocks:
      PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "63 (PR5C)", clk load = 48
      PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3D)", clk load = 20
      SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL8B)", clk load = 9, ce load = 0, sr load = 0
      SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL4A)", clk load = 8, ce load = 0, sr load = 0

      PRIMARY  : 2 out of 8 (25%)
      SECONDARY: 2 out of 8 (25%)

    Edge Clocks:
      No edge clock selected.

    I/O Usage Summary (final):
       64 + 4(JTAG) out of 108 (63.0%) PIO sites used.
       64 + 4(JTAG) out of 80 (85.0%) bonded PIO sites used.
       Number of PIO comps: 64; differential: 0.
       Number of Vref pins used: 0.

    I/O Bank Usage Summary:
    +----------+----------------+------------+-----------+
    | I/O Bank | Usage          | Bank Vccio | Bank Vref |
    +----------+----------------+------------+-----------+
    | 0        | 13 / 19 ( 68%) | 3.3V       | -         |
    | 1        | 20 / 21 ( 95%) | 3.3V       | -         |
    | 2        | 13 / 20 ( 65%) | 3.3V       | -         |
    | 3        | 18 / 20 ( 90%) | 3.3V       | -         |
    +----------+----------------+------------+-----------+

    Total placer CPU time: 8 secs

    Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd.

    0 connections routed; 1011 unrouted.
    Starting router resource preassignment

    Completed router resource preassignment. Real time: 13 secs

    Start NBR router at 02:06:10 11/18/23

    *****************************************************************
    Info: NBR allows conflicts(one node used by more than one signal)
          in the earlier iterations. In each iteration, it tries to
          solve the conflicts while keeping the critical connections
          routed as short as possible. The routing process is said to
          be completed when no conflicts exist and all connections
          are routed.
    Note: NBR uses a different method to calculate timing slacks. The
          worst slack and total negative slack may not be the same as
          that in TRCE report. You should always run TRCE to verify
          your design.
    *****************************************************************

    Start NBR special constraint process at 02:06:10 11/18/23

    Start NBR section for initial routing at 02:06:11 11/18/23
    Level 1, iteration 1
    0(0.00%) conflict; 814(80.51%) untouched conns; 0 (nbr) score;
    Estimated worst slack/total negative slack<setup>: 5.987ns/0.000ns; real time: 14 secs
    Level 2, iteration 1
    0(0.00%) conflict; 803(79.43%) untouched conns; 0 (nbr) score;
    Estimated worst slack/total negative slack<setup>: 6.236ns/0.000ns; real time: 14 secs
    Level 3, iteration 1
    0(0.00%) conflict; 803(79.43%) untouched conns; 0 (nbr) score;
    Estimated worst slack/total negative slack<setup>: 5.836ns/0.000ns; real time: 14 secs
    Level 4, iteration 1
    16(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
    Estimated worst slack/total negative slack<setup>: 6.236ns/0.000ns; real time: 14 secs

    Info: Initial congestion level at 75% usage is 0
    Info: Initial congestion area  at 75% usage is 0 (0.00%)

    Start NBR section for normal routing at 02:06:11 11/18/23
    Level 4, iteration 1
    3(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
    Estimated worst slack/total negative slack<setup>: 6.222ns/0.000ns; real time: 14 secs
    Level 4, iteration 2
    0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
    Estimated worst slack/total negative slack<setup>: 6.215ns/0.000ns; real time: 14 secs

    Start NBR section for setup/hold timing optimization with effort level 3 at 02:06:11 11/18/23

    Start NBR section for re-routing at 02:06:11 11/18/23
    Level 4, iteration 1
    0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
    Estimated worst slack/total negative slack<setup>: 6.215ns/0.000ns; real time: 14 secs

    Start NBR section for post-routing at 02:06:11 11/18/23

    End NBR router with 0 unrouted connection

    NBR Summary
    -----------
      Number of unrouted connections : 0 (0.00%)
      Number of connections with timing violations : 0 (0.00%)
      Estimated worst slack<setup> : 6.215ns
      Timing score<setup> : 0
    -----------
    Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.

    Total CPU time 14 secs
    Total REAL time: 15 secs
    Completely routed.
    End of route.  1011 routed (100.00%); 0 unrouted.

    Hold time timing score: 0, hold timing errors: 0

    Timing score: 0

    Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd.

    All signals are completely routed.

    PAR_SUMMARY::Run status = Completed
    PAR_SUMMARY::Number of unrouted conns = 0
    PAR_SUMMARY::Worst  slack<setup/<ns>> = 6.215
    PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
    PAR_SUMMARY::Worst  slack<hold /<ns>> = 0.304
    PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
    PAR_SUMMARY::Number of errors = 0

    Total CPU  time to completion: 15 secs
    Total REAL time to completion: 15 secs

    par done!

    Note: user must run 'Trace' for timing closure signoff.

    Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
    Copyright (c) 1995 AT&T Corp.   All rights reserved.
    Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
    Copyright (c) 2001 Agere Systems   All rights reserved.
    Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.