    Synthesis Report
    #Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
    #install: C:\lscc\diamond\3.12\synpbase
    #OS: Windows 8 6.2
    #Hostname: ZANEMACWIN11

    # Sat Jan  6 06:25:00 2024

    #Implementation: impl1

    Copyright (C) 1994-2021 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: R-2021.03L-SP1
    Install: C:\lscc\diamond\3.12\synpbase
    OS: Windows 6.2

    Hostname: ZANEMACWIN11

    Implementation : impl1
    Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @

    @N|Running in 64-bit mode
    ###########################################################[

    Copyright (C) 1994-2021 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: R-2021.03L-SP1
    Install: C:\lscc\diamond\3.12\synpbase
    OS: Windows 6.2

    Hostname: ZANEMACWIN11

    Implementation : impl1
    Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @

    @N|Running in 64-bit mode
    @I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v" (library work)
    @I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
    @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
    @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
    @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
    @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
    @I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-SPI.v" (library work)
    Verilog syntax check successful!

    Compiler output is up to date.  No re-compile necessary

    Selecting top level module RAM2GS
    @N: CG364 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work.
    Running optimization stage 1 on RAM2GS .......
    Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 100MB)
    Running optimization stage 2 on RAM2GS .......
    Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB)

    At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 96MB peak: 97MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Sat Jan  6 06:25:00 2024

    ###########################################################]
    ###########################################################[

    Copyright (C) 1994-2021 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: R-2021.03L-SP1
    Install: C:\lscc\diamond\3.12\synpbase
    OS: Windows 6.2

    Hostname: ZANEMACWIN11

    Implementation : impl1
    Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @

    @N|Running in 64-bit mode

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Sat Jan  6 06:25:00 2024

    ###########################################################]

    For a summary of runtime and memory usage for all design units, please see file:
    ==========================================================
    @L: A:\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_comp.rt.csv

    @END

    At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Sat Jan  6 06:25:00 2024

    ###########################################################]
    ###########################################################[

    Copyright (C) 1994-2021 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: R-2021.03L-SP1
    Install: C:\lscc\diamond\3.12\synpbase
    OS: Windows 6.2

    Hostname: ZANEMACWIN11

    Implementation : impl1
    Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @

    @N|Running in 64-bit mode
    File \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_comp.srs changed - recompiling

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Sat Jan  6 06:25:01 2024

    ###########################################################]
    # Sat Jan  6 06:25:02 2024

    Copyright (C) 1994-2021 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: R-2021.03L-SP1
    Install: C:\lscc\diamond\3.12\synpbase
    OS: Windows 6.2

    Hostname: ZANEMACWIN11

    Implementation : impl1
    Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)

    Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 140MB)

    Reading constraint file: \\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc
    @L: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1_scck.rpt
    See clock summary report "\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1_scck.rpt"
    @N: MF916 |Option synthesis_strategy=base is enabled.
    @N: MF248 |Running in 64-bit mode.
    @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 151MB)

    @N: FX493 |Applying initial value "0" on instance InitReady.
    @W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
    @N: FX493 |Applying initial value "0" on instance Ready.
    @N: FX493 |Applying initial value "0" on instance RCKE.
    @N: FX493 |Applying initial value "1" on instance nRCAS.
    @N: FX493 |Applying initial value "0" on instance CmdLEDEN.
    @N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN.
    @N: FX493 |Applying initial value "1" on instance nRCS.
    @N: FX493 |Applying initial value "0" on instance n8MEGEN.
    @N: FX493 |Applying initial value "1" on instance nRRAS.
    @N: FX493 |Applying initial value "0" on instance CmdUFMCLK.
    @N: FX493 |Applying initial value "0" on instance CmdUFMCS.
    @N: FX493 |Applying initial value "0" on instance CmdUFMSDI.
    @N: FX493 |Applying initial value "0" on instance C1Submitted.
    @N: FX493 |Applying initial value "0" on instance CmdSubmitted.
    @N: FX493 |Applying initial value "0" on instance ADSubmitted.
    @N: FX493 |Applying initial value "0" on instance XOR8MEG.
    @N: FX493 |Applying initial value "1" on instance nUFMCS.
    @N: FX493 |Applying initial value "0" on instance UFMSDI.
    @N: FX493 |Applying initial value "0" on instance UFMCLK.
    @N: FX493 |Applying initial value "0" on instance CmdEnable.
    @N: FX493 |Applying initial value "1" on instance nRWE.

    Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)

    Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)

    Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)

    Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)

    @N: FX1184 |Applying syn_allowed_resources blockrams=0 on top level netlist RAM2GS

    Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)

    Clock Summary
    ******************

              Start     Requested     Requested     Clock        Clock                Clock
    Level     Clock     Frequency     Period        Type         Group                Load
    ---------------------------------------------------------------------------------------
    0 -       RCLK      62.5 MHz      16.000        declared     default_clkgroup     48

    0 -       PHI2      2.9 MHz       350.000       declared     default_clkgroup     19

    0 -       nCRAS     2.9 MHz       350.000       declared     default_clkgroup     14

    0 -       nCCAS     2.9 MHz       350.000       declared     default_clkgroup     8
    =======================================================================================

    Clock Load Summary
    ***********************

              Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin
    Clock     Load      Pin             Seq Example     Seq Example       Comb Example
    ----------------------------------------------------------------------------------------
    RCLK      48        RCLK(port)      CASr2.C         -                 -

    PHI2      19        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)

    nCRAS     14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)

    nCCAS     8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)
    ========================================================================================

    ICG Latch Removal Summary:
    Number of ICG latches removed: 0
    Number of ICG latches not removed:	0
    For details review file gcc_ICG_report.rpt

    @S |Clock Optimization Summary

    #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

    4 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s)
    0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    0 instances converted, 0 sequential instances remain driven by gated/generated clocks

    =========================== Non-Gated/Non-Generated Clocks ============================
    Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
    ---------------------------------------------------------------------------------------
    @KP:ckid0_0       RCLK                port                   48         nRWE
    @KP:ckid0_1       PHI2                port                   19         RA11
    @KP:ckid0_2       nCCAS               port                   8          WRD[7:0]
    @KP:ckid0_3       nCRAS               port                   14         RowA[9:0]
    =======================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######

    @N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
    Finished Pre Mapping Phase.

    Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)

    Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)

    Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)

    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 184MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Sat Jan  6 06:25:03 2024

    ###########################################################]
    # Sat Jan  6 06:25:03 2024

    Copyright (C) 1994-2021 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: R-2021.03L-SP1
    Install: C:\lscc\diamond\3.12\synpbase
    OS: Windows 6.2

    Hostname: ZANEMACWIN11

    Implementation : impl1
    Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)

    @N: MF916 |Option synthesis_strategy=base is enabled.
    @N: MF248 |Running in 64-bit mode.
    @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 178MB peak: 178MB)

    Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)

    @N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":147:4:147:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0]
    @N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":134:4:134:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0]
    @N: FX493 |Applying initial value "0" on instance IS[0].
    @W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
    @N: FX493 |Applying initial value "0" on instance IS[1].
    @N: FX493 |Applying initial value "0" on instance IS[2].
    @N: FX493 |Applying initial value "0" on instance IS[3].

    Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 184MB peak: 184MB)

    Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 185MB peak: 185MB)

    Available hyper_sources - for debug and ip models
    	None Found

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 187MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)

    Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)

    Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:01s		    -4.01ns		 133 /        89
       2		0h:00m:01s		    -3.96ns		 131 /        89
    @N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 8 loads 1 time to improve timing.
    @N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 7 loads 1 time to improve timing.
    @N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":147:4:147:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 19 loads 1 time to improve timing.
    Timing driven replication report
    Added 3 Registers via timing driven replication
    Added 1 LUTs via timing driven replication

       3		0h:00m:02s		    -3.08ns		 143 /        92
       4		0h:00m:02s		    -3.08ns		 141 /        92

       5		0h:00m:02s		    -3.08ns		 140 /        92
       6		0h:00m:02s		    -3.19ns		 140 /        92
       7		0h:00m:02s		    -3.19ns		 140 /        92
       8		0h:00m:02s		    -3.19ns		 140 /        92
       9		0h:00m:02s		    -3.19ns		 140 /        92

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 191MB)

    Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 191MB)

    Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 155MB peak: 192MB)

    Writing Analyst data base \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_m.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 192MB peak: 192MB)

    Writing EDIF Netlist and constraint files
    @N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.edi
    @N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF

    Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 197MB peak: 197MB)

    Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 197MB peak: 197MB)

    Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 195MB peak: 197MB)

    @N: MT615 |Found clock RCLK with period 16.00ns
    @N: MT615 |Found clock PHI2 with period 350.00ns
    @N: MT615 |Found clock nCRAS with period 350.00ns
    @N: MT615 |Found clock nCCAS with period 350.00ns

    ##### START OF TIMING REPORT #####[
    # Timing report written on Sat Jan  6 06:25:08 2024
    #

    Top view:               RAM2GS
    Requested Frequency:    2.9 MHz
    Wire load mode:         top
    Paths requested:        3
    Constraint File(s):    \\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc

    @N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

    @N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.

    Performance Summary
    *******************

    Worst slack in design: -3.705

                       Requested     Estimated     Requested     Estimated                Clock        Clock
    Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group
    -------------------------------------------------------------------------------------------------------------------
    PHI2               2.9 MHz       0.6 MHz       350.000       1646.750      -3.705     declared     default_clkgroup
    RCLK               62.5 MHz      13.3 MHz      16.000        75.280        -2.312     declared     default_clkgroup
    nCCAS              2.9 MHz       NA            350.000       NA            NA         declared     default_clkgroup
    nCRAS              2.9 MHz       0.6 MHz       350.000       1613.150      -3.609     declared     default_clkgroup
    ===================================================================================================================
    Estimated period and frequency reported as NA means no slack depends directly on the clock waveform

    @W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.
    @W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.
    @W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.
    @W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.
    @W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.

    Clock Relationships
    *******************

    Clocks            |    rise  to  rise    |    fall  to  fall     |    rise  to  fall     |    fall  to  rise
    ---------------------------------------------------------------------------------------------------------------
    Starting  Ending  |  constraint  slack   |  constraint  slack    |  constraint  slack    |  constraint  slack
    ---------------------------------------------------------------------------------------------------------------
    RCLK      RCLK    |  16.000      7.464   |  No paths    -        |  No paths    -        |  No paths    -
    RCLK      PHI2    |  2.000       -1.216  |  No paths    -        |  1.000       -2.312   |  No paths    -
    PHI2      RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -3.705
    PHI2      PHI2    |  No paths    -       |  350.000     344.094  |  175.000     165.215  |  175.000     171.784
    nCRAS     RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -3.609
    ===============================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: PHI2
    ====================================

    Starting Points with Worst Slack
    ********************************

                     Starting                                           Arrival
    Instance         Reference     Type        Pin     Net              Time        Slack
                     Clock
    ---------------------------------------------------------------------------------------
    CmdSubmitted     PHI2          FD1S3AX     Q       CmdSubmitted     1.552       -3.705
    CmdUFMCLK        PHI2          FD1P3AX     Q       CmdUFMCLK        1.348       -3.297
    CmdUFMCS         PHI2          FD1P3AX     Q       CmdUFMCS         1.348       -3.297
    CmdUFMSDI        PHI2          FD1P3AX     Q       CmdUFMSDI        1.348       -3.297
    CmdLEDEN         PHI2          FD1P3AX     Q       CmdLEDEN         1.456       -2.216
    Cmdn8MEGEN       PHI2          FD1P3AX     Q       Cmdn8MEGEN       1.456       -2.216
    Bank[0]          PHI2          FD1S3AX     Q       Bank[0]          1.348       165.215
    Bank[1]          PHI2          FD1S3AX     Q       Bank[1]          1.348       165.215
    Bank[2]          PHI2          FD1S3AX     Q       Bank[2]          1.348       165.215
    Bank[3]          PHI2          FD1S3AX     Q       Bank[3]          1.348       165.215
    =======================================================================================

    Ending Points with Worst Slack
    ******************************

                     Starting                                               Required
    Instance         Reference     Type        Pin     Net                  Time         Slack
                     Clock
    --------------------------------------------------------------------------------------------
    UFMCLK           PHI2          FD1S3AX     D       UFMCLK_RNO           -0.003       -3.705
    UFMSDI           PHI2          FD1S3AX     D       UFMSDI_RNO           -0.003       -3.705
    nUFMCS           PHI2          FD1S3AY     D       nUFMCS_s_0_N_5_i     -0.003       -3.705
    LEDEN            PHI2          FD1P3AX     SP      N_26                 0.806        -2.800
    n8MEGEN          PHI2          FD1P3AX     SP      N_24                 0.806        -2.800
    LEDEN            PHI2          FD1P3AX     D       N_49                 -0.003       -2.216
    n8MEGEN          PHI2          FD1P3AX     D       N_48                 -0.003       -2.216
    CmdEnable        PHI2          FD1S3AX     D       CmdEnable_s          173.997      165.215
    CmdSubmitted     PHI2          FD1S3AX     D       N_428_0              173.997      165.311
    ADSubmitted      PHI2          FD1S3AX     D       ADSubmitted_r        173.997      166.404
    ============================================================================================

    Worst Path Information
    ***********************

    Path information for path number 1:
          Requested Period:                      1.000
        - Setup time:                            1.003
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         -0.003

        - Propagation time:                      3.702
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -3.705

        Number of logic level(s):                2
        Starting point:                          CmdSubmitted / Q
        Ending point:                            UFMCLK / D
        The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
        The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK

    Instance / Net                   Pin      Pin               Arrival     No. of
    Name                Type         Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------
    CmdSubmitted        FD1S3AX      Q        Out     1.552     1.552 r     -
    CmdSubmitted        Net          -        -       -         -           3
    PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.552 r     -
    PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.393     2.945 r     -
    N_137_i             Net          -        -       -         -           3
    UFMCLK_RNO          ORCALUT4     A        In      0.000     2.945 r     -
    UFMCLK_RNO          ORCALUT4     Z        Out     0.757     3.702 r     -
    UFMCLK_RNO          Net          -        -       -         -           1
    UFMCLK              FD1S3AX      D        In      0.000     3.702 r     -
    ==================================================================================

    Path information for path number 2:
          Requested Period:                      1.000
        - Setup time:                            1.003
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         -0.003

        - Propagation time:                      3.702
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -3.705

        Number of logic level(s):                2
        Starting point:                          CmdSubmitted / Q
        Ending point:                            nUFMCS / D
        The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
        The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK

    Instance / Net                    Pin      Pin               Arrival     No. of
    Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------
    CmdSubmitted         FD1S3AX      Q        Out     1.552     1.552 r     -
    CmdSubmitted         Net          -        -       -         -           3
    PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.552 r     -
    PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.393     2.945 r     -
    N_137_i              Net          -        -       -         -           3
    nUFMCS_s_0_N_5_i     ORCALUT4     A        In      0.000     2.945 r     -
    nUFMCS_s_0_N_5_i     ORCALUT4     Z        Out     0.757     3.702 r     -
    nUFMCS_s_0_N_5_i     Net          -        -       -         -           1
    nUFMCS               FD1S3AY      D        In      0.000     3.702 r     -
    ===================================================================================

    Path information for path number 3:
          Requested Period:                      1.000
        - Setup time:                            1.003
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         -0.003

        - Propagation time:                      3.702
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -3.705

        Number of logic level(s):                2
        Starting point:                          CmdSubmitted / Q
        Ending point:                            UFMSDI / D
        The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
        The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK

    Instance / Net                   Pin      Pin               Arrival     No. of
    Name                Type         Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------
    CmdSubmitted        FD1S3AX      Q        Out     1.552     1.552 r     -
    CmdSubmitted        Net          -        -       -         -           3
    PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.552 r     -
    PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.393     2.945 r     -
    N_137_i             Net          -        -       -         -           3
    UFMSDI_RNO          ORCALUT4     A        In      0.000     2.945 r     -
    UFMSDI_RNO          ORCALUT4     Z        Out     0.757     3.702 r     -
    UFMSDI_RNO          Net          -        -       -         -           1
    UFMSDI              FD1S3AX      D        In      0.000     3.702 r     -
    ==================================================================================

    ====================================
    Detailed Report for Clock: RCLK
    ====================================

    Starting Points with Worst Slack
    ********************************

                  Starting                                        Arrival
    Instance      Reference     Type        Pin     Net           Time        Slack
                  Clock
    --------------------------------------------------------------------------------
    LEDEN         RCLK          FD1P3AX     Q       LEDEN         1.552       -2.312
    n8MEGEN       RCLK          FD1P3AX     Q       n8MEGEN       1.456       -2.216
    FS[12]        RCLK          FD1S3AX     Q       FS[12]        1.552       7.464
    FS[14]        RCLK          FD1S3AX     Q       FS[14]        1.552       7.464
    FS[15]        RCLK          FD1S3AX     Q       FS[15]        1.552       7.464
    FS[17]        RCLK          FD1S3AX     Q       FS[17]        1.552       7.464
    InitReady     RCLK          FD1S3AX     Q       InitReady     1.792       8.569
    S[1]          RCLK          FD1S3IX     Q       S[1]          1.792       8.569
    S[0]          RCLK          FD1S3IX     Q       CO0           1.780       8.581
    FS[13]        RCLK          FD1S3AX     Q       FS[13]        1.612       8.593
    ================================================================================

    Ending Points with Worst Slack
    ******************************

                   Starting                                               Required
    Instance       Reference     Type        Pin     Net                  Time         Slack
                   Clock
    -----------------------------------------------------------------------------------------
    CmdLEDEN       RCLK          FD1P3AX     D       N_14_i               -0.003       -2.312
    XOR8MEG        RCLK          FD1P3AX     D       XOR8MEG_3            -0.003       -2.312
    Cmdn8MEGEN     RCLK          FD1P3AX     D       N_12_i               -0.003       -2.216
    RA11           RCLK          FD1S3IX     D       RA11_2               0.997        -1.216
    UFMSDI         RCLK          FD1S3AX     D       UFMSDI_RNO           14.997       7.464
    UFMCLK         RCLK          FD1S3AX     D       UFMCLK_RNO           14.997       7.668
    nRCAS          RCLK          FD1S3AY     D       N_46_i               14.997       8.569
    nUFMCS         RCLK          FD1S3AY     D       nUFMCS_s_0_N_5_i     14.997       8.653
    nRCS           RCLK          FD1S3AY     D       N_143_i              14.997       8.881
    LEDEN          RCLK          FD1P3AX     SP      N_26                 15.806       9.463
    =========================================================================================

    Worst Path Information
    ***********************

    Path information for path number 1:
          Requested Period:                      1.000
        - Setup time:                            1.003
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         -0.003

        - Propagation time:                      2.309
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -2.312

        Number of logic level(s):                1
        Starting point:                          LEDEN / Q
        Ending point:                            CmdLEDEN / D
        The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
        The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK

    Instance / Net                  Pin      Pin               Arrival     No. of
    Name               Type         Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------
    LEDEN              FD1P3AX      Q        Out     1.552     1.552 r     -
    LEDEN              Net          -        -       -         -           3
    CmdLEDEN_RNO       ORCALUT4     B        In      0.000     1.552 r     -
    CmdLEDEN_RNO       ORCALUT4     Z        Out     0.757     2.309 r     -
    N_14_i             Net          -        -       -         -           1
    CmdLEDEN           FD1P3AX      D        In      0.000     2.309 r     -
    =================================================================================

    Path information for path number 2:
          Requested Period:                      1.000
        - Setup time:                            1.003
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         -0.003

        - Propagation time:                      2.309
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -2.312

        Number of logic level(s):                1
        Starting point:                          LEDEN / Q
        Ending point:                            XOR8MEG / D
        The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
        The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK

    Instance / Net                        Pin      Pin               Arrival     No. of
    Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------
    LEDEN                    FD1P3AX      Q        Out     1.552     1.552 r     -
    LEDEN                    Net          -        -       -         -           3
    XOR8MEG_3_u_0_a3_0_2     ORCALUT4     B        In      0.000     1.552 r     -
    XOR8MEG_3_u_0_a3_0_2     ORCALUT4     Z        Out     0.757     2.309 f     -
    XOR8MEG_3                Net          -        -       -         -           1
    XOR8MEG                  FD1P3AX      D        In      0.000     2.309 f     -
    =======================================================================================

    Path information for path number 3:
          Requested Period:                      1.000
        - Setup time:                            1.003
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         -0.003

        - Propagation time:                      2.213
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -2.216

        Number of logic level(s):                1
        Starting point:                          n8MEGEN / Q
        Ending point:                            Cmdn8MEGEN / D
        The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
        The end   point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK

    Instance / Net                  Pin      Pin               Arrival     No. of
    Name               Type         Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------
    n8MEGEN            FD1P3AX      Q        Out     1.456     1.456 r     -
    n8MEGEN            Net          -        -       -         -           2
    Cmdn8MEGEN_RNO     ORCALUT4     C        In      0.000     1.456 r     -
    Cmdn8MEGEN_RNO     ORCALUT4     Z        Out     0.757     2.213 r     -
    N_12_i             Net          -        -       -         -           1
    Cmdn8MEGEN         FD1P3AX      D        In      0.000     2.213 r     -
    =================================================================================

    ====================================
    Detailed Report for Clock: nCRAS
    ====================================

    Starting Points with Worst Slack
    ********************************

                  Starting                                        Arrival
    Instance      Reference     Type        Pin     Net           Time        Slack
                  Clock
    --------------------------------------------------------------------------------
    CBR_fast      nCRAS         FD1S3AX     Q       CBR_fast      1.552       -3.609
    CBR           nCRAS         FD1S3AX     Q       CBR           1.612       -3.561
    FWEr          nCRAS         FD1S3AX     Q       FWEr          1.552       -3.501
    FWEr_fast     nCRAS         FD1S3AX     Q       FWEr_fast     1.552       -3.501
    ================================================================================

    Ending Points with Worst Slack
    ******************************

                   Starting                                             Required
    Instance       Reference     Type        Pin     Net                Time         Slack
                   Clock
    ---------------------------------------------------------------------------------------
    nRCAS          nCRAS         FD1S3AY     D       N_46_i             -0.003       -3.609
    nRWE           nCRAS         FD1S3AY     D       N_144_i            -0.003       -3.609
    nRowColSel     nCRAS         FD1S3IX     D       nRowColSel_0_0     -0.003       -3.561
    RCKEEN         nCRAS         FD1S3AX     D       RCKEEN_8           -0.003       -3.501
    nRCS           nCRAS         FD1S3AY     D       N_143_i            -0.003       -3.501
    =======================================================================================

    Worst Path Information
    ***********************

    Path information for path number 1:
          Requested Period:                      1.000
        - Setup time:                            1.003
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         -0.003

        - Propagation time:                      3.606
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -3.609

        Number of logic level(s):                2
        Starting point:                          CBR_fast / Q
        Ending point:                            nRCAS / D
        The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
        The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK

    Instance / Net                         Pin      Pin               Arrival     No. of
    Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------
    CBR_fast                  FD1S3AX      Q        Out     1.552     1.552 r     -
    CBR_fast                  Net          -        -       -         -           3
    nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.552 r     -
    nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.297     2.849 r     -
    nRCAS_0_sqmuxa_1          Net          -        -       -         -           2
    nRCAS_RNO                 ORCALUT4     C        In      0.000     2.849 r     -
    nRCAS_RNO                 ORCALUT4     Z        Out     0.757     3.606 f     -
    N_46_i                    Net          -        -       -         -           1
    nRCAS                     FD1S3AY      D        In      0.000     3.606 f     -
    ========================================================================================

    Path information for path number 2:
          Requested Period:                      1.000
        - Setup time:                            1.003
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         -0.003

        - Propagation time:                      3.606
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -3.609

        Number of logic level(s):                2
        Starting point:                          CBR_fast / Q
        Ending point:                            nRWE / D
        The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
        The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK

    Instance / Net                         Pin      Pin               Arrival     No. of
    Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------
    CBR_fast                  FD1S3AX      Q        Out     1.552     1.552 r     -
    CBR_fast                  Net          -        -       -         -           3
    nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.552 r     -
    nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.297     2.849 r     -
    nRCAS_0_sqmuxa_1          Net          -        -       -         -           2
    nRWE_RNO                  ORCALUT4     C        In      0.000     2.849 r     -
    nRWE_RNO                  ORCALUT4     Z        Out     0.757     3.606 r     -
    N_144_i                   Net          -        -       -         -           1
    nRWE                      FD1S3AY      D        In      0.000     3.606 r     -
    ========================================================================================

    Path information for path number 3:
          Requested Period:                      1.000
        - Setup time:                            1.003
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         -0.003

        - Propagation time:                      3.558
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -3.561

        Number of logic level(s):                2
        Starting point:                          CBR / Q
        Ending point:                            nRCAS / D
        The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
        The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK

    Instance / Net                  Pin      Pin               Arrival     No. of
    Name               Type         Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------
    CBR                FD1S3AX      Q        Out     1.612     1.612 r     -
    CBR                Net          -        -       -         -           4
    nRCAS_RNO_1        ORCALUT4     A        In      0.000     1.612 r     -
    nRCAS_RNO_1        ORCALUT4     Z        Out     1.189     2.801 f     -
    G_1_1              Net          -        -       -         -           1
    nRCAS_RNO          ORCALUT4     B        In      0.000     2.801 f     -
    nRCAS_RNO          ORCALUT4     Z        Out     0.757     3.558 r     -
    N_46_i             Net          -        -       -         -           1
    nRCAS              FD1S3AY      D        In      0.000     3.558 r     -
    =================================================================================

    ##### END OF TIMING REPORT #####]

    Timing exceptions that could not be applied

    Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 196MB peak: 197MB)

    Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 196MB peak: 197MB)

    ---------------------------------------
    Resource Usage Report
    Part: lcmxo640c-3

    Register bits: 92 of 640 (14%)
    PIC Latch:       0
    I/O cells:       67

    Details:
    BB:             8
    CCU2:           9
    FD1P3AX:        11
    FD1S3AX:        59
    FD1S3AY:        5
    FD1S3IX:        14
    FD1S3JX:        3
    GSR:            1
    IB:             26
    INV:            7
    OB:             33
    ORCALUT4:       133
    PFUMX:          1
    PUR:            1
    VHI:            1
    VLO:            1
    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 78MB peak: 197MB)

    Process took 0h:00m:04s realtime, 0h:00m:04s cputime
    # Sat Jan  6 06:25:08 2024

    ###########################################################]