    Map TRACE Report

    Loading design for application trce from file ram2gs_lcmxo256c_impl1_map.ncd.
    Design name: RAM2GS
    NCD version: 3.3
    Vendor:      LATTICE
    Device:      LCMXO256C
    Package:     TQFP100
    Performance: 3
    Loading device for application trce from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
    Package Status:                     Final          Version 1.19.
    Performance Hardware Data Status: Version 1.124.
    Setup and Hold Report

    --------------------------------------------------------------------------------
    Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
    Sat Jan 06 06:24:59 2024

    Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
    Copyright (c) 1995 AT&T Corp.   All rights reserved.
    Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
    Copyright (c) 2001 Agere Systems   All rights reserved.
    Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

    Report Information
    ------------------
    Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf
    Design file:     ram2gs_lcmxo256c_impl1_map.ncd
    Preference file: ram2gs_lcmxo256c_impl1.prf
    Device,speed:    LCMXO256C,3
    Report level:    verbose report, limited to 1 item per preference
    --------------------------------------------------------------------------------

    Preference Summary

    FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)            168 items scored, 0 timing errors detected.
    Report:   43.077MHz is the maximum frequency for this preference.

    FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)            0 items scored, 0 timing errors detected.
    Report:  400.000MHz is the maximum frequency for this preference.

    FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)            0 items scored, 0 timing errors detected.
    Report:  400.000MHz is the maximum frequency for this preference.

    FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)            392 items scored, 0 timing errors detected.
    Report:  102.020MHz is the maximum frequency for this preference.

    BLOCK ASYNCPATHS
    BLOCK RESETPATHS
    --------------------------------------------------------------------------------

    ================================================================================
    Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
                168 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

    Passed: The following path meets requirements by 160.807ns (weighted slack = 321.614ns)

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              Bank[6]  (from PHI2_c +)
       Destination:    FF         Data in        CmdEnable  (to PHI2_c -)

       Delay:              11.433ns  (24.4% logic, 75.6% route), 7 logic levels.

     Constraint Details:

         11.433ns physical path delay SLICE_75 to SLICE_20 meets
        172.414ns delay constraint less
          0.174ns DIN_SET requirement (totaling 172.240ns) by 160.807ns

     Physical Path Details:

          Data path SLICE_75 to SLICE_20:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.560   SLICE_75.CLK to    SLICE_75.Q0 SLICE_75 (from PHI2_c)
    ROUTE         1   e 1.441    SLICE_75.Q0 to    SLICE_77.C1 Bank[6]
    CTOF_DEL    ---     0.371    SLICE_77.C1 to    SLICE_77.F1 SLICE_77
    ROUTE         2   e 1.441    SLICE_77.F1 to    SLICE_79.D0 un1_Bank_1_5
    CTOF_DEL    ---     0.371    SLICE_79.D0 to    SLICE_79.F0 SLICE_79
    ROUTE         2   e 1.441    SLICE_79.F0 to    SLICE_76.B0 C1WR_7
    CTOF_DEL    ---     0.371    SLICE_76.B0 to    SLICE_76.F0 SLICE_76
    ROUTE         5   e 1.441    SLICE_76.F0 to    SLICE_70.B0 C1WR
    CTOF_DEL    ---     0.371    SLICE_70.B0 to    SLICE_70.F0 SLICE_70
    ROUTE         1   e 1.441    SLICE_70.F0 to    SLICE_14.C1 N_121
    CTOF_DEL    ---     0.371    SLICE_14.C1 to    SLICE_14.F1 SLICE_14
    ROUTE         1   e 1.441    SLICE_14.F1 to    SLICE_20.C0 un1_CmdEnable20_i
    CTOF_DEL    ---     0.371    SLICE_20.C0 to    SLICE_20.F0 SLICE_20
    ROUTE         1   e 0.001    SLICE_20.F0 to   SLICE_20.DI0 CmdEnable_s (to PHI2_c)
                      --------
                       11.433   (24.4% logic, 75.6% route), 7 logic levels.

    Report:   43.077MHz is the maximum frequency for this preference.

    ================================================================================
    Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
                0 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

    Passed:  The following path meets requirements by 342.328ns
             The internal maximum frequency of the following component is 400.000 MHz

     Logical Details:  Cell type  Pin name       Component name

       Destination:    PIO        PAD            nCCAS

       Delay:               2.500ns -- based on Minimum Pulse Width

    Report:  400.000MHz is the maximum frequency for this preference.

    ================================================================================
    Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
                0 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

    Passed:  The following path meets requirements by 342.328ns
             The internal maximum frequency of the following component is 400.000 MHz

     Logical Details:  Cell type  Pin name       Component name

       Destination:    PIO        PAD            nCRAS

       Delay:               2.500ns -- based on Minimum Pulse Width

    Report:  400.000MHz is the maximum frequency for this preference.

    ================================================================================
    Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
                392 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

    Passed: The following path meets requirements by 6.198ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              FS[17]  (from RCLK_c +)
       Destination:    FF         Data in        UFMSDI  (to RCLK_c +)

       Delay:               9.621ns  (25.1% logic, 74.9% route), 6 logic levels.

     Constraint Details:

          9.621ns physical path delay SLICE_1 to SLICE_52 meets
         16.000ns delay constraint less
          0.181ns DIN_SET requirement (totaling 15.819ns) by 6.198ns

     Physical Path Details:

          Data path SLICE_1 to SLICE_52:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.560    SLICE_1.CLK to     SLICE_1.Q1 SLICE_1 (from RCLK_c)
    ROUTE         3   e 1.441     SLICE_1.Q1 to    SLICE_86.D1 FS[17]
    CTOF_DEL    ---     0.371    SLICE_86.D1 to    SLICE_86.F1 SLICE_86
    ROUTE         1   e 1.441    SLICE_86.F1 to    SLICE_69.C1 UFMSDI_ens2_i_o2_0_3
    CTOF_DEL    ---     0.371    SLICE_69.C1 to    SLICE_69.F1 SLICE_69
    ROUTE         4   e 1.441    SLICE_69.F1 to    SLICE_58.C1 N_128
    CTOF_DEL    ---     0.371    SLICE_58.C1 to    SLICE_58.F1 SLICE_58
    ROUTE         3   e 1.441    SLICE_58.F1 to    SLICE_55.C0 N_94
    CTOF_DEL    ---     0.371    SLICE_55.C0 to    SLICE_55.F0 SLICE_55
    ROUTE         1   e 1.441    SLICE_55.F0 to    SLICE_52.D0 UFMSDI_r_xx_mm_1
    CTOF_DEL    ---     0.371    SLICE_52.D0 to    SLICE_52.F0 SLICE_52
    ROUTE         1   e 0.001    SLICE_52.F0 to   SLICE_52.DI0 UFMSDI_RNO (to RCLK_c)
                      --------
                        9.621   (25.1% logic, 74.9% route), 6 logic levels.

    Report:  102.020MHz is the maximum frequency for this preference.

    Report Summary
    --------------
    ----------------------------------------------------------------------------
    Preference                              |   Constraint|       Actual|Levels
    ----------------------------------------------------------------------------
                                            |             |             |
    FREQUENCY PORT "PHI2" 2.900000 MHz ;    |    2.900 MHz|   43.077 MHz|   7
                                            |             |             |
    FREQUENCY PORT "nCCAS" 2.900000 MHz ;   |    2.900 MHz|  400.000 MHz|   0
                                            |             |             |
    FREQUENCY PORT "nCRAS" 2.900000 MHz ;   |    2.900 MHz|  400.000 MHz|   0
                                            |             |             |
    FREQUENCY PORT "RCLK" 62.500000 MHz ;   |   62.500 MHz|  102.020 MHz|   6
                                            |             |             |
    ----------------------------------------------------------------------------

    All preferences were met.

    Clock Domains Analysis
    ------------------------

    Found 4 clocks:

    Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 10
       No transfer within this clock domain is found

       Data transfers from:
       Clock Domain: RCLK_c   Source: RCLK.PAD
          Not reported because source and destination domains are unrelated.
          To report these transfers please refer to preference CLKSKEWDIFF to define
          external clock skew between clock ports.

    Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 8
       No transfer within this clock domain is found

    Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 32
       Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;

       Data transfers from:
       Clock Domain: nCRAS_c   Source: nCRAS.PAD
          Not reported because source and destination domains are unrelated.
          To report these transfers please refer to preference CLKSKEWDIFF to define
          external clock skew between clock ports.

       Clock Domain: PHI2_c   Source: PHI2.PAD
          Not reported because source and destination domains are unrelated.
          To report these transfers please refer to preference CLKSKEWDIFF to define
          external clock skew between clock ports.

    Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 15
       Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;

       Data transfers from:
       Clock Domain: RCLK_c   Source: RCLK.PAD
          Not reported because source and destination domains are unrelated.
          To report these transfers please refer to preference CLKSKEWDIFF to define
          external clock skew between clock ports.

    Timing summary (Setup):
    ---------------

    Timing errors: 0  Score: 0
    Cumulative negative slack: 0

    Constraints cover 560 paths, 4 nets, and 424 connections (62.26% coverage)

    --------------------------------------------------------------------------------
    Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
    Sat Jan 06 06:24:59 2024

    Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
    Copyright (c) 1995 AT&T Corp.   All rights reserved.
    Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
    Copyright (c) 2001 Agere Systems   All rights reserved.
    Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

    Report Information
    ------------------
    Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf
    Design file:     ram2gs_lcmxo256c_impl1_map.ncd
    Preference file: ram2gs_lcmxo256c_impl1.prf
    Device,speed:    LCMXO256C,M
    Report level:    verbose report, limited to 1 item per preference
    --------------------------------------------------------------------------------

    Preference Summary

    FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)            168 items scored, 0 timing errors detected.

    FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)            0 items scored, 0 timing errors detected.

    FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)            0 items scored, 0 timing errors detected.

    FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)            392 items scored, 0 timing errors detected.

    BLOCK ASYNCPATHS
    BLOCK RESETPATHS
    --------------------------------------------------------------------------------

    ================================================================================
    Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
                168 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

    Passed: The following path meets requirements by 0.430ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              C1Submitted  (from PHI2_c -)
       Destination:    FF         Data in        C1Submitted  (to PHI2_c -)

       Delay:               0.411ns  (51.3% logic, 48.7% route), 2 logic levels.

     Constraint Details:

          0.411ns physical path delay SLICE_14 to SLICE_14 meets
         -0.019ns DIN_HLD and
          0.000ns delay constraint requirement (totaling -0.019ns) by 0.430ns

     Physical Path Details:

          Data path SLICE_14 to SLICE_14:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.137   SLICE_14.CLK to    SLICE_14.Q0 SLICE_14 (from PHI2_c)
    ROUTE         2   e 0.199    SLICE_14.Q0 to    SLICE_14.B0 C1Submitted
    CTOF_DEL    ---     0.074    SLICE_14.B0 to    SLICE_14.F0 SLICE_14
    ROUTE         1   e 0.001    SLICE_14.F0 to   SLICE_14.DI0 C1Submitted_RNO (to PHI2_c)
                      --------
                        0.411   (51.3% logic, 48.7% route), 2 logic levels.

    ================================================================================
    Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
                0 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

    ================================================================================
    Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
                0 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

    ================================================================================
    Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
                392 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

    Passed: The following path meets requirements by 0.342ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              CASr  (from RCLK_c +)
       Destination:    FF         Data in        CASr2  (to RCLK_c +)

       Delay:               0.325ns  (38.8% logic, 61.2% route), 1 logic levels.

     Constraint Details:

          0.325ns physical path delay SLICE_74 to SLICE_74 meets
         -0.017ns M_HLD and
          0.000ns delay constraint requirement (totaling -0.017ns) by 0.342ns

     Physical Path Details:

          Data path SLICE_74 to SLICE_74:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.126   SLICE_74.CLK to    SLICE_74.Q0 SLICE_74 (from RCLK_c)
    ROUTE         1   e 0.199    SLICE_74.Q0 to    SLICE_74.M1 CASr (to RCLK_c)
                      --------
                        0.325   (38.8% logic, 61.2% route), 1 logic levels.

    Report Summary
    --------------
    ----------------------------------------------------------------------------
    Preference(MIN Delays)                  |   Constraint|       Actual|Levels
    ----------------------------------------------------------------------------
                                            |             |             |
    FREQUENCY PORT "PHI2" 2.900000 MHz ;    |            -|            -|   2
                                            |             |             |
    FREQUENCY PORT "nCCAS" 2.900000 MHz ;   |            -|            -|   0
                                            |             |             |
    FREQUENCY PORT "nCRAS" 2.900000 MHz ;   |            -|            -|   0
                                            |             |             |
    FREQUENCY PORT "RCLK" 62.500000 MHz ;   |            -|            -|   1
                                            |             |             |
    ----------------------------------------------------------------------------

    All preferences were met.

    Clock Domains Analysis
    ------------------------

    Found 4 clocks:

    Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 10
       No transfer within this clock domain is found

       Data transfers from:
       Clock Domain: RCLK_c   Source: RCLK.PAD
          Not reported because source and destination domains are unrelated.
          To report these transfers please refer to preference CLKSKEWDIFF to define
          external clock skew between clock ports.

    Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 8
       No transfer within this clock domain is found

    Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 32
       Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;

       Data transfers from:
       Clock Domain: nCRAS_c   Source: nCRAS.PAD
          Not reported because source and destination domains are unrelated.
          To report these transfers please refer to preference CLKSKEWDIFF to define
          external clock skew between clock ports.

       Clock Domain: PHI2_c   Source: PHI2.PAD
          Not reported because source and destination domains are unrelated.
          To report these transfers please refer to preference CLKSKEWDIFF to define
          external clock skew between clock ports.

    Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 15
       Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;

       Data transfers from:
       Clock Domain: RCLK_c   Source: RCLK.PAD
          Not reported because source and destination domains are unrelated.
          To report these transfers please refer to preference CLKSKEWDIFF to define
          external clock skew between clock ports.

    Timing summary (Hold):
    ---------------

    Timing errors: 0  Score: 0
    Cumulative negative slack: 0

    Constraints cover 560 paths, 4 nets, and 424 connections (62.26% coverage)

    Timing summary (Setup and Hold):
    ---------------

    Timing errors: 0 (setup), 0 (hold)
    Score: 0 (setup), 0 (hold)
    Cumulative negative slack: 0 (0+0)
    --------------------------------------------------------------------------------

    --------------------------------------------------------------------------------