2023-08-20 11:10:11 +00:00
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<HEAD><TITLE>Lattice Map TRACE Report</TITLE>
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<PRE><A name="Map_Twr"></A><B><U><big>Map TRACE Report</big></U></B>
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2023-09-21 09:45:45 +00:00
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Loading design for application trce from file ram2gs_lcmxo2_1200hc_impl1_map.ncd.
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2023-08-20 11:10:11 +00:00
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Design name: RAM2GS
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NCD version: 3.3
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Vendor: LATTICE
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2023-09-21 09:45:45 +00:00
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Device: LCMXO2-1200HC
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2023-08-20 11:10:11 +00:00
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Package: TQFP100
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Performance: 4
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2023-09-21 09:45:45 +00:00
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Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
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Package Status: Final Version 1.44.
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2023-08-20 11:10:11 +00:00
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Performance Hardware Data Status: Final Version 34.4.
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Setup and Hold Report
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--------------------------------------------------------------------------------
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<A name="Map_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454</big></U></B>
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2024-01-07 02:52:05 +00:00
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Sat Nov 18 02:05:54 2023
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2023-08-20 11:10:11 +00:00
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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<A name="mtw1_set_ri"></A><B><U><big>Report Information</big></U></B>
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------------------
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2023-09-21 09:45:45 +00:00
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Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_1200HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
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Design file: ram2gs_lcmxo2_1200hc_impl1_map.ncd
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Preference file: ram2gs_lcmxo2_1200hc_impl1.prf
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Device,speed: LCMXO2-1200HC,4
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2023-08-20 11:10:11 +00:00
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Report level: verbose report, limited to 1 item per preference
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--------------------------------------------------------------------------------
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<A name="mtw1_set_ps"></A><B><U><big>Preference Summary</big></U></B>
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2023-09-21 09:45:45 +00:00
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<LI><A href='#map_twr_pref_0_0' Target='right'>FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)</A></LI> 147 items scored, 0 timing errors detected.
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2024-01-07 02:52:05 +00:00
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Report: 53.254MHz is the maximum frequency for this preference.
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2023-08-20 11:10:11 +00:00
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<LI><A href='#map_twr_pref_0_1' Target='right'>FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
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Report: 150.150MHz is the maximum frequency for this preference.
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<LI><A href='#map_twr_pref_0_2' Target='right'>FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
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Report: 150.150MHz is the maximum frequency for this preference.
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2024-01-07 02:52:05 +00:00
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<LI><A href='#map_twr_pref_0_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 891 items scored, 0 timing errors detected.
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Report: 95.383MHz is the maximum frequency for this preference.
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2023-08-20 11:10:11 +00:00
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BLOCK ASYNCPATHS
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BLOCK RESETPATHS
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--------------------------------------------------------------------------------
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================================================================================
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<A name="map_twr_pref_0_0"></A>Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
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2023-09-21 09:45:45 +00:00
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147 items scored, 0 timing errors detected.
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2023-08-20 11:10:11 +00:00
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--------------------------------------------------------------------------------
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2024-01-07 02:52:05 +00:00
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Passed: The following path meets requirements by 163.025ns (weighted slack = 326.050ns)
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2023-08-20 11:10:11 +00:00
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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2024-01-07 02:52:05 +00:00
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Source: FF Q Bank_0io[1] (from PHI2_c +)
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Destination: FF Data in CmdEnable (to PHI2_c -)
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2023-08-20 11:10:11 +00:00
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2024-01-07 02:52:05 +00:00
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Delay: 9.223ns (33.1% logic, 66.9% route), 6 logic levels.
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2023-08-20 11:10:11 +00:00
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Constraint Details:
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2024-01-07 02:52:05 +00:00
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9.223ns physical path delay Din[1]_MGIOL to SLICE_17 meets
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2023-08-20 11:10:11 +00:00
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172.414ns delay constraint less
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2024-01-07 02:52:05 +00:00
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0.166ns DIN_SET requirement (totaling 172.248ns) by 163.025ns
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2023-08-20 11:10:11 +00:00
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Physical Path Details:
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2024-01-07 02:52:05 +00:00
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Data path Din[1]_MGIOL to SLICE_17:
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2023-08-20 11:10:11 +00:00
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Name Fanout Delay (ns) Site Resource
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2024-01-07 02:52:05 +00:00
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C2INP_DEL --- 0.577 *[1]_MGIOL.CLK to *n[1]_MGIOL.IN Din[1]_MGIOL (from PHI2_c)
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ROUTE 1 e 1.234 *n[1]_MGIOL.IN to SLICE_90.A0 Bank[1]
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CTOF_DEL --- 0.495 SLICE_90.A0 to SLICE_90.F0 SLICE_90
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ROUTE 1 e 1.234 SLICE_90.F0 to SLICE_80.C0 un1_CmdEnable20_0_0_o2_10
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CTOF_DEL --- 0.495 SLICE_80.C0 to SLICE_80.F0 SLICE_80
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ROUTE 6 e 1.234 SLICE_80.F0 to SLICE_11.C1 N_367
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CTOF_DEL --- 0.495 SLICE_11.C1 to SLICE_11.F1 SLICE_11
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ROUTE 3 e 1.234 SLICE_11.F1 to SLICE_33.B0 CmdEnable16
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CTOF_DEL --- 0.495 SLICE_33.B0 to SLICE_33.F0 SLICE_33
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ROUTE 1 e 1.234 SLICE_33.F0 to SLICE_17.D0 CmdEnable_0_sqmuxa
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CTOF_DEL --- 0.495 SLICE_17.D0 to SLICE_17.F0 SLICE_17
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ROUTE 1 e 0.001 SLICE_17.F0 to SLICE_17.DI0 CmdEnable_s (to PHI2_c)
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2023-08-20 11:10:11 +00:00
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--------
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2024-01-07 02:52:05 +00:00
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9.223 (33.1% logic, 66.9% route), 6 logic levels.
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2023-08-20 11:10:11 +00:00
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2024-01-07 02:52:05 +00:00
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Report: 53.254MHz is the maximum frequency for this preference.
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2023-08-20 11:10:11 +00:00
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================================================================================
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<A name="map_twr_pref_0_1"></A>Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
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0 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 338.168ns
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The internal maximum frequency of the following component is 150.150 MHz
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Logical Details: Cell type Pin name Component name
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Destination: PIO PAD nCCAS
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Delay: 6.660ns -- based on Minimum Pulse Width
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Report: 150.150MHz is the maximum frequency for this preference.
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================================================================================
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<A name="map_twr_pref_0_2"></A>Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
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0 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 338.168ns
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The internal maximum frequency of the following component is 150.150 MHz
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Logical Details: Cell type Pin name Component name
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Destination: PIO PAD nCRAS
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Delay: 6.660ns -- based on Minimum Pulse Width
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Report: 150.150MHz is the maximum frequency for this preference.
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================================================================================
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<A name="map_twr_pref_0_3"></A>Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
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2024-01-07 02:52:05 +00:00
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891 items scored, 0 timing errors detected.
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2023-08-20 11:10:11 +00:00
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--------------------------------------------------------------------------------
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2024-01-07 02:52:05 +00:00
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Passed: The following path meets requirements by 5.516ns
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2023-08-20 11:10:11 +00:00
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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2024-01-07 02:52:05 +00:00
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Source: FF Q S[0] (from RCLK_c +)
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Destination: FF Data in nRWE_0io (to RCLK_c +)
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2023-08-20 11:10:11 +00:00
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2024-01-07 02:52:05 +00:00
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Delay: 10.331ns (28.3% logic, 71.7% route), 6 logic levels.
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2023-08-20 11:10:11 +00:00
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Constraint Details:
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2024-01-07 02:52:05 +00:00
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10.331ns physical path delay SLICE_16 to nRWE_MGIOL meets
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2023-08-20 11:10:11 +00:00
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16.000ns delay constraint less
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2024-01-07 02:52:05 +00:00
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0.153ns DO_SET requirement (totaling 15.847ns) by 5.516ns
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2023-08-20 11:10:11 +00:00
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Physical Path Details:
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2024-01-07 02:52:05 +00:00
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Data path SLICE_16 to nRWE_MGIOL:
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2023-08-20 11:10:11 +00:00
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Name Fanout Delay (ns) Site Resource
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2024-01-07 02:52:05 +00:00
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REG_DEL --- 0.452 SLICE_16.CLK to SLICE_16.Q0 SLICE_16 (from RCLK_c)
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ROUTE 12 e 1.234 SLICE_16.Q0 to SLICE_62.D1 CO0
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CTOF_DEL --- 0.495 SLICE_62.D1 to SLICE_62.F1 SLICE_62
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ROUTE 6 e 1.234 SLICE_62.F1 to SLICE_79.A1 IS_0_sqmuxa_0_o2
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CTOF_DEL --- 0.495 SLICE_79.A1 to SLICE_79.F1 SLICE_79
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ROUTE 2 e 1.234 SLICE_79.F1 to SLICE_28.D1 IS_0_sqmuxa_0_o3
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CTOF_DEL --- 0.495 SLICE_28.D1 to SLICE_28.F1 SLICE_28
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ROUTE 1 e 1.234 SLICE_28.F1 to SLICE_68.D1 nRWE_s_i_a2_1_0
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CTOF_DEL --- 0.495 SLICE_68.D1 to SLICE_68.F1 SLICE_68
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ROUTE 1 e 1.234 SLICE_68.F1 to SLICE_75.D0 nRWE_s_i_tz_0
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CTOF_DEL --- 0.495 SLICE_75.D0 to SLICE_75.F0 SLICE_75
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ROUTE 1 e 1.234 SLICE_75.F0 to *WE_MGIOL.OPOS N_252_i (to RCLK_c)
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2023-08-20 11:10:11 +00:00
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--------
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2024-01-07 02:52:05 +00:00
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10.331 (28.3% logic, 71.7% route), 6 logic levels.
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2023-08-20 11:10:11 +00:00
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2024-01-07 02:52:05 +00:00
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Report: 95.383MHz is the maximum frequency for this preference.
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2023-08-20 11:10:11 +00:00
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<A name="mtw1_set_rs"></A><B><U><big>Report Summary</big></U></B>
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--------------
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----------------------------------------------------------------------------
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Preference | Constraint| Actual|Levels
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----------------------------------------------------------------------------
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2024-01-07 02:52:05 +00:00
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FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 53.254 MHz| 6
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2023-08-20 11:10:11 +00:00
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FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
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FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
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2024-01-07 02:52:05 +00:00
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FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 95.383 MHz| 6
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2023-08-20 11:10:11 +00:00
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----------------------------------------------------------------------------
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All preferences were met.
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<A name="mtw1_set_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
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------------------------
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Found 4 clocks:
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2024-01-07 02:52:05 +00:00
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Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
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2023-08-20 11:10:11 +00:00
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No transfer within this clock domain is found
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Data transfers from:
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Clock Domain: RCLK_c Source: RCLK.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
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external clock skew between clock ports.
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Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
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No transfer within this clock domain is found
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2023-11-03 08:26:41 +00:00
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Clock Domain: RCLK_c Source: RCLK.PAD Loads: 48
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2023-08-20 11:10:11 +00:00
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Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
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Data transfers from:
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Clock Domain: nCRAS_c Source: nCRAS.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
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external clock skew between clock ports.
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Clock Domain: PHI2_c Source: PHI2.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
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external clock skew between clock ports.
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2023-09-21 09:45:45 +00:00
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Clock Domain: PHI2_c Source: PHI2.PAD Loads: 21
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2023-08-20 11:10:11 +00:00
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Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
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Data transfers from:
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Clock Domain: RCLK_c Source: RCLK.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
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external clock skew between clock ports.
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<A name="mtw1_set_ts"></A><B><U><big>Timing summary (Setup):</big></U></B>
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---------------
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Timing errors: 0 Score: 0
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Cumulative negative slack: 0
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2024-01-07 02:52:05 +00:00
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Constraints cover 1038 paths, 4 nets, and 732 connections (72.40% coverage)
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2023-08-20 11:10:11 +00:00
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--------------------------------------------------------------------------------
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<A name="Map_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454</big></U></B>
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2024-01-07 02:52:05 +00:00
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Sat Nov 18 02:05:54 2023
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2023-08-20 11:10:11 +00:00
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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<A name="mtw1_hold_ri"></A><B><U><big>Report Information</big></U></B>
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------------------
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2023-09-21 09:45:45 +00:00
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Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_1200HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
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Design file: ram2gs_lcmxo2_1200hc_impl1_map.ncd
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Preference file: ram2gs_lcmxo2_1200hc_impl1.prf
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Device,speed: LCMXO2-1200HC,M
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2023-08-20 11:10:11 +00:00
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Report level: verbose report, limited to 1 item per preference
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--------------------------------------------------------------------------------
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<A name="mtw1_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
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2023-09-21 09:45:45 +00:00
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<LI><A href='#map_twr_pref_1_0' Target='right'>FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)</A></LI> 147 items scored, 0 timing errors detected.
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2023-08-20 11:10:11 +00:00
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<LI><A href='#map_twr_pref_1_1' Target='right'>FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_1_2' Target='right'>FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
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2024-01-07 02:52:05 +00:00
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<LI><A href='#map_twr_pref_1_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 891 items scored, 0 timing errors detected.
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2023-08-20 11:10:11 +00:00
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BLOCK ASYNCPATHS
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BLOCK RESETPATHS
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--------------------------------------------------------------------------------
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================================================================================
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<A name="map_twr_pref_1_0"></A>Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
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2023-09-21 09:45:45 +00:00
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147 items scored, 0 timing errors detected.
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2023-08-20 11:10:11 +00:00
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 0.447ns
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q ADSubmitted (from PHI2_c -)
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Destination: FF Data in ADSubmitted (to PHI2_c -)
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Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels.
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Constraint Details:
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0.434ns physical path delay SLICE_10 to SLICE_10 meets
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-0.013ns DIN_HLD and
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0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
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Physical Path Details:
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Data path SLICE_10 to SLICE_10:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.133 SLICE_10.CLK to SLICE_10.Q0 SLICE_10 (from PHI2_c)
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ROUTE 2 e 0.199 SLICE_10.Q0 to SLICE_10.A0 ADSubmitted
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CTOF_DEL --- 0.101 SLICE_10.A0 to SLICE_10.F0 SLICE_10
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2024-01-07 02:52:05 +00:00
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ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r_0_0 (to PHI2_c)
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2023-08-20 11:10:11 +00:00
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--------
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0.434 (53.9% logic, 46.1% route), 2 logic levels.
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================================================================================
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<A name="map_twr_pref_1_1"></A>Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
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0 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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================================================================================
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<A name="map_twr_pref_1_2"></A>Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
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0 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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================================================================================
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<A name="map_twr_pref_1_3"></A>Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
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2024-01-07 02:52:05 +00:00
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891 items scored, 0 timing errors detected.
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2023-08-20 11:10:11 +00:00
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 0.351ns
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q CASr (from RCLK_c +)
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Destination: FF Data in CASr2 (to RCLK_c +)
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Delay: 0.332ns (40.1% logic, 59.9% route), 1 logic levels.
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Constraint Details:
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0.332ns physical path delay SLICE_12 to SLICE_12 meets
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-0.019ns M_HLD and
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0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns
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Physical Path Details:
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Data path SLICE_12 to SLICE_12:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.133 SLICE_12.CLK to SLICE_12.Q0 SLICE_12 (from RCLK_c)
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ROUTE 1 e 0.199 SLICE_12.Q0 to SLICE_12.M1 CASr (to RCLK_c)
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--------
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0.332 (40.1% logic, 59.9% route), 1 logic levels.
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<A name="mtw1_hold_rs"></A><B><U><big>Report Summary</big></U></B>
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--------------
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----------------------------------------------------------------------------
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Preference(MIN Delays) | Constraint| Actual|Levels
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----------------------------------------------------------------------------
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| | |
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FREQUENCY PORT "PHI2" 2.900000 MHz ; | -| -| 2
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FREQUENCY PORT "nCCAS" 2.900000 MHz ; | -| -| 0
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FREQUENCY PORT "nCRAS" 2.900000 MHz ; | -| -| 0
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FREQUENCY PORT "RCLK" 62.500000 MHz ; | -| -| 1
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----------------------------------------------------------------------------
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All preferences were met.
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<A name="mtw1_hold_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
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------------------------
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Found 4 clocks:
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2024-01-07 02:52:05 +00:00
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Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
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2023-08-20 11:10:11 +00:00
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No transfer within this clock domain is found
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Data transfers from:
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Clock Domain: RCLK_c Source: RCLK.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
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external clock skew between clock ports.
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Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
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No transfer within this clock domain is found
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2023-11-03 08:26:41 +00:00
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Clock Domain: RCLK_c Source: RCLK.PAD Loads: 48
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2023-08-20 11:10:11 +00:00
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Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
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Data transfers from:
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Clock Domain: nCRAS_c Source: nCRAS.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
|
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external clock skew between clock ports.
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Clock Domain: PHI2_c Source: PHI2.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
|
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|
external clock skew between clock ports.
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|
2023-09-21 09:45:45 +00:00
|
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Clock Domain: PHI2_c Source: PHI2.PAD Loads: 21
|
2023-08-20 11:10:11 +00:00
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Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
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Data transfers from:
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Clock Domain: RCLK_c Source: RCLK.PAD
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Not reported because source and destination domains are unrelated.
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|
To report these transfers please refer to preference CLKSKEWDIFF to define
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|
external clock skew between clock ports.
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<A name="mtw1_hold_ts"></A><B><U><big>Timing summary (Hold):</big></U></B>
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---------------
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Timing errors: 0 Score: 0
|
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|
|
Cumulative negative slack: 0
|
|
|
|
|
|
2024-01-07 02:52:05 +00:00
|
|
|
Constraints cover 1038 paths, 4 nets, and 732 connections (72.40% coverage)
|
2023-08-20 11:10:11 +00:00
|
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<A name="mtw1_ts"></A><B><U><big>Timing summary (Setup and Hold):</big></U></B>
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---------------
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Timing errors: 0 (setup), 0 (hold)
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Score: 0 (setup), 0 (hold)
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Cumulative negative slack: 0 (0+0)
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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