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CPLD/LCMXO2/LCMXO2-640HC/impl1/xxx_lse_cp_file_list create mode 100644 CPLD/LCMXO2/LCMXO2-640HC/impl1/xxx_lse_sign_file create mode 100644 CPLD/LCMXO2/LCMXO2-640HC/msg_file.log create mode 100644 CPLD/LCMXO2/RAM2GS-LCMXO2.v diff --git a/CPLD/LCMXO/LCMXO256C/.run_manager.ini b/CPLD/LCMXO/LCMXO256C/.run_manager.ini new file mode 100644 index 0000000..be682d1 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/.run_manager.ini @@ -0,0 +1,9 @@ +[Runmanager] +Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0) +windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\x2\xc9\0\0\x2i\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0) +headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0) + +[impl1%3CStrategy1%3E] +isChecked=true +isHidden=false +isExpanded=true diff --git a/CPLD/LCMXO/LCMXO256C/.setting.ini b/CPLD/LCMXO/LCMXO256C/.setting.ini new file mode 100644 index 0000000..c145fb8 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/.setting.ini @@ -0,0 +1,4 @@ +[General] +Export.auto_tasks=IBIS, Bitgen +Map.auto_tasks=MapEqu, MapTrace +PAR.auto_tasks=PARTrace, IOTiming diff --git a/CPLD/LCMXO/LCMXO256C/.spread_sheet.ini b/CPLD/LCMXO/LCMXO256C/.spread_sheet.ini new file mode 100644 index 0000000..6c511f4 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/.spread_sheet.ini @@ -0,0 +1,3 @@ +[General] +COLUMN_POS_INFO_NAME_-1_0=Prioritize +COLUMN_POS_INFO_NAME_-1_1=PIO Register diff --git a/CPLD/LCMXO/LCMXO256C/.spreadsheet_view.ini b/CPLD/LCMXO/LCMXO256C/.spreadsheet_view.ini new file mode 100644 index 0000000..0aa848d --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/.spreadsheet_view.ini @@ -0,0 +1,65 @@ +[General] +pin_sort_type=0 +pin_sort_ascending=true +sig_sort_type=0 +sig_sort_ascending=true +active_Sheet=Timing Preferences + +[Port%20Assignments] +Name="166,0" +Group%20By="84,1" +Pin="63,2" +BANK="62,3" +IO_TYPE="117,4" +PULLMODE="119,5" +DRIVE="67,6" +SLEWRATE="92,7" +OPENDRAIN="97,8" +Outload%20%28pF%29="103,9" +MaxSkew="87,10" +Clock%20Load%20Only="121,11" +sort_columns="Name,Ascending" + +[Pin%20Assignments] +Pin="90,0" +Pad%20Name="89,1" +Dual%20Function="109,2" +Polarity="77,3" +BANK="0,4" +IO_TYPE="117,5" +Signal%20Name="123,6" +Signal%20Type="115,7" +sort_columns="Pin,Ascending" + +[Clock%20Resource] +Clock%20Type="100,ELLIPSIS" +Clock%20Name="100,ELLIPSIS" +Selection="100,ELLIPSIS" + +[Global%20Preferences] +Preference%20Name="222,ELLIPSIS" +Preference%20Value="236,ELLIPSIS" + +[Cell%20Mapping] +Type="100,ELLIPSIS" +Name="100,ELLIPSIS" +Din\Dout="100,ELLIPSIS" +PIO%20Register="100,ELLIPSIS" + +[Route%20Priority] +Type="100,ELLIPSIS" +Name="100,ELLIPSIS" +Prioritize="100,ELLIPSIS" + +[Timing%20Preferences] +Preference%20Name="246,ELLIPSIS" +Preference%20Value="104,ELLIPSIS" +Preference%20Unit="1012,ELLIPSIS" + +[Group] +Group%20Type\Name="134,ELLIPSIS" +Value="1245,ELLIPSIS" + +[Misc%20Preferences] +Preference%20Name="117,ELLIPSIS" +Preference%20Value="104,ELLIPSIS" diff --git a/CPLD/MAX/UFM.qip b/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ccl similarity index 100% rename from CPLD/MAX/UFM.qip rename to CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ccl diff --git a/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ldf b/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ldf new file mode 100644 index 0000000..0accfcf --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ldf @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.lpf b/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.lpf new file mode 100644 index 0000000..9fa278f --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.lpf @@ -0,0 +1,226 @@ +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +LOCATE COMP "Dout[0]" SITE "1" ; +LOCATE COMP "Dout[6]" SITE "2" ; +LOCATE COMP "Dout[7]" SITE "3" ; +LOCATE COMP "Dout[4]" SITE "4" ; +LOCATE COMP "Dout[5]" SITE "5" ; +LOCATE COMP "Dout[3]" SITE "6" ; +LOCATE COMP "Dout[1]" SITE "7" ; +LOCATE COMP "Dout[2]" SITE "8" ; +LOCATE COMP "Din[2]" SITE "14" ; +LOCATE COMP "Din[1]" SITE "15" ; +LOCATE COMP "Din[3]" SITE "16" ; +LOCATE COMP "Din[5]" SITE "17" ; +LOCATE COMP "Din[4]" SITE "18" ; +LOCATE COMP "Din[7]" SITE "19" ; +LOCATE COMP "Din[6]" SITE "20" ; +LOCATE COMP "Din[0]" SITE "21" ; +LOCATE COMP "LED" SITE "57" ; +LOCATE COMP "RA[0]" SITE "98" ; +LOCATE COMP "RA[1]" SITE "89" ; +LOCATE COMP "RA[2]" SITE "94" ; +LOCATE COMP "RA[3]" SITE "97" ; +LOCATE COMP "RA[4]" SITE "99" ; +LOCATE COMP "RA[5]" SITE "95" ; +LOCATE COMP "RA[6]" SITE "91" ; +LOCATE COMP "RA[7]" SITE "100" ; +LOCATE COMP "RA[8]" SITE "96" ; +LOCATE COMP "RA[9]" SITE "85" ; +LOCATE COMP "RA[10]" SITE "87" ; +LOCATE COMP "RA[11]" SITE "79" ; +LOCATE COMP "RBA[1]" SITE "83" ; +LOCATE COMP "RBA[0]" SITE "63" ; +LOCATE COMP "RCKE" SITE "82" ; +LOCATE COMP "RDQMH" SITE "76" ; +LOCATE COMP "RDQML" SITE "61" ; +LOCATE COMP "UFMCLK" SITE "58" ; +LOCATE COMP "UFMSDI" SITE "56" ; +LOCATE COMP "nUFMCS" SITE "53" ; +LOCATE COMP "nRCAS" SITE "78" ; +LOCATE COMP "nRCS" SITE "77" ; +LOCATE COMP "nRRAS" SITE "73" ; +LOCATE COMP "nRWE" SITE "72" ; +LOCATE COMP "RD[0]" SITE "64" ; +LOCATE COMP "RD[1]" SITE "65" ; +LOCATE COMP "RD[2]" SITE "66" ; +LOCATE COMP "RD[3]" SITE "67" ; +LOCATE COMP "RD[4]" SITE "68" ; +LOCATE COMP "RD[5]" SITE "69" ; +LOCATE COMP "RD[6]" SITE "70" ; +LOCATE COMP "RD[7]" SITE "71" ; +LOCATE COMP "PHI2" SITE "39" ; +LOCATE COMP "RCLK" SITE "86" ; +LOCATE COMP "nCCAS" SITE "27" ; +LOCATE COMP "nCRAS" SITE "43" ; +LOCATE COMP "CROW[0]" SITE "32" ; +LOCATE COMP "CROW[1]" SITE "34" ; +LOCATE COMP "UFMSDO" SITE "55" ; +LOCATE COMP "nFWE" SITE "22" ; +LOCATE COMP "MAin[0]" SITE "23" ; +LOCATE COMP "MAin[1]" SITE "38" ; +LOCATE COMP "MAin[2]" SITE "37" ; +LOCATE COMP "MAin[3]" SITE "47" ; +LOCATE COMP "MAin[4]" SITE "46" ; +LOCATE COMP "MAin[5]" SITE "45" ; +LOCATE COMP "MAin[6]" SITE "49" ; +LOCATE COMP "MAin[7]" SITE "44" ; +LOCATE COMP "MAin[8]" SITE "50" ; +LOCATE COMP "MAin[9]" SITE "51" ; +IOBUF PORT "CROW[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "CROW[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "nCRAS" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "nCCAS" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "RCLK" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "PHI2" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "Din[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "Din[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "Din[2]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "Din[3]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "Din[4]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "Din[5]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "Din[6]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "Din[7]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "MAin[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "MAin[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "MAin[2]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "MAin[3]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "MAin[4]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "MAin[5]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "MAin[6]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "MAin[7]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "MAin[8]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "MAin[9]" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "UFMSDO" PULLMODE=KEEPER IO_TYPE=LVTTL33 ; +IOBUF PORT "nFWE" PULLMODE=NONE IO_TYPE=LVTTL33 ; +IOBUF PORT "Dout[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "Dout[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "Dout[2]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "Dout[3]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "Dout[4]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "Dout[5]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "Dout[6]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "Dout[7]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "LED" PULLMODE=NONE IO_TYPE=LVTTL33 DRIVE=16 SLEWRATE=SLOW ; +IOBUF PORT "RA[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "RA[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "RA[2]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "RA[3]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "RA[4]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "RA[5]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "RA[6]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "RA[7]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "RA[8]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "RA[9]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "RA[10]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "RA[11]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "RBA[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "RBA[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "RCKE" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "RDQMH" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "RDQML" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "UFMCLK" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "UFMSDI" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "nRCAS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "nRCS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "nRRAS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "nRWE" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "nUFMCS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; +IOBUF PORT "RD[0]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "RD[1]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "RD[2]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "RD[3]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "RD[4]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "RD[5]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "RD[6]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "RD[7]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; +OUTPUT PORT "RD[7]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[0]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[1]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[2]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[3]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[4]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[5]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[6]" LOAD 20.000000 pF ; +OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ; +OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ; +OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ; +OUTPUT PORT "nRWE" LOAD 10.000000 pF ; +OUTPUT PORT "nRCAS" LOAD 10.000000 pF ; +OUTPUT PORT "nRCS" LOAD 10.000000 pF ; +OUTPUT PORT "nRRAS" LOAD 10.000000 pF ; +OUTPUT PORT "RDQML" LOAD 10.000000 pF ; +OUTPUT PORT "RDQMH" LOAD 10.000000 pF ; +OUTPUT PORT "RCKE" LOAD 10.000000 pF ; +OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ; +OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[11]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[10]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[9]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[8]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[7]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[6]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[5]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[4]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[3]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[2]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[1]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[0]" LOAD 10.000000 pF ; +OUTPUT PORT "LED" LOAD 25.000000 pF ; +OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ; +USE PRIMARY NET "PHI2_c" ; +USE PRIMARY NET "RCLK_c" ; +VOLTAGE 3.300 V; +VCCIO_DERATE BANK 0 PERCENT -5; +VCCIO_DERATE PERCENT -5; +VCCIO_DERATE BANK 1 PERCENT -5; +PERIOD NET "PHI2_c" 350.000000 ns ; +PERIOD NET "nCCAS_c" 350.000000 ns ; +PERIOD NET "nCRAS_c" 350.000000 ns ; +PERIOD NET "RCLK_c" 16.000000 ns ; +CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; +USE PRIMARY NET "nCCAS_c" ; +USE PRIMARY NET "nCRAS_c" ; diff --git a/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C1.sty b/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C1.sty new file mode 100644 index 0000000..feec63c --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C1.sty @@ -0,0 +1,205 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcl.html b/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcl.html new file mode 100644 index 0000000..ddd739c --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcl.html @@ -0,0 +1,91 @@ + +Lattice TCL Log + + +
pn210816194012
+#Start recording tcl command: 8/16/2021 19:02:08
+#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C; Project name: RAM2GS_LCMXO256C
+prj_project new -name "RAM2GS_LCMXO256C" -impl "impl1" -dev LCMXO256C-3T100C -synthesis "lse"
+prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM4GS-LCMXO.v"
+prj_project save
+prj_src remove "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM4GS-LCMXO.v"
+prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v"
+prj_run PAR -impl impl1
+prj_run PAR -impl impl1
+prj_run Map -impl impl1
+prj_run Export -impl impl1
+prj_run PAR -impl impl1
+prj_run Map -impl impl1
+prj_run PAR -impl impl1
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+#Stop recording: 8/16/2021 19:40:12
+
+
+
+pn210816202808
+#Start recording tcl command: 8/16/2021 20:24:10
+#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C; Project name: RAM2GS_LCMXO256C
+prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ldf"
+prj_run Export -impl impl1 -forceAll
+#Stop recording: 8/16/2021 20:28:08
+
+
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+ + diff --git a/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn210816194012.tcr b/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn210816194012.tcr new file mode 100644 index 0000000..c6ef2b4 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn210816194012.tcr @@ -0,0 +1,17 @@ +#Start recording tcl command: 8/16/2021 19:02:08 +#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C; Project name: RAM2GS_LCMXO256C +prj_project new -name "RAM2GS_LCMXO256C" -impl "impl1" -dev LCMXO256C-3T100C -synthesis "lse" +prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM4GS-LCMXO.v" +prj_project save +prj_src remove "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM4GS-LCMXO.v" +prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v" +prj_run PAR -impl impl1 +prj_run PAR -impl impl1 +prj_run Map -impl impl1 +prj_run Export -impl impl1 +prj_run PAR -impl impl1 +prj_run Map -impl impl1 +prj_run PAR -impl impl1 +prj_run Export -impl impl1 -forceAll +prj_run Export -impl impl1 -forceAll +#Stop recording: 8/16/2021 19:40:12 diff --git a/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn210816202808.tcr b/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn210816202808.tcr new file mode 100644 index 0000000..fa5fbe8 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn210816202808.tcr @@ -0,0 +1,5 @@ +#Start recording tcl command: 8/16/2021 20:24:10 +#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C; Project name: RAM2GS_LCMXO256C +prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ldf" +prj_run Export -impl impl1 -forceAll +#Stop recording: 8/16/2021 20:28:08 diff --git a/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn210816213322.tcr b/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn210816213322.tcr new file mode 100644 index 0000000..2a19da1 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn210816213322.tcr @@ -0,0 +1,4 @@ +#Start recording tcl command: 8/16/2021 21:33:16 +#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C; Project name: RAM2GS_LCMXO256C +prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ldf" +#Stop recording: 8/16/2021 21:33:22 diff --git a/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn210816214112.tcr b/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn210816214112.tcr new file mode 100644 index 0000000..e2e3953 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn210816214112.tcr @@ -0,0 +1,6 @@ +#Start recording tcl command: 8/16/2021 21:32:14 +#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C; Project name: RAM2GS_LCMXO256C +prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ldf" +prj_run Export -impl impl1 -forceAll +prj_run Export -impl impl1 -forceOne +#Stop recording: 8/16/2021 21:41:12 diff --git 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zY_ZoYDESrK^FXR&?DC5`D7Dc%E7d`7irHcHDIj(ixO>6G5r>Lb2FM5oIetN* z70gyz-4xAu)?!Si4-?He4Dd^$8M6$xjcr&x4XKX1{f2Cv^I%@{UP_&ap#cU* zDV}~~16t>2Q0K#iR`9^dmaXvzQ?VYqE=DYSxl6Oj*%GLG86t?L3M_K8d<9j{Es)`X;Q$xH{q0H)qI=Qu^5 z^b1TmR_3$5Vwd7X`=EmS(u*+&i(||@OAV}5u(nUaV%3-zNHHX6@rqAu#$wCsh{t7~G63sX^H|`Y8SjCZs_r2GK zZ@M5wq=&@JqrQ9CB36dh7LlBELe(6lV7_nj>|d&AW4`6#^Vp3;ta~aEfkVWg#U0h> zu3EKfR1mh4g-tHAYe-dxy(5Qt+?miR4k xjhDL0-m;DEOEy>)Ev%M}BzD++$R<|AUnO}cNAy(4q%@>tyyIR{wr_mn{{V8_x2pgE literal 0 HcmV?d00001 diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.pad b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.pad new file mode 100644 index 0000000..0445323 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.pad @@ -0,0 +1,271 @@ +PAD Specification File +*************************** + +PART TYPE: LCMXO256C +Performance Grade: 3 +PACKAGE: TQFP100 +Package Status: Final Version 1.19 + +Mon Aug 16 21:32:33 2021 + +Pinout by Port Name: ++-----------+----------+--------------+------+----------------------------------+ +| Port Name | Pin/Bank | Buffer Type | Site | Properties | ++-----------+----------+--------------+------+----------------------------------+ +| CROW[0] | 32/1 | LVTTL33_IN | PB2C | SLEW:FAST | +| CROW[1] | 34/1 | LVTTL33_IN | PB2D | SLEW:FAST | +| Din[0] | 21/1 | LVTTL33_IN | PL8A | SLEW:FAST | +| Din[1] | 15/1 | LVTTL33_IN | PL6A | SLEW:FAST | +| Din[2] | 14/1 | LVTTL33_IN | PL5D | SLEW:FAST | +| Din[3] | 16/1 | LVTTL33_IN | PL6B | SLEW:FAST | +| Din[4] | 18/1 | LVTTL33_IN | PL7B | SLEW:FAST | +| Din[5] | 17/1 | LVTTL33_IN | PL7A | SLEW:FAST | +| Din[6] | 20/1 | LVTTL33_IN | PL7D | SLEW:FAST | +| Din[7] | 19/1 | LVTTL33_IN | PL7C | SLEW:FAST | +| Dout[0] | 1/1 | LVTTL33_OUT | PL2A | DRIVE:4mA SLEW:SLOW | +| Dout[1] | 7/1 | LVTTL33_OUT | PL4A | DRIVE:4mA SLEW:SLOW | +| Dout[2] | 8/1 | LVTTL33_OUT | PL4B | DRIVE:4mA SLEW:SLOW | +| Dout[3] | 6/1 | LVTTL33_OUT | PL3D | DRIVE:4mA SLEW:SLOW | +| Dout[4] | 4/1 | LVTTL33_OUT | PL3B | DRIVE:4mA SLEW:SLOW | +| Dout[5] | 5/1 | LVTTL33_OUT | PL3C | DRIVE:4mA SLEW:SLOW | +| Dout[6] | 2/1 | LVTTL33_OUT | PL2B | DRIVE:4mA SLEW:SLOW | +| Dout[7] | 3/1 | LVTTL33_OUT | PL3A | DRIVE:4mA SLEW:SLOW | +| LED | 57/0 | LVTTL33_OUT | PR7B | DRIVE:16mA SLEW:SLOW | +| MAin[0] | 23/1 | LVTTL33_IN | PL9A | SLEW:FAST | +| MAin[1] | 38/1 | LVTTL33_IN | PB3C | SLEW:FAST | +| MAin[2] | 37/1 | LVTTL33_IN | PB3B | SLEW:FAST | +| MAin[3] | 47/1 | LVTTL33_IN | PB5A | SLEW:FAST | +| MAin[4] | 46/1 | LVTTL33_IN | PB4D | SLEW:FAST | +| MAin[5] | 45/1 | LVTTL33_IN | PB4C | SLEW:FAST | +| MAin[6] | 49/1 | LVTTL33_IN | PB5C | SLEW:FAST | +| MAin[7] | 44/1 | LVTTL33_IN | PB4B | SLEW:FAST | +| MAin[8] | 50/1 | LVTTL33_IN | PB5D | SLEW:FAST | +| MAin[9] | 51/0 | LVTTL33_IN | PR9B | SLEW:FAST | +| PHI2 | 39/1 | LVTTL33_IN | PB3D | SLEW:FAST | +| RA[0] | 98/0 | LVTTL33_OUT | PT2C | DRIVE:4mA SLEW:SLOW | +| RA[10] | 87/0 | LVTTL33_OUT | PT3D | DRIVE:4mA SLEW:SLOW | +| RA[11] | 79/0 | LVTTL33_OUT | PT5A | DRIVE:4mA SLEW:SLOW | +| RA[1] | 89/0 | LVTTL33_OUT | PT3C | DRIVE:4mA SLEW:SLOW | +| RA[2] | 94/0 | LVTTL33_OUT | PT3A | DRIVE:4mA SLEW:SLOW | +| RA[3] | 97/0 | LVTTL33_OUT | PT2D | DRIVE:4mA SLEW:SLOW | +| RA[4] | 99/0 | LVTTL33_OUT | PT2B | DRIVE:4mA SLEW:SLOW | +| RA[5] | 95/0 | LVTTL33_OUT | PT2F | DRIVE:4mA SLEW:SLOW | +| RA[6] | 91/0 | LVTTL33_OUT | PT3B | DRIVE:4mA SLEW:SLOW | +| RA[7] | 100/0 | LVTTL33_OUT | PT2A | DRIVE:4mA SLEW:SLOW | +| RA[8] | 96/0 | LVTTL33_OUT | PT2E | DRIVE:4mA SLEW:SLOW | +| RA[9] | 85/0 | LVTTL33_OUT | PT4B | DRIVE:4mA SLEW:SLOW | +| RBA[0] | 63/0 | LVTTL33_OUT | PR5D | DRIVE:4mA SLEW:SLOW | +| RBA[1] | 83/0 | LVTTL33_OUT | PT4C | DRIVE:4mA SLEW:SLOW | +| RCKE | 82/0 | LVTTL33_OUT | PT4D | DRIVE:4mA SLEW:SLOW | +| RCLK | 86/0 | LVTTL33_IN | PT4A | SLEW:FAST | +| RDQMH | 76/0 | LVTTL33_OUT | PR2A | DRIVE:4mA SLEW:SLOW | +| RDQML | 61/0 | LVTTL33_OUT | PR6A | DRIVE:4mA SLEW:SLOW | +| RD[0] | 64/0 | LVTTL33_BIDI | PR5C | DRIVE:4mA SLEW:SLOW PULL:KEEPER | +| RD[1] | 65/0 | LVTTL33_BIDI | PR5B | DRIVE:4mA SLEW:SLOW PULL:KEEPER | +| RD[2] | 66/0 | LVTTL33_BIDI | PR5A | DRIVE:4mA SLEW:SLOW PULL:KEEPER | +| RD[3] | 67/0 | LVTTL33_BIDI | PR4B | DRIVE:4mA SLEW:SLOW PULL:KEEPER | +| RD[4] | 68/0 | LVTTL33_BIDI | PR4A | DRIVE:4mA SLEW:SLOW PULL:KEEPER | +| RD[5] | 69/0 | LVTTL33_BIDI | PR3D | DRIVE:4mA SLEW:SLOW PULL:KEEPER | +| RD[6] | 70/0 | LVTTL33_BIDI | PR3C | DRIVE:4mA SLEW:SLOW PULL:KEEPER | +| RD[7] | 71/0 | LVTTL33_BIDI | PR3B | DRIVE:4mA SLEW:SLOW PULL:KEEPER | +| UFMCLK | 58/0 | LVTTL33_OUT | PR7A | DRIVE:4mA SLEW:SLOW | +| UFMSDI | 56/0 | LVTTL33_OUT | PR7C | DRIVE:4mA SLEW:SLOW | +| UFMSDO | 55/0 | LVTTL33_IN | PR7D | SLEW:FAST PULL:KEEPER | +| nCCAS | 27/1 | LVTTL33_IN | PL9B | SLEW:FAST | +| nCRAS | 43/1 | LVTTL33_IN | PB4A | SLEW:FAST | +| nFWE | 22/1 | LVTTL33_IN | PL8B | SLEW:FAST | +| nRCAS | 78/0 | LVTTL33_OUT | PT5B | DRIVE:4mA SLEW:SLOW | +| nRCS | 77/0 | LVTTL33_OUT | PT5C | DRIVE:4mA SLEW:SLOW | +| nRRAS | 73/0 | LVTTL33_OUT | PR2B | DRIVE:4mA SLEW:SLOW | +| nRWE | 72/0 | LVTTL33_OUT | PR3A | DRIVE:4mA SLEW:SLOW | +| nUFMCS | 53/0 | LVTTL33_OUT | PR8B | DRIVE:4mA SLEW:SLOW | ++-----------+----------+--------------+------+----------------------------------+ + +Vccio by Bank: ++------+-------+ +| Bank | Vccio | ++------+-------+ +| 0 | 3.3V | +| 1 | 3.3V | ++------+-------+ + +Vref by Bank: ++------+-----+-----------------+---------+ +| Vref | Pin | Bank # / Vref # | Load(s) | ++------+-----+-----------------+---------+ ++------+-----+-----------------+---------+ + +Pinout by Pin Number: ++----------+---------------------+------------+--------------+------+---------------+ +| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | ++----------+---------------------+------------+--------------+------+---------------+ +| 1/1 | Dout[0] | LOCATED | LVTTL33_OUT | PL2A | | +| 2/1 | Dout[6] | LOCATED | LVTTL33_OUT | PL2B | | +| 3/1 | Dout[7] | LOCATED | LVTTL33_OUT | PL3A | | +| 4/1 | Dout[4] | LOCATED | LVTTL33_OUT | PL3B | | +| 5/1 | Dout[5] | LOCATED | LVTTL33_OUT | PL3C | | +| 6/1 | Dout[3] | LOCATED | LVTTL33_OUT | PL3D | | +| 7/1 | Dout[1] | LOCATED | LVTTL33_OUT | PL4A | | +| 8/1 | Dout[2] | LOCATED | LVTTL33_OUT | PL4B | | +| 9/1 | unused, PULL:UP | | | PL5A | | +| 11/1 | unused, PULL:UP | | | PL5B | | +| 13/1 | unused, PULL:UP | | | PL5C | | +| 14/1 | Din[2] | LOCATED | LVTTL33_IN | PL5D | GSR_PADN | +| 15/1 | Din[1] | LOCATED | LVTTL33_IN | PL6A | | +| 16/1 | Din[3] | LOCATED | LVTTL33_IN | PL6B | TSALLPAD | +| 17/1 | Din[5] | LOCATED | LVTTL33_IN | PL7A | | +| 18/1 | Din[4] | LOCATED | LVTTL33_IN | PL7B | | +| 19/1 | Din[7] | LOCATED | LVTTL33_IN | PL7C | | +| 20/1 | Din[6] | LOCATED | LVTTL33_IN | PL7D | | +| 21/1 | Din[0] | LOCATED | LVTTL33_IN | PL8A | | +| 22/1 | nFWE | LOCATED | LVTTL33_IN | PL8B | | +| 23/1 | MAin[0] | LOCATED | LVTTL33_IN | PL9A | | +| 27/1 | nCCAS | LOCATED | LVTTL33_IN | PL9B | | +| 29/1 | unused, PULL:UP | | | PB2A | | +| 30/1 | unused, PULL:UP | | | PB2B | | +| 32/1 | CROW[0] | LOCATED | LVTTL33_IN | PB2C | | +| 34/1 | CROW[1] | LOCATED | LVTTL33_IN | PB2D | | +| 36/1 | unused, PULL:UP | | | PB3A | PCLKT1_1 | +| 37/1 | MAin[2] | LOCATED | LVTTL33_IN | PB3B | | +| 38/1 | MAin[1] | LOCATED | LVTTL33_IN | PB3C | PCLKT1_0 | +| 39/1 | PHI2 | LOCATED | LVTTL33_IN | PB3D | | +| 43/1 | nCRAS | LOCATED | LVTTL33_IN | PB4A | | +| 44/1 | MAin[7] | LOCATED | LVTTL33_IN | PB4B | | +| 45/1 | MAin[5] | LOCATED | LVTTL33_IN | PB4C | | +| 46/1 | MAin[4] | LOCATED | LVTTL33_IN | PB4D | | +| 47/1 | MAin[3] | LOCATED | LVTTL33_IN | PB5A | | +| 49/1 | MAin[6] | LOCATED | LVTTL33_IN | PB5C | | +| 50/1 | MAin[8] | LOCATED | LVTTL33_IN | PB5D | | +| 51/0 | MAin[9] | LOCATED | LVTTL33_IN | PR9B | | +| 52/0 | unused, PULL:UP | | | PR9A | | +| 53/0 | nUFMCS | LOCATED | LVTTL33_OUT | PR8B | | +| 54/0 | unused, PULL:UP | | | PR8A | | +| 55/0 | UFMSDO | LOCATED | LVTTL33_IN | PR7D | | +| 56/0 | UFMSDI | LOCATED | LVTTL33_OUT | PR7C | | +| 57/0 | LED | LOCATED | LVTTL33_OUT | PR7B | | +| 58/0 | UFMCLK | LOCATED | LVTTL33_OUT | PR7A | | +| 59/0 | unused, PULL:UP | | | PR6B | | +| 61/0 | RDQML | LOCATED | LVTTL33_OUT | PR6A | | +| 63/0 | RBA[0] | LOCATED | LVTTL33_OUT | PR5D | | +| 64/0 | RD[0] | LOCATED | LVTTL33_BIDI | PR5C | | +| 65/0 | RD[1] | LOCATED | LVTTL33_BIDI | PR5B | | +| 66/0 | RD[2] | LOCATED | LVTTL33_BIDI | PR5A | | +| 67/0 | RD[3] | LOCATED | LVTTL33_BIDI | PR4B | | +| 68/0 | RD[4] | LOCATED | LVTTL33_BIDI | PR4A | | +| 69/0 | RD[5] | LOCATED | LVTTL33_BIDI | PR3D | | +| 70/0 | RD[6] | LOCATED | LVTTL33_BIDI | PR3C | | +| 71/0 | RD[7] | LOCATED | LVTTL33_BIDI | PR3B | | +| 72/0 | nRWE | LOCATED | LVTTL33_OUT | PR3A | | +| 73/0 | nRRAS | LOCATED | LVTTL33_OUT | PR2B | | +| 76/0 | RDQMH | LOCATED | LVTTL33_OUT | PR2A | | +| 77/0 | nRCS | LOCATED | LVTTL33_OUT | PT5C | | +| 78/0 | nRCAS | LOCATED | LVTTL33_OUT | PT5B | | +| 79/0 | RA[11] | LOCATED | LVTTL33_OUT | PT5A | | +| 80/0 | unused, PULL:UP | | | PT4F | | +| 81/0 | unused, PULL:UP | | | PT4E | | +| 82/0 | RCKE | LOCATED | LVTTL33_OUT | PT4D | | +| 83/0 | RBA[1] | LOCATED | LVTTL33_OUT | PT4C | | +| 85/0 | RA[9] | LOCATED | LVTTL33_OUT | PT4B | PCLKT0_1 | +| 86/0 | RCLK | LOCATED | LVTTL33_IN | PT4A | PCLKT0_0 | +| 87/0 | RA[10] | LOCATED | LVTTL33_OUT | PT3D | | +| 89/0 | RA[1] | LOCATED | LVTTL33_OUT | PT3C | | +| 91/0 | RA[6] | LOCATED | LVTTL33_OUT | PT3B | | +| 94/0 | RA[2] | LOCATED | LVTTL33_OUT | PT3A | | +| 95/0 | RA[5] | LOCATED | LVTTL33_OUT | PT2F | | +| 96/0 | RA[8] | LOCATED | LVTTL33_OUT | PT2E | | +| 97/0 | RA[3] | LOCATED | LVTTL33_OUT | PT2D | | +| 98/0 | RA[0] | LOCATED | LVTTL33_OUT | PT2C | | +| 99/0 | RA[4] | LOCATED | LVTTL33_OUT | PT2B | | +| 100/0 | RA[7] | LOCATED | LVTTL33_OUT | PT2A | | +| PB5B/0 | unused, PULL:UP | | | PB5B | | +| PT5D/0 | unused, PULL:UP | | | PT5D | | +| TCK/1 | | | | TCK | TCK | +| TDI/1 | | | | TDI | TDI | +| TDO/1 | | | | TDO | TDO | +| TMS/1 | | | | TMS | TMS | ++----------+---------------------+------------+--------------+------+---------------+ + + +List of All Pins' Locate Preferences Based on Final Placement After PAR +to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): + +LOCATE COMP "CROW[0]" SITE "32"; +LOCATE COMP "CROW[1]" SITE "34"; +LOCATE COMP "Din[0]" SITE "21"; +LOCATE COMP "Din[1]" SITE "15"; +LOCATE COMP "Din[2]" SITE "14"; +LOCATE COMP "Din[3]" SITE "16"; +LOCATE COMP "Din[4]" SITE "18"; +LOCATE COMP "Din[5]" SITE "17"; +LOCATE COMP "Din[6]" SITE "20"; +LOCATE COMP "Din[7]" SITE "19"; +LOCATE COMP "Dout[0]" SITE "1"; +LOCATE COMP "Dout[1]" SITE "7"; +LOCATE COMP "Dout[2]" SITE "8"; +LOCATE COMP "Dout[3]" SITE "6"; +LOCATE COMP "Dout[4]" SITE "4"; +LOCATE COMP "Dout[5]" SITE "5"; +LOCATE COMP "Dout[6]" SITE "2"; +LOCATE COMP "Dout[7]" SITE "3"; +LOCATE COMP "LED" SITE "57"; +LOCATE COMP "MAin[0]" SITE "23"; +LOCATE COMP "MAin[1]" SITE "38"; +LOCATE COMP "MAin[2]" SITE "37"; +LOCATE COMP "MAin[3]" SITE "47"; +LOCATE COMP "MAin[4]" SITE "46"; +LOCATE COMP "MAin[5]" SITE "45"; +LOCATE COMP "MAin[6]" SITE "49"; +LOCATE COMP "MAin[7]" SITE "44"; +LOCATE COMP "MAin[8]" SITE "50"; +LOCATE COMP "MAin[9]" SITE "51"; +LOCATE COMP "PHI2" SITE "39"; +LOCATE COMP "RA[0]" SITE "98"; +LOCATE COMP "RA[10]" SITE "87"; +LOCATE COMP "RA[11]" SITE "79"; +LOCATE COMP "RA[1]" SITE "89"; +LOCATE COMP "RA[2]" SITE "94"; +LOCATE COMP "RA[3]" SITE "97"; +LOCATE COMP "RA[4]" SITE "99"; +LOCATE COMP "RA[5]" SITE "95"; +LOCATE COMP "RA[6]" SITE "91"; +LOCATE COMP "RA[7]" SITE "100"; +LOCATE COMP "RA[8]" SITE "96"; +LOCATE COMP "RA[9]" SITE "85"; +LOCATE COMP "RBA[0]" SITE "63"; +LOCATE COMP "RBA[1]" SITE "83"; +LOCATE COMP "RCKE" SITE "82"; +LOCATE COMP "RCLK" SITE "86"; +LOCATE COMP "RDQMH" SITE "76"; +LOCATE COMP "RDQML" SITE "61"; +LOCATE COMP "RD[0]" SITE "64"; +LOCATE COMP "RD[1]" SITE "65"; +LOCATE COMP "RD[2]" SITE "66"; +LOCATE COMP "RD[3]" SITE "67"; +LOCATE COMP "RD[4]" SITE "68"; +LOCATE COMP "RD[5]" SITE "69"; +LOCATE COMP "RD[6]" SITE "70"; +LOCATE COMP "RD[7]" SITE "71"; +LOCATE COMP "UFMCLK" SITE "58"; +LOCATE COMP "UFMSDI" SITE "56"; +LOCATE COMP "UFMSDO" SITE "55"; +LOCATE COMP "nCCAS" SITE "27"; +LOCATE COMP "nCRAS" SITE "43"; +LOCATE COMP "nFWE" SITE "22"; +LOCATE COMP "nRCAS" SITE "78"; +LOCATE COMP "nRCS" SITE "77"; +LOCATE COMP "nRRAS" SITE "73"; +LOCATE COMP "nRWE" SITE "72"; +LOCATE COMP "nUFMCS" SITE "53"; + + + + + +PAR: Place And Route Diamond (64-bit) 3.12.0.240.2. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Mon Aug 16 21:32:33 2021 + diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.par b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.par new file mode 100644 index 0000000..5d8ae58 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.par @@ -0,0 +1,211 @@ + +Lattice Place and Route Report for Design "RAM2GS_LCMXO256C_impl1_map.ncd" +Mon Aug 16 21:32:27 2021 + +PAR: Place And Route Diamond (64-bit) 3.12.0.240.2. +Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir/5_1.ncd RAM2GS_LCMXO256C_impl1.prf +Preference file: RAM2GS_LCMXO256C_impl1.prf. +Placement level-cost: 5-1. +Routing Iterations: 6 + +Loading design for application par from file RAM2GS_LCMXO256C_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 3 +Loading device for application par from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +License checked out. + + +Ignore Preference Error(s): True +Device utilization summary: + + PIO (prelim) 67/79 84% used + 67/78 85% bonded + SLICE 65/128 50% used + + + +Number of Signals: 252 +Number of Connections: 618 + +Pin Constraint Summary: + 67 out of 67 pins locked (100% locked). + +The following 4 signals are selected to use the primary clock routing resources: + RCLK_c (driver: RCLK, clk load #: 39) + PHI2_c (driver: PHI2, clk load #: 13) + nCCAS_c (driver: nCCAS, clk load #: 4) + nCRAS_c (driver: nCRAS, clk load #: 7) + +No signal is selected as secondary clock. + +No signal is selected as Global Set/Reset. +Starting Placer Phase 0. +........ +Finished Placer Phase 0. REAL time: 0 secs + +Starting Placer Phase 1. +............... +Placer score = 586066. +Finished Placer Phase 1. REAL time: 6 secs + +Starting Placer Phase 2. +. +Placer score = 584668 +Finished Placer Phase 2. REAL time: 6 secs + + +------------------ Clock Report ------------------ + +Global Clock Resources: + CLK_PIN : 1 out of 4 (25%) + General PIO: 3 out of 80 (3%) + +Global Clocks: + PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT4A)", clk load = 39 + PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB3D)", clk load = 13 + PRIMARY "nCCAS_c" from comp "nCCAS" on PIO site "27 (PL9B)", clk load = 4 + PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB4A)", clk load = 7 + + PRIMARY : 4 out of 4 (100%) + SECONDARY: 0 out of 4 (0%) + +--------------- End of Clock Report --------------- + + +I/O Usage Summary (final): + 67 out of 79 (84.8%) PIO sites used. + 67 out of 78 (85.9%) bonded PIO sites used. + Number of PIO comps: 67; differential: 0. + Number of Vref pins used: 0. + +I/O Bank Usage Summary: ++----------+----------------+------------+------------+------------+ +| I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 | ++----------+----------------+------------+------------+------------+ +| 0 | 36 / 41 ( 87%) | 3.3V | - | - | +| 1 | 31 / 37 ( 83%) | 3.3V | - | - | ++----------+----------------+------------+------------+------------+ + +Total placer CPU time: 6 secs + +Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd. + +0 connections routed; 618 unrouted. +Starting router resource preassignment +WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew. +WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew. +WARNING - par: The driver of primary clock net nCCAS_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew. + +Completed router resource preassignment. Real time: 6 secs + +Start NBR router at 21:32:33 08/16/21 + +***************************************************************** +Info: NBR allows conflicts(one node used by more than one signal) + in the earlier iterations. In each iteration, it tries to + solve the conflicts while keeping the critical connections + routed as short as possible. The routing process is said to + be completed when no conflicts exist and all connections + are routed. +Note: NBR uses a different method to calculate timing slacks. The + worst slack and total negative slack may not be the same as + that in TRCE report. You should always run TRCE to verify + your design. +***************************************************************** + +Start NBR special constraint process at 21:32:33 08/16/21 + +Start NBR section for initial routing at 21:32:33 08/16/21 +Level 1, iteration 1 +0(0.00%) conflict; 535(86.57%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack: 2.084ns/0.000ns; real time: 6 secs +Level 2, iteration 1 +0(0.00%) conflict; 535(86.57%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack: 2.084ns/0.000ns; real time: 6 secs +Level 3, iteration 1 +0(0.00%) conflict; 509(82.36%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack: 2.038ns/0.000ns; real time: 6 secs +Level 4, iteration 1 +23(0.19%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 2.023ns/0.000ns; real time: 6 secs + +Info: Initial congestion level at 75% usage is 0 +Info: Initial congestion area at 75% usage is 0 (0.00%) + +Start NBR section for normal routing at 21:32:33 08/16/21 +Level 1, iteration 1 +0(0.00%) conflict; 24(3.88%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack: 2.023ns/0.000ns; real time: 6 secs +Level 4, iteration 1 +8(0.07%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 2.023ns/0.000ns; real time: 6 secs +Level 4, iteration 2 +4(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 2.023ns/0.000ns; real time: 6 secs +Level 4, iteration 3 +0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 2.023ns/0.000ns; real time: 6 secs + +Start NBR section for setup/hold timing optimization with effort level 3 at 21:32:33 08/16/21 + +Start NBR section for re-routing at 21:32:33 08/16/21 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 2.023ns/0.000ns; real time: 6 secs + +Start NBR section for post-routing at 21:32:33 08/16/21 + +End NBR router with 0 unrouted connection + +NBR Summary +----------- + Number of unrouted connections : 0 (0.00%) + Number of connections with timing violations : 0 (0.00%) + Estimated worst slack : 2.023ns + Timing score : 0 +----------- +Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. + + + +Total CPU time 6 secs +Total REAL time: 7 secs +Completely routed. +End of route. 618 routed (100.00%); 0 unrouted. + +Hold time timing score: 0, hold timing errors: 0 + +Timing score: 0 + +Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd. + + +All signals are completely routed. + + +PAR_SUMMARY::Run status = Completed +PAR_SUMMARY::Number of unrouted conns = 0 +PAR_SUMMARY::Worst slack> = 2.023 +PAR_SUMMARY::Timing score> = 0.000 +PAR_SUMMARY::Worst slack> = 0.339 +PAR_SUMMARY::Timing score> = 0.000 +PAR_SUMMARY::Number of errors = 0 + +Total CPU time to completion: 6 secs +Total REAL time to completion: 7 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1_par.asd b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1_par.asd new file mode 100644 index 0000000..6e5f093 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1_par.asd @@ -0,0 +1,33 @@ +[ActiveSupport PAR] +; Global primary clocks +GLOBAL_PRIMARY_USED = 4; +; Global primary clock #0 +GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c; +GLOBAL_PRIMARY_0_DRIVERTYPE = CLK_PIN; +GLOBAL_PRIMARY_0_LOADNUM = 39; +; Global primary clock #1 +GLOBAL_PRIMARY_1_SIGNALNAME = PHI2_c; +GLOBAL_PRIMARY_1_DRIVERTYPE = PIO; +GLOBAL_PRIMARY_1_LOADNUM = 13; +; Global primary clock #2 +GLOBAL_PRIMARY_2_SIGNALNAME = nCCAS_c; +GLOBAL_PRIMARY_2_DRIVERTYPE = PIO; +GLOBAL_PRIMARY_2_LOADNUM = 4; +; Global primary clock #3 +GLOBAL_PRIMARY_3_SIGNALNAME = nCRAS_c; +GLOBAL_PRIMARY_3_DRIVERTYPE = PIO; +GLOBAL_PRIMARY_3_LOADNUM = 7; +; # of global secondary clocks +GLOBAL_SECONDARY_USED = 0; +; I/O Bank 0 Usage +BANK_0_USED = 36; +BANK_0_AVAIL = 41; +BANK_0_VCCIO = 3.3V; +BANK_0_VREF1 = NA; +BANK_0_VREF2 = NA; +; I/O Bank 1 Usage +BANK_1_USED = 31; +BANK_1_AVAIL = 37; +BANK_1_VCCIO = 3.3V; +BANK_1_VREF1 = NA; +BANK_1_VREF2 = NA; diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/RAM2GS_LCMXO256C_impl1.par b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/RAM2GS_LCMXO256C_impl1.par new file mode 100644 index 0000000..feb14ae --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/RAM2GS_LCMXO256C_impl1.par @@ -0,0 +1,28 @@ +PAR: Place And Route Diamond (64-bit) 3.12.0.240.2. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Mon Aug 16 21:32:27 2021 + +C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO256C_impl1.p2t +RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir +RAM2GS_LCMXO256C_impl1.prf -gui -msgset +C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml + + +Preference file: RAM2GS_LCMXO256C_impl1.prf. + +Level/ Number Worst Timing Worst Timing Run NCD +Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status +---------- -------- ----- ------ ----------- ----------- ---- ------ +5_1 * 0 2.023 0 0.339 0 07 Completed + +* : Design saved. + +Total (real) run time for 1-seed: 7 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.drc b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.drc new file mode 100644 index 0000000..ec074a2 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.drc @@ -0,0 +1 @@ +DRC detected 0 errors and 0 warnings. diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.jed b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.jed new file mode 100644 index 0000000..b3a7f61 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.jed @@ -0,0 +1,977 @@ + +* +NOTE JEDEC CREATED BY: Lattice Semiconductor Diamond Deployment Tool 3.12* +NOTE Version: Diamond (64-bit) 3.12.0.240.2* +NOTE Readback: Off* +NOTE Security: Off* +NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation * +NOTE All Rights Reserved * +NOTE DATE CREATED: Mon Aug 16 21:36:26 2021 * +NOTE DESIGN NAME: RAM2GS * +NOTE DEVICE NAME: LCMXO256C-3TQFP100 * +NOTE PIN ASSIGNMENTS * +NOTE PINS RD[7] : 71 : inout * +NOTE PINS RD[6] : 70 : inout * +NOTE PINS RD[5] : 69 : inout * +NOTE PINS RD[4] : 68 : inout * +NOTE PINS RD[3] : 67 : inout * +NOTE PINS RD[2] : 66 : inout * +NOTE PINS RD[1] : 65 : inout * +NOTE PINS RD[0] : 64 : inout * +NOTE PINS Dout[7] : 3 : out * +NOTE PINS Dout[6] : 2 : out * +NOTE PINS Dout[5] : 5 : out * +NOTE PINS Dout[4] : 4 : out * +NOTE PINS Dout[3] : 6 : out * +NOTE PINS Dout[2] : 8 : out * +NOTE PINS Dout[1] : 7 : out * +NOTE PINS Dout[0] : 1 : out * +NOTE PINS LED : 57 : out * +NOTE PINS RBA[1] : 83 : out * +NOTE PINS RBA[0] : 63 : out * +NOTE PINS RA[11] : 79 : out * +NOTE PINS RA[10] : 87 : out * +NOTE PINS RA[9] : 85 : out * +NOTE PINS RA[8] : 96 : out * +NOTE PINS RA[7] : 100 : out * +NOTE PINS RA[6] : 91 : out * +NOTE PINS RA[5] : 95 : out * +NOTE PINS RA[4] : 99 : out * +NOTE PINS RA[3] : 97 : out * +NOTE PINS RA[2] : 94 : out * +NOTE PINS RA[1] : 89 : out * +NOTE PINS RA[0] : 98 : out * +NOTE PINS nRCS : 77 : out * +NOTE PINS RCKE : 82 : out * +NOTE PINS nRWE : 72 : out * +NOTE PINS nRRAS : 73 : out * +NOTE PINS nRCAS : 78 : out * +NOTE PINS RDQMH : 76 : out * +NOTE PINS RDQML : 61 : out * +NOTE PINS nUFMCS : 53 : out * +NOTE PINS UFMCLK : 58 : out * +NOTE PINS UFMSDI : 56 : out * +NOTE PINS PHI2 : 39 : in * +NOTE PINS MAin[9] : 51 : in * +NOTE PINS MAin[8] : 50 : in * +NOTE PINS MAin[7] : 44 : in * +NOTE PINS MAin[6] : 49 : in * +NOTE PINS MAin[5] : 45 : in * +NOTE PINS MAin[4] : 46 : in * +NOTE PINS MAin[3] : 47 : in * +NOTE PINS MAin[2] : 37 : in * +NOTE PINS MAin[1] : 38 : in * +NOTE PINS MAin[0] : 23 : in * +NOTE PINS CROW[1] : 34 : in * +NOTE PINS CROW[0] : 32 : in * +NOTE PINS Din[7] : 19 : in * +NOTE PINS Din[6] : 20 : in * +NOTE PINS Din[5] : 17 : in * +NOTE PINS Din[4] : 18 : in * +NOTE PINS Din[3] : 16 : in * +NOTE PINS Din[2] : 14 : in * +NOTE PINS Din[1] : 15 : in * +NOTE PINS Din[0] : 21 : in * +NOTE PINS nCCAS : 27 : in * +NOTE PINS nCRAS : 43 : in * +NOTE PINS nFWE : 22 : in * +NOTE PINS RCLK : 86 : in * +NOTE PINS UFMSDO : 55 : in * +NOTE CONFIGURATION MODE: NONE * +NOTE COMPRESSION: off * + + +QF56640* +G0* +F0* +L00000 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+N User Electronic Signature Data* +U00000000000000000000000000000000* +2290 diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.log b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.log new file mode 100644 index 0000000..d0353b8 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.log @@ -0,0 +1,4 @@ +---- MParTrce Tool Log File ---- + +==== Par Standard Out ==== +==== End of Par Standard Out ==== diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.lpf b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.lpf new file mode 100644 index 0000000..2743d95 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.lpf @@ -0,0 +1,4 @@ +#BLOCK ASYNCPATHS; +#BLOCK RESETPATHS; + +#FREQUENCY 200.000000 MHz; diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.lsedata b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.lsedata new file mode 100644 index 0000000..f0b54bc --- /dev/null +++ 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+ + + + diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mrp b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mrp new file mode 100644 index 0000000..d38f4ce --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mrp @@ -0,0 +1,402 @@ + + Lattice Mapping Report File for Design Module 'RAM2GS' + + +Design Information +------------------ + +Command line: map -a MachXO -p LCMXO256C -t TQFP100 -s 3 -oc Commercial + RAM2GS_LCMXO256C_impl1.ngd -o RAM2GS_LCMXO256C_impl1_map.ncd -pr + RAM2GS_LCMXO256C_impl1.prf -mp RAM2GS_LCMXO256C_impl1.mrp -lpf C:/Users/Dog + /Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1. + lpf -lpf C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/RAM2GS_L + CMXO256C.lpf -c 0 -gui -msgset + C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml +Target Vendor: LATTICE +Target Device: LCMXO256CTQFP100 +Target Performance: 3 +Mapper: mj5g00, version: Diamond (64-bit) 3.12.0.240.2 +Mapped on: 08/16/21 21:32:26 + +Design Summary +-------------- + + Number of PFU registers: 102 out of 256 (40%) + Number of SLICEs: 65 out of 128 (51%) + SLICEs as Logic/ROM: 65 out of 128 (51%) + SLICEs as RAM: 0 out of 64 (0%) + SLICEs as Carry: 9 out of 128 (7%) + Number of LUT4s: 129 out of 256 (50%) + Number used as logic LUTs: 111 + Number used as distributed RAM: 0 + Number used as ripple logic: 18 + Number used as shift registers: 0 + Number of external PIOs: 67 out of 78 (86%) + Number of GSRs: 0 out of 1 (0%) + JTAG used : No + Readback used : No + Oscillator used : No + Startup used : No + Number of TSALL: 0 out of 1 (0%) + Notes:- + 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of + distributed RAMs) + 2*(Number of ripple logic) + 2. Number of logic LUT4s does not include count of distributed RAM and + ripple logic. + Number of clocks: 4 + Net RCLK_c: 39 loads, 39 rising, 0 falling (Driver: PIO RCLK ) + Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 ) + Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS ) + Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS ) + Number of Clock Enables: 13 + Net PHI2_N_114_enable_7: 2 loads, 2 LSLICEs + Net RCLK_c_enable_6: 1 loads, 1 LSLICEs + Net RCLK_c_enable_4: 3 loads, 3 LSLICEs + Net RCLK_c_enable_24: 2 loads, 2 LSLICEs + Net RCLK_c_enable_3: 1 loads, 1 LSLICEs + Net RCLK_c_enable_7: 1 loads, 1 LSLICEs + Net RCLK_c_enable_23: 8 loads, 8 LSLICEs + Net PHI2_N_114_enable_1: 1 loads, 1 LSLICEs + Net PHI2_N_114_enable_8: 1 loads, 1 LSLICEs + Net PHI2_N_114_enable_6: 2 loads, 2 LSLICEs + Net PHI2_N_114_enable_2: 1 loads, 1 LSLICEs + + Page 1 + + + + +Design: RAM2GS Date: 08/16/21 21:32:26 + +Design Summary (cont) +--------------------- + Net RCLK_c_enable_25: 1 loads, 1 LSLICEs + Net Ready_N_268: 1 loads, 1 LSLICEs + Number of LSRs: 9 + Net RASr2: 1 loads, 1 LSLICEs + Net C1Submitted_N_225: 2 loads, 2 LSLICEs + Net n2299: 1 loads, 1 LSLICEs + Net nRowColSel_N_35: 1 loads, 1 LSLICEs + Net nRowColSel_N_34: 1 loads, 1 LSLICEs + Net LEDEN_N_88: 1 loads, 1 LSLICEs + Net n2291: 2 loads, 2 LSLICEs + Net Ready: 7 loads, 7 LSLICEs + Net nRWE_N_173: 1 loads, 1 LSLICEs + Number of nets driven by tri-state buffers: 0 + Top 10 highest fanout non-clock nets: + Net Ready: 19 loads + Net InitReady: 17 loads + Net RASr2: 16 loads + Net nRowColSel_N_35: 14 loads + Net nRowColSel: 13 loads + Net Din_c_6: 9 loads + Net MAin_c_1: 9 loads + Net Din_c_5: 8 loads + Net FS_11: 8 loads + Net MAin_c_0: 8 loads + + + + + Number of warnings: 0 + Number of errors: 0 + + +Design Errors/Warnings +---------------------- + + No errors or warnings present. + +IO (PIO) Attributes +------------------- + ++---------------------+-----------+-----------+------------+------------+ +| IO Name | Direction | Levelmode | IO | FIXEDDELAY | +| | | IO_TYPE | Register | | ++---------------------+-----------+-----------+------------+------------+ +| RD[7] | BIDIR | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RD[6] | BIDIR | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RD[5] | BIDIR | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RD[4] | BIDIR | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RD[3] | BIDIR | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RD[2] | BIDIR | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ + + Page 2 + + + + +Design: RAM2GS Date: 08/16/21 21:32:26 + +IO (PIO) Attributes (cont) +-------------------------- +| RD[1] | BIDIR | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RD[0] | BIDIR | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[7] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[6] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[5] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[4] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[3] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[2] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[1] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[0] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| LED | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RBA[1] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RBA[0] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[11] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[10] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[9] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[8] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[7] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[6] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[5] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[4] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[3] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[2] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[1] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[0] | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| nRCS | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RCKE | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| nRWE | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ + + Page 3 + + + + +Design: RAM2GS Date: 08/16/21 21:32:26 + +IO (PIO) Attributes (cont) +-------------------------- +| nRRAS | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| nRCAS | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RDQMH | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RDQML | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| nUFMCS | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| UFMCLK | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| UFMSDI | OUTPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| PHI2 | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[9] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[8] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[7] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[6] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[5] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[4] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[3] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[2] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[1] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[0] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| CROW[1] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| CROW[0] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[7] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[6] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[5] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[4] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[3] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[2] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[1] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[0] | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ + + Page 4 + + + + +Design: RAM2GS Date: 08/16/21 21:32:26 + +IO (PIO) Attributes (cont) +-------------------------- +| nCCAS | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| nCRAS | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| nFWE | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RCLK | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ +| UFMSDO | INPUT | LVTTL33 | | | ++---------------------+-----------+-----------+------------+------------+ + +Removed logic +------------- + +Block i2 undriven or does not drive anything - clipped. +Block GSR_INST undriven or does not drive anything - clipped. +Signal PHI2_N_114 was merged into signal PHI2_c +Signal nCRAS_N_9 was merged into signal nCRAS_c +Signal nCCAS_N_3 was merged into signal nCCAS_c +Signal n2302 was merged into signal nRowColSel_N_35 +Signal nRWE_N_172 was merged into signal nRWE_N_173 +Signal n2307 was merged into signal Ready +Signal RASr2_N_63 was merged into signal RASr2 +Signal n1377 was merged into signal nRowColSel_N_34 +Signal n2306 was merged into signal nFWE_c +Signal UFMSDO_N_74 was merged into signal UFMSDO_c +Signal GND_net undriven or does not drive anything - clipped. +Signal VCC_net undriven or does not drive anything - clipped. +Signal FS_577_add_4_14/CO0 undriven or does not drive anything - clipped. +Signal FS_577_add_4_16/CO0 undriven or does not drive anything - clipped. +Signal FS_577_add_4_12/CO0 undriven or does not drive anything - clipped. +Signal FS_577_add_4_2/CO0 undriven or does not drive anything - clipped. +Signal FS_577_add_4_4/CO0 undriven or does not drive anything - clipped. +Signal FS_577_add_4_6/CO0 undriven or does not drive anything - clipped. +Signal FS_577_add_4_18/CO1 undriven or does not drive anything - clipped. +Signal FS_577_add_4_18/CO0 undriven or does not drive anything - clipped. +Signal FS_577_add_4_8/CO0 undriven or does not drive anything - clipped. +Signal FS_577_add_4_10/CO0 undriven or does not drive anything - clipped. +Block i1962 was optimized away. +Block i1961 was optimized away. +Block i1963 was optimized away. +Block i1070_1_lut_rep_25 was optimized away. +Block nRWE_I_49_1_lut was optimized away. +Block i604_1_lut_rep_30 was optimized away. +Block RASr2_I_0_1_lut was optimized away. +Block i1069_1_lut was optimized away. +Block i1_1_lut_rep_29 was optimized away. +Block UFMSDO_I_0_1_lut was optimized away. +Block i1 was optimized away. + +Run Time and Memory Usage +------------------------- + + Total CPU Time: 0 secs + Total REAL Time: 0 secs + Peak Memory Usage: 29 MB + + Page 5 + + + + +Design: RAM2GS Date: 08/16/21 21:32:26 + +Run Time and Memory Usage (cont) +-------------------------------- + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Page 6 + + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. + Copyright (c) 1995 AT&T Corp. All rights reserved. + Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. + Copyright (c) 2001 Agere Systems All rights reserved. + Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights + reserved. diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mt b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mt new file mode 100644 index 0000000..2d70ad1 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mt @@ -0,0 +1,9 @@ +-v +1 + + +-gt + + +-mapchkpnt 0 +-sethld diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.n2e b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.n2e new file mode 100644 index 0000000..c5da0e1 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.n2e @@ -0,0 +1,574 @@ + +comp 0: SLICE_0 (FSLICE) + +comp 1: SLICE_1 (FSLICE) + +comp 2: SLICE_2 (FSLICE) + +comp 3: SLICE_3 (FSLICE) + +comp 4: SLICE_4 (FSLICE) + +comp 5: SLICE_5 (FSLICE) + +comp 6: SLICE_6 (FSLICE) + +comp 7: SLICE_7 (FSLICE) + +comp 8: SLICE_8 (FSLICE) + +comp 9: SLICE_9 (FSLICE) +n1361 = ((ADSubmitted*(~MAin_c_1+n2290))+ADSubmitted_N_234) +ADSubmitted.D = n1361 +ADSubmitted.CLK = ~PHI2_c +ADSubmitted.SP = VCC +ADSubmitted.LSR = C1Submitted_N_225 +n2080 = (~MAin_c_0*(~ADSubmitted*n2122)) + +comp 10: SLICE_14 (FSLICE) +n2386 = GND +C1Submitted.D = n2386 +C1Submitted.CLK = ~PHI2_c +C1Submitted.SP = PHI2_N_114_enable_1 +C1Submitted.LSR = C1Submitted_N_225 +n2098 = (MAin_c_0*(~C1Submitted*(MAin_c_1*n2108))) + +comp 11: SLICE_18 (FSLICE) +CmdEnable_N_236 = (ADSubmitted_N_234+C1Submitted_N_225) +CmdEnable.D = CmdEnable_N_236 +CmdEnable.CLK = ~PHI2_c +CmdEnable.SP = PHI2_N_114_enable_8 +CmdEnable.LSR = GND +XOR8MEG_N_112 = (~n2290*(CmdEnable*(MAin_c_0*~MAin_c_1))) + +comp 12: SLICE_19 (FSLICE) +n2387\000/BUF1 = VCC +CmdSubmitted.D = n2387\000/BUF1 +CmdSubmitted.CLK = ~PHI2_c +CmdSubmitted.SP = PHI2_N_114_enable_6 +CmdSubmitted.LSR = GND +n2308 = (~PHI2r2*(CmdSubmitted*PHI2r3)) + +comp 13: SLICE_23 (FSLICE) +Cmdn8MEGEN_N_248 = (~n2296*(~Din_c_5*~Din_c_0+Din_c_5*n8MEGEN)+n2296*n8MEGEN) +Cmdn8MEGEN.D = Cmdn8MEGEN_N_248 +Cmdn8MEGEN.CLK = ~PHI2_c +Cmdn8MEGEN.SP = PHI2_N_114_enable_6 +Cmdn8MEGEN.LSR = GND +n2296 = (~Din_c_4+(Din_c_6+Din_c_7)) + +comp 14: SLICE_25 (FSLICE) +n2387 = VCC +InitReady.D = n2387 +InitReady.CLK = RCLK_c +InitReady.SP = RCLK_c_enable_6 +InitReady.LSR = GND +RCLK_c_enable_24 = (~InitReady+(~PHI2r2*(CmdSubmitted*PHI2r3))) + +comp 15: SLICE_31 (FSLICE) +RA11_N_180 = (~n8MEGEN*(XOR8MEG@Din_c_6)+n8MEGEN*XOR8MEG) +RA_c.D = RA11_N_180 +RA_c.CLK = PHI2_c +RA_c.SP = VCC +RA_c.LSR = ~Ready +n2385 = (Din_c_6+Din_c_7) + +comp 16: SLICE_33 (FSLICE) +RCKEEN_N_115 = (~Ready*InitReady+Ready*RCKEEN_N_116) +RCKEEN.D = RCKEEN_N_115 +RCKEEN.CLK = RCLK_c +RCKEEN.SP = RCLK_c_enable_4 +RCKEEN.LSR = GND +RCLK_c_enable_7 = (~n2119*(InitReady*n2308)+n2119*(~InitReady*~FS_5+InitReady*n2308)) + +comp 17: SLICE_34 (FSLICE) +RCKE_N_128 = (~RASr3*(~RASr2*(RCKEEN*RASr)+RASr2*RCKEEN)+RASr3*(~RASr2+RCKEEN)) +RCKE_c.D = RCKE_N_128 +RCKE_c.CLK = RCLK_c +RCKE_c.SP = VCC +RCKE_c.LSR = GND +nRWE_N_178 = (~RCKE_c+RASr2) +CASr2.D = CASr +CASr2.CLK = RCLK_c +CASr2.SP = VCC +CASr2.LSR = GND + +comp 18: SLICE_35 (FSLICE) +n2387\001/BUF1 = VCC +Ready.D = n2387\001/BUF1 +Ready.CLK = RCLK_c +Ready.SP = Ready_N_268 +Ready.LSR = GND +RCLK_c_enable_23 = (InitReady*(RASr2*(nRowColSel_N_35*~Ready))) + +comp 19: SLICE_42 (FSLICE) +UFMCLK_N_212 = (~n2076*(~InitReady*FS_4+InitReady*CmdUFMCLK)+n2076*(InitReady*CmdUFMCLK)) +UFMCLK_c.D = UFMCLK_N_212 +UFMCLK_c.CLK = RCLK_c +UFMCLK_c.SP = RCLK_c_enable_24 +UFMCLK_c.LSR = n2291 +RCLK_c_enable_6 = (n2076*FS_10) + +comp 20: SLICE_43 (FSLICE) +UFMSDI_N_219 = (~InitReady*n1895+InitReady*CmdUFMSDI) +UFMSDI_c.D = UFMSDI_N_219 +UFMSDI_c.CLK = RCLK_c +UFMSDI_c.SP = RCLK_c_enable_24 +UFMSDI_c.LSR = n2291 +n1895 = (~FS_10*(n2103*(~n2293*FS_6))) + +comp 21: SLICE_55 (FSLICE) +n2128 = (((n2297+n2301)+nRCAS_N_161)+Ready) +n980.D = n2128 +n980.CLK = RCLK_c +n980.SP = VCC +n980.LSR = ~nRWE_N_173 +n2301 = (~InitReady+~RASr2) + +comp 22: SLICE_56 (FSLICE) +n8MEGEN_N_94 = (~n4*(~FS_10*Cmdn8MEGEN+FS_10*~UFMSDO_c)+n4*Cmdn8MEGEN) +n8MEGEN.D = n8MEGEN_N_94 +n8MEGEN.CLK = RCLK_c +n8MEGEN.SP = RCLK_c_enable_7 +n8MEGEN.LSR = GND +n4 = ((~FS_11+n2300)+InitReady) + +comp 23: SLICE_58 (FSLICE) +nRCAS_N_157 = (~nRowColSel_N_35*(~n2117+~Ready)+nRowColSel_N_35*n2287) +nRCAS_c.D = nRCAS_N_157 +nRCAS_c.CLK = RCLK_c +nRCAS_c.SP = RCLK_c_enable_4 +nRCAS_c.LSR = GND +n2287 = (~n2248*(~Ready*~RASr2+Ready*(~RASr2+~CBR))+n2248*(~Ready+(~RASr2+~CBR))) + +comp 24: SLICE_60 (FSLICE) +nRCS_N_132 = (((~RCKE_c*nRowColSel_N_35*~RASr2)+(~n2117*~nRowColSel_N_35))*Ready)+((~InitReady+nRCS_N_135+~RASr2+~nRowColSel_N_35)*~Ready) +nRCS_c.D = nRCS_N_132 +nRCS_c.CLK = RCLK_c +nRCS_c.SP = RCLK_c_enable_4 +nRCS_c.LSR = GND + +comp 25: SLICE_61 (FSLICE) +n33 = (~Ready*(n2244+n2297)+Ready*(n2244+n18)) +nRRAS_c.D = n33 +nRRAS_c.CLK = RCLK_c +nRRAS_c.SP = VCC +nRRAS_c.LSR = GND +n50 = ((nRowColSel_N_33+nRRAS_c)+nRowColSel_N_32) +RASr.D = ~nCRAS_c +RASr.CLK = RCLK_c +RASr.SP = VCC +RASr.LSR = GND + +comp 26: SLICE_62 (FSLICE) +n1369 = (~n2308*nUFMCS_c+n2308*~CmdUFMCS) +nRWE_N_173.D = n705 +nRWE_N_173.CLK = RCLK_c +nRWE_N_173.SP = RCLK_c_enable_23 +nRWE_N_173.LSR = GND +nRCS_N_135.D = Ready_N_272 +nRCS_N_135.CLK = RCLK_c +nRCS_N_135.SP = RCLK_c_enable_23 +nRCS_N_135.LSR = GND + +comp 27: SLICE_63 (FSLICE) +nRWE_N_167 = (~n2292*(~Ready*~n2164+Ready*nRWE_N_174)+n2292*(~Ready+nRWE_N_174)) +nRWE_c.D = nRWE_N_167 +nRWE_c.CLK = RCLK_c +nRWE_c.SP = RCLK_c_enable_3 +nRWE_c.LSR = GND +nRWE_N_174 = (~nRowColSel_N_35*(~n1+n1627)+nRowColSel_N_35*nRWE_N_178) + +comp 28: SLICE_64 (FSLICE) +n1368 = (~nRowColSel_N_32*(nRowColSel+n1627)+nRowColSel_N_32*(~nRowColSel_N_28+n1627)) +nRowColSel.D = n1368 +nRowColSel.CLK = RCLK_c +nRowColSel.SP = VCC +nRowColSel.LSR = n2299 +RA_c_4 = (~nRowColSel*RowA_4+nRowColSel*MAin_c_4) + +comp 29: SLICE_65 (FSLICE) +n1628 = (nRowColSel_N_32+nRowColSel_N_33) +nRowColSel_N_32.D = n1628 +nRowColSel_N_32.CLK = RCLK_c +nRowColSel_N_32.SP = VCC +nRowColSel_N_32.LSR = ~RASr2 +RCLK_c_enable_4 = (((nRowColSel_N_32+n2299)+nRowColSel_N_34)+nRowColSel_N_33) + +comp 30: SLICE_66 (FSLICE) +n1135 = (RASr2*~nRowColSel_N_32) +nRowColSel_N_33.D = n1135 +nRowColSel_N_33.CLK = RCLK_c +nRowColSel_N_33.SP = VCC +nRowColSel_N_33.LSR = ~nRowColSel_N_34 +n2117 = (~nRowColSel_N_33*(n1*~nRowColSel_N_34)+nRowColSel_N_33*(~n2304*~nRowColSel_N_34)) + +comp 31: SLICE_67 (FSLICE) +LED_N_90 = (~LEDEN+nCRAS_c) +nRowColSel_N_34.D = n1135 +nRowColSel_N_34.CLK = RCLK_c +nRowColSel_N_34.SP = VCC +nRowColSel_N_34.LSR = ~nRowColSel_N_35 +n2154 = (MAin_c_4*Bank_7) + +comp 32: SLICE_68 (FSLICE) +n2168 = (FS_3*(FS_2*(FS_0*FS_1))) +nRowColSel_N_35.D = ~RASr2 +nRowColSel_N_35.CLK = RCLK_c +nRowColSel_N_35.SP = VCC +nRowColSel_N_35.LSR = GND +n962 = (nCCAS_c+nFWE_c) +CASr3.D = CASr2 +CASr3.CLK = RCLK_c +CASr3.SP = VCC +CASr3.LSR = GND + +comp 33: SLICE_69 (FSLICE) +n1348 = (~InitReady*n2076+InitReady*n1369) +nUFMCS_c.D = n1348 +nUFMCS_c.CLK = RCLK_c +nUFMCS_c.SP = VCC +nUFMCS_c.LSR = LEDEN_N_88 +n2076 = (FS_17*(FS_11*(n12_adj_2*FS_15))) + +comp 34: i1912/SLICE_70 (FSLICE) +n2244 = (((~RCKE_c*nRowColSel_N_35*~RASr2)+(~nRowColSel_N_35*n50))*Ready)+(((~nRowColSel_N_35*n50)+~InitReady+~RASr2)*~Ready) + +comp 35: RCKEEN_I_0_419/SLICE_71 (FSLICE) +RCKEEN_N_116 = (((~FWEr*~CBR)+~RASr2)*nRowColSel_N_35)+(((FWEr*n11_adj_3*~CBR)+(nRowColSel_N_34*~CBR))*~nRowColSel_N_35) + +comp 36: SLICE_72 (FSLICE) +PHI2_N_114_enable_7 = (Din_c_5*(~n2296*(n2298*XOR8MEG_N_112))) +n702.D = n703 +n702.CLK = RCLK_c +n702.SP = RCLK_c_enable_23 +n702.LSR = GND +n2298 = (((Din_c_6+Din_c_7)+Din_c_5)+Din_c_4) +n701.D = n702 +n701.CLK = RCLK_c +n701.SP = RCLK_c_enable_23 +n701.LSR = GND + +comp 37: SLICE_73 (FSLICE) +n11 = (~n2168+((~FS_11+n2300)+FS_6)) +n706.D = n707 +n706.CLK = RCLK_c +n706.SP = RCLK_c_enable_23 +n706.LSR = GND +n2300 = ((FS_16+n10)+FS_17) +n705.D = n706 +n705.CLK = RCLK_c +n705.SP = RCLK_c_enable_23 +n705.LSR = GND + +comp 38: SLICE_74 (FSLICE) +C1Submitted_N_225 = (~n2131*(~Din_c_2*(n2295*n2122))) +n710.D = n711 +n710.CLK = RCLK_c +n710.SP = RCLK_c_enable_23 +n710.LSR = GND +n2295 = (n2114*~nFWE_c) +n709.D = n710 +n709.CLK = RCLK_c +n709.SP = RCLK_c_enable_23 +n709.LSR = GND + +comp 39: SLICE_75 (FSLICE) +n2119 = (~n12*(~n11*(FS_10*n2294))) +n708.D = n709 +n708.CLK = RCLK_c +n708.SP = RCLK_c_enable_23 +n708.LSR = GND +RCLK_c_enable_25 = (n2119*(FS_5*~InitReady)) +n707.D = n708 +n707.CLK = RCLK_c +n707.SP = RCLK_c_enable_23 +n707.LSR = GND + +comp 40: SLICE_76 (FSLICE) +n2131 = ((~MAin_c_1+n1285)+MAin_c_0) +WRD_0.D = Din_c_0 +WRD_0.CLK = ~nCCAS_c +WRD_0.SP = VCC +WRD_0.LSR = GND +n1285 = (~MAin_c_5+(~n2170+(~Bank_3+n26))) +WRD_1.D = Din_c_1 +WRD_1.CLK = ~nCCAS_c +WRD_1.SP = VCC +WRD_1.LSR = GND + +comp 41: SLICE_77 (FSLICE) +PHI2_N_114_enable_8 = (~MAin_c_1*(~n2286*(~n2290*MAin_c_0))+MAin_c_1*(~n2286*~n2290)) +RowA_2.D = MAin_c_2 +RowA_2.CLK = ~nCRAS_c +RowA_2.SP = VCC +RowA_2.LSR = ~Ready +n2286 = (n2114*(~Din_c_2*n2080+Din_c_2*n2098)) +RowA_3.D = MAin_c_3 +RowA_3.CLK = ~nCRAS_c +RowA_3.SP = VCC +RowA_3.LSR = ~Ready + +comp 42: SLICE_78 (FSLICE) +n10 = (((FS_14+FS_13)+FS_12)+FS_15) +CASr.D = ~nCCAS_c +CASr.CLK = RCLK_c +CASr.SP = VCC +CASr.LSR = GND +n2294 = (((FS_16+n10)+FS_17)+FS_11) +PHI2r2.D = PHI2r +PHI2r2.CLK = RCLK_c +PHI2r2.SP = VCC +PHI2r2.LSR = GND + +comp 43: SLICE_79 (FSLICE) +n1627 = (nRowColSel_N_34+nRowColSel_N_33) +WRD_2.D = Din_c_2 +WRD_2.CLK = ~nCCAS_c +WRD_2.SP = VCC +WRD_2.LSR = GND +RCLK_c_enable_3 = (((~Ready+nRowColSel_N_32)+n1627)+nRowColSel_N_35) +WRD_3.D = Din_c_3 +WRD_3.CLK = ~nCCAS_c +WRD_3.SP = VCC +WRD_3.LSR = GND + +comp 44: SLICE_80 (FSLICE) +ADSubmitted_N_234 = (~n2289*(n4_adj_1*(MAin_c_0*n2108))) +WRD_6.D = Din_c_6 +WRD_6.CLK = ~nCCAS_c +WRD_6.SP = VCC +WRD_6.LSR = GND +n2289 = (~MAin_c_1+n1285) +WRD_7.D = Din_c_7 +WRD_7.CLK = ~nCCAS_c +WRD_7.SP = VCC +WRD_7.LSR = GND + +comp 45: SLICE_81 (FSLICE) +n4_adj_1 = (n2114*(Din_c_2*~nFWE_c)) +RowA_8.D = MAin_c_8 +RowA_8.CLK = ~nCRAS_c +RowA_8.SP = VCC +RowA_8.LSR = ~Ready +n2114 = (Din_c_7*(~Din_c_4*(~Din_c_1*Din_c_0))) +RowA_9.D = MAin_c_9 +RowA_9.CLK = ~nCRAS_c +RowA_9.SP = VCC +RowA_9.LSR = ~Ready + +comp 46: SLICE_82 (FSLICE) +n2166 = (Bank_6*(MAin_c_2*(Bank_5*Bank_0))) +RowA_0.D = MAin_c_0 +RowA_0.CLK = ~nCRAS_c +RowA_0.SP = VCC +RowA_0.LSR = ~Ready +n26 = (~MAin_c_6+(~n2154+(~n2166+Bank_2))) +RowA_1.D = MAin_c_1 +RowA_1.CLK = ~nCRAS_c +RowA_1.SP = VCC +RowA_1.LSR = ~Ready + +comp 47: SLICE_83 (FSLICE) +n2245 = (InitReady*(Ready_N_272*(~RASr2*nRowColSel_N_32))) +CmdUFMCLK.D = Din_c_1 +CmdUFMCLK.CLK = ~PHI2_c +CmdUFMCLK.SP = PHI2_N_114_enable_7 +CmdUFMCLK.LSR = GND +Ready_N_268 = (n2245+Ready) +CmdUFMCS.D = Din_c_2 +CmdUFMCS.CLK = ~PHI2_c +CmdUFMCS.SP = PHI2_N_114_enable_7 +CmdUFMCS.LSR = GND + +comp 48: SLICE_84 (FSLICE) +nRowColSel_N_28 = ((~FWEr+CASr3)+CBR) +nRCAS_N_161.D = nRCS_N_135 +nRCAS_N_161.CLK = RCLK_c +nRCAS_N_161.SP = RCLK_c_enable_23 +nRCAS_N_161.LSR = GND +n1 = (~CASr3*(CASr2*(FWEr*~CBR))) +n703.D = nRWE_N_173 +n703.CLK = RCLK_c +n703.SP = RCLK_c_enable_23 +n703.LSR = GND + +comp 49: SLICE_85 (FSLICE) +n12 = (((~FS_4+FS_9)+FS_8)+FS_7) +PHI2r3.D = PHI2r2 +PHI2r3.CLK = RCLK_c +PHI2r3.SP = VCC +PHI2r3.LSR = GND +n2103 = (~FS_9*(FS_7*~FS_8)+FS_9*(FS_5*(~FS_7*~FS_8))) +PHI2r.D = PHI2_c +PHI2r.CLK = RCLK_c +PHI2r.SP = VCC +PHI2r.LSR = GND + +comp 50: SLICE_86 (FSLICE) +n2291 = (~InitReady*(~n2300*~FS_11)) +RowA_6.D = MAin_c_6 +RowA_6.CLK = ~nCRAS_c +RowA_6.SP = VCC +RowA_6.LSR = ~Ready +LEDEN_N_88 = (~InitReady*(~FS_10*(~n2300*~FS_11))) +RowA_7.D = MAin_c_7 +RowA_7.CLK = ~nCRAS_c +RowA_7.SP = VCC +RowA_7.LSR = ~Ready + +comp 51: SLICE_87 (FSLICE) +n2122 = (~Din_c_5*(Din_c_6*~Din_c_3)) +Ready_N_272.D = n699 +Ready_N_272.CLK = RCLK_c +Ready_N_272.SP = RCLK_c_enable_23 +Ready_N_272.LSR = GND +n2108 = (Din_c_3*(Din_c_5*~Din_c_6)) +n711.D = nRCAS_N_161 +n711.CLK = RCLK_c +n711.SP = RCLK_c_enable_23 +n711.LSR = GND + +comp 52: SLICE_88 (FSLICE) +RDQMH_c = (~nRowColSel+MAin_c_9) +CmdUFMSDI.D = Din_c_0 +CmdUFMSDI.CLK = ~PHI2_c +CmdUFMSDI.SP = PHI2_N_114_enable_7 +CmdUFMSDI.LSR = GND +RA_c_9 = (~nRowColSel*RowA_9+nRowColSel*MAin_c_9) + +comp 53: SLICE_89 (FSLICE) +n2290 = (nFWE_c+n1285) +LEDEN.D = ~UFMSDO_c +LEDEN.CLK = RCLK_c +LEDEN.SP = RCLK_c_enable_25 +LEDEN.LSR = GND +PHI2_N_114_enable_1 = (MAin_c_1*(~n1285*~nFWE_c)) + +comp 54: SLICE_90 (FSLICE) +PHI2_N_114_enable_6 = (Din_c_4*(XOR8MEG_N_112*(~Din_c_7*~Din_c_6))) +n700.D = n701 +n700.CLK = RCLK_c +n700.SP = RCLK_c_enable_23 +n700.LSR = GND +PHI2_N_114_enable_2 = (XOR8MEG_N_112*(~Din_c_5*(~Din_c_4*~n2385))) +n699.D = n700 +n699.CLK = RCLK_c +n699.SP = RCLK_c_enable_23 +n699.LSR = GND + +comp 55: SLICE_91 (FSLICE) +n2248 = (~InitReady+(nRCAS_N_161+nRCS_N_135)) +CBR.D = ~nCCAS_c +CBR.CLK = ~nCRAS_c +CBR.SP = VCC +CBR.LSR = GND +n2292 = (~RASr2+(~InitReady+(~nRowColSel_N_35+nRCS_N_135))) +FWEr.D = ~nFWE_c +FWEr.CLK = ~nCRAS_c +FWEr.SP = VCC +FWEr.LSR = GND + +comp 56: SLICE_92 (FSLICE) +RDQML_c = (~nRowColSel+~MAin_c_9) +RowA_4.D = MAin_c_4 +RowA_4.CLK = ~nCRAS_c +RowA_4.SP = VCC +RowA_4.LSR = ~Ready +RA_c_0 = (~nRowColSel*RowA_0+nRowColSel*MAin_c_0) +RowA_5.D = MAin_c_5 +RowA_5.CLK = ~nCRAS_c +RowA_5.SP = VCC +RowA_5.LSR = ~Ready + +comp 57: SLICE_93 (FSLICE) +n12_adj_2 = (FS_12*(FS_13*(FS_16*FS_14))) +RASr2.D = RASr +RASr2.CLK = RCLK_c +RASr2.SP = VCC +RASr2.LSR = GND +n2293 = (~FS_11+((FS_16+n10)+FS_17)) +RASr3.D = RASr2 +RASr3.CLK = RCLK_c +RASr3.SP = VCC +RASr3.LSR = GND + +comp 58: SLICE_94 (FSLICE) +RA_c_1 = (~nRowColSel*RowA_1+nRowColSel*MAin_c_1) +Bank_0.D = Din_c_0 +Bank_0.CLK = PHI2_c +Bank_0.SP = VCC +Bank_0.LSR = GND +RA_c_3 = (~nRowColSel*RowA_3+nRowColSel*MAin_c_3) +Bank_1.D = Din_c_1 +Bank_1.CLK = PHI2_c +Bank_1.SP = VCC +Bank_1.LSR = GND + +comp 59: SLICE_95 (FSLICE) +RA_c_8 = (~nRowColSel*RowA_8+nRowColSel*MAin_c_8) +Bank_6.D = Din_c_6 +Bank_6.CLK = PHI2_c +Bank_6.SP = VCC +Bank_6.LSR = GND +RA_c_2 = (~nRowColSel*RowA_2+nRowColSel*MAin_c_2) +Bank_7.D = Din_c_7 +Bank_7.CLK = PHI2_c +Bank_7.SP = VCC +Bank_7.LSR = GND + +comp 60: SLICE_96 (FSLICE) +n2299 = (~Ready+nRowColSel_N_35) +XOR8MEG.D = Din_c_0 +XOR8MEG.CLK = ~PHI2_c +XOR8MEG.SP = PHI2_N_114_enable_2 +XOR8MEG.LSR = GND +n2297 = (~nRowColSel_N_35+nRCS_N_135) + +comp 61: SLICE_97 (FSLICE) +RA_c_7 = (~nRowColSel*RowA_7+nRowColSel*MAin_c_7) +Bank_4.D = Din_c_4 +Bank_4.CLK = PHI2_c +Bank_4.SP = VCC +Bank_4.LSR = GND +n2170 = (Bank_1*(Bank_4*(MAin_c_3*MAin_c_7))) +Bank_5.D = Din_c_5 +Bank_5.CLK = PHI2_c +Bank_5.SP = VCC +Bank_5.LSR = GND + +comp 62: SLICE_98 (FSLICE) +RA_c_6 = (~nRowColSel*RowA_6+nRowColSel*MAin_c_6) +Bank_2.D = Din_c_2 +Bank_2.CLK = PHI2_c +Bank_2.SP = VCC +Bank_2.LSR = GND +RA_c_5 = (~nRowColSel*RowA_5+nRowColSel*MAin_c_5) +Bank_3.D = Din_c_3 +Bank_3.CLK = PHI2_c +Bank_3.SP = VCC +Bank_3.LSR = GND + +comp 63: SLICE_99 (FSLICE) +n2164 = (nRCAS_N_161+nRWE_N_173) +RBA_c_0.D = CROW_c_0 +RBA_c_0.CLK = ~nCRAS_c +RBA_c_0.SP = VCC +RBA_c_0.LSR = ~Ready +n18 = (nRowColSel_N_34*~nRowColSel_N_35) +RBA_c_1.D = CROW_c_1 +RBA_c_1.CLK = ~nCRAS_c +RBA_c_1.SP = VCC +RBA_c_1.LSR = ~Ready + +comp 64: SLICE_100 (FSLICE) +n11_adj_3 = (~CASr2+nRowColSel_N_33) +WRD_4.D = Din_c_4 +WRD_4.CLK = ~nCCAS_c +WRD_4.SP = VCC +WRD_4.LSR = GND +n2304 = (FWEr+CBR) +WRD_5.D = Din_c_5 +WRD_5.CLK = ~nCCAS_c +WRD_5.SP = VCC +WRD_5.LSR = GND diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.ncd b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.ncd new file mode 100644 index 0000000000000000000000000000000000000000..ea7b083f50e6de0377ea862e7ae988bd2b157371 GIT binary patch literal 154201 zcmeFa37nl(kv4uq$evDs1Va**hK6)Pg7m$;CkE5$?m(N)LMLG{VjCf11R6mYbPx>U z?kFAxCgNPe0gAAghjH086j-sDBir~zk9|OTrMzwz#H{EEOfBfwC z_dEC2ty5>KQ&p$V@}4_y-eZqVsC?$~(!|olfv$CxlQ)&NEj;+c6G{^&b`X0&9@|N**4G;>)t#Cn ztrRx6A`Q+rq9Qru8&Q!4=NnOx2Im`5kp|}*QIQ7c8&Q!4=b2uS25Sd-(+YXsEZBSo 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0000000..16daf53 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.p2t @@ -0,0 +1,9 @@ +-w +-l 5 +-i 6 +-n 1 +-t 1 +-s 1 +-c 0 +-e 0 +-exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.p2t.tmp0 b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.p2t.tmp0 new file mode 100644 index 0000000..eb789dd --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.p2t.tmp0 @@ -0,0 +1,9 @@ +-w +-l 5 +-i 6 +-n 1 +-t 1 +-s 1 +-c 0 +-e 0 +-exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.p3t b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.p3t new file mode 100644 index 0000000..e625c68 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.p3t @@ -0,0 +1,5 @@ +-rem +-distrce +-log "RAM2GS_LCMXO256C_impl1.log" +-o "RAM2GS_LCMXO256C_impl1.csv" +-pr "RAM2GS_LCMXO256C_impl1.prf" diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pad b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pad new file mode 100644 index 0000000..0445323 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pad @@ -0,0 +1,271 @@ +PAD Specification File +*************************** + +PART TYPE: LCMXO256C +Performance Grade: 3 +PACKAGE: TQFP100 +Package Status: Final Version 1.19 + +Mon Aug 16 21:32:33 2021 + +Pinout by Port Name: ++-----------+----------+--------------+------+----------------------------------+ +| Port Name | Pin/Bank | Buffer Type | Site | Properties | ++-----------+----------+--------------+------+----------------------------------+ +| CROW[0] | 32/1 | LVTTL33_IN | PB2C | SLEW:FAST | +| CROW[1] | 34/1 | LVTTL33_IN | PB2D | SLEW:FAST | +| Din[0] | 21/1 | LVTTL33_IN | PL8A | SLEW:FAST | +| Din[1] | 15/1 | LVTTL33_IN | PL6A | SLEW:FAST | +| Din[2] | 14/1 | LVTTL33_IN | PL5D | SLEW:FAST | +| Din[3] | 16/1 | LVTTL33_IN | PL6B | SLEW:FAST | +| Din[4] | 18/1 | LVTTL33_IN | PL7B | SLEW:FAST | +| Din[5] | 17/1 | LVTTL33_IN | PL7A | SLEW:FAST | +| Din[6] | 20/1 | LVTTL33_IN | PL7D | SLEW:FAST | +| Din[7] | 19/1 | LVTTL33_IN | PL7C | SLEW:FAST | +| Dout[0] | 1/1 | LVTTL33_OUT | PL2A | DRIVE:4mA SLEW:SLOW | +| Dout[1] | 7/1 | LVTTL33_OUT | PL4A | DRIVE:4mA SLEW:SLOW | +| Dout[2] | 8/1 | LVTTL33_OUT | PL4B | DRIVE:4mA SLEW:SLOW | +| Dout[3] | 6/1 | LVTTL33_OUT | PL3D | DRIVE:4mA SLEW:SLOW | +| Dout[4] | 4/1 | LVTTL33_OUT | PL3B | DRIVE:4mA SLEW:SLOW | +| Dout[5] | 5/1 | LVTTL33_OUT | PL3C | DRIVE:4mA SLEW:SLOW | +| Dout[6] | 2/1 | LVTTL33_OUT | PL2B | DRIVE:4mA SLEW:SLOW | +| Dout[7] | 3/1 | LVTTL33_OUT | PL3A | DRIVE:4mA SLEW:SLOW | +| LED | 57/0 | LVTTL33_OUT | PR7B | DRIVE:16mA SLEW:SLOW | +| MAin[0] | 23/1 | LVTTL33_IN | PL9A | SLEW:FAST | +| MAin[1] | 38/1 | LVTTL33_IN | PB3C | SLEW:FAST | +| MAin[2] | 37/1 | LVTTL33_IN | PB3B | SLEW:FAST | +| MAin[3] | 47/1 | LVTTL33_IN | PB5A | SLEW:FAST | +| MAin[4] | 46/1 | LVTTL33_IN | PB4D | SLEW:FAST | +| MAin[5] | 45/1 | LVTTL33_IN | PB4C | SLEW:FAST | +| MAin[6] | 49/1 | LVTTL33_IN | PB5C | SLEW:FAST | +| MAin[7] | 44/1 | LVTTL33_IN | PB4B | SLEW:FAST | +| MAin[8] | 50/1 | LVTTL33_IN | PB5D | SLEW:FAST | +| MAin[9] | 51/0 | LVTTL33_IN | PR9B | SLEW:FAST | +| PHI2 | 39/1 | LVTTL33_IN | PB3D | SLEW:FAST | +| RA[0] | 98/0 | LVTTL33_OUT | PT2C | DRIVE:4mA SLEW:SLOW | +| RA[10] | 87/0 | LVTTL33_OUT | PT3D | DRIVE:4mA SLEW:SLOW | +| RA[11] | 79/0 | LVTTL33_OUT | PT5A | DRIVE:4mA SLEW:SLOW | +| RA[1] | 89/0 | LVTTL33_OUT | PT3C | DRIVE:4mA SLEW:SLOW | +| RA[2] | 94/0 | LVTTL33_OUT | PT3A | DRIVE:4mA SLEW:SLOW | +| RA[3] | 97/0 | LVTTL33_OUT | PT2D | DRIVE:4mA SLEW:SLOW | +| RA[4] | 99/0 | LVTTL33_OUT | PT2B | DRIVE:4mA SLEW:SLOW | +| RA[5] | 95/0 | LVTTL33_OUT | PT2F | DRIVE:4mA SLEW:SLOW | +| RA[6] | 91/0 | LVTTL33_OUT | PT3B | DRIVE:4mA SLEW:SLOW | +| RA[7] | 100/0 | LVTTL33_OUT | PT2A | DRIVE:4mA SLEW:SLOW | +| RA[8] | 96/0 | LVTTL33_OUT | PT2E | DRIVE:4mA SLEW:SLOW | +| RA[9] | 85/0 | LVTTL33_OUT | PT4B | DRIVE:4mA SLEW:SLOW | +| RBA[0] | 63/0 | LVTTL33_OUT | PR5D | DRIVE:4mA SLEW:SLOW | +| RBA[1] | 83/0 | LVTTL33_OUT | PT4C | DRIVE:4mA SLEW:SLOW | +| RCKE | 82/0 | LVTTL33_OUT | PT4D | DRIVE:4mA SLEW:SLOW | +| RCLK | 86/0 | LVTTL33_IN | PT4A | SLEW:FAST | +| RDQMH | 76/0 | LVTTL33_OUT | PR2A | DRIVE:4mA SLEW:SLOW | +| RDQML | 61/0 | LVTTL33_OUT | PR6A | DRIVE:4mA SLEW:SLOW | +| RD[0] | 64/0 | LVTTL33_BIDI | PR5C | DRIVE:4mA SLEW:SLOW PULL:KEEPER | +| RD[1] | 65/0 | LVTTL33_BIDI | PR5B | DRIVE:4mA SLEW:SLOW PULL:KEEPER | +| RD[2] | 66/0 | LVTTL33_BIDI | PR5A | DRIVE:4mA SLEW:SLOW PULL:KEEPER | +| RD[3] | 67/0 | LVTTL33_BIDI | PR4B | DRIVE:4mA SLEW:SLOW PULL:KEEPER | +| RD[4] | 68/0 | LVTTL33_BIDI | PR4A | DRIVE:4mA SLEW:SLOW PULL:KEEPER | +| RD[5] | 69/0 | LVTTL33_BIDI | PR3D | DRIVE:4mA SLEW:SLOW PULL:KEEPER | +| RD[6] | 70/0 | LVTTL33_BIDI | PR3C | DRIVE:4mA SLEW:SLOW PULL:KEEPER | +| RD[7] | 71/0 | LVTTL33_BIDI | PR3B | DRIVE:4mA SLEW:SLOW PULL:KEEPER | +| UFMCLK | 58/0 | LVTTL33_OUT | PR7A | DRIVE:4mA SLEW:SLOW | +| UFMSDI | 56/0 | LVTTL33_OUT | PR7C | DRIVE:4mA SLEW:SLOW | +| UFMSDO | 55/0 | LVTTL33_IN | PR7D | SLEW:FAST PULL:KEEPER | +| nCCAS | 27/1 | LVTTL33_IN | PL9B | SLEW:FAST | +| nCRAS | 43/1 | LVTTL33_IN | PB4A | SLEW:FAST | +| nFWE | 22/1 | LVTTL33_IN | PL8B | SLEW:FAST | +| nRCAS | 78/0 | LVTTL33_OUT | PT5B | DRIVE:4mA SLEW:SLOW | +| nRCS | 77/0 | LVTTL33_OUT | PT5C | DRIVE:4mA SLEW:SLOW | +| nRRAS | 73/0 | LVTTL33_OUT | PR2B | DRIVE:4mA SLEW:SLOW | +| nRWE | 72/0 | LVTTL33_OUT | PR3A | DRIVE:4mA SLEW:SLOW | +| nUFMCS | 53/0 | LVTTL33_OUT | PR8B | DRIVE:4mA SLEW:SLOW | ++-----------+----------+--------------+------+----------------------------------+ + +Vccio by Bank: ++------+-------+ +| Bank | Vccio | ++------+-------+ +| 0 | 3.3V | +| 1 | 3.3V | ++------+-------+ + +Vref by Bank: ++------+-----+-----------------+---------+ +| Vref | Pin | Bank # / Vref # | Load(s) | ++------+-----+-----------------+---------+ ++------+-----+-----------------+---------+ + +Pinout by Pin Number: ++----------+---------------------+------------+--------------+------+---------------+ +| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | ++----------+---------------------+------------+--------------+------+---------------+ +| 1/1 | Dout[0] | LOCATED | LVTTL33_OUT | PL2A | | +| 2/1 | Dout[6] | LOCATED | LVTTL33_OUT | PL2B | | +| 3/1 | Dout[7] | LOCATED | LVTTL33_OUT | PL3A | | +| 4/1 | Dout[4] | LOCATED | LVTTL33_OUT | PL3B | | +| 5/1 | Dout[5] | LOCATED | LVTTL33_OUT | PL3C | | +| 6/1 | Dout[3] | LOCATED | LVTTL33_OUT | PL3D | | +| 7/1 | Dout[1] | LOCATED | LVTTL33_OUT | PL4A | | +| 8/1 | Dout[2] | LOCATED | LVTTL33_OUT | PL4B | | +| 9/1 | unused, PULL:UP | | | PL5A | | +| 11/1 | unused, PULL:UP | | | PL5B | | +| 13/1 | unused, PULL:UP | | | PL5C | | +| 14/1 | Din[2] | LOCATED | LVTTL33_IN | PL5D | GSR_PADN | +| 15/1 | Din[1] | LOCATED | LVTTL33_IN | PL6A | | +| 16/1 | Din[3] | LOCATED | LVTTL33_IN | PL6B | TSALLPAD | +| 17/1 | Din[5] | LOCATED | LVTTL33_IN | PL7A | | +| 18/1 | Din[4] | LOCATED | LVTTL33_IN | PL7B | | +| 19/1 | Din[7] | LOCATED | LVTTL33_IN | PL7C | | +| 20/1 | Din[6] | LOCATED | LVTTL33_IN | PL7D | | +| 21/1 | Din[0] | LOCATED | LVTTL33_IN | PL8A | | +| 22/1 | nFWE | LOCATED | LVTTL33_IN | PL8B | | +| 23/1 | MAin[0] | LOCATED | LVTTL33_IN | PL9A | | +| 27/1 | nCCAS | LOCATED | LVTTL33_IN | PL9B | | +| 29/1 | unused, PULL:UP | | | PB2A | | +| 30/1 | unused, PULL:UP | | | PB2B | | +| 32/1 | CROW[0] | LOCATED | LVTTL33_IN | PB2C | | +| 34/1 | CROW[1] | LOCATED | LVTTL33_IN | PB2D | | +| 36/1 | unused, PULL:UP | | | PB3A | PCLKT1_1 | +| 37/1 | MAin[2] | LOCATED | LVTTL33_IN | PB3B | | +| 38/1 | MAin[1] | LOCATED | LVTTL33_IN | PB3C | PCLKT1_0 | +| 39/1 | PHI2 | LOCATED | LVTTL33_IN | PB3D | | +| 43/1 | nCRAS | LOCATED | LVTTL33_IN | PB4A | | +| 44/1 | MAin[7] | LOCATED | LVTTL33_IN | PB4B | | +| 45/1 | MAin[5] | LOCATED | LVTTL33_IN | PB4C | | +| 46/1 | MAin[4] | LOCATED | LVTTL33_IN | PB4D | | +| 47/1 | MAin[3] | LOCATED | LVTTL33_IN | PB5A | | +| 49/1 | MAin[6] | LOCATED | LVTTL33_IN | PB5C | | +| 50/1 | MAin[8] | LOCATED | LVTTL33_IN | PB5D | | +| 51/0 | MAin[9] | LOCATED | LVTTL33_IN | PR9B | | +| 52/0 | unused, PULL:UP | | | PR9A | | +| 53/0 | nUFMCS | LOCATED | LVTTL33_OUT | PR8B | | +| 54/0 | unused, PULL:UP | | | PR8A | | +| 55/0 | UFMSDO | LOCATED | LVTTL33_IN | PR7D | | +| 56/0 | UFMSDI | LOCATED | LVTTL33_OUT | PR7C | | +| 57/0 | LED | LOCATED | LVTTL33_OUT | PR7B | | +| 58/0 | UFMCLK | LOCATED | LVTTL33_OUT | PR7A | | +| 59/0 | unused, PULL:UP | | | PR6B | | +| 61/0 | RDQML | LOCATED | LVTTL33_OUT | PR6A | | +| 63/0 | RBA[0] | LOCATED | LVTTL33_OUT | PR5D | | +| 64/0 | RD[0] | LOCATED | LVTTL33_BIDI | PR5C | | +| 65/0 | RD[1] | LOCATED | LVTTL33_BIDI | PR5B | | +| 66/0 | RD[2] | LOCATED | LVTTL33_BIDI | PR5A | | +| 67/0 | RD[3] | LOCATED | LVTTL33_BIDI | PR4B | | +| 68/0 | RD[4] | LOCATED | LVTTL33_BIDI | PR4A | | +| 69/0 | RD[5] | LOCATED | LVTTL33_BIDI | PR3D | | +| 70/0 | RD[6] | LOCATED | LVTTL33_BIDI | PR3C | | +| 71/0 | RD[7] | LOCATED | LVTTL33_BIDI | PR3B | | +| 72/0 | nRWE | LOCATED | LVTTL33_OUT | PR3A | | +| 73/0 | nRRAS | LOCATED | LVTTL33_OUT | PR2B | | +| 76/0 | RDQMH | LOCATED | LVTTL33_OUT | PR2A | | +| 77/0 | nRCS | LOCATED | LVTTL33_OUT | PT5C | | +| 78/0 | nRCAS | LOCATED | LVTTL33_OUT | PT5B | | +| 79/0 | RA[11] | LOCATED | LVTTL33_OUT | PT5A | | +| 80/0 | unused, PULL:UP | | | PT4F | | +| 81/0 | unused, PULL:UP | | | PT4E | | +| 82/0 | RCKE | LOCATED | LVTTL33_OUT | PT4D | | +| 83/0 | RBA[1] | LOCATED | LVTTL33_OUT | PT4C | | +| 85/0 | RA[9] | LOCATED | LVTTL33_OUT | PT4B | PCLKT0_1 | +| 86/0 | RCLK | LOCATED | LVTTL33_IN | PT4A | PCLKT0_0 | +| 87/0 | RA[10] | LOCATED | LVTTL33_OUT | PT3D | | +| 89/0 | RA[1] | LOCATED | LVTTL33_OUT | PT3C | | +| 91/0 | RA[6] | LOCATED | LVTTL33_OUT | PT3B | | +| 94/0 | RA[2] | LOCATED | LVTTL33_OUT | PT3A | | +| 95/0 | RA[5] | LOCATED | LVTTL33_OUT | PT2F | | +| 96/0 | RA[8] | LOCATED | LVTTL33_OUT | PT2E | | +| 97/0 | RA[3] | LOCATED | LVTTL33_OUT | PT2D | | +| 98/0 | RA[0] | LOCATED | LVTTL33_OUT | PT2C | | +| 99/0 | RA[4] | LOCATED | LVTTL33_OUT | PT2B | | +| 100/0 | RA[7] | LOCATED | LVTTL33_OUT | PT2A | | +| PB5B/0 | unused, PULL:UP | | | PB5B | | +| PT5D/0 | unused, PULL:UP | | | PT5D | | +| TCK/1 | | | | TCK | TCK | +| TDI/1 | | | | TDI | TDI | +| TDO/1 | | | | TDO | TDO | +| TMS/1 | | | | TMS | TMS | ++----------+---------------------+------------+--------------+------+---------------+ + + +List of All Pins' Locate Preferences Based on Final Placement After PAR +to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): + +LOCATE COMP "CROW[0]" SITE "32"; +LOCATE COMP "CROW[1]" SITE "34"; +LOCATE COMP "Din[0]" SITE "21"; +LOCATE COMP "Din[1]" SITE "15"; +LOCATE COMP "Din[2]" SITE "14"; +LOCATE COMP "Din[3]" SITE "16"; +LOCATE COMP "Din[4]" SITE "18"; +LOCATE COMP "Din[5]" SITE "17"; +LOCATE COMP "Din[6]" SITE "20"; +LOCATE COMP "Din[7]" SITE "19"; +LOCATE COMP "Dout[0]" SITE "1"; +LOCATE COMP "Dout[1]" SITE "7"; +LOCATE COMP "Dout[2]" SITE "8"; +LOCATE COMP "Dout[3]" SITE "6"; +LOCATE COMP "Dout[4]" SITE "4"; +LOCATE COMP "Dout[5]" SITE "5"; +LOCATE COMP "Dout[6]" SITE "2"; +LOCATE COMP "Dout[7]" SITE "3"; +LOCATE COMP "LED" SITE "57"; +LOCATE COMP "MAin[0]" SITE "23"; +LOCATE COMP "MAin[1]" SITE "38"; +LOCATE COMP "MAin[2]" SITE "37"; +LOCATE COMP "MAin[3]" SITE "47"; +LOCATE COMP "MAin[4]" SITE "46"; +LOCATE COMP "MAin[5]" SITE "45"; +LOCATE COMP "MAin[6]" SITE "49"; +LOCATE COMP "MAin[7]" SITE "44"; +LOCATE COMP "MAin[8]" SITE "50"; +LOCATE COMP "MAin[9]" SITE "51"; +LOCATE COMP "PHI2" SITE "39"; +LOCATE COMP "RA[0]" SITE "98"; +LOCATE COMP "RA[10]" SITE "87"; +LOCATE COMP "RA[11]" SITE "79"; +LOCATE COMP "RA[1]" SITE "89"; +LOCATE COMP "RA[2]" SITE "94"; +LOCATE COMP "RA[3]" SITE "97"; +LOCATE COMP "RA[4]" SITE "99"; +LOCATE COMP "RA[5]" SITE "95"; +LOCATE COMP "RA[6]" SITE "91"; +LOCATE COMP "RA[7]" SITE "100"; +LOCATE COMP "RA[8]" SITE "96"; +LOCATE COMP "RA[9]" SITE "85"; +LOCATE COMP "RBA[0]" SITE "63"; +LOCATE COMP "RBA[1]" SITE "83"; +LOCATE COMP "RCKE" SITE "82"; +LOCATE COMP "RCLK" SITE "86"; +LOCATE COMP "RDQMH" SITE "76"; +LOCATE COMP "RDQML" SITE "61"; +LOCATE COMP "RD[0]" SITE "64"; +LOCATE COMP "RD[1]" SITE "65"; +LOCATE COMP "RD[2]" SITE "66"; +LOCATE COMP "RD[3]" SITE "67"; +LOCATE COMP "RD[4]" SITE "68"; +LOCATE COMP "RD[5]" SITE "69"; +LOCATE COMP "RD[6]" SITE "70"; +LOCATE COMP "RD[7]" SITE "71"; +LOCATE COMP "UFMCLK" SITE "58"; +LOCATE COMP "UFMSDI" SITE "56"; +LOCATE COMP "UFMSDO" SITE "55"; +LOCATE COMP "nCCAS" SITE "27"; +LOCATE COMP "nCRAS" SITE "43"; +LOCATE COMP "nFWE" SITE "22"; +LOCATE COMP "nRCAS" SITE "78"; +LOCATE COMP "nRCS" SITE "77"; +LOCATE COMP "nRRAS" SITE "73"; +LOCATE COMP "nRWE" SITE "72"; +LOCATE COMP "nUFMCS" SITE "53"; + + + + + +PAR: Place And Route Diamond (64-bit) 3.12.0.240.2. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Mon Aug 16 21:32:33 2021 + diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.par b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.par new file mode 100644 index 0000000..6275f58 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.par @@ -0,0 +1,239 @@ +PAR: Place And Route Diamond (64-bit) 3.12.0.240.2. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Mon Aug 16 21:32:27 2021 + +C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO256C_impl1.p2t +RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir +RAM2GS_LCMXO256C_impl1.prf -gui -msgset +C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml + + +Preference file: RAM2GS_LCMXO256C_impl1.prf. + +Level/ Number Worst Timing Worst Timing Run NCD +Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status +---------- -------- ----- ------ ----------- ----------- ---- ------ +5_1 * 0 2.023 0 0.339 0 07 Completed + +* : Design saved. + +Total (real) run time for 1-seed: 7 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Lattice Place and Route Report for Design "RAM2GS_LCMXO256C_impl1_map.ncd" +Mon Aug 16 21:32:27 2021 + +PAR: Place And Route Diamond (64-bit) 3.12.0.240.2. +Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir/5_1.ncd RAM2GS_LCMXO256C_impl1.prf +Preference file: RAM2GS_LCMXO256C_impl1.prf. +Placement level-cost: 5-1. +Routing Iterations: 6 + +Loading design for application par from file RAM2GS_LCMXO256C_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 3 +Loading device for application par from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +License checked out. + + +Ignore Preference Error(s): True +Device utilization summary: + + PIO (prelim) 67/79 84% used + 67/78 85% bonded + SLICE 65/128 50% used + + + +Number of Signals: 252 +Number of Connections: 618 + +Pin Constraint Summary: + 67 out of 67 pins locked (100% locked). + +The following 4 signals are selected to use the primary clock routing resources: + RCLK_c (driver: RCLK, clk load #: 39) + PHI2_c (driver: PHI2, clk load #: 13) + nCCAS_c (driver: nCCAS, clk load #: 4) + nCRAS_c (driver: nCRAS, clk load #: 7) + +No signal is selected as secondary clock. + +No signal is selected as Global Set/Reset. +Starting Placer Phase 0. +........ +Finished Placer Phase 0. REAL time: 0 secs + +Starting Placer Phase 1. +............... +Placer score = 586066. +Finished Placer Phase 1. REAL time: 6 secs + +Starting Placer Phase 2. +. +Placer score = 584668 +Finished Placer Phase 2. REAL time: 6 secs + + +------------------ Clock Report ------------------ + +Global Clock Resources: + CLK_PIN : 1 out of 4 (25%) + General PIO: 3 out of 80 (3%) + +Global Clocks: + PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT4A)", clk load = 39 + PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB3D)", clk load = 13 + PRIMARY "nCCAS_c" from comp "nCCAS" on PIO site "27 (PL9B)", clk load = 4 + PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB4A)", clk load = 7 + + PRIMARY : 4 out of 4 (100%) + SECONDARY: 0 out of 4 (0%) + +--------------- End of Clock Report --------------- + + +I/O Usage Summary (final): + 67 out of 79 (84.8%) PIO sites used. + 67 out of 78 (85.9%) bonded PIO sites used. + Number of PIO comps: 67; differential: 0. + Number of Vref pins used: 0. + +I/O Bank Usage Summary: ++----------+----------------+------------+------------+------------+ +| I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 | ++----------+----------------+------------+------------+------------+ +| 0 | 36 / 41 ( 87%) | 3.3V | - | - | +| 1 | 31 / 37 ( 83%) | 3.3V | - | - | ++----------+----------------+------------+------------+------------+ + +Total placer CPU time: 6 secs + +Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd. + +0 connections routed; 618 unrouted. +Starting router resource preassignment +WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew. +WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew. +WARNING - par: The driver of primary clock net nCCAS_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew. + +Completed router resource preassignment. Real time: 6 secs + +Start NBR router at 21:32:33 08/16/21 + +***************************************************************** +Info: NBR allows conflicts(one node used by more than one signal) + in the earlier iterations. In each iteration, it tries to + solve the conflicts while keeping the critical connections + routed as short as possible. The routing process is said to + be completed when no conflicts exist and all connections + are routed. +Note: NBR uses a different method to calculate timing slacks. The + worst slack and total negative slack may not be the same as + that in TRCE report. You should always run TRCE to verify + your design. +***************************************************************** + +Start NBR special constraint process at 21:32:33 08/16/21 + +Start NBR section for initial routing at 21:32:33 08/16/21 +Level 1, iteration 1 +0(0.00%) conflict; 535(86.57%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack: 2.084ns/0.000ns; real time: 6 secs +Level 2, iteration 1 +0(0.00%) conflict; 535(86.57%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack: 2.084ns/0.000ns; real time: 6 secs +Level 3, iteration 1 +0(0.00%) conflict; 509(82.36%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack: 2.038ns/0.000ns; real time: 6 secs +Level 4, iteration 1 +23(0.19%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 2.023ns/0.000ns; real time: 6 secs + +Info: Initial congestion level at 75% usage is 0 +Info: Initial congestion area at 75% usage is 0 (0.00%) + +Start NBR section for normal routing at 21:32:33 08/16/21 +Level 1, iteration 1 +0(0.00%) conflict; 24(3.88%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack: 2.023ns/0.000ns; real time: 6 secs +Level 4, iteration 1 +8(0.07%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 2.023ns/0.000ns; real time: 6 secs +Level 4, iteration 2 +4(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 2.023ns/0.000ns; real time: 6 secs +Level 4, iteration 3 +0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 2.023ns/0.000ns; real time: 6 secs + +Start NBR section for setup/hold timing optimization with effort level 3 at 21:32:33 08/16/21 + +Start NBR section for re-routing at 21:32:33 08/16/21 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 2.023ns/0.000ns; real time: 6 secs + +Start NBR section for post-routing at 21:32:33 08/16/21 + +End NBR router with 0 unrouted connection + +NBR Summary +----------- + Number of unrouted connections : 0 (0.00%) + Number of connections with timing violations : 0 (0.00%) + Estimated worst slack : 2.023ns + Timing score : 0 +----------- +Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. + + + +Total CPU time 6 secs +Total REAL time: 7 secs +Completely routed. +End of route. 618 routed (100.00%); 0 unrouted. + +Hold time timing score: 0, hold timing errors: 0 + +Timing score: 0 + +Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd. + + +All signals are completely routed. + + +PAR_SUMMARY::Run status = Completed +PAR_SUMMARY::Number of unrouted conns = 0 +PAR_SUMMARY::Worst slack> = 2.023 +PAR_SUMMARY::Timing score> = 0.000 +PAR_SUMMARY::Worst slack> = 0.339 +PAR_SUMMARY::Timing score> = 0.000 +PAR_SUMMARY::Number of errors = 0 + +Total CPU time to completion: 6 secs +Total REAL time to completion: 7 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.prf b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.prf new file mode 100644 index 0000000..4d03744 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.prf @@ -0,0 +1,165 @@ +SCHEMATIC START ; +# map: version Diamond (64-bit) 3.12.0.240.2 -- WARNING: Map write only section -- Mon Aug 16 21:32:26 2021 + +SYSCONFIG INBUF=ON CONFIG_SECURE=OFF ; +LOCATE COMP "RD[7]" SITE "71" ; +LOCATE COMP "RD[6]" SITE "70" ; +LOCATE COMP "RD[5]" SITE "69" ; +LOCATE COMP "RD[4]" SITE "68" ; +LOCATE COMP "RD[3]" SITE "67" ; +LOCATE COMP "RD[2]" SITE "66" ; +LOCATE COMP "RD[1]" SITE "65" ; +LOCATE COMP "RD[0]" SITE "64" ; +LOCATE COMP "Dout[7]" SITE "3" ; +LOCATE COMP "Dout[6]" SITE "2" ; +LOCATE COMP "Dout[5]" SITE "5" ; +LOCATE COMP "Dout[4]" SITE "4" ; +LOCATE COMP "Dout[3]" SITE "6" ; +LOCATE COMP "Dout[2]" SITE "8" ; +LOCATE COMP "Dout[1]" SITE "7" ; +LOCATE COMP "Dout[0]" SITE "1" ; +LOCATE COMP "LED" SITE "57" ; +LOCATE COMP "RBA[1]" SITE "83" ; +LOCATE COMP "RBA[0]" SITE "63" ; +LOCATE COMP "RA[11]" SITE "79" ; +LOCATE COMP "RA[10]" SITE "87" ; +LOCATE COMP "RA[9]" SITE "85" ; +LOCATE COMP "RA[8]" SITE "96" ; +LOCATE COMP "RA[7]" SITE "100" ; +LOCATE COMP "RA[6]" SITE "91" ; +LOCATE COMP "RA[5]" SITE "95" ; +LOCATE COMP "RA[4]" SITE "99" ; +LOCATE COMP "RA[3]" SITE "97" ; +LOCATE COMP "RA[2]" SITE "94" ; +LOCATE COMP "RA[1]" SITE "89" ; +LOCATE COMP "RA[0]" SITE "98" ; +LOCATE COMP "nRCS" SITE "77" ; +LOCATE COMP "RCKE" SITE "82" ; +LOCATE COMP "nRWE" SITE "72" ; +LOCATE COMP "nRRAS" SITE "73" ; +LOCATE COMP "nRCAS" SITE "78" ; +LOCATE COMP "RDQMH" SITE "76" ; +LOCATE COMP "RDQML" SITE "61" ; +LOCATE COMP "nUFMCS" SITE "53" ; +LOCATE COMP "UFMCLK" SITE "58" ; +LOCATE COMP "UFMSDI" SITE "56" ; +LOCATE COMP "PHI2" SITE "39" ; +LOCATE COMP "MAin[9]" SITE "51" ; +LOCATE COMP "MAin[8]" SITE "50" ; +LOCATE COMP "MAin[7]" SITE "44" ; +LOCATE COMP "MAin[6]" SITE "49" ; +LOCATE COMP "MAin[5]" SITE "45" ; +LOCATE COMP "MAin[4]" SITE "46" ; +LOCATE COMP "MAin[3]" SITE "47" ; +LOCATE COMP "MAin[2]" SITE "37" ; +LOCATE COMP "MAin[1]" SITE "38" ; +LOCATE COMP "MAin[0]" SITE "23" ; +LOCATE COMP "CROW[1]" SITE "34" ; +LOCATE COMP "CROW[0]" SITE "32" ; +LOCATE COMP "Din[7]" SITE "19" ; +LOCATE COMP "Din[6]" SITE "20" ; +LOCATE COMP "Din[5]" SITE "17" ; +LOCATE COMP "Din[4]" SITE "18" ; +LOCATE COMP "Din[3]" SITE "16" ; +LOCATE COMP "Din[2]" SITE "14" ; +LOCATE COMP "Din[1]" SITE "15" ; +LOCATE COMP "Din[0]" SITE "21" ; +LOCATE COMP "nCCAS" SITE "27" ; +LOCATE COMP "nCRAS" SITE "43" ; +LOCATE COMP "nFWE" SITE "22" ; +LOCATE COMP "RCLK" SITE "86" ; +LOCATE COMP "UFMSDO" SITE "55" ; +PERIOD NET "PHI2_c" 350.000000 ns ; +USE PRIMARY NET "RCLK_c" ; +PERIOD NET "nCCAS_c" 350.000000 ns ; +USE PRIMARY NET "PHI2_c" ; +PERIOD NET "nCRAS_c" 350.000000 ns ; +USE PRIMARY NET "nCCAS_c" ; +PERIOD NET "RCLK_c" 16.000000 ns ; +USE PRIMARY NET "nCRAS_c" ; +SCHEMATIC END ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +OUTPUT PORT "RD[7]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[0]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[1]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[2]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[3]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[4]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[5]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[6]" LOAD 20.000000 pF ; +OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ; +OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ; +OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ; +OUTPUT PORT "nRWE" LOAD 10.000000 pF ; +OUTPUT PORT "nRCAS" LOAD 10.000000 pF ; +OUTPUT PORT "nRCS" LOAD 10.000000 pF ; +OUTPUT PORT "nRRAS" LOAD 10.000000 pF ; +OUTPUT PORT "RDQML" LOAD 10.000000 pF ; +OUTPUT PORT "RDQMH" LOAD 10.000000 pF ; +OUTPUT PORT "RCKE" LOAD 10.000000 pF ; +OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ; +OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[11]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[10]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[9]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[8]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[7]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[6]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[5]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[4]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[3]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[2]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[1]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[0]" LOAD 10.000000 pF ; +OUTPUT PORT "LED" LOAD 25.000000 pF ; +OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ; +VOLTAGE 3.300 V; +VCCIO_DERATE BANK 0 PERCENT -5; +VCCIO_DERATE PERCENT -5; +VCCIO_DERATE BANK 1 PERCENT -5; +CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; +COMMERCIAL ; diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pt b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pt new file mode 100644 index 0000000..916dbc3 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pt @@ -0,0 +1,10 @@ +-v +10 + + + + +-gt +-sethld +-sp 3 +-sphld m diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.t2b b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.t2b new file mode 100644 index 0000000..aa05f83 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.t2b @@ -0,0 +1,2 @@ + +-g ES:No diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.tw1 b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.tw1 new file mode 100644 index 0000000..f728d52 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.tw1 @@ -0,0 +1,2507 @@ + +Loading design for application trce from file ram2gs_lcmxo256c_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 3 +Loading device for application trce from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2 +Mon Aug 16 21:32:27 2021 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf +Design file: ram2gs_lcmxo256c_impl1_map.ncd +Preference file: ram2gs_lcmxo256c_impl1.prf +Device,speed: LCMXO256C,3 +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + +Derating parameters +------------------- +Voltage: 3.300 V + + + +================================================================================ +Preference: PERIOD NET "PHI2_c" 350.000000 ns ; + 113 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 161.862ns (weighted slack = 323.724ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i7 (from PHI2_c +) + Destination: FF Data in CmdSubmitted_384 (to PHI2_c -) + + Delay: 12.873ns (21.6% logic, 78.4% route), 7 logic levels. + + Constraint Details: + + 12.873ns physical path delay SLICE_95 to SLICE_19 meets + 175.000ns delay constraint less + 0.265ns CE_SET requirement (totaling 174.735ns) by 161.862ns + + Physical Path Details: + + Data path SLICE_95 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_95.CLK to SLICE_95.Q1 SLICE_95 (from PHI2_c) +ROUTE 1 e 1.441 SLICE_95.Q1 to SLICE_67.A1 Bank_7 +CTOF_DEL --- 0.371 SLICE_67.A1 to SLICE_67.F1 SLICE_67 +ROUTE 1 e 1.441 SLICE_67.F1 to SLICE_82.C1 n2154 +CTOF_DEL --- 0.371 SLICE_82.C1 to SLICE_82.F1 SLICE_82 +ROUTE 1 e 1.441 SLICE_82.F1 to SLICE_76.B1 n26 +CTOF_DEL --- 0.371 SLICE_76.B1 to SLICE_76.F1 SLICE_76 +ROUTE 4 e 1.441 SLICE_76.F1 to SLICE_89.B0 n1285 +CTOF_DEL --- 0.371 SLICE_89.B0 to SLICE_89.F0 SLICE_89 +ROUTE 3 e 1.441 SLICE_89.F0 to SLICE_18.D1 n2290 +CTOF_DEL --- 0.371 SLICE_18.D1 to SLICE_18.F1 SLICE_18 +ROUTE 3 e 1.441 SLICE_18.F1 to SLICE_90.C0 XOR8MEG_N_112 +CTOF_DEL --- 0.371 SLICE_90.C0 to SLICE_90.F0 SLICE_90 +ROUTE 2 e 1.441 SLICE_90.F0 to SLICE_19.CE PHI2_N_114_enable_6 (to PHI2_c) + -------- + 12.873 (21.6% logic, 78.4% route), 7 logic levels. + +Report: 26.276ns is the minimum period for this preference. + + +================================================================================ +Preference: PERIOD NET "nCCAS_c" 350.000000 ns ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 348.000ns + The internal maximum frequency of the following component is 500.000 MHz + + Logical Details: Cell type Pin name Component name + + Destination: FSLICE CLK SLICE_76 + + Delay: 2.000ns -- based on Minimum Pulse Width + +Report: 2.000ns is the minimum period for this preference. + + +================================================================================ +Preference: PERIOD NET "nCRAS_c" 350.000000 ns ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 348.000ns + The internal maximum frequency of the following component is 500.000 MHz + + Logical Details: Cell type Pin name Component name + + Destination: FSLICE CLK SLICE_77 + + Delay: 2.000ns -- based on Minimum Pulse Width + +Report: 2.000ns is the minimum period for this preference. + + +================================================================================ +Preference: PERIOD NET "RCLK_c" 16.000000 ns ; + 395 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 5.575ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_577__i14 (from RCLK_c +) + Destination: FF Data in n8MEGEN_391 (to RCLK_c +) + + Delay: 10.181ns (23.7% logic, 76.3% route), 6 logic levels. + + Constraint Details: + + 10.181ns physical path delay SLICE_7 to SLICE_56 meets + 16.000ns delay constraint less + 0.244ns CE_SET requirement (totaling 15.756ns) by 5.575ns + + Physical Path Details: + + Data path SLICE_7 to SLICE_56: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_7.CLK to SLICE_7.Q0 SLICE_7 (from RCLK_c) +ROUTE 3 e 1.441 SLICE_7.Q0 to SLICE_78.A0 FS_14 +CTOF_DEL --- 0.371 SLICE_78.A0 to SLICE_78.F0 SLICE_78 +ROUTE 3 e 1.441 SLICE_78.F0 to SLICE_73.B1 n10 +CTOF_DEL --- 0.371 SLICE_73.B1 to SLICE_73.F1 SLICE_73 +ROUTE 4 e 0.561 SLICE_73.F1 to SLICE_73.B0 n2300 +CTOF_DEL --- 0.371 SLICE_73.B0 to SLICE_73.F0 SLICE_73 +ROUTE 1 e 1.441 SLICE_73.F0 to SLICE_75.C0 n11 +CTOF_DEL --- 0.371 SLICE_75.C0 to SLICE_75.F0 SLICE_75 +ROUTE 2 e 1.441 SLICE_75.F0 to SLICE_33.D1 n2119 +CTOF_DEL --- 0.371 SLICE_33.D1 to SLICE_33.F1 SLICE_33 +ROUTE 1 e 1.441 SLICE_33.F1 to SLICE_56.CE RCLK_c_enable_7 (to RCLK_c) + -------- + 10.181 (23.7% logic, 76.3% route), 6 logic levels. + +Report: 10.425ns is the minimum period for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 4.359ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RA10_373 (from RCLK_c +) + Destination: Port Pad RA[10] + + Data Path Delay: 5.637ns (74.4% logic, 25.6% route), 2 logic levels. + + Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. + + Constraint Details: + 2.504ns delay RCLK to SLICE_55 and + 5.637ns delay SLICE_55 to RA[10] (totaling 8.141ns) meets + 12.500ns offset RCLK to RA[10] by 4.359ns + + Physical Path Details: + + Clock path RCLK to SLICE_55: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 e 1.441 86.PADDI to SLICE_55.CLK RCLK_c + -------- + 2.504 (42.5% logic, 57.5% route), 1 logic levels. + + Data path SLICE_55 to RA[10]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_55.CLK to SLICE_55.Q0 SLICE_55 (from RCLK_c) +ROUTE 1 e 1.441 SLICE_55.Q0 to 87.PADDO n980 +DOPAD_DEL --- 3.636 87.PADDO to 87.PAD RA[10] + -------- + 5.637 (74.4% logic, 25.6% route), 2 logic levels. + +Report: 8.141ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.547ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[9] + + Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels. + + Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. + + Constraint Details: + 2.504ns delay RCLK to SLICE_64 and + 7.449ns delay SLICE_64 to RA[9] (totaling 9.953ns) meets + 12.500ns offset RCLK to RA[9] by 2.547ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 2.504 (42.5% logic, 57.5% route), 1 logic levels. + + Data path SLICE_64 to RA[9]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_88.C1 nRowColSel +CTOF_DEL --- 0.371 SLICE_88.C1 to SLICE_88.F1 SLICE_88 +ROUTE 1 e 1.441 SLICE_88.F1 to 85.PADDO RA_c_9 +DOPAD_DEL --- 3.636 85.PADDO to 85.PAD RA[9] + -------- + 7.449 (61.3% logic, 38.7% route), 3 logic levels. + +Report: 9.953ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.547ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[8] + + Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels. + + Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. + + Constraint Details: + 2.504ns delay RCLK to SLICE_64 and + 7.449ns delay SLICE_64 to RA[8] (totaling 9.953ns) meets + 12.500ns offset RCLK to RA[8] by 2.547ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 2.504 (42.5% logic, 57.5% route), 1 logic levels. + + Data path SLICE_64 to RA[8]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_95.C0 nRowColSel +CTOF_DEL --- 0.371 SLICE_95.C0 to SLICE_95.F0 SLICE_95 +ROUTE 1 e 1.441 SLICE_95.F0 to 96.PADDO RA_c_8 +DOPAD_DEL --- 3.636 96.PADDO to 96.PAD RA[8] + -------- + 7.449 (61.3% logic, 38.7% route), 3 logic levels. + +Report: 9.953ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.547ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[7] + + Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels. + + Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. + + Constraint Details: + 2.504ns delay RCLK to SLICE_64 and + 7.449ns delay SLICE_64 to RA[7] (totaling 9.953ns) meets + 12.500ns offset RCLK to RA[7] by 2.547ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 2.504 (42.5% logic, 57.5% route), 1 logic levels. + + Data path SLICE_64 to RA[7]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_97.C0 nRowColSel +CTOF_DEL --- 0.371 SLICE_97.C0 to SLICE_97.F0 SLICE_97 +ROUTE 1 e 1.441 SLICE_97.F0 to 100.PADDO RA_c_7 +DOPAD_DEL --- 3.636 100.PADDO to 100.PAD RA[7] + -------- + 7.449 (61.3% logic, 38.7% route), 3 logic levels. + +Report: 9.953ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.547ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[6] + + Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels. + + Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. + + Constraint Details: + 2.504ns delay RCLK to SLICE_64 and + 7.449ns delay SLICE_64 to RA[6] (totaling 9.953ns) meets + 12.500ns offset RCLK to RA[6] by 2.547ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 2.504 (42.5% logic, 57.5% route), 1 logic levels. + + Data path SLICE_64 to RA[6]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_98.C0 nRowColSel +CTOF_DEL --- 0.371 SLICE_98.C0 to SLICE_98.F0 SLICE_98 +ROUTE 1 e 1.441 SLICE_98.F0 to 91.PADDO RA_c_6 +DOPAD_DEL --- 3.636 91.PADDO to 91.PAD RA[6] + -------- + 7.449 (61.3% logic, 38.7% route), 3 logic levels. + +Report: 9.953ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.547ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[5] + + Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels. + + Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. + + Constraint Details: + 2.504ns delay RCLK to SLICE_64 and + 7.449ns delay SLICE_64 to RA[5] (totaling 9.953ns) meets + 12.500ns offset RCLK to RA[5] by 2.547ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 2.504 (42.5% logic, 57.5% route), 1 logic levels. + + Data path SLICE_64 to RA[5]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_98.C1 nRowColSel +CTOF_DEL --- 0.371 SLICE_98.C1 to SLICE_98.F1 SLICE_98 +ROUTE 1 e 1.441 SLICE_98.F1 to 95.PADDO RA_c_5 +DOPAD_DEL --- 3.636 95.PADDO to 95.PAD RA[5] + -------- + 7.449 (61.3% logic, 38.7% route), 3 logic levels. + +Report: 9.953ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.427ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[4] + + Data Path Delay: 6.569ns (69.5% logic, 30.5% route), 3 logic levels. + + Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. + + Constraint Details: + 2.504ns delay RCLK to SLICE_64 and + 6.569ns delay SLICE_64 to RA[4] (totaling 9.073ns) meets + 12.500ns offset RCLK to RA[4] by 3.427ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 2.504 (42.5% logic, 57.5% route), 1 logic levels. + + Data path SLICE_64 to RA[4]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 0.561 SLICE_64.Q0 to SLICE_64.C1 nRowColSel +CTOF_DEL --- 0.371 SLICE_64.C1 to SLICE_64.F1 SLICE_64 +ROUTE 1 e 1.441 SLICE_64.F1 to 99.PADDO RA_c_4 +DOPAD_DEL --- 3.636 99.PADDO to 99.PAD RA[4] + -------- + 6.569 (69.5% logic, 30.5% route), 3 logic levels. + +Report: 9.073ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.547ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[3] + + Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels. + + Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. + + Constraint Details: + 2.504ns delay RCLK to SLICE_64 and + 7.449ns delay SLICE_64 to RA[3] (totaling 9.953ns) meets + 12.500ns offset RCLK to RA[3] by 2.547ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 2.504 (42.5% logic, 57.5% route), 1 logic levels. + + Data path SLICE_64 to RA[3]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_94.C1 nRowColSel +CTOF_DEL --- 0.371 SLICE_94.C1 to SLICE_94.F1 SLICE_94 +ROUTE 1 e 1.441 SLICE_94.F1 to 97.PADDO RA_c_3 +DOPAD_DEL --- 3.636 97.PADDO to 97.PAD RA[3] + -------- + 7.449 (61.3% logic, 38.7% route), 3 logic levels. + +Report: 9.953ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.547ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[2] + + Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels. + + Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. + + Constraint Details: + 2.504ns delay RCLK to SLICE_64 and + 7.449ns delay SLICE_64 to RA[2] (totaling 9.953ns) meets + 12.500ns offset RCLK to RA[2] by 2.547ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 2.504 (42.5% logic, 57.5% route), 1 logic levels. + + Data path SLICE_64 to RA[2]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_95.C1 nRowColSel +CTOF_DEL --- 0.371 SLICE_95.C1 to SLICE_95.F1 SLICE_95 +ROUTE 1 e 1.441 SLICE_95.F1 to 94.PADDO RA_c_2 +DOPAD_DEL --- 3.636 94.PADDO to 94.PAD RA[2] + -------- + 7.449 (61.3% logic, 38.7% route), 3 logic levels. + +Report: 9.953ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.547ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[1] + + Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels. + + Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. + + Constraint Details: + 2.504ns delay RCLK to SLICE_64 and + 7.449ns delay SLICE_64 to RA[1] (totaling 9.953ns) meets + 12.500ns offset RCLK to RA[1] by 2.547ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 2.504 (42.5% logic, 57.5% route), 1 logic levels. + + Data path SLICE_64 to RA[1]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_94.C0 nRowColSel +CTOF_DEL --- 0.371 SLICE_94.C0 to SLICE_94.F0 SLICE_94 +ROUTE 1 e 1.441 SLICE_94.F0 to 89.PADDO RA_c_1 +DOPAD_DEL --- 3.636 89.PADDO to 89.PAD RA[1] + -------- + 7.449 (61.3% logic, 38.7% route), 3 logic levels. + +Report: 9.953ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.547ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[0] + + Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels. + + Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. + + Constraint Details: + 2.504ns delay RCLK to SLICE_64 and + 7.449ns delay SLICE_64 to RA[0] (totaling 9.953ns) meets + 12.500ns offset RCLK to RA[0] by 2.547ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 2.504 (42.5% logic, 57.5% route), 1 logic levels. + + Data path SLICE_64 to RA[0]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_92.C1 nRowColSel +CTOF_DEL --- 0.371 SLICE_92.C1 to SLICE_92.F1 SLICE_92 +ROUTE 1 e 1.441 SLICE_92.F1 to 98.PADDO RA_c_0 +DOPAD_DEL --- 3.636 98.PADDO to 98.PAD RA[0] + -------- + 7.449 (61.3% logic, 38.7% route), 3 logic levels. + +Report: 9.953ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 4.359ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRCS_369 (from RCLK_c +) + Destination: Port Pad nRCS + + Data Path Delay: 5.637ns (74.4% logic, 25.6% route), 2 logic levels. + + Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. + + Constraint Details: + 2.504ns delay RCLK to SLICE_60 and + 5.637ns delay SLICE_60 to nRCS (totaling 8.141ns) meets + 12.500ns offset RCLK to nRCS by 4.359ns + + Physical Path Details: + + Clock path RCLK to SLICE_60: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 e 1.441 86.PADDI to SLICE_60.CLK RCLK_c + -------- + 2.504 (42.5% logic, 57.5% route), 1 logic levels. + + Data path SLICE_60 to nRCS: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_60.CLK to SLICE_60.Q0 SLICE_60 (from RCLK_c) +ROUTE 1 e 1.441 SLICE_60.Q0 to 77.PADDO nRCS_c +DOPAD_DEL --- 3.636 77.PADDO to 77.PAD nRCS + -------- + 5.637 (74.4% logic, 25.6% route), 2 logic levels. + +Report: 8.141ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 4.359ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RCKE_368 (from RCLK_c +) + Destination: Port Pad RCKE + + Data Path Delay: 5.637ns (74.4% logic, 25.6% route), 2 logic levels. + + Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. + + Constraint Details: + 2.504ns delay RCLK to SLICE_34 and + 5.637ns delay SLICE_34 to RCKE (totaling 8.141ns) meets + 12.500ns offset RCLK to RCKE by 4.359ns + + Physical Path Details: + + Clock path RCLK to SLICE_34: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 e 1.441 86.PADDI to SLICE_34.CLK RCLK_c + -------- + 2.504 (42.5% logic, 57.5% route), 1 logic levels. + + Data path SLICE_34 to RCKE: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_34.CLK to SLICE_34.Q0 SLICE_34 (from RCLK_c) +ROUTE 4 e 1.441 SLICE_34.Q0 to 82.PADDO RCKE_c +DOPAD_DEL --- 3.636 82.PADDO to 82.PAD RCKE + -------- + 5.637 (74.4% logic, 25.6% route), 2 logic levels. + +Report: 8.141ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 4.359ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRWE_372 (from RCLK_c +) + Destination: Port Pad nRWE + + Data Path Delay: 5.637ns (74.4% logic, 25.6% route), 2 logic levels. + + Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. + + Constraint Details: + 2.504ns delay RCLK to SLICE_63 and + 5.637ns delay SLICE_63 to nRWE (totaling 8.141ns) meets + 12.500ns offset RCLK to nRWE by 4.359ns + + Physical Path Details: + + Clock path RCLK to SLICE_63: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 e 1.441 86.PADDI to SLICE_63.CLK RCLK_c + -------- + 2.504 (42.5% logic, 57.5% route), 1 logic levels. + + Data path SLICE_63 to nRWE: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) +ROUTE 1 e 1.441 SLICE_63.Q0 to 72.PADDO nRWE_c +DOPAD_DEL --- 3.636 72.PADDO to 72.PAD nRWE + -------- + 5.637 (74.4% logic, 25.6% route), 2 logic levels. + +Report: 8.141ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 4.359ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRRAS_370 (from RCLK_c +) + Destination: Port Pad nRRAS + + Data Path Delay: 5.637ns (74.4% logic, 25.6% route), 2 logic levels. + + Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. + + Constraint Details: + 2.504ns delay RCLK to SLICE_61 and + 5.637ns delay SLICE_61 to nRRAS (totaling 8.141ns) meets + 12.500ns offset RCLK to nRRAS by 4.359ns + + Physical Path Details: + + Clock path RCLK to SLICE_61: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 e 1.441 86.PADDI to SLICE_61.CLK RCLK_c + -------- + 2.504 (42.5% logic, 57.5% route), 1 logic levels. + + Data path SLICE_61 to nRRAS: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_61.CLK to SLICE_61.Q0 SLICE_61 (from RCLK_c) +ROUTE 2 e 1.441 SLICE_61.Q0 to 73.PADDO nRRAS_c +DOPAD_DEL --- 3.636 73.PADDO to 73.PAD nRRAS + -------- + 5.637 (74.4% logic, 25.6% route), 2 logic levels. + +Report: 8.141ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 4.359ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRCAS_371 (from RCLK_c +) + Destination: Port Pad nRCAS + + Data Path Delay: 5.637ns (74.4% logic, 25.6% route), 2 logic levels. + + Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. + + Constraint Details: + 2.504ns delay RCLK to SLICE_58 and + 5.637ns delay SLICE_58 to nRCAS (totaling 8.141ns) meets + 12.500ns offset RCLK to nRCAS by 4.359ns + + Physical Path Details: + + Clock path RCLK to SLICE_58: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 e 1.441 86.PADDI to SLICE_58.CLK RCLK_c + -------- + 2.504 (42.5% logic, 57.5% route), 1 logic levels. + + Data path SLICE_58 to nRCAS: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_58.CLK to SLICE_58.Q0 SLICE_58 (from RCLK_c) +ROUTE 1 e 1.441 SLICE_58.Q0 to 78.PADDO nRCAS_c +DOPAD_DEL --- 3.636 78.PADDO to 78.PAD nRCAS + -------- + 5.637 (74.4% logic, 25.6% route), 2 logic levels. + +Report: 8.141ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.547ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RDQMH + + Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels. + + Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. + + Constraint Details: + 2.504ns delay RCLK to SLICE_64 and + 7.449ns delay SLICE_64 to RDQMH (totaling 9.953ns) meets + 12.500ns offset RCLK to RDQMH by 2.547ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 2.504 (42.5% logic, 57.5% route), 1 logic levels. + + Data path SLICE_64 to RDQMH: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_88.B0 nRowColSel +CTOF_DEL --- 0.371 SLICE_88.B0 to SLICE_88.F0 SLICE_88 +ROUTE 1 e 1.441 SLICE_88.F0 to 76.PADDO RDQMH_c +DOPAD_DEL --- 3.636 76.PADDO to 76.PAD RDQMH + -------- + 7.449 (61.3% logic, 38.7% route), 3 logic levels. + +Report: 9.953ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.547ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RDQML + + Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels. + + Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. + + Constraint Details: + 2.504ns delay RCLK to SLICE_64 and + 7.449ns delay SLICE_64 to RDQML (totaling 9.953ns) meets + 12.500ns offset RCLK to RDQML by 2.547ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 2.504 (42.5% logic, 57.5% route), 1 logic levels. + + Data path SLICE_64 to RDQML: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_92.B0 nRowColSel +CTOF_DEL --- 0.371 SLICE_92.B0 to SLICE_92.F0 SLICE_92 +ROUTE 1 e 1.441 SLICE_92.F0 to 61.PADDO RDQML_c +DOPAD_DEL --- 3.636 61.PADDO to 61.PAD RDQML + -------- + 7.449 (61.3% logic, 38.7% route), 3 logic levels. + +Report: 9.953ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +PERIOD NET "PHI2_c" 350.000000 ns ; | 350.000 ns| 26.276 ns| 7 + | | | +PERIOD NET "nCCAS_c" 350.000000 ns ; | 350.000 ns| 2.000 ns| 0 + | | | +PERIOD NET "nCRAS_c" 350.000000 ns ; | 350.000 ns| 2.000 ns| 0 + | | | +PERIOD NET "RCLK_c" 16.000000 ns ; | 16.000 ns| 10.425 ns| 6 + | | | +CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[0]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[7]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[6]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[5]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[4]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[3]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[2]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[1]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 8.141 ns| 2 + | | | +CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 9.073 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3 + | | | +CLOCK_TO_OUT PORT "nRCS" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 8.141 ns| 2 + | | | +CLOCK_TO_OUT PORT "RCKE" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 8.141 ns| 2 + | | | +CLOCK_TO_OUT PORT "nRWE" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 8.141 ns| 2 + | | | +CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 8.141 ns| 2 + | | | +CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 8.141 ns| 2 + | | | +CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3 + | | | +CLOCK_TO_OUT PORT "RDQML" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3 + | | | +CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +---------------------------------------------------------------------------- + + +All preferences were met. + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 39 + Covered under: PERIOD NET "RCLK_c" 16.000000 ns ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: PERIOD NET "PHI2_c" 350.000000 ns ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Setup): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 526 paths, 6 nets, and 420 connections (67.96% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2 +Mon Aug 16 21:32:27 2021 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf +Design file: ram2gs_lcmxo256c_impl1_map.ncd +Preference file: ram2gs_lcmxo256c_impl1.prf +Device,speed: LCMXO256C,M +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + +Derating parameters +------------------- +Voltage: 3.300 V + + + +================================================================================ +Preference: PERIOD NET "PHI2_c" 350.000000 ns ; + 113 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.485ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q ADSubmitted_380 (from PHI2_c -) + Destination: FF Data in ADSubmitted_380 (to PHI2_c -) + + Delay: 0.462ns (56.7% logic, 43.3% route), 2 logic levels. + + Constraint Details: + + 0.462ns physical path delay SLICE_9 to SLICE_9 meets + -0.023ns DIN_HLD and + 0.000ns delay constraint requirement (totaling -0.023ns) by 0.485ns + + Physical Path Details: + + Data path SLICE_9 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.170 SLICE_9.CLK to SLICE_9.Q0 SLICE_9 (from PHI2_c) +ROUTE 2 e 0.199 SLICE_9.Q0 to SLICE_9.C0 ADSubmitted +CTOF_DEL --- 0.092 SLICE_9.C0 to SLICE_9.F0 SLICE_9 +ROUTE 1 e 0.001 SLICE_9.F0 to SLICE_9.DI0 n1361 (to PHI2_c) + -------- + 0.462 (56.7% logic, 43.3% route), 2 logic levels. + + +================================================================================ +Preference: PERIOD NET "nCCAS_c" 350.000000 ns ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: PERIOD NET "nCRAS_c" 350.000000 ns ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: PERIOD NET "RCLK_c" 16.000000 ns ; + 395 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.377ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i11 (from RCLK_c +) + Destination: FF Data in IS_FSM__i12 (to RCLK_c +) + + Delay: 0.356ns (44.1% logic, 55.9% route), 1 logic levels. + + Constraint Details: + + 0.356ns physical path delay SLICE_72 to SLICE_72 meets + -0.021ns M_HLD and + 0.000ns delay constraint requirement (totaling -0.021ns) by 0.377ns + + Physical Path Details: + + Data path SLICE_72 to SLICE_72: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 SLICE_72.CLK to SLICE_72.Q0 SLICE_72 (from RCLK_c) +ROUTE 1 e 0.199 SLICE_72.Q0 to SLICE_72.M1 n702 (to RCLK_c) + -------- + 0.356 (44.1% logic, 55.9% route), 1 logic levels. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.559ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RA10_373 (from RCLK_c +) + Destination: Port Pad RA[10] + + Data Path Delay: 1.780ns (71.1% logic, 28.9% route), 2 logic levels. + + Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. + + Constraint Details: + 0.779ns delay RCLK to SLICE_55 and + 1.780ns delay SLICE_55 to RA[10] (totaling 2.559ns) meets + 0.000ns hold offset RCLK to RA[10] by 2.559ns + + Physical Path Details: + + Clock path RCLK to SLICE_55: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 e 0.515 86.PADDI to SLICE_55.CLK RCLK_c + -------- + 0.779 (33.9% logic, 66.1% route), 1 logic levels. + + Data path SLICE_55 to RA[10]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 SLICE_55.CLK to SLICE_55.Q0 SLICE_55 (from RCLK_c) +ROUTE 1 e 0.515 SLICE_55.Q0 to 87.PADDO n980 +DOPAD_DEL --- 1.108 87.PADDO to 87.PAD RA[10] + -------- + 1.780 (71.1% logic, 28.9% route), 2 logic levels. + +Report: 2.559ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.166ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[9] + + Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels. + + Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. + + Constraint Details: + 0.779ns delay RCLK to SLICE_64 and + 2.387ns delay SLICE_64 to RA[9] (totaling 3.166ns) meets + 0.000ns hold offset RCLK to RA[9] by 3.166ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 0.779 (33.9% logic, 66.1% route), 1 logic levels. + + Data path SLICE_64 to RA[9]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_88.C1 nRowColSel +CTOF_DEL --- 0.092 SLICE_88.C1 to SLICE_88.F1 SLICE_88 +ROUTE 1 e 0.515 SLICE_88.F1 to 85.PADDO RA_c_9 +DOPAD_DEL --- 1.108 85.PADDO to 85.PAD RA[9] + -------- + 2.387 (56.8% logic, 43.2% route), 3 logic levels. + +Report: 3.166ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.166ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[8] + + Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels. + + Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. + + Constraint Details: + 0.779ns delay RCLK to SLICE_64 and + 2.387ns delay SLICE_64 to RA[8] (totaling 3.166ns) meets + 0.000ns hold offset RCLK to RA[8] by 3.166ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 0.779 (33.9% logic, 66.1% route), 1 logic levels. + + Data path SLICE_64 to RA[8]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_95.C0 nRowColSel +CTOF_DEL --- 0.092 SLICE_95.C0 to SLICE_95.F0 SLICE_95 +ROUTE 1 e 0.515 SLICE_95.F0 to 96.PADDO RA_c_8 +DOPAD_DEL --- 1.108 96.PADDO to 96.PAD RA[8] + -------- + 2.387 (56.8% logic, 43.2% route), 3 logic levels. + +Report: 3.166ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.166ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[7] + + Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels. + + Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. + + Constraint Details: + 0.779ns delay RCLK to SLICE_64 and + 2.387ns delay SLICE_64 to RA[7] (totaling 3.166ns) meets + 0.000ns hold offset RCLK to RA[7] by 3.166ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 0.779 (33.9% logic, 66.1% route), 1 logic levels. + + Data path SLICE_64 to RA[7]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_97.C0 nRowColSel +CTOF_DEL --- 0.092 SLICE_97.C0 to SLICE_97.F0 SLICE_97 +ROUTE 1 e 0.515 SLICE_97.F0 to 100.PADDO RA_c_7 +DOPAD_DEL --- 1.108 100.PADDO to 100.PAD RA[7] + -------- + 2.387 (56.8% logic, 43.2% route), 3 logic levels. + +Report: 3.166ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.166ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[6] + + Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels. + + Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. + + Constraint Details: + 0.779ns delay RCLK to SLICE_64 and + 2.387ns delay SLICE_64 to RA[6] (totaling 3.166ns) meets + 0.000ns hold offset RCLK to RA[6] by 3.166ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 0.779 (33.9% logic, 66.1% route), 1 logic levels. + + Data path SLICE_64 to RA[6]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_98.C0 nRowColSel +CTOF_DEL --- 0.092 SLICE_98.C0 to SLICE_98.F0 SLICE_98 +ROUTE 1 e 0.515 SLICE_98.F0 to 91.PADDO RA_c_6 +DOPAD_DEL --- 1.108 91.PADDO to 91.PAD RA[6] + -------- + 2.387 (56.8% logic, 43.2% route), 3 logic levels. + +Report: 3.166ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.166ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[5] + + Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels. + + Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. + + Constraint Details: + 0.779ns delay RCLK to SLICE_64 and + 2.387ns delay SLICE_64 to RA[5] (totaling 3.166ns) meets + 0.000ns hold offset RCLK to RA[5] by 3.166ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 0.779 (33.9% logic, 66.1% route), 1 logic levels. + + Data path SLICE_64 to RA[5]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_98.C1 nRowColSel +CTOF_DEL --- 0.092 SLICE_98.C1 to SLICE_98.F1 SLICE_98 +ROUTE 1 e 0.515 SLICE_98.F1 to 95.PADDO RA_c_5 +DOPAD_DEL --- 1.108 95.PADDO to 95.PAD RA[5] + -------- + 2.387 (56.8% logic, 43.2% route), 3 logic levels. + +Report: 3.166ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.850ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[4] + + Data Path Delay: 2.071ns (65.5% logic, 34.5% route), 3 logic levels. + + Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. + + Constraint Details: + 0.779ns delay RCLK to SLICE_64 and + 2.071ns delay SLICE_64 to RA[4] (totaling 2.850ns) meets + 0.000ns hold offset RCLK to RA[4] by 2.850ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 0.779 (33.9% logic, 66.1% route), 1 logic levels. + + Data path SLICE_64 to RA[4]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 0.199 SLICE_64.Q0 to SLICE_64.C1 nRowColSel +CTOF_DEL --- 0.092 SLICE_64.C1 to SLICE_64.F1 SLICE_64 +ROUTE 1 e 0.515 SLICE_64.F1 to 99.PADDO RA_c_4 +DOPAD_DEL --- 1.108 99.PADDO to 99.PAD RA[4] + -------- + 2.071 (65.5% logic, 34.5% route), 3 logic levels. + +Report: 2.850ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.166ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[3] + + Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels. + + Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. + + Constraint Details: + 0.779ns delay RCLK to SLICE_64 and + 2.387ns delay SLICE_64 to RA[3] (totaling 3.166ns) meets + 0.000ns hold offset RCLK to RA[3] by 3.166ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 0.779 (33.9% logic, 66.1% route), 1 logic levels. + + Data path SLICE_64 to RA[3]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_94.C1 nRowColSel +CTOF_DEL --- 0.092 SLICE_94.C1 to SLICE_94.F1 SLICE_94 +ROUTE 1 e 0.515 SLICE_94.F1 to 97.PADDO RA_c_3 +DOPAD_DEL --- 1.108 97.PADDO to 97.PAD RA[3] + -------- + 2.387 (56.8% logic, 43.2% route), 3 logic levels. + +Report: 3.166ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.166ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[2] + + Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels. + + Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. + + Constraint Details: + 0.779ns delay RCLK to SLICE_64 and + 2.387ns delay SLICE_64 to RA[2] (totaling 3.166ns) meets + 0.000ns hold offset RCLK to RA[2] by 3.166ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 0.779 (33.9% logic, 66.1% route), 1 logic levels. + + Data path SLICE_64 to RA[2]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_95.C1 nRowColSel +CTOF_DEL --- 0.092 SLICE_95.C1 to SLICE_95.F1 SLICE_95 +ROUTE 1 e 0.515 SLICE_95.F1 to 94.PADDO RA_c_2 +DOPAD_DEL --- 1.108 94.PADDO to 94.PAD RA[2] + -------- + 2.387 (56.8% logic, 43.2% route), 3 logic levels. + +Report: 3.166ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.166ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[1] + + Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels. + + Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. + + Constraint Details: + 0.779ns delay RCLK to SLICE_64 and + 2.387ns delay SLICE_64 to RA[1] (totaling 3.166ns) meets + 0.000ns hold offset RCLK to RA[1] by 3.166ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 0.779 (33.9% logic, 66.1% route), 1 logic levels. + + Data path SLICE_64 to RA[1]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_94.C0 nRowColSel +CTOF_DEL --- 0.092 SLICE_94.C0 to SLICE_94.F0 SLICE_94 +ROUTE 1 e 0.515 SLICE_94.F0 to 89.PADDO RA_c_1 +DOPAD_DEL --- 1.108 89.PADDO to 89.PAD RA[1] + -------- + 2.387 (56.8% logic, 43.2% route), 3 logic levels. + +Report: 3.166ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.166ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[0] + + Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels. + + Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. + + Constraint Details: + 0.779ns delay RCLK to SLICE_64 and + 2.387ns delay SLICE_64 to RA[0] (totaling 3.166ns) meets + 0.000ns hold offset RCLK to RA[0] by 3.166ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 0.779 (33.9% logic, 66.1% route), 1 logic levels. + + Data path SLICE_64 to RA[0]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_92.C1 nRowColSel +CTOF_DEL --- 0.092 SLICE_92.C1 to SLICE_92.F1 SLICE_92 +ROUTE 1 e 0.515 SLICE_92.F1 to 98.PADDO RA_c_0 +DOPAD_DEL --- 1.108 98.PADDO to 98.PAD RA[0] + -------- + 2.387 (56.8% logic, 43.2% route), 3 logic levels. + +Report: 3.166ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.559ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRCS_369 (from RCLK_c +) + Destination: Port Pad nRCS + + Data Path Delay: 1.780ns (71.1% logic, 28.9% route), 2 logic levels. + + Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. + + Constraint Details: + 0.779ns delay RCLK to SLICE_60 and + 1.780ns delay SLICE_60 to nRCS (totaling 2.559ns) meets + 0.000ns hold offset RCLK to nRCS by 2.559ns + + Physical Path Details: + + Clock path RCLK to SLICE_60: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 e 0.515 86.PADDI to SLICE_60.CLK RCLK_c + -------- + 0.779 (33.9% logic, 66.1% route), 1 logic levels. + + Data path SLICE_60 to nRCS: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 SLICE_60.CLK to SLICE_60.Q0 SLICE_60 (from RCLK_c) +ROUTE 1 e 0.515 SLICE_60.Q0 to 77.PADDO nRCS_c +DOPAD_DEL --- 1.108 77.PADDO to 77.PAD nRCS + -------- + 1.780 (71.1% logic, 28.9% route), 2 logic levels. + +Report: 2.559ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.559ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RCKE_368 (from RCLK_c +) + Destination: Port Pad RCKE + + Data Path Delay: 1.780ns (71.1% logic, 28.9% route), 2 logic levels. + + Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. + + Constraint Details: + 0.779ns delay RCLK to SLICE_34 and + 1.780ns delay SLICE_34 to RCKE (totaling 2.559ns) meets + 0.000ns hold offset RCLK to RCKE by 2.559ns + + Physical Path Details: + + Clock path RCLK to SLICE_34: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 e 0.515 86.PADDI to SLICE_34.CLK RCLK_c + -------- + 0.779 (33.9% logic, 66.1% route), 1 logic levels. + + Data path SLICE_34 to RCKE: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 SLICE_34.CLK to SLICE_34.Q0 SLICE_34 (from RCLK_c) +ROUTE 4 e 0.515 SLICE_34.Q0 to 82.PADDO RCKE_c +DOPAD_DEL --- 1.108 82.PADDO to 82.PAD RCKE + -------- + 1.780 (71.1% logic, 28.9% route), 2 logic levels. + +Report: 2.559ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.559ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRWE_372 (from RCLK_c +) + Destination: Port Pad nRWE + + Data Path Delay: 1.780ns (71.1% logic, 28.9% route), 2 logic levels. + + Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. + + Constraint Details: + 0.779ns delay RCLK to SLICE_63 and + 1.780ns delay SLICE_63 to nRWE (totaling 2.559ns) meets + 0.000ns hold offset RCLK to nRWE by 2.559ns + + Physical Path Details: + + Clock path RCLK to SLICE_63: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 e 0.515 86.PADDI to SLICE_63.CLK RCLK_c + -------- + 0.779 (33.9% logic, 66.1% route), 1 logic levels. + + Data path SLICE_63 to nRWE: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) +ROUTE 1 e 0.515 SLICE_63.Q0 to 72.PADDO nRWE_c +DOPAD_DEL --- 1.108 72.PADDO to 72.PAD nRWE + -------- + 1.780 (71.1% logic, 28.9% route), 2 logic levels. + +Report: 2.559ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.559ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRRAS_370 (from RCLK_c +) + Destination: Port Pad nRRAS + + Data Path Delay: 1.780ns (71.1% logic, 28.9% route), 2 logic levels. + + Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. + + Constraint Details: + 0.779ns delay RCLK to SLICE_61 and + 1.780ns delay SLICE_61 to nRRAS (totaling 2.559ns) meets + 0.000ns hold offset RCLK to nRRAS by 2.559ns + + Physical Path Details: + + Clock path RCLK to SLICE_61: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 e 0.515 86.PADDI to SLICE_61.CLK RCLK_c + -------- + 0.779 (33.9% logic, 66.1% route), 1 logic levels. + + Data path SLICE_61 to nRRAS: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 SLICE_61.CLK to SLICE_61.Q0 SLICE_61 (from RCLK_c) +ROUTE 2 e 0.515 SLICE_61.Q0 to 73.PADDO nRRAS_c +DOPAD_DEL --- 1.108 73.PADDO to 73.PAD nRRAS + -------- + 1.780 (71.1% logic, 28.9% route), 2 logic levels. + +Report: 2.559ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.559ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRCAS_371 (from RCLK_c +) + Destination: Port Pad nRCAS + + Data Path Delay: 1.780ns (71.1% logic, 28.9% route), 2 logic levels. + + Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. + + Constraint Details: + 0.779ns delay RCLK to SLICE_58 and + 1.780ns delay SLICE_58 to nRCAS (totaling 2.559ns) meets + 0.000ns hold offset RCLK to nRCAS by 2.559ns + + Physical Path Details: + + Clock path RCLK to SLICE_58: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 e 0.515 86.PADDI to SLICE_58.CLK RCLK_c + -------- + 0.779 (33.9% logic, 66.1% route), 1 logic levels. + + Data path SLICE_58 to nRCAS: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 SLICE_58.CLK to SLICE_58.Q0 SLICE_58 (from RCLK_c) +ROUTE 1 e 0.515 SLICE_58.Q0 to 78.PADDO nRCAS_c +DOPAD_DEL --- 1.108 78.PADDO to 78.PAD nRCAS + -------- + 1.780 (71.1% logic, 28.9% route), 2 logic levels. + +Report: 2.559ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.166ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RDQMH + + Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels. + + Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. + + Constraint Details: + 0.779ns delay RCLK to SLICE_64 and + 2.387ns delay SLICE_64 to RDQMH (totaling 3.166ns) meets + 0.000ns hold offset RCLK to RDQMH by 3.166ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 0.779 (33.9% logic, 66.1% route), 1 logic levels. + + Data path SLICE_64 to RDQMH: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_88.B0 nRowColSel +CTOF_DEL --- 0.092 SLICE_88.B0 to SLICE_88.F0 SLICE_88 +ROUTE 1 e 0.515 SLICE_88.F0 to 76.PADDO RDQMH_c +DOPAD_DEL --- 1.108 76.PADDO to 76.PAD RDQMH + -------- + 2.387 (56.8% logic, 43.2% route), 3 logic levels. + +Report: 3.166ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.166ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RDQML + + Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels. + + Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. + + Constraint Details: + 0.779ns delay RCLK to SLICE_64 and + 2.387ns delay SLICE_64 to RDQML (totaling 3.166ns) meets + 0.000ns hold offset RCLK to RDQML by 3.166ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c + -------- + 0.779 (33.9% logic, 66.1% route), 1 logic levels. + + Data path SLICE_64 to RDQML: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_92.B0 nRowColSel +CTOF_DEL --- 0.092 SLICE_92.B0 to SLICE_92.F0 SLICE_92 +ROUTE 1 e 0.515 SLICE_92.F0 to 61.PADDO RDQML_c +DOPAD_DEL --- 1.108 61.PADDO to 61.PAD RDQML + -------- + 2.387 (56.8% logic, 43.2% route), 3 logic levels. + +Report: 3.166ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference(MIN Delays) | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +PERIOD NET "PHI2_c" 350.000000 ns ; | -| -| 2 + | | | +PERIOD NET "nCCAS_c" 350.000000 ns ; | -| -| 0 + | | | +PERIOD NET "nCRAS_c" 350.000000 ns ; | -| -| 0 + | | | +PERIOD NET "RCLK_c" 16.000000 ns ; | -| -| 1 + | | | +CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[0]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[7]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[6]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[5]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[4]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[3]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[2]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[1]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.559 ns| 2 + | | | +CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.850 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3 + | | | +CLOCK_TO_OUT PORT "nRCS" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.559 ns| 2 + | | | +CLOCK_TO_OUT PORT "RCKE" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.559 ns| 2 + | | | +CLOCK_TO_OUT PORT "nRWE" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.559 ns| 2 + | | | +CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.559 ns| 2 + | | | +CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.559 ns| 2 + | | | +CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3 + | | | +CLOCK_TO_OUT PORT "RDQML" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3 + | | | +CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +---------------------------------------------------------------------------- + + +All preferences were met. + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 39 + Covered under: PERIOD NET "RCLK_c" 16.000000 ns ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: PERIOD NET "PHI2_c" 350.000000 ns ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 526 paths, 6 nets, and 420 connections (67.96% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 0 (setup), 0 (hold) +Score: 0 (setup), 0 (hold) +Cumulative negative slack: 0 (0+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.twr b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.twr new file mode 100644 index 0000000..b0d4521 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.twr @@ -0,0 +1,4355 @@ + +Loading design for application trce from file ram2gs_lcmxo256c_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 3 +Loading device for application trce from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2 +Mon Aug 16 21:32:34 2021 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO256C_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf +Design file: ram2gs_lcmxo256c_impl1.ncd +Preference file: ram2gs_lcmxo256c_impl1.prf +Device,speed: LCMXO256C,3 +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + +Derating parameters +------------------- +Voltage: 3.300 V + + + +================================================================================ +Preference: PERIOD NET "PHI2_c" 350.000000 ns ; + 113 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 161.925ns (weighted slack = 323.850ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i0 (from PHI2_c +) + Destination: FF Data in CmdUFMCS_385 (to PHI2_c -) + FF CmdUFMCLK_386 + + Delay: 12.810ns (21.7% logic, 78.3% route), 7 logic levels. + + Constraint Details: + + 12.810ns physical path delay SLICE_94 to SLICE_83 meets + 175.000ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 174.735ns) by 161.925ns + + Physical Path Details: + + Data path SLICE_94 to SLICE_83: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C3B.CLK to R2C3B.Q0 SLICE_94 (from PHI2_c) +ROUTE 1 1.643 R2C3B.Q0 to R5C2C.B0 Bank_0 +CTOF_DEL --- 0.371 R5C2C.B0 to R5C2C.F0 SLICE_82 +ROUTE 1 0.497 R5C2C.F0 to R5C2C.C1 n2166 +CTOF_DEL --- 0.371 R5C2C.C1 to R5C2C.F1 SLICE_82 +ROUTE 1 1.548 R5C2C.F1 to R5C5B.B1 n26 +CTOF_DEL --- 0.371 R5C5B.B1 to R5C5B.F1 SLICE_76 +ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285 +CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89 +ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290 +CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18 +ROUTE 3 1.504 R5C3C.F1 to R4C4A.A0 XOR8MEG_N_112 +CTOF_DEL --- 0.371 R4C4A.A0 to R4C4A.F0 SLICE_72 +ROUTE 2 2.034 R4C4A.F0 to R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c) + -------- + 12.810 (21.7% logic, 78.3% route), 7 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_94: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R2C3B.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_83: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R5C4B.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.080ns (weighted slack = 324.160ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i6 (from PHI2_c +) + Destination: FF Data in CmdUFMCS_385 (to PHI2_c -) + FF CmdUFMCLK_386 + + Delay: 12.655ns (22.0% logic, 78.0% route), 7 logic levels. + + Constraint Details: + + 12.655ns physical path delay SLICE_95 to SLICE_83 meets + 175.000ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 174.735ns) by 162.080ns + + Physical Path Details: + + Data path SLICE_95 to SLICE_83: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2C.CLK to R2C2C.Q0 SLICE_95 (from PHI2_c) +ROUTE 1 1.488 R2C2C.Q0 to R5C2C.A0 Bank_6 +CTOF_DEL --- 0.371 R5C2C.A0 to R5C2C.F0 SLICE_82 +ROUTE 1 0.497 R5C2C.F0 to R5C2C.C1 n2166 +CTOF_DEL --- 0.371 R5C2C.C1 to R5C2C.F1 SLICE_82 +ROUTE 1 1.548 R5C2C.F1 to R5C5B.B1 n26 +CTOF_DEL --- 0.371 R5C5B.B1 to R5C5B.F1 SLICE_76 +ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285 +CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89 +ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290 +CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18 +ROUTE 3 1.504 R5C3C.F1 to R4C4A.A0 XOR8MEG_N_112 +CTOF_DEL --- 0.371 R4C4A.A0 to R4C4A.F0 SLICE_72 +ROUTE 2 2.034 R4C4A.F0 to R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c) + -------- + 12.655 (22.0% logic, 78.0% route), 7 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_95: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R2C2C.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_83: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R5C4B.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.409ns (weighted slack = 324.818ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i0 (from PHI2_c +) + Destination: FF Data in CmdSubmitted_384 (to PHI2_c -) + + Delay: 12.326ns (22.6% logic, 77.4% route), 7 logic levels. + + Constraint Details: + + 12.326ns physical path delay SLICE_94 to SLICE_19 meets + 175.000ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 174.735ns) by 162.409ns + + Physical Path Details: + + Data path SLICE_94 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C3B.CLK to R2C3B.Q0 SLICE_94 (from PHI2_c) +ROUTE 1 1.643 R2C3B.Q0 to R5C2C.B0 Bank_0 +CTOF_DEL --- 0.371 R5C2C.B0 to R5C2C.F0 SLICE_82 +ROUTE 1 0.497 R5C2C.F0 to R5C2C.C1 n2166 +CTOF_DEL --- 0.371 R5C2C.C1 to R5C2C.F1 SLICE_82 +ROUTE 1 1.548 R5C2C.F1 to R5C5B.B1 n26 +CTOF_DEL --- 0.371 R5C5B.B1 to R5C5B.F1 SLICE_76 +ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285 +CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89 +ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290 +CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18 +ROUTE 3 1.504 R5C3C.F1 to R4C4D.A0 XOR8MEG_N_112 +CTOF_DEL --- 0.371 R4C4D.A0 to R4C4D.F0 SLICE_90 +ROUTE 2 1.550 R4C4D.F0 to R5C5A.CE PHI2_N_114_enable_6 (to PHI2_c) + -------- + 12.326 (22.6% logic, 77.4% route), 7 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_94: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R2C3B.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R5C5A.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.416ns (weighted slack = 324.832ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i0 (from PHI2_c +) + Destination: FF Data in CmdUFMSDI_387 (to PHI2_c -) + + Delay: 12.319ns (22.6% logic, 77.4% route), 7 logic levels. + + Constraint Details: + + 12.319ns physical path delay SLICE_94 to SLICE_88 meets + 175.000ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 174.735ns) by 162.416ns + + Physical Path Details: + + Data path SLICE_94 to SLICE_88: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C3B.CLK to R2C3B.Q0 SLICE_94 (from PHI2_c) +ROUTE 1 1.643 R2C3B.Q0 to R5C2C.B0 Bank_0 +CTOF_DEL --- 0.371 R5C2C.B0 to R5C2C.F0 SLICE_82 +ROUTE 1 0.497 R5C2C.F0 to R5C2C.C1 n2166 +CTOF_DEL --- 0.371 R5C2C.C1 to R5C2C.F1 SLICE_82 +ROUTE 1 1.548 R5C2C.F1 to R5C5B.B1 n26 +CTOF_DEL --- 0.371 R5C5B.B1 to R5C5B.F1 SLICE_76 +ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285 +CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89 +ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290 +CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18 +ROUTE 3 1.504 R5C3C.F1 to R4C4A.A0 XOR8MEG_N_112 +CTOF_DEL --- 0.371 R4C4A.A0 to R4C4A.F0 SLICE_72 +ROUTE 2 1.543 R4C4A.F0 to R2C4A.CE PHI2_N_114_enable_7 (to PHI2_c) + -------- + 12.319 (22.6% logic, 77.4% route), 7 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_94: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R2C3B.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_88: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R2C4A.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.564ns (weighted slack = 325.128ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i6 (from PHI2_c +) + Destination: FF Data in CmdSubmitted_384 (to PHI2_c -) + + Delay: 12.171ns (22.9% logic, 77.1% route), 7 logic levels. + + Constraint Details: + + 12.171ns physical path delay SLICE_95 to SLICE_19 meets + 175.000ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 174.735ns) by 162.564ns + + Physical Path Details: + + Data path SLICE_95 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2C.CLK to R2C2C.Q0 SLICE_95 (from PHI2_c) +ROUTE 1 1.488 R2C2C.Q0 to R5C2C.A0 Bank_6 +CTOF_DEL --- 0.371 R5C2C.A0 to R5C2C.F0 SLICE_82 +ROUTE 1 0.497 R5C2C.F0 to R5C2C.C1 n2166 +CTOF_DEL --- 0.371 R5C2C.C1 to R5C2C.F1 SLICE_82 +ROUTE 1 1.548 R5C2C.F1 to R5C5B.B1 n26 +CTOF_DEL --- 0.371 R5C5B.B1 to R5C5B.F1 SLICE_76 +ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285 +CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89 +ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290 +CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18 +ROUTE 3 1.504 R5C3C.F1 to R4C4D.A0 XOR8MEG_N_112 +CTOF_DEL --- 0.371 R4C4D.A0 to R4C4D.F0 SLICE_90 +ROUTE 2 1.550 R4C4D.F0 to R5C5A.CE PHI2_N_114_enable_6 (to PHI2_c) + -------- + 12.171 (22.9% logic, 77.1% route), 7 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_95: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R2C2C.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R5C5A.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.571ns (weighted slack = 325.142ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i6 (from PHI2_c +) + Destination: FF Data in CmdUFMSDI_387 (to PHI2_c -) + + Delay: 12.164ns (22.9% logic, 77.1% route), 7 logic levels. + + Constraint Details: + + 12.164ns physical path delay SLICE_95 to SLICE_88 meets + 175.000ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 174.735ns) by 162.571ns + + Physical Path Details: + + Data path SLICE_95 to SLICE_88: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2C.CLK to R2C2C.Q0 SLICE_95 (from PHI2_c) +ROUTE 1 1.488 R2C2C.Q0 to R5C2C.A0 Bank_6 +CTOF_DEL --- 0.371 R5C2C.A0 to R5C2C.F0 SLICE_82 +ROUTE 1 0.497 R5C2C.F0 to R5C2C.C1 n2166 +CTOF_DEL --- 0.371 R5C2C.C1 to R5C2C.F1 SLICE_82 +ROUTE 1 1.548 R5C2C.F1 to R5C5B.B1 n26 +CTOF_DEL --- 0.371 R5C5B.B1 to R5C5B.F1 SLICE_76 +ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285 +CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89 +ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290 +CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18 +ROUTE 3 1.504 R5C3C.F1 to R4C4A.A0 XOR8MEG_N_112 +CTOF_DEL --- 0.371 R4C4A.A0 to R4C4A.F0 SLICE_72 +ROUTE 2 1.543 R4C4A.F0 to R2C4A.CE PHI2_N_114_enable_7 (to PHI2_c) + -------- + 12.164 (22.9% logic, 77.1% route), 7 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_95: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R2C2C.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_88: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R2C4A.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.606ns (weighted slack = 325.212ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i7 (from PHI2_c +) + Destination: FF Data in CmdUFMCS_385 (to PHI2_c -) + FF CmdUFMCLK_386 + + Delay: 12.129ns (23.0% logic, 77.0% route), 7 logic levels. + + Constraint Details: + + 12.129ns physical path delay SLICE_95 to SLICE_83 meets + 175.000ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 174.735ns) by 162.606ns + + Physical Path Details: + + Data path SLICE_95 to SLICE_83: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2C.CLK to R2C2C.Q1 SLICE_95 (from PHI2_c) +ROUTE 1 1.155 R2C2C.Q1 to R5C2B.D1 Bank_7 +CTOF_DEL --- 0.371 R5C2B.D1 to R5C2B.F1 SLICE_67 +ROUTE 1 0.304 R5C2B.F1 to R5C2C.D1 n2154 +CTOF_DEL --- 0.371 R5C2C.D1 to R5C2C.F1 SLICE_82 +ROUTE 1 1.548 R5C2C.F1 to R5C5B.B1 n26 +CTOF_DEL --- 0.371 R5C5B.B1 to R5C5B.F1 SLICE_76 +ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285 +CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89 +ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290 +CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18 +ROUTE 3 1.504 R5C3C.F1 to R4C4A.A0 XOR8MEG_N_112 +CTOF_DEL --- 0.371 R4C4A.A0 to R4C4A.F0 SLICE_72 +ROUTE 2 2.034 R4C4A.F0 to R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c) + -------- + 12.129 (23.0% logic, 77.0% route), 7 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_95: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R2C2C.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_83: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R5C4B.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.635ns (weighted slack = 325.270ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i1 (from PHI2_c +) + Destination: FF Data in CmdUFMCS_385 (to PHI2_c -) + FF CmdUFMCLK_386 + + Delay: 12.100ns (20.0% logic, 80.0% route), 6 logic levels. + + Constraint Details: + + 12.100ns physical path delay SLICE_94 to SLICE_83 meets + 175.000ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 174.735ns) by 162.635ns + + Physical Path Details: + + Data path SLICE_94 to SLICE_83: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C3B.CLK to R2C3B.Q1 SLICE_94 (from PHI2_c) +ROUTE 1 1.905 R2C3B.Q1 to R6C2B.C1 Bank_1 +CTOF_DEL --- 0.371 R6C2B.C1 to R6C2B.F1 SLICE_97 +ROUTE 1 1.444 R6C2B.F1 to R5C5B.C1 n2170 +CTOF_DEL --- 0.371 R5C5B.C1 to R5C5B.F1 SLICE_76 +ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285 +CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89 +ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290 +CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18 +ROUTE 3 1.504 R5C3C.F1 to R4C4A.A0 XOR8MEG_N_112 +CTOF_DEL --- 0.371 R4C4A.A0 to R4C4A.F0 SLICE_72 +ROUTE 2 2.034 R4C4A.F0 to R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c) + -------- + 12.100 (20.0% logic, 80.0% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_94: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R2C3B.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_83: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R5C4B.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.868ns (weighted slack = 325.736ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i5 (from PHI2_c +) + Destination: FF Data in CmdUFMCS_385 (to PHI2_c -) + FF CmdUFMCLK_386 + + Delay: 11.867ns (23.5% logic, 76.5% route), 7 logic levels. + + Constraint Details: + + 11.867ns physical path delay SLICE_97 to SLICE_83 meets + 175.000ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 174.735ns) by 162.868ns + + Physical Path Details: + + Data path SLICE_97 to SLICE_83: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R6C2B.CLK to R6C2B.Q1 SLICE_97 (from PHI2_c) +ROUTE 1 0.700 R6C2B.Q1 to R5C2C.D0 Bank_5 +CTOF_DEL --- 0.371 R5C2C.D0 to R5C2C.F0 SLICE_82 +ROUTE 1 0.497 R5C2C.F0 to R5C2C.C1 n2166 +CTOF_DEL --- 0.371 R5C2C.C1 to R5C2C.F1 SLICE_82 +ROUTE 1 1.548 R5C2C.F1 to R5C5B.B1 n26 +CTOF_DEL --- 0.371 R5C5B.B1 to R5C5B.F1 SLICE_76 +ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285 +CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89 +ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290 +CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18 +ROUTE 3 1.504 R5C3C.F1 to R4C4A.A0 XOR8MEG_N_112 +CTOF_DEL --- 0.371 R4C4A.A0 to R4C4A.F0 SLICE_72 +ROUTE 2 2.034 R4C4A.F0 to R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c) + -------- + 11.867 (23.5% logic, 76.5% route), 7 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_97: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R6C2B.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_83: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R5C4B.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.886ns (weighted slack = 325.772ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i0 (from PHI2_c +) + Destination: FF Data in XOR8MEG_381 (to PHI2_c -) + + Delay: 11.849ns (23.5% logic, 76.5% route), 7 logic levels. + + Constraint Details: + + 11.849ns physical path delay SLICE_94 to SLICE_96 meets + 175.000ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 174.735ns) by 162.886ns + + Physical Path Details: + + Data path SLICE_94 to SLICE_96: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C3B.CLK to R2C3B.Q0 SLICE_94 (from PHI2_c) +ROUTE 1 1.643 R2C3B.Q0 to R5C2C.B0 Bank_0 +CTOF_DEL --- 0.371 R5C2C.B0 to R5C2C.F0 SLICE_82 +ROUTE 1 0.497 R5C2C.F0 to R5C2C.C1 n2166 +CTOF_DEL --- 0.371 R5C2C.C1 to R5C2C.F1 SLICE_82 +ROUTE 1 1.548 R5C2C.F1 to R5C5B.B1 n26 +CTOF_DEL --- 0.371 R5C5B.B1 to R5C5B.F1 SLICE_76 +ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285 +CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89 +ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290 +CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18 +ROUTE 3 1.504 R5C3C.F1 to R4C4D.A1 XOR8MEG_N_112 +CTOF_DEL --- 0.371 R4C4D.A1 to R4C4D.F1 SLICE_90 +ROUTE 1 1.073 R4C4D.F1 to R3C4B.CE PHI2_N_114_enable_2 (to PHI2_c) + -------- + 11.849 (23.5% logic, 76.5% route), 7 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_94: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R2C3B.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_96: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R3C4B.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + +Report: 26.150ns is the minimum period for this preference. + + +================================================================================ +Preference: PERIOD NET "nCCAS_c" 350.000000 ns ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 348.000ns + The internal maximum frequency of the following component is 500.000 MHz + + Logical Details: Cell type Pin name Component name + + Destination: FSLICE CLK SLICE_76 + + Delay: 2.000ns -- based on Minimum Pulse Width + +Report: 2.000ns is the minimum period for this preference. + + +================================================================================ +Preference: PERIOD NET "nCRAS_c" 350.000000 ns ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 348.000ns + The internal maximum frequency of the following component is 500.000 MHz + + Logical Details: Cell type Pin name Component name + + Destination: FSLICE CLK SLICE_77 + + Delay: 2.000ns -- based on Minimum Pulse Width + +Report: 2.000ns is the minimum period for this preference. + + +================================================================================ +Preference: PERIOD NET "RCLK_c" 16.000000 ns ; + 395 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 7.566ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_577__i15 (from RCLK_c +) + Destination: FF Data in LEDEN_392 (to RCLK_c +) + + Delay: 8.190ns (29.5% logic, 70.5% route), 6 logic levels. + + Constraint Details: + + 8.190ns physical path delay SLICE_7 to SLICE_89 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.244ns CE_SET requirement (totaling 15.756ns) by 7.566ns + + Physical Path Details: + + Data path SLICE_7 to SLICE_89: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R8C4D.CLK to R8C4D.Q1 SLICE_7 (from RCLK_c) +ROUTE 3 1.929 R8C4D.Q1 to R7C5C.B0 FS_15 +CTOF_DEL --- 0.371 R7C5C.B0 to R7C5C.F0 SLICE_78 +ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10 +CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73 +ROUTE 4 0.712 R7C4A.F1 to R7C4A.B0 n2300 +CTOF_DEL --- 0.371 R7C4A.B0 to R7C4A.F0 SLICE_73 +ROUTE 1 0.304 R7C4A.F0 to R7C4B.D0 n11 +CTOF_DEL --- 0.371 R7C4B.D0 to R7C4B.F0 SLICE_75 +ROUTE 2 0.513 R7C4B.F0 to R7C4B.C1 n2119 +CTOF_DEL --- 0.371 R7C4B.C1 to R7C4B.F1 SLICE_75 +ROUTE 1 1.260 R7C4B.F1 to R6C3A.CE RCLK_c_enable_25 (to RCLK_c) + -------- + 8.190 (29.5% logic, 70.5% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_7: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R8C4D.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_89: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R6C3A.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 7.590ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_577__i15 (from RCLK_c +) + Destination: FF Data in n8MEGEN_391 (to RCLK_c +) + + Delay: 8.166ns (29.6% logic, 70.4% route), 6 logic levels. + + Constraint Details: + + 8.166ns physical path delay SLICE_7 to SLICE_56 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.244ns CE_SET requirement (totaling 15.756ns) by 7.590ns + + Physical Path Details: + + Data path SLICE_7 to SLICE_56: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R8C4D.CLK to R8C4D.Q1 SLICE_7 (from RCLK_c) +ROUTE 3 1.929 R8C4D.Q1 to R7C5C.B0 FS_15 +CTOF_DEL --- 0.371 R7C5C.B0 to R7C5C.F0 SLICE_78 +ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10 +CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73 +ROUTE 4 0.712 R7C4A.F1 to R7C4A.B0 n2300 +CTOF_DEL --- 0.371 R7C4A.B0 to R7C4A.F0 SLICE_73 +ROUTE 1 0.304 R7C4A.F0 to R7C4B.D0 n11 +CTOF_DEL --- 0.371 R7C4B.D0 to R7C4B.F0 SLICE_75 +ROUTE 2 1.102 R7C4B.F0 to R6C4C.B1 n2119 +CTOF_DEL --- 0.371 R6C4C.B1 to R6C4C.F1 SLICE_33 +ROUTE 1 0.647 R6C4C.F1 to R6C4B.CE RCLK_c_enable_7 (to RCLK_c) + -------- + 8.166 (29.6% logic, 70.4% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_7: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R8C4D.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_56: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R6C4B.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 7.984ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_577__i13 (from RCLK_c +) + Destination: FF Data in LEDEN_392 (to RCLK_c +) + + Delay: 7.772ns (31.1% logic, 68.9% route), 6 logic levels. + + Constraint Details: + + 7.772ns physical path delay SLICE_8 to SLICE_89 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.244ns CE_SET requirement (totaling 15.756ns) by 7.984ns + + Physical Path Details: + + Data path SLICE_8 to SLICE_89: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R8C4C.CLK to R8C4C.Q1 SLICE_8 (from RCLK_c) +ROUTE 3 1.511 R8C4C.Q1 to R7C5C.A0 FS_13 +CTOF_DEL --- 0.371 R7C5C.A0 to R7C5C.F0 SLICE_78 +ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10 +CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73 +ROUTE 4 0.712 R7C4A.F1 to R7C4A.B0 n2300 +CTOF_DEL --- 0.371 R7C4A.B0 to R7C4A.F0 SLICE_73 +ROUTE 1 0.304 R7C4A.F0 to R7C4B.D0 n11 +CTOF_DEL --- 0.371 R7C4B.D0 to R7C4B.F0 SLICE_75 +ROUTE 2 0.513 R7C4B.F0 to R7C4B.C1 n2119 +CTOF_DEL --- 0.371 R7C4B.C1 to R7C4B.F1 SLICE_75 +ROUTE 1 1.260 R7C4B.F1 to R6C3A.CE RCLK_c_enable_25 (to RCLK_c) + -------- + 7.772 (31.1% logic, 68.9% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_8: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R8C4C.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_89: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R6C3A.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 8.008ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_577__i13 (from RCLK_c +) + Destination: FF Data in n8MEGEN_391 (to RCLK_c +) + + Delay: 7.748ns (31.2% logic, 68.8% route), 6 logic levels. + + Constraint Details: + + 7.748ns physical path delay SLICE_8 to SLICE_56 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.244ns CE_SET requirement (totaling 15.756ns) by 8.008ns + + Physical Path Details: + + Data path SLICE_8 to SLICE_56: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R8C4C.CLK to R8C4C.Q1 SLICE_8 (from RCLK_c) +ROUTE 3 1.511 R8C4C.Q1 to R7C5C.A0 FS_13 +CTOF_DEL --- 0.371 R7C5C.A0 to R7C5C.F0 SLICE_78 +ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10 +CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73 +ROUTE 4 0.712 R7C4A.F1 to R7C4A.B0 n2300 +CTOF_DEL --- 0.371 R7C4A.B0 to R7C4A.F0 SLICE_73 +ROUTE 1 0.304 R7C4A.F0 to R7C4B.D0 n11 +CTOF_DEL --- 0.371 R7C4B.D0 to R7C4B.F0 SLICE_75 +ROUTE 2 1.102 R7C4B.F0 to R6C4C.B1 n2119 +CTOF_DEL --- 0.371 R6C4C.B1 to R6C4C.F1 SLICE_33 +ROUTE 1 0.647 R6C4C.F1 to R6C4B.CE RCLK_c_enable_7 (to RCLK_c) + -------- + 7.748 (31.2% logic, 68.8% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_8: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R8C4C.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_56: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R6C4B.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 8.123ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_577__i12 (from RCLK_c +) + Destination: FF Data in LEDEN_392 (to RCLK_c +) + + Delay: 7.633ns (31.6% logic, 68.4% route), 6 logic levels. + + Constraint Details: + + 7.633ns physical path delay SLICE_8 to SLICE_89 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.244ns CE_SET requirement (totaling 15.756ns) by 8.123ns + + Physical Path Details: + + Data path SLICE_8 to SLICE_89: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R8C4C.CLK to R8C4C.Q0 SLICE_8 (from RCLK_c) +ROUTE 3 1.372 R8C4C.Q0 to R7C5C.C0 FS_12 +CTOF_DEL --- 0.371 R7C5C.C0 to R7C5C.F0 SLICE_78 +ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10 +CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73 +ROUTE 4 0.712 R7C4A.F1 to R7C4A.B0 n2300 +CTOF_DEL --- 0.371 R7C4A.B0 to R7C4A.F0 SLICE_73 +ROUTE 1 0.304 R7C4A.F0 to R7C4B.D0 n11 +CTOF_DEL --- 0.371 R7C4B.D0 to R7C4B.F0 SLICE_75 +ROUTE 2 0.513 R7C4B.F0 to R7C4B.C1 n2119 +CTOF_DEL --- 0.371 R7C4B.C1 to R7C4B.F1 SLICE_75 +ROUTE 1 1.260 R7C4B.F1 to R6C3A.CE RCLK_c_enable_25 (to RCLK_c) + -------- + 7.633 (31.6% logic, 68.4% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_8: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R8C4C.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_89: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R6C3A.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 8.147ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_577__i12 (from RCLK_c +) + Destination: FF Data in n8MEGEN_391 (to RCLK_c +) + + Delay: 7.609ns (31.7% logic, 68.3% route), 6 logic levels. + + Constraint Details: + + 7.609ns physical path delay SLICE_8 to SLICE_56 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.244ns CE_SET requirement (totaling 15.756ns) by 8.147ns + + Physical Path Details: + + Data path SLICE_8 to SLICE_56: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R8C4C.CLK to R8C4C.Q0 SLICE_8 (from RCLK_c) +ROUTE 3 1.372 R8C4C.Q0 to R7C5C.C0 FS_12 +CTOF_DEL --- 0.371 R7C5C.C0 to R7C5C.F0 SLICE_78 +ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10 +CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73 +ROUTE 4 0.712 R7C4A.F1 to R7C4A.B0 n2300 +CTOF_DEL --- 0.371 R7C4A.B0 to R7C4A.F0 SLICE_73 +ROUTE 1 0.304 R7C4A.F0 to R7C4B.D0 n11 +CTOF_DEL --- 0.371 R7C4B.D0 to R7C4B.F0 SLICE_75 +ROUTE 2 1.102 R7C4B.F0 to R6C4C.B1 n2119 +CTOF_DEL --- 0.371 R6C4C.B1 to R6C4C.F1 SLICE_33 +ROUTE 1 0.647 R6C4C.F1 to R6C4B.CE RCLK_c_enable_7 (to RCLK_c) + -------- + 7.609 (31.7% logic, 68.3% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_8: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R8C4C.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_56: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R6C4B.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 8.262ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_577__i15 (from RCLK_c +) + Destination: FF Data in UFMCLK_389 (to RCLK_c +) + + Delay: 7.112ns (23.5% logic, 76.5% route), 4 logic levels. + + Constraint Details: + + 7.112ns physical path delay SLICE_7 to SLICE_42 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.626ns LSR_SET requirement (totaling 15.374ns) by 8.262ns + + Physical Path Details: + + Data path SLICE_7 to SLICE_42: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R8C4D.CLK to R8C4D.Q1 SLICE_7 (from RCLK_c) +ROUTE 3 1.929 R8C4D.Q1 to R7C5C.B0 FS_15 +CTOF_DEL --- 0.371 R7C5C.B0 to R7C5C.F0 SLICE_78 +ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10 +CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73 +ROUTE 4 0.915 R7C4A.F1 to R6C4A.C0 n2300 +CTOF_DEL --- 0.371 R6C4A.C0 to R6C4A.F0 SLICE_86 +ROUTE 2 1.538 R6C4A.F0 to R7C5A.LSR n2291 (to RCLK_c) + -------- + 7.112 (23.5% logic, 76.5% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_7: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R8C4D.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_42: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R7C5A.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 8.262ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_577__i15 (from RCLK_c +) + Destination: FF Data in UFMSDI_390 (to RCLK_c +) + + Delay: 7.112ns (23.5% logic, 76.5% route), 4 logic levels. + + Constraint Details: + + 7.112ns physical path delay SLICE_7 to SLICE_43 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.626ns LSR_SET requirement (totaling 15.374ns) by 8.262ns + + Physical Path Details: + + Data path SLICE_7 to SLICE_43: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R8C4D.CLK to R8C4D.Q1 SLICE_7 (from RCLK_c) +ROUTE 3 1.929 R8C4D.Q1 to R7C5C.B0 FS_15 +CTOF_DEL --- 0.371 R7C5C.B0 to R7C5C.F0 SLICE_78 +ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10 +CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73 +ROUTE 4 0.915 R7C4A.F1 to R6C4A.C0 n2300 +CTOF_DEL --- 0.371 R6C4A.C0 to R6C4A.F0 SLICE_86 +ROUTE 2 1.538 R6C4A.F0 to R7C5B.LSR n2291 (to RCLK_c) + -------- + 7.112 (23.5% logic, 76.5% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_7: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R8C4D.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_43: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R7C5B.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 8.316ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_577__i14 (from RCLK_c +) + Destination: FF Data in LEDEN_392 (to RCLK_c +) + + Delay: 7.440ns (32.5% logic, 67.5% route), 6 logic levels. + + Constraint Details: + + 7.440ns physical path delay SLICE_7 to SLICE_89 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.244ns CE_SET requirement (totaling 15.756ns) by 8.316ns + + Physical Path Details: + + Data path SLICE_7 to SLICE_89: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R8C4D.CLK to R8C4D.Q0 SLICE_7 (from RCLK_c) +ROUTE 3 1.179 R8C4D.Q0 to R7C5C.D0 FS_14 +CTOF_DEL --- 0.371 R7C5C.D0 to R7C5C.F0 SLICE_78 +ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10 +CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73 +ROUTE 4 0.712 R7C4A.F1 to R7C4A.B0 n2300 +CTOF_DEL --- 0.371 R7C4A.B0 to R7C4A.F0 SLICE_73 +ROUTE 1 0.304 R7C4A.F0 to R7C4B.D0 n11 +CTOF_DEL --- 0.371 R7C4B.D0 to R7C4B.F0 SLICE_75 +ROUTE 2 0.513 R7C4B.F0 to R7C4B.C1 n2119 +CTOF_DEL --- 0.371 R7C4B.C1 to R7C4B.F1 SLICE_75 +ROUTE 1 1.260 R7C4B.F1 to R6C3A.CE RCLK_c_enable_25 (to RCLK_c) + -------- + 7.440 (32.5% logic, 67.5% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_7: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R8C4D.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_89: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R6C3A.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 8.340ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_577__i14 (from RCLK_c +) + Destination: FF Data in n8MEGEN_391 (to RCLK_c +) + + Delay: 7.416ns (32.6% logic, 67.4% route), 6 logic levels. + + Constraint Details: + + 7.416ns physical path delay SLICE_7 to SLICE_56 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.244ns CE_SET requirement (totaling 15.756ns) by 8.340ns + + Physical Path Details: + + Data path SLICE_7 to SLICE_56: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R8C4D.CLK to R8C4D.Q0 SLICE_7 (from RCLK_c) +ROUTE 3 1.179 R8C4D.Q0 to R7C5C.D0 FS_14 +CTOF_DEL --- 0.371 R7C5C.D0 to R7C5C.F0 SLICE_78 +ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10 +CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73 +ROUTE 4 0.712 R7C4A.F1 to R7C4A.B0 n2300 +CTOF_DEL --- 0.371 R7C4A.B0 to R7C4A.F0 SLICE_73 +ROUTE 1 0.304 R7C4A.F0 to R7C4B.D0 n11 +CTOF_DEL --- 0.371 R7C4B.D0 to R7C4B.F0 SLICE_75 +ROUTE 2 1.102 R7C4B.F0 to R6C4C.B1 n2119 +CTOF_DEL --- 0.371 R6C4C.B1 to R6C4C.F1 SLICE_33 +ROUTE 1 0.647 R6C4C.F1 to R6C4B.CE RCLK_c_enable_7 (to RCLK_c) + -------- + 7.416 (32.6% logic, 67.4% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_7: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R8C4D.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_56: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.353 86.PADDI to R6C4B.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + +Report: 8.434ns is the minimum period for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.904ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RA10_373 (from RCLK_c +) + Destination: Port Pad RA[10] + + Data Path Delay: 6.180ns (67.9% logic, 32.1% route), 2 logic levels. + + Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. + + Constraint Details: + 2.416ns delay RCLK to SLICE_55 and + 6.180ns delay SLICE_55 to RA[10] (totaling 8.596ns) meets + 12.500ns offset RCLK to RA[10] by 3.904ns + + Physical Path Details: + + Clock path RCLK to SLICE_55: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 1.353 86.PADDI to R2C4B.CLK RCLK_c + -------- + 2.416 (44.0% logic, 56.0% route), 1 logic levels. + + Data path SLICE_55 to RA[10]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C4B.CLK to R2C4B.Q0 SLICE_55 (from RCLK_c) +ROUTE 1 1.984 R2C4B.Q0 to 87.PADDO n980 +DOPAD_DEL --- 3.636 87.PADDO to 87.PAD RA[10] + -------- + 6.180 (67.9% logic, 32.1% route), 2 logic levels. + +Report: 8.596ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.734ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[9] + + Data Path Delay: 6.350ns (71.9% logic, 28.1% route), 3 logic levels. + + Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. + + Constraint Details: + 2.416ns delay RCLK to SLICE_64 and + 6.350ns delay SLICE_64 to RA[9] (totaling 8.766ns) meets + 12.500ns offset RCLK to RA[9] by 3.734ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c + -------- + 2.416 (44.0% logic, 56.0% route), 1 logic levels. + + Data path SLICE_64 to RA[9]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.966 R2C2A.Q0 to R2C4A.C1 nRowColSel +CTOF_DEL --- 0.371 R2C4A.C1 to R2C4A.F1 SLICE_88 +ROUTE 1 0.817 R2C4A.F1 to 85.PADDO RA_c_9 +DOPAD_DEL --- 3.636 85.PADDO to 85.PAD RA[9] + -------- + 6.350 (71.9% logic, 28.1% route), 3 logic levels. + +Report: 8.766ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.604ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[8] + + Data Path Delay: 6.480ns (70.5% logic, 29.5% route), 3 logic levels. + + Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. + + Constraint Details: + 2.416ns delay RCLK to SLICE_64 and + 6.480ns delay SLICE_64 to RA[8] (totaling 8.896ns) meets + 12.500ns offset RCLK to RA[8] by 3.604ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c + -------- + 2.416 (44.0% logic, 56.0% route), 1 logic levels. + + Data path SLICE_64 to RA[8]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 1.096 R2C2A.Q0 to R2C2C.B0 nRowColSel +CTOF_DEL --- 0.371 R2C2C.B0 to R2C2C.F0 SLICE_95 +ROUTE 1 0.817 R2C2C.F0 to 96.PADDO RA_c_8 +DOPAD_DEL --- 3.636 96.PADDO to 96.PAD RA[8] + -------- + 6.480 (70.5% logic, 29.5% route), 3 logic levels. + +Report: 8.896ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.245ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[7] + + Data Path Delay: 7.839ns (58.3% logic, 41.7% route), 3 logic levels. + + Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. + + Constraint Details: + 2.416ns delay RCLK to SLICE_64 and + 7.839ns delay SLICE_64 to RA[7] (totaling 10.255ns) meets + 12.500ns offset RCLK to RA[7] by 2.245ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c + -------- + 2.416 (44.0% logic, 56.0% route), 1 logic levels. + + Data path SLICE_64 to RA[7]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 1.234 R2C2A.Q0 to R6C2B.D0 nRowColSel +CTOF_DEL --- 0.371 R6C2B.D0 to R6C2B.F0 SLICE_97 +ROUTE 1 2.038 R6C2B.F0 to 100.PADDO RA_c_7 +DOPAD_DEL --- 3.636 100.PADDO to 100.PAD RA[7] + -------- + 7.839 (58.3% logic, 41.7% route), 3 logic levels. + +Report: 10.255ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.499ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[6] + + Data Path Delay: 7.585ns (60.2% logic, 39.8% route), 3 logic levels. + + Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. + + Constraint Details: + 2.416ns delay RCLK to SLICE_64 and + 7.585ns delay SLICE_64 to RA[6] (totaling 10.001ns) meets + 12.500ns offset RCLK to RA[6] by 2.499ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c + -------- + 2.416 (44.0% logic, 56.0% route), 1 logic levels. + + Data path SLICE_64 to RA[6]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.966 R2C2A.Q0 to R3C2A.C0 nRowColSel +CTOF_DEL --- 0.371 R3C2A.C0 to R3C2A.F0 SLICE_98 +ROUTE 1 2.052 R3C2A.F0 to 91.PADDO RA_c_6 +DOPAD_DEL --- 3.636 91.PADDO to 91.PAD RA[6] + -------- + 7.585 (60.2% logic, 39.8% route), 3 logic levels. + +Report: 10.001ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.891ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[5] + + Data Path Delay: 7.193ns (63.5% logic, 36.5% route), 3 logic levels. + + Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. + + Constraint Details: + 2.416ns delay RCLK to SLICE_64 and + 7.193ns delay SLICE_64 to RA[5] (totaling 9.609ns) meets + 12.500ns offset RCLK to RA[5] by 2.891ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c + -------- + 2.416 (44.0% logic, 56.0% route), 1 logic levels. + + Data path SLICE_64 to RA[5]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.966 R2C2A.Q0 to R3C2A.C1 nRowColSel +CTOF_DEL --- 0.371 R3C2A.C1 to R3C2A.F1 SLICE_98 +ROUTE 1 1.660 R3C2A.F1 to 95.PADDO RA_c_5 +DOPAD_DEL --- 3.636 95.PADDO to 95.PAD RA[5] + -------- + 7.193 (63.5% logic, 36.5% route), 3 logic levels. + +Report: 9.609ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.996ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[4] + + Data Path Delay: 6.088ns (75.0% logic, 25.0% route), 3 logic levels. + + Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. + + Constraint Details: + 2.416ns delay RCLK to SLICE_64 and + 6.088ns delay SLICE_64 to RA[4] (totaling 8.504ns) meets + 12.500ns offset RCLK to RA[4] by 3.996ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c + -------- + 2.416 (44.0% logic, 56.0% route), 1 logic levels. + + Data path SLICE_64 to RA[4]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.704 R2C2A.Q0 to R2C2A.D1 nRowColSel +CTOF_DEL --- 0.371 R2C2A.D1 to R2C2A.F1 SLICE_64 +ROUTE 1 0.817 R2C2A.F1 to 99.PADDO RA_c_4 +DOPAD_DEL --- 3.636 99.PADDO to 99.PAD RA[4] + -------- + 6.088 (75.0% logic, 25.0% route), 3 logic levels. + +Report: 8.504ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.567ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[3] + + Data Path Delay: 7.517ns (60.8% logic, 39.2% route), 3 logic levels. + + Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. + + Constraint Details: + 2.416ns delay RCLK to SLICE_64 and + 7.517ns delay SLICE_64 to RA[3] (totaling 9.933ns) meets + 12.500ns offset RCLK to RA[3] by 2.567ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c + -------- + 2.416 (44.0% logic, 56.0% route), 1 logic levels. + + Data path SLICE_64 to RA[3]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.966 R2C2A.Q0 to R2C3B.C1 nRowColSel +CTOF_DEL --- 0.371 R2C3B.C1 to R2C3B.F1 SLICE_94 +ROUTE 1 1.984 R2C3B.F1 to 97.PADDO RA_c_3 +DOPAD_DEL --- 3.636 97.PADDO to 97.PAD RA[3] + -------- + 7.517 (60.8% logic, 39.2% route), 3 logic levels. + +Report: 9.933ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.438ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[2] + + Data Path Delay: 7.646ns (59.7% logic, 40.3% route), 3 logic levels. + + Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. + + Constraint Details: + 2.416ns delay RCLK to SLICE_64 and + 7.646ns delay SLICE_64 to RA[2] (totaling 10.062ns) meets + 12.500ns offset RCLK to RA[2] by 2.438ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c + -------- + 2.416 (44.0% logic, 56.0% route), 1 logic levels. + + Data path SLICE_64 to RA[2]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 1.096 R2C2A.Q0 to R2C2C.B1 nRowColSel +CTOF_DEL --- 0.371 R2C2C.B1 to R2C2C.F1 SLICE_95 +ROUTE 1 1.983 R2C2C.F1 to 94.PADDO RA_c_2 +DOPAD_DEL --- 3.636 94.PADDO to 94.PAD RA[2] + -------- + 7.646 (59.7% logic, 40.3% route), 3 logic levels. + +Report: 10.062ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.734ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[1] + + Data Path Delay: 6.350ns (71.9% logic, 28.1% route), 3 logic levels. + + Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. + + Constraint Details: + 2.416ns delay RCLK to SLICE_64 and + 6.350ns delay SLICE_64 to RA[1] (totaling 8.766ns) meets + 12.500ns offset RCLK to RA[1] by 3.734ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c + -------- + 2.416 (44.0% logic, 56.0% route), 1 logic levels. + + Data path SLICE_64 to RA[1]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.966 R2C2A.Q0 to R2C3B.C0 nRowColSel +CTOF_DEL --- 0.371 R2C3B.C0 to R2C3B.F0 SLICE_94 +ROUTE 1 0.817 R2C3B.F0 to 89.PADDO RA_c_1 +DOPAD_DEL --- 3.636 89.PADDO to 89.PAD RA[1] + -------- + 6.350 (71.9% logic, 28.1% route), 3 logic levels. + +Report: 8.766ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.826ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[0] + + Data Path Delay: 7.258ns (62.9% logic, 37.1% route), 3 logic levels. + + Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. + + Constraint Details: + 2.416ns delay RCLK to SLICE_64 and + 7.258ns delay SLICE_64 to RA[0] (totaling 9.674ns) meets + 12.500ns offset RCLK to RA[0] by 2.826ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c + -------- + 2.416 (44.0% logic, 56.0% route), 1 logic levels. + + Data path SLICE_64 to RA[0]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 1.165 R2C2A.Q0 to R3C2B.B1 nRowColSel +CTOF_DEL --- 0.371 R3C2B.B1 to R3C2B.F1 SLICE_92 +ROUTE 1 1.526 R3C2B.F1 to 98.PADDO RA_c_0 +DOPAD_DEL --- 3.636 98.PADDO to 98.PAD RA[0] + -------- + 7.258 (62.9% logic, 37.1% route), 3 logic levels. + +Report: 9.674ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 5.071ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRCS_369 (from RCLK_c +) + Destination: Port Pad nRCS + + Data Path Delay: 5.013ns (83.7% logic, 16.3% route), 2 logic levels. + + Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. + + Constraint Details: + 2.416ns delay RCLK to SLICE_60 and + 5.013ns delay SLICE_60 to nRCS (totaling 7.429ns) meets + 12.500ns offset RCLK to nRCS by 5.071ns + + Physical Path Details: + + Clock path RCLK to SLICE_60: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 1.353 86.PADDI to R2C5B.CLK RCLK_c + -------- + 2.416 (44.0% logic, 56.0% route), 1 logic levels. + + Data path SLICE_60 to nRCS: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C5B.CLK to R2C5B.Q0 SLICE_60 (from RCLK_c) +ROUTE 1 0.817 R2C5B.Q0 to 77.PADDO nRCS_c +DOPAD_DEL --- 3.636 77.PADDO to 77.PAD nRCS + -------- + 5.013 (83.7% logic, 16.3% route), 2 logic levels. + +Report: 7.429ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.420ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RCKE_368 (from RCLK_c +) + Destination: Port Pad RCKE + + Data Path Delay: 6.664ns (63.0% logic, 37.0% route), 2 logic levels. + + Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. + + Constraint Details: + 2.416ns delay RCLK to SLICE_34 and + 6.664ns delay SLICE_34 to RCKE (totaling 9.080ns) meets + 12.500ns offset RCLK to RCKE by 3.420ns + + Physical Path Details: + + Clock path RCLK to SLICE_34: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 1.353 86.PADDI to R5C2A.CLK RCLK_c + -------- + 2.416 (44.0% logic, 56.0% route), 1 logic levels. + + Data path SLICE_34 to RCKE: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R5C2A.CLK to R5C2A.Q0 SLICE_34 (from RCLK_c) +ROUTE 4 2.468 R5C2A.Q0 to 82.PADDO RCKE_c +DOPAD_DEL --- 3.636 82.PADDO to 82.PAD RCKE + -------- + 6.664 (63.0% logic, 37.0% route), 2 logic levels. + +Report: 9.080ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 5.071ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRWE_372 (from RCLK_c +) + Destination: Port Pad nRWE + + Data Path Delay: 5.013ns (83.7% logic, 16.3% route), 2 logic levels. + + Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. + + Constraint Details: + 2.416ns delay RCLK to SLICE_63 and + 5.013ns delay SLICE_63 to nRWE (totaling 7.429ns) meets + 12.500ns offset RCLK to nRWE by 5.071ns + + Physical Path Details: + + Clock path RCLK to SLICE_63: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 1.353 86.PADDI to R3C5B.CLK RCLK_c + -------- + 2.416 (44.0% logic, 56.0% route), 1 logic levels. + + Data path SLICE_63 to nRWE: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R3C5B.CLK to R3C5B.Q0 SLICE_63 (from RCLK_c) +ROUTE 1 0.817 R3C5B.Q0 to 72.PADDO nRWE_c +DOPAD_DEL --- 3.636 72.PADDO to 72.PAD nRWE + -------- + 5.013 (83.7% logic, 16.3% route), 2 logic levels. + +Report: 7.429ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.885ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRRAS_370 (from RCLK_c +) + Destination: Port Pad nRRAS + + Data Path Delay: 6.199ns (67.7% logic, 32.3% route), 2 logic levels. + + Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. + + Constraint Details: + 2.416ns delay RCLK to SLICE_61 and + 6.199ns delay SLICE_61 to nRRAS (totaling 8.615ns) meets + 12.500ns offset RCLK to nRRAS by 3.885ns + + Physical Path Details: + + Clock path RCLK to SLICE_61: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 1.353 86.PADDI to R4C5A.CLK RCLK_c + -------- + 2.416 (44.0% logic, 56.0% route), 1 logic levels. + + Data path SLICE_61 to nRRAS: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R4C5A.CLK to R4C5A.Q0 SLICE_61 (from RCLK_c) +ROUTE 2 2.003 R4C5A.Q0 to 73.PADDO nRRAS_c +DOPAD_DEL --- 3.636 73.PADDO to 73.PAD nRRAS + -------- + 6.199 (67.7% logic, 32.3% route), 2 logic levels. + +Report: 8.615ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.905ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRCAS_371 (from RCLK_c +) + Destination: Port Pad nRCAS + + Data Path Delay: 6.179ns (67.9% logic, 32.1% route), 2 logic levels. + + Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. + + Constraint Details: + 2.416ns delay RCLK to SLICE_58 and + 6.179ns delay SLICE_58 to nRCAS (totaling 8.595ns) meets + 12.500ns offset RCLK to nRCAS by 3.905ns + + Physical Path Details: + + Clock path RCLK to SLICE_58: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 1.353 86.PADDI to R2C4C.CLK RCLK_c + -------- + 2.416 (44.0% logic, 56.0% route), 1 logic levels. + + Data path SLICE_58 to nRCAS: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C4C.CLK to R2C4C.Q0 SLICE_58 (from RCLK_c) +ROUTE 1 1.983 R2C4C.Q0 to 78.PADDO nRCAS_c +DOPAD_DEL --- 3.636 78.PADDO to 78.PAD nRCAS + -------- + 6.179 (67.9% logic, 32.1% route), 2 logic levels. + +Report: 8.595ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 3.025ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RDQMH + + Data Path Delay: 7.059ns (64.7% logic, 35.3% route), 3 logic levels. + + Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. + + Constraint Details: + 2.416ns delay RCLK to SLICE_64 and + 7.059ns delay SLICE_64 to RDQMH (totaling 9.475ns) meets + 12.500ns offset RCLK to RDQMH by 3.025ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c + -------- + 2.416 (44.0% logic, 56.0% route), 1 logic levels. + + Data path SLICE_64 to RDQMH: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.966 R2C2A.Q0 to R2C4A.C0 nRowColSel +CTOF_DEL --- 0.371 R2C4A.C0 to R2C4A.F0 SLICE_88 +ROUTE 1 1.526 R2C4A.F0 to 76.PADDO RDQMH_c +DOPAD_DEL --- 3.636 76.PADDO to 76.PAD RDQMH + -------- + 7.059 (64.7% logic, 35.3% route), 3 logic levels. + +Report: 9.475ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.023ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RDQML + + Data Path Delay: 8.061ns (56.7% logic, 43.3% route), 3 logic levels. + + Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. + + Constraint Details: + 2.416ns delay RCLK to SLICE_64 and + 8.061ns delay SLICE_64 to RDQML (totaling 10.477ns) meets + 12.500ns offset RCLK to RDQML by 2.023ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK +ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c + -------- + 2.416 (44.0% logic, 56.0% route), 1 logic levels. + + Data path SLICE_64 to RDQML: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.954 R2C2A.Q0 to R3C2B.C0 nRowColSel +CTOF_DEL --- 0.371 R3C2B.C0 to R3C2B.F0 SLICE_92 +ROUTE 1 2.540 R3C2B.F0 to 61.PADDO RDQML_c +DOPAD_DEL --- 3.636 61.PADDO to 61.PAD RDQML + -------- + 8.061 (56.7% logic, 43.3% route), 3 logic levels. + +Report: 10.477ns is the minimum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +PERIOD NET "PHI2_c" 350.000000 ns ; | 350.000 ns| 26.150 ns| 7 + | | | +PERIOD NET "nCCAS_c" 350.000000 ns ; | 350.000 ns| 2.000 ns| 0 + | | | +PERIOD NET "nCRAS_c" 350.000000 ns ; | 350.000 ns| 2.000 ns| 0 + | | | +PERIOD NET "RCLK_c" 16.000000 ns ; | 16.000 ns| 8.434 ns| 6 + | | | +CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[0]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[7]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[6]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[5]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[4]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[3]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[2]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[1]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 8.596 ns| 2 + | | | +CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 8.766 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 8.896 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 10.255 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 10.001 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 9.609 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 8.504 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 9.933 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 10.062 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 8.766 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 9.674 ns| 3 + | | | +CLOCK_TO_OUT PORT "nRCS" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 7.429 ns| 2 + | | | +CLOCK_TO_OUT PORT "RCKE" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 9.080 ns| 2 + | | | +CLOCK_TO_OUT PORT "nRWE" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 7.429 ns| 2 + | | | +CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 8.615 ns| 2 + | | | +CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 8.595 ns| 2 + | | | +CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 9.475 ns| 3 + | | | +CLOCK_TO_OUT PORT "RDQML" 12.500000 ns | | | +CLKPORT "RCLK" ; | 12.500 ns| 10.477 ns| 3 + | | | +CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +---------------------------------------------------------------------------- + + +All preferences were met. + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 39 + Covered under: PERIOD NET "RCLK_c" 16.000000 ns ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: PERIOD NET "PHI2_c" 350.000000 ns ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Setup): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 526 paths, 6 nets, and 440 connections (71.20% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2 +Mon Aug 16 21:32:34 2021 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO256C_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf +Design file: ram2gs_lcmxo256c_impl1.ncd +Preference file: ram2gs_lcmxo256c_impl1.prf +Device,speed: LCMXO256C,m +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + +Derating parameters +------------------- +Voltage: 3.300 V + + + +================================================================================ +Preference: PERIOD NET "PHI2_c" 350.000000 ns ; + 113 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.444ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q ADSubmitted_380 (from PHI2_c -) + Destination: FF Data in ADSubmitted_380 (to PHI2_c -) + + Delay: 0.421ns (62.2% logic, 37.8% route), 2 logic levels. + + Constraint Details: + + 0.421ns physical path delay SLICE_9 to SLICE_9 meets + -0.023ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.023ns) by 0.444ns + + Physical Path Details: + + Data path SLICE_9 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.170 R5C3A.CLK to R5C3A.Q0 SLICE_9 (from PHI2_c) +ROUTE 2 0.159 R5C3A.Q0 to R5C3A.D0 ADSubmitted +CTOF_DEL --- 0.092 R5C3A.D0 to R5C3A.F0 SLICE_9 +ROUTE 1 0.000 R5C3A.F0 to R5C3A.DI0 n1361 (to PHI2_c) + -------- + 0.421 (62.2% logic, 37.8% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R5C3A.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R5C3A.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.186ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_378 (from PHI2_c -) + Destination: FF Data in Cmdn8MEGEN_383 (to PHI2_c -) + + Delay: 1.157ns (30.6% logic, 69.4% route), 3 logic levels. + + Constraint Details: + + 1.157ns physical path delay SLICE_18 to SLICE_23 meets + -0.029ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.029ns) by 1.186ns + + Physical Path Details: + + Data path SLICE_18 to SLICE_23: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.170 R5C3C.CLK to R5C3C.Q0 SLICE_18 (from PHI2_c) +ROUTE 1 0.253 R5C3C.Q0 to R5C3C.B1 CmdEnable +CTOF_DEL --- 0.092 R5C3C.B1 to R5C3C.F1 SLICE_18 +ROUTE 3 0.383 R5C3C.F1 to R4C4D.A0 XOR8MEG_N_112 +CTOF_DEL --- 0.092 R4C4D.A0 to R4C4D.F0 SLICE_90 +ROUTE 2 0.167 R4C4D.F0 to R4C4C.CE PHI2_N_114_enable_6 (to PHI2_c) + -------- + 1.157 (30.6% logic, 69.4% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R5C3C.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_23: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R4C4C.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.193ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q C1Submitted_379 (from PHI2_c -) + Destination: FF Data in CmdEnable_378 (to PHI2_c -) + + Delay: 1.164ns (38.3% logic, 61.7% route), 4 logic levels. + + Constraint Details: + + 1.164ns physical path delay SLICE_14 to SLICE_18 meets + -0.029ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.029ns) by 1.193ns + + Physical Path Details: + + Data path SLICE_14 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.170 R6C3B.CLK to R6C3B.Q0 SLICE_14 (from PHI2_c) +ROUTE 1 0.253 R6C3B.Q0 to R6C3B.B1 C1Submitted +CTOF_DEL --- 0.092 R6C3B.B1 to R6C3B.F1 SLICE_14 +ROUTE 1 0.075 R6C3B.F1 to R6C3C.D1 n2098 +CTOF_DEL --- 0.092 R6C3C.D1 to R6C3C.F1 SLICE_77 +ROUTE 1 0.123 R6C3C.F1 to R6C3C.C0 n2286 +CTOF_DEL --- 0.092 R6C3C.C0 to R6C3C.F0 SLICE_77 +ROUTE 1 0.267 R6C3C.F0 to R5C3C.CE PHI2_N_114_enable_8 (to PHI2_c) + -------- + 1.164 (38.3% logic, 61.7% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R6C3B.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R5C3C.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.280ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q ADSubmitted_380 (from PHI2_c -) + Destination: FF Data in CmdEnable_378 (to PHI2_c -) + + Delay: 1.251ns (35.7% logic, 64.3% route), 4 logic levels. + + Constraint Details: + + 1.251ns physical path delay SLICE_9 to SLICE_18 meets + -0.029ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.029ns) by 1.280ns + + Physical Path Details: + + Data path SLICE_9 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.170 R5C3A.CLK to R5C3A.Q0 SLICE_9 (from PHI2_c) +ROUTE 2 0.159 R5C3A.Q0 to R5C3A.D1 ADSubmitted +CTOF_DEL --- 0.092 R5C3A.D1 to R5C3A.F1 SLICE_9 +ROUTE 1 0.256 R5C3A.F1 to R6C3C.A1 n2080 +CTOF_DEL --- 0.092 R6C3C.A1 to R6C3C.F1 SLICE_77 +ROUTE 1 0.123 R6C3C.F1 to R6C3C.C0 n2286 +CTOF_DEL --- 0.092 R6C3C.C0 to R6C3C.F0 SLICE_77 +ROUTE 1 0.267 R6C3C.F0 to R5C3C.CE PHI2_N_114_enable_8 (to PHI2_c) + -------- + 1.251 (35.7% logic, 64.3% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R5C3A.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R5C3C.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.286ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_378 (from PHI2_c -) + Destination: FF Data in XOR8MEG_381 (to PHI2_c -) + + Delay: 1.257ns (28.2% logic, 71.8% route), 3 logic levels. + + Constraint Details: + + 1.257ns physical path delay SLICE_18 to SLICE_96 meets + -0.029ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.029ns) by 1.286ns + + Physical Path Details: + + Data path SLICE_18 to SLICE_96: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.170 R5C3C.CLK to R5C3C.Q0 SLICE_18 (from PHI2_c) +ROUTE 1 0.253 R5C3C.Q0 to R5C3C.B1 CmdEnable +CTOF_DEL --- 0.092 R5C3C.B1 to R5C3C.F1 SLICE_18 +ROUTE 3 0.383 R5C3C.F1 to R4C4D.A1 XOR8MEG_N_112 +CTOF_DEL --- 0.092 R4C4D.A1 to R4C4D.F1 SLICE_90 +ROUTE 1 0.267 R4C4D.F1 to R3C4B.CE PHI2_N_114_enable_2 (to PHI2_c) + -------- + 1.257 (28.2% logic, 71.8% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R5C3C.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_96: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R3C4B.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.400ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_378 (from PHI2_c -) + Destination: FF Data in CmdUFMSDI_387 (to PHI2_c -) + + Delay: 1.371ns (25.8% logic, 74.2% route), 3 logic levels. + + Constraint Details: + + 1.371ns physical path delay SLICE_18 to SLICE_88 meets + -0.029ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.029ns) by 1.400ns + + Physical Path Details: + + Data path SLICE_18 to SLICE_88: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.170 R5C3C.CLK to R5C3C.Q0 SLICE_18 (from PHI2_c) +ROUTE 1 0.253 R5C3C.Q0 to R5C3C.B1 CmdEnable +CTOF_DEL --- 0.092 R5C3C.B1 to R5C3C.F1 SLICE_18 +ROUTE 3 0.383 R5C3C.F1 to R4C4A.A0 XOR8MEG_N_112 +CTOF_DEL --- 0.092 R4C4A.A0 to R4C4A.F0 SLICE_72 +ROUTE 2 0.381 R4C4A.F0 to R2C4A.CE PHI2_N_114_enable_7 (to PHI2_c) + -------- + 1.371 (25.8% logic, 74.2% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R5C3C.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_88: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R2C4A.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.414ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_378 (from PHI2_c -) + Destination: FF Data in CmdSubmitted_384 (to PHI2_c -) + + Delay: 1.385ns (25.6% logic, 74.4% route), 3 logic levels. + + Constraint Details: + + 1.385ns physical path delay SLICE_18 to SLICE_19 meets + -0.029ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.029ns) by 1.414ns + + Physical Path Details: + + Data path SLICE_18 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.170 R5C3C.CLK to R5C3C.Q0 SLICE_18 (from PHI2_c) +ROUTE 1 0.253 R5C3C.Q0 to R5C3C.B1 CmdEnable +CTOF_DEL --- 0.092 R5C3C.B1 to R5C3C.F1 SLICE_18 +ROUTE 3 0.383 R5C3C.F1 to R4C4D.A0 XOR8MEG_N_112 +CTOF_DEL --- 0.092 R4C4D.A0 to R4C4D.F0 SLICE_90 +ROUTE 2 0.395 R4C4D.F0 to R5C5A.CE PHI2_N_114_enable_6 (to PHI2_c) + -------- + 1.385 (25.6% logic, 74.4% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R5C3C.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R5C5A.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.537ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_378 (from PHI2_c -) + Destination: FF Data in CmdUFMCS_385 (to PHI2_c -) + FF CmdUFMCLK_386 + + Delay: 1.508ns (23.5% logic, 76.5% route), 3 logic levels. + + Constraint Details: + + 1.508ns physical path delay SLICE_18 to SLICE_83 meets + -0.029ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.029ns) by 1.537ns + + Physical Path Details: + + Data path SLICE_18 to SLICE_83: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.170 R5C3C.CLK to R5C3C.Q0 SLICE_18 (from PHI2_c) +ROUTE 1 0.253 R5C3C.Q0 to R5C3C.B1 CmdEnable +CTOF_DEL --- 0.092 R5C3C.B1 to R5C3C.F1 SLICE_18 +ROUTE 3 0.383 R5C3C.F1 to R4C4A.A0 XOR8MEG_N_112 +CTOF_DEL --- 0.092 R4C4A.A0 to R4C4A.F0 SLICE_72 +ROUTE 2 0.518 R4C4A.F0 to R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c) + -------- + 1.508 (23.5% logic, 76.5% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R5C3C.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_83: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R5C4B.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 175.681ns (weighted slack = 351.362ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q XOR8MEG_381 (from PHI2_c -) + Destination: FF Data in RA11_358 (to PHI2_c +) + + Delay: 0.670ns (39.1% logic, 60.9% route), 2 logic levels. + + Constraint Details: + + 0.670ns physical path delay SLICE_96 to SLICE_31 meets + -0.011ns DIN_HLD and + -175.000ns delay constraint less + 0.000ns skew requirement (totaling -175.011ns) by 175.681ns + + Physical Path Details: + + Data path SLICE_96 to SLICE_31: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.170 R3C4B.CLK to R3C4B.Q0 SLICE_96 (from PHI2_c) +ROUTE 1 0.408 R3C4B.Q0 to R2C5A.D0 XOR8MEG +CTOF_DEL --- 0.092 R2C5A.D0 to R2C5A.F0 SLICE_31 +ROUTE 1 0.000 R2C5A.F0 to R2C5A.DI0 RA11_N_180 (to PHI2_c) + -------- + 0.670 (39.1% logic, 60.9% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_96: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R3C4B.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_31: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R2C5A.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 176.485ns (weighted slack = 352.970ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i3 (from PHI2_c +) + Destination: FF Data in C1Submitted_379 (to PHI2_c -) + + Delay: 1.456ns (23.4% logic, 76.6% route), 3 logic levels. + + Constraint Details: + + 1.456ns physical path delay SLICE_98 to SLICE_14 meets + -0.029ns CE_HLD and + -175.000ns delay constraint less + 0.000ns skew requirement (totaling -175.029ns) by 176.485ns + + Physical Path Details: + + Data path SLICE_98 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R3C2A.CLK to R3C2A.Q1 SLICE_98 (from PHI2_c) +ROUTE 1 0.495 R3C2A.Q1 to R5C5B.A1 Bank_3 +CTOF_DEL --- 0.092 R5C5B.A1 to R5C5B.F1 SLICE_76 +ROUTE 4 0.459 R5C5B.F1 to R6C3A.D1 n1285 +CTOF_DEL --- 0.092 R6C3A.D1 to R6C3A.F1 SLICE_89 +ROUTE 1 0.161 R6C3A.F1 to R6C3B.CE PHI2_N_114_enable_1 (to PHI2_c) + -------- + 1.456 (23.4% logic, 76.6% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_98: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R3C2A.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.196 39.PADDI to R6C3B.CLK PHI2_c + -------- + 1.196 (0.0% logic, 100.0% route), 0 logic levels. + + +================================================================================ +Preference: PERIOD NET "nCCAS_c" 350.000000 ns ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: PERIOD NET "nCRAS_c" 350.000000 ns ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: PERIOD NET "RCLK_c" 16.000000 ns ; + 395 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.339ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i11 (from RCLK_c +) + Destination: FF Data in IS_FSM__i12 (to RCLK_c +) + + Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels. + + Constraint Details: + + 0.318ns physical path delay SLICE_72 to SLICE_72 meets + -0.021ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.021ns) by 0.339ns + + Physical Path Details: + + Data path SLICE_72 to SLICE_72: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R4C4A.CLK to R4C4A.Q0 SLICE_72 (from RCLK_c) +ROUTE 1 0.161 R4C4A.Q0 to R4C4A.M1 n702 (to RCLK_c) + -------- + 0.318 (49.4% logic, 50.6% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_72: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R4C4A.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_72: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R4C4A.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.339ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i12 (from RCLK_c +) + Destination: FF Data in IS_FSM__i13 (to RCLK_c +) + + Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels. + + Constraint Details: + + 0.318ns physical path delay SLICE_72 to SLICE_90 meets + -0.021ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.021ns) by 0.339ns + + Physical Path Details: + + Data path SLICE_72 to SLICE_90: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R4C4A.CLK to R4C4A.Q1 SLICE_72 (from RCLK_c) +ROUTE 1 0.161 R4C4A.Q1 to R4C4D.M0 n701 (to RCLK_c) + -------- + 0.318 (49.4% logic, 50.6% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_72: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R4C4A.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_90: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R4C4D.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.339ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i7 (from RCLK_c +) + Destination: FF Data in IS_FSM__i8 (to RCLK_c +) + + Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels. + + Constraint Details: + + 0.318ns physical path delay SLICE_73 to SLICE_73 meets + -0.021ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.021ns) by 0.339ns + + Physical Path Details: + + Data path SLICE_73 to SLICE_73: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R7C4A.CLK to R7C4A.Q0 SLICE_73 (from RCLK_c) +ROUTE 1 0.161 R7C4A.Q0 to R7C4A.M1 n706 (to RCLK_c) + -------- + 0.318 (49.4% logic, 50.6% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_73: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R7C4A.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_73: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R7C4A.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.339ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i3 (from RCLK_c +) + Destination: FF Data in IS_FSM__i4 (to RCLK_c +) + + Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels. + + Constraint Details: + + 0.318ns physical path delay SLICE_74 to SLICE_74 meets + -0.021ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.021ns) by 0.339ns + + Physical Path Details: + + Data path SLICE_74 to SLICE_74: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R5C3B.CLK to R5C3B.Q0 SLICE_74 (from RCLK_c) +ROUTE 1 0.161 R5C3B.Q0 to R5C3B.M1 n710 (to RCLK_c) + -------- + 0.318 (49.4% logic, 50.6% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_74: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R5C3B.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_74: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R5C3B.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.339ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i6 (from RCLK_c +) + Destination: FF Data in IS_FSM__i7 (to RCLK_c +) + + Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels. + + Constraint Details: + + 0.318ns physical path delay SLICE_75 to SLICE_73 meets + -0.021ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.021ns) by 0.339ns + + Physical Path Details: + + Data path SLICE_75 to SLICE_73: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R7C4B.CLK to R7C4B.Q1 SLICE_75 (from RCLK_c) +ROUTE 1 0.161 R7C4B.Q1 to R7C4A.M0 n707 (to RCLK_c) + -------- + 0.318 (49.4% logic, 50.6% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_75: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R7C4B.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_73: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R7C4A.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.339ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i5 (from RCLK_c +) + Destination: FF Data in IS_FSM__i6 (to RCLK_c +) + + Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels. + + Constraint Details: + + 0.318ns physical path delay SLICE_75 to SLICE_75 meets + -0.021ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.021ns) by 0.339ns + + Physical Path Details: + + Data path SLICE_75 to SLICE_75: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R7C4B.CLK to R7C4B.Q0 SLICE_75 (from RCLK_c) +ROUTE 1 0.161 R7C4B.Q0 to R7C4B.M1 n708 (to RCLK_c) + -------- + 0.318 (49.4% logic, 50.6% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_75: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R7C4B.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_75: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R7C4B.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.339ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i10 (from RCLK_c +) + Destination: FF Data in IS_FSM__i11 (to RCLK_c +) + + Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels. + + Constraint Details: + + 0.318ns physical path delay SLICE_84 to SLICE_72 meets + -0.021ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.021ns) by 0.339ns + + Physical Path Details: + + Data path SLICE_84 to SLICE_72: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R4C4B.CLK to R4C4B.Q1 SLICE_84 (from RCLK_c) +ROUTE 1 0.161 R4C4B.Q1 to R4C4A.M0 n703 (to RCLK_c) + -------- + 0.318 (49.4% logic, 50.6% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_84: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R4C4B.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_72: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R4C4A.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.339ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i2 (from RCLK_c +) + Destination: FF Data in IS_FSM__i3 (to RCLK_c +) + + Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels. + + Constraint Details: + + 0.318ns physical path delay SLICE_87 to SLICE_74 meets + -0.021ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.021ns) by 0.339ns + + Physical Path Details: + + Data path SLICE_87 to SLICE_74: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R5C3D.CLK to R5C3D.Q1 SLICE_87 (from RCLK_c) +ROUTE 1 0.161 R5C3D.Q1 to R5C3B.M0 n711 (to RCLK_c) + -------- + 0.318 (49.4% logic, 50.6% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_87: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R5C3D.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_74: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R5C3B.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.339ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i13 (from RCLK_c +) + Destination: FF Data in IS_FSM__i14 (to RCLK_c +) + + Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels. + + Constraint Details: + + 0.318ns physical path delay SLICE_90 to SLICE_90 meets + -0.021ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.021ns) by 0.339ns + + Physical Path Details: + + Data path SLICE_90 to SLICE_90: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R4C4D.CLK to R4C4D.Q0 SLICE_90 (from RCLK_c) +ROUTE 1 0.161 R4C4D.Q0 to R4C4D.M1 n700 (to RCLK_c) + -------- + 0.318 (49.4% logic, 50.6% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_90: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R4C4D.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_90: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R4C4D.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.345ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RASr2_353 (from RCLK_c +) + Destination: FF Data in RASr3_354 (to RCLK_c +) + + Delay: 0.324ns (48.5% logic, 51.5% route), 1 logic levels. + + Constraint Details: + + 0.324ns physical path delay SLICE_93 to SLICE_93 meets + -0.021ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.021ns) by 0.345ns + + Physical Path Details: + + Data path SLICE_93 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R7C5D.CLK to R7C5D.Q0 SLICE_93 (from RCLK_c) +ROUTE 16 0.167 R7C5D.Q0 to R7C5D.M1 RASr2 (to RCLK_c) + -------- + 0.324 (48.5% logic, 51.5% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R7C5D.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 0.413 86.PADDI to R7C5D.CLK RCLK_c + -------- + 0.413 (0.0% logic, 100.0% route), 0 logic levels. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.220ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RA10_373 (from RCLK_c +) + Destination: Port Pad RA[10] + + Data Path Delay: 1.733ns (73.0% logic, 27.0% route), 2 logic levels. + + Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. + + Constraint Details: + 0.487ns delay RCLK to SLICE_55 and + 1.733ns delay SLICE_55 to RA[10] (totaling 2.220ns) meets + 0.000ns hold offset RCLK to RA[10] by 2.220ns + + Physical Path Details: + + Clock path RCLK to SLICE_55: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 0.223 86.PADDI to R2C4B.CLK RCLK_c + -------- + 0.487 (54.2% logic, 45.8% route), 1 logic levels. + + Data path SLICE_55 to RA[10]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R2C4B.CLK to R2C4B.Q0 SLICE_55 (from RCLK_c) +ROUTE 1 0.468 R2C4B.Q0 to 87.PADDO n980 +DOPAD_DEL --- 1.108 87.PADDO to 87.PAD RA[10] + -------- + 1.733 (73.0% logic, 27.0% route), 2 logic levels. + +Report: 2.220ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.284ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[9] + + Data Path Delay: 1.797ns (75.5% logic, 24.5% route), 3 logic levels. + + Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. + + Constraint Details: + 0.487ns delay RCLK to SLICE_64 and + 1.797ns delay SLICE_64 to RA[9] (totaling 2.284ns) meets + 0.000ns hold offset RCLK to RA[9] by 2.284ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c + -------- + 0.487 (54.2% logic, 45.8% route), 1 logic levels. + + Data path SLICE_64 to RA[9]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.243 R2C2A.Q0 to R2C4A.C1 nRowColSel +CTOF_DEL --- 0.092 R2C4A.C1 to R2C4A.F1 SLICE_88 +ROUTE 1 0.197 R2C4A.F1 to 85.PADDO RA_c_9 +DOPAD_DEL --- 1.108 85.PADDO to 85.PAD RA[9] + -------- + 1.797 (75.5% logic, 24.5% route), 3 logic levels. + +Report: 2.284ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.316ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[8] + + Data Path Delay: 1.829ns (74.2% logic, 25.8% route), 3 logic levels. + + Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. + + Constraint Details: + 0.487ns delay RCLK to SLICE_64 and + 1.829ns delay SLICE_64 to RA[8] (totaling 2.316ns) meets + 0.000ns hold offset RCLK to RA[8] by 2.316ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c + -------- + 0.487 (54.2% logic, 45.8% route), 1 logic levels. + + Data path SLICE_64 to RA[8]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.275 R2C2A.Q0 to R2C2C.B0 nRowColSel +CTOF_DEL --- 0.092 R2C2C.B0 to R2C2C.F0 SLICE_95 +ROUTE 1 0.197 R2C2C.F0 to 96.PADDO RA_c_8 +DOPAD_DEL --- 1.108 96.PADDO to 96.PAD RA[8] + -------- + 1.829 (74.2% logic, 25.8% route), 3 logic levels. + +Report: 2.316ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.652ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[7] + + Data Path Delay: 2.165ns (62.7% logic, 37.3% route), 3 logic levels. + + Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. + + Constraint Details: + 0.487ns delay RCLK to SLICE_64 and + 2.165ns delay SLICE_64 to RA[7] (totaling 2.652ns) meets + 0.000ns hold offset RCLK to RA[7] by 2.652ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c + -------- + 0.487 (54.2% logic, 45.8% route), 1 logic levels. + + Data path SLICE_64 to RA[7]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.319 R2C2A.Q0 to R6C2B.D0 nRowColSel +CTOF_DEL --- 0.092 R6C2B.D0 to R6C2B.F0 SLICE_97 +ROUTE 1 0.489 R6C2B.F0 to 100.PADDO RA_c_7 +DOPAD_DEL --- 1.108 100.PADDO to 100.PAD RA[7] + -------- + 2.165 (62.7% logic, 37.3% route), 3 logic levels. + +Report: 2.652ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.579ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[6] + + Data Path Delay: 2.092ns (64.9% logic, 35.1% route), 3 logic levels. + + Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. + + Constraint Details: + 0.487ns delay RCLK to SLICE_64 and + 2.092ns delay SLICE_64 to RA[6] (totaling 2.579ns) meets + 0.000ns hold offset RCLK to RA[6] by 2.579ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c + -------- + 0.487 (54.2% logic, 45.8% route), 1 logic levels. + + Data path SLICE_64 to RA[6]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.243 R2C2A.Q0 to R3C2A.C0 nRowColSel +CTOF_DEL --- 0.092 R3C2A.C0 to R3C2A.F0 SLICE_98 +ROUTE 1 0.492 R3C2A.F0 to 91.PADDO RA_c_6 +DOPAD_DEL --- 1.108 91.PADDO to 91.PAD RA[6] + -------- + 2.092 (64.9% logic, 35.1% route), 3 logic levels. + +Report: 2.579ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.481ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[5] + + Data Path Delay: 1.994ns (68.1% logic, 31.9% route), 3 logic levels. + + Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. + + Constraint Details: + 0.487ns delay RCLK to SLICE_64 and + 1.994ns delay SLICE_64 to RA[5] (totaling 2.481ns) meets + 0.000ns hold offset RCLK to RA[5] by 2.481ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c + -------- + 0.487 (54.2% logic, 45.8% route), 1 logic levels. + + Data path SLICE_64 to RA[5]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.243 R2C2A.Q0 to R3C2A.C1 nRowColSel +CTOF_DEL --- 0.092 R3C2A.C1 to R3C2A.F1 SLICE_98 +ROUTE 1 0.394 R3C2A.F1 to 95.PADDO RA_c_5 +DOPAD_DEL --- 1.108 95.PADDO to 95.PAD RA[5] + -------- + 1.994 (68.1% logic, 31.9% route), 3 logic levels. + +Report: 2.481ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.219ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[4] + + Data Path Delay: 1.732ns (78.3% logic, 21.7% route), 3 logic levels. + + Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. + + Constraint Details: + 0.487ns delay RCLK to SLICE_64 and + 1.732ns delay SLICE_64 to RA[4] (totaling 2.219ns) meets + 0.000ns hold offset RCLK to RA[4] by 2.219ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c + -------- + 0.487 (54.2% logic, 45.8% route), 1 logic levels. + + Data path SLICE_64 to RA[4]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.178 R2C2A.Q0 to R2C2A.D1 nRowColSel +CTOF_DEL --- 0.092 R2C2A.D1 to R2C2A.F1 SLICE_64 +ROUTE 1 0.197 R2C2A.F1 to 99.PADDO RA_c_4 +DOPAD_DEL --- 1.108 99.PADDO to 99.PAD RA[4] + -------- + 1.732 (78.3% logic, 21.7% route), 3 logic levels. + +Report: 2.219ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.555ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[3] + + Data Path Delay: 2.068ns (65.6% logic, 34.4% route), 3 logic levels. + + Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. + + Constraint Details: + 0.487ns delay RCLK to SLICE_64 and + 2.068ns delay SLICE_64 to RA[3] (totaling 2.555ns) meets + 0.000ns hold offset RCLK to RA[3] by 2.555ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c + -------- + 0.487 (54.2% logic, 45.8% route), 1 logic levels. + + Data path SLICE_64 to RA[3]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.243 R2C2A.Q0 to R2C3B.C1 nRowColSel +CTOF_DEL --- 0.092 R2C3B.C1 to R2C3B.F1 SLICE_94 +ROUTE 1 0.468 R2C3B.F1 to 97.PADDO RA_c_3 +DOPAD_DEL --- 1.108 97.PADDO to 97.PAD RA[3] + -------- + 2.068 (65.6% logic, 34.4% route), 3 logic levels. + +Report: 2.555ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.599ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[2] + + Data Path Delay: 2.112ns (64.3% logic, 35.7% route), 3 logic levels. + + Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. + + Constraint Details: + 0.487ns delay RCLK to SLICE_64 and + 2.112ns delay SLICE_64 to RA[2] (totaling 2.599ns) meets + 0.000ns hold offset RCLK to RA[2] by 2.599ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c + -------- + 0.487 (54.2% logic, 45.8% route), 1 logic levels. + + Data path SLICE_64 to RA[2]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.275 R2C2A.Q0 to R2C2C.B1 nRowColSel +CTOF_DEL --- 0.092 R2C2C.B1 to R2C2C.F1 SLICE_95 +ROUTE 1 0.480 R2C2C.F1 to 94.PADDO RA_c_2 +DOPAD_DEL --- 1.108 94.PADDO to 94.PAD RA[2] + -------- + 2.112 (64.3% logic, 35.7% route), 3 logic levels. + +Report: 2.599ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.284ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[1] + + Data Path Delay: 1.797ns (75.5% logic, 24.5% route), 3 logic levels. + + Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. + + Constraint Details: + 0.487ns delay RCLK to SLICE_64 and + 1.797ns delay SLICE_64 to RA[1] (totaling 2.284ns) meets + 0.000ns hold offset RCLK to RA[1] by 2.284ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c + -------- + 0.487 (54.2% logic, 45.8% route), 1 logic levels. + + Data path SLICE_64 to RA[1]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.243 R2C2A.Q0 to R2C3B.C0 nRowColSel +CTOF_DEL --- 0.092 R2C3B.C0 to R2C3B.F0 SLICE_94 +ROUTE 1 0.197 R2C3B.F0 to 89.PADDO RA_c_1 +DOPAD_DEL --- 1.108 89.PADDO to 89.PAD RA[1] + -------- + 1.797 (75.5% logic, 24.5% route), 3 logic levels. + +Report: 2.284ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.492ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RA[0] + + Data Path Delay: 2.005ns (67.7% logic, 32.3% route), 3 logic levels. + + Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. + + Constraint Details: + 0.487ns delay RCLK to SLICE_64 and + 2.005ns delay SLICE_64 to RA[0] (totaling 2.492ns) meets + 0.000ns hold offset RCLK to RA[0] by 2.492ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c + -------- + 0.487 (54.2% logic, 45.8% route), 1 logic levels. + + Data path SLICE_64 to RA[0]: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.292 R2C2A.Q0 to R3C2B.B1 nRowColSel +CTOF_DEL --- 0.092 R3C2B.B1 to R3C2B.F1 SLICE_92 +ROUTE 1 0.356 R3C2B.F1 to 98.PADDO RA_c_0 +DOPAD_DEL --- 1.108 98.PADDO to 98.PAD RA[0] + -------- + 2.005 (67.7% logic, 32.3% route), 3 logic levels. + +Report: 2.492ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 1.949ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRCS_369 (from RCLK_c +) + Destination: Port Pad nRCS + + Data Path Delay: 1.462ns (86.5% logic, 13.5% route), 2 logic levels. + + Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. + + Constraint Details: + 0.487ns delay RCLK to SLICE_60 and + 1.462ns delay SLICE_60 to nRCS (totaling 1.949ns) meets + 0.000ns hold offset RCLK to nRCS by 1.949ns + + Physical Path Details: + + Clock path RCLK to SLICE_60: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 0.223 86.PADDI to R2C5B.CLK RCLK_c + -------- + 0.487 (54.2% logic, 45.8% route), 1 logic levels. + + Data path SLICE_60 to nRCS: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R2C5B.CLK to R2C5B.Q0 SLICE_60 (from RCLK_c) +ROUTE 1 0.197 R2C5B.Q0 to 77.PADDO nRCS_c +DOPAD_DEL --- 1.108 77.PADDO to 77.PAD nRCS + -------- + 1.462 (86.5% logic, 13.5% route), 2 logic levels. + +Report: 1.949ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.363ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RCKE_368 (from RCLK_c +) + Destination: Port Pad RCKE + + Data Path Delay: 1.876ns (67.4% logic, 32.6% route), 2 logic levels. + + Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. + + Constraint Details: + 0.487ns delay RCLK to SLICE_34 and + 1.876ns delay SLICE_34 to RCKE (totaling 2.363ns) meets + 0.000ns hold offset RCLK to RCKE by 2.363ns + + Physical Path Details: + + Clock path RCLK to SLICE_34: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 0.223 86.PADDI to R5C2A.CLK RCLK_c + -------- + 0.487 (54.2% logic, 45.8% route), 1 logic levels. + + Data path SLICE_34 to RCKE: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R5C2A.CLK to R5C2A.Q0 SLICE_34 (from RCLK_c) +ROUTE 4 0.611 R5C2A.Q0 to 82.PADDO RCKE_c +DOPAD_DEL --- 1.108 82.PADDO to 82.PAD RCKE + -------- + 1.876 (67.4% logic, 32.6% route), 2 logic levels. + +Report: 2.363ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 1.949ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRWE_372 (from RCLK_c +) + Destination: Port Pad nRWE + + Data Path Delay: 1.462ns (86.5% logic, 13.5% route), 2 logic levels. + + Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. + + Constraint Details: + 0.487ns delay RCLK to SLICE_63 and + 1.462ns delay SLICE_63 to nRWE (totaling 1.949ns) meets + 0.000ns hold offset RCLK to nRWE by 1.949ns + + Physical Path Details: + + Clock path RCLK to SLICE_63: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 0.223 86.PADDI to R3C5B.CLK RCLK_c + -------- + 0.487 (54.2% logic, 45.8% route), 1 logic levels. + + Data path SLICE_63 to nRWE: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R3C5B.CLK to R3C5B.Q0 SLICE_63 (from RCLK_c) +ROUTE 1 0.197 R3C5B.Q0 to 72.PADDO nRWE_c +DOPAD_DEL --- 1.108 72.PADDO to 72.PAD nRWE + -------- + 1.462 (86.5% logic, 13.5% route), 2 logic levels. + +Report: 1.949ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.236ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRRAS_370 (from RCLK_c +) + Destination: Port Pad nRRAS + + Data Path Delay: 1.749ns (72.3% logic, 27.7% route), 2 logic levels. + + Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. + + Constraint Details: + 0.487ns delay RCLK to SLICE_61 and + 1.749ns delay SLICE_61 to nRRAS (totaling 2.236ns) meets + 0.000ns hold offset RCLK to nRRAS by 2.236ns + + Physical Path Details: + + Clock path RCLK to SLICE_61: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 0.223 86.PADDI to R4C5A.CLK RCLK_c + -------- + 0.487 (54.2% logic, 45.8% route), 1 logic levels. + + Data path SLICE_61 to nRRAS: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R4C5A.CLK to R4C5A.Q0 SLICE_61 (from RCLK_c) +ROUTE 2 0.484 R4C5A.Q0 to 73.PADDO nRRAS_c +DOPAD_DEL --- 1.108 73.PADDO to 73.PAD nRRAS + -------- + 1.749 (72.3% logic, 27.7% route), 2 logic levels. + +Report: 2.236ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.232ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRCAS_371 (from RCLK_c +) + Destination: Port Pad nRCAS + + Data Path Delay: 1.745ns (72.5% logic, 27.5% route), 2 logic levels. + + Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. + + Constraint Details: + 0.487ns delay RCLK to SLICE_58 and + 1.745ns delay SLICE_58 to nRCAS (totaling 2.232ns) meets + 0.000ns hold offset RCLK to nRCAS by 2.232ns + + Physical Path Details: + + Clock path RCLK to SLICE_58: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 0.223 86.PADDI to R2C4C.CLK RCLK_c + -------- + 0.487 (54.2% logic, 45.8% route), 1 logic levels. + + Data path SLICE_58 to nRCAS: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R2C4C.CLK to R2C4C.Q0 SLICE_58 (from RCLK_c) +ROUTE 1 0.480 R2C4C.Q0 to 78.PADDO nRCAS_c +DOPAD_DEL --- 1.108 78.PADDO to 78.PAD nRCAS + -------- + 1.745 (72.5% logic, 27.5% route), 2 logic levels. + +Report: 2.232ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.443ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RDQMH + + Data Path Delay: 1.956ns (69.4% logic, 30.6% route), 3 logic levels. + + Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. + + Constraint Details: + 0.487ns delay RCLK to SLICE_64 and + 1.956ns delay SLICE_64 to RDQMH (totaling 2.443ns) meets + 0.000ns hold offset RCLK to RDQMH by 2.443ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c + -------- + 0.487 (54.2% logic, 45.8% route), 1 logic levels. + + Data path SLICE_64 to RDQMH: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.243 R2C2A.Q0 to R2C4A.C0 nRowColSel +CTOF_DEL --- 0.092 R2C4A.C0 to R2C4A.F0 SLICE_88 +ROUTE 1 0.356 R2C4A.F0 to 76.PADDO RDQMH_c +DOPAD_DEL --- 1.108 76.PADDO to 76.PAD RDQMH + -------- + 1.956 (69.4% logic, 30.6% route), 3 logic levels. + +Report: 2.443ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; + 1 item scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 2.713ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nRowColSel_375 (from RCLK_c +) + Destination: Port Pad RDQML + + Data Path Delay: 2.226ns (61.0% logic, 39.0% route), 3 logic levels. + + Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. + + Constraint Details: + 0.487ns delay RCLK to SLICE_64 and + 2.226ns delay SLICE_64 to RDQML (totaling 2.713ns) meets + 0.000ns hold offset RCLK to RDQML by 2.713ns + + Physical Path Details: + + Clock path RCLK to SLICE_64: + + Name Fanout Delay (ns) Site Resource +PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK +ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c + -------- + 0.487 (54.2% logic, 45.8% route), 1 logic levels. + + Data path SLICE_64 to RDQML: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) +ROUTE 13 0.238 R2C2A.Q0 to R3C2B.C0 nRowColSel +CTOF_DEL --- 0.092 R3C2B.C0 to R3C2B.F0 SLICE_92 +ROUTE 1 0.631 R3C2B.F0 to 61.PADDO RDQML_c +DOPAD_DEL --- 1.108 61.PADDO to 61.PAD RDQML + -------- + 2.226 (61.0% logic, 39.0% route), 3 logic levels. + +Report: 2.713ns is the maximum offset for this preference. + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference(MIN Delays) | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +PERIOD NET "PHI2_c" 350.000000 ns ; | -| -| 2 + | | | +PERIOD NET "nCCAS_c" 350.000000 ns ; | -| -| 0 + | | | +PERIOD NET "nCRAS_c" 350.000000 ns ; | -| -| 0 + | | | +PERIOD NET "RCLK_c" 16.000000 ns ; | -| -| 1 + | | | +CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[0]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[7]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[6]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[5]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[4]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[3]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[2]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "Dout[1]" 12.500000 | | | +ns CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.220 ns| 2 + | | | +CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.284 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.316 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.652 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.579 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.481 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.219 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.555 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.599 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.284 ns| 3 + | | | +CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.492 ns| 3 + | | | +CLOCK_TO_OUT PORT "nRCS" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 1.949 ns| 2 + | | | +CLOCK_TO_OUT PORT "RCKE" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.363 ns| 2 + | | | +CLOCK_TO_OUT PORT "nRWE" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 1.949 ns| 2 + | | | +CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.236 ns| 2 + | | | +CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.232 ns| 2 + | | | +CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.443 ns| 3 + | | | +CLOCK_TO_OUT PORT "RDQML" 12.500000 ns | | | +CLKPORT "RCLK" ; | 0.000 ns| 2.713 ns| 3 + | | | +CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns | | | +CLKPORT "RCLK" ; | -| -| 0 + | | | +---------------------------------------------------------------------------- + + +All preferences were met. + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 39 + Covered under: PERIOD NET "RCLK_c" 16.000000 ns ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: PERIOD NET "PHI2_c" 350.000000 ns ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 526 paths, 6 nets, and 440 connections (71.20% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 0 (setup), 0 (hold) +Score: 0 (setup), 0 (hold) +Cumulative negative slack: 0 (0+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_bgn.html b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_bgn.html new file mode 100644 index 0000000..0fd44c9 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_bgn.html @@ -0,0 +1,111 @@ + +Bitgen Report + + + + + diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_iotiming.html b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_iotiming.html new file mode 100644 index 0000000..61370c6 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_iotiming.html @@ -0,0 +1,202 @@ + +I/O Timing Report + + +
I/O Timing Report
+Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: 4
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: 5
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: M
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+// Design: RAM2GS
+// Package: TQFP100
+// ncd File: ram2gs_lcmxo256c_impl1.ncd
+// Version: Diamond (64-bit) 3.12.0.240.2
+// Written on Mon Aug 16 21:32:34 2021
+// M: Minimum Performance Grade
+// iotiming RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml
+
+I/O Timing Report (All units are in ns)
+
+Worst Case Results across Performance Grades (M, 5, 4, 3):
+
+// Input Setup and Hold Times
+
+Port    Clock Edge  Setup Performance_Grade  Hold Performance_Grade
+----------------------------------------------------------------------
+CROW[0] nCRAS F     0.215      3       1.805     3
+CROW[1] nCRAS F    -0.050      M       2.105     3
+Din[0]  PHI2  F     5.083      3       2.097     3
+Din[0]  nCCAS F    -0.020      M       2.133     3
+Din[1]  PHI2  F     3.519      3       2.454     3
+Din[1]  nCCAS F    -0.146      M       2.462     3
+Din[2]  PHI2  F     4.416      3       2.660     3
+Din[2]  nCCAS F     0.272      3       1.853     3
+Din[3]  PHI2  F     5.627      3       2.084     3
+Din[3]  nCCAS F    -0.024      M       2.144     3
+Din[4]  PHI2  F     4.808      3       2.117     3
+Din[4]  nCCAS F     0.350      3       1.766     3
+Din[5]  PHI2  F     5.446      3       2.212     3
+Din[5]  nCCAS F     0.435      3       1.708     3
+Din[6]  PHI2  F     5.339      3       1.487     3
+Din[6]  nCCAS F    -0.140      M       2.452     3
+Din[7]  PHI2  F     4.546      3       1.555     3
+Din[7]  nCCAS F    -0.016      M       2.122     3
+MAin[0] PHI2  F     4.027      3       0.711     3
+MAin[0] nCRAS F     1.132      3       0.987     3
+MAin[1] PHI2  F     4.032      3       1.734     3
+MAin[1] nCRAS F     0.704      3       1.373     3
+MAin[2] PHI2  F    10.358      3      -0.773     M
+MAin[2] nCRAS F    -0.202      M       2.529     3
+MAin[3] PHI2  F    10.442      3      -0.829     M
+MAin[3] nCRAS F     0.186      3       1.819     3
+MAin[4] PHI2  F    10.311      3      -0.765     M
+MAin[4] nCRAS F     0.569      3       1.506     3
+MAin[5] PHI2  F     7.007      3       0.178     3
+MAin[5] nCRAS F     0.186      3       1.819     3
+MAin[6] PHI2  F     9.786      3      -0.641     M
+MAin[6] nCRAS F     0.177      3       1.829     3
+MAin[7] PHI2  F    10.008      3      -0.718     M
+MAin[7] nCRAS F    -0.092      M       2.222     3
+MAin[8] nCRAS F    -0.202      M       2.532     3
+MAin[9] nCRAS F     0.228      3       1.797     3
+PHI2    RCLK  R     5.091      3      -0.759     M
+UFMSDO  RCLK  R     2.219      3      -0.104     M
+nCCAS   RCLK  R     3.820      3      -0.611     M
+nCCAS   nCRAS F     1.538      3       0.708     3
+nCRAS   RCLK  R     4.749      3      -0.670     M
+nFWE    PHI2  F     5.301      3       1.647     3
+nFWE    nCRAS F     1.049      3       1.128     3
+
+
+// Clock to Output Delay
+
+Port   Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
+------------------------------------------------------------------------
+LED    RCLK  R    11.669         3        3.051          M
+RA[0]  RCLK  R     9.674         3        2.492          M
+RA[0]  nCRAS F    12.127         3        3.067          M
+RA[10] RCLK  R     8.596         3        2.220          M
+RA[11] PHI2  R     9.987         3        2.559          M
+RA[1]  RCLK  R     8.766         3        2.284          M
+RA[1]  nCRAS F    11.652         3        2.982          M
+RA[2]  RCLK  R    10.062         3        2.599          M
+RA[2]  nCRAS F    12.947         3        3.306          M
+RA[3]  RCLK  R     9.933         3        2.555          M
+RA[3]  nCRAS F    12.783         3        3.240          M
+RA[4]  RCLK  R     8.504         3        2.219          M
+RA[4]  nCRAS F    11.513         3        2.948          M
+RA[5]  RCLK  R     9.609         3        2.481          M
+RA[5]  nCRAS F    11.870         3        3.010          M
+RA[6]  RCLK  R    10.001         3        2.579          M
+RA[6]  nCRAS F    12.947         3        3.292          M
+RA[7]  RCLK  R    10.255         3        2.652          M
+RA[7]  nCRAS F    12.177         3        3.089          M
+RA[8]  RCLK  R     8.896         3        2.316          M
+RA[8]  nCRAS F    11.417         3        2.920          M
+RA[9]  RCLK  R     8.766         3        2.284          M
+RA[9]  nCRAS F    11.617         3        2.957          M
+RBA[0] nCRAS F     9.698         3        2.483          M
+RBA[1] nCRAS F    11.425         3        2.916          M
+RCKE   RCLK  R     9.080         3        2.363          M
+RDQMH  RCLK  R     9.475         3        2.443          M
+RDQML  RCLK  R    10.477         3        2.713          M
+RD[0]  nCCAS F    11.252         3        2.942          M
+RD[1]  nCCAS F    11.963         3        3.100          M
+RD[2]  nCCAS F    12.880         3        3.336          M
+RD[3]  nCCAS F    12.422         3        3.224          M
+RD[4]  nCCAS F    11.252         3        2.942          M
+RD[5]  nCCAS F    12.423         3        3.212          M
+RD[6]  nCCAS F    12.979         3        3.375          M
+RD[7]  nCCAS F    12.914         3        3.350          M
+UFMCLK RCLK  R     8.007         3        2.126          M
+UFMSDI RCLK  R     8.007         3        2.126          M
+nRCAS  RCLK  R     8.595         3        2.232          M
+nRCS   RCLK  R     7.429         3        1.949          M
+nRRAS  RCLK  R     8.615         3        2.236          M
+nRWE   RCLK  R     7.429         3        1.949          M
+nUFMCS RCLK  R     9.193         3        2.413          M
+WARNING: you must also run trce with hold speed: 3
+WARNING: you must also run trce with setup speed: M
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+ + diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_lattice.synproj b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_lattice.synproj new file mode 100644 index 0000000..a0fe340 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_lattice.synproj @@ -0,0 +1,41 @@ +-a "MachXO" +-d LCMXO256C +-t TQFP100 +-s 3 +-frequency 200 +-optimization_goal Balanced +-bram_utilization 100 +-ramstyle Auto +-romstyle auto +-dsp_utilization 100 +-use_dsp 1 +-use_carry_chain 1 +-carry_chain_length 0 +-force_gsr Auto +-resource_sharing 1 +-propagate_constants 1 +-remove_duplicate_regs 1 +-mux_style Auto +-max_fanout 1000 +-fsm_encoding_style Auto +-twr_paths 3 +-fix_gated_clocks 1 +-loop_limit 1950 + + + +-use_io_insertion 1 +-resolve_mixed_drivers 0 +-use_io_reg auto + + +-lpf 1 +-p "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C" +-ver "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v" +-top RAM2GS + + +-p "C:/lscc/diamond/3.12/ispfpga/mj5g00/data" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/impl1" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C" + +-ngd "RAM2GS_LCMXO256C_impl1.ngd" + diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.asd b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.asd new file mode 100644 index 0000000..c70636c --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.asd @@ -0,0 +1,13 @@ +[ActiveSupport MAP] +Device = LCMXO256C; +Package = TQFP100; +Performance = 3; +LUTS_avail = 256; +LUTS_used = 129; +FF_avail = 256; +FF_used = 102; +INPUT_LVTTL33 = 26; +OUTPUT_LVTTL33 = 33; +BIDI_LVTTL33 = 8; +IO_avail = 78; +IO_used = 67; diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.cam b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.cam new file mode 100644 index 0000000..816529f --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.cam @@ -0,0 +1,108 @@ +[ START MERGED ] +nCRAS_N_9 nCRAS_c +nCCAS_N_3 nCCAS_c +n2307 Ready +n2306 nFWE_c +PHI2_N_114 PHI2_c +n2302 nRowColSel_N_35 +nRWE_N_172 nRWE_N_173 +UFMSDO_N_74 UFMSDO_c +n1377 nRowColSel_N_34 +RASr2_N_63 RASr2 +[ END MERGED ] +[ START CLIPPED ] +GND_net +VCC_net +FS_577_add_4_14/CO0 +FS_577_add_4_16/CO0 +FS_577_add_4_12/CO0 +FS_577_add_4_2/CO0 +FS_577_add_4_4/CO0 +FS_577_add_4_6/CO0 +FS_577_add_4_18/CO1 +FS_577_add_4_18/CO0 +FS_577_add_4_8/CO0 +FS_577_add_4_10/CO0 +[ END CLIPPED ] +[ START DESIGN PREFS ] +SCHEMATIC START ; +# map: version Diamond (64-bit) 3.12.0.240.2 -- WARNING: Map write only section -- Mon Aug 16 21:32:26 2021 + +SYSCONFIG INBUF=ON CONFIG_SECURE=OFF ; +LOCATE COMP "RD[7]" SITE "71" ; +LOCATE COMP "RD[6]" SITE "70" ; +LOCATE COMP "RD[5]" SITE "69" ; +LOCATE COMP "RD[4]" SITE "68" ; +LOCATE COMP "RD[3]" SITE "67" ; +LOCATE COMP "RD[2]" SITE "66" ; +LOCATE COMP "RD[1]" SITE "65" ; +LOCATE COMP "RD[0]" SITE "64" ; +LOCATE COMP "Dout[7]" SITE "3" ; +LOCATE COMP "Dout[6]" SITE "2" ; +LOCATE COMP "Dout[5]" SITE "5" ; +LOCATE COMP "Dout[4]" SITE "4" ; +LOCATE COMP "Dout[3]" SITE "6" ; +LOCATE COMP "Dout[2]" SITE "8" ; +LOCATE COMP "Dout[1]" SITE "7" ; +LOCATE COMP "Dout[0]" SITE "1" ; +LOCATE COMP "LED" SITE "57" ; +LOCATE COMP "RBA[1]" SITE "83" ; +LOCATE COMP "RBA[0]" SITE "63" ; +LOCATE COMP "RA[11]" SITE "79" ; +LOCATE COMP "RA[10]" SITE "87" ; +LOCATE COMP "RA[9]" SITE "85" ; +LOCATE COMP "RA[8]" SITE "96" ; +LOCATE COMP "RA[7]" SITE "100" ; +LOCATE COMP "RA[6]" SITE "91" ; +LOCATE COMP "RA[5]" SITE "95" ; +LOCATE COMP "RA[4]" SITE "99" ; +LOCATE COMP "RA[3]" SITE "97" ; +LOCATE COMP "RA[2]" SITE "94" ; +LOCATE COMP "RA[1]" SITE "89" ; +LOCATE COMP "RA[0]" SITE "98" ; +LOCATE COMP "nRCS" SITE "77" ; +LOCATE COMP "RCKE" SITE "82" ; +LOCATE COMP "nRWE" SITE "72" ; +LOCATE COMP "nRRAS" SITE "73" ; +LOCATE COMP "nRCAS" SITE "78" ; +LOCATE COMP "RDQMH" SITE "76" ; +LOCATE COMP "RDQML" SITE "61" ; +LOCATE COMP "nUFMCS" SITE "53" ; +LOCATE COMP "UFMCLK" SITE "58" ; +LOCATE COMP "UFMSDI" SITE "56" ; +LOCATE COMP "PHI2" SITE "39" ; +LOCATE COMP "MAin[9]" SITE "51" ; +LOCATE COMP "MAin[8]" SITE "50" ; +LOCATE COMP "MAin[7]" SITE "44" ; +LOCATE COMP "MAin[6]" SITE "49" ; +LOCATE COMP "MAin[5]" SITE "45" ; +LOCATE COMP "MAin[4]" SITE "46" ; +LOCATE COMP "MAin[3]" SITE "47" ; +LOCATE COMP "MAin[2]" SITE "37" ; +LOCATE COMP "MAin[1]" SITE "38" ; +LOCATE COMP "MAin[0]" SITE "23" ; +LOCATE COMP "CROW[1]" SITE "34" ; +LOCATE COMP "CROW[0]" SITE "32" ; +LOCATE COMP "Din[7]" SITE "19" ; +LOCATE COMP "Din[6]" SITE "20" ; +LOCATE COMP "Din[5]" SITE "17" ; +LOCATE COMP "Din[4]" SITE "18" ; +LOCATE COMP "Din[3]" SITE "16" ; +LOCATE COMP "Din[2]" SITE "14" ; +LOCATE COMP "Din[1]" SITE "15" ; +LOCATE COMP "Din[0]" SITE "21" ; +LOCATE COMP "nCCAS" SITE "27" ; +LOCATE COMP "nCRAS" SITE "43" ; +LOCATE COMP "nFWE" SITE "22" ; +LOCATE COMP "RCLK" SITE "86" ; +LOCATE COMP "UFMSDO" SITE "55" ; +PERIOD NET "PHI2_c" 350.000000 ns ; +USE PRIMARY NET "RCLK_c" ; +PERIOD NET "nCCAS_c" 350.000000 ns ; +USE PRIMARY NET "PHI2_c" ; +PERIOD NET "nCRAS_c" 350.000000 ns ; +USE PRIMARY NET "nCCAS_c" ; +PERIOD NET "RCLK_c" 16.000000 ns ; +USE PRIMARY NET "nCRAS_c" ; +SCHEMATIC END ; +[ END DESIGN PREFS ] diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.hrr b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.hrr new file mode 100644 index 0000000..5a900d5 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.hrr @@ -0,0 +1,10 @@ +--------------------------------------------------- +Report for cell RAM2GS + Instance path: RAM2GS + Cell usage: + cell count Res Usage(%) + SLIC 65.00 100.0 + LUT4 111.00 100.0 + IOBUF 67 100.0 + PFUREG 102 100.0 + RIPPLE 9 100.0 diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.ncd b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.ncd new file mode 100644 index 0000000000000000000000000000000000000000..81a1185f6f37cb7a88c7f60990b2114a5c7fe912 GIT binary patch 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+            Lattice Mapping Report File for Design Module 'RAM2GS'
+
+
+
+Design Information
+
+Command line:   map -a MachXO -p LCMXO256C -t TQFP100 -s 3 -oc Commercial
+     RAM2GS_LCMXO256C_impl1.ngd -o RAM2GS_LCMXO256C_impl1_map.ncd -pr
+     RAM2GS_LCMXO256C_impl1.prf -mp RAM2GS_LCMXO256C_impl1.mrp -lpf C:/Users/Dog
+     /Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.
+     lpf -lpf C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/RAM2GS_L
+     CMXO256C.lpf -c 0 -gui -msgset
+     C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml 
+Target Vendor:  LATTICE
+Target Device:  LCMXO256CTQFP100
+Target Performance:   3
+Mapper:  mj5g00,  version:  Diamond (64-bit) 3.12.0.240.2
+Mapped on:  08/16/21  21:32:26
+
+
+Design Summary
+   Number of PFU registers:   102 out of   256 (40%)
+   Number of SLICEs:        65 out of   128 (51%)
+      SLICEs as Logic/ROM:     65 out of   128 (51%)
+      SLICEs as RAM:            0 out of    64 (0%)
+      SLICEs as Carry:          9 out of   128 (7%)
+   Number of LUT4s:        129 out of   256 (50%)
+      Number used as logic LUTs:        111
+      Number used as distributed RAM:     0
+      Number used as ripple logic:       18
+      Number used as shift registers:     0
+   Number of external PIOs: 67 out of 78 (86%)
+   Number of GSRs:  0 out of 1 (0%)
+   JTAG used :      No
+   Readback used :  No
+   Oscillator used :  No
+   Startup used :   No
+   Number of TSALL: 0 out of 1 (0%)
+   Notes:-
+      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
+     distributed RAMs) + 2*(Number of ripple logic)
+      2. Number of logic LUT4s does not include count of distributed RAM and
+     ripple logic.
+   Number of clocks:  4
+     Net RCLK_c: 39 loads, 39 rising, 0 falling (Driver: PIO RCLK )
+     Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 )
+     Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
+     Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS )
+   Number of Clock Enables:  13
+     Net PHI2_N_114_enable_7: 2 loads, 2 LSLICEs
+     Net RCLK_c_enable_6: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_4: 3 loads, 3 LSLICEs
+     Net RCLK_c_enable_24: 2 loads, 2 LSLICEs
+     Net RCLK_c_enable_3: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_7: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_23: 8 loads, 8 LSLICEs
+     Net PHI2_N_114_enable_1: 1 loads, 1 LSLICEs
+     Net PHI2_N_114_enable_8: 1 loads, 1 LSLICEs
+     Net PHI2_N_114_enable_6: 2 loads, 2 LSLICEs
+     Net PHI2_N_114_enable_2: 1 loads, 1 LSLICEs
+
+     Net RCLK_c_enable_25: 1 loads, 1 LSLICEs
+     Net Ready_N_268: 1 loads, 1 LSLICEs
+   Number of LSRs:  9
+     Net RASr2: 1 loads, 1 LSLICEs
+     Net C1Submitted_N_225: 2 loads, 2 LSLICEs
+     Net n2299: 1 loads, 1 LSLICEs
+     Net nRowColSel_N_35: 1 loads, 1 LSLICEs
+     Net nRowColSel_N_34: 1 loads, 1 LSLICEs
+     Net LEDEN_N_88: 1 loads, 1 LSLICEs
+     Net n2291: 2 loads, 2 LSLICEs
+     Net Ready: 7 loads, 7 LSLICEs
+     Net nRWE_N_173: 1 loads, 1 LSLICEs
+   Number of nets driven by tri-state buffers:  0
+   Top 10 highest fanout non-clock nets:
+     Net Ready: 19 loads
+     Net InitReady: 17 loads
+     Net RASr2: 16 loads
+     Net nRowColSel_N_35: 14 loads
+     Net nRowColSel: 13 loads
+     Net Din_c_6: 9 loads
+     Net MAin_c_1: 9 loads
+     Net Din_c_5: 8 loads
+     Net FS_11: 8 loads
+     Net MAin_c_0: 8 loads
+
+
+
+
+   Number of warnings:  0
+   Number of errors:    0
+     
+
+
+
+
+Design Errors/Warnings
+
+   No errors or warnings present.
+
+
+
+IO (PIO) Attributes
+
++---------------------+-----------+-----------+------------+------------+
+| IO Name             | Direction | Levelmode | IO         | FIXEDDELAY |
+|                     |           |  IO_TYPE  | Register   |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[7]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[6]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[5]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[4]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[3]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[2]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+
+| RD[1]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[0]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[7]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[6]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[5]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[4]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[3]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[2]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[1]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[0]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| LED                 | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RBA[1]              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RBA[0]              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[11]              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[10]              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[9]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[8]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[7]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[6]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[5]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[4]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[3]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[2]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[1]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[0]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nRCS                | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RCKE                | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nRWE                | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+
+| nRRAS               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nRCAS               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RDQMH               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RDQML               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nUFMCS              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| UFMCLK              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| UFMSDI              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| PHI2                | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[9]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[8]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[7]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[6]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[5]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[4]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[3]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[2]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[1]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[0]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| CROW[1]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| CROW[0]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[7]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[6]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[5]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[4]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[3]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[2]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[1]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[0]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+
+| nCCAS               | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nCRAS               | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nFWE                | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RCLK                | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| UFMSDO              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+
+
+
+Removed logic
+
+Block i2 undriven or does not drive anything - clipped.
+Block GSR_INST undriven or does not drive anything - clipped.
+Signal PHI2_N_114 was merged into signal PHI2_c
+Signal nCRAS_N_9 was merged into signal nCRAS_c
+Signal nCCAS_N_3 was merged into signal nCCAS_c
+Signal n2302 was merged into signal nRowColSel_N_35
+Signal nRWE_N_172 was merged into signal nRWE_N_173
+Signal n2307 was merged into signal Ready
+Signal RASr2_N_63 was merged into signal RASr2
+Signal n1377 was merged into signal nRowColSel_N_34
+Signal n2306 was merged into signal nFWE_c
+Signal UFMSDO_N_74 was merged into signal UFMSDO_c
+Signal GND_net undriven or does not drive anything - clipped.
+Signal VCC_net undriven or does not drive anything - clipped.
+Signal FS_577_add_4_14/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_16/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_12/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_2/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_4/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_6/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_18/CO1 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_18/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_8/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_10/CO0 undriven or does not drive anything - clipped.
+Block i1962 was optimized away.
+Block i1961 was optimized away.
+Block i1963 was optimized away.
+Block i1070_1_lut_rep_25 was optimized away.
+Block nRWE_I_49_1_lut was optimized away.
+Block i604_1_lut_rep_30 was optimized away.
+Block RASr2_I_0_1_lut was optimized away.
+Block i1069_1_lut was optimized away.
+Block i1_1_lut_rep_29 was optimized away.
+Block UFMSDO_I_0_1_lut was optimized away.
+Block i1 was optimized away.
+
+
+
+Run Time and Memory Usage
+-------------------------
+
+   Total CPU Time: 0 secs  
+   Total REAL Time: 0 secs  
+   Peak Memory Usage: 29 MB
+
+        
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+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+     Copyright (c) 1995 AT&T Corp.   All rights reserved.
+     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+     Copyright (c) 2001 Agere Systems   All rights reserved.
+     Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights
+     reserved.
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+
+ + diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_pad.html b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_pad.html new file mode 100644 index 0000000..911c6d4 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_pad.html @@ -0,0 +1,336 @@ + +PAD Specification File + + +
PAD Specification File
+***************************
+
+PART TYPE:        LCMXO256C
+Performance Grade:      3
+PACKAGE:          TQFP100
+Package Status:                     Final          Version 1.19
+
+Mon Aug 16 21:32:33 2021
+
+Pinout by Port Name:
++-----------+----------+--------------+------+----------------------------------+
+| Port Name | Pin/Bank | Buffer Type  | Site | Properties                       |
++-----------+----------+--------------+------+----------------------------------+
+| CROW[0]   | 32/1     | LVTTL33_IN   | PB2C | SLEW:FAST                        |
+| CROW[1]   | 34/1     | LVTTL33_IN   | PB2D | SLEW:FAST                        |
+| Din[0]    | 21/1     | LVTTL33_IN   | PL8A | SLEW:FAST                        |
+| Din[1]    | 15/1     | LVTTL33_IN   | PL6A | SLEW:FAST                        |
+| Din[2]    | 14/1     | LVTTL33_IN   | PL5D | SLEW:FAST                        |
+| Din[3]    | 16/1     | LVTTL33_IN   | PL6B | SLEW:FAST                        |
+| Din[4]    | 18/1     | LVTTL33_IN   | PL7B | SLEW:FAST                        |
+| Din[5]    | 17/1     | LVTTL33_IN   | PL7A | SLEW:FAST                        |
+| Din[6]    | 20/1     | LVTTL33_IN   | PL7D | SLEW:FAST                        |
+| Din[7]    | 19/1     | LVTTL33_IN   | PL7C | SLEW:FAST                        |
+| Dout[0]   | 1/1      | LVTTL33_OUT  | PL2A | DRIVE:4mA SLEW:SLOW              |
+| Dout[1]   | 7/1      | LVTTL33_OUT  | PL4A | DRIVE:4mA SLEW:SLOW              |
+| Dout[2]   | 8/1      | LVTTL33_OUT  | PL4B | DRIVE:4mA SLEW:SLOW              |
+| Dout[3]   | 6/1      | LVTTL33_OUT  | PL3D | DRIVE:4mA SLEW:SLOW              |
+| Dout[4]   | 4/1      | LVTTL33_OUT  | PL3B | DRIVE:4mA SLEW:SLOW              |
+| Dout[5]   | 5/1      | LVTTL33_OUT  | PL3C | DRIVE:4mA SLEW:SLOW              |
+| Dout[6]   | 2/1      | LVTTL33_OUT  | PL2B | DRIVE:4mA SLEW:SLOW              |
+| Dout[7]   | 3/1      | LVTTL33_OUT  | PL3A | DRIVE:4mA SLEW:SLOW              |
+| LED       | 57/0     | LVTTL33_OUT  | PR7B | DRIVE:16mA SLEW:SLOW             |
+| MAin[0]   | 23/1     | LVTTL33_IN   | PL9A | SLEW:FAST                        |
+| MAin[1]   | 38/1     | LVTTL33_IN   | PB3C | SLEW:FAST                        |
+| MAin[2]   | 37/1     | LVTTL33_IN   | PB3B | SLEW:FAST                        |
+| MAin[3]   | 47/1     | LVTTL33_IN   | PB5A | SLEW:FAST                        |
+| MAin[4]   | 46/1     | LVTTL33_IN   | PB4D | SLEW:FAST                        |
+| MAin[5]   | 45/1     | LVTTL33_IN   | PB4C | SLEW:FAST                        |
+| MAin[6]   | 49/1     | LVTTL33_IN   | PB5C | SLEW:FAST                        |
+| MAin[7]   | 44/1     | LVTTL33_IN   | PB4B | SLEW:FAST                        |
+| MAin[8]   | 50/1     | LVTTL33_IN   | PB5D | SLEW:FAST                        |
+| MAin[9]   | 51/0     | LVTTL33_IN   | PR9B | SLEW:FAST                        |
+| PHI2      | 39/1     | LVTTL33_IN   | PB3D | SLEW:FAST                        |
+| RA[0]     | 98/0     | LVTTL33_OUT  | PT2C | DRIVE:4mA SLEW:SLOW              |
+| RA[10]    | 87/0     | LVTTL33_OUT  | PT3D | DRIVE:4mA SLEW:SLOW              |
+| RA[11]    | 79/0     | LVTTL33_OUT  | PT5A | DRIVE:4mA SLEW:SLOW              |
+| RA[1]     | 89/0     | LVTTL33_OUT  | PT3C | DRIVE:4mA SLEW:SLOW              |
+| RA[2]     | 94/0     | LVTTL33_OUT  | PT3A | DRIVE:4mA SLEW:SLOW              |
+| RA[3]     | 97/0     | LVTTL33_OUT  | PT2D | DRIVE:4mA SLEW:SLOW              |
+| RA[4]     | 99/0     | LVTTL33_OUT  | PT2B | DRIVE:4mA SLEW:SLOW              |
+| RA[5]     | 95/0     | LVTTL33_OUT  | PT2F | DRIVE:4mA SLEW:SLOW              |
+| RA[6]     | 91/0     | LVTTL33_OUT  | PT3B | DRIVE:4mA SLEW:SLOW              |
+| RA[7]     | 100/0    | LVTTL33_OUT  | PT2A | DRIVE:4mA SLEW:SLOW              |
+| RA[8]     | 96/0     | LVTTL33_OUT  | PT2E | DRIVE:4mA SLEW:SLOW              |
+| RA[9]     | 85/0     | LVTTL33_OUT  | PT4B | DRIVE:4mA SLEW:SLOW              |
+| RBA[0]    | 63/0     | LVTTL33_OUT  | PR5D | DRIVE:4mA SLEW:SLOW              |
+| RBA[1]    | 83/0     | LVTTL33_OUT  | PT4C | DRIVE:4mA SLEW:SLOW              |
+| RCKE      | 82/0     | LVTTL33_OUT  | PT4D | DRIVE:4mA SLEW:SLOW              |
+| RCLK      | 86/0     | LVTTL33_IN   | PT4A | SLEW:FAST                        |
+| RDQMH     | 76/0     | LVTTL33_OUT  | PR2A | DRIVE:4mA SLEW:SLOW              |
+| RDQML     | 61/0     | LVTTL33_OUT  | PR6A | DRIVE:4mA SLEW:SLOW              |
+| RD[0]     | 64/0     | LVTTL33_BIDI | PR5C | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[1]     | 65/0     | LVTTL33_BIDI | PR5B | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[2]     | 66/0     | LVTTL33_BIDI | PR5A | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[3]     | 67/0     | LVTTL33_BIDI | PR4B | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[4]     | 68/0     | LVTTL33_BIDI | PR4A | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[5]     | 69/0     | LVTTL33_BIDI | PR3D | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[6]     | 70/0     | LVTTL33_BIDI | PR3C | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[7]     | 71/0     | LVTTL33_BIDI | PR3B | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| UFMCLK    | 58/0     | LVTTL33_OUT  | PR7A | DRIVE:4mA SLEW:SLOW              |
+| UFMSDI    | 56/0     | LVTTL33_OUT  | PR7C | DRIVE:4mA SLEW:SLOW              |
+| UFMSDO    | 55/0     | LVTTL33_IN   | PR7D | SLEW:FAST PULL:KEEPER            |
+| nCCAS     | 27/1     | LVTTL33_IN   | PL9B | SLEW:FAST                        |
+| nCRAS     | 43/1     | LVTTL33_IN   | PB4A | SLEW:FAST                        |
+| nFWE      | 22/1     | LVTTL33_IN   | PL8B | SLEW:FAST                        |
+| nRCAS     | 78/0     | LVTTL33_OUT  | PT5B | DRIVE:4mA SLEW:SLOW              |
+| nRCS      | 77/0     | LVTTL33_OUT  | PT5C | DRIVE:4mA SLEW:SLOW              |
+| nRRAS     | 73/0     | LVTTL33_OUT  | PR2B | DRIVE:4mA SLEW:SLOW              |
+| nRWE      | 72/0     | LVTTL33_OUT  | PR3A | DRIVE:4mA SLEW:SLOW              |
+| nUFMCS    | 53/0     | LVTTL33_OUT  | PR8B | DRIVE:4mA SLEW:SLOW              |
++-----------+----------+--------------+------+----------------------------------+
+
+Vccio by Bank:
++------+-------+
+| Bank | Vccio |
++------+-------+
+| 0    | 3.3V  |
+| 1    | 3.3V  |
++------+-------+
+
+
+Vref by Bank:
++------+-----+-----------------+---------+
+| Vref | Pin | Bank # / Vref # | Load(s) |
++------+-----+-----------------+---------+
++------+-----+-----------------+---------+
+
+Pinout by Pin Number:
++----------+---------------------+------------+--------------+------+---------------+
+| Pin/Bank | Pin Info            | Preference | Buffer Type  | Site | Dual Function |
++----------+---------------------+------------+--------------+------+---------------+
+| 1/1      | Dout[0]             | LOCATED    | LVTTL33_OUT  | PL2A |               |
+| 2/1      | Dout[6]             | LOCATED    | LVTTL33_OUT  | PL2B |               |
+| 3/1      | Dout[7]             | LOCATED    | LVTTL33_OUT  | PL3A |               |
+| 4/1      | Dout[4]             | LOCATED    | LVTTL33_OUT  | PL3B |               |
+| 5/1      | Dout[5]             | LOCATED    | LVTTL33_OUT  | PL3C |               |
+| 6/1      | Dout[3]             | LOCATED    | LVTTL33_OUT  | PL3D |               |
+| 7/1      | Dout[1]             | LOCATED    | LVTTL33_OUT  | PL4A |               |
+| 8/1      | Dout[2]             | LOCATED    | LVTTL33_OUT  | PL4B |               |
+| 9/1      |     unused, PULL:UP |            |              | PL5A |               |
+| 11/1     |     unused, PULL:UP |            |              | PL5B |               |
+| 13/1     |     unused, PULL:UP |            |              | PL5C |               |
+| 14/1     | Din[2]              | LOCATED    | LVTTL33_IN   | PL5D | GSR_PADN      |
+| 15/1     | Din[1]              | LOCATED    | LVTTL33_IN   | PL6A |               |
+| 16/1     | Din[3]              | LOCATED    | LVTTL33_IN   | PL6B | TSALLPAD      |
+| 17/1     | Din[5]              | LOCATED    | LVTTL33_IN   | PL7A |               |
+| 18/1     | Din[4]              | LOCATED    | LVTTL33_IN   | PL7B |               |
+| 19/1     | Din[7]              | LOCATED    | LVTTL33_IN   | PL7C |               |
+| 20/1     | Din[6]              | LOCATED    | LVTTL33_IN   | PL7D |               |
+| 21/1     | Din[0]              | LOCATED    | LVTTL33_IN   | PL8A |               |
+| 22/1     | nFWE                | LOCATED    | LVTTL33_IN   | PL8B |               |
+| 23/1     | MAin[0]             | LOCATED    | LVTTL33_IN   | PL9A |               |
+| 27/1     | nCCAS               | LOCATED    | LVTTL33_IN   | PL9B |               |
+| 29/1     |     unused, PULL:UP |            |              | PB2A |               |
+| 30/1     |     unused, PULL:UP |            |              | PB2B |               |
+| 32/1     | CROW[0]             | LOCATED    | LVTTL33_IN   | PB2C |               |
+| 34/1     | CROW[1]             | LOCATED    | LVTTL33_IN   | PB2D |               |
+| 36/1     |     unused, PULL:UP |            |              | PB3A | PCLKT1_1      |
+| 37/1     | MAin[2]             | LOCATED    | LVTTL33_IN   | PB3B |               |
+| 38/1     | MAin[1]             | LOCATED    | LVTTL33_IN   | PB3C | PCLKT1_0      |
+| 39/1     | PHI2                | LOCATED    | LVTTL33_IN   | PB3D |               |
+| 43/1     | nCRAS               | LOCATED    | LVTTL33_IN   | PB4A |               |
+| 44/1     | MAin[7]             | LOCATED    | LVTTL33_IN   | PB4B |               |
+| 45/1     | MAin[5]             | LOCATED    | LVTTL33_IN   | PB4C |               |
+| 46/1     | MAin[4]             | LOCATED    | LVTTL33_IN   | PB4D |               |
+| 47/1     | MAin[3]             | LOCATED    | LVTTL33_IN   | PB5A |               |
+| 49/1     | MAin[6]             | LOCATED    | LVTTL33_IN   | PB5C |               |
+| 50/1     | MAin[8]             | LOCATED    | LVTTL33_IN   | PB5D |               |
+| 51/0     | MAin[9]             | LOCATED    | LVTTL33_IN   | PR9B |               |
+| 52/0     |     unused, PULL:UP |            |              | PR9A |               |
+| 53/0     | nUFMCS              | LOCATED    | LVTTL33_OUT  | PR8B |               |
+| 54/0     |     unused, PULL:UP |            |              | PR8A |               |
+| 55/0     | UFMSDO              | LOCATED    | LVTTL33_IN   | PR7D |               |
+| 56/0     | UFMSDI              | LOCATED    | LVTTL33_OUT  | PR7C |               |
+| 57/0     | LED                 | LOCATED    | LVTTL33_OUT  | PR7B |               |
+| 58/0     | UFMCLK              | LOCATED    | LVTTL33_OUT  | PR7A |               |
+| 59/0     |     unused, PULL:UP |            |              | PR6B |               |
+| 61/0     | RDQML               | LOCATED    | LVTTL33_OUT  | PR6A |               |
+| 63/0     | RBA[0]              | LOCATED    | LVTTL33_OUT  | PR5D |               |
+| 64/0     | RD[0]               | LOCATED    | LVTTL33_BIDI | PR5C |               |
+| 65/0     | RD[1]               | LOCATED    | LVTTL33_BIDI | PR5B |               |
+| 66/0     | RD[2]               | LOCATED    | LVTTL33_BIDI | PR5A |               |
+| 67/0     | RD[3]               | LOCATED    | LVTTL33_BIDI | PR4B |               |
+| 68/0     | RD[4]               | LOCATED    | LVTTL33_BIDI | PR4A |               |
+| 69/0     | RD[5]               | LOCATED    | LVTTL33_BIDI | PR3D |               |
+| 70/0     | RD[6]               | LOCATED    | LVTTL33_BIDI | PR3C |               |
+| 71/0     | RD[7]               | LOCATED    | LVTTL33_BIDI | PR3B |               |
+| 72/0     | nRWE                | LOCATED    | LVTTL33_OUT  | PR3A |               |
+| 73/0     | nRRAS               | LOCATED    | LVTTL33_OUT  | PR2B |               |
+| 76/0     | RDQMH               | LOCATED    | LVTTL33_OUT  | PR2A |               |
+| 77/0     | nRCS                | LOCATED    | LVTTL33_OUT  | PT5C |               |
+| 78/0     | nRCAS               | LOCATED    | LVTTL33_OUT  | PT5B |               |
+| 79/0     | RA[11]              | LOCATED    | LVTTL33_OUT  | PT5A |               |
+| 80/0     |     unused, PULL:UP |            |              | PT4F |               |
+| 81/0     |     unused, PULL:UP |            |              | PT4E |               |
+| 82/0     | RCKE                | LOCATED    | LVTTL33_OUT  | PT4D |               |
+| 83/0     | RBA[1]              | LOCATED    | LVTTL33_OUT  | PT4C |               |
+| 85/0     | RA[9]               | LOCATED    | LVTTL33_OUT  | PT4B | PCLKT0_1      |
+| 86/0     | RCLK                | LOCATED    | LVTTL33_IN   | PT4A | PCLKT0_0      |
+| 87/0     | RA[10]              | LOCATED    | LVTTL33_OUT  | PT3D |               |
+| 89/0     | RA[1]               | LOCATED    | LVTTL33_OUT  | PT3C |               |
+| 91/0     | RA[6]               | LOCATED    | LVTTL33_OUT  | PT3B |               |
+| 94/0     | RA[2]               | LOCATED    | LVTTL33_OUT  | PT3A |               |
+| 95/0     | RA[5]               | LOCATED    | LVTTL33_OUT  | PT2F |               |
+| 96/0     | RA[8]               | LOCATED    | LVTTL33_OUT  | PT2E |               |
+| 97/0     | RA[3]               | LOCATED    | LVTTL33_OUT  | PT2D |               |
+| 98/0     | RA[0]               | LOCATED    | LVTTL33_OUT  | PT2C |               |
+| 99/0     | RA[4]               | LOCATED    | LVTTL33_OUT  | PT2B |               |
+| 100/0    | RA[7]               | LOCATED    | LVTTL33_OUT  | PT2A |               |
+| PB5B/0   |     unused, PULL:UP |            |              | PB5B |               |
+| PT5D/0   |     unused, PULL:UP |            |              | PT5D |               |
+| TCK/1    |                     |            |              | TCK  | TCK           |
+| TDI/1    |                     |            |              | TDI  | TDI           |
+| TDO/1    |                     |            |              | TDO  | TDO           |
+| TMS/1    |                     |            |              | TMS  | TMS           |
++----------+---------------------+------------+--------------+------+---------------+
+
+
+List of All Pins' Locate Preferences Based on Final Placement After PAR 
+to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
+
+LOCATE  COMP  "CROW[0]"  SITE  "32";
+LOCATE  COMP  "CROW[1]"  SITE  "34";
+LOCATE  COMP  "Din[0]"  SITE  "21";
+LOCATE  COMP  "Din[1]"  SITE  "15";
+LOCATE  COMP  "Din[2]"  SITE  "14";
+LOCATE  COMP  "Din[3]"  SITE  "16";
+LOCATE  COMP  "Din[4]"  SITE  "18";
+LOCATE  COMP  "Din[5]"  SITE  "17";
+LOCATE  COMP  "Din[6]"  SITE  "20";
+LOCATE  COMP  "Din[7]"  SITE  "19";
+LOCATE  COMP  "Dout[0]"  SITE  "1";
+LOCATE  COMP  "Dout[1]"  SITE  "7";
+LOCATE  COMP  "Dout[2]"  SITE  "8";
+LOCATE  COMP  "Dout[3]"  SITE  "6";
+LOCATE  COMP  "Dout[4]"  SITE  "4";
+LOCATE  COMP  "Dout[5]"  SITE  "5";
+LOCATE  COMP  "Dout[6]"  SITE  "2";
+LOCATE  COMP  "Dout[7]"  SITE  "3";
+LOCATE  COMP  "LED"  SITE  "57";
+LOCATE  COMP  "MAin[0]"  SITE  "23";
+LOCATE  COMP  "MAin[1]"  SITE  "38";
+LOCATE  COMP  "MAin[2]"  SITE  "37";
+LOCATE  COMP  "MAin[3]"  SITE  "47";
+LOCATE  COMP  "MAin[4]"  SITE  "46";
+LOCATE  COMP  "MAin[5]"  SITE  "45";
+LOCATE  COMP  "MAin[6]"  SITE  "49";
+LOCATE  COMP  "MAin[7]"  SITE  "44";
+LOCATE  COMP  "MAin[8]"  SITE  "50";
+LOCATE  COMP  "MAin[9]"  SITE  "51";
+LOCATE  COMP  "PHI2"  SITE  "39";
+LOCATE  COMP  "RA[0]"  SITE  "98";
+LOCATE  COMP  "RA[10]"  SITE  "87";
+LOCATE  COMP  "RA[11]"  SITE  "79";
+LOCATE  COMP  "RA[1]"  SITE  "89";
+LOCATE  COMP  "RA[2]"  SITE  "94";
+LOCATE  COMP  "RA[3]"  SITE  "97";
+LOCATE  COMP  "RA[4]"  SITE  "99";
+LOCATE  COMP  "RA[5]"  SITE  "95";
+LOCATE  COMP  "RA[6]"  SITE  "91";
+LOCATE  COMP  "RA[7]"  SITE  "100";
+LOCATE  COMP  "RA[8]"  SITE  "96";
+LOCATE  COMP  "RA[9]"  SITE  "85";
+LOCATE  COMP  "RBA[0]"  SITE  "63";
+LOCATE  COMP  "RBA[1]"  SITE  "83";
+LOCATE  COMP  "RCKE"  SITE  "82";
+LOCATE  COMP  "RCLK"  SITE  "86";
+LOCATE  COMP  "RDQMH"  SITE  "76";
+LOCATE  COMP  "RDQML"  SITE  "61";
+LOCATE  COMP  "RD[0]"  SITE  "64";
+LOCATE  COMP  "RD[1]"  SITE  "65";
+LOCATE  COMP  "RD[2]"  SITE  "66";
+LOCATE  COMP  "RD[3]"  SITE  "67";
+LOCATE  COMP  "RD[4]"  SITE  "68";
+LOCATE  COMP  "RD[5]"  SITE  "69";
+LOCATE  COMP  "RD[6]"  SITE  "70";
+LOCATE  COMP  "RD[7]"  SITE  "71";
+LOCATE  COMP  "UFMCLK"  SITE  "58";
+LOCATE  COMP  "UFMSDI"  SITE  "56";
+LOCATE  COMP  "UFMSDO"  SITE  "55";
+LOCATE  COMP  "nCCAS"  SITE  "27";
+LOCATE  COMP  "nCRAS"  SITE  "43";
+LOCATE  COMP  "nFWE"  SITE  "22";
+LOCATE  COMP  "nRCAS"  SITE  "78";
+LOCATE  COMP  "nRCS"  SITE  "77";
+LOCATE  COMP  "nRRAS"  SITE  "73";
+LOCATE  COMP  "nRWE"  SITE  "72";
+LOCATE  COMP  "nUFMCS"  SITE  "53";
+
+
+
+
+
+PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Mon Aug 16 21:32:33 2021
+
+
+
+
+

+

+

+

+

+

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+

+

+

+

+

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+

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+

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+

+

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+

+

+
+ + diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_par.html b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_par.html new file mode 100644 index 0000000..ce22106 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_par.html @@ -0,0 +1,307 @@ + +Place & Route Report + + +
PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Mon Aug 16 21:32:27 2021
+
+C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO256C_impl1.p2t
+RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir
+RAM2GS_LCMXO256C_impl1.prf -gui -msgset
+C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml
+
+
+Preference file: RAM2GS_LCMXO256C_impl1.prf.
+
+Cost Table Summary
+Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
+Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
+----------   --------     -----        ------       -----------  -----------  ----         ------
+5_1   *      0            2.023        0            0.339        0            07           Completed
+* : Design saved.
+
+Total (real) run time for 1-seed: 7 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Lattice Place and Route Report for Design "RAM2GS_LCMXO256C_impl1_map.ncd"
+Mon Aug 16 21:32:27 2021
+
+
+Best Par Run
+PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir/5_1.ncd RAM2GS_LCMXO256C_impl1.prf
+Preference file: RAM2GS_LCMXO256C_impl1.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file RAM2GS_LCMXO256C_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: 3
+Loading device for application par from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+
+Device utilization summary:
+
+   PIO (prelim)      67/79           84% used
+                     67/78           85% bonded
+   SLICE             65/128          50% used
+
+
+
+Number of Signals: 252
+Number of Connections: 618
+
+Pin Constraint Summary:
+   67 out of 67 pins locked (100% locked).
+
+The following 4 signals are selected to use the primary clock routing resources:
+    RCLK_c (driver: RCLK, clk load #: 39)
+    PHI2_c (driver: PHI2, clk load #: 13)
+    nCCAS_c (driver: nCCAS, clk load #: 4)
+    nCRAS_c (driver: nCRAS, clk load #: 7)
+
+No signal is selected as secondary clock.
+
+No signal is selected as Global Set/Reset.
+Starting Placer Phase 0.
+........
+Finished Placer Phase 0.  REAL time: 0 secs 
+
+Starting Placer Phase 1.
+...............
+Placer score = 586066.
+Finished Placer Phase 1.  REAL time: 6 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  584668
+Finished Placer Phase 2.  REAL time: 6 secs 
+
+
+
+Clock Report
+
+Global Clock Resources:
+  CLK_PIN    : 1 out of 4 (25%)
+  General PIO: 3 out of 80 (3%)
+
+Global Clocks:
+  PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT4A)", clk load = 39
+  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB3D)", clk load = 13
+  PRIMARY "nCCAS_c" from comp "nCCAS" on PIO site "27 (PL9B)", clk load = 4
+  PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB4A)", clk load = 7
+
+  PRIMARY  : 4 out of 4 (100%)
+  SECONDARY: 0 out of 4 (0%)
+
+
+
+
+I/O Usage Summary (final):
+   67 out of 79 (84.8%) PIO sites used.
+   67 out of 78 (85.9%) bonded PIO sites used.
+   Number of PIO comps: 67; differential: 0.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+----------------+------------+------------+------------+
+| I/O Bank | Usage          | Bank Vccio | Bank Vref1 | Bank Vref2 |
++----------+----------------+------------+------------+------------+
+| 0        | 36 / 41 ( 87%) | 3.3V       | -          | -          |
+| 1        | 31 / 37 ( 83%) | 3.3V       | -          | -          |
++----------+----------------+------------+------------+------------+
+
+Total placer CPU time: 6 secs 
+
+Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd.
+
+0 connections routed; 618 unrouted.
+Starting router resource preassignment
+WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks.  This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
+WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the PIO sites dedicated for primary clocks.  This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
+WARNING - par: The driver of primary clock net nCCAS_c is not placed on one of the PIO sites dedicated for primary clocks.  This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
+
+Completed router resource preassignment. Real time: 6 secs 
+
+Start NBR router at 21:32:33 08/16/21
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at 21:32:33 08/16/21
+
+Start NBR section for initial routing at 21:32:33 08/16/21
+Level 1, iteration 1
+0(0.00%) conflict; 535(86.57%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 2.084ns/0.000ns; real time: 6 secs 
+Level 2, iteration 1
+0(0.00%) conflict; 535(86.57%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 2.084ns/0.000ns; real time: 6 secs 
+Level 3, iteration 1
+0(0.00%) conflict; 509(82.36%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 2.038ns/0.000ns; real time: 6 secs 
+Level 4, iteration 1
+23(0.19%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 21:32:33 08/16/21
+Level 1, iteration 1
+0(0.00%) conflict; 24(3.88%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs 
+Level 4, iteration 1
+8(0.07%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs 
+Level 4, iteration 2
+4(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs 
+Level 4, iteration 3
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs 
+
+Start NBR section for setup/hold timing optimization with effort level 3 at 21:32:33 08/16/21
+
+Start NBR section for re-routing at 21:32:33 08/16/21
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs 
+
+Start NBR section for post-routing at 21:32:33 08/16/21
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 0 (0.00%)
+  Estimated worst slack<setup> : 2.023ns
+  Timing score<setup> : 0
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+Total CPU time 6 secs 
+Total REAL time: 7 secs 
+Completely routed.
+End of route.  618 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 0 
+
+Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = Completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack<setup/<ns>> = 2.023
+PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
+PAR_SUMMARY::Worst  slack<hold /<ns>> = 0.339
+PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 6 secs 
+Total REAL time to completion: 7 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
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RAM2GS_LCMXO256C project summary
Module Name:RAM2GS_LCMXO256CSynthesis:Lattice LSE
Implementation Name:impl1Strategy Name:Strategy1
Last Process:JEDEC FileState:Passed
Target Device:LCMXO256C-3T100CDevice Family:MachXO
Device Type:LCMXO256CPackage Type:TQFP100
Performance grade:3Operating conditions:COM
Logic preference file:RAM2GS_LCMXO256C.lpf
Physical Preference file:impl1/RAM2GS_LCMXO256C_impl1.prf
Product Version:3.12.0.240.2Patch Version:
Updated:2021/08/16 21:36:29
Implementation Location:C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/impl1
Project File:C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ldf

+

+

+

+

+

+
+ + diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_tw1.html b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_tw1.html new file mode 100644 index 0000000..01aa986 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_tw1.html @@ -0,0 +1,2740 @@ + +Lattice Map TRACE Report + + +
Map TRACE Report
+
+Loading design for application trce from file ram2gs_lcmxo256c_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: 3
+Loading device for application trce from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
+Mon Aug 16 21:32:27 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf 
+Design file:     ram2gs_lcmxo256c_impl1_map.ncd
+Preference file: ram2gs_lcmxo256c_impl1.prf
+Device,speed:    LCMXO256C,3
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • PERIOD NET "PHI2_c" 350.000000 ns  (0 errors)
    •             113 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCCAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCRAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "RCLK_c" 16.000000 ns  (0 errors)
    •             395 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            113 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 161.862ns (weighted slack = 323.724ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdSubmitted_384  (to PHI2_c -)
+
+   Delay:              12.873ns  (21.6% logic, 78.4% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.873ns physical path delay SLICE_95 to SLICE_19 meets
+    175.000ns delay constraint less
+      0.265ns CE_SET requirement (totaling 174.735ns) by 161.862ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_95.CLK to    SLICE_95.Q1 SLICE_95 (from PHI2_c)
+ROUTE         1   e 1.441    SLICE_95.Q1 to    SLICE_67.A1 Bank_7
+CTOF_DEL    ---     0.371    SLICE_67.A1 to    SLICE_67.F1 SLICE_67
+ROUTE         1   e 1.441    SLICE_67.F1 to    SLICE_82.C1 n2154
+CTOF_DEL    ---     0.371    SLICE_82.C1 to    SLICE_82.F1 SLICE_82
+ROUTE         1   e 1.441    SLICE_82.F1 to    SLICE_76.B1 n26
+CTOF_DEL    ---     0.371    SLICE_76.B1 to    SLICE_76.F1 SLICE_76
+ROUTE         4   e 1.441    SLICE_76.F1 to    SLICE_89.B0 n1285
+CTOF_DEL    ---     0.371    SLICE_89.B0 to    SLICE_89.F0 SLICE_89
+ROUTE         3   e 1.441    SLICE_89.F0 to    SLICE_18.D1 n2290
+CTOF_DEL    ---     0.371    SLICE_18.D1 to    SLICE_18.F1 SLICE_18
+ROUTE         3   e 1.441    SLICE_18.F1 to    SLICE_90.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371    SLICE_90.C0 to    SLICE_90.F0 SLICE_90
+ROUTE         2   e 1.441    SLICE_90.F0 to    SLICE_19.CE PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                   12.873   (21.6% logic, 78.4% route), 7 logic levels.
+
+Report:   26.276ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 348.000ns
+         The internal maximum frequency of the following component is 500.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    FSLICE     CLK            SLICE_76
+
+   Delay:               2.000ns -- based on Minimum Pulse Width
+
+Report:    2.000ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 348.000ns
+         The internal maximum frequency of the following component is 500.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    FSLICE     CLK            SLICE_77
+
+   Delay:               2.000ns -- based on Minimum Pulse Width
+
+Report:    2.000ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            395 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 5.575ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i14  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_391  (to RCLK_c +)
+
+   Delay:              10.181ns  (23.7% logic, 76.3% route), 6 logic levels.
+
+ Constraint Details:
+
+     10.181ns physical path delay SLICE_7 to SLICE_56 meets
+     16.000ns delay constraint less
+      0.244ns CE_SET requirement (totaling 15.756ns) by 5.575ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560    SLICE_7.CLK to     SLICE_7.Q0 SLICE_7 (from RCLK_c)
+ROUTE         3   e 1.441     SLICE_7.Q0 to    SLICE_78.A0 FS_14
+CTOF_DEL    ---     0.371    SLICE_78.A0 to    SLICE_78.F0 SLICE_78
+ROUTE         3   e 1.441    SLICE_78.F0 to    SLICE_73.B1 n10
+CTOF_DEL    ---     0.371    SLICE_73.B1 to    SLICE_73.F1 SLICE_73
+ROUTE         4   e 0.561    SLICE_73.F1 to    SLICE_73.B0 n2300
+CTOF_DEL    ---     0.371    SLICE_73.B0 to    SLICE_73.F0 SLICE_73
+ROUTE         1   e 1.441    SLICE_73.F0 to    SLICE_75.C0 n11
+CTOF_DEL    ---     0.371    SLICE_75.C0 to    SLICE_75.F0 SLICE_75
+ROUTE         2   e 1.441    SLICE_75.F0 to    SLICE_33.D1 n2119
+CTOF_DEL    ---     0.371    SLICE_33.D1 to    SLICE_33.F1 SLICE_33
+ROUTE         1   e 1.441    SLICE_33.F1 to    SLICE_56.CE RCLK_c_enable_7 (to RCLK_c)
+                  --------
+                   10.181   (23.7% logic, 76.3% route), 6 logic levels.
+
+Report:   10.425ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_373  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_55 and
+      5.637ns delay SLICE_55 to RA[10] (totaling 8.141ns) meets
+     12.500ns offset RCLK to RA[10] by 4.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_55.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_55 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_55.CLK to    SLICE_55.Q0 SLICE_55 (from RCLK_c)
+ROUTE         1   e 1.441    SLICE_55.Q0 to       87.PADDO n980
+DOPAD_DEL   ---     3.636       87.PADDO to         87.PAD RA[10]
+                  --------
+                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    8.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[9] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[9] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_88.C1 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_88.C1 to    SLICE_88.F1 SLICE_88
+ROUTE         1   e 1.441    SLICE_88.F1 to       85.PADDO RA_c_9
+DOPAD_DEL   ---     3.636       85.PADDO to         85.PAD RA[9]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[8] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[8] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_95.C0 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_95.C0 to    SLICE_95.F0 SLICE_95
+ROUTE         1   e 1.441    SLICE_95.F0 to       96.PADDO RA_c_8
+DOPAD_DEL   ---     3.636       96.PADDO to         96.PAD RA[8]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[7] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[7] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_97.C0 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_97.C0 to    SLICE_97.F0 SLICE_97
+ROUTE         1   e 1.441    SLICE_97.F0 to      100.PADDO RA_c_7
+DOPAD_DEL   ---     3.636      100.PADDO to        100.PAD RA[7]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[6] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[6] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_98.C0 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_98.C0 to    SLICE_98.F0 SLICE_98
+ROUTE         1   e 1.441    SLICE_98.F0 to       91.PADDO RA_c_6
+DOPAD_DEL   ---     3.636       91.PADDO to         91.PAD RA[6]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[5] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[5] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_98.C1 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_98.C1 to    SLICE_98.F1 SLICE_98
+ROUTE         1   e 1.441    SLICE_98.F1 to       95.PADDO RA_c_5
+DOPAD_DEL   ---     3.636       95.PADDO to         95.PAD RA[5]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.427ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     6.569ns  (69.5% logic, 30.5% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      6.569ns delay SLICE_64 to RA[4] (totaling 9.073ns) meets
+     12.500ns offset RCLK to RA[4] by 3.427ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.561    SLICE_64.Q0 to    SLICE_64.C1 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_64.C1 to    SLICE_64.F1 SLICE_64
+ROUTE         1   e 1.441    SLICE_64.F1 to       99.PADDO RA_c_4
+DOPAD_DEL   ---     3.636       99.PADDO to         99.PAD RA[4]
+                  --------
+                    6.569   (69.5% logic, 30.5% route), 3 logic levels.
+
+Report:    9.073ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[3] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[3] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_94.C1 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_94.C1 to    SLICE_94.F1 SLICE_94
+ROUTE         1   e 1.441    SLICE_94.F1 to       97.PADDO RA_c_3
+DOPAD_DEL   ---     3.636       97.PADDO to         97.PAD RA[3]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[2] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[2] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_95.C1 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_95.C1 to    SLICE_95.F1 SLICE_95
+ROUTE         1   e 1.441    SLICE_95.F1 to       94.PADDO RA_c_2
+DOPAD_DEL   ---     3.636       94.PADDO to         94.PAD RA[2]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[1] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[1] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_94.C0 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_94.C0 to    SLICE_94.F0 SLICE_94
+ROUTE         1   e 1.441    SLICE_94.F0 to       89.PADDO RA_c_1
+DOPAD_DEL   ---     3.636       89.PADDO to         89.PAD RA[1]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[0] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[0] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_92.C1 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_92.C1 to    SLICE_92.F1 SLICE_92
+ROUTE         1   e 1.441    SLICE_92.F1 to       98.PADDO RA_c_0
+DOPAD_DEL   ---     3.636       98.PADDO to         98.PAD RA[0]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_369  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_60 and
+      5.637ns delay SLICE_60 to nRCS (totaling 8.141ns) meets
+     12.500ns offset RCLK to nRCS by 4.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_60.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_60 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_60.CLK to    SLICE_60.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1   e 1.441    SLICE_60.Q0 to       77.PADDO nRCS_c
+DOPAD_DEL   ---     3.636       77.PADDO to         77.PAD nRCS
+                  --------
+                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    8.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_368  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_34 and
+      5.637ns delay SLICE_34 to RCKE (totaling 8.141ns) meets
+     12.500ns offset RCLK to RCKE by 4.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_34.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_34 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_34.CLK to    SLICE_34.Q0 SLICE_34 (from RCLK_c)
+ROUTE         4   e 1.441    SLICE_34.Q0 to       82.PADDO RCKE_c
+DOPAD_DEL   ---     3.636       82.PADDO to         82.PAD RCKE
+                  --------
+                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    8.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_372  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_63 and
+      5.637ns delay SLICE_63 to nRWE (totaling 8.141ns) meets
+     12.500ns offset RCLK to nRWE by 4.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_63 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE         1   e 1.441    SLICE_63.Q0 to       72.PADDO nRWE_c
+DOPAD_DEL   ---     3.636       72.PADDO to         72.PAD nRWE
+                  --------
+                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    8.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_61 and
+      5.637ns delay SLICE_61 to nRRAS (totaling 8.141ns) meets
+     12.500ns offset RCLK to nRRAS by 4.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_61.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_61 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_61.CLK to    SLICE_61.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2   e 1.441    SLICE_61.Q0 to       73.PADDO nRRAS_c
+DOPAD_DEL   ---     3.636       73.PADDO to         73.PAD nRRAS
+                  --------
+                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    8.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_371  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_58 and
+      5.637ns delay SLICE_58 to nRCAS (totaling 8.141ns) meets
+     12.500ns offset RCLK to nRCAS by 4.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_58.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_58 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_58.CLK to    SLICE_58.Q0 SLICE_58 (from RCLK_c)
+ROUTE         1   e 1.441    SLICE_58.Q0 to       78.PADDO nRCAS_c
+DOPAD_DEL   ---     3.636       78.PADDO to         78.PAD nRCAS
+                  --------
+                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    8.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RDQMH (totaling 9.953ns) meets
+     12.500ns offset RCLK to RDQMH by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_88.B0 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_88.B0 to    SLICE_88.F0 SLICE_88
+ROUTE         1   e 1.441    SLICE_88.F0 to       76.PADDO RDQMH_c
+DOPAD_DEL   ---     3.636       76.PADDO to         76.PAD RDQMH
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RDQML (totaling 9.953ns) meets
+     12.500ns offset RCLK to RDQML by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_92.B0 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_92.B0 to    SLICE_92.F0 SLICE_92
+ROUTE         1   e 1.441    SLICE_92.F0 to       61.PADDO RDQML_c
+DOPAD_DEL   ---     3.636       61.PADDO to         61.PAD RDQML
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |   350.000 ns|    26.276 ns|   7  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |    16.000 ns|    10.425 ns|   6  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.073 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 526 paths, 6 nets, and 420 connections (67.96% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
+Mon Aug 16 21:32:27 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf 
+Design file:     ram2gs_lcmxo256c_impl1_map.ncd
+Preference file: ram2gs_lcmxo256c_impl1.prf
+Device,speed:    LCMXO256C,M
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • PERIOD NET "PHI2_c" 350.000000 ns  (0 errors)
    •             113 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCCAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCRAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "RCLK_c" 16.000000 ns  (0 errors)
    •             395 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            113 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.485ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_380  (from PHI2_c -)
+   Destination:    FF         Data in        ADSubmitted_380  (to PHI2_c -)
+
+   Delay:               0.462ns  (56.7% logic, 43.3% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.462ns physical path delay SLICE_9 to SLICE_9 meets
+     -0.023ns DIN_HLD and
+      0.000ns delay constraint requirement (totaling -0.023ns) by 0.485ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170    SLICE_9.CLK to     SLICE_9.Q0 SLICE_9 (from PHI2_c)
+ROUTE         2   e 0.199     SLICE_9.Q0 to     SLICE_9.C0 ADSubmitted
+CTOF_DEL    ---     0.092     SLICE_9.C0 to     SLICE_9.F0 SLICE_9
+ROUTE         1   e 0.001     SLICE_9.F0 to    SLICE_9.DI0 n1361 (to PHI2_c)
+                  --------
+                    0.462   (56.7% logic, 43.3% route), 2 logic levels.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            395 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.377ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i11  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i12  (to RCLK_c +)
+
+   Delay:               0.356ns  (44.1% logic, 55.9% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.356ns physical path delay SLICE_72 to SLICE_72 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint requirement (totaling -0.021ns) by 0.377ns
+
+ Physical Path Details:
+
+      Data path SLICE_72 to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_72.CLK to    SLICE_72.Q0 SLICE_72 (from RCLK_c)
+ROUTE         1   e 0.199    SLICE_72.Q0 to    SLICE_72.M1 n702 (to RCLK_c)
+                  --------
+                    0.356   (44.1% logic, 55.9% route), 1 logic levels.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_373  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_55 and
+      1.780ns delay SLICE_55 to RA[10] (totaling 2.559ns) meets
+      0.000ns hold offset RCLK to RA[10] by 2.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_55.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_55 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_55.CLK to    SLICE_55.Q0 SLICE_55 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_55.Q0 to       87.PADDO n980
+DOPAD_DEL   ---     1.108       87.PADDO to         87.PAD RA[10]
+                  --------
+                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
+
+Report:    2.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[9] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[9] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_88.C1 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_88.C1 to    SLICE_88.F1 SLICE_88
+ROUTE         1   e 0.515    SLICE_88.F1 to       85.PADDO RA_c_9
+DOPAD_DEL   ---     1.108       85.PADDO to         85.PAD RA[9]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[8] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[8] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_95.C0 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_95.C0 to    SLICE_95.F0 SLICE_95
+ROUTE         1   e 0.515    SLICE_95.F0 to       96.PADDO RA_c_8
+DOPAD_DEL   ---     1.108       96.PADDO to         96.PAD RA[8]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[7] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[7] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_97.C0 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_97.C0 to    SLICE_97.F0 SLICE_97
+ROUTE         1   e 0.515    SLICE_97.F0 to      100.PADDO RA_c_7
+DOPAD_DEL   ---     1.108      100.PADDO to        100.PAD RA[7]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[6] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[6] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_98.C0 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_98.C0 to    SLICE_98.F0 SLICE_98
+ROUTE         1   e 0.515    SLICE_98.F0 to       91.PADDO RA_c_6
+DOPAD_DEL   ---     1.108       91.PADDO to         91.PAD RA[6]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[5] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[5] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_98.C1 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_98.C1 to    SLICE_98.F1 SLICE_98
+ROUTE         1   e 0.515    SLICE_98.F1 to       95.PADDO RA_c_5
+DOPAD_DEL   ---     1.108       95.PADDO to         95.PAD RA[5]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.850ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     2.071ns  (65.5% logic, 34.5% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.071ns delay SLICE_64 to RA[4] (totaling 2.850ns) meets
+      0.000ns hold offset RCLK to RA[4] by 2.850ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.199    SLICE_64.Q0 to    SLICE_64.C1 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_64.C1 to    SLICE_64.F1 SLICE_64
+ROUTE         1   e 0.515    SLICE_64.F1 to       99.PADDO RA_c_4
+DOPAD_DEL   ---     1.108       99.PADDO to         99.PAD RA[4]
+                  --------
+                    2.071   (65.5% logic, 34.5% route), 3 logic levels.
+
+Report:    2.850ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[3] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[3] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_94.C1 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_94.C1 to    SLICE_94.F1 SLICE_94
+ROUTE         1   e 0.515    SLICE_94.F1 to       97.PADDO RA_c_3
+DOPAD_DEL   ---     1.108       97.PADDO to         97.PAD RA[3]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[2] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[2] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_95.C1 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_95.C1 to    SLICE_95.F1 SLICE_95
+ROUTE         1   e 0.515    SLICE_95.F1 to       94.PADDO RA_c_2
+DOPAD_DEL   ---     1.108       94.PADDO to         94.PAD RA[2]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[1] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[1] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_94.C0 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_94.C0 to    SLICE_94.F0 SLICE_94
+ROUTE         1   e 0.515    SLICE_94.F0 to       89.PADDO RA_c_1
+DOPAD_DEL   ---     1.108       89.PADDO to         89.PAD RA[1]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[0] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[0] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_92.C1 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_92.C1 to    SLICE_92.F1 SLICE_92
+ROUTE         1   e 0.515    SLICE_92.F1 to       98.PADDO RA_c_0
+DOPAD_DEL   ---     1.108       98.PADDO to         98.PAD RA[0]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_369  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_60 and
+      1.780ns delay SLICE_60 to nRCS (totaling 2.559ns) meets
+      0.000ns hold offset RCLK to nRCS by 2.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_60.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_60 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_60.CLK to    SLICE_60.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_60.Q0 to       77.PADDO nRCS_c
+DOPAD_DEL   ---     1.108       77.PADDO to         77.PAD nRCS
+                  --------
+                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
+
+Report:    2.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_368  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_34 and
+      1.780ns delay SLICE_34 to RCKE (totaling 2.559ns) meets
+      0.000ns hold offset RCLK to RCKE by 2.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_34.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_34 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_34.CLK to    SLICE_34.Q0 SLICE_34 (from RCLK_c)
+ROUTE         4   e 0.515    SLICE_34.Q0 to       82.PADDO RCKE_c
+DOPAD_DEL   ---     1.108       82.PADDO to         82.PAD RCKE
+                  --------
+                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
+
+Report:    2.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_372  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_63 and
+      1.780ns delay SLICE_63 to nRWE (totaling 2.559ns) meets
+      0.000ns hold offset RCLK to nRWE by 2.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_63 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_63.Q0 to       72.PADDO nRWE_c
+DOPAD_DEL   ---     1.108       72.PADDO to         72.PAD nRWE
+                  --------
+                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
+
+Report:    2.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_61 and
+      1.780ns delay SLICE_61 to nRRAS (totaling 2.559ns) meets
+      0.000ns hold offset RCLK to nRRAS by 2.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_61.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_61 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_61.CLK to    SLICE_61.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2   e 0.515    SLICE_61.Q0 to       73.PADDO nRRAS_c
+DOPAD_DEL   ---     1.108       73.PADDO to         73.PAD nRRAS
+                  --------
+                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
+
+Report:    2.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_371  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_58 and
+      1.780ns delay SLICE_58 to nRCAS (totaling 2.559ns) meets
+      0.000ns hold offset RCLK to nRCAS by 2.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_58.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_58 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_58.CLK to    SLICE_58.Q0 SLICE_58 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_58.Q0 to       78.PADDO nRCAS_c
+DOPAD_DEL   ---     1.108       78.PADDO to         78.PAD nRCAS
+                  --------
+                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
+
+Report:    2.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RDQMH (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RDQMH by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_88.B0 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_88.B0 to    SLICE_88.F0 SLICE_88
+ROUTE         1   e 0.515    SLICE_88.F0 to       76.PADDO RDQMH_c
+DOPAD_DEL   ---     1.108       76.PADDO to         76.PAD RDQMH
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RDQML (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RDQML by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_92.B0 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_92.B0 to    SLICE_92.F0 SLICE_92
+ROUTE         1   e 0.515    SLICE_92.F0 to       61.PADDO RDQML_c
+DOPAD_DEL   ---     1.108       61.PADDO to         61.PAD RDQML
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |            -|            -|   2  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |            -|            -|   1  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.850 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 526 paths, 6 nets, and 420 connections (67.96% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 0 (setup), 0 (hold)
+Score: 0 (setup), 0 (hold)
+Cumulative negative slack: 0 (0+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
+
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    + + diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_twr.html b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_twr.html new file mode 100644 index 0000000..bdfe34c --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_twr.html @@ -0,0 +1,4588 @@ + +Lattice TRACE Report + + +
    Place & Route TRACE Report
+
+Loading design for application trce from file ram2gs_lcmxo256c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: 3
+Loading device for application trce from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
+Mon Aug 16 21:32:34 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO256C_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf 
+Design file:     ram2gs_lcmxo256c_impl1.ncd
+Preference file: ram2gs_lcmxo256c_impl1.prf
+Device,speed:    LCMXO256C,3
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • PERIOD NET "PHI2_c" 350.000000 ns  (0 errors)
    •             113 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCCAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCRAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "RCLK_c" 16.000000 ns  (0 errors)
    •             395 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            113 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 161.925ns (weighted slack = 323.850ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i0  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS_385  (to PHI2_c -)
+                   FF                        CmdUFMCLK_386
+
+   Delay:              12.810ns  (21.7% logic, 78.3% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.810ns physical path delay SLICE_94 to SLICE_83 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 161.925ns
+
+ Physical Path Details:
+
+      Data path SLICE_94 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C3B.CLK to       R2C3B.Q0 SLICE_94 (from PHI2_c)
+ROUTE         1     1.643       R2C3B.Q0 to       R5C2C.B0 Bank_0
+CTOF_DEL    ---     0.371       R5C2C.B0 to       R5C2C.F0 SLICE_82
+ROUTE         1     0.497       R5C2C.F0 to       R5C2C.C1 n2166
+CTOF_DEL    ---     0.371       R5C2C.C1 to       R5C2C.F1 SLICE_82
+ROUTE         1     1.548       R5C2C.F1 to       R5C5B.B1 n26
+CTOF_DEL    ---     0.371       R5C5B.B1 to       R5C5B.F1 SLICE_76
+ROUTE         4     1.750       R5C5B.F1 to       R6C3A.D0 n1285
+CTOF_DEL    ---     0.371       R6C3A.D0 to       R6C3A.F0 SLICE_89
+ROUTE         3     1.048       R6C3A.F0 to       R5C3C.A1 n2290
+CTOF_DEL    ---     0.371       R5C3C.A1 to       R5C3C.F1 SLICE_18
+ROUTE         3     1.504       R5C3C.F1 to       R4C4A.A0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R4C4A.A0 to       R4C4A.F0 SLICE_72
+ROUTE         2     2.034       R4C4A.F0 to       R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   12.810   (21.7% logic, 78.3% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R2C3B.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R5C4B.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.080ns (weighted slack = 324.160ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS_385  (to PHI2_c -)
+                   FF                        CmdUFMCLK_386
+
+   Delay:              12.655ns  (22.0% logic, 78.0% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.655ns physical path delay SLICE_95 to SLICE_83 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 162.080ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2C.CLK to       R2C2C.Q0 SLICE_95 (from PHI2_c)
+ROUTE         1     1.488       R2C2C.Q0 to       R5C2C.A0 Bank_6
+CTOF_DEL    ---     0.371       R5C2C.A0 to       R5C2C.F0 SLICE_82
+ROUTE         1     0.497       R5C2C.F0 to       R5C2C.C1 n2166
+CTOF_DEL    ---     0.371       R5C2C.C1 to       R5C2C.F1 SLICE_82
+ROUTE         1     1.548       R5C2C.F1 to       R5C5B.B1 n26
+CTOF_DEL    ---     0.371       R5C5B.B1 to       R5C5B.F1 SLICE_76
+ROUTE         4     1.750       R5C5B.F1 to       R6C3A.D0 n1285
+CTOF_DEL    ---     0.371       R6C3A.D0 to       R6C3A.F0 SLICE_89
+ROUTE         3     1.048       R6C3A.F0 to       R5C3C.A1 n2290
+CTOF_DEL    ---     0.371       R5C3C.A1 to       R5C3C.F1 SLICE_18
+ROUTE         3     1.504       R5C3C.F1 to       R4C4A.A0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R4C4A.A0 to       R4C4A.F0 SLICE_72
+ROUTE         2     2.034       R4C4A.F0 to       R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   12.655   (22.0% logic, 78.0% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R2C2C.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R5C4B.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.409ns (weighted slack = 324.818ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i0  (from PHI2_c +)
+   Destination:    FF         Data in        CmdSubmitted_384  (to PHI2_c -)
+
+   Delay:              12.326ns  (22.6% logic, 77.4% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.326ns physical path delay SLICE_94 to SLICE_19 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 162.409ns
+
+ Physical Path Details:
+
+      Data path SLICE_94 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C3B.CLK to       R2C3B.Q0 SLICE_94 (from PHI2_c)
+ROUTE         1     1.643       R2C3B.Q0 to       R5C2C.B0 Bank_0
+CTOF_DEL    ---     0.371       R5C2C.B0 to       R5C2C.F0 SLICE_82
+ROUTE         1     0.497       R5C2C.F0 to       R5C2C.C1 n2166
+CTOF_DEL    ---     0.371       R5C2C.C1 to       R5C2C.F1 SLICE_82
+ROUTE         1     1.548       R5C2C.F1 to       R5C5B.B1 n26
+CTOF_DEL    ---     0.371       R5C5B.B1 to       R5C5B.F1 SLICE_76
+ROUTE         4     1.750       R5C5B.F1 to       R6C3A.D0 n1285
+CTOF_DEL    ---     0.371       R6C3A.D0 to       R6C3A.F0 SLICE_89
+ROUTE         3     1.048       R6C3A.F0 to       R5C3C.A1 n2290
+CTOF_DEL    ---     0.371       R5C3C.A1 to       R5C3C.F1 SLICE_18
+ROUTE         3     1.504       R5C3C.F1 to       R4C4D.A0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R4C4D.A0 to       R4C4D.F0 SLICE_90
+ROUTE         2     1.550       R4C4D.F0 to       R5C5A.CE PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                   12.326   (22.6% logic, 77.4% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R2C3B.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R5C5A.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.416ns (weighted slack = 324.832ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i0  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMSDI_387  (to PHI2_c -)
+
+   Delay:              12.319ns  (22.6% logic, 77.4% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.319ns physical path delay SLICE_94 to SLICE_88 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 162.416ns
+
+ Physical Path Details:
+
+      Data path SLICE_94 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C3B.CLK to       R2C3B.Q0 SLICE_94 (from PHI2_c)
+ROUTE         1     1.643       R2C3B.Q0 to       R5C2C.B0 Bank_0
+CTOF_DEL    ---     0.371       R5C2C.B0 to       R5C2C.F0 SLICE_82
+ROUTE         1     0.497       R5C2C.F0 to       R5C2C.C1 n2166
+CTOF_DEL    ---     0.371       R5C2C.C1 to       R5C2C.F1 SLICE_82
+ROUTE         1     1.548       R5C2C.F1 to       R5C5B.B1 n26
+CTOF_DEL    ---     0.371       R5C5B.B1 to       R5C5B.F1 SLICE_76
+ROUTE         4     1.750       R5C5B.F1 to       R6C3A.D0 n1285
+CTOF_DEL    ---     0.371       R6C3A.D0 to       R6C3A.F0 SLICE_89
+ROUTE         3     1.048       R6C3A.F0 to       R5C3C.A1 n2290
+CTOF_DEL    ---     0.371       R5C3C.A1 to       R5C3C.F1 SLICE_18
+ROUTE         3     1.504       R5C3C.F1 to       R4C4A.A0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R4C4A.A0 to       R4C4A.F0 SLICE_72
+ROUTE         2     1.543       R4C4A.F0 to       R2C4A.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   12.319   (22.6% logic, 77.4% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R2C3B.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R2C4A.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.564ns (weighted slack = 325.128ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        CmdSubmitted_384  (to PHI2_c -)
+
+   Delay:              12.171ns  (22.9% logic, 77.1% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.171ns physical path delay SLICE_95 to SLICE_19 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 162.564ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2C.CLK to       R2C2C.Q0 SLICE_95 (from PHI2_c)
+ROUTE         1     1.488       R2C2C.Q0 to       R5C2C.A0 Bank_6
+CTOF_DEL    ---     0.371       R5C2C.A0 to       R5C2C.F0 SLICE_82
+ROUTE         1     0.497       R5C2C.F0 to       R5C2C.C1 n2166
+CTOF_DEL    ---     0.371       R5C2C.C1 to       R5C2C.F1 SLICE_82
+ROUTE         1     1.548       R5C2C.F1 to       R5C5B.B1 n26
+CTOF_DEL    ---     0.371       R5C5B.B1 to       R5C5B.F1 SLICE_76
+ROUTE         4     1.750       R5C5B.F1 to       R6C3A.D0 n1285
+CTOF_DEL    ---     0.371       R6C3A.D0 to       R6C3A.F0 SLICE_89
+ROUTE         3     1.048       R6C3A.F0 to       R5C3C.A1 n2290
+CTOF_DEL    ---     0.371       R5C3C.A1 to       R5C3C.F1 SLICE_18
+ROUTE         3     1.504       R5C3C.F1 to       R4C4D.A0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R4C4D.A0 to       R4C4D.F0 SLICE_90
+ROUTE         2     1.550       R4C4D.F0 to       R5C5A.CE PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                   12.171   (22.9% logic, 77.1% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R2C2C.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R5C5A.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.571ns (weighted slack = 325.142ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMSDI_387  (to PHI2_c -)
+
+   Delay:              12.164ns  (22.9% logic, 77.1% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.164ns physical path delay SLICE_95 to SLICE_88 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 162.571ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2C.CLK to       R2C2C.Q0 SLICE_95 (from PHI2_c)
+ROUTE         1     1.488       R2C2C.Q0 to       R5C2C.A0 Bank_6
+CTOF_DEL    ---     0.371       R5C2C.A0 to       R5C2C.F0 SLICE_82
+ROUTE         1     0.497       R5C2C.F0 to       R5C2C.C1 n2166
+CTOF_DEL    ---     0.371       R5C2C.C1 to       R5C2C.F1 SLICE_82
+ROUTE         1     1.548       R5C2C.F1 to       R5C5B.B1 n26
+CTOF_DEL    ---     0.371       R5C5B.B1 to       R5C5B.F1 SLICE_76
+ROUTE         4     1.750       R5C5B.F1 to       R6C3A.D0 n1285
+CTOF_DEL    ---     0.371       R6C3A.D0 to       R6C3A.F0 SLICE_89
+ROUTE         3     1.048       R6C3A.F0 to       R5C3C.A1 n2290
+CTOF_DEL    ---     0.371       R5C3C.A1 to       R5C3C.F1 SLICE_18
+ROUTE         3     1.504       R5C3C.F1 to       R4C4A.A0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R4C4A.A0 to       R4C4A.F0 SLICE_72
+ROUTE         2     1.543       R4C4A.F0 to       R2C4A.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   12.164   (22.9% logic, 77.1% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R2C2C.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R2C4A.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.606ns (weighted slack = 325.212ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS_385  (to PHI2_c -)
+                   FF                        CmdUFMCLK_386
+
+   Delay:              12.129ns  (23.0% logic, 77.0% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.129ns physical path delay SLICE_95 to SLICE_83 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 162.606ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2C.CLK to       R2C2C.Q1 SLICE_95 (from PHI2_c)
+ROUTE         1     1.155       R2C2C.Q1 to       R5C2B.D1 Bank_7
+CTOF_DEL    ---     0.371       R5C2B.D1 to       R5C2B.F1 SLICE_67
+ROUTE         1     0.304       R5C2B.F1 to       R5C2C.D1 n2154
+CTOF_DEL    ---     0.371       R5C2C.D1 to       R5C2C.F1 SLICE_82
+ROUTE         1     1.548       R5C2C.F1 to       R5C5B.B1 n26
+CTOF_DEL    ---     0.371       R5C5B.B1 to       R5C5B.F1 SLICE_76
+ROUTE         4     1.750       R5C5B.F1 to       R6C3A.D0 n1285
+CTOF_DEL    ---     0.371       R6C3A.D0 to       R6C3A.F0 SLICE_89
+ROUTE         3     1.048       R6C3A.F0 to       R5C3C.A1 n2290
+CTOF_DEL    ---     0.371       R5C3C.A1 to       R5C3C.F1 SLICE_18
+ROUTE         3     1.504       R5C3C.F1 to       R4C4A.A0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R4C4A.A0 to       R4C4A.F0 SLICE_72
+ROUTE         2     2.034       R4C4A.F0 to       R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   12.129   (23.0% logic, 77.0% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R2C2C.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R5C4B.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.635ns (weighted slack = 325.270ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i1  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS_385  (to PHI2_c -)
+                   FF                        CmdUFMCLK_386
+
+   Delay:              12.100ns  (20.0% logic, 80.0% route), 6 logic levels.
+
+ Constraint Details:
+
+     12.100ns physical path delay SLICE_94 to SLICE_83 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 162.635ns
+
+ Physical Path Details:
+
+      Data path SLICE_94 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C3B.CLK to       R2C3B.Q1 SLICE_94 (from PHI2_c)
+ROUTE         1     1.905       R2C3B.Q1 to       R6C2B.C1 Bank_1
+CTOF_DEL    ---     0.371       R6C2B.C1 to       R6C2B.F1 SLICE_97
+ROUTE         1     1.444       R6C2B.F1 to       R5C5B.C1 n2170
+CTOF_DEL    ---     0.371       R5C5B.C1 to       R5C5B.F1 SLICE_76
+ROUTE         4     1.750       R5C5B.F1 to       R6C3A.D0 n1285
+CTOF_DEL    ---     0.371       R6C3A.D0 to       R6C3A.F0 SLICE_89
+ROUTE         3     1.048       R6C3A.F0 to       R5C3C.A1 n2290
+CTOF_DEL    ---     0.371       R5C3C.A1 to       R5C3C.F1 SLICE_18
+ROUTE         3     1.504       R5C3C.F1 to       R4C4A.A0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R4C4A.A0 to       R4C4A.F0 SLICE_72
+ROUTE         2     2.034       R4C4A.F0 to       R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   12.100   (20.0% logic, 80.0% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R2C3B.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R5C4B.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.868ns (weighted slack = 325.736ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i5  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS_385  (to PHI2_c -)
+                   FF                        CmdUFMCLK_386
+
+   Delay:              11.867ns  (23.5% logic, 76.5% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.867ns physical path delay SLICE_97 to SLICE_83 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 162.868ns
+
+ Physical Path Details:
+
+      Data path SLICE_97 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R6C2B.CLK to       R6C2B.Q1 SLICE_97 (from PHI2_c)
+ROUTE         1     0.700       R6C2B.Q1 to       R5C2C.D0 Bank_5
+CTOF_DEL    ---     0.371       R5C2C.D0 to       R5C2C.F0 SLICE_82
+ROUTE         1     0.497       R5C2C.F0 to       R5C2C.C1 n2166
+CTOF_DEL    ---     0.371       R5C2C.C1 to       R5C2C.F1 SLICE_82
+ROUTE         1     1.548       R5C2C.F1 to       R5C5B.B1 n26
+CTOF_DEL    ---     0.371       R5C5B.B1 to       R5C5B.F1 SLICE_76
+ROUTE         4     1.750       R5C5B.F1 to       R6C3A.D0 n1285
+CTOF_DEL    ---     0.371       R6C3A.D0 to       R6C3A.F0 SLICE_89
+ROUTE         3     1.048       R6C3A.F0 to       R5C3C.A1 n2290
+CTOF_DEL    ---     0.371       R5C3C.A1 to       R5C3C.F1 SLICE_18
+ROUTE         3     1.504       R5C3C.F1 to       R4C4A.A0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R4C4A.A0 to       R4C4A.F0 SLICE_72
+ROUTE         2     2.034       R4C4A.F0 to       R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   11.867   (23.5% logic, 76.5% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_97:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R6C2B.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R5C4B.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.886ns (weighted slack = 325.772ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i0  (from PHI2_c +)
+   Destination:    FF         Data in        XOR8MEG_381  (to PHI2_c -)
+
+   Delay:              11.849ns  (23.5% logic, 76.5% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.849ns physical path delay SLICE_94 to SLICE_96 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 162.886ns
+
+ Physical Path Details:
+
+      Data path SLICE_94 to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C3B.CLK to       R2C3B.Q0 SLICE_94 (from PHI2_c)
+ROUTE         1     1.643       R2C3B.Q0 to       R5C2C.B0 Bank_0
+CTOF_DEL    ---     0.371       R5C2C.B0 to       R5C2C.F0 SLICE_82
+ROUTE         1     0.497       R5C2C.F0 to       R5C2C.C1 n2166
+CTOF_DEL    ---     0.371       R5C2C.C1 to       R5C2C.F1 SLICE_82
+ROUTE         1     1.548       R5C2C.F1 to       R5C5B.B1 n26
+CTOF_DEL    ---     0.371       R5C5B.B1 to       R5C5B.F1 SLICE_76
+ROUTE         4     1.750       R5C5B.F1 to       R6C3A.D0 n1285
+CTOF_DEL    ---     0.371       R6C3A.D0 to       R6C3A.F0 SLICE_89
+ROUTE         3     1.048       R6C3A.F0 to       R5C3C.A1 n2290
+CTOF_DEL    ---     0.371       R5C3C.A1 to       R5C3C.F1 SLICE_18
+ROUTE         3     1.504       R5C3C.F1 to       R4C4D.A1 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R4C4D.A1 to       R4C4D.F1 SLICE_90
+ROUTE         1     1.073       R4C4D.F1 to       R3C4B.CE PHI2_N_114_enable_2 (to PHI2_c)
+                  --------
+                   11.849   (23.5% logic, 76.5% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R2C3B.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R3C4B.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:   26.150ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 348.000ns
+         The internal maximum frequency of the following component is 500.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    FSLICE     CLK            SLICE_76
+
+   Delay:               2.000ns -- based on Minimum Pulse Width
+
+Report:    2.000ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 348.000ns
+         The internal maximum frequency of the following component is 500.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    FSLICE     CLK            SLICE_77
+
+   Delay:               2.000ns -- based on Minimum Pulse Width
+
+Report:    2.000ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            395 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 7.566ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i15  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_392  (to RCLK_c +)
+
+   Delay:               8.190ns  (29.5% logic, 70.5% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.190ns physical path delay SLICE_7 to SLICE_89 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 7.566ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C4D.CLK to       R8C4D.Q1 SLICE_7 (from RCLK_c)
+ROUTE         3     1.929       R8C4D.Q1 to       R7C5C.B0 FS_15
+CTOF_DEL    ---     0.371       R7C5C.B0 to       R7C5C.F0 SLICE_78
+ROUTE         3     1.057       R7C5C.F0 to       R7C4A.A1 n10
+CTOF_DEL    ---     0.371       R7C4A.A1 to       R7C4A.F1 SLICE_73
+ROUTE         4     0.712       R7C4A.F1 to       R7C4A.B0 n2300
+CTOF_DEL    ---     0.371       R7C4A.B0 to       R7C4A.F0 SLICE_73
+ROUTE         1     0.304       R7C4A.F0 to       R7C4B.D0 n11
+CTOF_DEL    ---     0.371       R7C4B.D0 to       R7C4B.F0 SLICE_75
+ROUTE         2     0.513       R7C4B.F0 to       R7C4B.C1 n2119
+CTOF_DEL    ---     0.371       R7C4B.C1 to       R7C4B.F1 SLICE_75
+ROUTE         1     1.260       R7C4B.F1 to       R6C3A.CE RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    8.190   (29.5% logic, 70.5% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R8C4D.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R6C3A.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.590ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i15  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_391  (to RCLK_c +)
+
+   Delay:               8.166ns  (29.6% logic, 70.4% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.166ns physical path delay SLICE_7 to SLICE_56 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 7.590ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C4D.CLK to       R8C4D.Q1 SLICE_7 (from RCLK_c)
+ROUTE         3     1.929       R8C4D.Q1 to       R7C5C.B0 FS_15
+CTOF_DEL    ---     0.371       R7C5C.B0 to       R7C5C.F0 SLICE_78
+ROUTE         3     1.057       R7C5C.F0 to       R7C4A.A1 n10
+CTOF_DEL    ---     0.371       R7C4A.A1 to       R7C4A.F1 SLICE_73
+ROUTE         4     0.712       R7C4A.F1 to       R7C4A.B0 n2300
+CTOF_DEL    ---     0.371       R7C4A.B0 to       R7C4A.F0 SLICE_73
+ROUTE         1     0.304       R7C4A.F0 to       R7C4B.D0 n11
+CTOF_DEL    ---     0.371       R7C4B.D0 to       R7C4B.F0 SLICE_75
+ROUTE         2     1.102       R7C4B.F0 to       R6C4C.B1 n2119
+CTOF_DEL    ---     0.371       R6C4C.B1 to       R6C4C.F1 SLICE_33
+ROUTE         1     0.647       R6C4C.F1 to       R6C4B.CE RCLK_c_enable_7 (to RCLK_c)
+                  --------
+                    8.166   (29.6% logic, 70.4% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R8C4D.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R6C4B.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.984ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i13  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_392  (to RCLK_c +)
+
+   Delay:               7.772ns  (31.1% logic, 68.9% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.772ns physical path delay SLICE_8 to SLICE_89 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 7.984ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C4C.CLK to       R8C4C.Q1 SLICE_8 (from RCLK_c)
+ROUTE         3     1.511       R8C4C.Q1 to       R7C5C.A0 FS_13
+CTOF_DEL    ---     0.371       R7C5C.A0 to       R7C5C.F0 SLICE_78
+ROUTE         3     1.057       R7C5C.F0 to       R7C4A.A1 n10
+CTOF_DEL    ---     0.371       R7C4A.A1 to       R7C4A.F1 SLICE_73
+ROUTE         4     0.712       R7C4A.F1 to       R7C4A.B0 n2300
+CTOF_DEL    ---     0.371       R7C4A.B0 to       R7C4A.F0 SLICE_73
+ROUTE         1     0.304       R7C4A.F0 to       R7C4B.D0 n11
+CTOF_DEL    ---     0.371       R7C4B.D0 to       R7C4B.F0 SLICE_75
+ROUTE         2     0.513       R7C4B.F0 to       R7C4B.C1 n2119
+CTOF_DEL    ---     0.371       R7C4B.C1 to       R7C4B.F1 SLICE_75
+ROUTE         1     1.260       R7C4B.F1 to       R6C3A.CE RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    7.772   (31.1% logic, 68.9% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R8C4C.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R6C3A.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 8.008ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i13  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_391  (to RCLK_c +)
+
+   Delay:               7.748ns  (31.2% logic, 68.8% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.748ns physical path delay SLICE_8 to SLICE_56 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 8.008ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C4C.CLK to       R8C4C.Q1 SLICE_8 (from RCLK_c)
+ROUTE         3     1.511       R8C4C.Q1 to       R7C5C.A0 FS_13
+CTOF_DEL    ---     0.371       R7C5C.A0 to       R7C5C.F0 SLICE_78
+ROUTE         3     1.057       R7C5C.F0 to       R7C4A.A1 n10
+CTOF_DEL    ---     0.371       R7C4A.A1 to       R7C4A.F1 SLICE_73
+ROUTE         4     0.712       R7C4A.F1 to       R7C4A.B0 n2300
+CTOF_DEL    ---     0.371       R7C4A.B0 to       R7C4A.F0 SLICE_73
+ROUTE         1     0.304       R7C4A.F0 to       R7C4B.D0 n11
+CTOF_DEL    ---     0.371       R7C4B.D0 to       R7C4B.F0 SLICE_75
+ROUTE         2     1.102       R7C4B.F0 to       R6C4C.B1 n2119
+CTOF_DEL    ---     0.371       R6C4C.B1 to       R6C4C.F1 SLICE_33
+ROUTE         1     0.647       R6C4C.F1 to       R6C4B.CE RCLK_c_enable_7 (to RCLK_c)
+                  --------
+                    7.748   (31.2% logic, 68.8% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R8C4C.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R6C4B.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 8.123ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i12  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_392  (to RCLK_c +)
+
+   Delay:               7.633ns  (31.6% logic, 68.4% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.633ns physical path delay SLICE_8 to SLICE_89 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 8.123ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C4C.CLK to       R8C4C.Q0 SLICE_8 (from RCLK_c)
+ROUTE         3     1.372       R8C4C.Q0 to       R7C5C.C0 FS_12
+CTOF_DEL    ---     0.371       R7C5C.C0 to       R7C5C.F0 SLICE_78
+ROUTE         3     1.057       R7C5C.F0 to       R7C4A.A1 n10
+CTOF_DEL    ---     0.371       R7C4A.A1 to       R7C4A.F1 SLICE_73
+ROUTE         4     0.712       R7C4A.F1 to       R7C4A.B0 n2300
+CTOF_DEL    ---     0.371       R7C4A.B0 to       R7C4A.F0 SLICE_73
+ROUTE         1     0.304       R7C4A.F0 to       R7C4B.D0 n11
+CTOF_DEL    ---     0.371       R7C4B.D0 to       R7C4B.F0 SLICE_75
+ROUTE         2     0.513       R7C4B.F0 to       R7C4B.C1 n2119
+CTOF_DEL    ---     0.371       R7C4B.C1 to       R7C4B.F1 SLICE_75
+ROUTE         1     1.260       R7C4B.F1 to       R6C3A.CE RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    7.633   (31.6% logic, 68.4% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R8C4C.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R6C3A.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 8.147ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i12  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_391  (to RCLK_c +)
+
+   Delay:               7.609ns  (31.7% logic, 68.3% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.609ns physical path delay SLICE_8 to SLICE_56 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 8.147ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C4C.CLK to       R8C4C.Q0 SLICE_8 (from RCLK_c)
+ROUTE         3     1.372       R8C4C.Q0 to       R7C5C.C0 FS_12
+CTOF_DEL    ---     0.371       R7C5C.C0 to       R7C5C.F0 SLICE_78
+ROUTE         3     1.057       R7C5C.F0 to       R7C4A.A1 n10
+CTOF_DEL    ---     0.371       R7C4A.A1 to       R7C4A.F1 SLICE_73
+ROUTE         4     0.712       R7C4A.F1 to       R7C4A.B0 n2300
+CTOF_DEL    ---     0.371       R7C4A.B0 to       R7C4A.F0 SLICE_73
+ROUTE         1     0.304       R7C4A.F0 to       R7C4B.D0 n11
+CTOF_DEL    ---     0.371       R7C4B.D0 to       R7C4B.F0 SLICE_75
+ROUTE         2     1.102       R7C4B.F0 to       R6C4C.B1 n2119
+CTOF_DEL    ---     0.371       R6C4C.B1 to       R6C4C.F1 SLICE_33
+ROUTE         1     0.647       R6C4C.F1 to       R6C4B.CE RCLK_c_enable_7 (to RCLK_c)
+                  --------
+                    7.609   (31.7% logic, 68.3% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R8C4C.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R6C4B.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 8.262ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i15  (from RCLK_c +)
+   Destination:    FF         Data in        UFMCLK_389  (to RCLK_c +)
+
+   Delay:               7.112ns  (23.5% logic, 76.5% route), 4 logic levels.
+
+ Constraint Details:
+
+      7.112ns physical path delay SLICE_7 to SLICE_42 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.626ns LSR_SET requirement (totaling 15.374ns) by 8.262ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_42:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C4D.CLK to       R8C4D.Q1 SLICE_7 (from RCLK_c)
+ROUTE         3     1.929       R8C4D.Q1 to       R7C5C.B0 FS_15
+CTOF_DEL    ---     0.371       R7C5C.B0 to       R7C5C.F0 SLICE_78
+ROUTE         3     1.057       R7C5C.F0 to       R7C4A.A1 n10
+CTOF_DEL    ---     0.371       R7C4A.A1 to       R7C4A.F1 SLICE_73
+ROUTE         4     0.915       R7C4A.F1 to       R6C4A.C0 n2300
+CTOF_DEL    ---     0.371       R6C4A.C0 to       R6C4A.F0 SLICE_86
+ROUTE         2     1.538       R6C4A.F0 to      R7C5A.LSR n2291 (to RCLK_c)
+                  --------
+                    7.112   (23.5% logic, 76.5% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R8C4D.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_42:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R7C5A.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 8.262ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i15  (from RCLK_c +)
+   Destination:    FF         Data in        UFMSDI_390  (to RCLK_c +)
+
+   Delay:               7.112ns  (23.5% logic, 76.5% route), 4 logic levels.
+
+ Constraint Details:
+
+      7.112ns physical path delay SLICE_7 to SLICE_43 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.626ns LSR_SET requirement (totaling 15.374ns) by 8.262ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C4D.CLK to       R8C4D.Q1 SLICE_7 (from RCLK_c)
+ROUTE         3     1.929       R8C4D.Q1 to       R7C5C.B0 FS_15
+CTOF_DEL    ---     0.371       R7C5C.B0 to       R7C5C.F0 SLICE_78
+ROUTE         3     1.057       R7C5C.F0 to       R7C4A.A1 n10
+CTOF_DEL    ---     0.371       R7C4A.A1 to       R7C4A.F1 SLICE_73
+ROUTE         4     0.915       R7C4A.F1 to       R6C4A.C0 n2300
+CTOF_DEL    ---     0.371       R6C4A.C0 to       R6C4A.F0 SLICE_86
+ROUTE         2     1.538       R6C4A.F0 to      R7C5B.LSR n2291 (to RCLK_c)
+                  --------
+                    7.112   (23.5% logic, 76.5% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R8C4D.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R7C5B.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 8.316ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i14  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_392  (to RCLK_c +)
+
+   Delay:               7.440ns  (32.5% logic, 67.5% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.440ns physical path delay SLICE_7 to SLICE_89 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 8.316ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C4D.CLK to       R8C4D.Q0 SLICE_7 (from RCLK_c)
+ROUTE         3     1.179       R8C4D.Q0 to       R7C5C.D0 FS_14
+CTOF_DEL    ---     0.371       R7C5C.D0 to       R7C5C.F0 SLICE_78
+ROUTE         3     1.057       R7C5C.F0 to       R7C4A.A1 n10
+CTOF_DEL    ---     0.371       R7C4A.A1 to       R7C4A.F1 SLICE_73
+ROUTE         4     0.712       R7C4A.F1 to       R7C4A.B0 n2300
+CTOF_DEL    ---     0.371       R7C4A.B0 to       R7C4A.F0 SLICE_73
+ROUTE         1     0.304       R7C4A.F0 to       R7C4B.D0 n11
+CTOF_DEL    ---     0.371       R7C4B.D0 to       R7C4B.F0 SLICE_75
+ROUTE         2     0.513       R7C4B.F0 to       R7C4B.C1 n2119
+CTOF_DEL    ---     0.371       R7C4B.C1 to       R7C4B.F1 SLICE_75
+ROUTE         1     1.260       R7C4B.F1 to       R6C3A.CE RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    7.440   (32.5% logic, 67.5% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R8C4D.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R6C3A.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 8.340ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i14  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_391  (to RCLK_c +)
+
+   Delay:               7.416ns  (32.6% logic, 67.4% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.416ns physical path delay SLICE_7 to SLICE_56 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 8.340ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C4D.CLK to       R8C4D.Q0 SLICE_7 (from RCLK_c)
+ROUTE         3     1.179       R8C4D.Q0 to       R7C5C.D0 FS_14
+CTOF_DEL    ---     0.371       R7C5C.D0 to       R7C5C.F0 SLICE_78
+ROUTE         3     1.057       R7C5C.F0 to       R7C4A.A1 n10
+CTOF_DEL    ---     0.371       R7C4A.A1 to       R7C4A.F1 SLICE_73
+ROUTE         4     0.712       R7C4A.F1 to       R7C4A.B0 n2300
+CTOF_DEL    ---     0.371       R7C4A.B0 to       R7C4A.F0 SLICE_73
+ROUTE         1     0.304       R7C4A.F0 to       R7C4B.D0 n11
+CTOF_DEL    ---     0.371       R7C4B.D0 to       R7C4B.F0 SLICE_75
+ROUTE         2     1.102       R7C4B.F0 to       R6C4C.B1 n2119
+CTOF_DEL    ---     0.371       R6C4C.B1 to       R6C4C.F1 SLICE_33
+ROUTE         1     0.647       R6C4C.F1 to       R6C4B.CE RCLK_c_enable_7 (to RCLK_c)
+                  --------
+                    7.416   (32.6% logic, 67.4% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R8C4D.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to      R6C4B.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:    8.434ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.904ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_373  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     6.180ns  (67.9% logic, 32.1% route), 2 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_55 and
+      6.180ns delay SLICE_55 to RA[10] (totaling 8.596ns) meets
+     12.500ns offset RCLK to RA[10] by 3.904ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to      R2C4B.CLK RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_55 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C4B.CLK to       R2C4B.Q0 SLICE_55 (from RCLK_c)
+ROUTE         1     1.984       R2C4B.Q0 to       87.PADDO n980
+DOPAD_DEL   ---     3.636       87.PADDO to         87.PAD RA[10]
+                  --------
+                    6.180   (67.9% logic, 32.1% route), 2 logic levels.
+
+Report:    8.596ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.734ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     6.350ns  (71.9% logic, 28.1% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      6.350ns delay SLICE_64 to RA[9] (totaling 8.766ns) meets
+     12.500ns offset RCLK to RA[9] by 3.734ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.966       R2C2A.Q0 to       R2C4A.C1 nRowColSel
+CTOF_DEL    ---     0.371       R2C4A.C1 to       R2C4A.F1 SLICE_88
+ROUTE         1     0.817       R2C4A.F1 to       85.PADDO RA_c_9
+DOPAD_DEL   ---     3.636       85.PADDO to         85.PAD RA[9]
+                  --------
+                    6.350   (71.9% logic, 28.1% route), 3 logic levels.
+
+Report:    8.766ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.604ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     6.480ns  (70.5% logic, 29.5% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      6.480ns delay SLICE_64 to RA[8] (totaling 8.896ns) meets
+     12.500ns offset RCLK to RA[8] by 3.604ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.096       R2C2A.Q0 to       R2C2C.B0 nRowColSel
+CTOF_DEL    ---     0.371       R2C2C.B0 to       R2C2C.F0 SLICE_95
+ROUTE         1     0.817       R2C2C.F0 to       96.PADDO RA_c_8
+DOPAD_DEL   ---     3.636       96.PADDO to         96.PAD RA[8]
+                  --------
+                    6.480   (70.5% logic, 29.5% route), 3 logic levels.
+
+Report:    8.896ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.245ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     7.839ns  (58.3% logic, 41.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      7.839ns delay SLICE_64 to RA[7] (totaling 10.255ns) meets
+     12.500ns offset RCLK to RA[7] by 2.245ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.234       R2C2A.Q0 to       R6C2B.D0 nRowColSel
+CTOF_DEL    ---     0.371       R6C2B.D0 to       R6C2B.F0 SLICE_97
+ROUTE         1     2.038       R6C2B.F0 to      100.PADDO RA_c_7
+DOPAD_DEL   ---     3.636      100.PADDO to        100.PAD RA[7]
+                  --------
+                    7.839   (58.3% logic, 41.7% route), 3 logic levels.
+
+Report:   10.255ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.499ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     7.585ns  (60.2% logic, 39.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      7.585ns delay SLICE_64 to RA[6] (totaling 10.001ns) meets
+     12.500ns offset RCLK to RA[6] by 2.499ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.966       R2C2A.Q0 to       R3C2A.C0 nRowColSel
+CTOF_DEL    ---     0.371       R3C2A.C0 to       R3C2A.F0 SLICE_98
+ROUTE         1     2.052       R3C2A.F0 to       91.PADDO RA_c_6
+DOPAD_DEL   ---     3.636       91.PADDO to         91.PAD RA[6]
+                  --------
+                    7.585   (60.2% logic, 39.8% route), 3 logic levels.
+
+Report:   10.001ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.891ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     7.193ns  (63.5% logic, 36.5% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      7.193ns delay SLICE_64 to RA[5] (totaling 9.609ns) meets
+     12.500ns offset RCLK to RA[5] by 2.891ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.966       R2C2A.Q0 to       R3C2A.C1 nRowColSel
+CTOF_DEL    ---     0.371       R3C2A.C1 to       R3C2A.F1 SLICE_98
+ROUTE         1     1.660       R3C2A.F1 to       95.PADDO RA_c_5
+DOPAD_DEL   ---     3.636       95.PADDO to         95.PAD RA[5]
+                  --------
+                    7.193   (63.5% logic, 36.5% route), 3 logic levels.
+
+Report:    9.609ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.996ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     6.088ns  (75.0% logic, 25.0% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      6.088ns delay SLICE_64 to RA[4] (totaling 8.504ns) meets
+     12.500ns offset RCLK to RA[4] by 3.996ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.704       R2C2A.Q0 to       R2C2A.D1 nRowColSel
+CTOF_DEL    ---     0.371       R2C2A.D1 to       R2C2A.F1 SLICE_64
+ROUTE         1     0.817       R2C2A.F1 to       99.PADDO RA_c_4
+DOPAD_DEL   ---     3.636       99.PADDO to         99.PAD RA[4]
+                  --------
+                    6.088   (75.0% logic, 25.0% route), 3 logic levels.
+
+Report:    8.504ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.567ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     7.517ns  (60.8% logic, 39.2% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      7.517ns delay SLICE_64 to RA[3] (totaling 9.933ns) meets
+     12.500ns offset RCLK to RA[3] by 2.567ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.966       R2C2A.Q0 to       R2C3B.C1 nRowColSel
+CTOF_DEL    ---     0.371       R2C3B.C1 to       R2C3B.F1 SLICE_94
+ROUTE         1     1.984       R2C3B.F1 to       97.PADDO RA_c_3
+DOPAD_DEL   ---     3.636       97.PADDO to         97.PAD RA[3]
+                  --------
+                    7.517   (60.8% logic, 39.2% route), 3 logic levels.
+
+Report:    9.933ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.438ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     7.646ns  (59.7% logic, 40.3% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      7.646ns delay SLICE_64 to RA[2] (totaling 10.062ns) meets
+     12.500ns offset RCLK to RA[2] by 2.438ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.096       R2C2A.Q0 to       R2C2C.B1 nRowColSel
+CTOF_DEL    ---     0.371       R2C2C.B1 to       R2C2C.F1 SLICE_95
+ROUTE         1     1.983       R2C2C.F1 to       94.PADDO RA_c_2
+DOPAD_DEL   ---     3.636       94.PADDO to         94.PAD RA[2]
+                  --------
+                    7.646   (59.7% logic, 40.3% route), 3 logic levels.
+
+Report:   10.062ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.734ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     6.350ns  (71.9% logic, 28.1% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      6.350ns delay SLICE_64 to RA[1] (totaling 8.766ns) meets
+     12.500ns offset RCLK to RA[1] by 3.734ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.966       R2C2A.Q0 to       R2C3B.C0 nRowColSel
+CTOF_DEL    ---     0.371       R2C3B.C0 to       R2C3B.F0 SLICE_94
+ROUTE         1     0.817       R2C3B.F0 to       89.PADDO RA_c_1
+DOPAD_DEL   ---     3.636       89.PADDO to         89.PAD RA[1]
+                  --------
+                    6.350   (71.9% logic, 28.1% route), 3 logic levels.
+
+Report:    8.766ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.826ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     7.258ns  (62.9% logic, 37.1% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      7.258ns delay SLICE_64 to RA[0] (totaling 9.674ns) meets
+     12.500ns offset RCLK to RA[0] by 2.826ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.165       R2C2A.Q0 to       R3C2B.B1 nRowColSel
+CTOF_DEL    ---     0.371       R3C2B.B1 to       R3C2B.F1 SLICE_92
+ROUTE         1     1.526       R3C2B.F1 to       98.PADDO RA_c_0
+DOPAD_DEL   ---     3.636       98.PADDO to         98.PAD RA[0]
+                  --------
+                    7.258   (62.9% logic, 37.1% route), 3 logic levels.
+
+Report:    9.674ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 5.071ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_369  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_60 and
+      5.013ns delay SLICE_60 to nRCS (totaling 7.429ns) meets
+     12.500ns offset RCLK to nRCS by 5.071ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to      R2C5B.CLK RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_60 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C5B.CLK to       R2C5B.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1     0.817       R2C5B.Q0 to       77.PADDO nRCS_c
+DOPAD_DEL   ---     3.636       77.PADDO to         77.PAD nRCS
+                  --------
+                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
+
+Report:    7.429ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.420ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_368  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     6.664ns  (63.0% logic, 37.0% route), 2 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_34 and
+      6.664ns delay SLICE_34 to RCKE (totaling 9.080ns) meets
+     12.500ns offset RCLK to RCKE by 3.420ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to      R5C2A.CLK RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_34 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C2A.CLK to       R5C2A.Q0 SLICE_34 (from RCLK_c)
+ROUTE         4     2.468       R5C2A.Q0 to       82.PADDO RCKE_c
+DOPAD_DEL   ---     3.636       82.PADDO to         82.PAD RCKE
+                  --------
+                    6.664   (63.0% logic, 37.0% route), 2 logic levels.
+
+Report:    9.080ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 5.071ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_372  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_63 and
+      5.013ns delay SLICE_63 to nRWE (totaling 7.429ns) meets
+     12.500ns offset RCLK to nRWE by 5.071ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to      R3C5B.CLK RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C5B.CLK to       R3C5B.Q0 SLICE_63 (from RCLK_c)
+ROUTE         1     0.817       R3C5B.Q0 to       72.PADDO nRWE_c
+DOPAD_DEL   ---     3.636       72.PADDO to         72.PAD nRWE
+                  --------
+                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
+
+Report:    7.429ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.885ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     6.199ns  (67.7% logic, 32.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_61 and
+      6.199ns delay SLICE_61 to nRRAS (totaling 8.615ns) meets
+     12.500ns offset RCLK to nRRAS by 3.885ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to      R4C5A.CLK RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_61 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R4C5A.CLK to       R4C5A.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2     2.003       R4C5A.Q0 to       73.PADDO nRRAS_c
+DOPAD_DEL   ---     3.636       73.PADDO to         73.PAD nRRAS
+                  --------
+                    6.199   (67.7% logic, 32.3% route), 2 logic levels.
+
+Report:    8.615ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.905ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_371  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     6.179ns  (67.9% logic, 32.1% route), 2 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_58 and
+      6.179ns delay SLICE_58 to nRCAS (totaling 8.595ns) meets
+     12.500ns offset RCLK to nRCAS by 3.905ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to      R2C4C.CLK RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_58 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C4C.CLK to       R2C4C.Q0 SLICE_58 (from RCLK_c)
+ROUTE         1     1.983       R2C4C.Q0 to       78.PADDO nRCAS_c
+DOPAD_DEL   ---     3.636       78.PADDO to         78.PAD nRCAS
+                  --------
+                    6.179   (67.9% logic, 32.1% route), 2 logic levels.
+
+Report:    8.595ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.025ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     7.059ns  (64.7% logic, 35.3% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      7.059ns delay SLICE_64 to RDQMH (totaling 9.475ns) meets
+     12.500ns offset RCLK to RDQMH by 3.025ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.966       R2C2A.Q0 to       R2C4A.C0 nRowColSel
+CTOF_DEL    ---     0.371       R2C4A.C0 to       R2C4A.F0 SLICE_88
+ROUTE         1     1.526       R2C4A.F0 to       76.PADDO RDQMH_c
+DOPAD_DEL   ---     3.636       76.PADDO to         76.PAD RDQMH
+                  --------
+                    7.059   (64.7% logic, 35.3% route), 3 logic levels.
+
+Report:    9.475ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.023ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     8.061ns  (56.7% logic, 43.3% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      8.061ns delay SLICE_64 to RDQML (totaling 10.477ns) meets
+     12.500ns offset RCLK to RDQML by 2.023ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.954       R2C2A.Q0 to       R3C2B.C0 nRowColSel
+CTOF_DEL    ---     0.371       R3C2B.C0 to       R3C2B.F0 SLICE_92
+ROUTE         1     2.540       R3C2B.F0 to       61.PADDO RDQML_c
+DOPAD_DEL   ---     3.636       61.PADDO to         61.PAD RDQML
+                  --------
+                    8.061   (56.7% logic, 43.3% route), 3 logic levels.
+
+Report:   10.477ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |   350.000 ns|    26.150 ns|   7  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |    16.000 ns|     8.434 ns|   6  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.596 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.766 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.896 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.255 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.001 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.609 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.504 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.933 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.062 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.766 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.674 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     7.429 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.080 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     7.429 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.615 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.595 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.475 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.477 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 526 paths, 6 nets, and 440 connections (71.20% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
+Mon Aug 16 21:32:34 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO256C_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf 
+Design file:     ram2gs_lcmxo256c_impl1.ncd
+Preference file: ram2gs_lcmxo256c_impl1.prf
+Device,speed:    LCMXO256C,m
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • PERIOD NET "PHI2_c" 350.000000 ns  (0 errors)
    •             113 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCCAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCRAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "RCLK_c" 16.000000 ns  (0 errors)
    •             395 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            113 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.444ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_380  (from PHI2_c -)
+   Destination:    FF         Data in        ADSubmitted_380  (to PHI2_c -)
+
+   Delay:               0.421ns  (62.2% logic, 37.8% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.421ns physical path delay SLICE_9 to SLICE_9 meets
+     -0.023ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.023ns) by 0.444ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C3A.CLK to       R5C3A.Q0 SLICE_9 (from PHI2_c)
+ROUTE         2     0.159       R5C3A.Q0 to       R5C3A.D0 ADSubmitted
+CTOF_DEL    ---     0.092       R5C3A.D0 to       R5C3A.F0 SLICE_9
+ROUTE         1     0.000       R5C3A.F0 to      R5C3A.DI0 n1361 (to PHI2_c)
+                  --------
+                    0.421   (62.2% logic, 37.8% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R5C3A.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R5C3A.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.186ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
+   Destination:    FF         Data in        Cmdn8MEGEN_383  (to PHI2_c -)
+
+   Delay:               1.157ns  (30.6% logic, 69.4% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.157ns physical path delay SLICE_18 to SLICE_23 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.186ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C3C.CLK to       R5C3C.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.253       R5C3C.Q0 to       R5C3C.B1 CmdEnable
+CTOF_DEL    ---     0.092       R5C3C.B1 to       R5C3C.F1 SLICE_18
+ROUTE         3     0.383       R5C3C.F1 to       R4C4D.A0 XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R4C4D.A0 to       R4C4D.F0 SLICE_90
+ROUTE         2     0.167       R4C4D.F0 to       R4C4C.CE PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                    1.157   (30.6% logic, 69.4% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R5C3C.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R4C4C.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.193ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_379  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_378  (to PHI2_c -)
+
+   Delay:               1.164ns  (38.3% logic, 61.7% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.164ns physical path delay SLICE_14 to SLICE_18 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.193ns
+
+ Physical Path Details:
+
+      Data path SLICE_14 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R6C3B.CLK to       R6C3B.Q0 SLICE_14 (from PHI2_c)
+ROUTE         1     0.253       R6C3B.Q0 to       R6C3B.B1 C1Submitted
+CTOF_DEL    ---     0.092       R6C3B.B1 to       R6C3B.F1 SLICE_14
+ROUTE         1     0.075       R6C3B.F1 to       R6C3C.D1 n2098
+CTOF_DEL    ---     0.092       R6C3C.D1 to       R6C3C.F1 SLICE_77
+ROUTE         1     0.123       R6C3C.F1 to       R6C3C.C0 n2286
+CTOF_DEL    ---     0.092       R6C3C.C0 to       R6C3C.F0 SLICE_77
+ROUTE         1     0.267       R6C3C.F0 to       R5C3C.CE PHI2_N_114_enable_8 (to PHI2_c)
+                  --------
+                    1.164   (38.3% logic, 61.7% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R6C3B.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R5C3C.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.280ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_380  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_378  (to PHI2_c -)
+
+   Delay:               1.251ns  (35.7% logic, 64.3% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.251ns physical path delay SLICE_9 to SLICE_18 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.280ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C3A.CLK to       R5C3A.Q0 SLICE_9 (from PHI2_c)
+ROUTE         2     0.159       R5C3A.Q0 to       R5C3A.D1 ADSubmitted
+CTOF_DEL    ---     0.092       R5C3A.D1 to       R5C3A.F1 SLICE_9
+ROUTE         1     0.256       R5C3A.F1 to       R6C3C.A1 n2080
+CTOF_DEL    ---     0.092       R6C3C.A1 to       R6C3C.F1 SLICE_77
+ROUTE         1     0.123       R6C3C.F1 to       R6C3C.C0 n2286
+CTOF_DEL    ---     0.092       R6C3C.C0 to       R6C3C.F0 SLICE_77
+ROUTE         1     0.267       R6C3C.F0 to       R5C3C.CE PHI2_N_114_enable_8 (to PHI2_c)
+                  --------
+                    1.251   (35.7% logic, 64.3% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R5C3A.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R5C3C.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.286ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
+   Destination:    FF         Data in        XOR8MEG_381  (to PHI2_c -)
+
+   Delay:               1.257ns  (28.2% logic, 71.8% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.257ns physical path delay SLICE_18 to SLICE_96 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.286ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C3C.CLK to       R5C3C.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.253       R5C3C.Q0 to       R5C3C.B1 CmdEnable
+CTOF_DEL    ---     0.092       R5C3C.B1 to       R5C3C.F1 SLICE_18
+ROUTE         3     0.383       R5C3C.F1 to       R4C4D.A1 XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R4C4D.A1 to       R4C4D.F1 SLICE_90
+ROUTE         1     0.267       R4C4D.F1 to       R3C4B.CE PHI2_N_114_enable_2 (to PHI2_c)
+                  --------
+                    1.257   (28.2% logic, 71.8% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R5C3C.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R3C4B.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.400ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMSDI_387  (to PHI2_c -)
+
+   Delay:               1.371ns  (25.8% logic, 74.2% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.371ns physical path delay SLICE_18 to SLICE_88 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.400ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C3C.CLK to       R5C3C.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.253       R5C3C.Q0 to       R5C3C.B1 CmdEnable
+CTOF_DEL    ---     0.092       R5C3C.B1 to       R5C3C.F1 SLICE_18
+ROUTE         3     0.383       R5C3C.F1 to       R4C4A.A0 XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R4C4A.A0 to       R4C4A.F0 SLICE_72
+ROUTE         2     0.381       R4C4A.F0 to       R2C4A.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                    1.371   (25.8% logic, 74.2% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R5C3C.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R2C4A.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.414ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
+   Destination:    FF         Data in        CmdSubmitted_384  (to PHI2_c -)
+
+   Delay:               1.385ns  (25.6% logic, 74.4% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.385ns physical path delay SLICE_18 to SLICE_19 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.414ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C3C.CLK to       R5C3C.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.253       R5C3C.Q0 to       R5C3C.B1 CmdEnable
+CTOF_DEL    ---     0.092       R5C3C.B1 to       R5C3C.F1 SLICE_18
+ROUTE         3     0.383       R5C3C.F1 to       R4C4D.A0 XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R4C4D.A0 to       R4C4D.F0 SLICE_90
+ROUTE         2     0.395       R4C4D.F0 to       R5C5A.CE PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                    1.385   (25.6% logic, 74.4% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R5C3C.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R5C5A.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.537ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMCS_385  (to PHI2_c -)
+                   FF                        CmdUFMCLK_386
+
+   Delay:               1.508ns  (23.5% logic, 76.5% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.508ns physical path delay SLICE_18 to SLICE_83 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.537ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C3C.CLK to       R5C3C.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.253       R5C3C.Q0 to       R5C3C.B1 CmdEnable
+CTOF_DEL    ---     0.092       R5C3C.B1 to       R5C3C.F1 SLICE_18
+ROUTE         3     0.383       R5C3C.F1 to       R4C4A.A0 XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R4C4A.A0 to       R4C4A.F0 SLICE_72
+ROUTE         2     0.518       R4C4A.F0 to       R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                    1.508   (23.5% logic, 76.5% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R5C3C.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R5C4B.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 175.681ns (weighted slack = 351.362ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              XOR8MEG_381  (from PHI2_c -)
+   Destination:    FF         Data in        RA11_358  (to PHI2_c +)
+
+   Delay:               0.670ns  (39.1% logic, 60.9% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.670ns physical path delay SLICE_96 to SLICE_31 meets
+     -0.011ns DIN_HLD and
+    -175.000ns delay constraint less
+      0.000ns skew requirement (totaling -175.011ns) by 175.681ns
+
+ Physical Path Details:
+
+      Data path SLICE_96 to SLICE_31:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R3C4B.CLK to       R3C4B.Q0 SLICE_96 (from PHI2_c)
+ROUTE         1     0.408       R3C4B.Q0 to       R2C5A.D0 XOR8MEG
+CTOF_DEL    ---     0.092       R2C5A.D0 to       R2C5A.F0 SLICE_31
+ROUTE         1     0.000       R2C5A.F0 to      R2C5A.DI0 RA11_N_180 (to PHI2_c)
+                  --------
+                    0.670   (39.1% logic, 60.9% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R3C4B.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_31:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R2C5A.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 176.485ns (weighted slack = 352.970ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i3  (from PHI2_c +)
+   Destination:    FF         Data in        C1Submitted_379  (to PHI2_c -)
+
+   Delay:               1.456ns  (23.4% logic, 76.6% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.456ns physical path delay SLICE_98 to SLICE_14 meets
+     -0.029ns CE_HLD and
+    -175.000ns delay constraint less
+      0.000ns skew requirement (totaling -175.029ns) by 176.485ns
+
+ Physical Path Details:
+
+      Data path SLICE_98 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R3C2A.CLK to       R3C2A.Q1 SLICE_98 (from PHI2_c)
+ROUTE         1     0.495       R3C2A.Q1 to       R5C5B.A1 Bank_3
+CTOF_DEL    ---     0.092       R5C5B.A1 to       R5C5B.F1 SLICE_76
+ROUTE         4     0.459       R5C5B.F1 to       R6C3A.D1 n1285
+CTOF_DEL    ---     0.092       R6C3A.D1 to       R6C3A.F1 SLICE_89
+ROUTE         1     0.161       R6C3A.F1 to       R6C3B.CE PHI2_N_114_enable_1 (to PHI2_c)
+                  --------
+                    1.456   (23.4% logic, 76.6% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_98:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R3C2A.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.196       39.PADDI to      R6C3B.CLK PHI2_c
+                  --------
+                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            395 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i11  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i12  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_72 to SLICE_72 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_72 to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R4C4A.CLK to       R4C4A.Q0 SLICE_72 (from RCLK_c)
+ROUTE         1     0.161       R4C4A.Q0 to       R4C4A.M1 n702 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R4C4A.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R4C4A.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i12  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i13  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_72 to SLICE_90 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_72 to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R4C4A.CLK to       R4C4A.Q1 SLICE_72 (from RCLK_c)
+ROUTE         1     0.161       R4C4A.Q1 to       R4C4D.M0 n701 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R4C4A.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R4C4D.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i7  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i8  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_73 to SLICE_73 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_73 to SLICE_73:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R7C4A.CLK to       R7C4A.Q0 SLICE_73 (from RCLK_c)
+ROUTE         1     0.161       R7C4A.Q0 to       R7C4A.M1 n706 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_73:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R7C4A.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_73:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R7C4A.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i3  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i4  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_74 to SLICE_74 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_74 to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C3B.CLK to       R5C3B.Q0 SLICE_74 (from RCLK_c)
+ROUTE         1     0.161       R5C3B.Q0 to       R5C3B.M1 n710 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R5C3B.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R5C3B.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i6  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i7  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_75 to SLICE_73 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_75 to SLICE_73:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R7C4B.CLK to       R7C4B.Q1 SLICE_75 (from RCLK_c)
+ROUTE         1     0.161       R7C4B.Q1 to       R7C4A.M0 n707 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R7C4B.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_73:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R7C4A.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i5  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i6  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_75 to SLICE_75 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_75 to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R7C4B.CLK to       R7C4B.Q0 SLICE_75 (from RCLK_c)
+ROUTE         1     0.161       R7C4B.Q0 to       R7C4B.M1 n708 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R7C4B.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R7C4B.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i10  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i11  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_84 to SLICE_72 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_84 to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R4C4B.CLK to       R4C4B.Q1 SLICE_84 (from RCLK_c)
+ROUTE         1     0.161       R4C4B.Q1 to       R4C4A.M0 n703 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R4C4B.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R4C4A.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i2  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i3  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_87 to SLICE_74 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_87 to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C3D.CLK to       R5C3D.Q1 SLICE_87 (from RCLK_c)
+ROUTE         1     0.161       R5C3D.Q1 to       R5C3B.M0 n711 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_87:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R5C3D.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R5C3B.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i13  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i14  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_90 to SLICE_90 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_90 to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R4C4D.CLK to       R4C4D.Q0 SLICE_90 (from RCLK_c)
+ROUTE         1     0.161       R4C4D.Q0 to       R4C4D.M1 n700 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R4C4D.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R4C4D.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.345ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RASr2_353  (from RCLK_c +)
+   Destination:    FF         Data in        RASr3_354  (to RCLK_c +)
+
+   Delay:               0.324ns  (48.5% logic, 51.5% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.324ns physical path delay SLICE_93 to SLICE_93 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.345ns
+
+ Physical Path Details:
+
+      Data path SLICE_93 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R7C5D.CLK to       R7C5D.Q0 SLICE_93 (from RCLK_c)
+ROUTE        16     0.167       R7C5D.Q0 to       R7C5D.M1 RASr2 (to RCLK_c)
+                  --------
+                    0.324   (48.5% logic, 51.5% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R7C5D.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to      R7C5D.CLK RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.220ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_373  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     1.733ns  (73.0% logic, 27.0% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_55 and
+      1.733ns delay SLICE_55 to RA[10] (totaling 2.220ns) meets
+      0.000ns hold offset RCLK to RA[10] by 2.220ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C4B.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_55 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C4B.CLK to       R2C4B.Q0 SLICE_55 (from RCLK_c)
+ROUTE         1     0.468       R2C4B.Q0 to       87.PADDO n980
+DOPAD_DEL   ---     1.108       87.PADDO to         87.PAD RA[10]
+                  --------
+                    1.733   (73.0% logic, 27.0% route), 2 logic levels.
+
+Report:    2.220ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.284ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     1.797ns  (75.5% logic, 24.5% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      1.797ns delay SLICE_64 to RA[9] (totaling 2.284ns) meets
+      0.000ns hold offset RCLK to RA[9] by 2.284ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.243       R2C2A.Q0 to       R2C4A.C1 nRowColSel
+CTOF_DEL    ---     0.092       R2C4A.C1 to       R2C4A.F1 SLICE_88
+ROUTE         1     0.197       R2C4A.F1 to       85.PADDO RA_c_9
+DOPAD_DEL   ---     1.108       85.PADDO to         85.PAD RA[9]
+                  --------
+                    1.797   (75.5% logic, 24.5% route), 3 logic levels.
+
+Report:    2.284ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.316ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     1.829ns  (74.2% logic, 25.8% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      1.829ns delay SLICE_64 to RA[8] (totaling 2.316ns) meets
+      0.000ns hold offset RCLK to RA[8] by 2.316ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.275       R2C2A.Q0 to       R2C2C.B0 nRowColSel
+CTOF_DEL    ---     0.092       R2C2C.B0 to       R2C2C.F0 SLICE_95
+ROUTE         1     0.197       R2C2C.F0 to       96.PADDO RA_c_8
+DOPAD_DEL   ---     1.108       96.PADDO to         96.PAD RA[8]
+                  --------
+                    1.829   (74.2% logic, 25.8% route), 3 logic levels.
+
+Report:    2.316ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.652ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     2.165ns  (62.7% logic, 37.3% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.165ns delay SLICE_64 to RA[7] (totaling 2.652ns) meets
+      0.000ns hold offset RCLK to RA[7] by 2.652ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.319       R2C2A.Q0 to       R6C2B.D0 nRowColSel
+CTOF_DEL    ---     0.092       R6C2B.D0 to       R6C2B.F0 SLICE_97
+ROUTE         1     0.489       R6C2B.F0 to      100.PADDO RA_c_7
+DOPAD_DEL   ---     1.108      100.PADDO to        100.PAD RA[7]
+                  --------
+                    2.165   (62.7% logic, 37.3% route), 3 logic levels.
+
+Report:    2.652ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.579ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     2.092ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.092ns delay SLICE_64 to RA[6] (totaling 2.579ns) meets
+      0.000ns hold offset RCLK to RA[6] by 2.579ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.243       R2C2A.Q0 to       R3C2A.C0 nRowColSel
+CTOF_DEL    ---     0.092       R3C2A.C0 to       R3C2A.F0 SLICE_98
+ROUTE         1     0.492       R3C2A.F0 to       91.PADDO RA_c_6
+DOPAD_DEL   ---     1.108       91.PADDO to         91.PAD RA[6]
+                  --------
+                    2.092   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    2.579ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.481ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     1.994ns  (68.1% logic, 31.9% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      1.994ns delay SLICE_64 to RA[5] (totaling 2.481ns) meets
+      0.000ns hold offset RCLK to RA[5] by 2.481ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.243       R2C2A.Q0 to       R3C2A.C1 nRowColSel
+CTOF_DEL    ---     0.092       R3C2A.C1 to       R3C2A.F1 SLICE_98
+ROUTE         1     0.394       R3C2A.F1 to       95.PADDO RA_c_5
+DOPAD_DEL   ---     1.108       95.PADDO to         95.PAD RA[5]
+                  --------
+                    1.994   (68.1% logic, 31.9% route), 3 logic levels.
+
+Report:    2.481ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.219ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     1.732ns  (78.3% logic, 21.7% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      1.732ns delay SLICE_64 to RA[4] (totaling 2.219ns) meets
+      0.000ns hold offset RCLK to RA[4] by 2.219ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.178       R2C2A.Q0 to       R2C2A.D1 nRowColSel
+CTOF_DEL    ---     0.092       R2C2A.D1 to       R2C2A.F1 SLICE_64
+ROUTE         1     0.197       R2C2A.F1 to       99.PADDO RA_c_4
+DOPAD_DEL   ---     1.108       99.PADDO to         99.PAD RA[4]
+                  --------
+                    1.732   (78.3% logic, 21.7% route), 3 logic levels.
+
+Report:    2.219ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.555ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     2.068ns  (65.6% logic, 34.4% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.068ns delay SLICE_64 to RA[3] (totaling 2.555ns) meets
+      0.000ns hold offset RCLK to RA[3] by 2.555ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.243       R2C2A.Q0 to       R2C3B.C1 nRowColSel
+CTOF_DEL    ---     0.092       R2C3B.C1 to       R2C3B.F1 SLICE_94
+ROUTE         1     0.468       R2C3B.F1 to       97.PADDO RA_c_3
+DOPAD_DEL   ---     1.108       97.PADDO to         97.PAD RA[3]
+                  --------
+                    2.068   (65.6% logic, 34.4% route), 3 logic levels.
+
+Report:    2.555ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.599ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     2.112ns  (64.3% logic, 35.7% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.112ns delay SLICE_64 to RA[2] (totaling 2.599ns) meets
+      0.000ns hold offset RCLK to RA[2] by 2.599ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.275       R2C2A.Q0 to       R2C2C.B1 nRowColSel
+CTOF_DEL    ---     0.092       R2C2C.B1 to       R2C2C.F1 SLICE_95
+ROUTE         1     0.480       R2C2C.F1 to       94.PADDO RA_c_2
+DOPAD_DEL   ---     1.108       94.PADDO to         94.PAD RA[2]
+                  --------
+                    2.112   (64.3% logic, 35.7% route), 3 logic levels.
+
+Report:    2.599ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.284ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     1.797ns  (75.5% logic, 24.5% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      1.797ns delay SLICE_64 to RA[1] (totaling 2.284ns) meets
+      0.000ns hold offset RCLK to RA[1] by 2.284ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.243       R2C2A.Q0 to       R2C3B.C0 nRowColSel
+CTOF_DEL    ---     0.092       R2C3B.C0 to       R2C3B.F0 SLICE_94
+ROUTE         1     0.197       R2C3B.F0 to       89.PADDO RA_c_1
+DOPAD_DEL   ---     1.108       89.PADDO to         89.PAD RA[1]
+                  --------
+                    1.797   (75.5% logic, 24.5% route), 3 logic levels.
+
+Report:    2.284ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.492ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     2.005ns  (67.7% logic, 32.3% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.005ns delay SLICE_64 to RA[0] (totaling 2.492ns) meets
+      0.000ns hold offset RCLK to RA[0] by 2.492ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.292       R2C2A.Q0 to       R3C2B.B1 nRowColSel
+CTOF_DEL    ---     0.092       R3C2B.B1 to       R3C2B.F1 SLICE_92
+ROUTE         1     0.356       R3C2B.F1 to       98.PADDO RA_c_0
+DOPAD_DEL   ---     1.108       98.PADDO to         98.PAD RA[0]
+                  --------
+                    2.005   (67.7% logic, 32.3% route), 3 logic levels.
+
+Report:    2.492ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.949ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_369  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_60 and
+      1.462ns delay SLICE_60 to nRCS (totaling 1.949ns) meets
+      0.000ns hold offset RCLK to nRCS by 1.949ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C5B.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_60 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C5B.CLK to       R2C5B.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1     0.197       R2C5B.Q0 to       77.PADDO nRCS_c
+DOPAD_DEL   ---     1.108       77.PADDO to         77.PAD nRCS
+                  --------
+                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    1.949ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.363ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_368  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     1.876ns  (67.4% logic, 32.6% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_34 and
+      1.876ns delay SLICE_34 to RCKE (totaling 2.363ns) meets
+      0.000ns hold offset RCLK to RCKE by 2.363ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C2A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_34 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C2A.CLK to       R5C2A.Q0 SLICE_34 (from RCLK_c)
+ROUTE         4     0.611       R5C2A.Q0 to       82.PADDO RCKE_c
+DOPAD_DEL   ---     1.108       82.PADDO to         82.PAD RCKE
+                  --------
+                    1.876   (67.4% logic, 32.6% route), 2 logic levels.
+
+Report:    2.363ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.949ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_372  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_63 and
+      1.462ns delay SLICE_63 to nRWE (totaling 1.949ns) meets
+      0.000ns hold offset RCLK to nRWE by 1.949ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R3C5B.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_63 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R3C5B.CLK to       R3C5B.Q0 SLICE_63 (from RCLK_c)
+ROUTE         1     0.197       R3C5B.Q0 to       72.PADDO nRWE_c
+DOPAD_DEL   ---     1.108       72.PADDO to         72.PAD nRWE
+                  --------
+                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    1.949ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.236ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     1.749ns  (72.3% logic, 27.7% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_61 and
+      1.749ns delay SLICE_61 to nRRAS (totaling 2.236ns) meets
+      0.000ns hold offset RCLK to nRRAS by 2.236ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R4C5A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_61 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R4C5A.CLK to       R4C5A.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2     0.484       R4C5A.Q0 to       73.PADDO nRRAS_c
+DOPAD_DEL   ---     1.108       73.PADDO to         73.PAD nRRAS
+                  --------
+                    1.749   (72.3% logic, 27.7% route), 2 logic levels.
+
+Report:    2.236ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.232ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_371  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     1.745ns  (72.5% logic, 27.5% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_58 and
+      1.745ns delay SLICE_58 to nRCAS (totaling 2.232ns) meets
+      0.000ns hold offset RCLK to nRCAS by 2.232ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C4C.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_58 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C4C.CLK to       R2C4C.Q0 SLICE_58 (from RCLK_c)
+ROUTE         1     0.480       R2C4C.Q0 to       78.PADDO nRCAS_c
+DOPAD_DEL   ---     1.108       78.PADDO to         78.PAD nRCAS
+                  --------
+                    1.745   (72.5% logic, 27.5% route), 2 logic levels.
+
+Report:    2.232ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.443ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     1.956ns  (69.4% logic, 30.6% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      1.956ns delay SLICE_64 to RDQMH (totaling 2.443ns) meets
+      0.000ns hold offset RCLK to RDQMH by 2.443ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.243       R2C2A.Q0 to       R2C4A.C0 nRowColSel
+CTOF_DEL    ---     0.092       R2C4A.C0 to       R2C4A.F0 SLICE_88
+ROUTE         1     0.356       R2C4A.F0 to       76.PADDO RDQMH_c
+DOPAD_DEL   ---     1.108       76.PADDO to         76.PAD RDQMH
+                  --------
+                    1.956   (69.4% logic, 30.6% route), 3 logic levels.
+
+Report:    2.443ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.713ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     2.226ns  (61.0% logic, 39.0% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.226ns delay SLICE_64 to RDQML (totaling 2.713ns) meets
+      0.000ns hold offset RCLK to RDQML by 2.713ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C2A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.238       R2C2A.Q0 to       R3C2B.C0 nRowColSel
+CTOF_DEL    ---     0.092       R3C2B.C0 to       R3C2B.F0 SLICE_92
+ROUTE         1     0.631       R3C2B.F0 to       61.PADDO RDQML_c
+DOPAD_DEL   ---     1.108       61.PADDO to         61.PAD RDQML
+                  --------
+                    2.226   (61.0% logic, 39.0% route), 3 logic levels.
+
+Report:    2.713ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |            -|            -|   2  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |            -|            -|   1  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.220 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.284 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.316 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.652 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.579 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.481 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.219 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.555 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.599 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.284 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.492 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.363 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.236 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.232 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.443 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.713 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 526 paths, 6 nets, and 440 connections (71.20% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 0 (setup), 0 (hold)
+Score: 0 (setup), 0 (hold)
+Cumulative negative slack: 0 (0+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
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    + + diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_drc.log b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_drc.log new file mode 100644 index 0000000..946f96e --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_drc.log @@ -0,0 +1,15 @@ +Results of NGD DRC are available in RAM2GS_drc.log. +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... + + +Running DRC... + +DRC complete with no errors or warnings + +Design Results: + 304 blocks expanded +completed the first expansion +All blocks are expanded and NGD expansion is successful. +Writing NGD file RAM2GS_LCMXO256C_impl1.ngd. diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_lse.twr b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_lse.twr new file mode 100644 index 0000000..83d5ab2 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_lse.twr @@ -0,0 +1,311 @@ +-------------------------------------------------------------------------------- +Lattice Synthesis Timing Report, Version +Mon Aug 16 21:32:26 2021 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Design: RAM2GS +Constraint file: +Report level: verbose report, limited to 3 items per constraint +-------------------------------------------------------------------------------- + + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c] + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c] + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c] + 122 items scored, 121 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path violates requirements by 10.378ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK Bank_i5 (from PHI2_c +) + Destination: FD1P3AX SP CmdUFMCS_385 (to PHI2_c -) + + Delay: 12.614ns (23.4% logic, 76.6% route), 7 logic levels. + + Constraint Details: + + 12.614ns data_path Bank_i5 to CmdUFMCS_385 violates + 2.500ns delay constraint less + 0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns + + Path Details: Bank_i5 to CmdUFMCS_385 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.613 CK to Q Bank_i5 (from PHI2_c) +Route 1 e 1.220 Bank[5] +LUT4 --- 0.390 B to Z i1856_4_lut +Route 1 e 1.220 n2166 +LUT4 --- 0.390 B to Z i12_4_lut +Route 1 e 1.220 n26 +LUT4 --- 0.390 B to Z i13_4_lut +Route 4 e 1.552 n1285 +LUT4 --- 0.390 B to Z i1830_2_lut_rep_13 +Route 3 e 1.483 n2290 +LUT4 --- 0.390 D to Z i3_4_lut +Route 3 e 1.483 XOR8MEG_N_112 +LUT4 --- 0.390 A to Z i2_3_lut_4_lut +Route 3 e 1.483 PHI2_N_114_enable_7 + -------- + 12.614 (23.4% logic, 76.6% route), 7 logic levels. + + +Error: The following path violates requirements by 10.378ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK Bank_i5 (from PHI2_c +) + Destination: FD1P3AX SP CmdUFMSDI_387 (to PHI2_c -) + + Delay: 12.614ns (23.4% logic, 76.6% route), 7 logic levels. + + Constraint Details: + + 12.614ns data_path Bank_i5 to CmdUFMSDI_387 violates + 2.500ns delay constraint less + 0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns + + Path Details: Bank_i5 to CmdUFMSDI_387 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.613 CK to Q Bank_i5 (from PHI2_c) +Route 1 e 1.220 Bank[5] +LUT4 --- 0.390 B to Z i1856_4_lut +Route 1 e 1.220 n2166 +LUT4 --- 0.390 B to Z i12_4_lut +Route 1 e 1.220 n26 +LUT4 --- 0.390 B to Z i13_4_lut +Route 4 e 1.552 n1285 +LUT4 --- 0.390 B to Z i1830_2_lut_rep_13 +Route 3 e 1.483 n2290 +LUT4 --- 0.390 D to Z i3_4_lut +Route 3 e 1.483 XOR8MEG_N_112 +LUT4 --- 0.390 A to Z i2_3_lut_4_lut +Route 3 e 1.483 PHI2_N_114_enable_7 + -------- + 12.614 (23.4% logic, 76.6% route), 7 logic levels. + + +Error: The following path violates requirements by 10.378ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK Bank_i5 (from PHI2_c +) + Destination: FD1P3AX SP CmdUFMCLK_386 (to PHI2_c -) + + Delay: 12.614ns (23.4% logic, 76.6% route), 7 logic levels. + + Constraint Details: + + 12.614ns data_path Bank_i5 to CmdUFMCLK_386 violates + 2.500ns delay constraint less + 0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns + + Path Details: Bank_i5 to CmdUFMCLK_386 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.613 CK to Q Bank_i5 (from PHI2_c) +Route 1 e 1.220 Bank[5] +LUT4 --- 0.390 B to Z i1856_4_lut +Route 1 e 1.220 n2166 +LUT4 --- 0.390 B to Z i12_4_lut +Route 1 e 1.220 n26 +LUT4 --- 0.390 B to Z i13_4_lut +Route 4 e 1.552 n1285 +LUT4 --- 0.390 B to Z i1830_2_lut_rep_13 +Route 3 e 1.483 n2290 +LUT4 --- 0.390 D to Z i3_4_lut +Route 3 e 1.483 XOR8MEG_N_112 +LUT4 --- 0.390 A to Z i2_3_lut_4_lut +Route 3 e 1.483 PHI2_N_114_enable_7 + -------- + 12.614 (23.4% logic, 76.6% route), 7 logic levels. + +Warning: 12.878 ns is the maximum delay for this constraint. + + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c] + 369 items scored, 244 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path violates requirements by 6.291ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK FS_577__i12 (from RCLK_c +) + Destination: FD1P3AX SP LEDEN_392 (to RCLK_c +) + + Delay: 11.027ns (23.2% logic, 76.8% route), 6 logic levels. + + Constraint Details: + + 11.027ns data_path FS_577__i12 to LEDEN_392 violates + 5.000ns delay constraint less + 0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns + + Path Details: FS_577__i12 to LEDEN_392 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.613 CK to Q FS_577__i12 (from RCLK_c) +Route 3 e 1.603 FS[12] +LUT4 --- 0.390 C to Z i4_4_lut +Route 3 e 1.483 n10 +LUT4 --- 0.390 B to Z i5_3_lut_rep_23 +Route 4 e 1.552 n2300 +LUT4 --- 0.390 B to Z i4_3_lut_4_lut +Route 1 e 1.220 n11 +LUT4 --- 0.390 C to Z i2_4_lut_adj_4 +Route 2 e 1.386 n2119 +LUT4 --- 0.390 C to Z i2_3_lut_3_lut +Route 1 e 1.220 RCLK_c_enable_25 + -------- + 11.027 (23.2% logic, 76.8% route), 6 logic levels. + + +Error: The following path violates requirements by 6.291ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK FS_577__i12 (from RCLK_c +) + Destination: FD1P3AX SP n8MEGEN_391 (to RCLK_c +) + + Delay: 11.027ns (23.2% logic, 76.8% route), 6 logic levels. + + Constraint Details: + + 11.027ns data_path FS_577__i12 to n8MEGEN_391 violates + 5.000ns delay constraint less + 0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns + + Path Details: FS_577__i12 to n8MEGEN_391 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.613 CK to Q FS_577__i12 (from RCLK_c) +Route 3 e 1.603 FS[12] +LUT4 --- 0.390 C to Z i4_4_lut +Route 3 e 1.483 n10 +LUT4 --- 0.390 B to Z i5_3_lut_rep_23 +Route 4 e 1.552 n2300 +LUT4 --- 0.390 B to Z i4_3_lut_4_lut +Route 1 e 1.220 n11 +LUT4 --- 0.390 C to Z i2_4_lut_adj_4 +Route 2 e 1.386 n2119 +LUT4 --- 0.390 D to Z i1248_4_lut +Route 1 e 1.220 RCLK_c_enable_7 + -------- + 11.027 (23.2% logic, 76.8% route), 6 logic levels. + + +Error: The following path violates requirements by 6.291ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK FS_577__i13 (from RCLK_c +) + Destination: FD1P3AX SP LEDEN_392 (to RCLK_c +) + + Delay: 11.027ns (23.2% logic, 76.8% route), 6 logic levels. + + Constraint Details: + + 11.027ns data_path FS_577__i13 to LEDEN_392 violates + 5.000ns delay constraint less + 0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns + + Path Details: FS_577__i13 to LEDEN_392 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.613 CK to Q FS_577__i13 (from RCLK_c) +Route 3 e 1.603 FS[13] +LUT4 --- 0.390 B to Z i4_4_lut +Route 3 e 1.483 n10 +LUT4 --- 0.390 B to Z i5_3_lut_rep_23 +Route 4 e 1.552 n2300 +LUT4 --- 0.390 B to Z i4_3_lut_4_lut +Route 1 e 1.220 n11 +LUT4 --- 0.390 C to Z i2_4_lut_adj_4 +Route 2 e 1.386 n2119 +LUT4 --- 0.390 C to Z i2_3_lut_3_lut +Route 1 e 1.220 RCLK_c_enable_25 + -------- + 11.027 (23.2% logic, 76.8% route), 6 logic levels. + +Warning: 11.291 ns is the maximum delay for this constraint. + + +Timing Report Summary +-------------- +-------------------------------------------------------------------------------- +Constraint | Constraint| Actual|Levels +-------------------------------------------------------------------------------- + | | | +create_clock -period 5.000000 -name | | | +clk3 [get_nets nCCAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk2 [get_nets nCRAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk1 [get_nets PHI2_c] | 5.000 ns| 25.756 ns| 7 * + | | | +create_clock -period 5.000000 -name | | | +clk0 [get_nets RCLK_c] | 5.000 ns| 11.291 ns| 6 * + | | | +-------------------------------------------------------------------------------- + + +2 constraints not met. + +-------------------------------------------------------------------------------- +Critical Nets | Loads| Errors| % of total +-------------------------------------------------------------------------------- +n1285 | 4| 112| 30.68% + | | | +n26 | 1| 70| 19.18% + | | | +RCLK_c_enable_23 | 16| 64| 17.53% + | | | +n2290 | 3| 64| 17.53% + | | | +XOR8MEG_N_112 | 3| 54| 14.79% + | | | +n2119 | 2| 48| 13.15% + | | | +n2166 | 1| 42| 11.51% + | | | +-------------------------------------------------------------------------------- + + +Timing summary: +--------------- + +Timing errors: 365 Score: 2309745 + +Constraints cover 495 paths, 177 nets, and 464 connections (66.5% coverage) + + +Peak memory: 52502528 bytes, TRCE: 1482752 bytes, DLYMAN: 163840 bytes +CPU_TIME_REPORT: 0 secs diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_lse_lsetwr.html b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_lse_lsetwr.html new file mode 100644 index 0000000..82208e7 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_lse_lsetwr.html @@ -0,0 +1,376 @@ + +Lattice Synthesis Timing Report + + +
    Lattice Synthesis Timing Report
+--------------------------------------------------------------------------------
+Lattice Synthesis Timing Report, Version  
+Mon Aug 16 21:32:26 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Design:     RAM2GS
+Constraint file:  
+Report level:    verbose report, limited to 3 items per constraint
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c]
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c]
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c]
+            122 items scored, 121 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error:  The following path violates requirements by 10.378ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i5  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdUFMCS_385  (to PHI2_c -)
+
+   Delay:                  12.614ns  (23.4% logic, 76.6% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.614ns data_path Bank_i5 to CmdUFMCS_385 violates
+      2.500ns delay constraint less
+      0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns
+
+ Path Details: Bank_i5 to CmdUFMCS_385
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              Bank_i5 (from PHI2_c)
+Route         1   e 1.220                                  Bank[5]
+LUT4        ---     0.390              B to Z              i1856_4_lut
+Route         1   e 1.220                                  n2166
+LUT4        ---     0.390              B to Z              i12_4_lut
+Route         1   e 1.220                                  n26
+LUT4        ---     0.390              B to Z              i13_4_lut
+Route         4   e 1.552                                  n1285
+LUT4        ---     0.390              B to Z              i1830_2_lut_rep_13
+Route         3   e 1.483                                  n2290
+LUT4        ---     0.390              D to Z              i3_4_lut
+Route         3   e 1.483                                  XOR8MEG_N_112
+LUT4        ---     0.390              A to Z              i2_3_lut_4_lut
+Route         3   e 1.483                                  PHI2_N_114_enable_7
+                  --------
+                   12.614  (23.4% logic, 76.6% route), 7 logic levels.
+
+
+Error:  The following path violates requirements by 10.378ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i5  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdUFMSDI_387  (to PHI2_c -)
+
+   Delay:                  12.614ns  (23.4% logic, 76.6% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.614ns data_path Bank_i5 to CmdUFMSDI_387 violates
+      2.500ns delay constraint less
+      0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns
+
+ Path Details: Bank_i5 to CmdUFMSDI_387
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              Bank_i5 (from PHI2_c)
+Route         1   e 1.220                                  Bank[5]
+LUT4        ---     0.390              B to Z              i1856_4_lut
+Route         1   e 1.220                                  n2166
+LUT4        ---     0.390              B to Z              i12_4_lut
+Route         1   e 1.220                                  n26
+LUT4        ---     0.390              B to Z              i13_4_lut
+Route         4   e 1.552                                  n1285
+LUT4        ---     0.390              B to Z              i1830_2_lut_rep_13
+Route         3   e 1.483                                  n2290
+LUT4        ---     0.390              D to Z              i3_4_lut
+Route         3   e 1.483                                  XOR8MEG_N_112
+LUT4        ---     0.390              A to Z              i2_3_lut_4_lut
+Route         3   e 1.483                                  PHI2_N_114_enable_7
+                  --------
+                   12.614  (23.4% logic, 76.6% route), 7 logic levels.
+
+
+Error:  The following path violates requirements by 10.378ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i5  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdUFMCLK_386  (to PHI2_c -)
+
+   Delay:                  12.614ns  (23.4% logic, 76.6% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.614ns data_path Bank_i5 to CmdUFMCLK_386 violates
+      2.500ns delay constraint less
+      0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns
+
+ Path Details: Bank_i5 to CmdUFMCLK_386
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              Bank_i5 (from PHI2_c)
+Route         1   e 1.220                                  Bank[5]
+LUT4        ---     0.390              B to Z              i1856_4_lut
+Route         1   e 1.220                                  n2166
+LUT4        ---     0.390              B to Z              i12_4_lut
+Route         1   e 1.220                                  n26
+LUT4        ---     0.390              B to Z              i13_4_lut
+Route         4   e 1.552                                  n1285
+LUT4        ---     0.390              B to Z              i1830_2_lut_rep_13
+Route         3   e 1.483                                  n2290
+LUT4        ---     0.390              D to Z              i3_4_lut
+Route         3   e 1.483                                  XOR8MEG_N_112
+LUT4        ---     0.390              A to Z              i2_3_lut_4_lut
+Route         3   e 1.483                                  PHI2_N_114_enable_7
+                  --------
+                   12.614  (23.4% logic, 76.6% route), 7 logic levels.
+
+Warning: 12.878 ns is the maximum delay for this constraint.
+
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c]
+            369 items scored, 244 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error:  The following path violates requirements by 6.291ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_577__i12  (from RCLK_c +)
+   Destination:    FD1P3AX    SP             LEDEN_392  (to RCLK_c +)
+
+   Delay:                  11.027ns  (23.2% logic, 76.8% route), 6 logic levels.
+
+ Constraint Details:
+
+     11.027ns data_path FS_577__i12 to LEDEN_392 violates
+      5.000ns delay constraint less
+      0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns
+
+ Path Details: FS_577__i12 to LEDEN_392
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              FS_577__i12 (from RCLK_c)
+Route         3   e 1.603                                  FS[12]
+LUT4        ---     0.390              C to Z              i4_4_lut
+Route         3   e 1.483                                  n10
+LUT4        ---     0.390              B to Z              i5_3_lut_rep_23
+Route         4   e 1.552                                  n2300
+LUT4        ---     0.390              B to Z              i4_3_lut_4_lut
+Route         1   e 1.220                                  n11
+LUT4        ---     0.390              C to Z              i2_4_lut_adj_4
+Route         2   e 1.386                                  n2119
+LUT4        ---     0.390              C to Z              i2_3_lut_3_lut
+Route         1   e 1.220                                  RCLK_c_enable_25
+                  --------
+                   11.027  (23.2% logic, 76.8% route), 6 logic levels.
+
+
+Error:  The following path violates requirements by 6.291ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_577__i12  (from RCLK_c +)
+   Destination:    FD1P3AX    SP             n8MEGEN_391  (to RCLK_c +)
+
+   Delay:                  11.027ns  (23.2% logic, 76.8% route), 6 logic levels.
+
+ Constraint Details:
+
+     11.027ns data_path FS_577__i12 to n8MEGEN_391 violates
+      5.000ns delay constraint less
+      0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns
+
+ Path Details: FS_577__i12 to n8MEGEN_391
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              FS_577__i12 (from RCLK_c)
+Route         3   e 1.603                                  FS[12]
+LUT4        ---     0.390              C to Z              i4_4_lut
+Route         3   e 1.483                                  n10
+LUT4        ---     0.390              B to Z              i5_3_lut_rep_23
+Route         4   e 1.552                                  n2300
+LUT4        ---     0.390              B to Z              i4_3_lut_4_lut
+Route         1   e 1.220                                  n11
+LUT4        ---     0.390              C to Z              i2_4_lut_adj_4
+Route         2   e 1.386                                  n2119
+LUT4        ---     0.390              D to Z              i1248_4_lut
+Route         1   e 1.220                                  RCLK_c_enable_7
+                  --------
+                   11.027  (23.2% logic, 76.8% route), 6 logic levels.
+
+
+Error:  The following path violates requirements by 6.291ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_577__i13  (from RCLK_c +)
+   Destination:    FD1P3AX    SP             LEDEN_392  (to RCLK_c +)
+
+   Delay:                  11.027ns  (23.2% logic, 76.8% route), 6 logic levels.
+
+ Constraint Details:
+
+     11.027ns data_path FS_577__i13 to LEDEN_392 violates
+      5.000ns delay constraint less
+      0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns
+
+ Path Details: FS_577__i13 to LEDEN_392
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              FS_577__i13 (from RCLK_c)
+Route         3   e 1.603                                  FS[13]
+LUT4        ---     0.390              B to Z              i4_4_lut
+Route         3   e 1.483                                  n10
+LUT4        ---     0.390              B to Z              i5_3_lut_rep_23
+Route         4   e 1.552                                  n2300
+LUT4        ---     0.390              B to Z              i4_3_lut_4_lut
+Route         1   e 1.220                                  n11
+LUT4        ---     0.390              C to Z              i2_4_lut_adj_4
+Route         2   e 1.386                                  n2119
+LUT4        ---     0.390              C to Z              i2_3_lut_3_lut
+Route         1   e 1.220                                  RCLK_c_enable_25
+                  --------
+                   11.027  (23.2% logic, 76.8% route), 6 logic levels.
+
+Warning: 11.291 ns is the maximum delay for this constraint.
+
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk1 [get_nets PHI2_c]                  |     5.000 ns|    25.756 ns|     7 *
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets RCLK_c]                  |     5.000 ns|    11.291 ns|     6 *
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+2 constraints not met.
+
+--------------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+--------------------------------------------------------------------------------
+n1285                                   |       4|     112|     30.68%
+                                        |        |        |
+n26                                     |       1|      70|     19.18%
+                                        |        |        |
+RCLK_c_enable_23                        |      16|      64|     17.53%
+                                        |        |        |
+n2290                                   |       3|      64|     17.53%
+                                        |        |        |
+XOR8MEG_N_112                           |       3|      54|     14.79%
+                                        |        |        |
+n2119                                   |       2|      48|     13.15%
+                                        |        |        |
+n2166                                   |       1|      42|     11.51%
+                                        |        |        |
+--------------------------------------------------------------------------------
+
+
+Timing summary:
+---------------
+
+Timing errors: 365  Score: 2309745
+
+Constraints cover  495 paths, 177 nets, and 464 connections (66.5% coverage)
+
+
+Peak memory: 52502528 bytes, TRCE: 1482752 bytes, DLYMAN: 163840 bytes
+CPU_TIME_REPORT: 0 secs 
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    + + diff --git a/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_prim.v b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_prim.v new file mode 100644 index 0000000..d942735 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_prim.v @@ -0,0 +1,789 @@ +// Verilog netlist produced by program LSE : version Diamond (64-bit) 3.12.0.240.2 +// Netlist written on Mon Aug 16 21:32:26 2021 +// +// Verilog Description of module RAM2GS +// + +module RAM2GS (PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, + LED, RBA, RA, RD, nRCS, RCLK, RCKE, nRWE, nRRAS, + nRCAS, RDQMH, RDQML, nUFMCS, UFMCLK, UFMSDI, UFMSDO) /* synthesis syn_module_defined=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(1[8:14]) + input PHI2; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(8[8:12]) + input [9:0]MAin; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18]) + input [1:0]CROW; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(34[14:18]) + input [7:0]Din; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17]) + output [7:0]Dout; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19]) + input nCCAS; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[8:13]) + input nCRAS; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[15:20]) + input nFWE; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(36[8:12]) + output LED; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(12[9:12]) + output [1:0]RBA; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(47[19:22]) + output [11:0]RA; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18]) + inout [7:0]RD; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16]) + output nRCS; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[13:17]) + input RCLK; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(41[8:12]) + output RCKE; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(45[13:17]) + output nRWE; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[45:49]) + output nRRAS; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[23:28]) + output nRCAS; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[34:39]) + output RDQMH; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(56[16:21]) + output RDQML; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(56[9:14]) + output nUFMCS; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(63[13:19]) + output UFMCLK; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(64[13:19]) + output UFMSDI; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(65[13:19]) + input UFMSDO; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(66[8:14]) + + wire PHI2_c /* synthesis is_clock=1, SET_AS_NETWORK=PHI2_c */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(8[8:12]) + wire nCCAS_c /* synthesis is_clock=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[8:13]) + wire nCRAS_c /* synthesis is_clock=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[15:20]) + wire RCLK_c /* synthesis SET_AS_NETWORK=RCLK_c, is_clock=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(41[8:12]) + wire nCCAS_N_3 /* synthesis is_inv_clock=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19]) + wire nCRAS_N_9 /* synthesis is_inv_clock=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(47[19:22]) + wire PHI2_N_114 /* synthesis is_inv_clock=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(38[6:13]) + + wire GND_net, VCC_net, LEDEN, PHI2r, PHI2r2, PHI2r3, RASr, + RASr2, RASr3, CASr, CASr2, CASr3, FWEr, CBR, Din_c_7, + Din_c_6, Din_c_5, Din_c_4, Din_c_3, Din_c_2, Din_c_1, Din_c_0, + n2131, n33, PHI2_N_114_enable_2, n1; + wire [7:0]Bank; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(31[12:16]) + + wire CROW_c_1, CROW_c_0, MAin_c_9, MAin_c_8, MAin_c_7, MAin_c_6, + MAin_c_5, MAin_c_4, MAin_c_3, MAin_c_2, MAin_c_1, MAin_c_0, + nFWE_c, n8MEGEN, XOR8MEG, RCKEEN, RCKE_c, nRCS_c, nRRAS_c, + nRCAS_c, nRWE_c, RBA_c_1, RBA_c_0, nRowColSel, RA_c, n980; + wire [9:0]RowA; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(51[12:16]) + + wire RA_c_9, RA_c_8, RA_c_7, RA_c_6, RA_c_5, RA_c_4, RA_c_3, + RA_c_2, RA_c_1, RA_c_0, RDQML_c, RDQMH_c; + wire [7:0]WRD; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(59[12:15]) + + wire nUFMCS_c, UFMCLK_c, UFMSDI_c, UFMSDO_c, C1Submitted, ADSubmitted, + CmdEnable, CmdSubmitted, Cmdn8MEGEN, CmdUFMCLK, CmdUFMSDI, + CmdUFMCS, InitReady, Ready; + wire [17:0]FS; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(86[13:15]) + + wire LED_N_90, RA11_N_180, n2164, n1895, n2294, n4, PHI2_N_114_enable_6, + n1881, RASr2_N_63, RCKE_N_128, nRowColSel_N_35, nRWE_N_178, + RCKEEN_N_126, nRowColSel_N_34, nRowColSel_N_33, nRowColSel_N_32, + nRowColSel_N_28, n1880, n4_adj_1, n2286, RCKEEN_N_117, nRWE_N_174, + RCKEEN_N_116, nRCS_N_135, nRCAS_N_161, nRWE_N_173, nRWE_N_172, + n1377, Ready_N_272, n2287, n26, Ready_N_268, nRCS_N_132, + nRCAS_N_157, nRWE_N_167, RCKEEN_N_115, n2290, n2289, n1361, + n1369, ADSubmitted_N_234, CmdEnable_N_236, C1Submitted_N_225, + XOR8MEG_N_112, n2098, PHI2_N_114_enable_1, n2248, Cmdn8MEGEN_N_248, + RCLK_c_enable_7, n2244, n2117, LEDEN_N_88, RCLK_c_enable_6, + UFMSDO_N_74, n2243, RCLK_c_enable_24, n8MEGEN_N_94, UFMCLK_N_212, + UFMSDI_N_219, n2242, n2114, n2080, PHI2_N_114_enable_7, n12, + n699, n700, n701, n702, n703, n705, n706, n707, n708, + n709, n710, n711, n11, n2076, n2119, n1368, n12_adj_2, + n1878, PHI2_N_114_enable_8, n2308, n2291, n2307, n11_adj_3, + n973, n1135, n78, n79, n80, n81, n82, n83, n84, n85, + n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, + n1348, n50, n1877, RCLK_c_enable_23, n1876, n1875, n2293, + n2306, RCLK_c_enable_4, n2170, RCLK_c_enable_25, RCLK_c_enable_3, + n2128, n2103, n2304, n2386, n1879, n1874, n2310, n974, + n975, n962, n976, n2168, n977, n2245, n978, n2122, n979, + Dout_c, n2166, n2302, n2108, n2301, n2387, n1285, n2300, + n1628, n1627, n2299, n18, n2385, n2309, n2298, n2292, + n2297, n2154, n10, n2296, n2295; + + VHI i2 (.Z(VCC_net)); + INV i1963 (.A(nCCAS_c), .Z(nCCAS_N_3)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[8:13]) + FD1S3AX PHI2r2_350 (.D(PHI2r), .CK(RCLK_c), .Q(PHI2r2)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5]) + defparam PHI2r2_350.GSR = "ENABLED"; + ORCALUT4 i2_3_lut_4_lut (.A(XOR8MEG_N_112), .B(n2298), .C(n2296), + .D(Din_c_5), .Z(PHI2_N_114_enable_7)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ; + defparam i2_3_lut_4_lut.init = 16'h0800; + ORCALUT4 i1_2_lut_3_lut (.A(FS[11]), .B(n2300), .C(InitReady), .Z(n4)) /* synthesis lut_function=((B+(C))+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37]) + defparam i1_2_lut_3_lut.init = 16'hfdfd; + FD1S3AX PHI2r3_351 (.D(PHI2r2), .CK(RCLK_c), .Q(PHI2r3)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5]) + defparam PHI2r3_351.GSR = "ENABLED"; + FD1S3AX RASr_352 (.D(nCRAS_N_9), .CK(RCLK_c), .Q(RASr)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5]) + defparam RASr_352.GSR = "ENABLED"; + FD1S3AX RASr2_353 (.D(RASr), .CK(RCLK_c), .Q(RASr2)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5]) + defparam RASr2_353.GSR = "ENABLED"; + FD1S3AX RASr3_354 (.D(RASr2), .CK(RCLK_c), .Q(RASr3)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5]) + defparam RASr3_354.GSR = "ENABLED"; + FD1S3AX CASr_355 (.D(nCCAS_N_3), .CK(RCLK_c), .Q(CASr)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5]) + defparam CASr_355.GSR = "ENABLED"; + FD1S3AX CASr2_356 (.D(CASr), .CK(RCLK_c), .Q(CASr2)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5]) + defparam CASr2_356.GSR = "ENABLED"; + FD1S3AX CASr3_357 (.D(CASr2), .CK(RCLK_c), .Q(CASr3)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5]) + defparam CASr3_357.GSR = "ENABLED"; + FD1S3IX RA11_358 (.D(RA11_N_180), .CK(PHI2_c), .CD(n2307), .Q(RA_c)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5]) + defparam RA11_358.GSR = "ENABLED"; + FD1S3IX RowA_i0 (.D(MAin_c_0), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[0])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) + defparam RowA_i0.GSR = "ENABLED"; + FD1S3AX WRD_i0 (.D(Din_c_0), .CK(nCCAS_N_3), .Q(WRD[0])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5]) + defparam WRD_i0.GSR = "ENABLED"; + FD1S3AX FWEr_362 (.D(n2306), .CK(nCRAS_N_9), .Q(FWEr)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) + defparam FWEr_362.GSR = "ENABLED"; + FD1S3AX CBR_363 (.D(nCCAS_N_3), .CK(nCRAS_N_9), .Q(CBR)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) + defparam CBR_363.GSR = "ENABLED"; + FD1S3IX ADSubmitted_380 (.D(n1361), .CK(PHI2_N_114), .CD(C1Submitted_N_225), + .Q(ADSubmitted)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5]) + defparam ADSubmitted_380.GSR = "ENABLED"; + ORCALUT4 MAin_9__I_0_400_i5_3_lut (.A(RowA[4]), .B(MAin_c_4), .C(nRowColSel), + .Z(RA_c_4)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54]) + defparam MAin_9__I_0_400_i5_3_lut.init = 16'hcaca; + ORCALUT4 i1_2_lut (.A(FS[10]), .B(n2076), .Z(RCLK_c_enable_6)) /* synthesis lut_function=(A (B)) */ ; + defparam i1_2_lut.init = 16'h8888; + CCU2 FS_577_add_4_10 (.A0(FS[8]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[9]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1877), + .COUT1(n1878), .S0(n87), .S1(n86)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577_add_4_10.INIT0 = 16'hfaaa; + defparam FS_577_add_4_10.INIT1 = 16'hfaaa; + defparam FS_577_add_4_10.INJECT1_0 = "NO"; + defparam FS_577_add_4_10.INJECT1_1 = "NO"; + FD1S3AX RCKE_368 (.D(RCKE_N_128), .CK(RCLK_c), .Q(RCKE_c)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(141[9] 144[5]) + defparam RCKE_368.GSR = "ENABLED"; + FD1P3AY nRCS_369 (.D(nRCS_N_132), .SP(RCLK_c_enable_4), .CK(RCLK_c), + .Q(nRCS_c)) /* synthesis lse_init_val=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5]) + defparam nRCS_369.GSR = "ENABLED"; + FD1S3IX nRowColSel_375 (.D(n1368), .CK(RCLK_c), .CD(n2299), .Q(nRowColSel)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5]) + defparam nRowColSel_375.GSR = "ENABLED"; + ORCALUT4 n1_bdd_4_lut (.A(n1), .B(n1627), .C(nRWE_N_178), .D(nRowColSel_N_35), + .Z(nRWE_N_174)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))+!A (C+!(D))) */ ; + defparam n1_bdd_4_lut.init = 16'hf0dd; + ORCALUT4 i2_3_lut_rep_31 (.A(PHI2r3), .B(CmdSubmitted), .C(PHI2r2), + .Z(n2308)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ; + defparam i2_3_lut_rep_31.init = 16'h0808; + ORCALUT4 i1_2_lut_2_lut_4_lut (.A(PHI2r3), .B(CmdSubmitted), .C(PHI2r2), + .D(InitReady), .Z(RCLK_c_enable_24)) /* synthesis lut_function=(!(A (B (C (D))+!B (D))+!A (D))) */ ; + defparam i1_2_lut_2_lut_4_lut.init = 16'h08ff; + CCU2 FS_577_add_4_8 (.A0(FS[6]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[7]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1876), + .COUT1(n1877), .S0(n89), .S1(n88)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577_add_4_8.INIT0 = 16'hfaaa; + defparam FS_577_add_4_8.INIT1 = 16'hfaaa; + defparam FS_577_add_4_8.INJECT1_0 = "NO"; + defparam FS_577_add_4_8.INJECT1_1 = "NO"; + ORCALUT4 i1_4_lut (.A(nRowColSel_N_34), .B(n1), .C(n2304), .D(nRowColSel_N_33), + .Z(n2117)) /* synthesis lut_function=(!(A+(B (C (D))+!B (C+!(D))))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(84[6:11]) + defparam i1_4_lut.init = 16'h0544; + ORCALUT4 i3_4_lut (.A(MAin_c_1), .B(MAin_c_0), .C(CmdEnable), .D(n2290), + .Z(XOR8MEG_N_112)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ; + defparam i3_4_lut.init = 16'h0040; + ORCALUT4 i4_3_lut_4_lut (.A(FS[11]), .B(n2300), .C(FS[6]), .D(n2168), + .Z(n11)) /* synthesis lut_function=((B+(C+!(D)))+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37]) + defparam i4_3_lut_4_lut.init = 16'hfdff; + FD1S3IX S_FSM_i2 (.D(n1135), .CK(RCLK_c), .CD(n2302), .Q(nRowColSel_N_34)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) + defparam S_FSM_i2.GSR = "ENABLED"; + ORCALUT4 i1_4_lut_adj_1 (.A(nRowColSel), .B(n1627), .C(nRowColSel_N_28), + .D(nRowColSel_N_32), .Z(n1368)) /* synthesis lut_function=(A (B+!(C (D)))+!A (B+!(C+!(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) + defparam i1_4_lut_adj_1.init = 16'hcfee; + FD1S3AY nRRAS_370 (.D(n33), .CK(RCLK_c), .Q(nRRAS_c)) /* synthesis lse_init_val=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5]) + defparam nRRAS_370.GSR = "ENABLED"; + ORCALUT4 i1055_3_lut_4_lut (.A(MAin_c_1), .B(n2290), .C(ADSubmitted), + .D(ADSubmitted_N_234), .Z(n1361)) /* synthesis lut_function=(A (B (C+(D))+!B (D))+!A (C+(D))) */ ; + defparam i1055_3_lut_4_lut.init = 16'hffd0; + ORCALUT4 i2_3_lut (.A(FWEr), .B(CASr3), .C(CBR), .Z(nRowColSel_N_28)) /* synthesis lut_function=((B+(C))+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(230[16:37]) + defparam i2_3_lut.init = 16'hfdfd; + BB Dout_pad_7__688 (.I(WRD[7]), .T(n962), .B(RD[7]), .O(n973)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16]) + FD1P3AY nRCAS_371 (.D(nRCAS_N_157), .SP(RCLK_c_enable_4), .CK(RCLK_c), + .Q(nRCAS_c)) /* synthesis lse_init_val=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5]) + defparam nRCAS_371.GSR = "ENABLED"; + FD1P3AY nRWE_372 (.D(nRWE_N_167), .SP(RCLK_c_enable_3), .CK(RCLK_c), + .Q(nRWE_c)) /* synthesis lse_init_val=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5]) + defparam nRWE_372.GSR = "ENABLED"; + FD1S3JX RA10_373 (.D(n2128), .CK(RCLK_c), .PD(nRWE_N_172), .Q(n980)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5]) + defparam RA10_373.GSR = "ENABLED"; + FD1P3AX RCKEEN_374 (.D(RCKEEN_N_115), .SP(RCLK_c_enable_4), .CK(RCLK_c), + .Q(RCKEEN)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5]) + defparam RCKEEN_374.GSR = "ENABLED"; + ORCALUT4 i2_4_lut (.A(n2122), .B(n2295), .C(Din_c_2), .D(n2131), + .Z(C1Submitted_N_225)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ; + defparam i2_4_lut.init = 16'h0008; + FD1S3IX RBA__i1 (.D(CROW_c_0), .CK(nCRAS_N_9), .CD(n2307), .Q(RBA_c_0)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) + defparam RBA__i1.GSR = "ENABLED"; + ORCALUT4 Din_7__I_0_442_i6_2_lut_rep_32 (.A(Din_c_6), .B(Din_c_7), .Z(n2385)) /* synthesis lut_function=(A+(B)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(312[17:31]) + defparam Din_7__I_0_442_i6_2_lut_rep_32.init = 16'heeee; + ORCALUT4 i1248_4_lut (.A(FS[5]), .B(n2308), .C(InitReady), .D(n2119), + .Z(RCLK_c_enable_7)) /* synthesis lut_function=(A (B (C))+!A (B (C+(D))+!B !(C+!(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(83[6:15]) + defparam i1248_4_lut.init = 16'hc5c0; + ORCALUT4 i2_3_lut_4_lut_adj_2 (.A(nRowColSel_N_32), .B(n2299), .C(nRowColSel_N_34), + .D(nRowColSel_N_33), .Z(RCLK_c_enable_4)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) + defparam i2_3_lut_4_lut_adj_2.init = 16'hfffe; + ORCALUT4 i1437_4_lut (.A(UFMSDO_c), .B(Cmdn8MEGEN), .C(FS[10]), .D(n4), + .Z(n8MEGEN_N_94)) /* synthesis lut_function=(A (B ((D)+!C))+!A (B+!((D)+!C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(83[6:15]) + defparam i1437_4_lut.init = 16'hcc5c; + FD1P3AX IS_FSM__i0 (.D(Ready_N_272), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(nRCS_N_135)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) + defparam IS_FSM__i0.GSR = "ENABLED"; + ORCALUT4 i1_2_lut_adj_3 (.A(RASr2), .B(RCKE_c), .Z(nRWE_N_178)) /* synthesis lut_function=(A+!(B)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5]) + defparam i1_2_lut_adj_3.init = 16'hbbbb; + ORCALUT4 i2_4_lut_adj_4 (.A(n2294), .B(FS[10]), .C(n11), .D(n12), + .Z(n2119)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37]) + defparam i2_4_lut_adj_4.init = 16'h0008; + FD1P3JX C1Submitted_379 (.D(n2386), .SP(PHI2_N_114_enable_1), .PD(C1Submitted_N_225), + .CK(PHI2_N_114), .Q(C1Submitted)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5]) + defparam C1Submitted_379.GSR = "ENABLED"; + FD1S3JX nUFMCS_388 (.D(n1348), .CK(RCLK_c), .PD(LEDEN_N_88), .Q(nUFMCS_c)) /* synthesis lse_init_val=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5]) + defparam nUFMCS_388.GSR = "ENABLED"; + ORCALUT4 m1_lut (.Z(n2387)) /* synthesis lut_function=1, syn_instantiated=1 */ ; + defparam m1_lut.init = 16'hffff; + ORCALUT4 i2_4_lut_adj_5 (.A(n2108), .B(MAin_c_1), .C(C1Submitted), + .D(MAin_c_0), .Z(n2098)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ; + defparam i2_4_lut_adj_5.init = 16'h0800; + ORCALUT4 i5_4_lut (.A(FS[9]), .B(FS[4]), .C(FS[8]), .D(FS[7]), .Z(n12)) /* synthesis lut_function=(A+((C+(D))+!B)) */ ; + defparam i5_4_lut.init = 16'hfffb; + FD1S3AX FS_577__i0 (.D(n95), .CK(RCLK_c), .Q(FS[0])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577__i0.GSR = "ENABLED"; + ORCALUT4 i2_3_lut_adj_6 (.A(n2122), .B(ADSubmitted), .C(MAin_c_0), + .Z(n2080)) /* synthesis lut_function=(!((B+(C))+!A)) */ ; + defparam i2_3_lut_adj_6.init = 16'h0202; + ORCALUT4 i1419_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQMH_c)) /* synthesis lut_function=(A+!(B)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(58[17:46]) + defparam i1419_2_lut.init = 16'hbbbb; + ORCALUT4 n50_bdd_4_lut_1911 (.A(n50), .B(RASr2), .C(RCKE_c), .D(nRowColSel_N_35), + .Z(n2242)) /* synthesis lut_function=(!(A (B (D)+!B (C (D)))+!A (B+(C+!(D))))) */ ; + defparam n50_bdd_4_lut_1911.init = 16'h03aa; + ORCALUT4 i1893_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQML_c)) /* synthesis lut_function=(!(A (B))) */ ; + defparam i1893_2_lut.init = 16'h7777; + FD1S3AX Bank_i0 (.D(Din_c_0), .CK(PHI2_c), .Q(Bank[0])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5]) + defparam Bank_i0.GSR = "ENABLED"; + ORCALUT4 i1858_4_lut (.A(FS[1]), .B(FS[0]), .C(FS[2]), .D(FS[3]), + .Z(n2168)) /* synthesis lut_function=(A (B (C (D)))) */ ; + defparam i1858_4_lut.init = 16'h8000; + ORCALUT4 i1_2_lut_3_lut_adj_7 (.A(MAin_c_1), .B(n1285), .C(MAin_c_0), + .Z(n2131)) /* synthesis lut_function=((B+(C))+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(80[15:31]) + defparam i1_2_lut_3_lut_adj_7.init = 16'hfdfd; + ORCALUT4 i22_4_lut (.A(FS[4]), .B(CmdUFMCLK), .C(InitReady), .D(n2076), + .Z(UFMCLK_N_212)) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(83[6:15]) + defparam i22_4_lut.init = 16'hc0ca; + ORCALUT4 i5_4_lut_adj_8 (.A(FS[14]), .B(FS[16]), .C(FS[13]), .D(FS[12]), + .Z(n12_adj_2)) /* synthesis lut_function=(A (B (C (D)))) */ ; + defparam i5_4_lut_adj_8.init = 16'h8000; + ORCALUT4 i1889_4_lut_then_4_lut (.A(n2117), .B(RCKE_c), .C(RASr2), + .D(nRowColSel_N_35), .Z(n2310)) /* synthesis lut_function=(!(A (B+(C+!(D)))+!A (B (D)+!B (C (D))))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(84[6:11]) + defparam i1889_4_lut_then_4_lut.init = 16'h0355; + ORCALUT4 i1889_4_lut_else_4_lut (.A(InitReady), .B(nRCS_N_135), .C(RASr2), + .D(nRowColSel_N_35), .Z(n2309)) /* synthesis lut_function=((B+!(C (D)))+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(84[6:11]) + defparam i1889_4_lut_else_4_lut.init = 16'hdfff; + CCU2 FS_577_add_4_18 (.A0(FS[16]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[17]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1881), + .S0(n79), .S1(n78)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577_add_4_18.INIT0 = 16'hfaaa; + defparam FS_577_add_4_18.INIT1 = 16'hfaaa; + defparam FS_577_add_4_18.INJECT1_0 = "NO"; + defparam FS_577_add_4_18.INJECT1_1 = "NO"; + ORCALUT4 UFMSDO_I_0_1_lut (.A(UFMSDO_c), .Z(UFMSDO_N_74)) /* synthesis lut_function=(!(A)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(378[53:60]) + defparam UFMSDO_I_0_1_lut.init = 16'h5555; + FD1S3IX S_FSM_i3 (.D(n1135), .CK(RCLK_c), .CD(n1377), .Q(nRowColSel_N_33)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) + defparam S_FSM_i3.GSR = "ENABLED"; + ORCALUT4 i1897_2_lut_rep_14_3_lut (.A(FS[11]), .B(n2300), .C(InitReady), + .Z(n2291)) /* synthesis lut_function=(!(A+(B+(C)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37]) + defparam i1897_2_lut_rep_14_3_lut.init = 16'h0101; + ORCALUT4 i1878_2_lut_3_lut_4_lut (.A(FS[11]), .B(n2300), .C(FS[10]), + .D(InitReady), .Z(LEDEN_N_88)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37]) + defparam i1878_2_lut_3_lut_4_lut.init = 16'h0001; + ORCALUT4 i1884_4_lut (.A(MAin_c_0), .B(n2290), .C(n2286), .D(MAin_c_1), + .Z(PHI2_N_114_enable_8)) /* synthesis lut_function=(!(A (B+(C))+!A (B+(C+!(D))))) */ ; + defparam i1884_4_lut.init = 16'h0302; + FD1S3AX PHI2r_349 (.D(PHI2_c), .CK(RCLK_c), .Q(PHI2r)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5]) + defparam PHI2r_349.GSR = "ENABLED"; + ORCALUT4 i2_3_lut_rep_21_4_lut (.A(Din_c_6), .B(Din_c_7), .C(Din_c_5), + .D(Din_c_4), .Z(n2298)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(312[17:31]) + defparam i2_3_lut_rep_21_4_lut.init = 16'hfffe; + ORCALUT4 i1830_2_lut_rep_13 (.A(nFWE_c), .B(n1285), .Z(n2290)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1830_2_lut_rep_13.init = 16'heeee; + PFUMX i1912 (.BLUT(n2243), .ALUT(n2242), .C0(Ready), .Z(n2244)); + FD1S3AX S_FSM_i1 (.D(RASr2_N_63), .CK(RCLK_c), .Q(nRowColSel_N_35)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) + defparam S_FSM_i1.GSR = "ENABLED"; + ORCALUT4 i1886_2_lut (.A(nRowColSel_N_32), .B(RASr2), .Z(n1135)) /* synthesis lut_function=(!(A+!(B))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) + defparam i1886_2_lut.init = 16'h4444; + ORCALUT4 n50_bdd_4_lut (.A(n50), .B(InitReady), .C(RASr2), .D(nRowColSel_N_35), + .Z(n2243)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B (C)))) */ ; + defparam n50_bdd_4_lut.init = 16'h3fbf; + ORCALUT4 i1034_2_lut (.A(ADSubmitted_N_234), .B(C1Submitted_N_225), + .Z(CmdEnable_N_236)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1034_2_lut.init = 16'heeee; + ORCALUT4 i2_3_lut_4_lut_adj_9 (.A(Din_c_6), .B(Din_c_7), .C(XOR8MEG_N_112), + .D(Din_c_4), .Z(PHI2_N_114_enable_6)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(312[17:31]) + defparam i2_3_lut_4_lut_adj_9.init = 16'h1000; + ORCALUT4 i1832_2_lut_rep_19_3_lut (.A(Din_c_6), .B(Din_c_7), .C(Din_c_4), + .Z(n2296)) /* synthesis lut_function=(A+(B+!(C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(312[17:31]) + defparam i1832_2_lut_rep_19_3_lut.init = 16'hefef; + FD1S3IX S_FSM_i4 (.D(n1628), .CK(RCLK_c), .CD(RASr2_N_63), .Q(nRowColSel_N_32)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) + defparam S_FSM_i4.GSR = "ENABLED"; + ORCALUT4 i1424_2_lut_rep_27 (.A(FWEr), .B(CBR), .Z(n2304)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1424_2_lut_rep_27.init = 16'heeee; + ORCALUT4 i2_3_lut_adj_10 (.A(Din_c_3), .B(Din_c_6), .C(Din_c_5), .Z(n2122)) /* synthesis lut_function=(!(A+((C)+!B))) */ ; + defparam i2_3_lut_adj_10.init = 16'h0404; + ORCALUT4 i1429_2_lut_3_lut (.A(FWEr), .B(CBR), .C(RASr2), .Z(RCKEEN_N_126)) /* synthesis lut_function=(!(A (C)+!A (B (C)))) */ ; + defparam i1429_2_lut_3_lut.init = 16'h1f1f; + ORCALUT4 i4_4_lut (.A(FS[14]), .B(FS[13]), .C(FS[12]), .D(FS[15]), + .Z(n10)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37]) + defparam i4_4_lut.init = 16'hfffe; + ORCALUT4 i5_3_lut_rep_23 (.A(FS[16]), .B(n10), .C(FS[17]), .Z(n2300)) /* synthesis lut_function=(A+(B+(C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37]) + defparam i5_3_lut_rep_23.init = 16'hfefe; + ORCALUT4 i1_4_lut_adj_11 (.A(n2244), .B(n2297), .C(n18), .D(Ready), + .Z(n33)) /* synthesis lut_function=(A+(B (C+!(D))+!B (C (D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(84[6:11]) + defparam i1_4_lut_adj_11.init = 16'hfaee; + ORCALUT4 i1_2_lut_rep_16_4_lut (.A(FS[16]), .B(n10), .C(FS[17]), .D(FS[11]), + .Z(n2293)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37]) + defparam i1_2_lut_rep_16_4_lut.init = 16'hfeff; + ORCALUT4 i3_4_lut_adj_12 (.A(CBR), .B(FWEr), .C(CASr2), .D(CASr3), + .Z(n1)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ; + defparam i3_4_lut_adj_12.init = 16'h0040; + ORCALUT4 i1_2_lut_adj_13 (.A(nRowColSel_N_34), .B(nRowColSel_N_33), + .Z(n1627)) /* synthesis lut_function=(A+(B)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) + defparam i1_2_lut_adj_13.init = 16'heeee; + ORCALUT4 i1420_2_lut (.A(nCCAS_c), .B(nFWE_c), .Z(n962)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1420_2_lut.init = 16'heeee; + ORCALUT4 i1_1_lut_rep_29 (.A(nFWE_c), .Z(n2306)) /* synthesis lut_function=(!(A)) */ ; + defparam i1_1_lut_rep_29.init = 16'h5555; + ORCALUT4 Cmdn8MEGEN_I_84_4_lut (.A(Din_c_0), .B(n8MEGEN), .C(Din_c_5), + .D(n2296), .Z(Cmdn8MEGEN_N_248)) /* synthesis lut_function=(A (B (C+(D)))+!A (B+!(C+(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(316[13] 322[7]) + defparam Cmdn8MEGEN_I_84_4_lut.init = 16'hccc5; + ORCALUT4 i1069_1_lut (.A(nRowColSel_N_34), .Z(n1377)) /* synthesis lut_function=(!(A)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) + defparam i1069_1_lut.init = 16'h5555; + ORCALUT4 n2080_bdd_4_lut (.A(n2080), .B(n2098), .C(Din_c_2), .D(n2114), + .Z(n2286)) /* synthesis lut_function=(A (B (D)+!B !(C+!(D)))+!A (B (C (D)))) */ ; + defparam n2080_bdd_4_lut.init = 16'hca00; + ORCALUT4 RASr2_I_0_1_lut (.A(RASr2), .Z(RASr2_N_63)) /* synthesis lut_function=(!(A)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(143[40:46]) + defparam RASr2_I_0_1_lut.init = 16'h5555; + ORCALUT4 i847_2_lut_4_lut (.A(n2385), .B(Din_c_4), .C(Din_c_5), .D(XOR8MEG_N_112), + .Z(PHI2_N_114_enable_2)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(310[8:22]) + defparam i847_2_lut_4_lut.init = 16'h0100; + ORCALUT4 i1_4_lut_adj_14 (.A(n2108), .B(MAin_c_0), .C(n4_adj_1), .D(n2289), + .Z(ADSubmitted_N_234)) /* synthesis lut_function=(!((((D)+!C)+!B)+!A)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(309[7:24]) + defparam i1_4_lut_adj_14.init = 16'h0080; + ORCALUT4 i1_2_lut_adj_15 (.A(nRowColSel_N_33), .B(CASr2), .Z(n11_adj_3)) /* synthesis lut_function=(A+!(B)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(48[6:16]) + defparam i1_2_lut_adj_15.init = 16'hbbbb; + FD1S3AX FS_577__i17 (.D(n78), .CK(RCLK_c), .Q(FS[17])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577__i17.GSR = "ENABLED"; + ORCALUT4 i1_2_lut_3_lut_3_lut (.A(nFWE_c), .B(Din_c_2), .C(n2114), + .Z(n4_adj_1)) /* synthesis lut_function=(!(A+!(B (C)))) */ ; + defparam i1_2_lut_3_lut_3_lut.init = 16'h4040; + FD1S3AX FS_577__i16 (.D(n79), .CK(RCLK_c), .Q(FS[16])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577__i16.GSR = "ENABLED"; + FD1S3AX FS_577__i15 (.D(n80), .CK(RCLK_c), .Q(FS[15])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577__i15.GSR = "ENABLED"; + ORCALUT4 nRWE_I_0_428_4_lut (.A(n2164), .B(nRWE_N_174), .C(Ready), + .D(n2292), .Z(nRWE_N_167)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B+!(C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(232[12] 284[6]) + defparam nRWE_I_0_428_4_lut.init = 16'hcfc5; + ORCALUT4 i1257_3_lut (.A(n1895), .B(CmdUFMSDI), .C(InitReady), .Z(UFMSDI_N_219)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(83[6:15]) + defparam i1257_3_lut.init = 16'hcaca; + ORCALUT4 RCKE_I_0_423_4_lut (.A(RASr), .B(RCKEEN), .C(RASr2), .D(RASr3), + .Z(RCKE_N_128)) /* synthesis lut_function=(A (B+!(C+!(D)))+!A (B (C+(D))+!B !(C+!(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(143[11:55]) + defparam RCKE_I_0_423_4_lut.init = 16'hcfc8; + FD1P3AX InitReady_367 (.D(n2387), .SP(RCLK_c_enable_6), .CK(RCLK_c), + .Q(InitReady)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(134[9] 138[5]) + defparam InitReady_367.GSR = "ENABLED"; + ORCALUT4 i1_2_lut_adj_16 (.A(nRowColSel_N_32), .B(nRowColSel_N_33), + .Z(n1628)) /* synthesis lut_function=(A+(B)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) + defparam i1_2_lut_adj_16.init = 16'heeee; + ORCALUT4 i1854_2_lut (.A(nRCAS_N_161), .B(nRWE_N_173), .Z(n2164)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1854_2_lut.init = 16'heeee; + ORCALUT4 i1_2_lut_rep_17_4_lut (.A(FS[16]), .B(n10), .C(FS[17]), .D(FS[11]), + .Z(n2294)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37]) + defparam i1_2_lut_rep_17_4_lut.init = 16'hfffe; + ORCALUT4 i1881_2_lut_rep_24 (.A(RASr2), .B(InitReady), .Z(n2301)) /* synthesis lut_function=(!(A (B))) */ ; + defparam i1881_2_lut_rep_24.init = 16'h7777; + GSR GSR_INST (.GSR(VCC_net)); + ORCALUT4 i1_2_lut_rep_18_2_lut (.A(nFWE_c), .B(n2114), .Z(n2295)) /* synthesis lut_function=(!(A+!(B))) */ ; + defparam i1_2_lut_rep_18_2_lut.init = 16'h4444; + FD1S3AX FS_577__i14 (.D(n81), .CK(RCLK_c), .Q(FS[14])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577__i14.GSR = "ENABLED"; + ORCALUT4 i2_3_lut_3_lut (.A(InitReady), .B(FS[5]), .C(n2119), .Z(RCLK_c_enable_25)) /* synthesis lut_function=(!(A+!(B (C)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(384[16:26]) + defparam i2_3_lut_3_lut.init = 16'h4040; + ORCALUT4 i2_3_lut_adj_17 (.A(Din_c_6), .B(Din_c_5), .C(Din_c_3), .Z(n2108)) /* synthesis lut_function=(!(A+!(B (C)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(309[7:24]) + defparam i2_3_lut_adj_17.init = 16'h4040; + ORCALUT4 i2_4_lut_adj_18 (.A(FS[6]), .B(n2293), .C(n2103), .D(FS[10]), + .Z(n1895)) /* synthesis lut_function=(!((B+((D)+!C))+!A)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam i2_4_lut_adj_18.init = 16'h0020; + ORCALUT4 i1_4_lut_adj_19 (.A(FS[8]), .B(FS[7]), .C(FS[5]), .D(FS[9]), + .Z(n2103)) /* synthesis lut_function=(!(A+(B (D)+!B !(C (D))))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(339[4] 372[11]) + defparam i1_4_lut_adj_19.init = 16'h1044; + FD1P3AX XOR8MEG_381 (.D(Din_c_0), .SP(PHI2_N_114_enable_2), .CK(PHI2_N_114), + .Q(XOR8MEG)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5]) + defparam XOR8MEG_381.GSR = "ENABLED"; + FD1P3AX n8MEGEN_391 (.D(n8MEGEN_N_94), .SP(RCLK_c_enable_7), .CK(RCLK_c), + .Q(n8MEGEN)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5]) + defparam n8MEGEN_391.GSR = "ENABLED"; + FD1P3AX Ready_377 (.D(n2387), .SP(Ready_N_268), .CK(RCLK_c), .Q(Ready)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5]) + defparam Ready_377.GSR = "ENABLED"; + ORCALUT4 MAin_9__I_0_400_i2_3_lut (.A(RowA[1]), .B(MAin_c_1), .C(nRowColSel), + .Z(RA_c_1)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54]) + defparam MAin_9__I_0_400_i2_3_lut.init = 16'hcaca; + FD1P3AX CmdUFMCLK_386 (.D(Din_c_1), .SP(PHI2_N_114_enable_7), .CK(PHI2_N_114), + .Q(CmdUFMCLK)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5]) + defparam CmdUFMCLK_386.GSR = "ENABLED"; + FD1P3AX CmdUFMSDI_387 (.D(Din_c_0), .SP(PHI2_N_114_enable_7), .CK(PHI2_N_114), + .Q(CmdUFMSDI)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5]) + defparam CmdUFMSDI_387.GSR = "ENABLED"; + FD1P3AX Cmdn8MEGEN_383 (.D(Cmdn8MEGEN_N_248), .SP(PHI2_N_114_enable_6), + .CK(PHI2_N_114), .Q(Cmdn8MEGEN)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5]) + defparam Cmdn8MEGEN_383.GSR = "ENABLED"; + FD1P3AX CmdSubmitted_384 (.D(n2387), .SP(PHI2_N_114_enable_6), .CK(PHI2_N_114), + .Q(CmdSubmitted)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5]) + defparam CmdSubmitted_384.GSR = "ENABLED"; + CCU2 FS_577_add_4_6 (.A0(FS[4]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[5]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1875), + .COUT1(n1876), .S0(n91), .S1(n90)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577_add_4_6.INIT0 = 16'hfaaa; + defparam FS_577_add_4_6.INIT1 = 16'hfaaa; + defparam FS_577_add_4_6.INJECT1_0 = "NO"; + defparam FS_577_add_4_6.INJECT1_1 = "NO"; + FD1P3AX CmdUFMCS_385 (.D(Din_c_2), .SP(PHI2_N_114_enable_7), .CK(PHI2_N_114), + .Q(CmdUFMCS)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5]) + defparam CmdUFMCS_385.GSR = "ENABLED"; + FD1S3AX FS_577__i13 (.D(n82), .CK(RCLK_c), .Q(FS[13])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577__i13.GSR = "ENABLED"; + ORCALUT4 i1875_2_lut (.A(nCRAS_c), .B(LEDEN), .Z(LED_N_90)) /* synthesis lut_function=(A+!(B)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(13[15:34]) + defparam i1875_2_lut.init = 16'hbbbb; + FD1S3AX FS_577__i12 (.D(n83), .CK(RCLK_c), .Q(FS[12])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577__i12.GSR = "ENABLED"; + PFUMX RCKEEN_I_0_419 (.BLUT(RCKEEN_N_117), .ALUT(RCKEEN_N_126), .C0(nRowColSel_N_35), + .Z(RCKEEN_N_116)); + ORCALUT4 i1856_4_lut (.A(Bank[0]), .B(Bank[5]), .C(MAin_c_2), .D(Bank[6]), + .Z(n2166)) /* synthesis lut_function=(A (B (C (D)))) */ ; + defparam i1856_4_lut.init = 16'h8000; + FD1S3AX FS_577__i11 (.D(n84), .CK(RCLK_c), .Q(FS[11])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577__i11.GSR = "ENABLED"; + ORCALUT4 i1844_2_lut (.A(Bank[7]), .B(MAin_c_4), .Z(n2154)) /* synthesis lut_function=(A (B)) */ ; + defparam i1844_2_lut.init = 16'h8888; + ORCALUT4 RA11_I_53_3_lut (.A(Din_c_6), .B(XOR8MEG), .C(n8MEGEN), .Z(RA11_N_180)) /* synthesis lut_function=(A (B (C)+!B !(C))+!A (B)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(99[22:51]) + defparam RA11_I_53_3_lut.init = 16'hc6c6; + ORCALUT4 Ready_bdd_3_lut_1922 (.A(nRCAS_N_161), .B(nRCS_N_135), .C(InitReady), + .Z(n2248)) /* synthesis lut_function=(A+(B+!(C))) */ ; + defparam Ready_bdd_3_lut_1922.init = 16'hefef; + FD1P3IX UFMSDI_390 (.D(UFMSDI_N_219), .SP(RCLK_c_enable_24), .CD(n2291), + .CK(RCLK_c), .Q(UFMSDI_c)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5]) + defparam UFMSDI_390.GSR = "ENABLED"; + ORCALUT4 MAin_9__I_0_400_i10_3_lut (.A(RowA[9]), .B(MAin_c_9), .C(nRowColSel), + .Z(RA_c_9)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54]) + defparam MAin_9__I_0_400_i10_3_lut.init = 16'hcaca; + ORCALUT4 i604_1_lut_rep_30 (.A(Ready), .Z(n2307)) /* synthesis lut_function=(!(A)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5]) + defparam i604_1_lut_rep_30.init = 16'h5555; + FD1S3AX FS_577__i10 (.D(n85), .CK(RCLK_c), .Q(FS[10])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577__i10.GSR = "ENABLED"; + FD1S3AX FS_577__i9 (.D(n86), .CK(RCLK_c), .Q(FS[9])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577__i9.GSR = "ENABLED"; + FD1S3AX FS_577__i8 (.D(n87), .CK(RCLK_c), .Q(FS[8])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577__i8.GSR = "ENABLED"; + FD1S3AX FS_577__i7 (.D(n88), .CK(RCLK_c), .Q(FS[7])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577__i7.GSR = "ENABLED"; + FD1S3AX FS_577__i6 (.D(n89), .CK(RCLK_c), .Q(FS[6])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577__i6.GSR = "ENABLED"; + FD1S3AX FS_577__i5 (.D(n90), .CK(RCLK_c), .Q(FS[5])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577__i5.GSR = "ENABLED"; + FD1S3AX FS_577__i4 (.D(n91), .CK(RCLK_c), .Q(FS[4])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577__i4.GSR = "ENABLED"; + FD1S3AX FS_577__i3 (.D(n92), .CK(RCLK_c), .Q(FS[3])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577__i3.GSR = "ENABLED"; + FD1S3AX FS_577__i2 (.D(n93), .CK(RCLK_c), .Q(FS[2])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577__i2.GSR = "ENABLED"; + FD1S3AX FS_577__i1 (.D(n94), .CK(RCLK_c), .Q(FS[1])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577__i1.GSR = "ENABLED"; + FD1P3AX IS_FSM__i15 (.D(n699), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(Ready_N_272)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) + defparam IS_FSM__i15.GSR = "ENABLED"; + FD1P3AX IS_FSM__i14 (.D(n700), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n699)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) + defparam IS_FSM__i14.GSR = "ENABLED"; + FD1P3AX IS_FSM__i13 (.D(n701), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n700)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) + defparam IS_FSM__i13.GSR = "ENABLED"; + FD1P3AX IS_FSM__i12 (.D(n702), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n701)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) + defparam IS_FSM__i12.GSR = "ENABLED"; + FD1P3AX IS_FSM__i11 (.D(n703), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n702)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) + defparam IS_FSM__i11.GSR = "ENABLED"; + FD1P3AX IS_FSM__i10 (.D(nRWE_N_173), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n703)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) + defparam IS_FSM__i10.GSR = "ENABLED"; + FD1P3AX IS_FSM__i9 (.D(n705), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(nRWE_N_173)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) + defparam IS_FSM__i9.GSR = "ENABLED"; + FD1P3AX IS_FSM__i8 (.D(n706), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n705)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) + defparam IS_FSM__i8.GSR = "ENABLED"; + FD1P3AX IS_FSM__i7 (.D(n707), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n706)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) + defparam IS_FSM__i7.GSR = "ENABLED"; + FD1P3AX IS_FSM__i6 (.D(n708), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n707)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) + defparam IS_FSM__i6.GSR = "ENABLED"; + FD1P3AX IS_FSM__i5 (.D(n709), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n708)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) + defparam IS_FSM__i5.GSR = "ENABLED"; + FD1P3AX IS_FSM__i4 (.D(n710), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n709)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) + defparam IS_FSM__i4.GSR = "ENABLED"; + FD1P3AX IS_FSM__i3 (.D(n711), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n710)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) + defparam IS_FSM__i3.GSR = "ENABLED"; + FD1P3AX IS_FSM__i2 (.D(nRCAS_N_161), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n711)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) + defparam IS_FSM__i2.GSR = "ENABLED"; + FD1P3AX IS_FSM__i1 (.D(nRCS_N_135), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(nRCAS_N_161)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) + defparam IS_FSM__i1.GSR = "ENABLED"; + FD1S3IX RBA__i2 (.D(CROW_c_1), .CK(nCRAS_N_9), .CD(n2307), .Q(RBA_c_1)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) + defparam RBA__i2.GSR = "ENABLED"; + FD1S3AX WRD_i7 (.D(Din_c_7), .CK(nCCAS_N_3), .Q(WRD[7])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5]) + defparam WRD_i7.GSR = "ENABLED"; + FD1S3AX WRD_i6 (.D(Din_c_6), .CK(nCCAS_N_3), .Q(WRD[6])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5]) + defparam WRD_i6.GSR = "ENABLED"; + FD1S3AX WRD_i5 (.D(Din_c_5), .CK(nCCAS_N_3), .Q(WRD[5])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5]) + defparam WRD_i5.GSR = "ENABLED"; + FD1S3AX WRD_i4 (.D(Din_c_4), .CK(nCCAS_N_3), .Q(WRD[4])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5]) + defparam WRD_i4.GSR = "ENABLED"; + FD1S3AX WRD_i3 (.D(Din_c_3), .CK(nCCAS_N_3), .Q(WRD[3])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5]) + defparam WRD_i3.GSR = "ENABLED"; + FD1S3AX WRD_i2 (.D(Din_c_2), .CK(nCCAS_N_3), .Q(WRD[2])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5]) + defparam WRD_i2.GSR = "ENABLED"; + FD1S3AX WRD_i1 (.D(Din_c_1), .CK(nCCAS_N_3), .Q(WRD[1])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5]) + defparam WRD_i1.GSR = "ENABLED"; + FD1S3JX RowA_i9 (.D(MAin_c_9), .CK(nCRAS_N_9), .PD(n2307), .Q(RowA[9])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) + defparam RowA_i9.GSR = "ENABLED"; + FD1S3IX RowA_i8 (.D(MAin_c_8), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[8])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) + defparam RowA_i8.GSR = "ENABLED"; + FD1S3IX RowA_i7 (.D(MAin_c_7), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[7])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) + defparam RowA_i7.GSR = "ENABLED"; + FD1S3IX RowA_i6 (.D(MAin_c_6), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[6])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) + defparam RowA_i6.GSR = "ENABLED"; + FD1S3JX RowA_i5 (.D(MAin_c_5), .CK(nCRAS_N_9), .PD(n2307), .Q(RowA[5])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) + defparam RowA_i5.GSR = "ENABLED"; + FD1S3IX RowA_i4 (.D(MAin_c_4), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[4])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) + defparam RowA_i4.GSR = "ENABLED"; + FD1S3IX RowA_i3 (.D(MAin_c_3), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[3])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) + defparam RowA_i3.GSR = "ENABLED"; + FD1S3IX RowA_i2 (.D(MAin_c_2), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[2])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) + defparam RowA_i2.GSR = "ENABLED"; + FD1S3IX RowA_i1 (.D(MAin_c_1), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[1])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) + defparam RowA_i1.GSR = "ENABLED"; + FD1S3AX Bank_i7 (.D(Din_c_7), .CK(PHI2_c), .Q(Bank[7])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5]) + defparam Bank_i7.GSR = "ENABLED"; + ORCALUT4 i1_2_lut_rep_12 (.A(MAin_c_1), .B(n1285), .Z(n2289)) /* synthesis lut_function=((B)+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(80[15:31]) + defparam i1_2_lut_rep_12.init = 16'hdddd; + ORCALUT4 i1_2_lut_rep_15_3_lut_4_lut_4_lut (.A(nRowColSel_N_35), .B(nRCS_N_135), + .C(InitReady), .D(RASr2), .Z(n2292)) /* synthesis lut_function=((B+!(C (D)))+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) + defparam i1_2_lut_rep_15_3_lut_4_lut_4_lut.init = 16'hdfff; + ORCALUT4 i1_2_lut_4_lut_4_lut (.A(Ready), .B(nRowColSel_N_35), .C(RASr2), + .D(InitReady), .Z(RCLK_c_enable_23)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5]) + defparam i1_2_lut_4_lut_4_lut.init = 16'h4000; + FD1S3AX Bank_i6 (.D(Din_c_6), .CK(PHI2_c), .Q(Bank[6])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5]) + defparam Bank_i6.GSR = "ENABLED"; + FD1S3AX Bank_i5 (.D(Din_c_5), .CK(PHI2_c), .Q(Bank[5])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5]) + defparam Bank_i5.GSR = "ENABLED"; + FD1S3AX Bank_i4 (.D(Din_c_4), .CK(PHI2_c), .Q(Bank[4])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5]) + defparam Bank_i4.GSR = "ENABLED"; + FD1S3AX Bank_i3 (.D(Din_c_3), .CK(PHI2_c), .Q(Bank[3])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5]) + defparam Bank_i3.GSR = "ENABLED"; + FD1S3AX Bank_i2 (.D(Din_c_2), .CK(PHI2_c), .Q(Bank[2])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5]) + defparam Bank_i2.GSR = "ENABLED"; + FD1S3AX Bank_i1 (.D(Din_c_1), .CK(PHI2_c), .Q(Bank[1])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5]) + defparam Bank_i1.GSR = "ENABLED"; + BB Dout_pad_6__689 (.I(WRD[6]), .T(n962), .B(RD[6]), .O(n974)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16]) + BB Dout_pad_5__690 (.I(WRD[5]), .T(n962), .B(RD[5]), .O(n975)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16]) + BB Dout_pad_4__691 (.I(WRD[4]), .T(n962), .B(RD[4]), .O(n976)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16]) + BB Dout_pad_3__692 (.I(WRD[3]), .T(n962), .B(RD[3]), .O(n977)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16]) + BB Dout_pad_2__693 (.I(WRD[2]), .T(n962), .B(RD[2]), .O(n978)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16]) + BB Dout_pad_1__694 (.I(WRD[1]), .T(n962), .B(RD[1]), .O(n979)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16]) + ORCALUT4 nRWE_I_49_1_lut (.A(nRWE_N_173), .Z(nRWE_N_172)) /* synthesis lut_function=(!(A)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(255[14] 262[8]) + defparam nRWE_I_49_1_lut.init = 16'h5555; + BB Dout_pad_0__695 (.I(WRD[0]), .T(n962), .B(RD[0]), .O(Dout_c)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16]) + OB Dout_pad_7 (.I(n973), .O(Dout[7])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19]) + OB Dout_pad_6 (.I(n974), .O(Dout[6])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19]) + OB Dout_pad_5 (.I(n975), .O(Dout[5])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19]) + OB Dout_pad_4 (.I(n976), .O(Dout[4])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19]) + OB Dout_pad_3 (.I(n977), .O(Dout[3])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19]) + OB Dout_pad_2 (.I(n978), .O(Dout[2])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19]) + OB Dout_pad_1 (.I(n979), .O(Dout[1])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19]) + OB Dout_pad_0 (.I(Dout_c), .O(Dout[0])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19]) + OB LED_pad (.I(LED_N_90), .O(LED)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(12[9:12]) + OB RBA_pad_1 (.I(RBA_c_1), .O(RBA[1])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(47[19:22]) + OB RBA_pad_0 (.I(RBA_c_0), .O(RBA[0])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(47[19:22]) + OB RA_pad_11 (.I(RA_c), .O(RA[11])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18]) + OB RA_pad_10 (.I(n980), .O(RA[10])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18]) + OB RA_pad_9 (.I(RA_c_9), .O(RA[9])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18]) + OB RA_pad_8 (.I(RA_c_8), .O(RA[8])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18]) + OB RA_pad_7 (.I(RA_c_7), .O(RA[7])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18]) + OB RA_pad_6 (.I(RA_c_6), .O(RA[6])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18]) + OB RA_pad_5 (.I(RA_c_5), .O(RA[5])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18]) + OB RA_pad_4 (.I(RA_c_4), .O(RA[4])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18]) + OB RA_pad_3 (.I(RA_c_3), .O(RA[3])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18]) + OB RA_pad_2 (.I(RA_c_2), .O(RA[2])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18]) + OB RA_pad_1 (.I(RA_c_1), .O(RA[1])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18]) + OB RA_pad_0 (.I(RA_c_0), .O(RA[0])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18]) + OB nRCS_pad (.I(nRCS_c), .O(nRCS)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[13:17]) + OB RCKE_pad (.I(RCKE_c), .O(RCKE)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(45[13:17]) + OB nRWE_pad (.I(nRWE_c), .O(nRWE)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[45:49]) + OB nRRAS_pad (.I(nRRAS_c), .O(nRRAS)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[23:28]) + OB nRCAS_pad (.I(nRCAS_c), .O(nRCAS)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[34:39]) + OB RDQMH_pad (.I(RDQMH_c), .O(RDQMH)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(56[16:21]) + OB RDQML_pad (.I(RDQML_c), .O(RDQML)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(56[9:14]) + OB nUFMCS_pad (.I(nUFMCS_c), .O(nUFMCS)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(63[13:19]) + OB UFMCLK_pad (.I(UFMCLK_c), .O(UFMCLK)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(64[13:19]) + OB UFMSDI_pad (.I(UFMSDI_c), .O(UFMSDI)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(65[13:19]) + IB PHI2_pad (.I(PHI2), .O(PHI2_c)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(8[8:12]) + IB MAin_pad_9 (.I(MAin[9]), .O(MAin_c_9)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18]) + IB MAin_pad_8 (.I(MAin[8]), .O(MAin_c_8)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18]) + IB MAin_pad_7 (.I(MAin[7]), .O(MAin_c_7)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18]) + IB MAin_pad_6 (.I(MAin[6]), .O(MAin_c_6)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18]) + IB MAin_pad_5 (.I(MAin[5]), .O(MAin_c_5)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18]) + IB MAin_pad_4 (.I(MAin[4]), .O(MAin_c_4)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18]) + IB MAin_pad_3 (.I(MAin[3]), .O(MAin_c_3)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18]) + IB MAin_pad_2 (.I(MAin[2]), .O(MAin_c_2)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18]) + IB MAin_pad_1 (.I(MAin[1]), .O(MAin_c_1)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18]) + IB MAin_pad_0 (.I(MAin[0]), .O(MAin_c_0)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18]) + IB CROW_pad_1 (.I(CROW[1]), .O(CROW_c_1)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(34[14:18]) + IB CROW_pad_0 (.I(CROW[0]), .O(CROW_c_0)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(34[14:18]) + IB Din_pad_7 (.I(Din[7]), .O(Din_c_7)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17]) + IB Din_pad_6 (.I(Din[6]), .O(Din_c_6)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17]) + IB Din_pad_5 (.I(Din[5]), .O(Din_c_5)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17]) + IB Din_pad_4 (.I(Din[4]), .O(Din_c_4)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17]) + IB Din_pad_3 (.I(Din[3]), .O(Din_c_3)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17]) + IB Din_pad_2 (.I(Din[2]), .O(Din_c_2)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17]) + IB Din_pad_1 (.I(Din[1]), .O(Din_c_1)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17]) + IB Din_pad_0 (.I(Din[0]), .O(Din_c_0)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17]) + IB nCCAS_pad (.I(nCCAS), .O(nCCAS_c)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[8:13]) + IB nCRAS_pad (.I(nCRAS), .O(nCRAS_c)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[15:20]) + IB nFWE_pad (.I(nFWE), .O(nFWE_c)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(36[8:12]) + IB RCLK_pad (.I(RCLK), .O(RCLK_c)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(41[8:12]) + IB UFMSDO_pad (.I(UFMSDO), .O(UFMSDO_c)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(66[8:14]) + ORCALUT4 MAin_9__I_0_400_i9_3_lut (.A(RowA[8]), .B(MAin_c_8), .C(nRowColSel), + .Z(RA_c_8)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54]) + defparam MAin_9__I_0_400_i9_3_lut.init = 16'hcaca; + CCU2 FS_577_add_4_4 (.A0(FS[2]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[3]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1874), + .COUT1(n1875), .S0(n93), .S1(n92)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577_add_4_4.INIT0 = 16'hfaaa; + defparam FS_577_add_4_4.INIT1 = 16'hfaaa; + defparam FS_577_add_4_4.INJECT1_0 = "NO"; + defparam FS_577_add_4_4.INJECT1_1 = "NO"; + ORCALUT4 i1_2_lut_3_lut_4_lut_4_lut (.A(Ready), .B(nRowColSel_N_32), + .C(n1627), .D(nRowColSel_N_35), .Z(RCLK_c_enable_3)) /* synthesis lut_function=((B+(C+(D)))+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5]) + defparam i1_2_lut_3_lut_4_lut_4_lut.init = 16'hfffd; + FD1P3IX UFMCLK_389 (.D(UFMCLK_N_212), .SP(RCLK_c_enable_24), .CD(n2291), + .CK(RCLK_c), .Q(UFMCLK_c)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5]) + defparam UFMCLK_389.GSR = "ENABLED"; + ORCALUT4 i2_2_lut_rep_22_2_lut (.A(Ready), .B(nRowColSel_N_35), .Z(n2299)) /* synthesis lut_function=((B)+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5]) + defparam i2_2_lut_rep_22_2_lut.init = 16'hdddd; + ORCALUT4 i2_3_lut_4_lut_adj_20 (.A(n2297), .B(n2301), .C(nRCAS_N_161), + .D(Ready), .Z(n2128)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) + defparam i2_3_lut_4_lut_adj_20.init = 16'hfffe; + ORCALUT4 i2_3_lut_adj_21 (.A(nRowColSel_N_33), .B(nRRAS_c), .C(nRowColSel_N_32), + .Z(n50)) /* synthesis lut_function=(A+(B+(C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) + defparam i2_3_lut_adj_21.init = 16'hfefe; + ORCALUT4 MAin_9__I_0_400_i8_3_lut (.A(RowA[7]), .B(MAin_c_7), .C(nRowColSel), + .Z(RA_c_7)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54]) + defparam MAin_9__I_0_400_i8_3_lut.init = 16'hcaca; + ORCALUT4 Ready_bdd_4_lut (.A(Ready), .B(n2117), .C(n2287), .D(nRowColSel_N_35), + .Z(nRCAS_N_157)) /* synthesis lut_function=(A (B (C (D))+!B (C+!(D)))+!A (C+!(D))) */ ; + defparam Ready_bdd_4_lut.init = 16'hf077; + ORCALUT4 i1366_3_lut (.A(InitReady), .B(RCKEEN_N_116), .C(Ready), + .Z(RCKEEN_N_115)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(84[6:11]) + defparam i1366_3_lut.init = 16'hcaca; + ORCALUT4 i6_4_lut (.A(FS[15]), .B(n12_adj_2), .C(FS[11]), .D(FS[17]), + .Z(n2076)) /* synthesis lut_function=(A (B (C (D)))) */ ; + defparam i6_4_lut.init = 16'h8000; + ORCALUT4 i1_4_lut_4_lut (.A(CBR), .B(n11_adj_3), .C(FWEr), .D(nRowColSel_N_34), + .Z(RCKEEN_N_117)) /* synthesis lut_function=(!(A+!(B (C+(D))+!B (D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(214[26:30]) + defparam i1_4_lut_4_lut.init = 16'h5540; + ORCALUT4 i1_2_lut_rep_11_3_lut (.A(nFWE_c), .B(n1285), .C(MAin_c_1), + .Z(PHI2_N_114_enable_1)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ; + defparam i1_2_lut_rep_11_3_lut.init = 16'h1010; + CCU2 FS_577_add_4_2 (.A0(FS[0]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[1]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(GND_net), + .COUT1(n1874), .S0(n95), .S1(n94)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577_add_4_2.INIT0 = 16'h0555; + defparam FS_577_add_4_2.INIT1 = 16'hfaaa; + defparam FS_577_add_4_2.INJECT1_0 = "NO"; + defparam FS_577_add_4_2.INJECT1_1 = "NO"; + ORCALUT4 i3_4_lut_adj_22 (.A(Din_c_0), .B(Din_c_1), .C(Din_c_4), .D(Din_c_7), + .Z(n2114)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ; + defparam i3_4_lut_adj_22.init = 16'h0200; + ORCALUT4 Ready_bdd_4_lut_1960 (.A(nRowColSel_N_32), .B(RASr2), .C(Ready_N_272), + .D(InitReady), .Z(n2245)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ; + defparam Ready_bdd_4_lut_1960.init = 16'h2000; + ORCALUT4 n2245_bdd_2_lut (.A(n2245), .B(Ready), .Z(Ready_N_268)) /* synthesis lut_function=(A+(B)) */ ; + defparam n2245_bdd_2_lut.init = 16'heeee; + ORCALUT4 n2248_bdd_4_lut_4_lut (.A(CBR), .B(RASr2), .C(Ready), .D(n2248), + .Z(n2287)) /* synthesis lut_function=(!(A (B (C+!(D)))+!A !((C+(D))+!B))) */ ; + defparam n2248_bdd_4_lut_4_lut.init = 16'h7f73; + FD1P3AX LEDEN_392 (.D(UFMSDO_N_74), .SP(RCLK_c_enable_25), .CK(RCLK_c), + .Q(LEDEN)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5]) + defparam LEDEN_392.GSR = "ENABLED"; + ORCALUT4 MAin_9__I_0_400_i7_3_lut (.A(RowA[6]), .B(MAin_c_6), .C(nRowColSel), + .Z(RA_c_6)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54]) + defparam MAin_9__I_0_400_i7_3_lut.init = 16'hcaca; + ORCALUT4 MAin_9__I_0_400_i6_3_lut (.A(RowA[5]), .B(MAin_c_5), .C(nRowColSel), + .Z(RA_c_5)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54]) + defparam MAin_9__I_0_400_i6_3_lut.init = 16'hcaca; + CCU2 FS_577_add_4_12 (.A0(FS[10]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[11]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1878), + .COUT1(n1879), .S0(n85), .S1(n84)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577_add_4_12.INIT0 = 16'hfaaa; + defparam FS_577_add_4_12.INIT1 = 16'hfaaa; + defparam FS_577_add_4_12.INJECT1_0 = "NO"; + defparam FS_577_add_4_12.INJECT1_1 = "NO"; + FD1P3AX CmdEnable_378 (.D(CmdEnable_N_236), .SP(PHI2_N_114_enable_8), + .CK(PHI2_N_114), .Q(CmdEnable)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5]) + defparam CmdEnable_378.GSR = "ENABLED"; + CCU2 FS_577_add_4_16 (.A0(FS[14]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[15]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1880), + .COUT1(n1881), .S0(n81), .S1(n80)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577_add_4_16.INIT0 = 16'hfaaa; + defparam FS_577_add_4_16.INIT1 = 16'hfaaa; + defparam FS_577_add_4_16.INJECT1_0 = "NO"; + defparam FS_577_add_4_16.INJECT1_1 = "NO"; + CCU2 FS_577_add_4_14 (.A0(FS[12]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[13]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1879), + .COUT1(n1880), .S0(n83), .S1(n82)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) + defparam FS_577_add_4_14.INIT0 = 16'hfaaa; + defparam FS_577_add_4_14.INIT1 = 16'hfaaa; + defparam FS_577_add_4_14.INJECT1_0 = "NO"; + defparam FS_577_add_4_14.INJECT1_1 = "NO"; + ORCALUT4 MAin_9__I_0_400_i3_3_lut (.A(RowA[2]), .B(MAin_c_2), .C(nRowColSel), + .Z(RA_c_2)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54]) + defparam MAin_9__I_0_400_i3_3_lut.init = 16'hcaca; + ORCALUT4 i1485_3_lut (.A(n2076), .B(n1369), .C(InitReady), .Z(n1348)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(83[6:15]) + defparam i1485_3_lut.init = 16'hcaca; + ORCALUT4 i1_2_lut_2_lut (.A(nRowColSel_N_35), .B(nRowColSel_N_34), .Z(n18)) /* synthesis lut_function=(!(A+!(B))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) + defparam i1_2_lut_2_lut.init = 16'h4444; + ORCALUT4 i1_2_lut_rep_20_2_lut (.A(nRowColSel_N_35), .B(nRCS_N_135), + .Z(n2297)) /* synthesis lut_function=((B)+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) + defparam i1_2_lut_rep_20_2_lut.init = 16'hdddd; + ORCALUT4 i1062_3_lut (.A(nUFMCS_c), .B(CmdUFMCS), .C(n2308), .Z(n1369)) /* synthesis lut_function=(!(A (B (C))+!A (B+!(C)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5]) + defparam i1062_3_lut.init = 16'h3a3a; + ORCALUT4 MAin_9__I_0_400_i4_3_lut (.A(RowA[3]), .B(MAin_c_3), .C(nRowColSel), + .Z(RA_c_3)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54]) + defparam MAin_9__I_0_400_i4_3_lut.init = 16'hcaca; + ORCALUT4 MAin_9__I_0_400_i1_3_lut (.A(RowA[0]), .B(MAin_c_0), .C(nRowColSel), + .Z(RA_c_0)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54]) + defparam MAin_9__I_0_400_i1_3_lut.init = 16'hcaca; + INV i1961 (.A(nCRAS_c), .Z(nCRAS_N_9)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[15:20]) + INV i1962 (.A(PHI2_c), .Z(PHI2_N_114)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(8[8:12]) + VLO i1 (.Z(GND_net)); + TSALL TSALL_INST (.TSALL(GND_net)); + ORCALUT4 i1070_1_lut_rep_25 (.A(nRowColSel_N_35), .Z(n2302)) /* synthesis lut_function=(!(A)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) + defparam i1070_1_lut_rep_25.init = 16'h5555; + PUR PUR_INST (.PUR(VCC_net)); + defparam PUR_INST.RST_PULSE = 1; + ORCALUT4 i13_4_lut (.A(Bank[3]), .B(n26), .C(n2170), .D(MAin_c_5), + .Z(n1285)) /* synthesis lut_function=((B+!(C (D)))+!A) */ ; + defparam i13_4_lut.init = 16'hdfff; + ORCALUT4 i12_4_lut (.A(Bank[2]), .B(n2166), .C(n2154), .D(MAin_c_6), + .Z(n26)) /* synthesis lut_function=(A+!(B (C (D)))) */ ; + defparam i12_4_lut.init = 16'hbfff; + ORCALUT4 i1860_4_lut (.A(MAin_c_7), .B(MAin_c_3), .C(Bank[4]), .D(Bank[1]), + .Z(n2170)) /* synthesis lut_function=(A (B (C (D)))) */ ; + defparam i1860_4_lut.init = 16'h8000; + ORCALUT4 m0_lut (.Z(n2386)) /* synthesis lut_function=0, syn_instantiated=1 */ ; + defparam m0_lut.init = 16'h0000; + PFUMX i1934 (.BLUT(n2309), .ALUT(n2310), .C0(Ready), .Z(nRCS_N_132)); + +endmodule +// +// Verilog Description of module TSALL +// module not written out since it is a black-box. +// + +// +// Verilog Description of module PUR +// module not written out since it is a black-box. +// + diff --git a/CPLD/LCMXO/LCMXO256C/impl1/Untitled.tpf.prf b/CPLD/LCMXO/LCMXO256C/impl1/Untitled.tpf.prf new file mode 100644 index 0000000..420deec --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/Untitled.tpf.prf @@ -0,0 +1,89 @@ +PERIOD NET "PHI2_c" 350.000000 ns ; +PERIOD NET "nCCAS_c" 350.000000 ns ; +PERIOD NET "nCRAS_c" 350.000000 ns ; +PERIOD NET "RCLK_c" 15.000000 ns ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +OUTPUT PORT "RD[7]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[0]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[1]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[2]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[3]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[4]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[5]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[6]" LOAD 20.000000 pF ; +OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ; +OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ; +OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ; +OUTPUT PORT "nRWE" LOAD 10.000000 pF ; +OUTPUT PORT "nRCAS" LOAD 10.000000 pF ; +OUTPUT PORT "nRCS" LOAD 10.000000 pF ; +OUTPUT PORT "nRRAS" LOAD 10.000000 pF ; +OUTPUT PORT "RDQML" LOAD 10.000000 pF ; +OUTPUT PORT "RDQMH" LOAD 10.000000 pF ; +OUTPUT PORT "RCKE" LOAD 10.000000 pF ; +OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ; +OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[11]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[10]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[9]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[8]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[7]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[6]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[5]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[4]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[3]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[2]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[1]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[0]" LOAD 10.000000 pF ; +OUTPUT PORT "LED" LOAD 25.000000 pF ; +OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ; +VOLTAGE 3.300 V; +VCCIO_DERATE BANK 0 PERCENT -5; +VCCIO_DERATE PERCENT -5; +VCCIO_DERATE BANK 1 PERCENT -5; +CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; +COMMERCIAL ; \ No newline at end of file diff --git a/CPLD/LCMXO/LCMXO256C/impl1/Untitled.tpf.prf_cdmp b/CPLD/LCMXO/LCMXO256C/impl1/Untitled.tpf.prf_cdmp new file mode 100644 index 0000000..fc768e6 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/Untitled.tpf.prf_cdmp @@ -0,0 +1,155 @@ +VOLTAGE 3.300 V; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +IOBUF PORT "RD[7]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RD[6]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RD[5]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RD[4]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RD[3]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RD[2]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RD[1]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RD[0]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Dout[7]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Dout[6]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Dout[5]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Dout[4]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Dout[3]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Dout[2]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Dout[1]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Dout[0]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RBA[1]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RBA[0]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[11]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[10]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[9]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[8]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[7]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[6]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[5]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[4]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[3]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[2]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[1]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[0]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "nRCS" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RCKE" IO_TYPE=LVCMOS25 ; +IOBUF PORT "nRWE" IO_TYPE=LVCMOS25 ; +IOBUF PORT "nRRAS" IO_TYPE=LVCMOS25 ; +IOBUF PORT "nRCAS" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RDQMH" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RDQML" IO_TYPE=LVCMOS25 ; +IOBUF PORT "nUFMCS" IO_TYPE=LVCMOS25 ; +IOBUF PORT "UFMCLK" IO_TYPE=LVCMOS25 ; +IOBUF PORT "UFMSDI" IO_TYPE=LVCMOS25 ; +IOBUF PORT "PHI2" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[9]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[8]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[7]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[6]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[5]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[4]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[3]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[2]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[1]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[0]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "CROW[1]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "CROW[0]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Din[7]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Din[6]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Din[5]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Din[4]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Din[3]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Din[2]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Din[1]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Din[0]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "nCCAS" IO_TYPE=LVCMOS25 ; +IOBUF PORT "nCRAS" IO_TYPE=LVCMOS25 ; +IOBUF PORT "nFWE" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RCLK" IO_TYPE=LVCMOS25 ; +IOBUF PORT "UFMSDO" IO_TYPE=LVCMOS25 ; +PERIOD NET "PHI2_c" 350.000000 ns ; +PERIOD NET "nCCAS_c" 350.000000 ns ; +PERIOD NET "nCRAS_c" 350.000000 ns ; +PERIOD NET "RCLK_c" 15.000000 ns ; +CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; +OUTPUT PORT "RD[7]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[0]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[1]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[2]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[3]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[4]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[5]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[6]" LOAD 20.000000 pF ; +OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ; +OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ; +OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ; +OUTPUT PORT "nRWE" LOAD 10.000000 pF ; +OUTPUT PORT "nRCAS" LOAD 10.000000 pF ; +OUTPUT PORT "nRCS" LOAD 10.000000 pF ; +OUTPUT PORT "nRRAS" LOAD 10.000000 pF ; +OUTPUT PORT "RDQML" LOAD 10.000000 pF ; +OUTPUT PORT "RDQMH" LOAD 10.000000 pF ; +OUTPUT PORT "RCKE" LOAD 10.000000 pF ; +OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ; +OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[11]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[10]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[9]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[8]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[7]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[6]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[5]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[4]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[3]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[2]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[1]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[0]" LOAD 10.000000 pF ; +OUTPUT PORT "LED" LOAD 25.000000 pF ; +OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ; +VCCIO_DERATE BANK 0 PERCENT -5; +VCCIO_DERATE PERCENT -5; +VCCIO_DERATE BANK 1 PERCENT -5; diff --git a/CPLD/LCMXO/LCMXO256C/impl1/Untitled.tpf.prf_cdmp0 b/CPLD/LCMXO/LCMXO256C/impl1/Untitled.tpf.prf_cdmp0 new file mode 100644 index 0000000..f59c75e --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/Untitled.tpf.prf_cdmp0 @@ -0,0 +1,88 @@ +PERIOD NET "PHI2_c" 350.000000 ns ; +PERIOD NET "nCCAS_c" 350.000000 ns ; +PERIOD NET "nCRAS_c" 350.000000 ns ; +PERIOD NET "RCLK_c" 15.000000 ns ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +OUTPUT PORT "RD[7]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[0]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[1]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[2]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[3]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[4]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[5]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[6]" LOAD 20.000000 pF ; +OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ; +OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ; +OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ; +OUTPUT PORT "nRWE" LOAD 10.000000 pF ; +OUTPUT PORT "nRCAS" LOAD 10.000000 pF ; +OUTPUT PORT "nRCS" LOAD 10.000000 pF ; +OUTPUT PORT "nRRAS" LOAD 10.000000 pF ; +OUTPUT PORT "RDQML" LOAD 10.000000 pF ; +OUTPUT PORT "RDQMH" LOAD 10.000000 pF ; +OUTPUT PORT "RCKE" LOAD 10.000000 pF ; +OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ; +OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[11]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[10]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[9]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[8]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[7]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[6]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[5]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[4]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[3]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[2]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[1]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[0]" LOAD 10.000000 pF ; +OUTPUT PORT "LED" LOAD 25.000000 pF ; +OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ; +VOLTAGE 3.300 V; +VCCIO_DERATE BANK 0 PERCENT -5; +VCCIO_DERATE PERCENT -5; +VCCIO_DERATE BANK 1 PERCENT -5; +CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; diff --git a/CPLD/LCMXO/LCMXO256C/impl1/Untitled.tpf.prf_cdmp2 b/CPLD/LCMXO/LCMXO256C/impl1/Untitled.tpf.prf_cdmp2 new file mode 100644 index 0000000..fc768e6 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/Untitled.tpf.prf_cdmp2 @@ -0,0 +1,155 @@ +VOLTAGE 3.300 V; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +IOBUF PORT "RD[7]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RD[6]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RD[5]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RD[4]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RD[3]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RD[2]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RD[1]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RD[0]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Dout[7]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Dout[6]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Dout[5]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Dout[4]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Dout[3]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Dout[2]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Dout[1]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Dout[0]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RBA[1]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RBA[0]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[11]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[10]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[9]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[8]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[7]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[6]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[5]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[4]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[3]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[2]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[1]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RA[0]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "nRCS" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RCKE" IO_TYPE=LVCMOS25 ; +IOBUF PORT "nRWE" IO_TYPE=LVCMOS25 ; +IOBUF PORT "nRRAS" IO_TYPE=LVCMOS25 ; +IOBUF PORT "nRCAS" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RDQMH" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RDQML" IO_TYPE=LVCMOS25 ; +IOBUF PORT "nUFMCS" IO_TYPE=LVCMOS25 ; +IOBUF PORT "UFMCLK" IO_TYPE=LVCMOS25 ; +IOBUF PORT "UFMSDI" IO_TYPE=LVCMOS25 ; +IOBUF PORT "PHI2" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[9]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[8]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[7]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[6]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[5]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[4]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[3]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[2]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[1]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MAin[0]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "CROW[1]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "CROW[0]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Din[7]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Din[6]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Din[5]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Din[4]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Din[3]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Din[2]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Din[1]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "Din[0]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "nCCAS" IO_TYPE=LVCMOS25 ; +IOBUF PORT "nCRAS" IO_TYPE=LVCMOS25 ; +IOBUF PORT "nFWE" IO_TYPE=LVCMOS25 ; +IOBUF PORT "RCLK" IO_TYPE=LVCMOS25 ; +IOBUF PORT "UFMSDO" IO_TYPE=LVCMOS25 ; +PERIOD NET "PHI2_c" 350.000000 ns ; +PERIOD NET "nCCAS_c" 350.000000 ns ; +PERIOD NET "nCRAS_c" 350.000000 ns ; +PERIOD NET "RCLK_c" 15.000000 ns ; +CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; +CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; +OUTPUT PORT "RD[7]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[0]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[1]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[2]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[3]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[4]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[5]" LOAD 20.000000 pF ; +OUTPUT PORT "RD[6]" LOAD 20.000000 pF ; +OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ; +OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ; +OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ; +OUTPUT PORT "nRWE" LOAD 10.000000 pF ; +OUTPUT PORT "nRCAS" LOAD 10.000000 pF ; +OUTPUT PORT "nRCS" LOAD 10.000000 pF ; +OUTPUT PORT "nRRAS" LOAD 10.000000 pF ; +OUTPUT PORT "RDQML" LOAD 10.000000 pF ; +OUTPUT PORT "RDQMH" LOAD 10.000000 pF ; +OUTPUT PORT "RCKE" LOAD 10.000000 pF ; +OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ; +OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[11]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[10]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[9]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[8]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[7]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[6]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[5]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[4]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[3]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[2]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[1]" LOAD 10.000000 pF ; +OUTPUT PORT "RA[0]" LOAD 10.000000 pF ; +OUTPUT PORT "LED" LOAD 25.000000 pF ; +OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ; +OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ; +VCCIO_DERATE BANK 0 PERCENT -5; +VCCIO_DERATE PERCENT -5; +VCCIO_DERATE BANK 1 PERCENT -5; diff --git a/CPLD/LCMXO/LCMXO256C/impl1/Untitled.tpf_hold.html b/CPLD/LCMXO/LCMXO256C/impl1/Untitled.tpf_hold.html new file mode 100644 index 0000000..14546c8 --- /dev/null +++ b/CPLD/LCMXO/LCMXO256C/impl1/Untitled.tpf_hold.html @@ -0,0 +1,2080 @@ + + + + + + + +
    
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
+Mon Aug 16 20:23:38 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Design file:     RAM2GS
+Device,speed:    LCMXO256C,M
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            10 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+ 
+
+Passed: The following path meets requirements by 0.540ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_375  (from PHI2_c -)
+   Destination:    FF         Data in        ADSubmitted_375  (to PHI2_c -)
+
+   Delay:               0.517ns  (50.7% logic, 49.3% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.517ns physical path delay SLICE_9 to SLICE_9 meets
+     -0.023ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.023ns) by 0.540ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R6C3C.CLK to       R6C3C.Q0 SLICE_9 (from PHI2_c)
+ROUTE         2     0.255       R6C3C.Q0 to R6C3C.B0       ADSubmitted
+CTOF_DEL    ---     0.092       R6C3C.B0 to       R6C3C.F0 SLICE_9
+ROUTE         1     0.000       R6C3C.F0 to R6C3C.DI0      n1355 (to PHI2_c)
+                  --------
+                    0.517   (50.7% logic, 49.3% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R6C3C.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R6C3C.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 1.089ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_373  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMCS_379  (to PHI2_c -)
+                   FF                        CmdUFMCLK_380
+
+   Delay:               1.060ns  (33.4% logic, 66.6% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.060ns physical path delay SLICE_18 to SLICE_83 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.089ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R6C4D.CLK to       R6C4D.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.174       R6C4D.Q0 to R6C3A.D1       CmdEnable
+CTOF_DEL    ---     0.092       R6C3A.D1 to       R6C3A.F1 SLICE_76
+ROUTE         3     0.354       R6C3A.F1 to R4C5A.C1       XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R4C5A.C1 to       R4C5A.F1 SLICE_73
+ROUTE         2     0.178       R4C5A.F1 to R5C5D.CE       PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                    1.060   (33.4% logic, 66.6% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R6C4D.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R5C5D.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 1.165ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_373  (from PHI2_c -)
+   Destination:    FF         Data in        CmdSubmitted_378  (to PHI2_c -)
+
+   Delay:               1.136ns  (31.2% logic, 68.8% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.136ns physical path delay SLICE_18 to SLICE_19 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.165ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R6C4D.CLK to       R6C4D.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.174       R6C4D.Q0 to R6C3A.D1       CmdEnable
+CTOF_DEL    ---     0.092       R6C3A.D1 to       R6C3A.F1 SLICE_76
+ROUTE         3     0.181       R6C3A.F1 to R6C3A.B0       XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R6C3A.B0 to       R6C3A.F0 SLICE_76
+ROUTE         2     0.427       R6C3A.F0 to R7C4D.CE       PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                    1.136   (31.2% logic, 68.8% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R6C4D.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R7C4D.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 1.212ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_373  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMSDI_381  (to PHI2_c -)
+
+   Delay:               1.183ns  (29.9% logic, 70.1% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.183ns physical path delay SLICE_18 to SLICE_77 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.212ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R6C4D.CLK to       R6C4D.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.174       R6C4D.Q0 to R6C3A.D1       CmdEnable
+CTOF_DEL    ---     0.092       R6C3A.D1 to       R6C3A.F1 SLICE_76
+ROUTE         3     0.354       R6C3A.F1 to R4C5A.C1       XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R4C5A.C1 to       R4C5A.F1 SLICE_73
+ROUTE         2     0.301       R4C5A.F1 to R7C5C.CE       PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                    1.183   (29.9% logic, 70.1% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R6C4D.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R7C5C.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 1.247ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_373  (from PHI2_c -)
+   Destination:    FF         Data in        XOR8MEG_376  (to PHI2_c -)
+
+   Delay:               1.218ns  (29.1% logic, 70.9% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.218ns physical path delay SLICE_18 to SLICE_94 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.247ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R6C4D.CLK to       R6C4D.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.174       R6C4D.Q0 to R6C3A.D1       CmdEnable
+CTOF_DEL    ---     0.092       R6C3A.D1 to       R6C3A.F1 SLICE_76
+ROUTE         3     0.266       R6C3A.F1 to R7C3C.A0       XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R7C3C.A0 to       R7C3C.F0 SLICE_97
+ROUTE         1     0.424       R7C3C.F0 to R8C5C.CE       PHI2_N_114_enable_2 (to PHI2_c)
+                  --------
+                    1.218   (29.1% logic, 70.9% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R6C4D.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R8C5C.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 1.288ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_373  (from PHI2_c -)
+   Destination:    FF         Data in        Cmdn8MEGEN_377  (to PHI2_c -)
+
+   Delay:               1.259ns  (28.1% logic, 71.9% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.259ns physical path delay SLICE_18 to SLICE_23 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.288ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R6C4D.CLK to       R6C4D.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.174       R6C4D.Q0 to R6C3A.D1       CmdEnable
+CTOF_DEL    ---     0.092       R6C3A.D1 to       R6C3A.F1 SLICE_76
+ROUTE         3     0.181       R6C3A.F1 to R6C3A.B0       XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R6C3A.B0 to       R6C3A.F0 SLICE_76
+ROUTE         2     0.550       R6C3A.F0 to R7C3A.CE       PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                    1.259   (28.1% logic, 71.9% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R6C4D.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R7C3A.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 1.392ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_374  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_373  (to PHI2_c -)
+
+   Delay:               1.363ns  (37.1% logic, 62.9% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.363ns physical path delay SLICE_14 to SLICE_18 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.392ns
+
+ Physical Path Details:
+
+      Data path SLICE_14 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R6C4C.CLK to       R6C4C.Q0 SLICE_14 (from PHI2_c)
+ROUTE         1     0.256       R6C4C.Q0 to R6C3D.A1       C1Submitted
+CTOOFX_DEL  ---     0.151       R6C3D.A1 to     R6C3D.OFX0 i26/SLICE_70
+ROUTE         1     0.269     R6C3D.OFX0 to R6C4A.B1       n13
+CTOF_DEL    ---     0.092       R6C4A.B1 to       R6C4A.F1 SLICE_80
+ROUTE         1     0.172       R6C4A.F1 to R6C4A.B0       n6
+CTOF_DEL    ---     0.092       R6C4A.B0 to       R6C4A.F0 SLICE_80
+ROUTE         1     0.161       R6C4A.F0 to R6C4D.CE       PHI2_N_114_enable_8 (to PHI2_c)
+                  --------
+                    1.363   (37.1% logic, 62.9% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R6C4C.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R6C4D.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 1.395ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_375  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_373  (to PHI2_c -)
+
+   Delay:               1.366ns  (37.3% logic, 62.7% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.366ns physical path delay SLICE_9 to SLICE_18 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.395ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R6C3C.CLK to       R6C3C.Q0 SLICE_9 (from PHI2_c)
+ROUTE         2     0.255       R6C3C.Q0 to R6C3D.B0       ADSubmitted
+CTOOFX_DEL  ---     0.155       R6C3D.B0 to     R6C3D.OFX0 i26/SLICE_70
+ROUTE         1     0.269     R6C3D.OFX0 to R6C4A.B1       n13
+CTOF_DEL    ---     0.092       R6C4A.B1 to       R6C4A.F1 SLICE_80
+ROUTE         1     0.172       R6C4A.F1 to R6C4A.B0       n6
+CTOF_DEL    ---     0.092       R6C4A.B0 to       R6C4A.F0 SLICE_80
+ROUTE         1     0.161       R6C4A.F0 to R6C4D.CE       PHI2_N_114_enable_8 (to PHI2_c)
+                  --------
+                    1.366   (37.3% logic, 62.7% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R6C3C.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R6C4D.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 175.744ns (weighted slack = 351.488ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              XOR8MEG_376  (from PHI2_c -)
+   Destination:    FF         Data in        RA11_353  (to PHI2_c +)
+
+   Delay:               0.733ns  (35.7% logic, 64.3% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.733ns physical path delay SLICE_94 to SLICE_31 meets
+     -0.011ns DIN_HLD and
+    -175.000ns delay constraint less
+      0.000ns skew requirement (totaling -175.011ns) by 175.744ns
+
+ Physical Path Details:
+
+      Data path SLICE_94 to SLICE_31:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R8C5C.CLK to       R8C5C.Q0 SLICE_94 (from PHI2_c)
+ROUTE         1     0.471       R8C5C.Q0 to R2C5A.C0       XOR8MEG
+CTOF_DEL    ---     0.092       R2C5A.C0 to       R2C5A.F0 SLICE_31
+ROUTE         1     0.000       R2C5A.F0 to R2C5A.DI0      RA11_N_180 (to PHI2_c)
+                  --------
+                    0.733   (35.7% logic, 64.3% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R8C5C.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_31:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R2C5A.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 176.433ns (weighted slack = 352.866ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i3  (from PHI2_c +)
+   Destination:    FF         Data in        C1Submitted_374  (to PHI2_c -)
+
+   Delay:               1.404ns  (24.3% logic, 75.7% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.404ns physical path delay SLICE_92 to SLICE_14 meets
+     -0.029ns CE_HLD and
+    -175.000ns delay constraint less
+      0.000ns skew requirement (totaling -175.029ns) by 176.433ns
+
+ Physical Path Details:
+
+      Data path SLICE_92 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C3B.CLK to       R2C3B.Q1 SLICE_92 (from PHI2_c)
+ROUTE         1     0.502       R2C3B.Q1 to R5C4B.A1       Bank_3
+CTOF_DEL    ---     0.092       R5C4B.A1 to       R5C4B.F1 SLICE_74
+ROUTE         5     0.137       R5C4B.F1 to R5C4B.C0       n1279
+CTOF_DEL    ---     0.092       R5C4B.C0 to       R5C4B.F0 SLICE_74
+ROUTE         1     0.424       R5C4B.F0 to R6C4C.CE       PHI2_N_114_enable_1 (to PHI2_c)
+                  --------
+                    1.404   (24.3% logic, 75.7% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_92:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R2C3B.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.200       39.PADDI to R6C4C.CLK      PHI2_c
+                  --------
+                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 15.000000 ns  ;
+            10 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+ 
+
+Passed: The following path meets requirements by 0.339ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i2  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i3  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_101 to SLICE_101 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_101 to SLICE_101:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C4C.CLK to       R5C4C.Q0 SLICE_101 (from RCLK_c)
+ROUTE         1     0.161       R5C4C.Q0 to R5C4C.M1       n705 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_101:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R5C4C.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_101:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R5C4C.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.339ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i4  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i5  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_81 to SLICE_81 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_81 to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R4C4C.CLK to       R4C4C.Q0 SLICE_81 (from RCLK_c)
+ROUTE         1     0.161       R4C4C.Q0 to R4C4C.M1       n703 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R4C4C.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R4C4C.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.339ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i12  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i13  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_84 to SLICE_84 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_84 to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C4D.CLK to       R5C4D.Q0 SLICE_84 (from RCLK_c)
+ROUTE         1     0.161       R5C4D.Q0 to R5C4D.M1       n695 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R5C4D.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R5C4D.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.339ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i8  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i9  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_95 to SLICE_95 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R6C2A.CLK to       R6C2A.Q0 SLICE_95 (from RCLK_c)
+ROUTE         1     0.161       R6C2A.Q0 to R6C2A.M1       n699 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R6C2A.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R6C2A.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.339ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i11  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i12  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_96 to SLICE_84 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_96 to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C4A.CLK to       R5C4A.Q1 SLICE_96 (from RCLK_c)
+ROUTE         1     0.161       R5C4A.Q1 to R5C4D.M0       n696 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R5C4A.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R5C4D.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.339ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i10  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i11  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_96 to SLICE_96 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_96 to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C4A.CLK to       R5C4A.Q0 SLICE_96 (from RCLK_c)
+ROUTE         1     0.161       R5C4A.Q0 to R5C4A.M1       n697 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R5C4A.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R5C4A.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.339ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              PHI2r_344  (from RCLK_c +)
+   Destination:    FF         Data in        PHI2r2_345  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_97 to SLICE_88 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_97 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R7C3C.CLK to       R7C3C.Q1 SLICE_97 (from RCLK_c)
+ROUTE         1     0.161       R7C3C.Q1 to R7C3B.M1       PHI2r (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_97:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R7C3C.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R7C3B.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.339ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i14  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i15  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_99 to SLICE_99 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_99 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R3C5C.CLK to       R3C5C.Q0 SLICE_99 (from RCLK_c)
+ROUTE         1     0.161       R3C5C.Q0 to R3C5C.M1       n693 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R3C5C.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R3C5C.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.345ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              PHI2r2_345  (from RCLK_c +)
+   Destination:    FF         Data in        PHI2r3_346  (to RCLK_c +)
+
+   Delay:               0.324ns  (48.5% logic, 51.5% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.324ns physical path delay SLICE_88 to SLICE_97 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.345ns
+
+ Physical Path Details:
+
+      Data path SLICE_88 to SLICE_97:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R7C3B.CLK to       R7C3B.Q1 SLICE_88 (from RCLK_c)
+ROUTE         3     0.167       R7C3B.Q1 to R7C3C.M0       PHI2r2 (to RCLK_c)
+                  --------
+                    0.324   (48.5% logic, 51.5% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R7C3B.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_97:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R7C3C.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.345ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i15  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i0  (to RCLK_c +)
+
+   Delay:               0.324ns  (48.5% logic, 51.5% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.324ns physical path delay SLICE_99 to SLICE_87 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.345ns
+
+ Physical Path Details:
+
+      Data path SLICE_99 to SLICE_87:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R3C5C.CLK to       R3C5C.Q1 SLICE_99 (from RCLK_c)
+ROUTE         2     0.167       R3C5C.Q1 to R3C5A.M0       Ready_N_272 (to RCLK_c)
+                  --------
+                    0.324   (48.5% logic, 51.5% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R3C5C.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_87:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.413       86.PADDI to R3C5A.CLK      RCLK_c
+                  --------
+                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.220ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_368  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     1.733ns  (73.0% logic, 27.0% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_55 and
+      1.733ns delay SLICE_55 to RA[10] (totaling 2.220ns) meets
+      0.000ns hold offset RCLK to RA[10] by 2.220ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C4B.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_55 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C4B.CLK to       R2C4B.Q0 SLICE_55 (from RCLK_c)
+ROUTE         1     0.468       R2C4B.Q0 to 87.PADDO       n974
+DOPAD_DEL   ---     1.108       87.PADDO to         87.PAD RA[10]
+                  --------
+                    1.733   (73.0% logic, 27.0% route), 2 logic levels.
+
+Report:    2.220ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.805ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     2.318ns  (58.5% logic, 41.5% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.318ns delay SLICE_64 to RA[9] (totaling 2.805ns) meets
+      0.000ns hold offset RCLK to RA[9] by 2.805ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.469       R7C2B.Q0 to R3C5A.D1       nRowColSel
+CTOF_DEL    ---     0.092       R3C5A.D1 to       R3C5A.F1 SLICE_87
+ROUTE         1     0.492       R3C5A.F1 to 85.PADDO       RA_c_9
+DOPAD_DEL   ---     1.108       85.PADDO to         85.PAD RA[9]
+                  --------
+                    2.318   (58.5% logic, 41.5% route), 3 logic levels.
+
+Report:    2.805ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.476ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     1.989ns  (68.2% logic, 31.8% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      1.989ns delay SLICE_64 to RA[8] (totaling 2.476ns) meets
+      0.000ns hold offset RCLK to RA[8] by 2.476ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.435       R7C2B.Q0 to R2C2C.D0       nRowColSel
+CTOF_DEL    ---     0.092       R2C2C.D0 to       R2C2C.F0 SLICE_98
+ROUTE         1     0.197       R2C2C.F0 to 96.PADDO       RA_c_8
+DOPAD_DEL   ---     1.108       96.PADDO to         96.PAD RA[8]
+                  --------
+                    1.989   (68.2% logic, 31.8% route), 3 logic levels.
+
+Report:    2.476ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.460ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     1.973ns  (68.8% logic, 31.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      1.973ns delay SLICE_64 to RA[7] (totaling 2.460ns) meets
+      0.000ns hold offset RCLK to RA[7] by 2.460ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.222       R7C2B.Q0 to R7C2B.C1       nRowColSel
+CTOF_DEL    ---     0.092       R7C2B.C1 to       R7C2B.F1 SLICE_64
+ROUTE         1     0.394       R7C2B.F1 to 100.PADDO      RA_c_7
+DOPAD_DEL   ---     1.108      100.PADDO to        100.PAD RA[7]
+                  --------
+                    1.973   (68.8% logic, 31.2% route), 3 logic levels.
+
+Report:    2.460ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.759ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     2.272ns  (59.7% logic, 40.3% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.272ns delay SLICE_64 to RA[6] (totaling 2.759ns) meets
+      0.000ns hold offset RCLK to RA[6] by 2.759ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.435       R7C2B.Q0 to R2C2C.D1       nRowColSel
+CTOF_DEL    ---     0.092       R2C2C.D1 to       R2C2C.F1 SLICE_98
+ROUTE         1     0.480       R2C2C.F1 to 91.PADDO       RA_c_6
+DOPAD_DEL   ---     1.108       91.PADDO to         91.PAD RA[6]
+                  --------
+                    2.272   (59.7% logic, 40.3% route), 3 logic levels.
+
+Report:    2.759ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.516ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     2.029ns  (66.9% logic, 33.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.029ns delay SLICE_64 to RA[5] (totaling 2.516ns) meets
+      0.000ns hold offset RCLK to RA[5] by 2.516ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.278       R7C2B.Q0 to R6C2A.A1       nRowColSel
+CTOF_DEL    ---     0.092       R6C2A.A1 to       R6C2A.F1 SLICE_95
+ROUTE         1     0.394       R6C2A.F1 to 95.PADDO       RA_c_5
+DOPAD_DEL   ---     1.108       95.PADDO to         95.PAD RA[5]
+                  --------
+                    2.029   (66.9% logic, 33.1% route), 3 logic levels.
+
+Report:    2.516ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.635ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     2.148ns  (63.2% logic, 36.8% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.148ns delay SLICE_64 to RA[4] (totaling 2.635ns) meets
+      0.000ns hold offset RCLK to RA[4] by 2.635ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.435       R7C2B.Q0 to R2C2B.D1       nRowColSel
+CTOF_DEL    ---     0.092       R2C2B.D1 to       R2C2B.F1 SLICE_93
+ROUTE         1     0.356       R2C2B.F1 to 99.PADDO       RA_c_4
+DOPAD_DEL   ---     1.108       99.PADDO to         99.PAD RA[4]
+                  --------
+                    2.148   (63.2% logic, 36.8% route), 3 logic levels.
+
+Report:    2.635ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.758ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     2.271ns  (59.8% logic, 40.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.271ns delay SLICE_64 to RA[3] (totaling 2.758ns) meets
+      0.000ns hold offset RCLK to RA[3] by 2.758ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.446       R7C2B.Q0 to R2C3B.D1       nRowColSel
+CTOF_DEL    ---     0.092       R2C3B.D1 to       R2C3B.F1 SLICE_92
+ROUTE         1     0.468       R2C3B.F1 to 97.PADDO       RA_c_3
+DOPAD_DEL   ---     1.108       97.PADDO to         97.PAD RA[3]
+                  --------
+                    2.271   (59.8% logic, 40.2% route), 3 logic levels.
+
+Report:    2.758ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.487ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     2.000ns  (67.8% logic, 32.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.000ns delay SLICE_64 to RA[2] (totaling 2.487ns) meets
+      0.000ns hold offset RCLK to RA[2] by 2.487ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.446       R7C2B.Q0 to R2C3A.D0       nRowColSel
+CTOF_DEL    ---     0.092       R2C3A.D0 to       R2C3A.F0 SLICE_90
+ROUTE         1     0.197       R2C3A.F0 to 94.PADDO       RA_c_2
+DOPAD_DEL   ---     1.108       94.PADDO to         94.PAD RA[2]
+                  --------
+                    2.000   (67.8% logic, 32.1% route), 3 logic levels.
+
+Report:    2.487ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.487ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     2.000ns  (67.8% logic, 32.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.000ns delay SLICE_64 to RA[1] (totaling 2.487ns) meets
+      0.000ns hold offset RCLK to RA[1] by 2.487ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.446       R7C2B.Q0 to R2C3B.D0       nRowColSel
+CTOF_DEL    ---     0.092       R2C3B.D0 to       R2C3B.F0 SLICE_92
+ROUTE         1     0.197       R2C3B.F0 to 89.PADDO       RA_c_1
+DOPAD_DEL   ---     1.108       89.PADDO to         89.PAD RA[1]
+                  --------
+                    2.000   (67.8% logic, 32.1% route), 3 logic levels.
+
+Report:    2.487ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.476ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     1.989ns  (68.2% logic, 31.8% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      1.989ns delay SLICE_64 to RA[0] (totaling 2.476ns) meets
+      0.000ns hold offset RCLK to RA[0] by 2.476ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.435       R7C2B.Q0 to R2C2B.D0       nRowColSel
+CTOF_DEL    ---     0.092       R2C2B.D0 to       R2C2B.F0 SLICE_93
+ROUTE         1     0.197       R2C2B.F0 to 98.PADDO       RA_c_0
+DOPAD_DEL   ---     1.108       98.PADDO to         98.PAD RA[0]
+                  --------
+                    1.989   (68.2% logic, 31.8% route), 3 logic levels.
+
+Report:    2.476ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.949ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_364  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_60 and
+      1.462ns delay SLICE_60 to nRCS (totaling 1.949ns) meets
+      0.000ns hold offset RCLK to nRCS by 1.949ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C5B.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_60 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C5B.CLK to       R2C5B.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1     0.197       R2C5B.Q0 to 77.PADDO       nRCS_c
+DOPAD_DEL   ---     1.108       77.PADDO to         77.PAD nRCS
+                  --------
+                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    1.949ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.252ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_363  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     1.765ns  (71.7% logic, 28.3% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_34 and
+      1.765ns delay SLICE_34 to RCKE (totaling 2.252ns) meets
+      0.000ns hold offset RCLK to RCKE by 2.252ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R6C5B.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_34 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R6C5B.CLK to       R6C5B.Q0 SLICE_34 (from RCLK_c)
+ROUTE         4     0.500       R6C5B.Q0 to 82.PADDO       RCKE_c
+DOPAD_DEL   ---     1.108       82.PADDO to         82.PAD RCKE
+                  --------
+                    1.765   (71.7% logic, 28.3% route), 2 logic levels.
+
+Report:    2.252ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.949ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_367  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_63 and
+      1.462ns delay SLICE_63 to nRWE (totaling 1.949ns) meets
+      0.000ns hold offset RCLK to nRWE by 1.949ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R3C5B.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_63 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R3C5B.CLK to       R3C5B.Q0 SLICE_63 (from RCLK_c)
+ROUTE         1     0.197       R3C5B.Q0 to 72.PADDO       nRWE_c
+DOPAD_DEL   ---     1.108       72.PADDO to         72.PAD nRWE
+                  --------
+                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    1.949ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.111ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_365  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     1.624ns  (77.9% logic, 22.1% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_61 and
+      1.624ns delay SLICE_61 to nRRAS (totaling 2.111ns) meets
+      0.000ns hold offset RCLK to nRRAS by 2.111ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C4C.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_61 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C4C.CLK to       R2C4C.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2     0.359       R2C4C.Q0 to 73.PADDO       nRRAS_c
+DOPAD_DEL   ---     1.108       73.PADDO to         73.PAD nRRAS
+                  --------
+                    1.624   (77.9% logic, 22.1% route), 2 logic levels.
+
+Report:    2.111ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.220ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_366  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     1.733ns  (73.0% logic, 27.0% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_58 and
+      1.733ns delay SLICE_58 to nRCAS (totaling 2.220ns) meets
+      0.000ns hold offset RCLK to nRCAS by 2.220ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C4A.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_58 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C4A.CLK to       R2C4A.Q0 SLICE_58 (from RCLK_c)
+ROUTE         1     0.468       R2C4A.Q0 to 78.PADDO       nRCAS_c
+DOPAD_DEL   ---     1.108       78.PADDO to         78.PAD nRCAS
+                  --------
+                    1.733   (73.0% logic, 27.0% route), 2 logic levels.
+
+Report:    2.220ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.510ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     2.023ns  (67.1% logic, 32.9% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.023ns delay SLICE_64 to RDQMH (totaling 2.510ns) meets
+      0.000ns hold offset RCLK to RDQMH by 2.510ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.469       R7C2B.Q0 to R3C5A.D0       nRowColSel
+CTOF_DEL    ---     0.092       R3C5A.D0 to       R3C5A.F0 SLICE_87
+ROUTE         1     0.197       R3C5A.F0 to 76.PADDO       RDQMH_c
+DOPAD_DEL   ---     1.108       76.PADDO to         76.PAD RDQMH
+                  --------
+                    2.023   (67.1% logic, 32.9% route), 3 logic levels.
+
+Report:    2.510ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.602ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     2.115ns  (64.2% logic, 35.8% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.115ns delay SLICE_64 to RDQML (totaling 2.602ns) meets
+      0.000ns hold offset RCLK to RDQML by 2.602ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.278       R7C2B.Q0 to R6C2A.A0       nRowColSel
+CTOF_DEL    ---     0.092       R6C2A.A0 to       R6C2A.F0 SLICE_95
+ROUTE         1     0.480       R6C2A.F0 to 61.PADDO       RDQML_c
+DOPAD_DEL   ---     1.108       61.PADDO to         61.PAD RDQML
+                  --------
+                    2.115   (64.2% logic, 35.8% route), 3 logic levels.
+
+Report:    2.602ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |            -|            -|   2  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 15.000000 ns  ;     |            -|            -|   1  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.220 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.805 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.476 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.460 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.759 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.516 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.635 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.758 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.487 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.487 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.476 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.252 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.111 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.220 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.510 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.602 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
+   Covered under: PERIOD NET "RCLK_c" 15.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 520 paths, 6 nets, and 436 connections (70.89% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 0 (setup), 0 (hold)
+Score: 0 (setup), 0 (hold)
+Cumulative negative slack: 0 (0+0)
diff --git a/CPLD/LCMXO/LCMXO256C/impl1/Untitled.tpf_setup.html b/CPLD/LCMXO/LCMXO256C/impl1/Untitled.tpf_setup.html
new file mode 100644
index 0000000..267300a
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO256C/impl1/Untitled.tpf_setup.html
@@ -0,0 +1,3314 @@
+
+
+
+
+
+
+
+
    
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
+Mon Aug 16 20:23:38 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Design file:     RAM2GS
+Device,speed:    LCMXO256C,3
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            10 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+ 
+
+Passed: The following path meets requirements by 162.969ns (weighted slack = 325.938ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i0  (from PHI2_c +)
+   Destination:    FF         Data in        Cmdn8MEGEN_377  (to PHI2_c -)
+
+   Delay:              11.766ns  (23.7% logic, 76.3% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.766ns physical path delay SLICE_93 to SLICE_23 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 162.969ns
+
+ Physical Path Details:
+
+      Data path SLICE_93 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2B.CLK to       R2C2B.Q0 SLICE_93 (from PHI2_c)
+ROUTE         1     1.086       R2C2B.Q0 to R2C3A.B1       Bank_0
+CTOF_DEL    ---     0.371       R2C3A.B1 to       R2C3A.F1 SLICE_90
+ROUTE         1     1.643       R2C3A.F1 to R5C4D.B1       n2160
+CTOF_DEL    ---     0.371       R5C4D.B1 to       R5C4D.F1 SLICE_84
+ROUTE         1     0.819       R5C4D.F1 to R5C4B.C1       n26
+CTOF_DEL    ---     0.371       R5C4B.C1 to       R5C4B.F1 SLICE_74
+ROUTE         5     1.601       R5C4B.F1 to R6C3C.B1       n1279
+CTOF_DEL    ---     0.371       R6C3C.B1 to       R6C3C.F1 SLICE_9
+ROUTE         2     0.974       R6C3C.F1 to R6C3A.A1       n2288
+CTOF_DEL    ---     0.371       R6C3A.A1 to       R6C3A.F1 SLICE_76
+ROUTE         3     0.727       R6C3A.F1 to R6C3A.B0       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R6C3A.B0 to       R6C3A.F0 SLICE_76
+ROUTE         2     2.130       R6C3A.F0 to R7C3A.CE       PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                   11.766   (23.7% logic, 76.3% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R2C2B.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R7C3A.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 163.029ns (weighted slack = 326.058ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        Cmdn8MEGEN_377  (to PHI2_c -)
+
+   Delay:              11.706ns  (23.8% logic, 76.2% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.706ns physical path delay SLICE_98 to SLICE_23 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 163.029ns
+
+ Physical Path Details:
+
+      Data path SLICE_98 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2C.CLK to       R2C2C.Q0 SLICE_98 (from PHI2_c)
+ROUTE         1     1.026       R2C2C.Q0 to R2C3A.A1       Bank_6
+CTOF_DEL    ---     0.371       R2C3A.A1 to       R2C3A.F1 SLICE_90
+ROUTE         1     1.643       R2C3A.F1 to R5C4D.B1       n2160
+CTOF_DEL    ---     0.371       R5C4D.B1 to       R5C4D.F1 SLICE_84
+ROUTE         1     0.819       R5C4D.F1 to R5C4B.C1       n26
+CTOF_DEL    ---     0.371       R5C4B.C1 to       R5C4B.F1 SLICE_74
+ROUTE         5     1.601       R5C4B.F1 to R6C3C.B1       n1279
+CTOF_DEL    ---     0.371       R6C3C.B1 to       R6C3C.F1 SLICE_9
+ROUTE         2     0.974       R6C3C.F1 to R6C3A.A1       n2288
+CTOF_DEL    ---     0.371       R6C3A.A1 to       R6C3A.F1 SLICE_76
+ROUTE         3     0.727       R6C3A.F1 to R6C3A.B0       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R6C3A.B0 to       R6C3A.F0 SLICE_76
+ROUTE         2     2.130       R6C3A.F0 to R7C3A.CE       PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                   11.706   (23.8% logic, 76.2% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_98:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R2C2C.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R7C3A.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 163.113ns (weighted slack = 326.226ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i0  (from PHI2_c +)
+   Destination:    FF         Data in        XOR8MEG_376  (to PHI2_c -)
+
+   Delay:              11.622ns  (24.0% logic, 76.0% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.622ns physical path delay SLICE_93 to SLICE_94 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 163.113ns
+
+ Physical Path Details:
+
+      Data path SLICE_93 to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2B.CLK to       R2C2B.Q0 SLICE_93 (from PHI2_c)
+ROUTE         1     1.086       R2C2B.Q0 to R2C3A.B1       Bank_0
+CTOF_DEL    ---     0.371       R2C3A.B1 to       R2C3A.F1 SLICE_90
+ROUTE         1     1.643       R2C3A.F1 to R5C4D.B1       n2160
+CTOF_DEL    ---     0.371       R5C4D.B1 to       R5C4D.F1 SLICE_84
+ROUTE         1     0.819       R5C4D.F1 to R5C4B.C1       n26
+CTOF_DEL    ---     0.371       R5C4B.C1 to       R5C4B.F1 SLICE_74
+ROUTE         5     1.601       R5C4B.F1 to R6C3C.B1       n1279
+CTOF_DEL    ---     0.371       R6C3C.B1 to       R6C3C.F1 SLICE_9
+ROUTE         2     0.974       R6C3C.F1 to R6C3A.A1       n2288
+CTOF_DEL    ---     0.371       R6C3A.A1 to       R6C3A.F1 SLICE_76
+ROUTE         3     1.057       R6C3A.F1 to R7C3C.A0       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R7C3C.A0 to       R7C3C.F0 SLICE_97
+ROUTE         1     1.656       R7C3C.F0 to R8C5C.CE       PHI2_N_114_enable_2 (to PHI2_c)
+                  --------
+                   11.622   (24.0% logic, 76.0% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R2C2B.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R8C5C.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 163.173ns (weighted slack = 326.346ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        XOR8MEG_376  (to PHI2_c -)
+
+   Delay:              11.562ns  (24.1% logic, 75.9% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.562ns physical path delay SLICE_98 to SLICE_94 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 163.173ns
+
+ Physical Path Details:
+
+      Data path SLICE_98 to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2C.CLK to       R2C2C.Q0 SLICE_98 (from PHI2_c)
+ROUTE         1     1.026       R2C2C.Q0 to R2C3A.A1       Bank_6
+CTOF_DEL    ---     0.371       R2C3A.A1 to       R2C3A.F1 SLICE_90
+ROUTE         1     1.643       R2C3A.F1 to R5C4D.B1       n2160
+CTOF_DEL    ---     0.371       R5C4D.B1 to       R5C4D.F1 SLICE_84
+ROUTE         1     0.819       R5C4D.F1 to R5C4B.C1       n26
+CTOF_DEL    ---     0.371       R5C4B.C1 to       R5C4B.F1 SLICE_74
+ROUTE         5     1.601       R5C4B.F1 to R6C3C.B1       n1279
+CTOF_DEL    ---     0.371       R6C3C.B1 to       R6C3C.F1 SLICE_9
+ROUTE         2     0.974       R6C3C.F1 to R6C3A.A1       n2288
+CTOF_DEL    ---     0.371       R6C3A.A1 to       R6C3A.F1 SLICE_76
+ROUTE         3     1.057       R6C3A.F1 to R7C3C.A0       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R7C3C.A0 to       R7C3C.F0 SLICE_97
+ROUTE         1     1.656       R7C3C.F0 to R8C5C.CE       PHI2_N_114_enable_2 (to PHI2_c)
+                  --------
+                   11.562   (24.1% logic, 75.9% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_98:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R2C2C.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R8C5C.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 163.236ns (weighted slack = 326.472ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i5  (from PHI2_c +)
+   Destination:    FF         Data in        Cmdn8MEGEN_377  (to PHI2_c -)
+
+   Delay:              11.499ns  (24.2% logic, 75.8% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.499ns physical path delay SLICE_90 to SLICE_23 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 163.236ns
+
+ Physical Path Details:
+
+      Data path SLICE_90 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C3A.CLK to       R2C3A.Q1 SLICE_90 (from PHI2_c)
+ROUTE         1     0.819       R2C3A.Q1 to R2C3A.C1       Bank_5
+CTOF_DEL    ---     0.371       R2C3A.C1 to       R2C3A.F1 SLICE_90
+ROUTE         1     1.643       R2C3A.F1 to R5C4D.B1       n2160
+CTOF_DEL    ---     0.371       R5C4D.B1 to       R5C4D.F1 SLICE_84
+ROUTE         1     0.819       R5C4D.F1 to R5C4B.C1       n26
+CTOF_DEL    ---     0.371       R5C4B.C1 to       R5C4B.F1 SLICE_74
+ROUTE         5     1.601       R5C4B.F1 to R6C3C.B1       n1279
+CTOF_DEL    ---     0.371       R6C3C.B1 to       R6C3C.F1 SLICE_9
+ROUTE         2     0.974       R6C3C.F1 to R6C3A.A1       n2288
+CTOF_DEL    ---     0.371       R6C3A.A1 to       R6C3A.F1 SLICE_76
+ROUTE         3     0.727       R6C3A.F1 to R6C3A.B0       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R6C3A.B0 to       R6C3A.F0 SLICE_76
+ROUTE         2     2.130       R6C3A.F0 to R7C3A.CE       PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                   11.499   (24.2% logic, 75.8% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R2C3A.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R7C3A.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 163.277ns (weighted slack = 326.554ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i0  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMSDI_381  (to PHI2_c -)
+
+   Delay:              11.458ns  (24.3% logic, 75.7% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.458ns physical path delay SLICE_93 to SLICE_77 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 163.277ns
+
+ Physical Path Details:
+
+      Data path SLICE_93 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2B.CLK to       R2C2B.Q0 SLICE_93 (from PHI2_c)
+ROUTE         1     1.086       R2C2B.Q0 to R2C3A.B1       Bank_0
+CTOF_DEL    ---     0.371       R2C3A.B1 to       R2C3A.F1 SLICE_90
+ROUTE         1     1.643       R2C3A.F1 to R5C4D.B1       n2160
+CTOF_DEL    ---     0.371       R5C4D.B1 to       R5C4D.F1 SLICE_84
+ROUTE         1     0.819       R5C4D.F1 to R5C4B.C1       n26
+CTOF_DEL    ---     0.371       R5C4B.C1 to       R5C4B.F1 SLICE_74
+ROUTE         5     1.601       R5C4B.F1 to R6C3C.B1       n1279
+CTOF_DEL    ---     0.371       R6C3C.B1 to       R6C3C.F1 SLICE_9
+ROUTE         2     0.974       R6C3C.F1 to R6C3A.A1       n2288
+CTOF_DEL    ---     0.371       R6C3A.A1 to       R6C3A.F1 SLICE_76
+ROUTE         3     1.379       R6C3A.F1 to R4C5A.C1       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R4C5A.C1 to       R4C5A.F1 SLICE_73
+ROUTE         2     1.170       R4C5A.F1 to R7C5C.CE       PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   11.458   (24.3% logic, 75.7% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R2C2B.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R7C5C.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 163.337ns (weighted slack = 326.674ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMSDI_381  (to PHI2_c -)
+
+   Delay:              11.398ns  (24.4% logic, 75.6% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.398ns physical path delay SLICE_98 to SLICE_77 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 163.337ns
+
+ Physical Path Details:
+
+      Data path SLICE_98 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2C.CLK to       R2C2C.Q0 SLICE_98 (from PHI2_c)
+ROUTE         1     1.026       R2C2C.Q0 to R2C3A.A1       Bank_6
+CTOF_DEL    ---     0.371       R2C3A.A1 to       R2C3A.F1 SLICE_90
+ROUTE         1     1.643       R2C3A.F1 to R5C4D.B1       n2160
+CTOF_DEL    ---     0.371       R5C4D.B1 to       R5C4D.F1 SLICE_84
+ROUTE         1     0.819       R5C4D.F1 to R5C4B.C1       n26
+CTOF_DEL    ---     0.371       R5C4B.C1 to       R5C4B.F1 SLICE_74
+ROUTE         5     1.601       R5C4B.F1 to R6C3C.B1       n1279
+CTOF_DEL    ---     0.371       R6C3C.B1 to       R6C3C.F1 SLICE_9
+ROUTE         2     0.974       R6C3C.F1 to R6C3A.A1       n2288
+CTOF_DEL    ---     0.371       R6C3A.A1 to       R6C3A.F1 SLICE_76
+ROUTE         3     1.379       R6C3A.F1 to R4C5A.C1       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R4C5A.C1 to       R4C5A.F1 SLICE_73
+ROUTE         2     1.170       R4C5A.F1 to R7C5C.CE       PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   11.398   (24.4% logic, 75.6% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_98:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R2C2C.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R7C5C.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 163.380ns (weighted slack = 326.760ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i5  (from PHI2_c +)
+   Destination:    FF         Data in        XOR8MEG_376  (to PHI2_c -)
+
+   Delay:              11.355ns  (24.5% logic, 75.5% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.355ns physical path delay SLICE_90 to SLICE_94 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 163.380ns
+
+ Physical Path Details:
+
+      Data path SLICE_90 to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C3A.CLK to       R2C3A.Q1 SLICE_90 (from PHI2_c)
+ROUTE         1     0.819       R2C3A.Q1 to R2C3A.C1       Bank_5
+CTOF_DEL    ---     0.371       R2C3A.C1 to       R2C3A.F1 SLICE_90
+ROUTE         1     1.643       R2C3A.F1 to R5C4D.B1       n2160
+CTOF_DEL    ---     0.371       R5C4D.B1 to       R5C4D.F1 SLICE_84
+ROUTE         1     0.819       R5C4D.F1 to R5C4B.C1       n26
+CTOF_DEL    ---     0.371       R5C4B.C1 to       R5C4B.F1 SLICE_74
+ROUTE         5     1.601       R5C4B.F1 to R6C3C.B1       n1279
+CTOF_DEL    ---     0.371       R6C3C.B1 to       R6C3C.F1 SLICE_9
+ROUTE         2     0.974       R6C3C.F1 to R6C3A.A1       n2288
+CTOF_DEL    ---     0.371       R6C3A.A1 to       R6C3A.F1 SLICE_76
+ROUTE         3     1.057       R6C3A.F1 to R7C3C.A0       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R7C3C.A0 to       R7C3C.F0 SLICE_97
+ROUTE         1     1.656       R7C3C.F0 to R8C5C.CE       PHI2_N_114_enable_2 (to PHI2_c)
+                  --------
+                   11.355   (24.5% logic, 75.5% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R2C3A.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R8C5C.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 163.430ns (weighted slack = 326.860ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i0  (from PHI2_c +)
+   Destination:    FF         Data in        CmdSubmitted_378  (to PHI2_c -)
+
+   Delay:              11.305ns  (24.6% logic, 75.4% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.305ns physical path delay SLICE_93 to SLICE_19 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 163.430ns
+
+ Physical Path Details:
+
+      Data path SLICE_93 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2B.CLK to       R2C2B.Q0 SLICE_93 (from PHI2_c)
+ROUTE         1     1.086       R2C2B.Q0 to R2C3A.B1       Bank_0
+CTOF_DEL    ---     0.371       R2C3A.B1 to       R2C3A.F1 SLICE_90
+ROUTE         1     1.643       R2C3A.F1 to R5C4D.B1       n2160
+CTOF_DEL    ---     0.371       R5C4D.B1 to       R5C4D.F1 SLICE_84
+ROUTE         1     0.819       R5C4D.F1 to R5C4B.C1       n26
+CTOF_DEL    ---     0.371       R5C4B.C1 to       R5C4B.F1 SLICE_74
+ROUTE         5     1.601       R5C4B.F1 to R6C3C.B1       n1279
+CTOF_DEL    ---     0.371       R6C3C.B1 to       R6C3C.F1 SLICE_9
+ROUTE         2     0.974       R6C3C.F1 to R6C3A.A1       n2288
+CTOF_DEL    ---     0.371       R6C3A.A1 to       R6C3A.F1 SLICE_76
+ROUTE         3     0.727       R6C3A.F1 to R6C3A.B0       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R6C3A.B0 to       R6C3A.F0 SLICE_76
+ROUTE         2     1.669       R6C3A.F0 to R7C4D.CE       PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                   11.305   (24.6% logic, 75.4% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R2C2B.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R7C4D.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 163.490ns (weighted slack = 326.980ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        CmdSubmitted_378  (to PHI2_c -)
+
+   Delay:              11.245ns  (24.8% logic, 75.2% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.245ns physical path delay SLICE_98 to SLICE_19 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 163.490ns
+
+ Physical Path Details:
+
+      Data path SLICE_98 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2C.CLK to       R2C2C.Q0 SLICE_98 (from PHI2_c)
+ROUTE         1     1.026       R2C2C.Q0 to R2C3A.A1       Bank_6
+CTOF_DEL    ---     0.371       R2C3A.A1 to       R2C3A.F1 SLICE_90
+ROUTE         1     1.643       R2C3A.F1 to R5C4D.B1       n2160
+CTOF_DEL    ---     0.371       R5C4D.B1 to       R5C4D.F1 SLICE_84
+ROUTE         1     0.819       R5C4D.F1 to R5C4B.C1       n26
+CTOF_DEL    ---     0.371       R5C4B.C1 to       R5C4B.F1 SLICE_74
+ROUTE         5     1.601       R5C4B.F1 to R6C3C.B1       n1279
+CTOF_DEL    ---     0.371       R6C3C.B1 to       R6C3C.F1 SLICE_9
+ROUTE         2     0.974       R6C3C.F1 to R6C3A.A1       n2288
+CTOF_DEL    ---     0.371       R6C3A.A1 to       R6C3A.F1 SLICE_76
+ROUTE         3     0.727       R6C3A.F1 to R6C3A.B0       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R6C3A.B0 to       R6C3A.F0 SLICE_76
+ROUTE         2     1.669       R6C3A.F0 to R7C4D.CE       PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                   11.245   (24.8% logic, 75.2% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_98:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R2C2C.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.924       39.PADDI to R7C4D.CLK      PHI2_c
+                  --------
+                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:   24.062ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 348.000ns
+         The internal maximum frequency of the following component is 500.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    FSLICE     CLK            SLICE_73
+
+   Delay:               2.000ns -- based on Minimum Pulse Width
+
+Report:    2.000ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 348.000ns
+         The internal maximum frequency of the following component is 500.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    FSLICE     CLK            SLICE_74
+
+   Delay:               2.000ns -- based on Minimum Pulse Width
+
+Report:    2.000ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 15.000000 ns  ;
+            10 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+ 
+
+Passed: The following path meets requirements by 6.275ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i14  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_386  (to RCLK_c +)
+
+   Delay:               8.481ns  (28.5% logic, 71.5% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.481ns physical path delay SLICE_7 to SLICE_85 meets
+     15.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 14.756ns) by 6.275ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C4D.CLK to       R8C4D.Q0 SLICE_7 (from RCLK_c)
+ROUTE         3     1.466       R8C4D.Q0 to R8C5D.B1       FS_14
+CTOF_DEL    ---     0.371       R8C5D.B1 to       R8C5D.F1 SLICE_78
+ROUTE         3     1.117       R8C5D.F1 to R9C5A.B1       n10
+CTOF_DEL    ---     0.371       R9C5A.B1 to       R9C5A.F1 SLICE_75
+ROUTE         4     0.712       R9C5A.F1 to R9C5A.B0       n2298
+CTOF_DEL    ---     0.371       R9C5A.B0 to       R9C5A.F0 SLICE_75
+ROUTE         1     1.026       R9C5A.F0 to R7C5C.A1       n11
+CTOF_DEL    ---     0.371       R7C5C.A1 to       R7C5C.F1 SLICE_77
+ROUTE         2     1.042       R7C5C.F1 to R5C5A.A1       n2111
+CTOF_DEL    ---     0.371       R5C5A.A1 to       R5C5A.F1 SLICE_100
+ROUTE         1     0.703       R5C5A.F1 to R7C5D.CE       RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    8.481   (28.5% logic, 71.5% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R8C4D.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R7C5D.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 6.434ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i14  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)
+
+   Delay:               8.322ns  (29.0% logic, 71.0% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.322ns physical path delay SLICE_7 to SLICE_56 meets
+     15.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 14.756ns) by 6.434ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C4D.CLK to       R8C4D.Q0 SLICE_7 (from RCLK_c)
+ROUTE         3     1.466       R8C4D.Q0 to R8C5D.B1       FS_14
+CTOF_DEL    ---     0.371       R8C5D.B1 to       R8C5D.F1 SLICE_78
+ROUTE         3     1.117       R8C5D.F1 to R9C5A.B1       n10
+CTOF_DEL    ---     0.371       R9C5A.B1 to       R9C5A.F1 SLICE_75
+ROUTE         4     0.712       R9C5A.F1 to R9C5A.B0       n2298
+CTOF_DEL    ---     0.371       R9C5A.B0 to       R9C5A.F0 SLICE_75
+ROUTE         1     1.026       R9C5A.F0 to R7C5C.A1       n11
+CTOF_DEL    ---     0.371       R7C5C.A1 to       R7C5C.F1 SLICE_77
+ROUTE         2     0.513       R7C5C.F1 to R7C5C.C0       n2111
+CTOF_DEL    ---     0.371       R7C5C.C0 to       R7C5C.F0 SLICE_77
+ROUTE         1     1.073       R7C5C.F0 to R7C4B.CE       RCLK_c_enable_7 (to RCLK_c)
+                  --------
+                    8.322   (29.0% logic, 71.0% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R8C4D.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R7C4B.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 6.474ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i15  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_386  (to RCLK_c +)
+
+   Delay:               8.282ns  (29.2% logic, 70.8% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.282ns physical path delay SLICE_7 to SLICE_85 meets
+     15.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 14.756ns) by 6.474ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C4D.CLK to       R8C4D.Q1 SLICE_7 (from RCLK_c)
+ROUTE         3     1.267       R8C4D.Q1 to R8C5D.C1       FS_15
+CTOF_DEL    ---     0.371       R8C5D.C1 to       R8C5D.F1 SLICE_78
+ROUTE         3     1.117       R8C5D.F1 to R9C5A.B1       n10
+CTOF_DEL    ---     0.371       R9C5A.B1 to       R9C5A.F1 SLICE_75
+ROUTE         4     0.712       R9C5A.F1 to R9C5A.B0       n2298
+CTOF_DEL    ---     0.371       R9C5A.B0 to       R9C5A.F0 SLICE_75
+ROUTE         1     1.026       R9C5A.F0 to R7C5C.A1       n11
+CTOF_DEL    ---     0.371       R7C5C.A1 to       R7C5C.F1 SLICE_77
+ROUTE         2     1.042       R7C5C.F1 to R5C5A.A1       n2111
+CTOF_DEL    ---     0.371       R5C5A.A1 to       R5C5A.F1 SLICE_100
+ROUTE         1     0.703       R5C5A.F1 to R7C5D.CE       RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    8.282   (29.2% logic, 70.8% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R8C4D.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R7C5D.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 6.633ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i15  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)
+
+   Delay:               8.123ns  (29.7% logic, 70.3% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.123ns physical path delay SLICE_7 to SLICE_56 meets
+     15.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 14.756ns) by 6.633ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C4D.CLK to       R8C4D.Q1 SLICE_7 (from RCLK_c)
+ROUTE         3     1.267       R8C4D.Q1 to R8C5D.C1       FS_15
+CTOF_DEL    ---     0.371       R8C5D.C1 to       R8C5D.F1 SLICE_78
+ROUTE         3     1.117       R8C5D.F1 to R9C5A.B1       n10
+CTOF_DEL    ---     0.371       R9C5A.B1 to       R9C5A.F1 SLICE_75
+ROUTE         4     0.712       R9C5A.F1 to R9C5A.B0       n2298
+CTOF_DEL    ---     0.371       R9C5A.B0 to       R9C5A.F0 SLICE_75
+ROUTE         1     1.026       R9C5A.F0 to R7C5C.A1       n11
+CTOF_DEL    ---     0.371       R7C5C.A1 to       R7C5C.F1 SLICE_77
+ROUTE         2     0.513       R7C5C.F1 to R7C5C.C0       n2111
+CTOF_DEL    ---     0.371       R7C5C.C0 to       R7C5C.F0 SLICE_77
+ROUTE         1     1.073       R7C5C.F0 to R7C4B.CE       RCLK_c_enable_7 (to RCLK_c)
+                  --------
+                    8.123   (29.7% logic, 70.3% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R8C4D.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R7C4B.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 6.693ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i13  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_386  (to RCLK_c +)
+
+   Delay:               8.063ns  (30.0% logic, 70.0% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.063ns physical path delay SLICE_8 to SLICE_85 meets
+     15.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 14.756ns) by 6.693ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C4C.CLK to       R8C4C.Q1 SLICE_8 (from RCLK_c)
+ROUTE         3     1.048       R8C4C.Q1 to R8C5D.A1       FS_13
+CTOF_DEL    ---     0.371       R8C5D.A1 to       R8C5D.F1 SLICE_78
+ROUTE         3     1.117       R8C5D.F1 to R9C5A.B1       n10
+CTOF_DEL    ---     0.371       R9C5A.B1 to       R9C5A.F1 SLICE_75
+ROUTE         4     0.712       R9C5A.F1 to R9C5A.B0       n2298
+CTOF_DEL    ---     0.371       R9C5A.B0 to       R9C5A.F0 SLICE_75
+ROUTE         1     1.026       R9C5A.F0 to R7C5C.A1       n11
+CTOF_DEL    ---     0.371       R7C5C.A1 to       R7C5C.F1 SLICE_77
+ROUTE         2     1.042       R7C5C.F1 to R5C5A.A1       n2111
+CTOF_DEL    ---     0.371       R5C5A.A1 to       R5C5A.F1 SLICE_100
+ROUTE         1     0.703       R5C5A.F1 to R7C5D.CE       RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    8.063   (30.0% logic, 70.0% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R8C4C.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R7C5D.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 6.852ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i13  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)
+
+   Delay:               7.904ns  (30.6% logic, 69.4% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.904ns physical path delay SLICE_8 to SLICE_56 meets
+     15.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 14.756ns) by 6.852ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C4C.CLK to       R8C4C.Q1 SLICE_8 (from RCLK_c)
+ROUTE         3     1.048       R8C4C.Q1 to R8C5D.A1       FS_13
+CTOF_DEL    ---     0.371       R8C5D.A1 to       R8C5D.F1 SLICE_78
+ROUTE         3     1.117       R8C5D.F1 to R9C5A.B1       n10
+CTOF_DEL    ---     0.371       R9C5A.B1 to       R9C5A.F1 SLICE_75
+ROUTE         4     0.712       R9C5A.F1 to R9C5A.B0       n2298
+CTOF_DEL    ---     0.371       R9C5A.B0 to       R9C5A.F0 SLICE_75
+ROUTE         1     1.026       R9C5A.F0 to R7C5C.A1       n11
+CTOF_DEL    ---     0.371       R7C5C.A1 to       R7C5C.F1 SLICE_77
+ROUTE         2     0.513       R7C5C.F1 to R7C5C.C0       n2111
+CTOF_DEL    ---     0.371       R7C5C.C0 to       R7C5C.F0 SLICE_77
+ROUTE         1     1.073       R7C5C.F0 to R7C4B.CE       RCLK_c_enable_7 (to RCLK_c)
+                  --------
+                    7.904   (30.6% logic, 69.4% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R8C4C.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R7C4B.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 6.891ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i2  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_386  (to RCLK_c +)
+
+   Delay:               7.865ns  (26.0% logic, 74.0% route), 5 logic levels.
+
+ Constraint Details:
+
+      7.865ns physical path delay SLICE_4 to SLICE_85 meets
+     15.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 14.756ns) by 6.891ns
+
+ Physical Path Details:
+
+      Data path SLICE_4 to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C3B.CLK to       R8C3B.Q0 SLICE_4 (from RCLK_c)
+ROUTE         2     1.563       R8C3B.Q0 to R7C4C.B1       FS_2
+CTOF_DEL    ---     0.371       R7C4C.B1 to       R7C4C.F1 SLICE_68
+ROUTE         1     1.487       R7C4C.F1 to R9C5A.A0       n2164
+CTOF_DEL    ---     0.371       R9C5A.A0 to       R9C5A.F0 SLICE_75
+ROUTE         1     1.026       R9C5A.F0 to R7C5C.A1       n11
+CTOF_DEL    ---     0.371       R7C5C.A1 to       R7C5C.F1 SLICE_77
+ROUTE         2     1.042       R7C5C.F1 to R5C5A.A1       n2111
+CTOF_DEL    ---     0.371       R5C5A.A1 to       R5C5A.F1 SLICE_100
+ROUTE         1     0.703       R5C5A.F1 to R7C5D.CE       RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    7.865   (26.0% logic, 74.0% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_4:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R8C3B.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R7C5D.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 6.951ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i1  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_386  (to RCLK_c +)
+
+   Delay:               7.805ns  (26.2% logic, 73.8% route), 5 logic levels.
+
+ Constraint Details:
+
+      7.805ns physical path delay SLICE_5 to SLICE_85 meets
+     15.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 14.756ns) by 6.951ns
+
+ Physical Path Details:
+
+      Data path SLICE_5 to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C3A.CLK to       R8C3A.Q1 SLICE_5 (from RCLK_c)
+ROUTE         2     1.503       R8C3A.Q1 to R7C4C.A1       FS_1
+CTOF_DEL    ---     0.371       R7C4C.A1 to       R7C4C.F1 SLICE_68
+ROUTE         1     1.487       R7C4C.F1 to R9C5A.A0       n2164
+CTOF_DEL    ---     0.371       R9C5A.A0 to       R9C5A.F0 SLICE_75
+ROUTE         1     1.026       R9C5A.F0 to R7C5C.A1       n11
+CTOF_DEL    ---     0.371       R7C5C.A1 to       R7C5C.F1 SLICE_77
+ROUTE         2     1.042       R7C5C.F1 to R5C5A.A1       n2111
+CTOF_DEL    ---     0.371       R5C5A.A1 to       R5C5A.F1 SLICE_100
+ROUTE         1     0.703       R5C5A.F1 to R7C5D.CE       RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    7.805   (26.2% logic, 73.8% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R8C3A.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R7C5D.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 7.017ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i12  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_386  (to RCLK_c +)
+
+   Delay:               7.739ns  (31.2% logic, 68.8% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.739ns physical path delay SLICE_8 to SLICE_85 meets
+     15.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 14.756ns) by 7.017ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C4C.CLK to       R8C4C.Q0 SLICE_8 (from RCLK_c)
+ROUTE         3     0.724       R8C4C.Q0 to R8C5D.D1       FS_12
+CTOF_DEL    ---     0.371       R8C5D.D1 to       R8C5D.F1 SLICE_78
+ROUTE         3     1.117       R8C5D.F1 to R9C5A.B1       n10
+CTOF_DEL    ---     0.371       R9C5A.B1 to       R9C5A.F1 SLICE_75
+ROUTE         4     0.712       R9C5A.F1 to R9C5A.B0       n2298
+CTOF_DEL    ---     0.371       R9C5A.B0 to       R9C5A.F0 SLICE_75
+ROUTE         1     1.026       R9C5A.F0 to R7C5C.A1       n11
+CTOF_DEL    ---     0.371       R7C5C.A1 to       R7C5C.F1 SLICE_77
+ROUTE         2     1.042       R7C5C.F1 to R5C5A.A1       n2111
+CTOF_DEL    ---     0.371       R5C5A.A1 to       R5C5A.F1 SLICE_100
+ROUTE         1     0.703       R5C5A.F1 to R7C5D.CE       RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    7.739   (31.2% logic, 68.8% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R8C4C.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R7C5D.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 7.050ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i2  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)
+
+   Delay:               7.706ns  (26.5% logic, 73.5% route), 5 logic levels.
+
+ Constraint Details:
+
+      7.706ns physical path delay SLICE_4 to SLICE_56 meets
+     15.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 14.756ns) by 7.050ns
+
+ Physical Path Details:
+
+      Data path SLICE_4 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C3B.CLK to       R8C3B.Q0 SLICE_4 (from RCLK_c)
+ROUTE         2     1.563       R8C3B.Q0 to R7C4C.B1       FS_2
+CTOF_DEL    ---     0.371       R7C4C.B1 to       R7C4C.F1 SLICE_68
+ROUTE         1     1.487       R7C4C.F1 to R9C5A.A0       n2164
+CTOF_DEL    ---     0.371       R9C5A.A0 to       R9C5A.F0 SLICE_75
+ROUTE         1     1.026       R9C5A.F0 to R7C5C.A1       n11
+CTOF_DEL    ---     0.371       R7C5C.A1 to       R7C5C.F1 SLICE_77
+ROUTE         2     0.513       R7C5C.F1 to R7C5C.C0       n2111
+CTOF_DEL    ---     0.371       R7C5C.C0 to       R7C5C.F0 SLICE_77
+ROUTE         1     1.073       R7C5C.F0 to R7C4B.CE       RCLK_c_enable_7 (to RCLK_c)
+                  --------
+                    7.706   (26.5% logic, 73.5% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_4:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R8C3B.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.353       86.PADDI to R7C4B.CLK      RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:    8.725ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.904ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_368  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     6.180ns  (67.9% logic, 32.1% route), 2 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_55 and
+      6.180ns delay SLICE_55 to RA[10] (totaling 8.596ns) meets
+     12.500ns offset RCLK to RA[10] by 3.904ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to R2C4B.CLK      RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_55 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C4B.CLK to       R2C4B.Q0 SLICE_55 (from RCLK_c)
+ROUTE         1     1.984       R2C4B.Q0 to 87.PADDO       n974
+DOPAD_DEL   ---     3.636       87.PADDO to         87.PAD RA[10]
+                  --------
+                    6.180   (67.9% logic, 32.1% route), 2 logic levels.
+
+Report:    8.596ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 7.280ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_368  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     5.683ns  (73.0% logic, 27.0% route), 2 logic levels.
+
+   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
+
+ Constraint Details:
+      1.597ns delay RCLK to SLICE_55 and
+      5.683ns delay SLICE_55 to RA[10] (totaling 7.280ns) meets
+      0.000ns hold offset RCLK to RA[10] by 7.280ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.730       86.PADDI to R2C4B.CLK      RCLK_c
+                  --------
+                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
+
+      Data path SLICE_55 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C4B.CLK to       R2C4B.Q0 SLICE_55 (from RCLK_c)
+ROUTE         1     1.532       R2C4B.Q0 to 87.PADDO       n974
+DOPAD_DEL   ---     3.636       87.PADDO to         87.PAD RA[10]
+                  --------
+                    5.683   (73.0% logic, 27.0% route), 2 logic levels.
+
+Report:    7.280ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.684ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     8.400ns  (54.4% logic, 45.6% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      8.400ns delay SLICE_64 to RA[9] (totaling 10.816ns) meets
+     12.500ns offset RCLK to RA[9] by 1.684ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.781       R7C2B.Q0 to R3C5A.D1       nRowColSel
+CTOF_DEL    ---     0.371       R3C5A.D1 to       R3C5A.F1 SLICE_87
+ROUTE         1     2.052       R3C5A.F1 to 85.PADDO       RA_c_9
+DOPAD_DEL   ---     3.636       85.PADDO to         85.PAD RA[9]
+                  --------
+                    8.400   (54.4% logic, 45.6% route), 3 logic levels.
+
+Report:   10.816ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 9.193ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     7.596ns  (58.6% logic, 41.4% route), 3 logic levels.
+
+   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
+
+ Constraint Details:
+      1.597ns delay RCLK to SLICE_64 and
+      7.596ns delay SLICE_64 to RA[9] (totaling 9.193ns) meets
+      0.000ns hold offset RCLK to RA[9] by 9.193ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.730       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.534       R7C2B.Q0 to R3C5A.D1       nRowColSel
+CTOF_DEL    ---     0.301       R3C5A.D1 to       R3C5A.F1 SLICE_87
+ROUTE         1     1.610       R3C5A.F1 to 85.PADDO       RA_c_9
+DOPAD_DEL   ---     3.636       85.PADDO to         85.PAD RA[9]
+                  --------
+                    7.596   (58.6% logic, 41.4% route), 3 logic levels.
+
+Report:    9.193ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.988ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     7.096ns  (64.4% logic, 35.6% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      7.096ns delay SLICE_64 to RA[8] (totaling 9.512ns) meets
+     12.500ns offset RCLK to RA[8] by 2.988ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.712       R7C2B.Q0 to R2C2C.D0       nRowColSel
+CTOF_DEL    ---     0.371       R2C2C.D0 to       R2C2C.F0 SLICE_98
+ROUTE         1     0.817       R2C2C.F0 to 96.PADDO       RA_c_8
+DOPAD_DEL   ---     3.636       96.PADDO to         96.PAD RA[8]
+                  --------
+                    7.096   (64.4% logic, 35.6% route), 3 logic levels.
+
+Report:    9.512ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 8.119ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     6.522ns  (68.3% logic, 31.7% route), 3 logic levels.
+
+   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
+
+ Constraint Details:
+      1.597ns delay RCLK to SLICE_64 and
+      6.522ns delay SLICE_64 to RA[8] (totaling 8.119ns) meets
+      0.000ns hold offset RCLK to RA[8] by 8.119ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.730       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.424       R7C2B.Q0 to R2C2C.D0       nRowColSel
+CTOF_DEL    ---     0.301       R2C2C.D0 to       R2C2C.F0 SLICE_98
+ROUTE         1     0.646       R2C2C.F0 to 96.PADDO       RA_c_8
+DOPAD_DEL   ---     3.636       96.PADDO to         96.PAD RA[8]
+                  --------
+                    6.522   (68.3% logic, 31.7% route), 3 logic levels.
+
+Report:    8.119ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.977ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     7.107ns  (64.3% logic, 35.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      7.107ns delay SLICE_64 to RA[7] (totaling 9.523ns) meets
+     12.500ns offset RCLK to RA[7] by 2.977ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.880       R7C2B.Q0 to R7C2B.C1       nRowColSel
+CTOF_DEL    ---     0.371       R7C2B.C1 to       R7C2B.F1 SLICE_64
+ROUTE         1     1.660       R7C2B.F1 to 100.PADDO      RA_c_7
+DOPAD_DEL   ---     3.636      100.PADDO to        100.PAD RA[7]
+                  --------
+                    7.107   (64.3% logic, 35.7% route), 3 logic levels.
+
+Report:    9.523ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 8.063ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     6.466ns  (68.9% logic, 31.1% route), 3 logic levels.
+
+   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
+
+ Constraint Details:
+      1.597ns delay RCLK to SLICE_64 and
+      6.466ns delay SLICE_64 to RA[7] (totaling 8.063ns) meets
+      0.000ns hold offset RCLK to RA[7] by 8.063ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.730       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.726       R7C2B.Q0 to R7C2B.C1       nRowColSel
+CTOF_DEL    ---     0.301       R7C2B.C1 to       R7C2B.F1 SLICE_64
+ROUTE         1     1.288       R7C2B.F1 to 100.PADDO      RA_c_7
+DOPAD_DEL   ---     3.636      100.PADDO to        100.PAD RA[7]
+                  --------
+                    6.466   (68.9% logic, 31.1% route), 3 logic levels.
+
+Report:    8.063ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.822ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     8.262ns  (55.3% logic, 44.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      8.262ns delay SLICE_64 to RA[6] (totaling 10.678ns) meets
+     12.500ns offset RCLK to RA[6] by 1.822ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.712       R7C2B.Q0 to R2C2C.D1       nRowColSel
+CTOF_DEL    ---     0.371       R2C2C.D1 to       R2C2C.F1 SLICE_98
+ROUTE         1     1.983       R2C2C.F1 to 91.PADDO       RA_c_6
+DOPAD_DEL   ---     3.636       91.PADDO to         91.PAD RA[6]
+                  --------
+                    8.262   (55.3% logic, 44.7% route), 3 logic levels.
+
+Report:   10.678ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 9.044ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     7.447ns  (59.8% logic, 40.2% route), 3 logic levels.
+
+   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
+
+ Constraint Details:
+      1.597ns delay RCLK to SLICE_64 and
+      7.447ns delay SLICE_64 to RA[6] (totaling 9.044ns) meets
+      0.000ns hold offset RCLK to RA[6] by 9.044ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.730       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.424       R7C2B.Q0 to R2C2C.D1       nRowColSel
+CTOF_DEL    ---     0.301       R2C2C.D1 to       R2C2C.F1 SLICE_98
+ROUTE         1     1.571       R2C2C.F1 to 91.PADDO       RA_c_6
+DOPAD_DEL   ---     3.636       91.PADDO to         91.PAD RA[6]
+                  --------
+                    7.447   (59.8% logic, 40.2% route), 3 logic levels.
+
+Report:    9.044ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.738ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     7.346ns  (62.2% logic, 37.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      7.346ns delay SLICE_64 to RA[5] (totaling 9.762ns) meets
+     12.500ns offset RCLK to RA[5] by 2.738ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.119       R7C2B.Q0 to R6C2A.A1       nRowColSel
+CTOF_DEL    ---     0.371       R6C2A.A1 to       R6C2A.F1 SLICE_95
+ROUTE         1     1.660       R6C2A.F1 to 95.PADDO       RA_c_5
+DOPAD_DEL   ---     3.636       95.PADDO to         95.PAD RA[5]
+                  --------
+                    7.346   (62.2% logic, 37.8% route), 3 logic levels.
+
+Report:    9.762ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 8.252ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     6.655ns  (66.9% logic, 33.1% route), 3 logic levels.
+
+   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
+
+ Constraint Details:
+      1.597ns delay RCLK to SLICE_64 and
+      6.655ns delay SLICE_64 to RA[5] (totaling 8.252ns) meets
+      0.000ns hold offset RCLK to RA[5] by 8.252ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.730       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.915       R7C2B.Q0 to R6C2A.A1       nRowColSel
+CTOF_DEL    ---     0.301       R6C2A.A1 to       R6C2A.F1 SLICE_95
+ROUTE         1     1.288       R6C2A.F1 to 95.PADDO       RA_c_5
+DOPAD_DEL   ---     3.636       95.PADDO to         95.PAD RA[5]
+                  --------
+                    6.655   (66.9% logic, 33.1% route), 3 logic levels.
+
+Report:    8.252ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.279ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     7.805ns  (58.5% logic, 41.5% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      7.805ns delay SLICE_64 to RA[4] (totaling 10.221ns) meets
+     12.500ns offset RCLK to RA[4] by 2.279ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.712       R7C2B.Q0 to R2C2B.D1       nRowColSel
+CTOF_DEL    ---     0.371       R2C2B.D1 to       R2C2B.F1 SLICE_93
+ROUTE         1     1.526       R2C2B.F1 to 99.PADDO       RA_c_4
+DOPAD_DEL   ---     3.636       99.PADDO to         99.PAD RA[4]
+                  --------
+                    7.805   (58.5% logic, 41.5% route), 3 logic levels.
+
+Report:   10.221ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 8.638ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     7.041ns  (63.2% logic, 36.8% route), 3 logic levels.
+
+   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
+
+ Constraint Details:
+      1.597ns delay RCLK to SLICE_64 and
+      7.041ns delay SLICE_64 to RA[4] (totaling 8.638ns) meets
+      0.000ns hold offset RCLK to RA[4] by 8.638ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.730       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.424       R7C2B.Q0 to R2C2B.D1       nRowColSel
+CTOF_DEL    ---     0.301       R2C2B.D1 to       R2C2B.F1 SLICE_93
+ROUTE         1     1.165       R2C2B.F1 to 99.PADDO       RA_c_4
+DOPAD_DEL   ---     3.636       99.PADDO to         99.PAD RA[4]
+                  --------
+                    7.041   (63.2% logic, 36.8% route), 3 logic levels.
+
+Report:    8.638ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.800ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     8.284ns  (55.1% logic, 44.9% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      8.284ns delay SLICE_64 to RA[3] (totaling 10.700ns) meets
+     12.500ns offset RCLK to RA[3] by 1.800ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.733       R7C2B.Q0 to R2C3B.D1       nRowColSel
+CTOF_DEL    ---     0.371       R2C3B.D1 to       R2C3B.F1 SLICE_92
+ROUTE         1     1.984       R2C3B.F1 to 97.PADDO       RA_c_3
+DOPAD_DEL   ---     3.636       97.PADDO to         97.PAD RA[3]
+                  --------
+                    8.284   (55.1% logic, 44.9% route), 3 logic levels.
+
+Report:   10.700ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 9.042ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     7.445ns  (59.8% logic, 40.2% route), 3 logic levels.
+
+   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
+
+ Constraint Details:
+      1.597ns delay RCLK to SLICE_64 and
+      7.445ns delay SLICE_64 to RA[3] (totaling 9.042ns) meets
+      0.000ns hold offset RCLK to RA[3] by 9.042ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.730       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.461       R7C2B.Q0 to R2C3B.D1       nRowColSel
+CTOF_DEL    ---     0.301       R2C3B.D1 to       R2C3B.F1 SLICE_92
+ROUTE         1     1.532       R2C3B.F1 to 97.PADDO       RA_c_3
+DOPAD_DEL   ---     3.636       97.PADDO to         97.PAD RA[3]
+                  --------
+                    7.445   (59.8% logic, 40.2% route), 3 logic levels.
+
+Report:    9.042ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.967ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     7.117ns  (64.2% logic, 35.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      7.117ns delay SLICE_64 to RA[2] (totaling 9.533ns) meets
+     12.500ns offset RCLK to RA[2] by 2.967ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.733       R7C2B.Q0 to R2C3A.D0       nRowColSel
+CTOF_DEL    ---     0.371       R2C3A.D0 to       R2C3A.F0 SLICE_90
+ROUTE         1     0.817       R2C3A.F0 to 94.PADDO       RA_c_2
+DOPAD_DEL   ---     3.636       94.PADDO to         94.PAD RA[2]
+                  --------
+                    7.117   (64.2% logic, 35.8% route), 3 logic levels.
+
+Report:    9.533ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 8.156ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     6.559ns  (67.9% logic, 32.1% route), 3 logic levels.
+
+   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
+
+ Constraint Details:
+      1.597ns delay RCLK to SLICE_64 and
+      6.559ns delay SLICE_64 to RA[2] (totaling 8.156ns) meets
+      0.000ns hold offset RCLK to RA[2] by 8.156ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.730       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.461       R7C2B.Q0 to R2C3A.D0       nRowColSel
+CTOF_DEL    ---     0.301       R2C3A.D0 to       R2C3A.F0 SLICE_90
+ROUTE         1     0.646       R2C3A.F0 to 94.PADDO       RA_c_2
+DOPAD_DEL   ---     3.636       94.PADDO to         94.PAD RA[2]
+                  --------
+                    6.559   (67.9% logic, 32.1% route), 3 logic levels.
+
+Report:    8.156ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.967ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     7.117ns  (64.2% logic, 35.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      7.117ns delay SLICE_64 to RA[1] (totaling 9.533ns) meets
+     12.500ns offset RCLK to RA[1] by 2.967ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.733       R7C2B.Q0 to R2C3B.D0       nRowColSel
+CTOF_DEL    ---     0.371       R2C3B.D0 to       R2C3B.F0 SLICE_92
+ROUTE         1     0.817       R2C3B.F0 to 89.PADDO       RA_c_1
+DOPAD_DEL   ---     3.636       89.PADDO to         89.PAD RA[1]
+                  --------
+                    7.117   (64.2% logic, 35.8% route), 3 logic levels.
+
+Report:    9.533ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 8.156ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     6.559ns  (67.9% logic, 32.1% route), 3 logic levels.
+
+   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
+
+ Constraint Details:
+      1.597ns delay RCLK to SLICE_64 and
+      6.559ns delay SLICE_64 to RA[1] (totaling 8.156ns) meets
+      0.000ns hold offset RCLK to RA[1] by 8.156ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.730       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.461       R7C2B.Q0 to R2C3B.D0       nRowColSel
+CTOF_DEL    ---     0.301       R2C3B.D0 to       R2C3B.F0 SLICE_92
+ROUTE         1     0.646       R2C3B.F0 to 89.PADDO       RA_c_1
+DOPAD_DEL   ---     3.636       89.PADDO to         89.PAD RA[1]
+                  --------
+                    6.559   (67.9% logic, 32.1% route), 3 logic levels.
+
+Report:    8.156ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.988ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     7.096ns  (64.4% logic, 35.6% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      7.096ns delay SLICE_64 to RA[0] (totaling 9.512ns) meets
+     12.500ns offset RCLK to RA[0] by 2.988ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.712       R7C2B.Q0 to R2C2B.D0       nRowColSel
+CTOF_DEL    ---     0.371       R2C2B.D0 to       R2C2B.F0 SLICE_93
+ROUTE         1     0.817       R2C2B.F0 to 98.PADDO       RA_c_0
+DOPAD_DEL   ---     3.636       98.PADDO to         98.PAD RA[0]
+                  --------
+                    7.096   (64.4% logic, 35.6% route), 3 logic levels.
+
+Report:    9.512ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 8.119ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     6.522ns  (68.3% logic, 31.7% route), 3 logic levels.
+
+   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
+
+ Constraint Details:
+      1.597ns delay RCLK to SLICE_64 and
+      6.522ns delay SLICE_64 to RA[0] (totaling 8.119ns) meets
+      0.000ns hold offset RCLK to RA[0] by 8.119ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.730       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.424       R7C2B.Q0 to R2C2B.D0       nRowColSel
+CTOF_DEL    ---     0.301       R2C2B.D0 to       R2C2B.F0 SLICE_93
+ROUTE         1     0.646       R2C2B.F0 to 98.PADDO       RA_c_0
+DOPAD_DEL   ---     3.636       98.PADDO to         98.PAD RA[0]
+                  --------
+                    6.522   (68.3% logic, 31.7% route), 3 logic levels.
+
+Report:    8.119ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 5.071ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_364  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_60 and
+      5.013ns delay SLICE_60 to nRCS (totaling 7.429ns) meets
+     12.500ns offset RCLK to nRCS by 5.071ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to R2C5B.CLK      RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_60 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C5B.CLK to       R2C5B.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1     0.817       R2C5B.Q0 to 77.PADDO       nRCS_c
+DOPAD_DEL   ---     3.636       77.PADDO to         77.PAD nRCS
+                  --------
+                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
+
+Report:    7.429ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 6.394ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_364  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     4.797ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
+
+ Constraint Details:
+      1.597ns delay RCLK to SLICE_60 and
+      4.797ns delay SLICE_60 to nRCS (totaling 6.394ns) meets
+      0.000ns hold offset RCLK to nRCS by 6.394ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.730       86.PADDI to R2C5B.CLK      RCLK_c
+                  --------
+                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
+
+      Data path SLICE_60 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C5B.CLK to       R2C5B.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1     0.646       R2C5B.Q0 to 77.PADDO       nRCS_c
+DOPAD_DEL   ---     3.636       77.PADDO to         77.PAD nRCS
+                  --------
+                    4.797   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    6.394ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.806ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_363  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     6.278ns  (66.8% logic, 33.2% route), 2 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_34 and
+      6.278ns delay SLICE_34 to RCKE (totaling 8.694ns) meets
+     12.500ns offset RCLK to RCKE by 3.806ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to R6C5B.CLK      RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_34 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R6C5B.CLK to       R6C5B.Q0 SLICE_34 (from RCLK_c)
+ROUTE         4     2.082       R6C5B.Q0 to 82.PADDO       RCKE_c
+DOPAD_DEL   ---     3.636       82.PADDO to         82.PAD RCKE
+                  --------
+                    6.278   (66.8% logic, 33.2% route), 2 logic levels.
+
+Report:    8.694ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 7.385ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_363  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     5.788ns  (71.7% logic, 28.3% route), 2 logic levels.
+
+   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
+
+ Constraint Details:
+      1.597ns delay RCLK to SLICE_34 and
+      5.788ns delay SLICE_34 to RCKE (totaling 7.385ns) meets
+      0.000ns hold offset RCLK to RCKE by 7.385ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.730       86.PADDI to R6C5B.CLK      RCLK_c
+                  --------
+                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
+
+      Data path SLICE_34 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R6C5B.CLK to       R6C5B.Q0 SLICE_34 (from RCLK_c)
+ROUTE         4     1.637       R6C5B.Q0 to 82.PADDO       RCKE_c
+DOPAD_DEL   ---     3.636       82.PADDO to         82.PAD RCKE
+                  --------
+                    5.788   (71.7% logic, 28.3% route), 2 logic levels.
+
+Report:    7.385ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 5.071ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_367  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_63 and
+      5.013ns delay SLICE_63 to nRWE (totaling 7.429ns) meets
+     12.500ns offset RCLK to nRWE by 5.071ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to R3C5B.CLK      RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C5B.CLK to       R3C5B.Q0 SLICE_63 (from RCLK_c)
+ROUTE         1     0.817       R3C5B.Q0 to 72.PADDO       nRWE_c
+DOPAD_DEL   ---     3.636       72.PADDO to         72.PAD nRWE
+                  --------
+                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
+
+Report:    7.429ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 6.394ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_367  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     4.797ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
+
+ Constraint Details:
+      1.597ns delay RCLK to SLICE_63 and
+      4.797ns delay SLICE_63 to nRWE (totaling 6.394ns) meets
+      0.000ns hold offset RCLK to nRWE by 6.394ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.730       86.PADDI to R3C5B.CLK      RCLK_c
+                  --------
+                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
+
+      Data path SLICE_63 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R3C5B.CLK to       R3C5B.Q0 SLICE_63 (from RCLK_c)
+ROUTE         1     0.646       R3C5B.Q0 to 72.PADDO       nRWE_c
+DOPAD_DEL   ---     3.636       72.PADDO to         72.PAD nRWE
+                  --------
+                    4.797   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    6.394ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.360ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_365  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     5.724ns  (73.3% logic, 26.7% route), 2 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_61 and
+      5.724ns delay SLICE_61 to nRRAS (totaling 8.140ns) meets
+     12.500ns offset RCLK to nRRAS by 4.360ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to R2C4C.CLK      RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_61 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C4C.CLK to       R2C4C.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2     1.528       R2C4C.Q0 to 73.PADDO       nRRAS_c
+DOPAD_DEL   ---     3.636       73.PADDO to         73.PAD nRRAS
+                  --------
+                    5.724   (73.3% logic, 26.7% route), 2 logic levels.
+
+Report:    8.140ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 6.920ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_365  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     5.323ns  (78.0% logic, 22.0% route), 2 logic levels.
+
+   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
+
+ Constraint Details:
+      1.597ns delay RCLK to SLICE_61 and
+      5.323ns delay SLICE_61 to nRRAS (totaling 6.920ns) meets
+      0.000ns hold offset RCLK to nRRAS by 6.920ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.730       86.PADDI to R2C4C.CLK      RCLK_c
+                  --------
+                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
+
+      Data path SLICE_61 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C4C.CLK to       R2C4C.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2     1.172       R2C4C.Q0 to 73.PADDO       nRRAS_c
+DOPAD_DEL   ---     3.636       73.PADDO to         73.PAD nRRAS
+                  --------
+                    5.323   (78.0% logic, 22.0% route), 2 logic levels.
+
+Report:    6.920ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.904ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_366  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     6.180ns  (67.9% logic, 32.1% route), 2 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_58 and
+      6.180ns delay SLICE_58 to nRCAS (totaling 8.596ns) meets
+     12.500ns offset RCLK to nRCAS by 3.904ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to R2C4A.CLK      RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_58 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C4A.CLK to       R2C4A.Q0 SLICE_58 (from RCLK_c)
+ROUTE         1     1.984       R2C4A.Q0 to 78.PADDO       nRCAS_c
+DOPAD_DEL   ---     3.636       78.PADDO to         78.PAD nRCAS
+                  --------
+                    6.180   (67.9% logic, 32.1% route), 2 logic levels.
+
+Report:    8.596ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 7.280ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_366  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     5.683ns  (73.0% logic, 27.0% route), 2 logic levels.
+
+   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
+
+ Constraint Details:
+      1.597ns delay RCLK to SLICE_58 and
+      5.683ns delay SLICE_58 to nRCAS (totaling 7.280ns) meets
+      0.000ns hold offset RCLK to nRCAS by 7.280ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.730       86.PADDI to R2C4A.CLK      RCLK_c
+                  --------
+                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
+
+      Data path SLICE_58 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C4A.CLK to       R2C4A.Q0 SLICE_58 (from RCLK_c)
+ROUTE         1     1.532       R2C4A.Q0 to 78.PADDO       nRCAS_c
+DOPAD_DEL   ---     3.636       78.PADDO to         78.PAD nRCAS
+                  --------
+                    5.683   (73.0% logic, 27.0% route), 2 logic levels.
+
+Report:    7.280ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.919ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     7.165ns  (63.7% logic, 36.3% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      7.165ns delay SLICE_64 to RDQMH (totaling 9.581ns) meets
+     12.500ns offset RCLK to RDQMH by 2.919ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.781       R7C2B.Q0 to R3C5A.D0       nRowColSel
+CTOF_DEL    ---     0.371       R3C5A.D0 to       R3C5A.F0 SLICE_87
+ROUTE         1     0.817       R3C5A.F0 to 76.PADDO       RDQMH_c
+DOPAD_DEL   ---     3.636       76.PADDO to         76.PAD RDQMH
+                  --------
+                    7.165   (63.7% logic, 36.3% route), 3 logic levels.
+
+Report:    9.581ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 8.229ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     6.632ns  (67.1% logic, 32.9% route), 3 logic levels.
+
+   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
+
+ Constraint Details:
+      1.597ns delay RCLK to SLICE_64 and
+      6.632ns delay SLICE_64 to RDQMH (totaling 8.229ns) meets
+      0.000ns hold offset RCLK to RDQMH by 8.229ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.730       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.534       R7C2B.Q0 to R3C5A.D0       nRowColSel
+CTOF_DEL    ---     0.301       R3C5A.D0 to       R3C5A.F0 SLICE_87
+ROUTE         1     0.646       R3C5A.F0 to 76.PADDO       RDQMH_c
+DOPAD_DEL   ---     3.636       76.PADDO to         76.PAD RDQMH
+                  --------
+                    6.632   (67.1% logic, 32.9% route), 3 logic levels.
+
+Report:    8.229ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.415ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     7.669ns  (59.6% logic, 40.4% route), 3 logic levels.
+
+   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      2.416ns delay RCLK to SLICE_64 and
+      7.669ns delay SLICE_64 to RDQML (totaling 10.085ns) meets
+     12.500ns offset RCLK to RDQML by 2.415ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.353       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.119       R7C2B.Q0 to R6C2A.A0       nRowColSel
+CTOF_DEL    ---     0.371       R6C2A.A0 to       R6C2A.F0 SLICE_95
+ROUTE         1     1.983       R6C2A.F0 to 61.PADDO       RDQML_c
+DOPAD_DEL   ---     3.636       61.PADDO to         61.PAD RDQML
+                  --------
+                    7.669   (59.6% logic, 40.4% route), 3 logic levels.
+
+Report:   10.085ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 8.535ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     6.938ns  (64.2% logic, 35.8% route), 3 logic levels.
+
+   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
+
+ Constraint Details:
+      1.597ns delay RCLK to SLICE_64 and
+      6.938ns delay SLICE_64 to RDQML (totaling 8.535ns) meets
+      0.000ns hold offset RCLK to RDQML by 8.535ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.730       86.PADDI to R7C2B.CLK      RCLK_c
+                  --------
+                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.915       R7C2B.Q0 to R6C2A.A0       nRowColSel
+CTOF_DEL    ---     0.301       R6C2A.A0 to       R6C2A.F0 SLICE_95
+ROUTE         1     1.571       R6C2A.F0 to 61.PADDO       RDQML_c
+DOPAD_DEL   ---     3.636       61.PADDO to         61.PAD RDQML
+                  --------
+                    6.938   (64.2% logic, 35.8% route), 3 logic levels.
+
+Report:    8.535ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |   350.000 ns|    24.062 ns|   7  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 15.000000 ns  ;     |    15.000 ns|     8.725 ns|   6  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     8.596 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     7.280 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.816 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     9.193 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     9.512 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.119 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     9.523 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.063 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.678 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     9.044 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     9.762 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.252 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.221 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.638 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.700 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     9.042 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     9.533 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.156 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     9.533 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.156 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     9.512 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.119 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     7.429 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     6.394 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     8.694 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     7.385 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     7.429 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     6.394 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     8.140 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     6.920 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     8.596 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     7.280 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     9.581 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.229 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.085 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.535 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
+   Covered under: PERIOD NET "RCLK_c" 15.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 538 paths, 6 nets, and 436 connections (70.89% coverage)
+
diff --git a/CPLD/LCMXO/LCMXO256C/impl1/automake.log b/CPLD/LCMXO/LCMXO256C/impl1/automake.log
new file mode 100644
index 0000000..e197df1
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO256C/impl1/automake.log
@@ -0,0 +1,528 @@
+
+ibisgen "RAM2GS_LCMXO256C_impl1.pad" "C:/lscc/diamond/3.12/cae_library/ibis/machxo.ibs"   
+IBIS Models Generator: Lattice Diamond (64-bit) 3.12.0.240.2
+
+Mon Aug 16 21:36:25 2021
+
+Comp: CROW[0]
+ Site: 32
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: CROW[1]
+ Site: 34
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: Din[0]
+ Site: 21
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: Din[1]
+ Site: 15
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: Din[2]
+ Site: 14
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: Din[3]
+ Site: 16
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: Din[4]
+ Site: 18
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: Din[5]
+ Site: 17
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: Din[6]
+ Site: 20
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: Din[7]
+ Site: 19
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: Dout[0]
+ Site: 1
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[1]
+ Site: 7
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[2]
+ Site: 8
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[3]
+ Site: 6
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[4]
+ Site: 4
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[5]
+ Site: 5
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[6]
+ Site: 2
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[7]
+ Site: 3
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: LED
+ Site: 57
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=16mA 
+ SLEW=SLOW 
+-----------------------
+Comp: MAin[0]
+ Site: 23
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: MAin[1]
+ Site: 38
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: MAin[2]
+ Site: 37
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: MAin[3]
+ Site: 47
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: MAin[4]
+ Site: 46
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: MAin[5]
+ Site: 45
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: MAin[6]
+ Site: 49
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: MAin[7]
+ Site: 44
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: MAin[8]
+ Site: 50
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: MAin[9]
+ Site: 51
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: PHI2
+ Site: 39
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: RA[0]
+ Site: 98
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[10]
+ Site: 87
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[11]
+ Site: 79
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[1]
+ Site: 89
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[2]
+ Site: 94
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[3]
+ Site: 97
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[4]
+ Site: 99
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[5]
+ Site: 95
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[6]
+ Site: 91
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[7]
+ Site: 100
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[8]
+ Site: 96
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[9]
+ Site: 85
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RBA[0]
+ Site: 63
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RBA[1]
+ Site: 83
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RCKE
+ Site: 82
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RCLK
+ Site: 86
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: RDQMH
+ Site: 76
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RDQML
+ Site: 61
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RD[0]
+ Site: 64
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[1]
+ Site: 65
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[2]
+ Site: 66
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[3]
+ Site: 67
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[4]
+ Site: 68
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[5]
+ Site: 69
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[6]
+ Site: 70
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[7]
+ Site: 71
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: UFMCLK
+ Site: 58
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: UFMSDI
+ Site: 56
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: UFMSDO
+ Site: 55
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: nCCAS
+ Site: 27
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: nCRAS
+ Site: 43
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: nFWE
+ Site: 22
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: nRCAS
+ Site: 78
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: nRCS
+ Site: 77
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: nRRAS
+ Site: 73
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: nRWE
+ Site: 72
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: nUFMCS
+ Site: 53
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Created design models.
+
+
+Generating: C:\Users\Dog\Documents\GitHub\RAM2GS\CPLD\LCMXO\LCMXO256C\impl1\IBIS\RAM2GS_LCMXO256C_im~.ibs
+
+
+    
+
+tmcheck -par "RAM2GS_LCMXO256C_impl1.par" 
+
+bitgen -w "RAM2GS_LCMXO256C_impl1.ncd" -f "RAM2GS_LCMXO256C_impl1.t2b" "RAM2GS_LCMXO256C_impl1.prf"
+
+
+BITGEN: Bitstream Generator Diamond (64-bit) 3.12.0.240.2
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+
+Loading design for application Bitgen from file RAM2GS_LCMXO256C_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: 3
+Loading device for application Bitgen from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+
+Running DRC.
+DRC detected 0 errors and 0 warnings.
+Reading Preference File from RAM2GS_LCMXO256C_impl1.prf.
+
+Preference Summary:
++---------------------------------+---------------------------------+
+|  Preference                     |  Current Setting                |
++---------------------------------+---------------------------------+
+|                  CONFIG_SECURE  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                          INBUF  |                           ON**  |
++---------------------------------+---------------------------------+
+|                             ES  |                           No**  |
++---------------------------------+---------------------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+
+Creating bit map...
+Saving bit stream in "RAM2GS_LCMXO256C_impl1.bit".
+Total CPU Time: 0 secs 
+Total REAL Time: 0 secs 
+Peak Memory Usage: 44 MB
+
+ddtcmd -dev LCMXO256C-XXT100 -if "RAM2GS_LCMXO256C_impl1.bit" -oft -jed -of "RAM2GS_LCMXO256C_impl1.jed"  -comment "RAM2GS_LCMXO256C_impl1.alt" 
+Lattice Diamond Deployment Tool 3.12 Command Line
+
+Loading Programmer Device Database...
+
+Generating JED.....
+Device Name: LCMXO256C-XXT100
+Reading Input File: RAM2GS_LCMXO256C_impl1.bit
+Output File: RAM2GS_LCMXO256C_impl1.jed
+Comment file RAM2GS_LCMXO256C_impl1.alt.
+Generating JEDEC.....
+File RAM2GS_LCMXO256C_impl1.jed generated successfully.
+Lattice Diamond Deployment Tool has exited successfully.
+
diff --git a/CPLD/LCMXO/LCMXO256C/impl1/hdla_gen_hierarchy.html b/CPLD/LCMXO/LCMXO256C/impl1/hdla_gen_hierarchy.html
new file mode 100644
index 0000000..0b86833
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO256C/impl1/hdla_gen_hierarchy.html
@@ -0,0 +1,9 @@
+         	                                   	                                                	                                                 	                                                  	
    Setting log file to 'C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/impl1/hdla_gen_hierarchy.html'.
+Starting: parse design source files
+(VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v'
+(VERI-1482) Analyzing Verilog file 'C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v'
+INFO - C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v(1,8-1,14) (VERI-1018) compiling module 'RAM2GS'
+INFO - C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v(1,1-397,10) (VERI-9000) elaborating module 'RAM2GS'
+Done: design load finished with (0) errors, and (0) warnings
+
+
    
\ No newline at end of file
diff --git a/CPLD/LCMXO/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1.ior b/CPLD/LCMXO/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1.ior
new file mode 100644
index 0000000..68dddcc
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1.ior
@@ -0,0 +1,137 @@
+Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: 4
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: 5
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: M
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+// Design: RAM2GS
+// Package: TQFP100
+// ncd File: ram2gs_lcmxo256c_impl1.ncd
+// Version: Diamond (64-bit) 3.12.0.240.2
+// Written on Mon Aug 16 21:32:34 2021
+// M: Minimum Performance Grade
+// iotiming RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml
+
+I/O Timing Report (All units are in ns)
+
+Worst Case Results across Performance Grades (M, 5, 4, 3):
+
+// Input Setup and Hold Times
+
+Port    Clock Edge  Setup Performance_Grade  Hold Performance_Grade
+----------------------------------------------------------------------
+CROW[0] nCRAS F     0.215      3       1.805     3
+CROW[1] nCRAS F    -0.050      M       2.105     3
+Din[0]  PHI2  F     5.083      3       2.097     3
+Din[0]  nCCAS F    -0.020      M       2.133     3
+Din[1]  PHI2  F     3.519      3       2.454     3
+Din[1]  nCCAS F    -0.146      M       2.462     3
+Din[2]  PHI2  F     4.416      3       2.660     3
+Din[2]  nCCAS F     0.272      3       1.853     3
+Din[3]  PHI2  F     5.627      3       2.084     3
+Din[3]  nCCAS F    -0.024      M       2.144     3
+Din[4]  PHI2  F     4.808      3       2.117     3
+Din[4]  nCCAS F     0.350      3       1.766     3
+Din[5]  PHI2  F     5.446      3       2.212     3
+Din[5]  nCCAS F     0.435      3       1.708     3
+Din[6]  PHI2  F     5.339      3       1.487     3
+Din[6]  nCCAS F    -0.140      M       2.452     3
+Din[7]  PHI2  F     4.546      3       1.555     3
+Din[7]  nCCAS F    -0.016      M       2.122     3
+MAin[0] PHI2  F     4.027      3       0.711     3
+MAin[0] nCRAS F     1.132      3       0.987     3
+MAin[1] PHI2  F     4.032      3       1.734     3
+MAin[1] nCRAS F     0.704      3       1.373     3
+MAin[2] PHI2  F    10.358      3      -0.773     M
+MAin[2] nCRAS F    -0.202      M       2.529     3
+MAin[3] PHI2  F    10.442      3      -0.829     M
+MAin[3] nCRAS F     0.186      3       1.819     3
+MAin[4] PHI2  F    10.311      3      -0.765     M
+MAin[4] nCRAS F     0.569      3       1.506     3
+MAin[5] PHI2  F     7.007      3       0.178     3
+MAin[5] nCRAS F     0.186      3       1.819     3
+MAin[6] PHI2  F     9.786      3      -0.641     M
+MAin[6] nCRAS F     0.177      3       1.829     3
+MAin[7] PHI2  F    10.008      3      -0.718     M
+MAin[7] nCRAS F    -0.092      M       2.222     3
+MAin[8] nCRAS F    -0.202      M       2.532     3
+MAin[9] nCRAS F     0.228      3       1.797     3
+PHI2    RCLK  R     5.091      3      -0.759     M
+UFMSDO  RCLK  R     2.219      3      -0.104     M
+nCCAS   RCLK  R     3.820      3      -0.611     M
+nCCAS   nCRAS F     1.538      3       0.708     3
+nCRAS   RCLK  R     4.749      3      -0.670     M
+nFWE    PHI2  F     5.301      3       1.647     3
+nFWE    nCRAS F     1.049      3       1.128     3
+
+
+// Clock to Output Delay
+
+Port   Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
+------------------------------------------------------------------------
+LED    RCLK  R    11.669         3        3.051          M
+RA[0]  RCLK  R     9.674         3        2.492          M
+RA[0]  nCRAS F    12.127         3        3.067          M
+RA[10] RCLK  R     8.596         3        2.220          M
+RA[11] PHI2  R     9.987         3        2.559          M
+RA[1]  RCLK  R     8.766         3        2.284          M
+RA[1]  nCRAS F    11.652         3        2.982          M
+RA[2]  RCLK  R    10.062         3        2.599          M
+RA[2]  nCRAS F    12.947         3        3.306          M
+RA[3]  RCLK  R     9.933         3        2.555          M
+RA[3]  nCRAS F    12.783         3        3.240          M
+RA[4]  RCLK  R     8.504         3        2.219          M
+RA[4]  nCRAS F    11.513         3        2.948          M
+RA[5]  RCLK  R     9.609         3        2.481          M
+RA[5]  nCRAS F    11.870         3        3.010          M
+RA[6]  RCLK  R    10.001         3        2.579          M
+RA[6]  nCRAS F    12.947         3        3.292          M
+RA[7]  RCLK  R    10.255         3        2.652          M
+RA[7]  nCRAS F    12.177         3        3.089          M
+RA[8]  RCLK  R     8.896         3        2.316          M
+RA[8]  nCRAS F    11.417         3        2.920          M
+RA[9]  RCLK  R     8.766         3        2.284          M
+RA[9]  nCRAS F    11.617         3        2.957          M
+RBA[0] nCRAS F     9.698         3        2.483          M
+RBA[1] nCRAS F    11.425         3        2.916          M
+RCKE   RCLK  R     9.080         3        2.363          M
+RDQMH  RCLK  R     9.475         3        2.443          M
+RDQML  RCLK  R    10.477         3        2.713          M
+RD[0]  nCCAS F    11.252         3        2.942          M
+RD[1]  nCCAS F    11.963         3        3.100          M
+RD[2]  nCCAS F    12.880         3        3.336          M
+RD[3]  nCCAS F    12.422         3        3.224          M
+RD[4]  nCCAS F    11.252         3        2.942          M
+RD[5]  nCCAS F    12.423         3        3.212          M
+RD[6]  nCCAS F    12.979         3        3.375          M
+RD[7]  nCCAS F    12.914         3        3.350          M
+UFMCLK RCLK  R     8.007         3        2.126          M
+UFMSDI RCLK  R     8.007         3        2.126          M
+nRCAS  RCLK  R     8.595         3        2.232          M
+nRCS   RCLK  R     7.429         3        1.949          M
+nRRAS  RCLK  R     8.615         3        2.236          M
+nRWE   RCLK  R     7.429         3        1.949          M
+nUFMCS RCLK  R     9.193         3        2.413          M
+WARNING: you must also run trce with hold speed: 3
+WARNING: you must also run trce with setup speed: M
diff --git a/CPLD/LCMXO/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1_trce.asd b/CPLD/LCMXO/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1_trce.asd
new file mode 100644
index 0000000..7b7fee7
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1_trce.asd
@@ -0,0 +1,91 @@
+[ActiveSupport TRCE]
+; Setup Analysis
+Period_0 = 26.150 ns (350.000 ns);
+Period_1 = 2.000 ns (350.000 ns);
+Period_2 = 2.000 ns (350.000 ns);
+Period_3 = 8.434 ns (16.000 ns);
+Tco_4 = - (-);
+Tco_5 = - (-);
+Tco_6 = - (-);
+Tco_7 = - (-);
+Tco_8 = - (-);
+Tco_9 = - (-);
+Tco_10 = - (-);
+Tco_11 = - (-);
+Tco_12 = - (-);
+Tco_13 = - (-);
+Tco_14 = - (-);
+Tco_15 = - (-);
+Tco_16 = 8.596 ns (12.500 ns);
+Tco_17 = 8.766 ns (12.500 ns);
+Tco_18 = 8.896 ns (12.500 ns);
+Tco_19 = 10.255 ns (12.500 ns);
+Tco_20 = 10.001 ns (12.500 ns);
+Tco_21 = 9.609 ns (12.500 ns);
+Tco_22 = 8.504 ns (12.500 ns);
+Tco_23 = 9.933 ns (12.500 ns);
+Tco_24 = 10.062 ns (12.500 ns);
+Tco_25 = 8.766 ns (12.500 ns);
+Tco_26 = 9.674 ns (12.500 ns);
+Tco_27 = 7.429 ns (12.500 ns);
+Tco_28 = 9.080 ns (12.500 ns);
+Tco_29 = 7.429 ns (12.500 ns);
+Tco_30 = 8.615 ns (12.500 ns);
+Tco_31 = 8.595 ns (12.500 ns);
+Tco_32 = 9.475 ns (12.500 ns);
+Tco_33 = 10.477 ns (12.500 ns);
+Tco_34 = - (-);
+Tco_35 = - (-);
+Tco_36 = - (-);
+Tco_37 = - (-);
+Tco_38 = - (-);
+Tco_39 = - (-);
+Tco_40 = - (-);
+Failed = 0 (Total 41);
+Clock_ports = 4;
+Clock_nets = 4;
+; Hold Analysis
+Period_0 = - (-);
+Period_1 = - (-);
+Period_2 = - (-);
+Period_3 = - (-);
+Tco_4 = - (-);
+Tco_5 = - (-);
+Tco_6 = - (-);
+Tco_7 = - (-);
+Tco_8 = - (-);
+Tco_9 = - (-);
+Tco_10 = - (-);
+Tco_11 = - (-);
+Tco_12 = - (-);
+Tco_13 = - (-);
+Tco_14 = - (-);
+Tco_15 = - (-);
+Tco_16 = 2.220 ns (0.000 ns);
+Tco_17 = 2.284 ns (0.000 ns);
+Tco_18 = 2.316 ns (0.000 ns);
+Tco_19 = 2.652 ns (0.000 ns);
+Tco_20 = 2.579 ns (0.000 ns);
+Tco_21 = 2.481 ns (0.000 ns);
+Tco_22 = 2.219 ns (0.000 ns);
+Tco_23 = 2.555 ns (0.000 ns);
+Tco_24 = 2.599 ns (0.000 ns);
+Tco_25 = 2.284 ns (0.000 ns);
+Tco_26 = 2.492 ns (0.000 ns);
+Tco_27 = 1.949 ns (0.000 ns);
+Tco_28 = 2.363 ns (0.000 ns);
+Tco_29 = 1.949 ns (0.000 ns);
+Tco_30 = 2.236 ns (0.000 ns);
+Tco_31 = 2.232 ns (0.000 ns);
+Tco_32 = 2.443 ns (0.000 ns);
+Tco_33 = 2.713 ns (0.000 ns);
+Tco_34 = - (-);
+Tco_35 = - (-);
+Tco_36 = - (-);
+Tco_37 = - (-);
+Tco_38 = - (-);
+Tco_39 = - (-);
+Tco_40 = - (-);
+Failed = 0 (Total 41);
+Clock_ports = 4;
+Clock_nets = 4;
diff --git a/CPLD/LCMXO/LCMXO256C/impl1/synthesis.log b/CPLD/LCMXO/LCMXO256C/impl1/synthesis.log
new file mode 100644
index 0000000..70a7a9b
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO256C/impl1/synthesis.log
@@ -0,0 +1,239 @@
+synthesis:  version Diamond (64-bit) 3.12.0.240.2
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Mon Aug 16 21:32:25 2021
+
+
+Command Line:  synthesis -f RAM2GS_LCMXO256C_impl1_lattice.synproj -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml 
+
+Synthesis options:
+The -a option is MachXO.
+The -s option is 3.
+The -t option is TQFP100.
+The -d option is LCMXO256C.
+Using package TQFP100.
+Using performance grade 3.
+                                                          
+
+##########################################################
+
+### Lattice Family : MachXO
+
+### Device  : LCMXO256C
+
+### Package : TQFP100
+
+### Speed   : 3
+
+##########################################################
+
+                                                          
+
+INFO - synthesis: User-Selected Strategy Settings
+Optimization goal = Balanced
+Top-level module name = RAM2GS.
+Target frequency = 200.000000 MHz.
+Maximum fanout = 1000.
+Timing path count = 3
+BRAM utilization = 100.000000 %
+DSP usage = true
+DSP utilization = 100.000000 %
+fsm_encoding_style = auto
+resolve_mixed_drivers = 0
+fix_gated_clocks = 1
+
+Mux style = Auto
+Use Carry Chain = true
+carry_chain_length = 0
+Loop Limit = 1950.
+Use IO Insertion = TRUE
+Use IO Reg = AUTO
+
+Resource Sharing = TRUE
+Propagate Constants = TRUE
+Remove Duplicate Registers = TRUE
+force_gsr = auto
+ROM style = auto
+RAM style = auto
+The -comp option is FALSE.
+The -syn option is FALSE.
+-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C (searchpath added)
+-p C:/lscc/diamond/3.12/ispfpga/mj5g00/data (searchpath added)
+-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/impl1 (searchpath added)
+-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C (searchpath added)
+Verilog design file = C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v
+NGD file = RAM2GS_LCMXO256C_impl1.ngd
+-sdc option: SDC file input not used.
+-lpf option: Output file option is ON.
+Hardtimer checking is enabled (default). The -dt option is not used.
+The -r option is OFF. [ Remove LOC Properties is OFF. ]
+Technology check ok...
+
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
+Compile design.
+Compile Design Begin
+Analyzing Verilog file c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v. VERI-1482
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
+Top module name (Verilog): RAM2GS
+INFO - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(1): compiling module RAM2GS. VERI-1018
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131): expression size 32 truncated to fit in target size 2. VERI-1209
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136): expression size 32 truncated to fit in target size 18. VERI-1209
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263): expression size 32 truncated to fit in target size 4. VERI-1209
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+Loading device for application map from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.19.
+Top-level module name = RAM2GS.
+INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 0000 -> 0000000000000001
+
+ 0001 -> 0000000000000010
+
+ 0010 -> 0000000000000100
+
+ 0011 -> 0000000000001000
+
+ 0100 -> 0000000000010000
+
+ 0101 -> 0000000000100000
+
+ 0110 -> 0000000001000000
+
+ 0111 -> 0000000010000000
+
+ 1000 -> 0000000100000000
+
+ 1001 -> 0000001000000000
+
+ 1010 -> 0000010000000000
+
+ 1011 -> 0000100000000000
+
+ 1100 -> 0001000000000000
+
+ 1101 -> 0010000000000000
+
+ 1110 -> 0100000000000000
+
+ 1111 -> 1000000000000000
+
+INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 00 -> 0001
+
+ 01 -> 0010
+
+ 10 -> 0100
+
+ 11 -> 1000
+
+
+
+
+GSR will not be inferred because no asynchronous signal was found in the netlist.
+WARNING - synthesis: Initial value found on instance C1Submitted_379 will be ignored.
+Applying 200.000000 MHz constraint to all clocks
+
+WARNING - synthesis: No user .sdc file.
+Results of NGD DRC are available in RAM2GS_drc.log.
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+All blocks are expanded and NGD expansion is successful.
+Writing NGD file RAM2GS_LCMXO256C_impl1.ngd.
+
+################### Begin Area Report (RAM2GS)######################
+Number of register bits => 102 of 490 (20 % )
+BB => 8
+CCU2 => 9
+FD1P3AX => 28
+FD1P3AY => 3
+FD1P3IX => 2
+FD1P3JX => 1
+FD1S3AX => 47
+FD1S3AY => 1
+FD1S3IX => 16
+FD1S3JX => 4
+GSR => 1
+IB => 26
+INV => 3
+OB => 33
+ORCALUT4 => 116
+PFUMX => 3
+################### End Area Report ##################
+
+################### Begin BlackBox Report ######################
+TSALL => 1
+################### End BlackBox Report ##################
+
+################### Begin Clock Report ######################
+Clock Nets
+Number of Clocks: 4
+  Net : RCLK_c, loads : 62
+  Net : PHI2_c, loads : 11
+  Net : nCCAS_c, loads : 2
+  Net : nCRAS_c, loads : 2
+Clock Enable Nets
+Number of Clock Enables: 13
+Top 10 highest fanout Clock Enables:
+  Net : RCLK_c_enable_23, loads : 16
+  Net : RCLK_c_enable_4, loads : 3
+  Net : PHI2_N_114_enable_7, loads : 3
+  Net : RCLK_c_enable_24, loads : 2
+  Net : PHI2_N_114_enable_6, loads : 2
+  Net : RCLK_c_enable_7, loads : 1
+  Net : RCLK_c_enable_6, loads : 1
+  Net : RCLK_c_enable_3, loads : 1
+  Net : PHI2_N_114_enable_2, loads : 1
+  Net : PHI2_N_114_enable_1, loads : 1
+Highest fanout non-clock nets
+Top 10 highest fanout non-clock nets:
+  Net : InitReady, loads : 17
+  Net : RCLK_c_enable_23, loads : 16
+  Net : RASr2, loads : 15
+  Net : nCRAS_N_9, loads : 15
+  Net : nRowColSel_N_35, loads : 14
+  Net : nRowColSel, loads : 13
+  Net : Ready, loads : 13
+  Net : n2307, loads : 13
+  Net : nCCAS_N_3, loads : 10
+  Net : Din_c_6, loads : 9
+################### End Clock Report ##################
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk1 [get_nets PHI2_c]                  |  200.000 MHz|   38.826 MHz|     7 *
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets RCLK_c]                  |  200.000 MHz|   88.566 MHz|     6 *
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+2 constraints not met.
+
+
+Peak Memory Usage: 50.406  MB
+
+--------------------------------------------------------------
+Elapsed CPU time for LSE flow : 0.530  secs
+--------------------------------------------------------------
diff --git a/CPLD/LCMXO/LCMXO256C/impl1/synthesis_lse.html b/CPLD/LCMXO/LCMXO256C/impl1/synthesis_lse.html
new file mode 100644
index 0000000..8faa0b2
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO256C/impl1/synthesis_lse.html
@@ -0,0 +1,304 @@
+
+Synthesis and Ngdbuild Report
+
+
+
    Synthesis and Ngdbuild  Report
+synthesis:  version Diamond (64-bit) 3.12.0.240.2
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Mon Aug 16 21:32:25 2021
+
+
+Command Line:  synthesis -f RAM2GS_LCMXO256C_impl1_lattice.synproj -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml 
+
+Synthesis options:
+The -a option is MachXO.
+The -s option is 3.
+The -t option is TQFP100.
+The -d option is LCMXO256C.
+Using package TQFP100.
+Using performance grade 3.
+                                                          
+
+##########################################################
+
+### Lattice Family : MachXO
+
+### Device  : LCMXO256C
+
+### Package : TQFP100
+
+### Speed   : 3
+
+##########################################################
+
+                                                          
+
+INFO - synthesis: User-Selected Strategy Settings
+Optimization goal = Balanced
+Top-level module name = RAM2GS.
+Target frequency = 200.000000 MHz.
+Maximum fanout = 1000.
+Timing path count = 3
+BRAM utilization = 100.000000 %
+DSP usage = true
+DSP utilization = 100.000000 %
+fsm_encoding_style = auto
+resolve_mixed_drivers = 0
+fix_gated_clocks = 1
+
+Mux style = Auto
+Use Carry Chain = true
+carry_chain_length = 0
+Loop Limit = 1950.
+Use IO Insertion = TRUE
+Use IO Reg = AUTO
+
+Resource Sharing = TRUE
+Propagate Constants = TRUE
+Remove Duplicate Registers = TRUE
+force_gsr = auto
+ROM style = auto
+RAM style = auto
+The -comp option is FALSE.
+The -syn option is FALSE.
+-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C (searchpath added)
+-p C:/lscc/diamond/3.12/ispfpga/mj5g00/data (searchpath added)
+-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/impl1 (searchpath added)
+-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C (searchpath added)
+Verilog design file = C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v
+NGD file = RAM2GS_LCMXO256C_impl1.ngd
+-sdc option: SDC file input not used.
+-lpf option: Output file option is ON.
+Hardtimer checking is enabled (default). The -dt option is not used.
+The -r option is OFF. [ Remove LOC Properties is OFF. ]
+Technology check ok...
+
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
+Compile design.
+Compile Design Begin
+Analyzing Verilog file c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v. VERI-1482
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
+Top module name (Verilog): RAM2GS
+INFO - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(1): compiling module RAM2GS. VERI-1018
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131): expression size 32 truncated to fit in target size 2. VERI-1209
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136): expression size 32 truncated to fit in target size 18. VERI-1209
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263): expression size 32 truncated to fit in target size 4. VERI-1209
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+Loading device for application map from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.19.
+Top-level module name = RAM2GS.
+INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 0000 -> 0000000000000001
+
+ 0001 -> 0000000000000010
+
+ 0010 -> 0000000000000100
+
+ 0011 -> 0000000000001000
+
+ 0100 -> 0000000000010000
+
+ 0101 -> 0000000000100000
+
+ 0110 -> 0000000001000000
+
+ 0111 -> 0000000010000000
+
+ 1000 -> 0000000100000000
+
+ 1001 -> 0000001000000000
+
+ 1010 -> 0000010000000000
+
+ 1011 -> 0000100000000000
+
+ 1100 -> 0001000000000000
+
+ 1101 -> 0010000000000000
+
+ 1110 -> 0100000000000000
+
+ 1111 -> 1000000000000000
+
+INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 00 -> 0001
+
+ 01 -> 0010
+
+ 10 -> 0100
+
+ 11 -> 1000
+
+
+
+
+GSR will not be inferred because no asynchronous signal was found in the netlist.
+WARNING - synthesis: Initial value found on instance C1Submitted_379 will be ignored.
+Applying 200.000000 MHz constraint to all clocks
+
+WARNING - synthesis: No user .sdc file.
+Results of NGD DRC are available in RAM2GS_drc.log.
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+All blocks are expanded and NGD expansion is successful.
+Writing NGD file RAM2GS_LCMXO256C_impl1.ngd.
+
+################### Begin Area Report (RAM2GS)######################
+Number of register bits => 102 of 490 (20 % )
+BB => 8
+CCU2 => 9
+FD1P3AX => 28
+FD1P3AY => 3
+FD1P3IX => 2
+FD1P3JX => 1
+FD1S3AX => 47
+FD1S3AY => 1
+FD1S3IX => 16
+FD1S3JX => 4
+GSR => 1
+IB => 26
+INV => 3
+OB => 33
+ORCALUT4 => 116
+PFUMX => 3
+################### End Area Report ##################
+
+################### Begin BlackBox Report ######################
+TSALL => 1
+################### End BlackBox Report ##################
+
+################### Begin Clock Report ######################
+Clock Nets
+Number of Clocks: 4
+  Net : RCLK_c, loads : 62
+  Net : PHI2_c, loads : 11
+  Net : nCCAS_c, loads : 2
+  Net : nCRAS_c, loads : 2
+Clock Enable Nets
+Number of Clock Enables: 13
+Top 10 highest fanout Clock Enables:
+  Net : RCLK_c_enable_23, loads : 16
+  Net : RCLK_c_enable_4, loads : 3
+  Net : PHI2_N_114_enable_7, loads : 3
+  Net : RCLK_c_enable_24, loads : 2
+  Net : PHI2_N_114_enable_6, loads : 2
+  Net : RCLK_c_enable_7, loads : 1
+  Net : RCLK_c_enable_6, loads : 1
+  Net : RCLK_c_enable_3, loads : 1
+  Net : PHI2_N_114_enable_2, loads : 1
+  Net : PHI2_N_114_enable_1, loads : 1
+Highest fanout non-clock nets
+Top 10 highest fanout non-clock nets:
+  Net : InitReady, loads : 17
+  Net : RCLK_c_enable_23, loads : 16
+  Net : RASr2, loads : 15
+  Net : nCRAS_N_9, loads : 15
+  Net : nRowColSel_N_35, loads : 14
+  Net : nRowColSel, loads : 13
+  Net : Ready, loads : 13
+  Net : n2307, loads : 13
+  Net : nCCAS_N_3, loads : 10
+  Net : Din_c_6, loads : 9
+################### End Clock Report ##################
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk1 [get_nets PHI2_c]                  |  200.000 MHz|   38.826 MHz|     7 *
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets RCLK_c]                  |  200.000 MHz|   88.566 MHz|     6 *
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+2 constraints not met.
+
+
+Peak Memory Usage: 50.406  MB
+
+--------------------------------------------------------------
+Elapsed CPU time for LSE flow : 0.530  secs
+--------------------------------------------------------------
+
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diff --git a/CPLD/LCMXO/LCMXO256C/impl1/xxx_lse_cp_file_list b/CPLD/LCMXO/LCMXO256C/impl1/xxx_lse_cp_file_list
new file mode 100644
index 0000000..29f9161
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO256C/impl1/xxx_lse_cp_file_list
@@ -0,0 +1,252 @@
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new file mode 100644
index 0000000..47217b1
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index 0000000..c145fb8
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/.setting.ini
@@ -0,0 +1,4 @@
+[General]
+Export.auto_tasks=IBIS, Bitgen
+Map.auto_tasks=MapEqu, MapTrace
+PAR.auto_tasks=PARTrace, IOTiming
diff --git a/CPLD/LCMXO/LCMXO640C/.spread_sheet.ini b/CPLD/LCMXO/LCMXO640C/.spread_sheet.ini
new file mode 100644
index 0000000..6c511f4
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/.spread_sheet.ini
@@ -0,0 +1,3 @@
+[General]
+COLUMN_POS_INFO_NAME_-1_0=Prioritize
+COLUMN_POS_INFO_NAME_-1_1=PIO Register
diff --git a/CPLD/LCMXO/LCMXO640C/.spreadsheet_view.ini b/CPLD/LCMXO/LCMXO640C/.spreadsheet_view.ini
new file mode 100644
index 0000000..54adf6f
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/.spreadsheet_view.ini
@@ -0,0 +1,65 @@
+[General]
+pin_sort_type=0
+pin_sort_ascending=true
+sig_sort_type=0
+sig_sort_ascending=true
+active_Sheet=Port Assignments
+
+[Port%20Assignments]
+Name="166,0"
+Group%20By="84,1"
+Pin="56,2"
+BANK="62,3"
+IO_TYPE="131,4"
+PULLMODE="92,5"
+DRIVE="67,6"
+SLEWRATE="92,7"
+OPENDRAIN="97,8"
+Outload%20%28pF%29="103,9"
+MaxSkew="87,10"
+Clock%20Load%20Only="121,11"
+sort_columns="Name,Ascending"
+
+[Pin%20Assignments]
+Pin="90,0"
+Pad%20Name="89,1"
+Dual%20Function="109,2"
+Polarity="77,3"
+BANK="0,4"
+IO_TYPE="131,5"
+Signal%20Name="113,6"
+Signal%20Type="115,7"
+sort_columns="Pin,Ascending"
+
+[Clock%20Resource]
+Clock%20Type="100,ELLIPSIS"
+Clock%20Name="100,ELLIPSIS"
+Selection="100,ELLIPSIS"
+
+[Global%20Preferences]
+Preference%20Name="222,ELLIPSIS"
+Preference%20Value="236,ELLIPSIS"
+
+[Cell%20Mapping]
+Type="100,ELLIPSIS"
+Name="100,ELLIPSIS"
+Din\Dout="100,ELLIPSIS"
+PIO%20Register="100,ELLIPSIS"
+
+[Route%20Priority]
+Type="100,ELLIPSIS"
+Name="100,ELLIPSIS"
+Prioritize="100,ELLIPSIS"
+
+[Timing%20Preferences]
+Preference%20Name="246,ELLIPSIS"
+Preference%20Value="104,ELLIPSIS"
+Preference%20Unit="98,ELLIPSIS"
+
+[Group]
+Group%20Type\Name="134,ELLIPSIS"
+Value="38,ELLIPSIS"
+
+[Misc%20Preferences]
+Preference%20Name="117,ELLIPSIS"
+Preference%20Value="104,ELLIPSIS"
diff --git a/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C.ccl b/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C.ccl
new file mode 100644
index 0000000..dcf391b
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C.ccl
@@ -0,0 +1 @@
+VERSION=20110520
diff --git a/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C.ldf b/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C.ldf
new file mode 100644
index 0000000..c625cb6
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C.ldf
@@ -0,0 +1,14 @@
+
+
+    
+    
+        
+        
+            
+        
+        
+            
+        
+    
+    
+
diff --git a/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C.lpf b/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C.lpf
new file mode 100644
index 0000000..9fa278f
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C.lpf
@@ -0,0 +1,226 @@
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+LOCATE COMP "Dout[0]" SITE "1" ;
+LOCATE COMP "Dout[6]" SITE "2" ;
+LOCATE COMP "Dout[7]" SITE "3" ;
+LOCATE COMP "Dout[4]" SITE "4" ;
+LOCATE COMP "Dout[5]" SITE "5" ;
+LOCATE COMP "Dout[3]" SITE "6" ;
+LOCATE COMP "Dout[1]" SITE "7" ;
+LOCATE COMP "Dout[2]" SITE "8" ;
+LOCATE COMP "Din[2]" SITE "14" ;
+LOCATE COMP "Din[1]" SITE "15" ;
+LOCATE COMP "Din[3]" SITE "16" ;
+LOCATE COMP "Din[5]" SITE "17" ;
+LOCATE COMP "Din[4]" SITE "18" ;
+LOCATE COMP "Din[7]" SITE "19" ;
+LOCATE COMP "Din[6]" SITE "20" ;
+LOCATE COMP "Din[0]" SITE "21" ;
+LOCATE COMP "LED" SITE "57" ;
+LOCATE COMP "RA[0]" SITE "98" ;
+LOCATE COMP "RA[1]" SITE "89" ;
+LOCATE COMP "RA[2]" SITE "94" ;
+LOCATE COMP "RA[3]" SITE "97" ;
+LOCATE COMP "RA[4]" SITE "99" ;
+LOCATE COMP "RA[5]" SITE "95" ;
+LOCATE COMP "RA[6]" SITE "91" ;
+LOCATE COMP "RA[7]" SITE "100" ;
+LOCATE COMP "RA[8]" SITE "96" ;
+LOCATE COMP "RA[9]" SITE "85" ;
+LOCATE COMP "RA[10]" SITE "87" ;
+LOCATE COMP "RA[11]" SITE "79" ;
+LOCATE COMP "RBA[1]" SITE "83" ;
+LOCATE COMP "RBA[0]" SITE "63" ;
+LOCATE COMP "RCKE" SITE "82" ;
+LOCATE COMP "RDQMH" SITE "76" ;
+LOCATE COMP "RDQML" SITE "61" ;
+LOCATE COMP "UFMCLK" SITE "58" ;
+LOCATE COMP "UFMSDI" SITE "56" ;
+LOCATE COMP "nUFMCS" SITE "53" ;
+LOCATE COMP "nRCAS" SITE "78" ;
+LOCATE COMP "nRCS" SITE "77" ;
+LOCATE COMP "nRRAS" SITE "73" ;
+LOCATE COMP "nRWE" SITE "72" ;
+LOCATE COMP "RD[0]" SITE "64" ;
+LOCATE COMP "RD[1]" SITE "65" ;
+LOCATE COMP "RD[2]" SITE "66" ;
+LOCATE COMP "RD[3]" SITE "67" ;
+LOCATE COMP "RD[4]" SITE "68" ;
+LOCATE COMP "RD[5]" SITE "69" ;
+LOCATE COMP "RD[6]" SITE "70" ;
+LOCATE COMP "RD[7]" SITE "71" ;
+LOCATE COMP "PHI2" SITE "39" ;
+LOCATE COMP "RCLK" SITE "86" ;
+LOCATE COMP "nCCAS" SITE "27" ;
+LOCATE COMP "nCRAS" SITE "43" ;
+LOCATE COMP "CROW[0]" SITE "32" ;
+LOCATE COMP "CROW[1]" SITE "34" ;
+LOCATE COMP "UFMSDO" SITE "55" ;
+LOCATE COMP "nFWE" SITE "22" ;
+LOCATE COMP "MAin[0]" SITE "23" ;
+LOCATE COMP "MAin[1]" SITE "38" ;
+LOCATE COMP "MAin[2]" SITE "37" ;
+LOCATE COMP "MAin[3]" SITE "47" ;
+LOCATE COMP "MAin[4]" SITE "46" ;
+LOCATE COMP "MAin[5]" SITE "45" ;
+LOCATE COMP "MAin[6]" SITE "49" ;
+LOCATE COMP "MAin[7]" SITE "44" ;
+LOCATE COMP "MAin[8]" SITE "50" ;
+LOCATE COMP "MAin[9]" SITE "51" ;
+IOBUF PORT "CROW[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "CROW[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "nCRAS" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "nCCAS" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "RCLK" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "PHI2" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "Din[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "Din[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "Din[2]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "Din[3]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "Din[4]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "Din[5]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "Din[6]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "Din[7]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[2]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[3]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[4]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[5]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[6]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[7]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[8]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[9]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "UFMSDO" PULLMODE=KEEPER IO_TYPE=LVTTL33 ;
+IOBUF PORT "nFWE" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "Dout[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "Dout[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "Dout[2]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "Dout[3]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "Dout[4]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "Dout[5]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "Dout[6]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "Dout[7]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "LED" PULLMODE=NONE IO_TYPE=LVTTL33 DRIVE=16 SLEWRATE=SLOW ;
+IOBUF PORT "RA[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[2]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[3]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[4]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[5]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[6]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[7]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[8]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[9]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[10]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[11]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RBA[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RBA[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RCKE" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RDQMH" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RDQML" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "UFMCLK" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "UFMSDI" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "nRCAS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "nRCS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "nRRAS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "nRWE" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "nUFMCS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RD[0]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
+IOBUF PORT "RD[1]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
+IOBUF PORT "RD[2]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
+IOBUF PORT "RD[3]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
+IOBUF PORT "RD[4]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
+IOBUF PORT "RD[5]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
+IOBUF PORT "RD[6]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
+IOBUF PORT "RD[7]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
+OUTPUT PORT "RD[7]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[0]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[1]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[2]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[3]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[4]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[5]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[6]" LOAD 20.000000 pF ;
+OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ;
+OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ;
+OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ;
+OUTPUT PORT "nRWE" LOAD 10.000000 pF ;
+OUTPUT PORT "nRCAS" LOAD 10.000000 pF ;
+OUTPUT PORT "nRCS" LOAD 10.000000 pF ;
+OUTPUT PORT "nRRAS" LOAD 10.000000 pF ;
+OUTPUT PORT "RDQML" LOAD 10.000000 pF ;
+OUTPUT PORT "RDQMH" LOAD 10.000000 pF ;
+OUTPUT PORT "RCKE" LOAD 10.000000 pF ;
+OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ;
+OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[11]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[10]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[9]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[8]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[7]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[6]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[5]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[4]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[3]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[2]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[1]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[0]" LOAD 10.000000 pF ;
+OUTPUT PORT "LED" LOAD 25.000000 pF ;
+OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ;
+USE PRIMARY NET "PHI2_c" ;
+USE PRIMARY NET "RCLK_c" ;
+VOLTAGE 3.300 V;
+VCCIO_DERATE BANK 0 PERCENT -5; 
+VCCIO_DERATE PERCENT -5; 
+VCCIO_DERATE BANK 1 PERCENT -5; 
+PERIOD NET "PHI2_c" 350.000000 ns  ;
+PERIOD NET "nCCAS_c" 350.000000 ns  ;
+PERIOD NET "nCRAS_c" 350.000000 ns  ;
+PERIOD NET "RCLK_c" 16.000000 ns  ;
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+USE PRIMARY NET "nCCAS_c" ;
+USE PRIMARY NET "nCRAS_c" ;
diff --git a/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C1.sty b/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C1.sty
new file mode 100644
index 0000000..feec63c
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C1.sty
@@ -0,0 +1,205 @@
+
+
+
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
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+    
+    
+    
+    
+    
+    
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+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
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+    
+    
+    
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+    
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+    
+    
+    
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+    
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+    
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+    
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+    
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+    
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+    
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+    
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+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
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+    
+    
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+    
+    
+    
+    
+
diff --git a/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C_tcl.html b/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C_tcl.html
new file mode 100644
index 0000000..c0aa950
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C_tcl.html
@@ -0,0 +1,75 @@
+
+Lattice TCL Log
+
+
+
    pn210816203903
+#Start recording tcl command: 8/16/2021 20:34:20
+#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C; Project name: RAM2GS_LCMXO640C
+prj_project new -name "RAM2GS_LCMXO640C" -impl "impl1" -dev LCMXO640C-3T100C -synthesis "lse"
+prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v"
+prj_project save
+prj_src add -exclude "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS_LCMXO.lpf"
+prj_run Export -impl impl1 -forceAll
+prj_src remove "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS_LCMXO.lpf"
+prj_run Export -impl impl1 -forceAll
+#Stop recording: 8/16/2021 20:39:03
+
+
+
+
    
+
    
+
    
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+
    
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+
diff --git a/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn210816203903.tcr b/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn210816203903.tcr
new file mode 100644
index 0000000..aada37a
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn210816203903.tcr
@@ -0,0 +1,10 @@
+#Start recording tcl command: 8/16/2021 20:34:20
+#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C; Project name: RAM2GS_LCMXO640C
+prj_project new -name "RAM2GS_LCMXO640C" -impl "impl1" -dev LCMXO640C-3T100C -synthesis "lse"
+prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v"
+prj_project save
+prj_src add -exclude "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS_LCMXO.lpf"
+prj_run Export -impl impl1 -forceAll
+prj_src remove "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS_LCMXO.lpf"
+prj_run Export -impl impl1 -forceAll
+#Stop recording: 8/16/2021 20:39:03
diff --git a/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn210816214112.tcr b/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn210816214112.tcr
new file mode 100644
index 0000000..3c252b4
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn210816214112.tcr
@@ -0,0 +1,6 @@
+#Start recording tcl command: 8/16/2021 21:33:25
+#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C; Project name: RAM2GS_LCMXO640C
+prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C.ldf"
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceOne
+#Stop recording: 8/16/2021 21:41:12
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/.build_status b/CPLD/LCMXO/LCMXO640C/impl1/.build_status
new file mode 100644
index 0000000..45432b8
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/.build_status
@@ -0,0 +1,46 @@
+
+
+    
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+    
+
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/.vdbs/RAM2GS_LCMXO640C_impl1_map.vdb b/CPLD/LCMXO/LCMXO640C/impl1/.vdbs/RAM2GS_LCMXO640C_impl1_map.vdb
new file mode 100644
index 0000000000000000000000000000000000000000..983b4febc9f9c5d92715f68391a9eaed258ea38e
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diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.ncd b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.ncd
new file mode 100644
index 0000000000000000000000000000000000000000..fa3d1271d2b8a91aaa5c3455186366cb54bf9687
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zbC*+*mhqRsE+=)1W;_S3;=tdDW;_i3u;W0{gwft8N8^BTY2!!8XDnThxl1&*cgQlI
zzobF$+4yOmn0g;8y|t>>()&bdFmv#Imm`>m`K6a`UX|W6f8$i*W4$o`6x8kBn?*C`
z3Ag&A7DjP2@9{-ZOtA8uboYptoqydk*57%Tn*f(nITnExmEl
z1>3uQ@J(Ws-s8p=y`NB7?BDG-I2CCb&py4^0?~}wr}u%aGZ=GElK1xt!?u5bx>!#x
zdJW+gE4jGq6&lYFw9N-BrS|KhF{aX!MNysJ5w5$_J*$_E!vy1
zgiNF@T6g)U;&7SfM^p3Tr1{8)sbfoXK2<`8uI~@hytEKUfRPUu&Ay}3SW4GVoQkxJ
zzvQ``1sk(h^O=;vn6)#Wo)^KGza1AQt>Z$p{4db!Zz0WCHK1iBW7R;{PsGRC2>C)z
z(qh+A*#C;G4a9P^?R+>lGh&)Cx)1DwjlXo#h=DPSgV{O*{Gw_)&kj-x5Bp`ca#ry0
zLvrQJn1k_hO!gU!M{mlPYQ`?Vs52Yv&683c&J>_d_Zg|qX=uBvhp4k_l%yD_BM#A&
zfy7u^{4Yf!=I;qmgTZ*@O(~{v#Ue&?m=#!*I!9utF;hl+l|Vouy5d>mFh>itBI
z7-T07B?!?kfaq^Sbk4XCj6e7rh<>kV#uV3YT#fhLo}wGOtWxVSLq8=&M~{e^<*6z9
znXu$V?N;ncs@8AVuE9E~|(h6Zem$
z=l*I^!}3N#
z<7koZDy=cgwTi};si=sVOrv>fstC^%3pD4ZioJM=1fky3Cs4}_5d#&)A(}EkMvucW
zf3wgEjy3Ey(Tsa1HkH&kslyd?Uwp=}nK-r#s;+Hqt^dRAtN
zE<@F~yquMUfsxv6s7@Uzwkl3llFy@HB@v&ET>Lh|coiz^`L!$>XRQ^?%JlIX#ww0n
z7tf5rwKoOiiUwTWtfSMYrh(Lhm67UJ=VDaiM07u#;w{WDG0$9{x>_`2_Vl*PMKe~`
zq~SY<+2PmDPH{XXsRm4ob8Q+`B~CZ`Hm|1i$Y{)W@tvcJI0c6Y*H+>Hhd4pQ*%fnU
zpLxU)N6hFs1(mTKA?3mho2^sdoJbPdaYr{Nid7BC+Y%Yr7`!o2X+&e=GTw2GW@9JB
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S>jO?xXeHip?: 1.302ns/0.000ns; real time: 5 secs 
+Level 2, iteration 1
+0(0.00%) conflict; 523(84.63%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.256ns/0.000ns; real time: 5 secs 
+Level 3, iteration 1
+0(0.00%) conflict; 511(82.69%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.228ns/0.000ns; real time: 5 secs 
+Level 4, iteration 1
+16(0.06%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 21:33:37 08/16/21
+Level 1, iteration 1
+0(0.00%) conflict; 16(2.59%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
+Level 2, iteration 1
+0(0.00%) conflict; 16(2.59%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
+Level 3, iteration 1
+0(0.00%) conflict; 16(2.59%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
+Level 4, iteration 1
+5(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
+Level 4, iteration 2
+2(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
+Level 4, iteration 3
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
+
+Start NBR section for setup/hold timing optimization with effort level 3 at 21:33:37 08/16/21
+
+Start NBR section for re-routing at 21:33:37 08/16/21
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
+
+Start NBR section for post-routing at 21:33:37 08/16/21
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 0 (0.00%)
+  Estimated worst slack : 1.213ns
+  Timing score : 0
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+Total CPU time 6 secs 
+Total REAL time: 6 secs 
+Completely routed.
+End of route.  618 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 0 
+
+Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = Completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack> = 1.213
+PAR_SUMMARY::Timing score> = 0.000
+PAR_SUMMARY::Worst  slack> = 0.339
+PAR_SUMMARY::Timing score> = 0.000
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 6 secs 
+Total REAL time to completion: 6 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1_par.asd b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1_par.asd
new file mode 100644
index 0000000..878d798
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1_par.asd
@@ -0,0 +1,45 @@
+[ActiveSupport PAR]
+; Global primary clocks
+GLOBAL_PRIMARY_USED = 4;
+; Global primary clock #0
+GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c;
+GLOBAL_PRIMARY_0_DRIVERTYPE = CLK_PIN;
+GLOBAL_PRIMARY_0_LOADNUM = 39;
+; Global primary clock #1
+GLOBAL_PRIMARY_1_SIGNALNAME = PHI2_c;
+GLOBAL_PRIMARY_1_DRIVERTYPE = PIO;
+GLOBAL_PRIMARY_1_LOADNUM = 13;
+; Global primary clock #2
+GLOBAL_PRIMARY_2_SIGNALNAME = nCCAS_c;
+GLOBAL_PRIMARY_2_DRIVERTYPE = PIO;
+GLOBAL_PRIMARY_2_LOADNUM = 4;
+; Global primary clock #3
+GLOBAL_PRIMARY_3_SIGNALNAME = nCRAS_c;
+GLOBAL_PRIMARY_3_DRIVERTYPE = PIO;
+GLOBAL_PRIMARY_3_LOADNUM = 7;
+; # of global secondary clocks
+GLOBAL_SECONDARY_USED = 0;
+; I/O Bank 0 Usage
+BANK_0_USED = 18;
+BANK_0_AVAIL = 18;
+BANK_0_VCCIO = 3.3V;
+BANK_0_VREF1 = NA;
+BANK_0_VREF2 = NA;
+; I/O Bank 1 Usage
+BANK_1_USED = 18;
+BANK_1_AVAIL = 21;
+BANK_1_VCCIO = 3.3V;
+BANK_1_VREF1 = NA;
+BANK_1_VREF2 = NA;
+; I/O Bank 2 Usage
+BANK_2_USED = 13;
+BANK_2_AVAIL = 14;
+BANK_2_VCCIO = NA;
+BANK_2_VREF1 = NA;
+BANK_2_VREF2 = NA;
+; I/O Bank 3 Usage
+BANK_3_USED = 18;
+BANK_3_AVAIL = 21;
+BANK_3_VCCIO = 3.3V;
+BANK_3_VREF1 = NA;
+BANK_3_VREF2 = NA;
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/RAM2GS_LCMXO640C_impl1.par b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/RAM2GS_LCMXO640C_impl1.par
new file mode 100644
index 0000000..8bf94bf
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/RAM2GS_LCMXO640C_impl1.par
@@ -0,0 +1,28 @@
+PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Mon Aug 16 21:33:31 2021
+
+C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO640C_impl1.p2t
+RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir
+RAM2GS_LCMXO640C_impl1.prf -gui -msgset
+C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml
+
+
+Preference file: RAM2GS_LCMXO640C_impl1.prf.
+
+Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
+Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
+----------   --------     -----        ------       -----------  -----------  ----         ------
+5_1   *      0            1.213        0            0.339        0            06           Completed
+
+* : Design saved.
+
+Total (real) run time for 1-seed: 6 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.drc b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.drc
new file mode 100644
index 0000000..ec074a2
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.drc
@@ -0,0 +1 @@
+DRC detected 0 errors and 0 warnings.
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.jed b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.jed
new file mode 100644
index 0000000..149b5cf
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.jed
@@ -0,0 +1,1745 @@
+
+*
+NOTE JEDEC CREATED BY: Lattice Semiconductor Diamond Deployment Tool 3.12*
+NOTE Version:         Diamond (64-bit) 3.12.0.240.2*
+NOTE Readback:       Off*
+NOTE Security:      Off*
+NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
+NOTE All Rights Reserved *
+NOTE DATE CREATED: Mon Aug 16 21:36:33 2021 *
+NOTE DESIGN NAME: RAM2GS *
+NOTE DEVICE NAME: LCMXO640C-3TQFP100 *
+NOTE PIN ASSIGNMENTS *
+NOTE PINS RD[7] : 71 : inout *
+NOTE PINS RD[6] : 70 : inout *
+NOTE PINS RD[5] : 69 : inout *
+NOTE PINS RD[4] : 68 : inout *
+NOTE PINS RD[3] : 67 : inout *
+NOTE PINS RD[2] : 66 : inout *
+NOTE PINS RD[1] : 65 : inout *
+NOTE PINS RD[0] : 64 : inout *
+NOTE PINS Dout[7] : 3 : out *
+NOTE PINS Dout[6] : 2 : out *
+NOTE PINS Dout[5] : 5 : out *
+NOTE PINS Dout[4] : 4 : out *
+NOTE PINS Dout[3] : 6 : out *
+NOTE PINS Dout[2] : 8 : out *
+NOTE PINS Dout[1] : 7 : out *
+NOTE PINS Dout[0] : 1 : out *
+NOTE PINS LED : 57 : out *
+NOTE PINS RBA[1] : 83 : out *
+NOTE PINS RBA[0] : 63 : out *
+NOTE PINS RA[11] : 79 : out *
+NOTE PINS RA[10] : 87 : out *
+NOTE PINS RA[9] : 85 : out *
+NOTE PINS RA[8] : 96 : out *
+NOTE PINS RA[7] : 100 : out *
+NOTE PINS RA[6] : 91 : out *
+NOTE PINS RA[5] : 95 : out *
+NOTE PINS RA[4] : 99 : out *
+NOTE PINS RA[3] : 97 : out *
+NOTE PINS RA[2] : 94 : out *
+NOTE PINS RA[1] : 89 : out *
+NOTE PINS RA[0] : 98 : out *
+NOTE PINS nRCS : 77 : out *
+NOTE PINS RCKE : 82 : out *
+NOTE PINS nRWE : 72 : out *
+NOTE PINS nRRAS : 73 : out *
+NOTE PINS nRCAS : 78 : out *
+NOTE PINS RDQMH : 76 : out *
+NOTE PINS RDQML : 61 : out *
+NOTE PINS nUFMCS : 53 : out *
+NOTE PINS UFMCLK : 58 : out *
+NOTE PINS UFMSDI : 56 : out *
+NOTE PINS PHI2 : 39 : in *
+NOTE PINS MAin[9] : 51 : in *
+NOTE PINS MAin[8] : 50 : in *
+NOTE PINS MAin[7] : 44 : in *
+NOTE PINS MAin[6] : 49 : in *
+NOTE PINS MAin[5] : 45 : in *
+NOTE PINS MAin[4] : 46 : in *
+NOTE PINS MAin[3] : 47 : in *
+NOTE PINS MAin[2] : 37 : in *
+NOTE PINS MAin[1] : 38 : in *
+NOTE PINS MAin[0] : 23 : in *
+NOTE PINS CROW[1] : 34 : in *
+NOTE PINS CROW[0] : 32 : in *
+NOTE PINS Din[7] : 19 : in *
+NOTE PINS Din[6] : 20 : in *
+NOTE PINS Din[5] : 17 : in *
+NOTE PINS Din[4] : 18 : in *
+NOTE PINS Din[3] : 16 : in *
+NOTE PINS Din[2] : 14 : in *
+NOTE PINS Din[1] : 15 : in *
+NOTE PINS Din[0] : 21 : in *
+NOTE PINS nCCAS : 27 : in *
+NOTE PINS nCRAS : 43 : in *
+NOTE PINS nFWE : 22 : in *
+NOTE PINS RCLK : 86 : in *
+NOTE PINS UFMSDO : 55 : in *
+NOTE CONFIGURATION MODE: NONE *
+NOTE COMPRESSION: off *
+
+
+QF130036*
+G0*
+F0*
+L000000
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+*
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+46DE
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.log b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.log
new file mode 100644
index 0000000..d0353b8
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.log
@@ -0,0 +1,4 @@
+---- MParTrce Tool Log File ----
+
+==== Par Standard Out ====
+==== End of Par Standard Out ====
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.lpf b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.lpf
new file mode 100644
index 0000000..2743d95
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.lpf
@@ -0,0 +1,4 @@
+#BLOCK ASYNCPATHS;
+#BLOCK RESETPATHS;
+
+#FREQUENCY 200.000000 MHz;
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.lsedata b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.lsedata
new file mode 100644
index 0000000..f0b54bc
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.lsedata
@@ -0,0 +1,5981 @@
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diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mrp b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mrp
new file mode 100644
index 0000000..279152d
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mrp
@@ -0,0 +1,402 @@
+
+            Lattice Mapping Report File for Design Module 'RAM2GS'
+
+
+Design Information
+------------------
+
+Command line:   map -a MachXO -p LCMXO640C -t TQFP100 -s 3 -oc Commercial
+     RAM2GS_LCMXO640C_impl1.ngd -o RAM2GS_LCMXO640C_impl1_map.ncd -pr
+     RAM2GS_LCMXO640C_impl1.prf -mp RAM2GS_LCMXO640C_impl1.mrp -lpf C:/Users/Dog
+     /Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.
+     lpf -lpf C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/RAM2GS_L
+     CMXO640C.lpf -c 0 -gui -msgset
+     C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml 
+Target Vendor:  LATTICE
+Target Device:  LCMXO640CTQFP100
+Target Performance:   3
+Mapper:  mj5g00,  version:  Diamond (64-bit) 3.12.0.240.2
+Mapped on:  08/16/21  21:33:30
+
+Design Summary
+--------------
+
+   Number of PFU registers:   102 out of   640 (16%)
+   Number of SLICEs:        65 out of   320 (20%)
+      SLICEs as Logic/ROM:     65 out of   320 (20%)
+      SLICEs as RAM:            0 out of   192 (0%)
+      SLICEs as Carry:          9 out of   320 (3%)
+   Number of LUT4s:        129 out of   640 (20%)
+      Number used as logic LUTs:        111
+      Number used as distributed RAM:     0
+      Number used as ripple logic:       18
+      Number used as shift registers:     0
+   Number of external PIOs: 67 out of 74 (91%)
+   Number of GSRs:  0 out of 1 (0%)
+   JTAG used :      No
+   Readback used :  No
+   Oscillator used :  No
+   Startup used :   No
+   Number of TSALL: 0 out of 1 (0%)
+   Notes:-
+      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
+     distributed RAMs) + 2*(Number of ripple logic)
+      2. Number of logic LUT4s does not include count of distributed RAM and
+     ripple logic.
+   Number of clocks:  4
+     Net RCLK_c: 39 loads, 39 rising, 0 falling (Driver: PIO RCLK )
+     Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 )
+     Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
+     Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS )
+   Number of Clock Enables:  13
+     Net PHI2_N_114_enable_7: 2 loads, 2 LSLICEs
+     Net RCLK_c_enable_6: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_4: 3 loads, 3 LSLICEs
+     Net RCLK_c_enable_24: 2 loads, 2 LSLICEs
+     Net RCLK_c_enable_3: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_7: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_23: 8 loads, 8 LSLICEs
+     Net PHI2_N_114_enable_1: 1 loads, 1 LSLICEs
+     Net PHI2_N_114_enable_8: 1 loads, 1 LSLICEs
+     Net PHI2_N_114_enable_6: 2 loads, 2 LSLICEs
+     Net PHI2_N_114_enable_2: 1 loads, 1 LSLICEs
+
+                                    Page 1
+
+
+
+
+Design:  RAM2GS                                        Date:  08/16/21  21:33:30
+
+Design Summary (cont)
+---------------------
+     Net RCLK_c_enable_25: 1 loads, 1 LSLICEs
+     Net Ready_N_268: 1 loads, 1 LSLICEs
+   Number of LSRs:  9
+     Net RASr2: 1 loads, 1 LSLICEs
+     Net C1Submitted_N_225: 2 loads, 2 LSLICEs
+     Net n2299: 1 loads, 1 LSLICEs
+     Net nRowColSel_N_35: 1 loads, 1 LSLICEs
+     Net nRowColSel_N_34: 1 loads, 1 LSLICEs
+     Net LEDEN_N_88: 1 loads, 1 LSLICEs
+     Net n2291: 2 loads, 2 LSLICEs
+     Net Ready: 7 loads, 7 LSLICEs
+     Net nRWE_N_173: 1 loads, 1 LSLICEs
+   Number of nets driven by tri-state buffers:  0
+   Top 10 highest fanout non-clock nets:
+     Net Ready: 19 loads
+     Net InitReady: 17 loads
+     Net RASr2: 16 loads
+     Net nRowColSel_N_35: 14 loads
+     Net nRowColSel: 13 loads
+     Net Din_c_6: 9 loads
+     Net MAin_c_1: 9 loads
+     Net Din_c_5: 8 loads
+     Net FS_11: 8 loads
+     Net MAin_c_0: 8 loads
+
+
+
+
+   Number of warnings:  0
+   Number of errors:    0
+     
+
+Design Errors/Warnings
+----------------------
+
+   No errors or warnings present.
+
+IO (PIO) Attributes
+-------------------
+
++---------------------+-----------+-----------+------------+------------+
+| IO Name             | Direction | Levelmode | IO         | FIXEDDELAY |
+|                     |           |  IO_TYPE  | Register   |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[7]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[6]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[5]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[4]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[3]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[2]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+
+                                    Page 2
+
+
+
+
+Design:  RAM2GS                                        Date:  08/16/21  21:33:30
+
+IO (PIO) Attributes (cont)
+--------------------------
+| RD[1]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[0]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[7]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[6]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[5]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[4]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[3]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[2]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[1]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[0]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| LED                 | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RBA[1]              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RBA[0]              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[11]              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[10]              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[9]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[8]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[7]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[6]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[5]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[4]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[3]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[2]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[1]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[0]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nRCS                | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RCKE                | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nRWE                | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+
+                                    Page 3
+
+
+
+
+Design:  RAM2GS                                        Date:  08/16/21  21:33:30
+
+IO (PIO) Attributes (cont)
+--------------------------
+| nRRAS               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nRCAS               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RDQMH               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RDQML               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nUFMCS              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| UFMCLK              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| UFMSDI              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| PHI2                | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[9]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[8]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[7]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[6]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[5]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[4]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[3]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[2]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[1]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[0]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| CROW[1]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| CROW[0]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[7]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[6]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[5]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[4]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[3]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[2]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[1]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[0]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+
+                                    Page 4
+
+
+
+
+Design:  RAM2GS                                        Date:  08/16/21  21:33:30
+
+IO (PIO) Attributes (cont)
+--------------------------
+| nCCAS               | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nCRAS               | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nFWE                | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RCLK                | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| UFMSDO              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+
+Removed logic
+-------------
+
+Block i2 undriven or does not drive anything - clipped.
+Block GSR_INST undriven or does not drive anything - clipped.
+Signal PHI2_N_114 was merged into signal PHI2_c
+Signal nCRAS_N_9 was merged into signal nCRAS_c
+Signal nCCAS_N_3 was merged into signal nCCAS_c
+Signal n2302 was merged into signal nRowColSel_N_35
+Signal nRWE_N_172 was merged into signal nRWE_N_173
+Signal n2307 was merged into signal Ready
+Signal RASr2_N_63 was merged into signal RASr2
+Signal n1377 was merged into signal nRowColSel_N_34
+Signal n2306 was merged into signal nFWE_c
+Signal UFMSDO_N_74 was merged into signal UFMSDO_c
+Signal GND_net undriven or does not drive anything - clipped.
+Signal VCC_net undriven or does not drive anything - clipped.
+Signal FS_577_add_4_14/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_16/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_12/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_2/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_4/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_6/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_18/CO1 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_18/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_8/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_10/CO0 undriven or does not drive anything - clipped.
+Block i1962 was optimized away.
+Block i1961 was optimized away.
+Block i1963 was optimized away.
+Block i1070_1_lut_rep_25 was optimized away.
+Block nRWE_I_49_1_lut was optimized away.
+Block i604_1_lut_rep_30 was optimized away.
+Block RASr2_I_0_1_lut was optimized away.
+Block i1069_1_lut was optimized away.
+Block i1_1_lut_rep_29 was optimized away.
+Block UFMSDO_I_0_1_lut was optimized away.
+Block i1 was optimized away.
+
+Run Time and Memory Usage
+-------------------------
+
+   Total CPU Time: 0 secs  
+   Total REAL Time: 0 secs  
+   Peak Memory Usage: 30 MB
+
+                                    Page 5
+
+
+
+
+Design:  RAM2GS                                        Date:  08/16/21  21:33:30
+
+Run Time and Memory Usage (cont)
+--------------------------------
+        
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+                                    Page 6
+
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+     Copyright (c) 1995 AT&T Corp.   All rights reserved.
+     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+     Copyright (c) 2001 Agere Systems   All rights reserved.
+     Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights
+     reserved.
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mt b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mt
new file mode 100644
index 0000000..2d70ad1
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mt
@@ -0,0 +1,9 @@
+-v
+1
+
+
+-gt
+
+
+-mapchkpnt 0
+-sethld
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.n2e b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.n2e
new file mode 100644
index 0000000..c5da0e1
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.n2e
@@ -0,0 +1,574 @@
+
+comp 0: SLICE_0 (FSLICE)
+
+comp 1: SLICE_1 (FSLICE)
+
+comp 2: SLICE_2 (FSLICE)
+
+comp 3: SLICE_3 (FSLICE)
+
+comp 4: SLICE_4 (FSLICE)
+
+comp 5: SLICE_5 (FSLICE)
+
+comp 6: SLICE_6 (FSLICE)
+
+comp 7: SLICE_7 (FSLICE)
+
+comp 8: SLICE_8 (FSLICE)
+
+comp 9: SLICE_9 (FSLICE)
+n1361 = ((ADSubmitted*(~MAin_c_1+n2290))+ADSubmitted_N_234)
+ADSubmitted.D = n1361
+ADSubmitted.CLK = ~PHI2_c
+ADSubmitted.SP = VCC
+ADSubmitted.LSR = C1Submitted_N_225
+n2080 = (~MAin_c_0*(~ADSubmitted*n2122))
+
+comp 10: SLICE_14 (FSLICE)
+n2386 = GND
+C1Submitted.D = n2386
+C1Submitted.CLK = ~PHI2_c
+C1Submitted.SP = PHI2_N_114_enable_1
+C1Submitted.LSR = C1Submitted_N_225
+n2098 = (MAin_c_0*(~C1Submitted*(MAin_c_1*n2108)))
+
+comp 11: SLICE_18 (FSLICE)
+CmdEnable_N_236 = (ADSubmitted_N_234+C1Submitted_N_225)
+CmdEnable.D = CmdEnable_N_236
+CmdEnable.CLK = ~PHI2_c
+CmdEnable.SP = PHI2_N_114_enable_8
+CmdEnable.LSR = GND
+XOR8MEG_N_112 = (~n2290*(CmdEnable*(MAin_c_0*~MAin_c_1)))
+
+comp 12: SLICE_19 (FSLICE)
+n2387\000/BUF1 = VCC
+CmdSubmitted.D = n2387\000/BUF1
+CmdSubmitted.CLK = ~PHI2_c
+CmdSubmitted.SP = PHI2_N_114_enable_6
+CmdSubmitted.LSR = GND
+n2308 = (~PHI2r2*(CmdSubmitted*PHI2r3))
+
+comp 13: SLICE_23 (FSLICE)
+Cmdn8MEGEN_N_248 = (~n2296*(~Din_c_5*~Din_c_0+Din_c_5*n8MEGEN)+n2296*n8MEGEN)
+Cmdn8MEGEN.D = Cmdn8MEGEN_N_248
+Cmdn8MEGEN.CLK = ~PHI2_c
+Cmdn8MEGEN.SP = PHI2_N_114_enable_6
+Cmdn8MEGEN.LSR = GND
+n2296 = (~Din_c_4+(Din_c_6+Din_c_7))
+
+comp 14: SLICE_25 (FSLICE)
+n2387 = VCC
+InitReady.D = n2387
+InitReady.CLK = RCLK_c
+InitReady.SP = RCLK_c_enable_6
+InitReady.LSR = GND
+RCLK_c_enable_24 = (~InitReady+(~PHI2r2*(CmdSubmitted*PHI2r3)))
+
+comp 15: SLICE_31 (FSLICE)
+RA11_N_180 = (~n8MEGEN*(XOR8MEG@Din_c_6)+n8MEGEN*XOR8MEG)
+RA_c.D = RA11_N_180
+RA_c.CLK = PHI2_c
+RA_c.SP = VCC
+RA_c.LSR = ~Ready
+n2385 = (Din_c_6+Din_c_7)
+
+comp 16: SLICE_33 (FSLICE)
+RCKEEN_N_115 = (~Ready*InitReady+Ready*RCKEEN_N_116)
+RCKEEN.D = RCKEEN_N_115
+RCKEEN.CLK = RCLK_c
+RCKEEN.SP = RCLK_c_enable_4
+RCKEEN.LSR = GND
+RCLK_c_enable_7 = (~n2119*(InitReady*n2308)+n2119*(~InitReady*~FS_5+InitReady*n2308))
+
+comp 17: SLICE_34 (FSLICE)
+RCKE_N_128 = (~RASr3*(~RASr2*(RCKEEN*RASr)+RASr2*RCKEEN)+RASr3*(~RASr2+RCKEEN))
+RCKE_c.D = RCKE_N_128
+RCKE_c.CLK = RCLK_c
+RCKE_c.SP = VCC
+RCKE_c.LSR = GND
+nRWE_N_178 = (~RCKE_c+RASr2)
+CASr2.D = CASr
+CASr2.CLK = RCLK_c
+CASr2.SP = VCC
+CASr2.LSR = GND
+
+comp 18: SLICE_35 (FSLICE)
+n2387\001/BUF1 = VCC
+Ready.D = n2387\001/BUF1
+Ready.CLK = RCLK_c
+Ready.SP = Ready_N_268
+Ready.LSR = GND
+RCLK_c_enable_23 = (InitReady*(RASr2*(nRowColSel_N_35*~Ready)))
+
+comp 19: SLICE_42 (FSLICE)
+UFMCLK_N_212 = (~n2076*(~InitReady*FS_4+InitReady*CmdUFMCLK)+n2076*(InitReady*CmdUFMCLK))
+UFMCLK_c.D = UFMCLK_N_212
+UFMCLK_c.CLK = RCLK_c
+UFMCLK_c.SP = RCLK_c_enable_24
+UFMCLK_c.LSR = n2291
+RCLK_c_enable_6 = (n2076*FS_10)
+
+comp 20: SLICE_43 (FSLICE)
+UFMSDI_N_219 = (~InitReady*n1895+InitReady*CmdUFMSDI)
+UFMSDI_c.D = UFMSDI_N_219
+UFMSDI_c.CLK = RCLK_c
+UFMSDI_c.SP = RCLK_c_enable_24
+UFMSDI_c.LSR = n2291
+n1895 = (~FS_10*(n2103*(~n2293*FS_6)))
+
+comp 21: SLICE_55 (FSLICE)
+n2128 = (((n2297+n2301)+nRCAS_N_161)+Ready)
+n980.D = n2128
+n980.CLK = RCLK_c
+n980.SP = VCC
+n980.LSR = ~nRWE_N_173
+n2301 = (~InitReady+~RASr2)
+
+comp 22: SLICE_56 (FSLICE)
+n8MEGEN_N_94 = (~n4*(~FS_10*Cmdn8MEGEN+FS_10*~UFMSDO_c)+n4*Cmdn8MEGEN)
+n8MEGEN.D = n8MEGEN_N_94
+n8MEGEN.CLK = RCLK_c
+n8MEGEN.SP = RCLK_c_enable_7
+n8MEGEN.LSR = GND
+n4 = ((~FS_11+n2300)+InitReady)
+
+comp 23: SLICE_58 (FSLICE)
+nRCAS_N_157 = (~nRowColSel_N_35*(~n2117+~Ready)+nRowColSel_N_35*n2287)
+nRCAS_c.D = nRCAS_N_157
+nRCAS_c.CLK = RCLK_c
+nRCAS_c.SP = RCLK_c_enable_4
+nRCAS_c.LSR = GND
+n2287 = (~n2248*(~Ready*~RASr2+Ready*(~RASr2+~CBR))+n2248*(~Ready+(~RASr2+~CBR)))
+
+comp 24: SLICE_60 (FSLICE)
+nRCS_N_132 = (((~RCKE_c*nRowColSel_N_35*~RASr2)+(~n2117*~nRowColSel_N_35))*Ready)+((~InitReady+nRCS_N_135+~RASr2+~nRowColSel_N_35)*~Ready)
+nRCS_c.D = nRCS_N_132
+nRCS_c.CLK = RCLK_c
+nRCS_c.SP = RCLK_c_enable_4
+nRCS_c.LSR = GND
+
+comp 25: SLICE_61 (FSLICE)
+n33 = (~Ready*(n2244+n2297)+Ready*(n2244+n18))
+nRRAS_c.D = n33
+nRRAS_c.CLK = RCLK_c
+nRRAS_c.SP = VCC
+nRRAS_c.LSR = GND
+n50 = ((nRowColSel_N_33+nRRAS_c)+nRowColSel_N_32)
+RASr.D = ~nCRAS_c
+RASr.CLK = RCLK_c
+RASr.SP = VCC
+RASr.LSR = GND
+
+comp 26: SLICE_62 (FSLICE)
+n1369 = (~n2308*nUFMCS_c+n2308*~CmdUFMCS)
+nRWE_N_173.D = n705
+nRWE_N_173.CLK = RCLK_c
+nRWE_N_173.SP = RCLK_c_enable_23
+nRWE_N_173.LSR = GND
+nRCS_N_135.D = Ready_N_272
+nRCS_N_135.CLK = RCLK_c
+nRCS_N_135.SP = RCLK_c_enable_23
+nRCS_N_135.LSR = GND
+
+comp 27: SLICE_63 (FSLICE)
+nRWE_N_167 = (~n2292*(~Ready*~n2164+Ready*nRWE_N_174)+n2292*(~Ready+nRWE_N_174))
+nRWE_c.D = nRWE_N_167
+nRWE_c.CLK = RCLK_c
+nRWE_c.SP = RCLK_c_enable_3
+nRWE_c.LSR = GND
+nRWE_N_174 = (~nRowColSel_N_35*(~n1+n1627)+nRowColSel_N_35*nRWE_N_178)
+
+comp 28: SLICE_64 (FSLICE)
+n1368 = (~nRowColSel_N_32*(nRowColSel+n1627)+nRowColSel_N_32*(~nRowColSel_N_28+n1627))
+nRowColSel.D = n1368
+nRowColSel.CLK = RCLK_c
+nRowColSel.SP = VCC
+nRowColSel.LSR = n2299
+RA_c_4 = (~nRowColSel*RowA_4+nRowColSel*MAin_c_4)
+
+comp 29: SLICE_65 (FSLICE)
+n1628 = (nRowColSel_N_32+nRowColSel_N_33)
+nRowColSel_N_32.D = n1628
+nRowColSel_N_32.CLK = RCLK_c
+nRowColSel_N_32.SP = VCC
+nRowColSel_N_32.LSR = ~RASr2
+RCLK_c_enable_4 = (((nRowColSel_N_32+n2299)+nRowColSel_N_34)+nRowColSel_N_33)
+
+comp 30: SLICE_66 (FSLICE)
+n1135 = (RASr2*~nRowColSel_N_32)
+nRowColSel_N_33.D = n1135
+nRowColSel_N_33.CLK = RCLK_c
+nRowColSel_N_33.SP = VCC
+nRowColSel_N_33.LSR = ~nRowColSel_N_34
+n2117 = (~nRowColSel_N_33*(n1*~nRowColSel_N_34)+nRowColSel_N_33*(~n2304*~nRowColSel_N_34))
+
+comp 31: SLICE_67 (FSLICE)
+LED_N_90 = (~LEDEN+nCRAS_c)
+nRowColSel_N_34.D = n1135
+nRowColSel_N_34.CLK = RCLK_c
+nRowColSel_N_34.SP = VCC
+nRowColSel_N_34.LSR = ~nRowColSel_N_35
+n2154 = (MAin_c_4*Bank_7)
+
+comp 32: SLICE_68 (FSLICE)
+n2168 = (FS_3*(FS_2*(FS_0*FS_1)))
+nRowColSel_N_35.D = ~RASr2
+nRowColSel_N_35.CLK = RCLK_c
+nRowColSel_N_35.SP = VCC
+nRowColSel_N_35.LSR = GND
+n962 = (nCCAS_c+nFWE_c)
+CASr3.D = CASr2
+CASr3.CLK = RCLK_c
+CASr3.SP = VCC
+CASr3.LSR = GND
+
+comp 33: SLICE_69 (FSLICE)
+n1348 = (~InitReady*n2076+InitReady*n1369)
+nUFMCS_c.D = n1348
+nUFMCS_c.CLK = RCLK_c
+nUFMCS_c.SP = VCC
+nUFMCS_c.LSR = LEDEN_N_88
+n2076 = (FS_17*(FS_11*(n12_adj_2*FS_15)))
+
+comp 34: i1912/SLICE_70 (FSLICE)
+n2244 = (((~RCKE_c*nRowColSel_N_35*~RASr2)+(~nRowColSel_N_35*n50))*Ready)+(((~nRowColSel_N_35*n50)+~InitReady+~RASr2)*~Ready)
+
+comp 35: RCKEEN_I_0_419/SLICE_71 (FSLICE)
+RCKEEN_N_116 = (((~FWEr*~CBR)+~RASr2)*nRowColSel_N_35)+(((FWEr*n11_adj_3*~CBR)+(nRowColSel_N_34*~CBR))*~nRowColSel_N_35)
+
+comp 36: SLICE_72 (FSLICE)
+PHI2_N_114_enable_7 = (Din_c_5*(~n2296*(n2298*XOR8MEG_N_112)))
+n702.D = n703
+n702.CLK = RCLK_c
+n702.SP = RCLK_c_enable_23
+n702.LSR = GND
+n2298 = (((Din_c_6+Din_c_7)+Din_c_5)+Din_c_4)
+n701.D = n702
+n701.CLK = RCLK_c
+n701.SP = RCLK_c_enable_23
+n701.LSR = GND
+
+comp 37: SLICE_73 (FSLICE)
+n11 = (~n2168+((~FS_11+n2300)+FS_6))
+n706.D = n707
+n706.CLK = RCLK_c
+n706.SP = RCLK_c_enable_23
+n706.LSR = GND
+n2300 = ((FS_16+n10)+FS_17)
+n705.D = n706
+n705.CLK = RCLK_c
+n705.SP = RCLK_c_enable_23
+n705.LSR = GND
+
+comp 38: SLICE_74 (FSLICE)
+C1Submitted_N_225 = (~n2131*(~Din_c_2*(n2295*n2122)))
+n710.D = n711
+n710.CLK = RCLK_c
+n710.SP = RCLK_c_enable_23
+n710.LSR = GND
+n2295 = (n2114*~nFWE_c)
+n709.D = n710
+n709.CLK = RCLK_c
+n709.SP = RCLK_c_enable_23
+n709.LSR = GND
+
+comp 39: SLICE_75 (FSLICE)
+n2119 = (~n12*(~n11*(FS_10*n2294)))
+n708.D = n709
+n708.CLK = RCLK_c
+n708.SP = RCLK_c_enable_23
+n708.LSR = GND
+RCLK_c_enable_25 = (n2119*(FS_5*~InitReady))
+n707.D = n708
+n707.CLK = RCLK_c
+n707.SP = RCLK_c_enable_23
+n707.LSR = GND
+
+comp 40: SLICE_76 (FSLICE)
+n2131 = ((~MAin_c_1+n1285)+MAin_c_0)
+WRD_0.D = Din_c_0
+WRD_0.CLK = ~nCCAS_c
+WRD_0.SP = VCC
+WRD_0.LSR = GND
+n1285 = (~MAin_c_5+(~n2170+(~Bank_3+n26)))
+WRD_1.D = Din_c_1
+WRD_1.CLK = ~nCCAS_c
+WRD_1.SP = VCC
+WRD_1.LSR = GND
+
+comp 41: SLICE_77 (FSLICE)
+PHI2_N_114_enable_8 = (~MAin_c_1*(~n2286*(~n2290*MAin_c_0))+MAin_c_1*(~n2286*~n2290))
+RowA_2.D = MAin_c_2
+RowA_2.CLK = ~nCRAS_c
+RowA_2.SP = VCC
+RowA_2.LSR = ~Ready
+n2286 = (n2114*(~Din_c_2*n2080+Din_c_2*n2098))
+RowA_3.D = MAin_c_3
+RowA_3.CLK = ~nCRAS_c
+RowA_3.SP = VCC
+RowA_3.LSR = ~Ready
+
+comp 42: SLICE_78 (FSLICE)
+n10 = (((FS_14+FS_13)+FS_12)+FS_15)
+CASr.D = ~nCCAS_c
+CASr.CLK = RCLK_c
+CASr.SP = VCC
+CASr.LSR = GND
+n2294 = (((FS_16+n10)+FS_17)+FS_11)
+PHI2r2.D = PHI2r
+PHI2r2.CLK = RCLK_c
+PHI2r2.SP = VCC
+PHI2r2.LSR = GND
+
+comp 43: SLICE_79 (FSLICE)
+n1627 = (nRowColSel_N_34+nRowColSel_N_33)
+WRD_2.D = Din_c_2
+WRD_2.CLK = ~nCCAS_c
+WRD_2.SP = VCC
+WRD_2.LSR = GND
+RCLK_c_enable_3 = (((~Ready+nRowColSel_N_32)+n1627)+nRowColSel_N_35)
+WRD_3.D = Din_c_3
+WRD_3.CLK = ~nCCAS_c
+WRD_3.SP = VCC
+WRD_3.LSR = GND
+
+comp 44: SLICE_80 (FSLICE)
+ADSubmitted_N_234 = (~n2289*(n4_adj_1*(MAin_c_0*n2108)))
+WRD_6.D = Din_c_6
+WRD_6.CLK = ~nCCAS_c
+WRD_6.SP = VCC
+WRD_6.LSR = GND
+n2289 = (~MAin_c_1+n1285)
+WRD_7.D = Din_c_7
+WRD_7.CLK = ~nCCAS_c
+WRD_7.SP = VCC
+WRD_7.LSR = GND
+
+comp 45: SLICE_81 (FSLICE)
+n4_adj_1 = (n2114*(Din_c_2*~nFWE_c))
+RowA_8.D = MAin_c_8
+RowA_8.CLK = ~nCRAS_c
+RowA_8.SP = VCC
+RowA_8.LSR = ~Ready
+n2114 = (Din_c_7*(~Din_c_4*(~Din_c_1*Din_c_0)))
+RowA_9.D = MAin_c_9
+RowA_9.CLK = ~nCRAS_c
+RowA_9.SP = VCC
+RowA_9.LSR = ~Ready
+
+comp 46: SLICE_82 (FSLICE)
+n2166 = (Bank_6*(MAin_c_2*(Bank_5*Bank_0)))
+RowA_0.D = MAin_c_0
+RowA_0.CLK = ~nCRAS_c
+RowA_0.SP = VCC
+RowA_0.LSR = ~Ready
+n26 = (~MAin_c_6+(~n2154+(~n2166+Bank_2)))
+RowA_1.D = MAin_c_1
+RowA_1.CLK = ~nCRAS_c
+RowA_1.SP = VCC
+RowA_1.LSR = ~Ready
+
+comp 47: SLICE_83 (FSLICE)
+n2245 = (InitReady*(Ready_N_272*(~RASr2*nRowColSel_N_32)))
+CmdUFMCLK.D = Din_c_1
+CmdUFMCLK.CLK = ~PHI2_c
+CmdUFMCLK.SP = PHI2_N_114_enable_7
+CmdUFMCLK.LSR = GND
+Ready_N_268 = (n2245+Ready)
+CmdUFMCS.D = Din_c_2
+CmdUFMCS.CLK = ~PHI2_c
+CmdUFMCS.SP = PHI2_N_114_enable_7
+CmdUFMCS.LSR = GND
+
+comp 48: SLICE_84 (FSLICE)
+nRowColSel_N_28 = ((~FWEr+CASr3)+CBR)
+nRCAS_N_161.D = nRCS_N_135
+nRCAS_N_161.CLK = RCLK_c
+nRCAS_N_161.SP = RCLK_c_enable_23
+nRCAS_N_161.LSR = GND
+n1 = (~CASr3*(CASr2*(FWEr*~CBR)))
+n703.D = nRWE_N_173
+n703.CLK = RCLK_c
+n703.SP = RCLK_c_enable_23
+n703.LSR = GND
+
+comp 49: SLICE_85 (FSLICE)
+n12 = (((~FS_4+FS_9)+FS_8)+FS_7)
+PHI2r3.D = PHI2r2
+PHI2r3.CLK = RCLK_c
+PHI2r3.SP = VCC
+PHI2r3.LSR = GND
+n2103 = (~FS_9*(FS_7*~FS_8)+FS_9*(FS_5*(~FS_7*~FS_8)))
+PHI2r.D = PHI2_c
+PHI2r.CLK = RCLK_c
+PHI2r.SP = VCC
+PHI2r.LSR = GND
+
+comp 50: SLICE_86 (FSLICE)
+n2291 = (~InitReady*(~n2300*~FS_11))
+RowA_6.D = MAin_c_6
+RowA_6.CLK = ~nCRAS_c
+RowA_6.SP = VCC
+RowA_6.LSR = ~Ready
+LEDEN_N_88 = (~InitReady*(~FS_10*(~n2300*~FS_11)))
+RowA_7.D = MAin_c_7
+RowA_7.CLK = ~nCRAS_c
+RowA_7.SP = VCC
+RowA_7.LSR = ~Ready
+
+comp 51: SLICE_87 (FSLICE)
+n2122 = (~Din_c_5*(Din_c_6*~Din_c_3))
+Ready_N_272.D = n699
+Ready_N_272.CLK = RCLK_c
+Ready_N_272.SP = RCLK_c_enable_23
+Ready_N_272.LSR = GND
+n2108 = (Din_c_3*(Din_c_5*~Din_c_6))
+n711.D = nRCAS_N_161
+n711.CLK = RCLK_c
+n711.SP = RCLK_c_enable_23
+n711.LSR = GND
+
+comp 52: SLICE_88 (FSLICE)
+RDQMH_c = (~nRowColSel+MAin_c_9)
+CmdUFMSDI.D = Din_c_0
+CmdUFMSDI.CLK = ~PHI2_c
+CmdUFMSDI.SP = PHI2_N_114_enable_7
+CmdUFMSDI.LSR = GND
+RA_c_9 = (~nRowColSel*RowA_9+nRowColSel*MAin_c_9)
+
+comp 53: SLICE_89 (FSLICE)
+n2290 = (nFWE_c+n1285)
+LEDEN.D = ~UFMSDO_c
+LEDEN.CLK = RCLK_c
+LEDEN.SP = RCLK_c_enable_25
+LEDEN.LSR = GND
+PHI2_N_114_enable_1 = (MAin_c_1*(~n1285*~nFWE_c))
+
+comp 54: SLICE_90 (FSLICE)
+PHI2_N_114_enable_6 = (Din_c_4*(XOR8MEG_N_112*(~Din_c_7*~Din_c_6)))
+n700.D = n701
+n700.CLK = RCLK_c
+n700.SP = RCLK_c_enable_23
+n700.LSR = GND
+PHI2_N_114_enable_2 = (XOR8MEG_N_112*(~Din_c_5*(~Din_c_4*~n2385)))
+n699.D = n700
+n699.CLK = RCLK_c
+n699.SP = RCLK_c_enable_23
+n699.LSR = GND
+
+comp 55: SLICE_91 (FSLICE)
+n2248 = (~InitReady+(nRCAS_N_161+nRCS_N_135))
+CBR.D = ~nCCAS_c
+CBR.CLK = ~nCRAS_c
+CBR.SP = VCC
+CBR.LSR = GND
+n2292 = (~RASr2+(~InitReady+(~nRowColSel_N_35+nRCS_N_135)))
+FWEr.D = ~nFWE_c
+FWEr.CLK = ~nCRAS_c
+FWEr.SP = VCC
+FWEr.LSR = GND
+
+comp 56: SLICE_92 (FSLICE)
+RDQML_c = (~nRowColSel+~MAin_c_9)
+RowA_4.D = MAin_c_4
+RowA_4.CLK = ~nCRAS_c
+RowA_4.SP = VCC
+RowA_4.LSR = ~Ready
+RA_c_0 = (~nRowColSel*RowA_0+nRowColSel*MAin_c_0)
+RowA_5.D = MAin_c_5
+RowA_5.CLK = ~nCRAS_c
+RowA_5.SP = VCC
+RowA_5.LSR = ~Ready
+
+comp 57: SLICE_93 (FSLICE)
+n12_adj_2 = (FS_12*(FS_13*(FS_16*FS_14)))
+RASr2.D = RASr
+RASr2.CLK = RCLK_c
+RASr2.SP = VCC
+RASr2.LSR = GND
+n2293 = (~FS_11+((FS_16+n10)+FS_17))
+RASr3.D = RASr2
+RASr3.CLK = RCLK_c
+RASr3.SP = VCC
+RASr3.LSR = GND
+
+comp 58: SLICE_94 (FSLICE)
+RA_c_1 = (~nRowColSel*RowA_1+nRowColSel*MAin_c_1)
+Bank_0.D = Din_c_0
+Bank_0.CLK = PHI2_c
+Bank_0.SP = VCC
+Bank_0.LSR = GND
+RA_c_3 = (~nRowColSel*RowA_3+nRowColSel*MAin_c_3)
+Bank_1.D = Din_c_1
+Bank_1.CLK = PHI2_c
+Bank_1.SP = VCC
+Bank_1.LSR = GND
+
+comp 59: SLICE_95 (FSLICE)
+RA_c_8 = (~nRowColSel*RowA_8+nRowColSel*MAin_c_8)
+Bank_6.D = Din_c_6
+Bank_6.CLK = PHI2_c
+Bank_6.SP = VCC
+Bank_6.LSR = GND
+RA_c_2 = (~nRowColSel*RowA_2+nRowColSel*MAin_c_2)
+Bank_7.D = Din_c_7
+Bank_7.CLK = PHI2_c
+Bank_7.SP = VCC
+Bank_7.LSR = GND
+
+comp 60: SLICE_96 (FSLICE)
+n2299 = (~Ready+nRowColSel_N_35)
+XOR8MEG.D = Din_c_0
+XOR8MEG.CLK = ~PHI2_c
+XOR8MEG.SP = PHI2_N_114_enable_2
+XOR8MEG.LSR = GND
+n2297 = (~nRowColSel_N_35+nRCS_N_135)
+
+comp 61: SLICE_97 (FSLICE)
+RA_c_7 = (~nRowColSel*RowA_7+nRowColSel*MAin_c_7)
+Bank_4.D = Din_c_4
+Bank_4.CLK = PHI2_c
+Bank_4.SP = VCC
+Bank_4.LSR = GND
+n2170 = (Bank_1*(Bank_4*(MAin_c_3*MAin_c_7)))
+Bank_5.D = Din_c_5
+Bank_5.CLK = PHI2_c
+Bank_5.SP = VCC
+Bank_5.LSR = GND
+
+comp 62: SLICE_98 (FSLICE)
+RA_c_6 = (~nRowColSel*RowA_6+nRowColSel*MAin_c_6)
+Bank_2.D = Din_c_2
+Bank_2.CLK = PHI2_c
+Bank_2.SP = VCC
+Bank_2.LSR = GND
+RA_c_5 = (~nRowColSel*RowA_5+nRowColSel*MAin_c_5)
+Bank_3.D = Din_c_3
+Bank_3.CLK = PHI2_c
+Bank_3.SP = VCC
+Bank_3.LSR = GND
+
+comp 63: SLICE_99 (FSLICE)
+n2164 = (nRCAS_N_161+nRWE_N_173)
+RBA_c_0.D = CROW_c_0
+RBA_c_0.CLK = ~nCRAS_c
+RBA_c_0.SP = VCC
+RBA_c_0.LSR = ~Ready
+n18 = (nRowColSel_N_34*~nRowColSel_N_35)
+RBA_c_1.D = CROW_c_1
+RBA_c_1.CLK = ~nCRAS_c
+RBA_c_1.SP = VCC
+RBA_c_1.LSR = ~Ready
+
+comp 64: SLICE_100 (FSLICE)
+n11_adj_3 = (~CASr2+nRowColSel_N_33)
+WRD_4.D = Din_c_4
+WRD_4.CLK = ~nCCAS_c
+WRD_4.SP = VCC
+WRD_4.LSR = GND
+n2304 = (FWEr+CBR)
+WRD_5.D = Din_c_5
+WRD_5.CLK = ~nCCAS_c
+WRD_5.SP = VCC
+WRD_5.LSR = GND
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.ncd b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.ncd
new file mode 100644
index 0000000000000000000000000000000000000000..fa3d1271d2b8a91aaa5c3455186366cb54bf9687
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ziws#36?L*WNX>>KFRtjITo#!@G?NQ~j*&?zs9=0i~-uBfX>
zqZbuK(E@5L%f=OT@%b3Oq~zg#fasEPsj=LMEy~CeRpg2eXG2jguBdZZyC^S;7E)t{
z6A&XG;{FON|RNaYgFsym}%!3+vQ*P!z@%nP`PYdEvB(
z8d*24Xn!$AjFXS4b3v?}PmPNbu|+l?!Qj4L;i!16B@G*SBBA2hEE}+K6
zW?WJGkdNUD7UlU$Y6%qOV~a#%F-|_FE(Ni&lp6oAV~h9@u~g4qSBtNumO)VvSJcjv
zB`{7pbrsgB<~~!@TEFlH%qK!
zsjT0gC*%qSwV3F;4Cgy+oJPjnud<6IZk~#|!vU9j})sR&Ii#
zFs|qV(O54E#LCUoxZaH`TI}*Me5rOi$PgDj4L`TTe~O_MYlmwKCWoKQ>&=AA&M%gag!Zaw7{-ilo3U@Ls1Y{KSC_xcEM1Hguc$6VF?XTS{!>zC7T|ITwq18xM^
z((s($7S{pXn6N{94Y%yR=v}}~0B1BjaqSuWwX;Fk!J&pn=LXLQ+!U~@;W4A8oej7d
z;Dm-}UD69~-bpkktgolx=_?1@fLjpOQyZO{b7%9dfLjuFpf)-+_r|(U0B!}?R83Od
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z0PaFq2VcWOuIRBCa96+?4WHcMs4~Z3Aj69`|7!8Y&nPm?g3cOeN?X{
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zHbYC2T7E?fzC#QqY^&a+<;ps30S_VUHDBdUjTzEoDBz)lU7+KZ!zc1Px`z?A$ks+r
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z5jHI*PD4LL^2Lwp`YZ
zA#8;y;8^$+L$aeGbw;pb2y+6VjwS3gSEzA>O)dyE9;RQ2M24{0c_EJ@Y-UEN;|V*(
z5^4frr{{#4NZ2I#-4h^7DA**ZwS_tn+#I1M6LxA=s40Ym8xaBkYB&P>Trjb3&a@*g9XR#e_W{3UvV}
zAreand(IScDPe1Ep_UQ$tRvKN!q#MkT0z(|IiW5jY_%^`mawNop)LX?MB-w?o-&2}
z2VqazLR~`G6OK@q683mjsFj30mJ{kS!XEX7x}30lDAYee36Z#hu>Y7sUP;&^woq3Q
z_OK(=)r38i73vzo{+$!*TEZUmh4Kh{AQb94P(mcGC+vPx$QuZ|&lc)N!tQm1x{0uV
zWrez#uzPYsRS@G*BI|#coE7YBY-H{XO
zF2Zj2g~}0D84ATf36WSu*lnhecN2E2Ez~`P-Qo!KFTyIaLfuQ)%{ig&BkU$$sQU@K
zF%;?nP(magBOmFfY`bgoU0^ZxQy9E7aSB?am1G4q+c#LcL4a
zCx%elK^260kFZYzp>`1VSzf633ESfdwUe;VU7`AYOJ!4gbA|eputG+t&j|b85^4`&KNv!N4yqv37li#72=ygl
zKjnq`im;zOp}r>U7gwln2>WkFsBa1T)e`DE!v1FnRRC2G>U+X|3xxWCuwq`Q9|^1S
zg!+lF-(8`8ChU)lP`?oNrzO;X$*P1Q)UTilLj8}dN(MsxMpmWrLKVp>;t5qnR#8`|
z-^r?dGD7`9R@JeD`jf0m8(bw5pbA1I$*Q`6P${yiUS23dR@L`}qGVMASEzl+s)iY%
z>X229ETPh5#4baqx@5!$lGP(4cFJ+}$%yw|@!bYw#12oWhGfKhd7&DCvW03)M!ahX
z)r5?ACnuBv$`Yz68S%C+R5LQ-P1&V6C{wT&WW+YvuO%4~6a;HUM!YU-Tc`HOV8KFiIuZ}O&
z5yVU9ggTOVb+bYpMZ9{BP@{=g-xg{N@fw&yjU`?~E)vP3L4`scL%c@5P{$IlaZadl
z#A}ijYCQ1_N2m<(n%Y7gN4#dHP{$LmITwlK1W=(+6N%Tt7wQD!waf`MiFmEDLY+vw
z){anDeO9PbiPymq${}7y
zTd0?5gFkaz!SDWRXymyfj3zFWY86dnJNq
S: 1.302ns/0.000ns; real time: 5 secs 
+Level 2, iteration 1
+0(0.00%) conflict; 523(84.63%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.256ns/0.000ns; real time: 5 secs 
+Level 3, iteration 1
+0(0.00%) conflict; 511(82.69%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.228ns/0.000ns; real time: 5 secs 
+Level 4, iteration 1
+16(0.06%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 21:33:37 08/16/21
+Level 1, iteration 1
+0(0.00%) conflict; 16(2.59%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
+Level 2, iteration 1
+0(0.00%) conflict; 16(2.59%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
+Level 3, iteration 1
+0(0.00%) conflict; 16(2.59%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
+Level 4, iteration 1
+5(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
+Level 4, iteration 2
+2(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
+Level 4, iteration 3
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
+
+Start NBR section for setup/hold timing optimization with effort level 3 at 21:33:37 08/16/21
+
+Start NBR section for re-routing at 21:33:37 08/16/21
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
+
+Start NBR section for post-routing at 21:33:37 08/16/21
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 0 (0.00%)
+  Estimated worst slack : 1.213ns
+  Timing score : 0
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+Total CPU time 6 secs 
+Total REAL time: 6 secs 
+Completely routed.
+End of route.  618 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 0 
+
+Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = Completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack> = 1.213
+PAR_SUMMARY::Timing score> = 0.000
+PAR_SUMMARY::Worst  slack> = 0.339
+PAR_SUMMARY::Timing score> = 0.000
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 6 secs 
+Total REAL time to completion: 6 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.prf b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.prf
new file mode 100644
index 0000000..8dceb1f
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.prf
@@ -0,0 +1,165 @@
+SCHEMATIC START ;
+# map:  version Diamond (64-bit) 3.12.0.240.2 -- WARNING: Map write only section -- Mon Aug 16 21:33:30 2021
+
+SYSCONFIG INBUF=ON CONFIG_SECURE=OFF ;
+LOCATE COMP "RD[7]" SITE "71" ;
+LOCATE COMP "RD[6]" SITE "70" ;
+LOCATE COMP "RD[5]" SITE "69" ;
+LOCATE COMP "RD[4]" SITE "68" ;
+LOCATE COMP "RD[3]" SITE "67" ;
+LOCATE COMP "RD[2]" SITE "66" ;
+LOCATE COMP "RD[1]" SITE "65" ;
+LOCATE COMP "RD[0]" SITE "64" ;
+LOCATE COMP "Dout[7]" SITE "3" ;
+LOCATE COMP "Dout[6]" SITE "2" ;
+LOCATE COMP "Dout[5]" SITE "5" ;
+LOCATE COMP "Dout[4]" SITE "4" ;
+LOCATE COMP "Dout[3]" SITE "6" ;
+LOCATE COMP "Dout[2]" SITE "8" ;
+LOCATE COMP "Dout[1]" SITE "7" ;
+LOCATE COMP "Dout[0]" SITE "1" ;
+LOCATE COMP "LED" SITE "57" ;
+LOCATE COMP "RBA[1]" SITE "83" ;
+LOCATE COMP "RBA[0]" SITE "63" ;
+LOCATE COMP "RA[11]" SITE "79" ;
+LOCATE COMP "RA[10]" SITE "87" ;
+LOCATE COMP "RA[9]" SITE "85" ;
+LOCATE COMP "RA[8]" SITE "96" ;
+LOCATE COMP "RA[7]" SITE "100" ;
+LOCATE COMP "RA[6]" SITE "91" ;
+LOCATE COMP "RA[5]" SITE "95" ;
+LOCATE COMP "RA[4]" SITE "99" ;
+LOCATE COMP "RA[3]" SITE "97" ;
+LOCATE COMP "RA[2]" SITE "94" ;
+LOCATE COMP "RA[1]" SITE "89" ;
+LOCATE COMP "RA[0]" SITE "98" ;
+LOCATE COMP "nRCS" SITE "77" ;
+LOCATE COMP "RCKE" SITE "82" ;
+LOCATE COMP "nRWE" SITE "72" ;
+LOCATE COMP "nRRAS" SITE "73" ;
+LOCATE COMP "nRCAS" SITE "78" ;
+LOCATE COMP "RDQMH" SITE "76" ;
+LOCATE COMP "RDQML" SITE "61" ;
+LOCATE COMP "nUFMCS" SITE "53" ;
+LOCATE COMP "UFMCLK" SITE "58" ;
+LOCATE COMP "UFMSDI" SITE "56" ;
+LOCATE COMP "PHI2" SITE "39" ;
+LOCATE COMP "MAin[9]" SITE "51" ;
+LOCATE COMP "MAin[8]" SITE "50" ;
+LOCATE COMP "MAin[7]" SITE "44" ;
+LOCATE COMP "MAin[6]" SITE "49" ;
+LOCATE COMP "MAin[5]" SITE "45" ;
+LOCATE COMP "MAin[4]" SITE "46" ;
+LOCATE COMP "MAin[3]" SITE "47" ;
+LOCATE COMP "MAin[2]" SITE "37" ;
+LOCATE COMP "MAin[1]" SITE "38" ;
+LOCATE COMP "MAin[0]" SITE "23" ;
+LOCATE COMP "CROW[1]" SITE "34" ;
+LOCATE COMP "CROW[0]" SITE "32" ;
+LOCATE COMP "Din[7]" SITE "19" ;
+LOCATE COMP "Din[6]" SITE "20" ;
+LOCATE COMP "Din[5]" SITE "17" ;
+LOCATE COMP "Din[4]" SITE "18" ;
+LOCATE COMP "Din[3]" SITE "16" ;
+LOCATE COMP "Din[2]" SITE "14" ;
+LOCATE COMP "Din[1]" SITE "15" ;
+LOCATE COMP "Din[0]" SITE "21" ;
+LOCATE COMP "nCCAS" SITE "27" ;
+LOCATE COMP "nCRAS" SITE "43" ;
+LOCATE COMP "nFWE" SITE "22" ;
+LOCATE COMP "RCLK" SITE "86" ;
+LOCATE COMP "UFMSDO" SITE "55" ;
+PERIOD NET "PHI2_c" 350.000000 ns  ;
+USE PRIMARY NET "RCLK_c" ;
+PERIOD NET "nCCAS_c" 350.000000 ns  ;
+USE PRIMARY NET "PHI2_c" ;
+PERIOD NET "nCRAS_c" 350.000000 ns  ;
+USE PRIMARY NET "nCCAS_c" ;
+PERIOD NET "RCLK_c" 16.000000 ns  ;
+USE PRIMARY NET "nCRAS_c" ;
+SCHEMATIC END ;
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+OUTPUT PORT "RD[7]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[0]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[1]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[2]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[3]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[4]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[5]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[6]" LOAD 20.000000 pF ;
+OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ;
+OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ;
+OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ;
+OUTPUT PORT "nRWE" LOAD 10.000000 pF ;
+OUTPUT PORT "nRCAS" LOAD 10.000000 pF ;
+OUTPUT PORT "nRCS" LOAD 10.000000 pF ;
+OUTPUT PORT "nRRAS" LOAD 10.000000 pF ;
+OUTPUT PORT "RDQML" LOAD 10.000000 pF ;
+OUTPUT PORT "RDQMH" LOAD 10.000000 pF ;
+OUTPUT PORT "RCKE" LOAD 10.000000 pF ;
+OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ;
+OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[11]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[10]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[9]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[8]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[7]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[6]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[5]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[4]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[3]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[2]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[1]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[0]" LOAD 10.000000 pF ;
+OUTPUT PORT "LED" LOAD 25.000000 pF ;
+OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ;
+VOLTAGE 3.300 V;
+VCCIO_DERATE BANK 0 PERCENT -5; 
+VCCIO_DERATE PERCENT -5; 
+VCCIO_DERATE BANK 1 PERCENT -5; 
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+COMMERCIAL ;
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.pt b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.pt
new file mode 100644
index 0000000..916dbc3
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.pt
@@ -0,0 +1,10 @@
+-v
+10
+
+
+
+
+-gt
+-sethld
+-sp 3
+-sphld m
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.t2b b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.t2b
new file mode 100644
index 0000000..aa05f83
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.t2b
@@ -0,0 +1,2 @@
+
+-g ES:No
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.tw1 b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.tw1
new file mode 100644
index 0000000..21ca4c4
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.tw1
@@ -0,0 +1,2507 @@
+
+Loading design for application trce from file ram2gs_lcmxo640c_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 3
+Loading device for application trce from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
+Mon Aug 16 21:33:31 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO640C_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.prf 
+Design file:     ram2gs_lcmxo640c_impl1_map.ncd
+Preference file: ram2gs_lcmxo640c_impl1.prf
+Device,speed:    LCMXO640C,3
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            113 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 161.862ns (weighted slack = 323.724ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdSubmitted_384  (to PHI2_c -)
+
+   Delay:              12.873ns  (21.6% logic, 78.4% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.873ns physical path delay SLICE_95 to SLICE_19 meets
+    175.000ns delay constraint less
+      0.265ns CE_SET requirement (totaling 174.735ns) by 161.862ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_95.CLK to    SLICE_95.Q1 SLICE_95 (from PHI2_c)
+ROUTE         1   e 1.441    SLICE_95.Q1 to    SLICE_67.A1 Bank_7
+CTOF_DEL    ---     0.371    SLICE_67.A1 to    SLICE_67.F1 SLICE_67
+ROUTE         1   e 1.441    SLICE_67.F1 to    SLICE_82.C1 n2154
+CTOF_DEL    ---     0.371    SLICE_82.C1 to    SLICE_82.F1 SLICE_82
+ROUTE         1   e 1.441    SLICE_82.F1 to    SLICE_76.B1 n26
+CTOF_DEL    ---     0.371    SLICE_76.B1 to    SLICE_76.F1 SLICE_76
+ROUTE         4   e 1.441    SLICE_76.F1 to    SLICE_89.B0 n1285
+CTOF_DEL    ---     0.371    SLICE_89.B0 to    SLICE_89.F0 SLICE_89
+ROUTE         3   e 1.441    SLICE_89.F0 to    SLICE_18.D1 n2290
+CTOF_DEL    ---     0.371    SLICE_18.D1 to    SLICE_18.F1 SLICE_18
+ROUTE         3   e 1.441    SLICE_18.F1 to    SLICE_90.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371    SLICE_90.C0 to    SLICE_90.F0 SLICE_90
+ROUTE         2   e 1.441    SLICE_90.F0 to    SLICE_19.CE PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                   12.873   (21.6% logic, 78.4% route), 7 logic levels.
+
+Report:   26.276ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 348.000ns
+         The internal maximum frequency of the following component is 500.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    FSLICE     CLK            SLICE_76
+
+   Delay:               2.000ns -- based on Minimum Pulse Width
+
+Report:    2.000ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 348.000ns
+         The internal maximum frequency of the following component is 500.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    FSLICE     CLK            SLICE_77
+
+   Delay:               2.000ns -- based on Minimum Pulse Width
+
+Report:    2.000ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            395 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 5.575ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i14  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_391  (to RCLK_c +)
+
+   Delay:              10.181ns  (23.7% logic, 76.3% route), 6 logic levels.
+
+ Constraint Details:
+
+     10.181ns physical path delay SLICE_7 to SLICE_56 meets
+     16.000ns delay constraint less
+      0.244ns CE_SET requirement (totaling 15.756ns) by 5.575ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560    SLICE_7.CLK to     SLICE_7.Q0 SLICE_7 (from RCLK_c)
+ROUTE         3   e 1.441     SLICE_7.Q0 to    SLICE_78.A0 FS_14
+CTOF_DEL    ---     0.371    SLICE_78.A0 to    SLICE_78.F0 SLICE_78
+ROUTE         3   e 1.441    SLICE_78.F0 to    SLICE_73.B1 n10
+CTOF_DEL    ---     0.371    SLICE_73.B1 to    SLICE_73.F1 SLICE_73
+ROUTE         4   e 0.561    SLICE_73.F1 to    SLICE_73.B0 n2300
+CTOF_DEL    ---     0.371    SLICE_73.B0 to    SLICE_73.F0 SLICE_73
+ROUTE         1   e 1.441    SLICE_73.F0 to    SLICE_75.C0 n11
+CTOF_DEL    ---     0.371    SLICE_75.C0 to    SLICE_75.F0 SLICE_75
+ROUTE         2   e 1.441    SLICE_75.F0 to    SLICE_33.D1 n2119
+CTOF_DEL    ---     0.371    SLICE_33.D1 to    SLICE_33.F1 SLICE_33
+ROUTE         1   e 1.441    SLICE_33.F1 to    SLICE_56.CE RCLK_c_enable_7 (to RCLK_c)
+                  --------
+                   10.181   (23.7% logic, 76.3% route), 6 logic levels.
+
+Report:   10.425ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_373  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_55 and
+      5.637ns delay SLICE_55 to RA[10] (totaling 8.141ns) meets
+     12.500ns offset RCLK to RA[10] by 4.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_55.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_55 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_55.CLK to    SLICE_55.Q0 SLICE_55 (from RCLK_c)
+ROUTE         1   e 1.441    SLICE_55.Q0 to       87.PADDO n980
+DOPAD_DEL   ---     3.636       87.PADDO to         87.PAD RA[10]
+                  --------
+                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    8.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[9] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[9] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_88.C1 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_88.C1 to    SLICE_88.F1 SLICE_88
+ROUTE         1   e 1.441    SLICE_88.F1 to       85.PADDO RA_c_9
+DOPAD_DEL   ---     3.636       85.PADDO to         85.PAD RA[9]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[8] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[8] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_95.C0 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_95.C0 to    SLICE_95.F0 SLICE_95
+ROUTE         1   e 1.441    SLICE_95.F0 to       96.PADDO RA_c_8
+DOPAD_DEL   ---     3.636       96.PADDO to         96.PAD RA[8]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[7] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[7] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_97.C0 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_97.C0 to    SLICE_97.F0 SLICE_97
+ROUTE         1   e 1.441    SLICE_97.F0 to      100.PADDO RA_c_7
+DOPAD_DEL   ---     3.636      100.PADDO to        100.PAD RA[7]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[6] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[6] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_98.C0 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_98.C0 to    SLICE_98.F0 SLICE_98
+ROUTE         1   e 1.441    SLICE_98.F0 to       91.PADDO RA_c_6
+DOPAD_DEL   ---     3.636       91.PADDO to         91.PAD RA[6]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[5] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[5] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_98.C1 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_98.C1 to    SLICE_98.F1 SLICE_98
+ROUTE         1   e 1.441    SLICE_98.F1 to       95.PADDO RA_c_5
+DOPAD_DEL   ---     3.636       95.PADDO to         95.PAD RA[5]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.427ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     6.569ns  (69.5% logic, 30.5% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      6.569ns delay SLICE_64 to RA[4] (totaling 9.073ns) meets
+     12.500ns offset RCLK to RA[4] by 3.427ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.561    SLICE_64.Q0 to    SLICE_64.C1 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_64.C1 to    SLICE_64.F1 SLICE_64
+ROUTE         1   e 1.441    SLICE_64.F1 to       99.PADDO RA_c_4
+DOPAD_DEL   ---     3.636       99.PADDO to         99.PAD RA[4]
+                  --------
+                    6.569   (69.5% logic, 30.5% route), 3 logic levels.
+
+Report:    9.073ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[3] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[3] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_94.C1 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_94.C1 to    SLICE_94.F1 SLICE_94
+ROUTE         1   e 1.441    SLICE_94.F1 to       97.PADDO RA_c_3
+DOPAD_DEL   ---     3.636       97.PADDO to         97.PAD RA[3]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[2] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[2] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_95.C1 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_95.C1 to    SLICE_95.F1 SLICE_95
+ROUTE         1   e 1.441    SLICE_95.F1 to       94.PADDO RA_c_2
+DOPAD_DEL   ---     3.636       94.PADDO to         94.PAD RA[2]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[1] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[1] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_94.C0 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_94.C0 to    SLICE_94.F0 SLICE_94
+ROUTE         1   e 1.441    SLICE_94.F0 to       89.PADDO RA_c_1
+DOPAD_DEL   ---     3.636       89.PADDO to         89.PAD RA[1]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[0] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[0] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_92.C1 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_92.C1 to    SLICE_92.F1 SLICE_92
+ROUTE         1   e 1.441    SLICE_92.F1 to       98.PADDO RA_c_0
+DOPAD_DEL   ---     3.636       98.PADDO to         98.PAD RA[0]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_369  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_60 and
+      5.637ns delay SLICE_60 to nRCS (totaling 8.141ns) meets
+     12.500ns offset RCLK to nRCS by 4.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_60.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_60 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_60.CLK to    SLICE_60.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1   e 1.441    SLICE_60.Q0 to       77.PADDO nRCS_c
+DOPAD_DEL   ---     3.636       77.PADDO to         77.PAD nRCS
+                  --------
+                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    8.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_368  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_34 and
+      5.637ns delay SLICE_34 to RCKE (totaling 8.141ns) meets
+     12.500ns offset RCLK to RCKE by 4.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_34.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_34 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_34.CLK to    SLICE_34.Q0 SLICE_34 (from RCLK_c)
+ROUTE         4   e 1.441    SLICE_34.Q0 to       82.PADDO RCKE_c
+DOPAD_DEL   ---     3.636       82.PADDO to         82.PAD RCKE
+                  --------
+                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    8.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_372  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_63 and
+      5.637ns delay SLICE_63 to nRWE (totaling 8.141ns) meets
+     12.500ns offset RCLK to nRWE by 4.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_63 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE         1   e 1.441    SLICE_63.Q0 to       72.PADDO nRWE_c
+DOPAD_DEL   ---     3.636       72.PADDO to         72.PAD nRWE
+                  --------
+                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    8.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_61 and
+      5.637ns delay SLICE_61 to nRRAS (totaling 8.141ns) meets
+     12.500ns offset RCLK to nRRAS by 4.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_61.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_61 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_61.CLK to    SLICE_61.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2   e 1.441    SLICE_61.Q0 to       73.PADDO nRRAS_c
+DOPAD_DEL   ---     3.636       73.PADDO to         73.PAD nRRAS
+                  --------
+                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    8.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_371  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_58 and
+      5.637ns delay SLICE_58 to nRCAS (totaling 8.141ns) meets
+     12.500ns offset RCLK to nRCAS by 4.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_58.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_58 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_58.CLK to    SLICE_58.Q0 SLICE_58 (from RCLK_c)
+ROUTE         1   e 1.441    SLICE_58.Q0 to       78.PADDO nRCAS_c
+DOPAD_DEL   ---     3.636       78.PADDO to         78.PAD nRCAS
+                  --------
+                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    8.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RDQMH (totaling 9.953ns) meets
+     12.500ns offset RCLK to RDQMH by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_88.B0 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_88.B0 to    SLICE_88.F0 SLICE_88
+ROUTE         1   e 1.441    SLICE_88.F0 to       76.PADDO RDQMH_c
+DOPAD_DEL   ---     3.636       76.PADDO to         76.PAD RDQMH
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RDQML (totaling 9.953ns) meets
+     12.500ns offset RCLK to RDQML by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_92.B0 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_92.B0 to    SLICE_92.F0 SLICE_92
+ROUTE         1   e 1.441    SLICE_92.F0 to       61.PADDO RDQML_c
+DOPAD_DEL   ---     3.636       61.PADDO to         61.PAD RDQML
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |   350.000 ns|    26.276 ns|   7  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |    16.000 ns|    10.425 ns|   6  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.073 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 526 paths, 6 nets, and 420 connections (67.96% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
+Mon Aug 16 21:33:31 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO640C_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.prf 
+Design file:     ram2gs_lcmxo640c_impl1_map.ncd
+Preference file: ram2gs_lcmxo640c_impl1.prf
+Device,speed:    LCMXO640C,M
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            113 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.485ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_380  (from PHI2_c -)
+   Destination:    FF         Data in        ADSubmitted_380  (to PHI2_c -)
+
+   Delay:               0.462ns  (56.7% logic, 43.3% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.462ns physical path delay SLICE_9 to SLICE_9 meets
+     -0.023ns DIN_HLD and
+      0.000ns delay constraint requirement (totaling -0.023ns) by 0.485ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170    SLICE_9.CLK to     SLICE_9.Q0 SLICE_9 (from PHI2_c)
+ROUTE         2   e 0.199     SLICE_9.Q0 to     SLICE_9.C0 ADSubmitted
+CTOF_DEL    ---     0.092     SLICE_9.C0 to     SLICE_9.F0 SLICE_9
+ROUTE         1   e 0.001     SLICE_9.F0 to    SLICE_9.DI0 n1361 (to PHI2_c)
+                  --------
+                    0.462   (56.7% logic, 43.3% route), 2 logic levels.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            395 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.377ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i11  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i12  (to RCLK_c +)
+
+   Delay:               0.356ns  (44.1% logic, 55.9% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.356ns physical path delay SLICE_72 to SLICE_72 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint requirement (totaling -0.021ns) by 0.377ns
+
+ Physical Path Details:
+
+      Data path SLICE_72 to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_72.CLK to    SLICE_72.Q0 SLICE_72 (from RCLK_c)
+ROUTE         1   e 0.199    SLICE_72.Q0 to    SLICE_72.M1 n702 (to RCLK_c)
+                  --------
+                    0.356   (44.1% logic, 55.9% route), 1 logic levels.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_373  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_55 and
+      1.780ns delay SLICE_55 to RA[10] (totaling 2.559ns) meets
+      0.000ns hold offset RCLK to RA[10] by 2.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_55.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_55 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_55.CLK to    SLICE_55.Q0 SLICE_55 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_55.Q0 to       87.PADDO n980
+DOPAD_DEL   ---     1.108       87.PADDO to         87.PAD RA[10]
+                  --------
+                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
+
+Report:    2.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[9] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[9] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_88.C1 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_88.C1 to    SLICE_88.F1 SLICE_88
+ROUTE         1   e 0.515    SLICE_88.F1 to       85.PADDO RA_c_9
+DOPAD_DEL   ---     1.108       85.PADDO to         85.PAD RA[9]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[8] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[8] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_95.C0 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_95.C0 to    SLICE_95.F0 SLICE_95
+ROUTE         1   e 0.515    SLICE_95.F0 to       96.PADDO RA_c_8
+DOPAD_DEL   ---     1.108       96.PADDO to         96.PAD RA[8]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[7] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[7] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_97.C0 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_97.C0 to    SLICE_97.F0 SLICE_97
+ROUTE         1   e 0.515    SLICE_97.F0 to      100.PADDO RA_c_7
+DOPAD_DEL   ---     1.108      100.PADDO to        100.PAD RA[7]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[6] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[6] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_98.C0 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_98.C0 to    SLICE_98.F0 SLICE_98
+ROUTE         1   e 0.515    SLICE_98.F0 to       91.PADDO RA_c_6
+DOPAD_DEL   ---     1.108       91.PADDO to         91.PAD RA[6]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[5] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[5] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_98.C1 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_98.C1 to    SLICE_98.F1 SLICE_98
+ROUTE         1   e 0.515    SLICE_98.F1 to       95.PADDO RA_c_5
+DOPAD_DEL   ---     1.108       95.PADDO to         95.PAD RA[5]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.850ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     2.071ns  (65.5% logic, 34.5% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.071ns delay SLICE_64 to RA[4] (totaling 2.850ns) meets
+      0.000ns hold offset RCLK to RA[4] by 2.850ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.199    SLICE_64.Q0 to    SLICE_64.C1 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_64.C1 to    SLICE_64.F1 SLICE_64
+ROUTE         1   e 0.515    SLICE_64.F1 to       99.PADDO RA_c_4
+DOPAD_DEL   ---     1.108       99.PADDO to         99.PAD RA[4]
+                  --------
+                    2.071   (65.5% logic, 34.5% route), 3 logic levels.
+
+Report:    2.850ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[3] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[3] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_94.C1 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_94.C1 to    SLICE_94.F1 SLICE_94
+ROUTE         1   e 0.515    SLICE_94.F1 to       97.PADDO RA_c_3
+DOPAD_DEL   ---     1.108       97.PADDO to         97.PAD RA[3]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[2] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[2] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_95.C1 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_95.C1 to    SLICE_95.F1 SLICE_95
+ROUTE         1   e 0.515    SLICE_95.F1 to       94.PADDO RA_c_2
+DOPAD_DEL   ---     1.108       94.PADDO to         94.PAD RA[2]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[1] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[1] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_94.C0 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_94.C0 to    SLICE_94.F0 SLICE_94
+ROUTE         1   e 0.515    SLICE_94.F0 to       89.PADDO RA_c_1
+DOPAD_DEL   ---     1.108       89.PADDO to         89.PAD RA[1]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[0] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[0] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_92.C1 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_92.C1 to    SLICE_92.F1 SLICE_92
+ROUTE         1   e 0.515    SLICE_92.F1 to       98.PADDO RA_c_0
+DOPAD_DEL   ---     1.108       98.PADDO to         98.PAD RA[0]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_369  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_60 and
+      1.780ns delay SLICE_60 to nRCS (totaling 2.559ns) meets
+      0.000ns hold offset RCLK to nRCS by 2.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_60.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_60 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_60.CLK to    SLICE_60.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_60.Q0 to       77.PADDO nRCS_c
+DOPAD_DEL   ---     1.108       77.PADDO to         77.PAD nRCS
+                  --------
+                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
+
+Report:    2.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_368  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_34 and
+      1.780ns delay SLICE_34 to RCKE (totaling 2.559ns) meets
+      0.000ns hold offset RCLK to RCKE by 2.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_34.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_34 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_34.CLK to    SLICE_34.Q0 SLICE_34 (from RCLK_c)
+ROUTE         4   e 0.515    SLICE_34.Q0 to       82.PADDO RCKE_c
+DOPAD_DEL   ---     1.108       82.PADDO to         82.PAD RCKE
+                  --------
+                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
+
+Report:    2.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_372  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_63 and
+      1.780ns delay SLICE_63 to nRWE (totaling 2.559ns) meets
+      0.000ns hold offset RCLK to nRWE by 2.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_63 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_63.Q0 to       72.PADDO nRWE_c
+DOPAD_DEL   ---     1.108       72.PADDO to         72.PAD nRWE
+                  --------
+                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
+
+Report:    2.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_61 and
+      1.780ns delay SLICE_61 to nRRAS (totaling 2.559ns) meets
+      0.000ns hold offset RCLK to nRRAS by 2.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_61.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_61 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_61.CLK to    SLICE_61.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2   e 0.515    SLICE_61.Q0 to       73.PADDO nRRAS_c
+DOPAD_DEL   ---     1.108       73.PADDO to         73.PAD nRRAS
+                  --------
+                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
+
+Report:    2.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_371  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_58 and
+      1.780ns delay SLICE_58 to nRCAS (totaling 2.559ns) meets
+      0.000ns hold offset RCLK to nRCAS by 2.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_58.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_58 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_58.CLK to    SLICE_58.Q0 SLICE_58 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_58.Q0 to       78.PADDO nRCAS_c
+DOPAD_DEL   ---     1.108       78.PADDO to         78.PAD nRCAS
+                  --------
+                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
+
+Report:    2.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RDQMH (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RDQMH by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_88.B0 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_88.B0 to    SLICE_88.F0 SLICE_88
+ROUTE         1   e 0.515    SLICE_88.F0 to       76.PADDO RDQMH_c
+DOPAD_DEL   ---     1.108       76.PADDO to         76.PAD RDQMH
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RDQML (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RDQML by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_92.B0 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_92.B0 to    SLICE_92.F0 SLICE_92
+ROUTE         1   e 0.515    SLICE_92.F0 to       61.PADDO RDQML_c
+DOPAD_DEL   ---     1.108       61.PADDO to         61.PAD RDQML
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |            -|            -|   2  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |            -|            -|   1  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.850 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 526 paths, 6 nets, and 420 connections (67.96% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 0 (setup), 0 (hold)
+Score: 0 (setup), 0 (hold)
+Cumulative negative slack: 0 (0+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.twr b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.twr
new file mode 100644
index 0000000..546895c
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.twr
@@ -0,0 +1,4338 @@
+
+Loading design for application trce from file ram2gs_lcmxo640c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 3
+Loading device for application trce from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
+Mon Aug 16 21:33:37 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO640C_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf 
+Design file:     ram2gs_lcmxo640c_impl1.ncd
+Preference file: ram2gs_lcmxo640c_impl1.prf
+Device,speed:    LCMXO640C,3
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            113 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 161.362ns (weighted slack = 322.724ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdSubmitted_384  (to PHI2_c -)
+
+   Delay:              13.373ns  (20.8% logic, 79.2% route), 7 logic levels.
+
+ Constraint Details:
+
+     13.373ns physical path delay SLICE_95 to SLICE_19 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 161.362ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
+ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
+CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
+ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
+CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
+CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
+ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
+CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.899       R5C5A.F1 to       R5C7C.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C7C.C0 to       R5C7C.F0 SLICE_90
+ROUTE         2     1.672       R5C7C.F0 to       R9C8B.CE PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                   13.373   (20.8% logic, 79.2% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R9C8B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 161.494ns (weighted slack = 322.988ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS_385  (to PHI2_c -)
+                   FF                        CmdUFMCLK_386
+
+   Delay:              13.241ns  (21.0% logic, 79.0% route), 7 logic levels.
+
+ Constraint Details:
+
+     13.241ns physical path delay SLICE_95 to SLICE_83 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 161.494ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
+ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
+CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
+ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
+CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
+CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
+ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
+CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.899       R5C5A.F1 to       R5C7A.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C7A.C0 to       R5C7A.F0 SLICE_72
+ROUTE         2     1.540       R5C7A.F0 to       R7C8B.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   13.241   (21.0% logic, 79.0% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R7C8B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 161.494ns (weighted slack = 322.988ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMSDI_387  (to PHI2_c -)
+
+   Delay:              13.241ns  (21.0% logic, 79.0% route), 7 logic levels.
+
+ Constraint Details:
+
+     13.241ns physical path delay SLICE_95 to SLICE_88 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 161.494ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
+ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
+CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
+ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
+CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
+CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
+ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
+CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.899       R5C5A.F1 to       R5C7A.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C7A.C0 to       R5C7A.F0 SLICE_72
+ROUTE         2     1.540       R5C7A.F0 to       R4C9A.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   13.241   (21.0% logic, 79.0% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R4C9A.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 161.945ns (weighted slack = 323.890ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        Cmdn8MEGEN_383  (to PHI2_c -)
+
+   Delay:              12.790ns  (21.8% logic, 78.2% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.790ns physical path delay SLICE_95 to SLICE_23 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 161.945ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
+ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
+CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
+ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
+CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
+CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
+ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
+CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.899       R5C5A.F1 to       R5C7C.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C7C.C0 to       R5C7C.F0 SLICE_90
+ROUTE         2     1.089       R5C7C.F0 to       R6C7B.CE PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                   12.790   (21.8% logic, 78.2% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R6C7B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 161.961ns (weighted slack = 323.922ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        XOR8MEG_381  (to PHI2_c -)
+
+   Delay:              12.774ns  (21.8% logic, 78.2% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.774ns physical path delay SLICE_95 to SLICE_96 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 161.961ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
+ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
+CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
+ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
+CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
+CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
+ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
+CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.899       R5C5A.F1 to       R5C7C.C1 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C7C.C1 to       R5C7C.F1 SLICE_90
+ROUTE         1     1.073       R5C7C.F1 to       R5C8B.CE PHI2_N_114_enable_2 (to PHI2_c)
+                  --------
+                   12.774   (21.8% logic, 78.2% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R5C8B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.123ns (weighted slack = 324.246ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_378  (to PHI2_c -)
+
+   Delay:              12.703ns  (21.9% logic, 78.1% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.703ns physical path delay SLICE_95 to SLICE_18 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.174ns DIN_SET requirement (totaling 174.826ns) by 162.123ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
+ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
+CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
+ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
+CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.134       R4C2A.F1 to       R6C9A.B1 n1285
+CTOF_DEL    ---     0.371       R6C9A.B1 to       R6C9A.F1 SLICE_80
+ROUTE         1     0.696       R6C9A.F1 to       R6C9A.B0 n2289
+CTOF_DEL    ---     0.371       R6C9A.B0 to       R6C9A.F0 SLICE_80
+ROUTE         2     2.112       R6C9A.F0 to       R5C5A.B0 ADSubmitted_N_234
+CTOF_DEL    ---     0.371       R5C5A.B0 to       R5C5A.F0 SLICE_18
+ROUTE         1     0.000       R5C5A.F0 to      R5C5A.DI0 CmdEnable_N_236 (to PHI2_c)
+                  --------
+                   12.703   (21.9% logic, 78.1% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R5C5A.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.123ns (weighted slack = 324.246ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        ADSubmitted_380  (to PHI2_c -)
+
+   Delay:              12.703ns  (21.9% logic, 78.1% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.703ns physical path delay SLICE_95 to SLICE_9 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.174ns DIN_SET requirement (totaling 174.826ns) by 162.123ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
+ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
+CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
+ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
+CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.134       R4C2A.F1 to       R6C9A.B1 n1285
+CTOF_DEL    ---     0.371       R6C9A.B1 to       R6C9A.F1 SLICE_80
+ROUTE         1     0.696       R6C9A.F1 to       R6C9A.B0 n2289
+CTOF_DEL    ---     0.371       R6C9A.B0 to       R6C9A.F0 SLICE_80
+ROUTE         2     2.112       R6C9A.F0 to       R5C5B.B0 ADSubmitted_N_234
+CTOF_DEL    ---     0.371       R5C5B.B0 to       R5C5B.F0 SLICE_9
+ROUTE         1     0.000       R5C5B.F0 to      R5C5B.DI0 n1361 (to PHI2_c)
+                  --------
+                   12.703   (21.9% logic, 78.1% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R5C5B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.710ns (weighted slack = 325.420ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i5  (from PHI2_c +)
+   Destination:    FF         Data in        CmdSubmitted_384  (to PHI2_c -)
+
+   Delay:              12.025ns  (23.2% logic, 76.8% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.025ns physical path delay SLICE_97 to SLICE_19 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 162.710ns
+
+ Physical Path Details:
+
+      Data path SLICE_97 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_97 (from PHI2_c)
+ROUTE         1     1.643       R2C2A.Q1 to       R3C2C.B0 Bank_5
+CTOF_DEL    ---     0.371       R3C2C.B0 to       R3C2C.F0 SLICE_82
+ROUTE         1     0.958       R3C2C.F0 to       R3C2C.A1 n2166
+CTOF_DEL    ---     0.371       R3C2C.A1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
+CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
+ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
+CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.899       R5C5A.F1 to       R5C7C.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C7C.C0 to       R5C7C.F0 SLICE_90
+ROUTE         2     1.672       R5C7C.F0 to       R9C8B.CE PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                   12.025   (23.2% logic, 76.8% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_97:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R2C2A.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R9C8B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.842ns (weighted slack = 325.684ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i5  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS_385  (to PHI2_c -)
+                   FF                        CmdUFMCLK_386
+
+   Delay:              11.893ns  (23.4% logic, 76.6% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.893ns physical path delay SLICE_97 to SLICE_83 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 162.842ns
+
+ Physical Path Details:
+
+      Data path SLICE_97 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_97 (from PHI2_c)
+ROUTE         1     1.643       R2C2A.Q1 to       R3C2C.B0 Bank_5
+CTOF_DEL    ---     0.371       R3C2C.B0 to       R3C2C.F0 SLICE_82
+ROUTE         1     0.958       R3C2C.F0 to       R3C2C.A1 n2166
+CTOF_DEL    ---     0.371       R3C2C.A1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
+CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
+ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
+CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.899       R5C5A.F1 to       R5C7A.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C7A.C0 to       R5C7A.F0 SLICE_72
+ROUTE         2     1.540       R5C7A.F0 to       R7C8B.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   11.893   (23.4% logic, 76.6% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_97:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R2C2A.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R7C8B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.842ns (weighted slack = 325.684ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i5  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMSDI_387  (to PHI2_c -)
+
+   Delay:              11.893ns  (23.4% logic, 76.6% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.893ns physical path delay SLICE_97 to SLICE_88 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 162.842ns
+
+ Physical Path Details:
+
+      Data path SLICE_97 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_97 (from PHI2_c)
+ROUTE         1     1.643       R2C2A.Q1 to       R3C2C.B0 Bank_5
+CTOF_DEL    ---     0.371       R3C2C.B0 to       R3C2C.F0 SLICE_82
+ROUTE         1     0.958       R3C2C.F0 to       R3C2C.A1 n2166
+CTOF_DEL    ---     0.371       R3C2C.A1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
+CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
+ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
+CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.899       R5C5A.F1 to       R5C7A.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C7A.C0 to       R5C7A.F0 SLICE_72
+ROUTE         2     1.540       R5C7A.F0 to       R4C9A.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   11.893   (23.4% logic, 76.6% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_97:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R2C2A.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R4C9A.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:   27.276ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 348.000ns
+         The internal maximum frequency of the following component is 500.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    FSLICE     CLK            SLICE_76
+
+   Delay:               2.000ns -- based on Minimum Pulse Width
+
+Report:    2.000ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 348.000ns
+         The internal maximum frequency of the following component is 500.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    FSLICE     CLK            SLICE_77
+
+   Delay:               2.000ns -- based on Minimum Pulse Width
+
+Report:    2.000ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            395 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 6.557ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S_FSM_i4  (from RCLK_c +)
+   Destination:    FF         Data in        nRRAS_370  (to RCLK_c +)
+
+   Delay:               9.262ns  (20.9% logic, 79.1% route), 4 logic levels.
+
+ Constraint Details:
+
+      9.262ns physical path delay SLICE_65 to SLICE_61 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 15.819ns) by 6.557ns
+
+ Physical Path Details:
+
+      Data path SLICE_65 to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9C.CLK to       R5C9C.Q0 SLICE_65 (from RCLK_c)
+ROUTE         7     2.149       R5C9C.Q0 to       R3C2A.B1 nRowColSel_N_32
+CTOF_DEL    ---     0.371       R3C2A.B1 to       R3C2A.F1 SLICE_61
+ROUTE         2     2.624       R3C2A.F1 to       R8C9D.B0 n50
+CTOOFX_DEL  ---     0.631       R8C9D.B0 to     R8C9D.OFX0 i1912/SLICE_70
+ROUTE         1     2.556     R8C9D.OFX0 to       R3C2A.A0 n2244
+CTOF_DEL    ---     0.371       R3C2A.A0 to       R3C2A.F0 SLICE_61
+ROUTE         1     0.000       R3C2A.F0 to      R3C2A.DI0 n33 (to RCLK_c)
+                  --------
+                    9.262   (20.9% logic, 79.1% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_65:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R5C9C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 6.573ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S_FSM_i4  (from RCLK_c +)
+   Destination:    FF         Data in        nRRAS_370  (to RCLK_c +)
+
+   Delay:               9.246ns  (20.7% logic, 79.3% route), 4 logic levels.
+
+ Constraint Details:
+
+      9.246ns physical path delay SLICE_65 to SLICE_61 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 15.819ns) by 6.573ns
+
+ Physical Path Details:
+
+      Data path SLICE_65 to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9C.CLK to       R5C9C.Q0 SLICE_65 (from RCLK_c)
+ROUTE         7     2.149       R5C9C.Q0 to       R3C2A.B1 nRowColSel_N_32
+CTOF_DEL    ---     0.371       R3C2A.B1 to       R3C2A.F1 SLICE_61
+ROUTE         2     2.624       R3C2A.F1 to       R8C9D.B1 n50
+CTOOFX_DEL  ---     0.615       R8C9D.B1 to     R8C9D.OFX0 i1912/SLICE_70
+ROUTE         1     2.556     R8C9D.OFX0 to       R3C2A.A0 n2244
+CTOF_DEL    ---     0.371       R3C2A.A0 to       R3C2A.F0 SLICE_61
+ROUTE         1     0.000       R3C2A.F0 to      R3C2A.DI0 n33 (to RCLK_c)
+                  --------
+                    9.246   (20.7% logic, 79.3% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_65:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R5C9C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 6.866ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i15  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_392  (to RCLK_c +)
+
+   Delay:               8.890ns  (27.2% logic, 72.8% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.890ns physical path delay SLICE_7 to SLICE_89 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 6.866ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560     R10C7D.CLK to      R10C7D.Q1 SLICE_7 (from RCLK_c)
+ROUTE         3     1.466      R10C7D.Q1 to      R10C8D.B0 FS_15
+CTOF_DEL    ---     0.371      R10C8D.B0 to      R10C8D.F0 SLICE_78
+ROUTE         3     1.117      R10C8D.F0 to       R9C8A.B1 n10
+CTOF_DEL    ---     0.371       R9C8A.B1 to       R9C8A.F1 SLICE_73
+ROUTE         4     0.727       R9C8A.F1 to       R9C8A.B0 n2300
+CTOF_DEL    ---     0.371       R9C8A.B0 to       R9C8A.F0 SLICE_73
+ROUTE         1     0.626       R9C8A.F0 to       R9C8D.D0 n11
+CTOF_DEL    ---     0.371       R9C8D.D0 to       R9C8D.F0 SLICE_75
+ROUTE         2     0.513       R9C8D.F0 to       R9C8D.C1 n2119
+CTOF_DEL    ---     0.371       R9C8D.C1 to       R9C8D.F1 SLICE_75
+ROUTE         1     2.026       R9C8D.F1 to       R5C6A.CE RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    8.890   (27.2% logic, 72.8% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to     R10C7D.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R5C6A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 6.963ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S_FSM_i3  (from RCLK_c +)
+   Destination:    FF         Data in        nRRAS_370  (to RCLK_c +)
+
+   Delay:               8.856ns  (21.8% logic, 78.2% route), 4 logic levels.
+
+ Constraint Details:
+
+      8.856ns physical path delay SLICE_66 to SLICE_61 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 15.819ns) by 6.963ns
+
+ Physical Path Details:
+
+      Data path SLICE_66 to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9D.CLK to       R5C9D.Q0 SLICE_66 (from RCLK_c)
+ROUTE         6     1.743       R5C9D.Q0 to       R3C2A.D1 nRowColSel_N_33
+CTOF_DEL    ---     0.371       R3C2A.D1 to       R3C2A.F1 SLICE_61
+ROUTE         2     2.624       R3C2A.F1 to       R8C9D.B0 n50
+CTOOFX_DEL  ---     0.631       R8C9D.B0 to     R8C9D.OFX0 i1912/SLICE_70
+ROUTE         1     2.556     R8C9D.OFX0 to       R3C2A.A0 n2244
+CTOF_DEL    ---     0.371       R3C2A.A0 to       R3C2A.F0 SLICE_61
+ROUTE         1     0.000       R3C2A.F0 to      R3C2A.DI0 n33 (to RCLK_c)
+                  --------
+                    8.856   (21.8% logic, 78.2% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_66:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R5C9D.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 6.979ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S_FSM_i3  (from RCLK_c +)
+   Destination:    FF         Data in        nRRAS_370  (to RCLK_c +)
+
+   Delay:               8.840ns  (21.7% logic, 78.3% route), 4 logic levels.
+
+ Constraint Details:
+
+      8.840ns physical path delay SLICE_66 to SLICE_61 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 15.819ns) by 6.979ns
+
+ Physical Path Details:
+
+      Data path SLICE_66 to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9D.CLK to       R5C9D.Q0 SLICE_66 (from RCLK_c)
+ROUTE         6     1.743       R5C9D.Q0 to       R3C2A.D1 nRowColSel_N_33
+CTOF_DEL    ---     0.371       R3C2A.D1 to       R3C2A.F1 SLICE_61
+ROUTE         2     2.624       R3C2A.F1 to       R8C9D.B1 n50
+CTOOFX_DEL  ---     0.615       R8C9D.B1 to     R8C9D.OFX0 i1912/SLICE_70
+ROUTE         1     2.556     R8C9D.OFX0 to       R3C2A.A0 n2244
+CTOF_DEL    ---     0.371       R3C2A.A0 to       R3C2A.F0 SLICE_61
+ROUTE         1     0.000       R3C2A.F0 to      R3C2A.DI0 n33 (to RCLK_c)
+                  --------
+                    8.840   (21.7% logic, 78.3% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_66:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R5C9D.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.065ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i14  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_392  (to RCLK_c +)
+
+   Delay:               8.691ns  (27.8% logic, 72.2% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.691ns physical path delay SLICE_7 to SLICE_89 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 7.065ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560     R10C7D.CLK to      R10C7D.Q0 SLICE_7 (from RCLK_c)
+ROUTE         3     1.267      R10C7D.Q0 to      R10C8D.C0 FS_14
+CTOF_DEL    ---     0.371      R10C8D.C0 to      R10C8D.F0 SLICE_78
+ROUTE         3     1.117      R10C8D.F0 to       R9C8A.B1 n10
+CTOF_DEL    ---     0.371       R9C8A.B1 to       R9C8A.F1 SLICE_73
+ROUTE         4     0.727       R9C8A.F1 to       R9C8A.B0 n2300
+CTOF_DEL    ---     0.371       R9C8A.B0 to       R9C8A.F0 SLICE_73
+ROUTE         1     0.626       R9C8A.F0 to       R9C8D.D0 n11
+CTOF_DEL    ---     0.371       R9C8D.D0 to       R9C8D.F0 SLICE_75
+ROUTE         2     0.513       R9C8D.F0 to       R9C8D.C1 n2119
+CTOF_DEL    ---     0.371       R9C8D.C1 to       R9C8D.F1 SLICE_75
+ROUTE         1     2.026       R9C8D.F1 to       R5C6A.CE RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    8.691   (27.8% logic, 72.2% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to     R10C7D.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R5C6A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.284ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i13  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_392  (to RCLK_c +)
+
+   Delay:               8.472ns  (28.5% logic, 71.5% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.472ns physical path delay SLICE_8 to SLICE_89 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 7.284ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560     R10C7C.CLK to      R10C7C.Q1 SLICE_8 (from RCLK_c)
+ROUTE         3     1.048      R10C7C.Q1 to      R10C8D.A0 FS_13
+CTOF_DEL    ---     0.371      R10C8D.A0 to      R10C8D.F0 SLICE_78
+ROUTE         3     1.117      R10C8D.F0 to       R9C8A.B1 n10
+CTOF_DEL    ---     0.371       R9C8A.B1 to       R9C8A.F1 SLICE_73
+ROUTE         4     0.727       R9C8A.F1 to       R9C8A.B0 n2300
+CTOF_DEL    ---     0.371       R9C8A.B0 to       R9C8A.F0 SLICE_73
+ROUTE         1     0.626       R9C8A.F0 to       R9C8D.D0 n11
+CTOF_DEL    ---     0.371       R9C8D.D0 to       R9C8D.F0 SLICE_75
+ROUTE         2     0.513       R9C8D.F0 to       R9C8D.C1 n2119
+CTOF_DEL    ---     0.371       R9C8D.C1 to       R9C8D.F1 SLICE_75
+ROUTE         1     2.026       R9C8D.F1 to       R5C6A.CE RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    8.472   (28.5% logic, 71.5% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to     R10C7C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R5C6A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.601ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i12  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_392  (to RCLK_c +)
+
+   Delay:               8.155ns  (29.6% logic, 70.4% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.155ns physical path delay SLICE_8 to SLICE_89 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 7.601ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560     R10C7C.CLK to      R10C7C.Q0 SLICE_8 (from RCLK_c)
+ROUTE         3     0.731      R10C7C.Q0 to      R10C8D.D0 FS_12
+CTOF_DEL    ---     0.371      R10C8D.D0 to      R10C8D.F0 SLICE_78
+ROUTE         3     1.117      R10C8D.F0 to       R9C8A.B1 n10
+CTOF_DEL    ---     0.371       R9C8A.B1 to       R9C8A.F1 SLICE_73
+ROUTE         4     0.727       R9C8A.F1 to       R9C8A.B0 n2300
+CTOF_DEL    ---     0.371       R9C8A.B0 to       R9C8A.F0 SLICE_73
+ROUTE         1     0.626       R9C8A.F0 to       R9C8D.D0 n11
+CTOF_DEL    ---     0.371       R9C8D.D0 to       R9C8D.F0 SLICE_75
+ROUTE         2     0.513       R9C8D.F0 to       R9C8D.C1 n2119
+CTOF_DEL    ---     0.371       R9C8D.C1 to       R9C8D.F1 SLICE_75
+ROUTE         1     2.026       R9C8D.F1 to       R5C6A.CE RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    8.155   (29.6% logic, 70.4% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to     R10C7C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R5C6A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.732ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
+   Destination:    FF         Data in        nRRAS_370  (to RCLK_c +)
+
+   Delay:               8.087ns  (23.9% logic, 76.1% route), 4 logic levels.
+
+ Constraint Details:
+
+      8.087ns physical path delay SLICE_61 to SLICE_61 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 15.819ns) by 7.732ns
+
+ Physical Path Details:
+
+      Data path SLICE_61 to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2A.CLK to       R3C2A.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2     0.974       R3C2A.Q0 to       R3C2A.A1 nRRAS_c
+CTOF_DEL    ---     0.371       R3C2A.A1 to       R3C2A.F1 SLICE_61
+ROUTE         2     2.624       R3C2A.F1 to       R8C9D.B0 n50
+CTOOFX_DEL  ---     0.631       R8C9D.B0 to     R8C9D.OFX0 i1912/SLICE_70
+ROUTE         1     2.556     R8C9D.OFX0 to       R3C2A.A0 n2244
+CTOF_DEL    ---     0.371       R3C2A.A0 to       R3C2A.F0 SLICE_61
+ROUTE         1     0.000       R3C2A.F0 to      R3C2A.DI0 n33 (to RCLK_c)
+                  --------
+                    8.087   (23.9% logic, 76.1% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.748ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
+   Destination:    FF         Data in        nRRAS_370  (to RCLK_c +)
+
+   Delay:               8.071ns  (23.8% logic, 76.2% route), 4 logic levels.
+
+ Constraint Details:
+
+      8.071ns physical path delay SLICE_61 to SLICE_61 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 15.819ns) by 7.748ns
+
+ Physical Path Details:
+
+      Data path SLICE_61 to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2A.CLK to       R3C2A.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2     0.974       R3C2A.Q0 to       R3C2A.A1 nRRAS_c
+CTOF_DEL    ---     0.371       R3C2A.A1 to       R3C2A.F1 SLICE_61
+ROUTE         2     2.624       R3C2A.F1 to       R8C9D.B1 n50
+CTOOFX_DEL  ---     0.615       R8C9D.B1 to     R8C9D.OFX0 i1912/SLICE_70
+ROUTE         1     2.556     R8C9D.OFX0 to       R3C2A.A0 n2244
+CTOF_DEL    ---     0.371       R3C2A.A0 to       R3C2A.F0 SLICE_61
+ROUTE         1     0.000       R3C2A.F0 to      R3C2A.DI0 n33 (to RCLK_c)
+                  --------
+                    8.071   (23.8% logic, 76.2% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:    9.443ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.999ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_373  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_55 and
+      5.013ns delay SLICE_55 to RA[10] (totaling 7.501ns) meets
+     12.500ns offset RCLK to RA[10] by 4.999ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R2C5A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_55 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C5A.CLK to       R2C5A.Q0 SLICE_55 (from RCLK_c)
+ROUTE         1     0.817       R2C5A.Q0 to       87.PADDO n980
+DOPAD_DEL   ---     3.636       87.PADDO to         87.PAD RA[10]
+                  --------
+                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
+
+Report:    7.501ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.088ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     7.924ns  (57.6% logic, 42.4% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      7.924ns delay SLICE_64 to RA[9] (totaling 10.412ns) meets
+     12.500ns offset RCLK to RA[9] by 2.088ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.793       R5C9A.Q0 to       R4C9A.D1 nRowColSel
+CTOF_DEL    ---     0.371       R4C9A.D1 to       R4C9A.F1 SLICE_88
+ROUTE         1     2.564       R4C9A.F1 to       85.PADDO RA_c_9
+DOPAD_DEL   ---     3.636       85.PADDO to         85.PAD RA[9]
+                  --------
+                    7.924   (57.6% logic, 42.4% route), 3 logic levels.
+
+Report:   10.412ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.035ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     7.977ns  (57.3% logic, 42.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      7.977ns delay SLICE_64 to RA[8] (totaling 10.465ns) meets
+     12.500ns offset RCLK to RA[8] by 2.035ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.750       R5C9A.Q0 to       R3C2B.D0 nRowColSel
+CTOF_DEL    ---     0.371       R3C2B.D0 to       R3C2B.F0 SLICE_95
+ROUTE         1     1.660       R3C2B.F0 to       96.PADDO RA_c_8
+DOPAD_DEL   ---     3.636       96.PADDO to         96.PAD RA[8]
+                  --------
+                    7.977   (57.3% logic, 42.7% route), 3 logic levels.
+
+Report:   10.465ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.583ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     7.429ns  (61.5% logic, 38.5% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      7.429ns delay SLICE_64 to RA[7] (totaling 9.917ns) meets
+     12.500ns offset RCLK to RA[7] by 2.583ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     2.045       R5C9A.Q0 to       R2C2A.C0 nRowColSel
+CTOF_DEL    ---     0.371       R2C2A.C0 to       R2C2A.F0 SLICE_97
+ROUTE         1     0.817       R2C2A.F0 to      100.PADDO RA_c_7
+DOPAD_DEL   ---     3.636      100.PADDO to        100.PAD RA[7]
+                  --------
+                    7.429   (61.5% logic, 38.5% route), 3 logic levels.
+
+Report:    9.917ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     7.846ns  (58.2% logic, 41.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      7.846ns delay SLICE_64 to RA[6] (totaling 10.334ns) meets
+     12.500ns offset RCLK to RA[6] by 2.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.753       R5C9A.Q0 to       R2C3A.D0 nRowColSel
+CTOF_DEL    ---     0.371       R2C3A.D0 to       R2C3A.F0 SLICE_98
+ROUTE         1     1.526       R2C3A.F0 to       91.PADDO RA_c_6
+DOPAD_DEL   ---     3.636       91.PADDO to         91.PAD RA[6]
+                  --------
+                    7.846   (58.2% logic, 41.8% route), 3 logic levels.
+
+Report:   10.334ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     7.846ns  (58.2% logic, 41.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      7.846ns delay SLICE_64 to RA[5] (totaling 10.334ns) meets
+     12.500ns offset RCLK to RA[5] by 2.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.753       R5C9A.Q0 to       R2C3A.D1 nRowColSel
+CTOF_DEL    ---     0.371       R2C3A.D1 to       R2C3A.F1 SLICE_98
+ROUTE         1     1.526       R2C3A.F1 to       95.PADDO RA_c_5
+DOPAD_DEL   ---     3.636       95.PADDO to         95.PAD RA[5]
+                  --------
+                    7.846   (58.2% logic, 41.8% route), 3 logic levels.
+
+Report:   10.334ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.742ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     8.270ns  (55.2% logic, 44.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      8.270ns delay SLICE_64 to RA[4] (totaling 10.758ns) meets
+     12.500ns offset RCLK to RA[4] by 1.742ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.702       R5C9A.Q0 to       R5C9A.D1 nRowColSel
+CTOF_DEL    ---     0.371       R5C9A.D1 to       R5C9A.F1 SLICE_64
+ROUTE         1     3.001       R5C9A.F1 to       99.PADDO RA_c_4
+DOPAD_DEL   ---     3.636       99.PADDO to         99.PAD RA[4]
+                  --------
+                    8.270   (55.2% logic, 44.8% route), 3 logic levels.
+
+Report:   10.758ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.725ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     8.287ns  (55.1% logic, 44.9% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      8.287ns delay SLICE_64 to RA[3] (totaling 10.775ns) meets
+     12.500ns offset RCLK to RA[3] by 1.725ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     2.198       R5C9A.Q0 to       R2C2C.D1 nRowColSel
+CTOF_DEL    ---     0.371       R2C2C.D1 to       R2C2C.F1 SLICE_94
+ROUTE         1     1.522       R2C2C.F1 to       97.PADDO RA_c_3
+DOPAD_DEL   ---     3.636       97.PADDO to         97.PAD RA[3]
+                  --------
+                    8.287   (55.1% logic, 44.9% route), 3 logic levels.
+
+Report:   10.775ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.643ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     8.369ns  (54.6% logic, 45.4% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      8.369ns delay SLICE_64 to RA[2] (totaling 10.857ns) meets
+     12.500ns offset RCLK to RA[2] by 1.643ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.750       R5C9A.Q0 to       R3C2B.D1 nRowColSel
+CTOF_DEL    ---     0.371       R3C2B.D1 to       R3C2B.F1 SLICE_95
+ROUTE         1     2.052       R3C2B.F1 to       94.PADDO RA_c_2
+DOPAD_DEL   ---     3.636       94.PADDO to         94.PAD RA[2]
+                  --------
+                    8.369   (54.6% logic, 45.4% route), 3 logic levels.
+
+Report:   10.857ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.417ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     8.595ns  (53.1% logic, 46.9% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      8.595ns delay SLICE_64 to RA[1] (totaling 11.083ns) meets
+     12.500ns offset RCLK to RA[1] by 1.417ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     2.045       R5C9A.Q0 to       R2C2C.C0 nRowColSel
+CTOF_DEL    ---     0.371       R2C2C.C0 to       R2C2C.F0 SLICE_94
+ROUTE         1     1.983       R2C2C.F0 to       89.PADDO RA_c_1
+DOPAD_DEL   ---     3.636       89.PADDO to         89.PAD RA[1]
+                  --------
+                    8.595   (53.1% logic, 46.9% route), 3 logic levels.
+
+Report:   11.083ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.213ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     8.799ns  (51.9% logic, 48.1% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      8.799ns delay SLICE_64 to RA[0] (totaling 11.287ns) meets
+     12.500ns offset RCLK to RA[0] by 1.213ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.245       R5C9A.Q0 to       R8C9C.D1 nRowColSel
+CTOF_DEL    ---     0.371       R8C9C.D1 to       R8C9C.F1 SLICE_92
+ROUTE         1     2.987       R8C9C.F1 to       98.PADDO RA_c_0
+DOPAD_DEL   ---     3.636       98.PADDO to         98.PAD RA[0]
+                  --------
+                    8.799   (51.9% logic, 48.1% route), 3 logic levels.
+
+Report:   11.287ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.999ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_369  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_60 and
+      5.013ns delay SLICE_60 to nRCS (totaling 7.501ns) meets
+     12.500ns offset RCLK to nRCS by 4.999ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R2C9C.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_60 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C9C.CLK to       R2C9C.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1     0.817       R2C9C.Q0 to       77.PADDO nRCS_c
+DOPAD_DEL   ---     3.636       77.PADDO to         77.PAD nRCS
+                  --------
+                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
+
+Report:    7.501ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.999ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_368  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_34 and
+      5.013ns delay SLICE_34 to RCKE (totaling 7.501ns) meets
+     12.500ns offset RCLK to RCKE by 4.999ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R2C7C.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_34 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C7C.CLK to       R2C7C.Q0 SLICE_34 (from RCLK_c)
+ROUTE         4     0.817       R2C7C.Q0 to       82.PADDO RCKE_c
+DOPAD_DEL   ---     3.636       82.PADDO to         82.PAD RCKE
+                  --------
+                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
+
+Report:    7.501ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_372  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     6.653ns  (63.1% logic, 36.9% route), 2 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_63 and
+      6.653ns delay SLICE_63 to nRWE (totaling 9.141ns) meets
+     12.500ns offset RCLK to nRWE by 3.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to     R10C9C.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_63 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560     R10C9C.CLK to      R10C9C.Q0 SLICE_63 (from RCLK_c)
+ROUTE         1     2.457      R10C9C.Q0 to       72.PADDO nRWE_c
+DOPAD_DEL   ---     3.636       72.PADDO to         72.PAD nRWE
+                  --------
+                    6.653   (63.1% logic, 36.9% route), 2 logic levels.
+
+Report:    9.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.325ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     6.687ns  (62.7% logic, 37.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_61 and
+      6.687ns delay SLICE_61 to nRRAS (totaling 9.175ns) meets
+     12.500ns offset RCLK to nRRAS by 3.325ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_61 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2A.CLK to       R3C2A.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2     2.491       R3C2A.Q0 to       73.PADDO nRRAS_c
+DOPAD_DEL   ---     3.636       73.PADDO to         73.PAD nRRAS
+                  --------
+                    6.687   (62.7% logic, 37.3% route), 2 logic levels.
+
+Report:    9.175ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.999ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_371  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_58 and
+      5.013ns delay SLICE_58 to nRCAS (totaling 7.501ns) meets
+     12.500ns offset RCLK to nRCAS by 4.999ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R2C9B.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_58 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C9B.CLK to       R2C9B.Q0 SLICE_58 (from RCLK_c)
+ROUTE         1     0.817       R2C9B.Q0 to       78.PADDO nRCAS_c
+DOPAD_DEL   ---     3.636       78.PADDO to         78.PAD nRCAS
+                  --------
+                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
+
+Report:    7.501ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.669ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     7.343ns  (62.2% logic, 37.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      7.343ns delay SLICE_64 to RDQMH (totaling 9.831ns) meets
+     12.500ns offset RCLK to RDQMH by 2.669ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.793       R5C9A.Q0 to       R4C9A.D0 nRowColSel
+CTOF_DEL    ---     0.371       R4C9A.D0 to       R4C9A.F0 SLICE_88
+ROUTE         1     1.983       R4C9A.F0 to       76.PADDO RDQMH_c
+DOPAD_DEL   ---     3.636       76.PADDO to         76.PAD RDQMH
+                  --------
+                    7.343   (62.2% logic, 37.8% route), 3 logic levels.
+
+Report:    9.831ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.383ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     6.629ns  (68.9% logic, 31.1% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      6.629ns delay SLICE_64 to RDQML (totaling 9.117ns) meets
+     12.500ns offset RCLK to RDQML by 3.383ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.245       R5C9A.Q0 to       R8C9C.D0 nRowColSel
+CTOF_DEL    ---     0.371       R8C9C.D0 to       R8C9C.F0 SLICE_92
+ROUTE         1     0.817       R8C9C.F0 to       61.PADDO RDQML_c
+DOPAD_DEL   ---     3.636       61.PADDO to         61.PAD RDQML
+                  --------
+                    6.629   (68.9% logic, 31.1% route), 3 logic levels.
+
+Report:    9.117ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |   350.000 ns|    27.276 ns|   7  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |    16.000 ns|     9.443 ns|   4  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     7.501 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.412 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.465 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.917 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.334 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.334 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.758 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.775 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.857 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    11.083 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    11.287 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     7.501 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     7.501 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.175 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     7.501 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.831 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.117 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 526 paths, 6 nets, and 444 connections (71.84% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
+Mon Aug 16 21:33:37 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO640C_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf 
+Design file:     ram2gs_lcmxo640c_impl1.ncd
+Preference file: ram2gs_lcmxo640c_impl1.prf
+Device,speed:    LCMXO640C,m
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            113 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.447ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_380  (from PHI2_c -)
+   Destination:    FF         Data in        ADSubmitted_380  (to PHI2_c -)
+
+   Delay:               0.424ns  (61.8% logic, 38.2% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.424ns physical path delay SLICE_9 to SLICE_9 meets
+     -0.023ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.023ns) by 0.447ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C5B.CLK to       R5C5B.Q0 SLICE_9 (from PHI2_c)
+ROUTE         2     0.162       R5C5B.Q0 to       R5C5B.A0 ADSubmitted
+CTOF_DEL    ---     0.092       R5C5B.A0 to       R5C5B.F0 SLICE_9
+ROUTE         1     0.000       R5C5B.F0 to      R5C5B.DI0 n1361 (to PHI2_c)
+                  --------
+                    0.424   (61.8% logic, 38.2% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5B.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5B.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.113ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
+   Destination:    FF         Data in        XOR8MEG_381  (to PHI2_c -)
+
+   Delay:               1.084ns  (32.7% logic, 67.3% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.084ns physical path delay SLICE_18 to SLICE_96 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.113ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C5A.CLK to       R5C5A.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.238       R5C5A.Q0 to       R5C5A.A1 CmdEnable
+CTOF_DEL    ---     0.092       R5C5A.A1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.225       R5C5A.F1 to       R5C7C.C1 XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R5C7C.C1 to       R5C7C.F1 SLICE_90
+ROUTE         1     0.267       R5C7C.F1 to       R5C8B.CE PHI2_N_114_enable_2 (to PHI2_c)
+                  --------
+                    1.084   (32.7% logic, 67.3% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C8B.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.118ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
+   Destination:    FF         Data in        Cmdn8MEGEN_383  (to PHI2_c -)
+
+   Delay:               1.089ns  (32.5% logic, 67.5% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.089ns physical path delay SLICE_18 to SLICE_23 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.118ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C5A.CLK to       R5C5A.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.238       R5C5A.Q0 to       R5C5A.A1 CmdEnable
+CTOF_DEL    ---     0.092       R5C5A.A1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.225       R5C5A.F1 to       R5C7C.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R5C7C.C0 to       R5C7C.F0 SLICE_90
+ROUTE         2     0.272       R5C7C.F0 to       R6C7B.CE PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                    1.089   (32.5% logic, 67.5% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R6C7B.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.238ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMCS_385  (to PHI2_c -)
+                   FF                        CmdUFMCLK_386
+
+   Delay:               1.209ns  (29.3% logic, 70.7% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.209ns physical path delay SLICE_18 to SLICE_83 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.238ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C5A.CLK to       R5C5A.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.238       R5C5A.Q0 to       R5C5A.A1 CmdEnable
+CTOF_DEL    ---     0.092       R5C5A.A1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.225       R5C5A.F1 to       R5C7A.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R5C7A.C0 to       R5C7A.F0 SLICE_72
+ROUTE         2     0.392       R5C7A.F0 to       R7C8B.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                    1.209   (29.3% logic, 70.7% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R7C8B.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.238ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMSDI_387  (to PHI2_c -)
+
+   Delay:               1.209ns  (29.3% logic, 70.7% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.209ns physical path delay SLICE_18 to SLICE_88 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.238ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C5A.CLK to       R5C5A.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.238       R5C5A.Q0 to       R5C5A.A1 CmdEnable
+CTOF_DEL    ---     0.092       R5C5A.A1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.225       R5C5A.F1 to       R5C7A.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R5C7A.C0 to       R5C7A.F0 SLICE_72
+ROUTE         2     0.392       R5C7A.F0 to       R4C9A.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                    1.209   (29.3% logic, 70.7% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R4C9A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.270ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_380  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_378  (to PHI2_c -)
+
+   Delay:               1.241ns  (35.9% logic, 64.1% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.241ns physical path delay SLICE_9 to SLICE_18 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.270ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C5B.CLK to       R5C5B.Q0 SLICE_9 (from PHI2_c)
+ROUTE         2     0.258       R5C5B.Q0 to       R5C5B.B1 ADSubmitted
+CTOF_DEL    ---     0.092       R5C5B.B1 to       R5C5B.F1 SLICE_9
+ROUTE         1     0.123       R5C5B.F1 to       R5C5D.C1 n2080
+CTOF_DEL    ---     0.092       R5C5D.C1 to       R5C5D.F1 SLICE_77
+ROUTE         1     0.253       R5C5D.F1 to       R5C5D.B0 n2286
+CTOF_DEL    ---     0.092       R5C5D.B0 to       R5C5D.F0 SLICE_77
+ROUTE         1     0.161       R5C5D.F0 to       R5C5A.CE PHI2_N_114_enable_8 (to PHI2_c)
+                  --------
+                    1.241   (35.9% logic, 64.1% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5B.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.276ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
+   Destination:    FF         Data in        CmdSubmitted_384  (to PHI2_c -)
+
+   Delay:               1.247ns  (28.4% logic, 71.6% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.247ns physical path delay SLICE_18 to SLICE_19 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.276ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C5A.CLK to       R5C5A.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.238       R5C5A.Q0 to       R5C5A.A1 CmdEnable
+CTOF_DEL    ---     0.092       R5C5A.A1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.225       R5C5A.F1 to       R5C7C.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R5C7C.C0 to       R5C7C.F0 SLICE_90
+ROUTE         2     0.430       R5C7C.F0 to       R9C8B.CE PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                    1.247   (28.4% logic, 71.6% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R9C8B.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.299ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_379  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_378  (to PHI2_c -)
+
+   Delay:               1.270ns  (35.1% logic, 64.9% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.270ns physical path delay SLICE_14 to SLICE_18 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.299ns
+
+ Physical Path Details:
+
+      Data path SLICE_14 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C5C.CLK to       R5C5C.Q0 SLICE_14 (from PHI2_c)
+ROUTE         1     0.238       R5C5C.Q0 to       R5C5C.A1 C1Submitted
+CTOF_DEL    ---     0.092       R5C5C.A1 to       R5C5C.F1 SLICE_14
+ROUTE         1     0.172       R5C5C.F1 to       R5C5D.B1 n2098
+CTOF_DEL    ---     0.092       R5C5D.B1 to       R5C5D.F1 SLICE_77
+ROUTE         1     0.253       R5C5D.F1 to       R5C5D.B0 n2286
+CTOF_DEL    ---     0.092       R5C5D.B0 to       R5C5D.F0 SLICE_77
+ROUTE         1     0.161       R5C5D.F0 to       R5C5A.CE PHI2_N_114_enable_8 (to PHI2_c)
+                  --------
+                    1.270   (35.1% logic, 64.9% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5C.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 175.790ns (weighted slack = 351.580ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              XOR8MEG_381  (from PHI2_c -)
+   Destination:    FF         Data in        RA11_358  (to PHI2_c +)
+
+   Delay:               0.779ns  (33.6% logic, 66.4% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.779ns physical path delay SLICE_96 to SLICE_31 meets
+     -0.011ns DIN_HLD and
+    -175.000ns delay constraint less
+      0.000ns skew requirement (totaling -175.011ns) by 175.790ns
+
+ Physical Path Details:
+
+      Data path SLICE_96 to SLICE_31:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C8B.CLK to       R5C8B.Q0 SLICE_96 (from PHI2_c)
+ROUTE         1     0.517       R5C8B.Q0 to       R2C9A.B0 XOR8MEG
+CTOF_DEL    ---     0.092       R2C9A.B0 to       R2C9A.F0 SLICE_31
+ROUTE         1     0.000       R2C9A.F0 to      R2C9A.DI0 RA11_N_180 (to PHI2_c)
+                  --------
+                    0.779   (33.6% logic, 66.4% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C8B.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_31:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R2C9A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 176.484ns (weighted slack = 352.968ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i3  (from PHI2_c +)
+   Destination:    FF         Data in        C1Submitted_379  (to PHI2_c -)
+
+   Delay:               1.455ns  (23.4% logic, 76.6% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.455ns physical path delay SLICE_98 to SLICE_14 meets
+     -0.029ns CE_HLD and
+    -175.000ns delay constraint less
+      0.000ns skew requirement (totaling -175.029ns) by 176.484ns
+
+ Physical Path Details:
+
+      Data path SLICE_98 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C3A.CLK to       R2C3A.Q1 SLICE_98 (from PHI2_c)
+ROUTE         1     0.382       R2C3A.Q1 to       R4C2A.B1 Bank_3
+CTOF_DEL    ---     0.092       R4C2A.B1 to       R4C2A.F1 SLICE_76
+ROUTE         4     0.556       R4C2A.F1 to       R5C6A.B1 n1285
+CTOF_DEL    ---     0.092       R5C6A.B1 to       R5C6A.F1 SLICE_89
+ROUTE         1     0.176       R5C6A.F1 to       R5C5C.CE PHI2_N_114_enable_1 (to PHI2_c)
+                  --------
+                    1.455   (23.4% logic, 76.6% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_98:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R2C3A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5C.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            395 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i11  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i12  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_72 to SLICE_72 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_72 to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C7A.CLK to       R5C7A.Q0 SLICE_72 (from RCLK_c)
+ROUTE         1     0.161       R5C7A.Q0 to       R5C7A.M1 n702 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C7A.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C7A.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i12  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i13  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_72 to SLICE_90 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_72 to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C7A.CLK to       R5C7A.Q1 SLICE_72 (from RCLK_c)
+ROUTE         1     0.161       R5C7A.Q1 to       R5C7C.M0 n701 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C7A.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C7C.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i7  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i8  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_73 to SLICE_73 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_73 to SLICE_73:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R9C8A.CLK to       R9C8A.Q0 SLICE_73 (from RCLK_c)
+ROUTE         1     0.161       R9C8A.Q0 to       R9C8A.M1 n706 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_73:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R9C8A.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_73:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R9C8A.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i3  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i4  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_74 to SLICE_74 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_74 to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C6C.CLK to       R5C6C.Q0 SLICE_74 (from RCLK_c)
+ROUTE         1     0.161       R5C6C.Q0 to       R5C6C.M1 n710 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C6C.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C6C.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i6  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i7  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_75 to SLICE_73 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_75 to SLICE_73:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R9C8D.CLK to       R9C8D.Q1 SLICE_75 (from RCLK_c)
+ROUTE         1     0.161       R9C8D.Q1 to       R9C8A.M0 n707 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R9C8D.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_73:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R9C8A.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i5  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i6  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_75 to SLICE_75 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_75 to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R9C8D.CLK to       R9C8D.Q0 SLICE_75 (from RCLK_c)
+ROUTE         1     0.161       R9C8D.Q0 to       R9C8D.M1 n708 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R9C8D.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R9C8D.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              PHI2r_349  (from RCLK_c +)
+   Destination:    FF         Data in        PHI2r2_350  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_85 to SLICE_78 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_85 to SLICE_78:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157     R10C8C.CLK to      R10C8C.Q1 SLICE_85 (from RCLK_c)
+ROUTE         1     0.161      R10C8C.Q1 to      R10C8D.M1 PHI2r (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to     R10C8C.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_78:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to     R10C8D.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i2  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i3  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_87 to SLICE_74 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_87 to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C6B.CLK to       R5C6B.Q1 SLICE_87 (from RCLK_c)
+ROUTE         1     0.161       R5C6B.Q1 to       R5C6C.M0 n711 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_87:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C6B.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C6C.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i13  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i14  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_90 to SLICE_90 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_90 to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C7C.CLK to       R5C7C.Q0 SLICE_90 (from RCLK_c)
+ROUTE         1     0.161       R5C7C.Q0 to       R5C7C.M1 n700 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C7C.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C7C.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.345ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              PHI2r2_350  (from RCLK_c +)
+   Destination:    FF         Data in        PHI2r3_351  (to RCLK_c +)
+
+   Delay:               0.324ns  (48.5% logic, 51.5% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.324ns physical path delay SLICE_78 to SLICE_85 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.345ns
+
+ Physical Path Details:
+
+      Data path SLICE_78 to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157     R10C8D.CLK to      R10C8D.Q1 SLICE_78 (from RCLK_c)
+ROUTE         3     0.167      R10C8D.Q1 to      R10C8C.M0 PHI2r2 (to RCLK_c)
+                  --------
+                    0.324   (48.5% logic, 51.5% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_78:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to     R10C8D.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to     R10C8C.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.949ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_373  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_55 and
+      1.462ns delay SLICE_55 to RA[10] (totaling 1.949ns) meets
+      0.000ns hold offset RCLK to RA[10] by 1.949ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C5A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_55 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C5A.CLK to       R2C5A.Q0 SLICE_55 (from RCLK_c)
+ROUTE         1     0.197       R2C5A.Q0 to       87.PADDO n980
+DOPAD_DEL   ---     1.108       87.PADDO to         87.PAD RA[10]
+                  --------
+                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    1.949ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.668ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     2.181ns  (62.2% logic, 37.8% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.181ns delay SLICE_64 to RA[9] (totaling 2.668ns) meets
+      0.000ns hold offset RCLK to RA[9] by 2.668ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.199       R5C9A.Q0 to       R4C9A.D1 nRowColSel
+CTOF_DEL    ---     0.092       R4C9A.D1 to       R4C9A.F1 SLICE_88
+ROUTE         1     0.625       R4C9A.F1 to       85.PADDO RA_c_9
+DOPAD_DEL   ---     1.108       85.PADDO to         85.PAD RA[9]
+                  --------
+                    2.181   (62.2% logic, 37.8% route), 3 logic levels.
+
+Report:    2.668ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.689ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     2.202ns  (61.6% logic, 38.4% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.202ns delay SLICE_64 to RA[8] (totaling 2.689ns) meets
+      0.000ns hold offset RCLK to RA[8] by 2.689ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.451       R5C9A.Q0 to       R3C2B.D0 nRowColSel
+CTOF_DEL    ---     0.092       R3C2B.D0 to       R3C2B.F0 SLICE_95
+ROUTE         1     0.394       R3C2B.F0 to       96.PADDO RA_c_8
+DOPAD_DEL   ---     1.108       96.PADDO to         96.PAD RA[8]
+                  --------
+                    2.202   (61.6% logic, 38.4% route), 3 logic levels.
+
+Report:    2.689ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.572ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     2.085ns  (65.1% logic, 34.9% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.085ns delay SLICE_64 to RA[7] (totaling 2.572ns) meets
+      0.000ns hold offset RCLK to RA[7] by 2.572ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.531       R5C9A.Q0 to       R2C2A.C0 nRowColSel
+CTOF_DEL    ---     0.092       R2C2A.C0 to       R2C2A.F0 SLICE_97
+ROUTE         1     0.197       R2C2A.F0 to      100.PADDO RA_c_7
+DOPAD_DEL   ---     1.108      100.PADDO to        100.PAD RA[7]
+                  --------
+                    2.085   (65.1% logic, 34.9% route), 3 logic levels.
+
+Report:    2.572ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.652ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     2.165ns  (62.7% logic, 37.3% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.165ns delay SLICE_64 to RA[6] (totaling 2.652ns) meets
+      0.000ns hold offset RCLK to RA[6] by 2.652ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.452       R5C9A.Q0 to       R2C3A.D0 nRowColSel
+CTOF_DEL    ---     0.092       R2C3A.D0 to       R2C3A.F0 SLICE_98
+ROUTE         1     0.356       R2C3A.F0 to       91.PADDO RA_c_6
+DOPAD_DEL   ---     1.108       91.PADDO to         91.PAD RA[6]
+                  --------
+                    2.165   (62.7% logic, 37.3% route), 3 logic levels.
+
+Report:    2.652ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.652ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     2.165ns  (62.7% logic, 37.3% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.165ns delay SLICE_64 to RA[5] (totaling 2.652ns) meets
+      0.000ns hold offset RCLK to RA[5] by 2.652ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.452       R5C9A.Q0 to       R2C3A.D1 nRowColSel
+CTOF_DEL    ---     0.092       R2C3A.D1 to       R2C3A.F1 SLICE_98
+ROUTE         1     0.356       R2C3A.F1 to       95.PADDO RA_c_5
+DOPAD_DEL   ---     1.108       95.PADDO to         95.PAD RA[5]
+                  --------
+                    2.165   (62.7% logic, 37.3% route), 3 logic levels.
+
+Report:    2.652ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.776ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     2.289ns  (59.3% logic, 40.7% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.289ns delay SLICE_64 to RA[4] (totaling 2.776ns) meets
+      0.000ns hold offset RCLK to RA[4] by 2.776ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.178       R5C9A.Q0 to       R5C9A.D1 nRowColSel
+CTOF_DEL    ---     0.092       R5C9A.D1 to       R5C9A.F1 SLICE_64
+ROUTE         1     0.754       R5C9A.F1 to       99.PADDO RA_c_4
+DOPAD_DEL   ---     1.108       99.PADDO to         99.PAD RA[4]
+                  --------
+                    2.289   (59.3% logic, 40.7% route), 3 logic levels.
+
+Report:    2.776ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.772ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     2.285ns  (59.4% logic, 40.6% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.285ns delay SLICE_64 to RA[3] (totaling 2.772ns) meets
+      0.000ns hold offset RCLK to RA[3] by 2.772ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.571       R5C9A.Q0 to       R2C2C.D1 nRowColSel
+CTOF_DEL    ---     0.092       R2C2C.D1 to       R2C2C.F1 SLICE_94
+ROUTE         1     0.357       R2C2C.F1 to       97.PADDO RA_c_3
+DOPAD_DEL   ---     1.108       97.PADDO to         97.PAD RA[3]
+                  --------
+                    2.285   (59.4% logic, 40.6% route), 3 logic levels.
+
+Report:    2.772ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.787ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     2.300ns  (59.0% logic, 41.0% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.300ns delay SLICE_64 to RA[2] (totaling 2.787ns) meets
+      0.000ns hold offset RCLK to RA[2] by 2.787ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.451       R5C9A.Q0 to       R3C2B.D1 nRowColSel
+CTOF_DEL    ---     0.092       R3C2B.D1 to       R3C2B.F1 SLICE_95
+ROUTE         1     0.492       R3C2B.F1 to       94.PADDO RA_c_2
+DOPAD_DEL   ---     1.108       94.PADDO to         94.PAD RA[2]
+                  --------
+                    2.300   (59.0% logic, 41.0% route), 3 logic levels.
+
+Report:    2.787ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.855ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     2.368ns  (57.3% logic, 42.7% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.368ns delay SLICE_64 to RA[1] (totaling 2.855ns) meets
+      0.000ns hold offset RCLK to RA[1] by 2.855ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.531       R5C9A.Q0 to       R2C2C.C0 nRowColSel
+CTOF_DEL    ---     0.092       R2C2C.C0 to       R2C2C.F0 SLICE_94
+ROUTE         1     0.480       R2C2C.F0 to       89.PADDO RA_c_1
+DOPAD_DEL   ---     1.108       89.PADDO to         89.PAD RA[1]
+                  --------
+                    2.368   (57.3% logic, 42.7% route), 3 logic levels.
+
+Report:    2.855ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.893ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     2.406ns  (56.4% logic, 43.6% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.406ns delay SLICE_64 to RA[0] (totaling 2.893ns) meets
+      0.000ns hold offset RCLK to RA[0] by 2.893ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.310       R5C9A.Q0 to       R8C9C.D1 nRowColSel
+CTOF_DEL    ---     0.092       R8C9C.D1 to       R8C9C.F1 SLICE_92
+ROUTE         1     0.739       R8C9C.F1 to       98.PADDO RA_c_0
+DOPAD_DEL   ---     1.108       98.PADDO to         98.PAD RA[0]
+                  --------
+                    2.406   (56.4% logic, 43.6% route), 3 logic levels.
+
+Report:    2.893ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.949ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_369  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_60 and
+      1.462ns delay SLICE_60 to nRCS (totaling 1.949ns) meets
+      0.000ns hold offset RCLK to nRCS by 1.949ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C9C.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_60 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C9C.CLK to       R2C9C.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1     0.197       R2C9C.Q0 to       77.PADDO nRCS_c
+DOPAD_DEL   ---     1.108       77.PADDO to         77.PAD nRCS
+                  --------
+                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    1.949ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.949ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_368  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_34 and
+      1.462ns delay SLICE_34 to RCKE (totaling 1.949ns) meets
+      0.000ns hold offset RCLK to RCKE by 1.949ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C7C.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_34 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C7C.CLK to       R2C7C.Q0 SLICE_34 (from RCLK_c)
+ROUTE         4     0.197       R2C7C.Q0 to       82.PADDO RCKE_c
+DOPAD_DEL   ---     1.108       82.PADDO to         82.PAD RCKE
+                  --------
+                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    1.949ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.356ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_372  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     1.869ns  (67.7% logic, 32.3% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_63 and
+      1.869ns delay SLICE_63 to nRWE (totaling 2.356ns) meets
+      0.000ns hold offset RCLK to nRWE by 2.356ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to     R10C9C.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_63 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157     R10C9C.CLK to      R10C9C.Q0 SLICE_63 (from RCLK_c)
+ROUTE         1     0.604      R10C9C.Q0 to       72.PADDO nRWE_c
+DOPAD_DEL   ---     1.108       72.PADDO to         72.PAD nRWE
+                  --------
+                    1.869   (67.7% logic, 32.3% route), 2 logic levels.
+
+Report:    2.356ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.363ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     1.876ns  (67.4% logic, 32.6% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_61 and
+      1.876ns delay SLICE_61 to nRRAS (totaling 2.363ns) meets
+      0.000ns hold offset RCLK to nRRAS by 2.363ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_61 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R3C2A.CLK to       R3C2A.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2     0.611       R3C2A.Q0 to       73.PADDO nRRAS_c
+DOPAD_DEL   ---     1.108       73.PADDO to         73.PAD nRRAS
+                  --------
+                    1.876   (67.4% logic, 32.6% route), 2 logic levels.
+
+Report:    2.363ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.949ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_371  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_58 and
+      1.462ns delay SLICE_58 to nRCAS (totaling 1.949ns) meets
+      0.000ns hold offset RCLK to nRCAS by 1.949ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C9B.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_58 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C9B.CLK to       R2C9B.Q0 SLICE_58 (from RCLK_c)
+ROUTE         1     0.197       R2C9B.Q0 to       78.PADDO nRCAS_c
+DOPAD_DEL   ---     1.108       78.PADDO to         78.PAD nRCAS
+                  --------
+                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    1.949ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.523ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     2.036ns  (66.7% logic, 33.3% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.036ns delay SLICE_64 to RDQMH (totaling 2.523ns) meets
+      0.000ns hold offset RCLK to RDQMH by 2.523ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.199       R5C9A.Q0 to       R4C9A.D0 nRowColSel
+CTOF_DEL    ---     0.092       R4C9A.D0 to       R4C9A.F0 SLICE_88
+ROUTE         1     0.480       R4C9A.F0 to       76.PADDO RDQMH_c
+DOPAD_DEL   ---     1.108       76.PADDO to         76.PAD RDQMH
+                  --------
+                    2.036   (66.7% logic, 33.3% route), 3 logic levels.
+
+Report:    2.523ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.351ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     1.864ns  (72.8% logic, 27.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      1.864ns delay SLICE_64 to RDQML (totaling 2.351ns) meets
+      0.000ns hold offset RCLK to RDQML by 2.351ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.310       R5C9A.Q0 to       R8C9C.D0 nRowColSel
+CTOF_DEL    ---     0.092       R8C9C.D0 to       R8C9C.F0 SLICE_92
+ROUTE         1     0.197       R8C9C.F0 to       61.PADDO RDQML_c
+DOPAD_DEL   ---     1.108       61.PADDO to         61.PAD RDQML
+                  --------
+                    1.864   (72.8% logic, 27.2% route), 3 logic levels.
+
+Report:    2.351ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |            -|            -|   2  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |            -|            -|   1  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.668 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.689 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.572 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.652 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.652 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.776 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.772 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.787 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.855 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.893 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.356 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.363 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.523 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.351 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 526 paths, 6 nets, and 444 connections (71.84% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 0 (setup), 0 (hold)
+Score: 0 (setup), 0 (hold)
+Cumulative negative slack: 0 (0+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_bgn.html b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_bgn.html
new file mode 100644
index 0000000..b9ec128
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_bgn.html
@@ -0,0 +1,111 @@
+
+Bitgen Report
+
+
+
+
+
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_iotiming.html b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_iotiming.html
new file mode 100644
index 0000000..4d7032d
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_iotiming.html
@@ -0,0 +1,202 @@
+
+I/O Timing Report
+
+
+
    I/O Timing Report
+Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 4
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 5
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: M
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+// Design: RAM2GS
+// Package: TQFP100
+// ncd File: ram2gs_lcmxo640c_impl1.ncd
+// Version: Diamond (64-bit) 3.12.0.240.2
+// Written on Mon Aug 16 21:33:38 2021
+// M: Minimum Performance Grade
+// iotiming RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml
+
+I/O Timing Report (All units are in ns)
+
+Worst Case Results across Performance Grades (M, 5, 4, 3):
+
+// Input Setup and Hold Times
+
+Port    Clock Edge  Setup Performance_Grade  Hold Performance_Grade
+----------------------------------------------------------------------
+CROW[0] nCRAS F     0.474      3       1.625     3
+CROW[1] nCRAS F     0.104      3       1.925     3
+Din[0]  PHI2  F     6.682      3       1.613     3
+Din[0]  nCCAS F    -0.028      M       2.082     3
+Din[1]  PHI2  F     6.886      3       2.631     3
+Din[1]  nCCAS F    -0.025      M       2.074     3
+Din[2]  PHI2  F     5.426      3       1.921     3
+Din[2]  nCCAS F     1.175      3       1.003     3
+Din[3]  PHI2  F     5.699      3       1.852     3
+Din[3]  nCCAS F     0.331      3       1.707     3
+Din[4]  PHI2  F     6.556      3       1.438     3
+Din[4]  nCCAS F     0.706      3       1.406     3
+Din[5]  PHI2  F     6.281      3       1.959     3
+Din[5]  nCCAS F     0.246      3       1.807     3
+Din[6]  PHI2  F     5.585      3       1.441     3
+Din[6]  nCCAS F     0.799      3       1.341     3
+Din[7]  PHI2  F     7.980      3       1.725     3
+Din[7]  nCCAS F     0.333      3       1.707     3
+MAin[0] PHI2  F     4.994      3       1.265     3
+MAin[0] nCRAS F     0.662      3       1.471     3
+MAin[1] PHI2  F     6.056      3       1.867     3
+MAin[1] nCRAS F     1.180      3       0.990     3
+MAin[2] PHI2  F    10.634      3      -1.183     M
+MAin[2] nCRAS F    -0.218      M       2.631     3
+MAin[3] PHI2  F    10.902      3      -1.260     M
+MAin[3] nCRAS F     0.208      3       1.826     3
+MAin[4] PHI2  F    10.204      3      -1.072     M
+MAin[4] nCRAS F    -0.218      M       2.628     3
+MAin[5] PHI2  F     7.043      3      -0.270     M
+MAin[5] nCRAS F     0.123      3       1.925     3
+MAin[6] PHI2  F     9.465      3      -0.885     M
+MAin[6] nCRAS F     0.584      3       1.522     3
+MAin[7] PHI2  F     9.683      3      -0.938     M
+MAin[7] nCRAS F    -0.218      M       2.628     3
+MAin[8] nCRAS F     0.316      3       1.758     3
+MAin[9] nCRAS F    -0.058      M       2.185     3
+PHI2    RCLK  R     1.456      3       0.038     3
+UFMSDO  RCLK  R     2.953      3      -0.147     M
+nCCAS   RCLK  R     2.435      3      -0.244     M
+nCCAS   nCRAS F     0.156      3       1.902     3
+nCRAS   RCLK  R     5.307      3      -0.787     M
+nFWE    PHI2  F     5.614      3       1.072     3
+nFWE    nCRAS F    -0.101      M       2.317     3
+
+
+// Clock to Output Delay
+
+Port   Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
+------------------------------------------------------------------------
+LED    RCLK  R    11.635         3        3.019          M
+RA[0]  RCLK  R    11.287         3        2.893          M
+RA[0]  nCRAS F    15.323         3        3.902          M
+RA[10] RCLK  R     7.501         3        1.949          M
+RA[11] PHI2  R     9.747         3        2.487          M
+RA[1]  RCLK  R    11.083         3        2.855          M
+RA[1]  nCRAS F    12.034         3        3.047          M
+RA[2]  RCLK  R    10.857         3        2.787          M
+RA[2]  nCRAS F    13.411         3        3.403          M
+RA[3]  RCLK  R    10.775         3        2.772          M
+RA[3]  nCRAS F    12.977         3        3.296          M
+RA[4]  RCLK  R    10.758         3        2.776          M
+RA[4]  nCRAS F    14.192         3        3.619          M
+RA[5]  RCLK  R    10.334         3        2.652          M
+RA[5]  nCRAS F    13.484         3        3.424          M
+RA[6]  RCLK  R    10.334         3        2.652          M
+RA[6]  nCRAS F    12.972         3        3.291          M
+RA[7]  RCLK  R     9.917         3        2.572          M
+RA[7]  nCRAS F    12.327         3        3.147          M
+RA[8]  RCLK  R    10.465         3        2.689          M
+RA[8]  nCRAS F    12.559         3        3.170          M
+RA[9]  RCLK  R    10.412         3        2.668          M
+RA[9]  nCRAS F    14.019         3        3.564          M
+RBA[0] nCRAS F    11.063         3        2.809          M
+RBA[1] nCRAS F    11.902         3        3.028          M
+RCKE   RCLK  R     7.501         3        1.949          M
+RDQMH  RCLK  R     9.831         3        2.523          M
+RDQML  RCLK  R     9.117         3        2.351          M
+RD[0]  nCCAS F    12.575         3        3.249          M
+RD[1]  nCCAS F    13.016         3        3.365          M
+RD[2]  nCCAS F    11.602         3        2.993          M
+RD[3]  nCCAS F    10.893         3        2.834          M
+RD[4]  nCCAS F    12.063         3        3.116          M
+RD[5]  nCCAS F    12.555         3        3.242          M
+RD[6]  nCCAS F    12.537         3        3.240          M
+RD[7]  nCCAS F    12.524         3        3.239          M
+UFMCLK RCLK  R     8.079         3        2.126          M
+UFMSDI RCLK  R     8.079         3        2.126          M
+nRCAS  RCLK  R     7.501         3        1.949          M
+nRCS   RCLK  R     7.501         3        1.949          M
+nRRAS  RCLK  R     9.175         3        2.363          M
+nRWE   RCLK  R     9.141         3        2.356          M
+nUFMCS RCLK  R     8.804         3        2.290          M
+WARNING: you must also run trce with hold speed: 3
+WARNING: you must also run trce with setup speed: M
+
+
+
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diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_lattice.synproj b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_lattice.synproj
new file mode 100644
index 0000000..f265fc9
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_lattice.synproj
@@ -0,0 +1,41 @@
+-a "MachXO"
+-d LCMXO640C
+-t TQFP100
+-s 3
+-frequency 200
+-optimization_goal Balanced
+-bram_utilization 100
+-ramstyle Auto
+-romstyle auto
+-dsp_utilization 100
+-use_dsp 1
+-use_carry_chain 1
+-carry_chain_length 0
+-force_gsr Auto
+-resource_sharing 1
+-propagate_constants 1
+-remove_duplicate_regs 1
+-mux_style Auto
+-max_fanout 1000
+-fsm_encoding_style Auto
+-twr_paths 3
+-fix_gated_clocks 1
+-loop_limit 1950
+
+
+
+-use_io_insertion 1
+-resolve_mixed_drivers 0
+-use_io_reg auto
+
+
+-lpf 1
+-p "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C"
+-ver "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v"
+-top RAM2GS
+
+
+-p "C:/lscc/diamond/3.12/ispfpga/mj5g00/data" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/impl1" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C"
+
+-ngd "RAM2GS_LCMXO640C_impl1.ngd"
+
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.asd b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.asd
new file mode 100644
index 0000000..a946767
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.asd
@@ -0,0 +1,13 @@
+[ActiveSupport MAP]
+Device = LCMXO640C;
+Package = TQFP100;
+Performance = 3;
+LUTS_avail = 640;
+LUTS_used = 129;
+FF_avail = 640;
+FF_used = 102;
+INPUT_LVTTL33 = 26;
+OUTPUT_LVTTL33 = 33;
+BIDI_LVTTL33 = 8;
+IO_avail = 74;
+IO_used = 67;
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.cam b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.cam
new file mode 100644
index 0000000..4787547
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.cam
@@ -0,0 +1,108 @@
+[ START MERGED ]
+nCRAS_N_9 nCRAS_c
+nCCAS_N_3 nCCAS_c
+n2307 Ready
+n2306 nFWE_c
+PHI2_N_114 PHI2_c
+n2302 nRowColSel_N_35
+nRWE_N_172 nRWE_N_173
+UFMSDO_N_74 UFMSDO_c
+n1377 nRowColSel_N_34
+RASr2_N_63 RASr2
+[ END MERGED ]
+[ START CLIPPED ]
+GND_net
+VCC_net
+FS_577_add_4_14/CO0
+FS_577_add_4_16/CO0
+FS_577_add_4_12/CO0
+FS_577_add_4_2/CO0
+FS_577_add_4_4/CO0
+FS_577_add_4_6/CO0
+FS_577_add_4_18/CO1
+FS_577_add_4_18/CO0
+FS_577_add_4_8/CO0
+FS_577_add_4_10/CO0
+[ END CLIPPED ]
+[ START DESIGN PREFS ]
+SCHEMATIC START ;
+# map:  version Diamond (64-bit) 3.12.0.240.2 -- WARNING: Map write only section -- Mon Aug 16 21:33:30 2021
+
+SYSCONFIG INBUF=ON CONFIG_SECURE=OFF ;
+LOCATE COMP "RD[7]" SITE "71" ;
+LOCATE COMP "RD[6]" SITE "70" ;
+LOCATE COMP "RD[5]" SITE "69" ;
+LOCATE COMP "RD[4]" SITE "68" ;
+LOCATE COMP "RD[3]" SITE "67" ;
+LOCATE COMP "RD[2]" SITE "66" ;
+LOCATE COMP "RD[1]" SITE "65" ;
+LOCATE COMP "RD[0]" SITE "64" ;
+LOCATE COMP "Dout[7]" SITE "3" ;
+LOCATE COMP "Dout[6]" SITE "2" ;
+LOCATE COMP "Dout[5]" SITE "5" ;
+LOCATE COMP "Dout[4]" SITE "4" ;
+LOCATE COMP "Dout[3]" SITE "6" ;
+LOCATE COMP "Dout[2]" SITE "8" ;
+LOCATE COMP "Dout[1]" SITE "7" ;
+LOCATE COMP "Dout[0]" SITE "1" ;
+LOCATE COMP "LED" SITE "57" ;
+LOCATE COMP "RBA[1]" SITE "83" ;
+LOCATE COMP "RBA[0]" SITE "63" ;
+LOCATE COMP "RA[11]" SITE "79" ;
+LOCATE COMP "RA[10]" SITE "87" ;
+LOCATE COMP "RA[9]" SITE "85" ;
+LOCATE COMP "RA[8]" SITE "96" ;
+LOCATE COMP "RA[7]" SITE "100" ;
+LOCATE COMP "RA[6]" SITE "91" ;
+LOCATE COMP "RA[5]" SITE "95" ;
+LOCATE COMP "RA[4]" SITE "99" ;
+LOCATE COMP "RA[3]" SITE "97" ;
+LOCATE COMP "RA[2]" SITE "94" ;
+LOCATE COMP "RA[1]" SITE "89" ;
+LOCATE COMP "RA[0]" SITE "98" ;
+LOCATE COMP "nRCS" SITE "77" ;
+LOCATE COMP "RCKE" SITE "82" ;
+LOCATE COMP "nRWE" SITE "72" ;
+LOCATE COMP "nRRAS" SITE "73" ;
+LOCATE COMP "nRCAS" SITE "78" ;
+LOCATE COMP "RDQMH" SITE "76" ;
+LOCATE COMP "RDQML" SITE "61" ;
+LOCATE COMP "nUFMCS" SITE "53" ;
+LOCATE COMP "UFMCLK" SITE "58" ;
+LOCATE COMP "UFMSDI" SITE "56" ;
+LOCATE COMP "PHI2" SITE "39" ;
+LOCATE COMP "MAin[9]" SITE "51" ;
+LOCATE COMP "MAin[8]" SITE "50" ;
+LOCATE COMP "MAin[7]" SITE "44" ;
+LOCATE COMP "MAin[6]" SITE "49" ;
+LOCATE COMP "MAin[5]" SITE "45" ;
+LOCATE COMP "MAin[4]" SITE "46" ;
+LOCATE COMP "MAin[3]" SITE "47" ;
+LOCATE COMP "MAin[2]" SITE "37" ;
+LOCATE COMP "MAin[1]" SITE "38" ;
+LOCATE COMP "MAin[0]" SITE "23" ;
+LOCATE COMP "CROW[1]" SITE "34" ;
+LOCATE COMP "CROW[0]" SITE "32" ;
+LOCATE COMP "Din[7]" SITE "19" ;
+LOCATE COMP "Din[6]" SITE "20" ;
+LOCATE COMP "Din[5]" SITE "17" ;
+LOCATE COMP "Din[4]" SITE "18" ;
+LOCATE COMP "Din[3]" SITE "16" ;
+LOCATE COMP "Din[2]" SITE "14" ;
+LOCATE COMP "Din[1]" SITE "15" ;
+LOCATE COMP "Din[0]" SITE "21" ;
+LOCATE COMP "nCCAS" SITE "27" ;
+LOCATE COMP "nCRAS" SITE "43" ;
+LOCATE COMP "nFWE" SITE "22" ;
+LOCATE COMP "RCLK" SITE "86" ;
+LOCATE COMP "UFMSDO" SITE "55" ;
+PERIOD NET "PHI2_c" 350.000000 ns  ;
+USE PRIMARY NET "RCLK_c" ;
+PERIOD NET "nCCAS_c" 350.000000 ns  ;
+USE PRIMARY NET "PHI2_c" ;
+PERIOD NET "nCRAS_c" 350.000000 ns  ;
+USE PRIMARY NET "nCCAS_c" ;
+PERIOD NET "RCLK_c" 16.000000 ns  ;
+USE PRIMARY NET "nCRAS_c" ;
+SCHEMATIC END ;
+[ END DESIGN PREFS ]
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.hrr b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.hrr
new file mode 100644
index 0000000..5a900d5
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.hrr
@@ -0,0 +1,10 @@
+---------------------------------------------------
+Report for cell RAM2GS
+   Instance path: RAM2GS
+                     Cell usage:
+                                  cell	      count    Res Usage(%)
+                                  SLIC	      65.00        100.0
+                                  LUT4	     111.00        100.0
+                                 IOBUF	         67        100.0
+                                PFUREG	        102        100.0
+                                RIPPLE	          9        100.0
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.ncd b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.ncd
new file mode 100644
index 0000000000000000000000000000000000000000..f4f2deb380a22c1d20baf60d9a638727b58154a0
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HcmV?d00001

diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mrp.html b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mrp.html
new file mode 100644
index 0000000..cee33ff
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mrp.html
@@ -0,0 +1,425 @@
+
+Project Summary
+
+
+
    
+            Lattice Mapping Report File for Design Module 'RAM2GS'
+
+
+
+Design Information
+
+Command line:   map -a MachXO -p LCMXO640C -t TQFP100 -s 3 -oc Commercial
+     RAM2GS_LCMXO640C_impl1.ngd -o RAM2GS_LCMXO640C_impl1_map.ncd -pr
+     RAM2GS_LCMXO640C_impl1.prf -mp RAM2GS_LCMXO640C_impl1.mrp -lpf C:/Users/Dog
+     /Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.
+     lpf -lpf C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/RAM2GS_L
+     CMXO640C.lpf -c 0 -gui -msgset
+     C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml 
+Target Vendor:  LATTICE
+Target Device:  LCMXO640CTQFP100
+Target Performance:   3
+Mapper:  mj5g00,  version:  Diamond (64-bit) 3.12.0.240.2
+Mapped on:  08/16/21  21:33:30
+
+
+Design Summary
+   Number of PFU registers:   102 out of   640 (16%)
+   Number of SLICEs:        65 out of   320 (20%)
+      SLICEs as Logic/ROM:     65 out of   320 (20%)
+      SLICEs as RAM:            0 out of   192 (0%)
+      SLICEs as Carry:          9 out of   320 (3%)
+   Number of LUT4s:        129 out of   640 (20%)
+      Number used as logic LUTs:        111
+      Number used as distributed RAM:     0
+      Number used as ripple logic:       18
+      Number used as shift registers:     0
+   Number of external PIOs: 67 out of 74 (91%)
+   Number of GSRs:  0 out of 1 (0%)
+   JTAG used :      No
+   Readback used :  No
+   Oscillator used :  No
+   Startup used :   No
+   Number of TSALL: 0 out of 1 (0%)
+   Notes:-
+      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
+     distributed RAMs) + 2*(Number of ripple logic)
+      2. Number of logic LUT4s does not include count of distributed RAM and
+     ripple logic.
+   Number of clocks:  4
+     Net RCLK_c: 39 loads, 39 rising, 0 falling (Driver: PIO RCLK )
+     Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 )
+     Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
+     Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS )
+   Number of Clock Enables:  13
+     Net PHI2_N_114_enable_7: 2 loads, 2 LSLICEs
+     Net RCLK_c_enable_6: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_4: 3 loads, 3 LSLICEs
+     Net RCLK_c_enable_24: 2 loads, 2 LSLICEs
+     Net RCLK_c_enable_3: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_7: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_23: 8 loads, 8 LSLICEs
+     Net PHI2_N_114_enable_1: 1 loads, 1 LSLICEs
+     Net PHI2_N_114_enable_8: 1 loads, 1 LSLICEs
+     Net PHI2_N_114_enable_6: 2 loads, 2 LSLICEs
+     Net PHI2_N_114_enable_2: 1 loads, 1 LSLICEs
+
+     Net RCLK_c_enable_25: 1 loads, 1 LSLICEs
+     Net Ready_N_268: 1 loads, 1 LSLICEs
+   Number of LSRs:  9
+     Net RASr2: 1 loads, 1 LSLICEs
+     Net C1Submitted_N_225: 2 loads, 2 LSLICEs
+     Net n2299: 1 loads, 1 LSLICEs
+     Net nRowColSel_N_35: 1 loads, 1 LSLICEs
+     Net nRowColSel_N_34: 1 loads, 1 LSLICEs
+     Net LEDEN_N_88: 1 loads, 1 LSLICEs
+     Net n2291: 2 loads, 2 LSLICEs
+     Net Ready: 7 loads, 7 LSLICEs
+     Net nRWE_N_173: 1 loads, 1 LSLICEs
+   Number of nets driven by tri-state buffers:  0
+   Top 10 highest fanout non-clock nets:
+     Net Ready: 19 loads
+     Net InitReady: 17 loads
+     Net RASr2: 16 loads
+     Net nRowColSel_N_35: 14 loads
+     Net nRowColSel: 13 loads
+     Net Din_c_6: 9 loads
+     Net MAin_c_1: 9 loads
+     Net Din_c_5: 8 loads
+     Net FS_11: 8 loads
+     Net MAin_c_0: 8 loads
+
+
+
+
+   Number of warnings:  0
+   Number of errors:    0
+     
+
+
+
+
+Design Errors/Warnings
+
+   No errors or warnings present.
+
+
+
+IO (PIO) Attributes
+
++---------------------+-----------+-----------+------------+------------+
+| IO Name             | Direction | Levelmode | IO         | FIXEDDELAY |
+|                     |           |  IO_TYPE  | Register   |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[7]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[6]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[5]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[4]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[3]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[2]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+
+| RD[1]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[0]               | BIDIR     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[7]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[6]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[5]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[4]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[3]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[2]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[1]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[0]             | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| LED                 | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RBA[1]              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RBA[0]              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[11]              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[10]              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[9]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[8]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[7]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[6]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[5]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[4]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[3]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[2]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[1]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[0]               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nRCS                | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RCKE                | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nRWE                | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+
+| nRRAS               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nRCAS               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RDQMH               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RDQML               | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nUFMCS              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| UFMCLK              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| UFMSDI              | OUTPUT    | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| PHI2                | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[9]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[8]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[7]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[6]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[5]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[4]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[3]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[2]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[1]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[0]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| CROW[1]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| CROW[0]             | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[7]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[6]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[5]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[4]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[3]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[2]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[1]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[0]              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+
+| nCCAS               | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nCRAS               | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nFWE                | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RCLK                | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+| UFMSDO              | INPUT     | LVTTL33   |            |            |
++---------------------+-----------+-----------+------------+------------+
+
+
+
+Removed logic
+
+Block i2 undriven or does not drive anything - clipped.
+Block GSR_INST undriven or does not drive anything - clipped.
+Signal PHI2_N_114 was merged into signal PHI2_c
+Signal nCRAS_N_9 was merged into signal nCRAS_c
+Signal nCCAS_N_3 was merged into signal nCCAS_c
+Signal n2302 was merged into signal nRowColSel_N_35
+Signal nRWE_N_172 was merged into signal nRWE_N_173
+Signal n2307 was merged into signal Ready
+Signal RASr2_N_63 was merged into signal RASr2
+Signal n1377 was merged into signal nRowColSel_N_34
+Signal n2306 was merged into signal nFWE_c
+Signal UFMSDO_N_74 was merged into signal UFMSDO_c
+Signal GND_net undriven or does not drive anything - clipped.
+Signal VCC_net undriven or does not drive anything - clipped.
+Signal FS_577_add_4_14/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_16/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_12/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_2/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_4/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_6/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_18/CO1 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_18/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_8/CO0 undriven or does not drive anything - clipped.
+Signal FS_577_add_4_10/CO0 undriven or does not drive anything - clipped.
+Block i1962 was optimized away.
+Block i1961 was optimized away.
+Block i1963 was optimized away.
+Block i1070_1_lut_rep_25 was optimized away.
+Block nRWE_I_49_1_lut was optimized away.
+Block i604_1_lut_rep_30 was optimized away.
+Block RASr2_I_0_1_lut was optimized away.
+Block i1069_1_lut was optimized away.
+Block i1_1_lut_rep_29 was optimized away.
+Block UFMSDO_I_0_1_lut was optimized away.
+Block i1 was optimized away.
+
+
+
+Run Time and Memory Usage
+-------------------------
+
+   Total CPU Time: 0 secs  
+   Total REAL Time: 0 secs  
+   Peak Memory Usage: 30 MB
+
+        
+
+
+
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+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+     Copyright (c) 1995 AT&T Corp.   All rights reserved.
+     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+     Copyright (c) 2001 Agere Systems   All rights reserved.
+     Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights
+     reserved.
+
+
+
+
    
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diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_pad.html b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_pad.html
new file mode 100644
index 0000000..ab78925
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_pad.html
@@ -0,0 +1,418 @@
+
+PAD Specification File
+
+
+
    PAD Specification File
+***************************
+
+PART TYPE:        LCMXO640C
+Performance Grade:      3
+PACKAGE:          TQFP100
+Package Status:                     Final          Version 1.17
+
+Mon Aug 16 21:33:36 2021
+
+Pinout by Port Name:
++-----------+----------+--------------+-------+----------------------------------+
+| Port Name | Pin/Bank | Buffer Type  | Site  | Properties                       |
++-----------+----------+--------------+-------+----------------------------------+
+| CROW[0]   | 32/2     | LVTTL33_IN   | PB4C  | SLEW:FAST                        |
+| CROW[1]   | 34/2     | LVTTL33_IN   | PB4E  | SLEW:FAST                        |
+| Din[0]    | 21/3     | LVTTL33_IN   | PL10C | SLEW:FAST                        |
+| Din[1]    | 15/3     | LVTTL33_IN   | PL7B  | SLEW:FAST                        |
+| Din[2]    | 14/3     | LVTTL33_IN   | PL5B  | SLEW:FAST                        |
+| Din[3]    | 16/3     | LVTTL33_IN   | PL8C  | SLEW:FAST                        |
+| Din[4]    | 18/3     | LVTTL33_IN   | PL9A  | SLEW:FAST                        |
+| Din[5]    | 17/3     | LVTTL33_IN   | PL8D  | SLEW:FAST                        |
+| Din[6]    | 20/3     | LVTTL33_IN   | PL10A | SLEW:FAST                        |
+| Din[7]    | 19/3     | LVTTL33_IN   | PL9C  | SLEW:FAST                        |
+| Dout[0]   | 1/3      | LVTTL33_OUT  | PL2A  | DRIVE:4mA SLEW:SLOW              |
+| Dout[1]   | 7/3      | LVTTL33_OUT  | PL3C  | DRIVE:4mA SLEW:SLOW              |
+| Dout[2]   | 8/3      | LVTTL33_OUT  | PL3D  | DRIVE:4mA SLEW:SLOW              |
+| Dout[3]   | 6/3      | LVTTL33_OUT  | PL3B  | DRIVE:4mA SLEW:SLOW              |
+| Dout[4]   | 4/3      | LVTTL33_OUT  | PL2D  | DRIVE:4mA SLEW:SLOW              |
+| Dout[5]   | 5/3      | LVTTL33_OUT  | PL3A  | DRIVE:4mA SLEW:SLOW              |
+| Dout[6]   | 2/3      | LVTTL33_OUT  | PL2C  | DRIVE:4mA SLEW:SLOW              |
+| Dout[7]   | 3/3      | LVTTL33_OUT  | PL2B  | DRIVE:4mA SLEW:SLOW              |
+| LED       | 57/1     | LVTTL33_OUT  | PR10B | DRIVE:16mA SLEW:SLOW             |
+| MAin[0]   | 23/3     | LVTTL33_IN   | PL11C | SLEW:FAST                        |
+| MAin[1]   | 38/2     | LVTTL33_IN   | PB6B  | SLEW:FAST                        |
+| MAin[2]   | 37/2     | LVTTL33_IN   | PB5D  | SLEW:FAST                        |
+| MAin[3]   | 47/2     | LVTTL33_IN   | PB9C  | SLEW:FAST                        |
+| MAin[4]   | 46/2     | LVTTL33_IN   | PB9A  | SLEW:FAST                        |
+| MAin[5]   | 45/2     | LVTTL33_IN   | PB8D  | SLEW:FAST                        |
+| MAin[6]   | 49/2     | LVTTL33_IN   | PB9D  | SLEW:FAST                        |
+| MAin[7]   | 44/2     | LVTTL33_IN   | PB8C  | SLEW:FAST                        |
+| MAin[8]   | 50/2     | LVTTL33_IN   | PB9F  | SLEW:FAST                        |
+| MAin[9]   | 51/1     | LVTTL33_IN   | PR11D | SLEW:FAST                        |
+| PHI2      | 39/2     | LVTTL33_IN   | PB6C  | SLEW:FAST                        |
+| RA[0]     | 98/0     | LVTTL33_OUT  | PT2B  | DRIVE:4mA SLEW:SLOW              |
+| RA[10]    | 87/0     | LVTTL33_OUT  | PT5A  | DRIVE:4mA SLEW:SLOW              |
+| RA[11]    | 79/0     | LVTTL33_OUT  | PT9A  | DRIVE:4mA SLEW:SLOW              |
+| RA[1]     | 89/0     | LVTTL33_OUT  | PT4F  | DRIVE:4mA SLEW:SLOW              |
+| RA[2]     | 94/0     | LVTTL33_OUT  | PT3B  | DRIVE:4mA SLEW:SLOW              |
+| RA[3]     | 97/0     | LVTTL33_OUT  | PT2E  | DRIVE:4mA SLEW:SLOW              |
+| RA[4]     | 99/0     | LVTTL33_OUT  | PT2C  | DRIVE:4mA SLEW:SLOW              |
+| RA[5]     | 95/0     | LVTTL33_OUT  | PT3A  | DRIVE:4mA SLEW:SLOW              |
+| RA[6]     | 91/0     | LVTTL33_OUT  | PT3F  | DRIVE:4mA SLEW:SLOW              |
+| RA[7]     | 100/0    | LVTTL33_OUT  | PT2A  | DRIVE:4mA SLEW:SLOW              |
+| RA[8]     | 96/0     | LVTTL33_OUT  | PT2F  | DRIVE:4mA SLEW:SLOW              |
+| RA[9]     | 85/0     | LVTTL33_OUT  | PT6B  | DRIVE:4mA SLEW:SLOW              |
+| RBA[0]    | 63/1     | LVTTL33_OUT  | PR7B  | DRIVE:4mA SLEW:SLOW              |
+| RBA[1]    | 83/0     | LVTTL33_OUT  | PT7A  | DRIVE:4mA SLEW:SLOW              |
+| RCKE      | 82/0     | LVTTL33_OUT  | PT7E  | DRIVE:4mA SLEW:SLOW              |
+| RCLK      | 86/0     | LVTTL33_IN   | PT5B  | SLEW:FAST                        |
+| RDQMH     | 76/0     | LVTTL33_OUT  | PT9F  | DRIVE:4mA SLEW:SLOW              |
+| RDQML     | 61/1     | LVTTL33_OUT  | PR9B  | DRIVE:4mA SLEW:SLOW              |
+| RD[0]     | 64/1     | LVTTL33_BIDI | PR6C  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[1]     | 65/1     | LVTTL33_BIDI | PR6B  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[2]     | 66/1     | LVTTL33_BIDI | PR5D  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[3]     | 67/1     | LVTTL33_BIDI | PR5B  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[4]     | 68/1     | LVTTL33_BIDI | PR4D  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[5]     | 69/1     | LVTTL33_BIDI | PR4B  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[6]     | 70/1     | LVTTL33_BIDI | PR3D  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| RD[7]     | 71/1     | LVTTL33_BIDI | PR3B  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
+| UFMCLK    | 58/1     | LVTTL33_OUT  | PR10A | DRIVE:4mA SLEW:SLOW              |
+| UFMSDI    | 56/1     | LVTTL33_OUT  | PR10C | DRIVE:4mA SLEW:SLOW              |
+| UFMSDO    | 55/1     | LVTTL33_IN   | PR10D | SLEW:FAST PULL:KEEPER            |
+| nCCAS     | 27/2     | LVTTL33_IN   | PB2C  | SLEW:FAST                        |
+| nCRAS     | 43/2     | LVTTL33_IN   | PB8B  | SLEW:FAST                        |
+| nFWE      | 22/3     | LVTTL33_IN   | PL11A | SLEW:FAST                        |
+| nRCAS     | 78/0     | LVTTL33_OUT  | PT9C  | DRIVE:4mA SLEW:SLOW              |
+| nRCS      | 77/0     | LVTTL33_OUT  | PT9E  | DRIVE:4mA SLEW:SLOW              |
+| nRRAS     | 73/1     | LVTTL33_OUT  | PR2B  | DRIVE:4mA SLEW:SLOW              |
+| nRWE      | 72/1     | LVTTL33_OUT  | PR2D  | DRIVE:4mA SLEW:SLOW              |
+| nUFMCS    | 53/1     | LVTTL33_OUT  | PR11C | DRIVE:4mA SLEW:SLOW              |
++-----------+----------+--------------+-------+----------------------------------+
+
+Vccio by Bank:
++------+-------+
+| Bank | Vccio |
++------+-------+
+| 0    | 3.3V  |
+| 1    | 3.3V  |
+| 2    |       |
+| 3    | 3.3V  |
++------+-------+
+
+
+Vref by Bank:
++------+-----+-----------------+---------+
+| Vref | Pin | Bank # / Vref # | Load(s) |
++------+-----+-----------------+---------+
++------+-----+-----------------+---------+
+
+Pinout by Pin Number:
++----------+---------------------+------------+--------------+-------+---------------+
+| Pin/Bank | Pin Info            | Preference | Buffer Type  | Site  | Dual Function |
++----------+---------------------+------------+--------------+-------+---------------+
+| 1/3      | Dout[0]             | LOCATED    | LVTTL33_OUT  | PL2A  |               |
+| 2/3      | Dout[6]             | LOCATED    | LVTTL33_OUT  | PL2C  |               |
+| 3/3      | Dout[7]             | LOCATED    | LVTTL33_OUT  | PL2B  |               |
+| 4/3      | Dout[4]             | LOCATED    | LVTTL33_OUT  | PL2D  |               |
+| 5/3      | Dout[5]             | LOCATED    | LVTTL33_OUT  | PL3A  |               |
+| 6/3      | Dout[3]             | LOCATED    | LVTTL33_OUT  | PL3B  |               |
+| 7/3      | Dout[1]             | LOCATED    | LVTTL33_OUT  | PL3C  |               |
+| 8/3      | Dout[2]             | LOCATED    | LVTTL33_OUT  | PL3D  |               |
+| 9/3      |     unused, PULL:UP |            |              | PL4A  |               |
+| 11/3     |     unused, PULL:UP |            |              | PL4C  |               |
+| 13/3     |     unused, PULL:UP |            |              | PL4D  |               |
+| 14/3     | Din[2]              | LOCATED    | LVTTL33_IN   | PL5B  | GSR_PADN      |
+| 15/3     | Din[1]              | LOCATED    | LVTTL33_IN   | PL7B  |               |
+| 16/3     | Din[3]              | LOCATED    | LVTTL33_IN   | PL8C  | TSALLPAD      |
+| 17/3     | Din[5]              | LOCATED    | LVTTL33_IN   | PL8D  |               |
+| 18/3     | Din[4]              | LOCATED    | LVTTL33_IN   | PL9A  |               |
+| 19/3     | Din[7]              | LOCATED    | LVTTL33_IN   | PL9C  |               |
+| 20/3     | Din[6]              | LOCATED    | LVTTL33_IN   | PL10A |               |
+| 21/3     | Din[0]              | LOCATED    | LVTTL33_IN   | PL10C |               |
+| 22/3     | nFWE                | LOCATED    | LVTTL33_IN   | PL11A |               |
+| 23/3     | MAin[0]             | LOCATED    | LVTTL33_IN   | PL11C |               |
+| 27/2     | nCCAS               | LOCATED    | LVTTL33_IN   | PB2C  |               |
+| 32/2     | CROW[0]             | LOCATED    | LVTTL33_IN   | PB4C  |               |
+| 34/2     | CROW[1]             | LOCATED    | LVTTL33_IN   | PB4E  |               |
+| 36/2     |     unused, PULL:UP |            |              | PB5B  | PCLKT2_1      |
+| 37/2     | MAin[2]             | LOCATED    | LVTTL33_IN   | PB5D  |               |
+| 38/2     | MAin[1]             | LOCATED    | LVTTL33_IN   | PB6B  | PCLKT2_0      |
+| 39/2     | PHI2                | LOCATED    | LVTTL33_IN   | PB6C  |               |
+| 43/2     | nCRAS               | LOCATED    | LVTTL33_IN   | PB8B  |               |
+| 44/2     | MAin[7]             | LOCATED    | LVTTL33_IN   | PB8C  |               |
+| 45/2     | MAin[5]             | LOCATED    | LVTTL33_IN   | PB8D  |               |
+| 46/2     | MAin[4]             | LOCATED    | LVTTL33_IN   | PB9A  |               |
+| 47/2     | MAin[3]             | LOCATED    | LVTTL33_IN   | PB9C  |               |
+| 49/2     | MAin[6]             | LOCATED    | LVTTL33_IN   | PB9D  |               |
+| 50/2     | MAin[8]             | LOCATED    | LVTTL33_IN   | PB9F  |               |
+| 51/1     | MAin[9]             | LOCATED    | LVTTL33_IN   | PR11D |               |
+| 52/1     |     unused, PULL:UP |            |              | PR11B |               |
+| 53/1     | nUFMCS              | LOCATED    | LVTTL33_OUT  | PR11C |               |
+| 54/1     |     unused, PULL:UP |            |              | PR11A |               |
+| 55/1     | UFMSDO              | LOCATED    | LVTTL33_IN   | PR10D |               |
+| 56/1     | UFMSDI              | LOCATED    | LVTTL33_OUT  | PR10C |               |
+| 57/1     | LED                 | LOCATED    | LVTTL33_OUT  | PR10B |               |
+| 58/1     | UFMCLK              | LOCATED    | LVTTL33_OUT  | PR10A |               |
+| 59/1     |     unused, PULL:UP |            |              | PR9D  |               |
+| 61/1     | RDQML               | LOCATED    | LVTTL33_OUT  | PR9B  |               |
+| 63/1     | RBA[0]              | LOCATED    | LVTTL33_OUT  | PR7B  |               |
+| 64/1     | RD[0]               | LOCATED    | LVTTL33_BIDI | PR6C  |               |
+| 65/1     | RD[1]               | LOCATED    | LVTTL33_BIDI | PR6B  |               |
+| 66/1     | RD[2]               | LOCATED    | LVTTL33_BIDI | PR5D  |               |
+| 67/1     | RD[3]               | LOCATED    | LVTTL33_BIDI | PR5B  |               |
+| 68/1     | RD[4]               | LOCATED    | LVTTL33_BIDI | PR4D  |               |
+| 69/1     | RD[5]               | LOCATED    | LVTTL33_BIDI | PR4B  |               |
+| 70/1     | RD[6]               | LOCATED    | LVTTL33_BIDI | PR3D  |               |
+| 71/1     | RD[7]               | LOCATED    | LVTTL33_BIDI | PR3B  |               |
+| 72/1     | nRWE                | LOCATED    | LVTTL33_OUT  | PR2D  |               |
+| 73/1     | nRRAS               | LOCATED    | LVTTL33_OUT  | PR2B  |               |
+| 76/0     | RDQMH               | LOCATED    | LVTTL33_OUT  | PT9F  |               |
+| 77/0     | nRCS                | LOCATED    | LVTTL33_OUT  | PT9E  |               |
+| 78/0     | nRCAS               | LOCATED    | LVTTL33_OUT  | PT9C  |               |
+| 79/0     | RA[11]              | LOCATED    | LVTTL33_OUT  | PT9A  |               |
+| 82/0     | RCKE                | LOCATED    | LVTTL33_OUT  | PT7E  | D7            |
+| 83/0     | RBA[1]              | LOCATED    | LVTTL33_OUT  | PT7A  | D6            |
+| 85/0     | RA[9]               | LOCATED    | LVTTL33_OUT  | PT6B  | PCLKT0_1      |
+| 86/0     | RCLK                | LOCATED    | LVTTL33_IN   | PT5B  | PCLKT0_0      |
+| 87/0     | RA[10]              | LOCATED    | LVTTL33_OUT  | PT5A  |               |
+| 89/0     | RA[1]               | LOCATED    | LVTTL33_OUT  | PT4F  |               |
+| 91/0     | RA[6]               | LOCATED    | LVTTL33_OUT  | PT3F  | D3            |
+| 94/0     | RA[2]               | LOCATED    | LVTTL33_OUT  | PT3B  |               |
+| 95/0     | RA[5]               | LOCATED    | LVTTL33_OUT  | PT3A  |               |
+| 96/0     | RA[8]               | LOCATED    | LVTTL33_OUT  | PT2F  | D2            |
+| 97/0     | RA[3]               | LOCATED    | LVTTL33_OUT  | PT2E  |               |
+| 98/0     | RA[0]               | LOCATED    | LVTTL33_OUT  | PT2B  | D1            |
+| 99/0     | RA[4]               | LOCATED    | LVTTL33_OUT  | PT2C  |               |
+| 100/0    | RA[7]               | LOCATED    | LVTTL33_OUT  | PT2A  |               |
+| PB2A/2   |     unused, PULL:UP |            |              | PB2A  |               |
+| PB2B/2   |     unused, PULL:UP |            |              | PB2B  |               |
+| PB2D/2   |     unused, PULL:UP |            |              | PB2D  |               |
+| PB3A/2   |     unused, PULL:UP |            |              | PB3A  |               |
+| PB3B/2   |     unused, PULL:UP |            |              | PB3B  |               |
+| PB3C/2   |     unused, PULL:UP |            |              | PB3C  |               |
+| PB3D/2   |     unused, PULL:UP |            |              | PB3D  |               |
+| PB4A/2   |     unused, PULL:UP |            |              | PB4A  |               |
+| PB4B/2   |     unused, PULL:UP |            |              | PB4B  |               |
+| PB4D/2   |     unused, PULL:UP |            |              | PB4D  |               |
+| PB4F/2   |     unused, PULL:UP |            |              | PB4F  |               |
+| PB5A/2   |     unused, PULL:UP |            |              | PB5A  |               |
+| PB5C/2   |     unused, PULL:UP |            |              | PB5C  |               |
+| PB6A/2   |     unused, PULL:UP |            |              | PB6A  |               |
+| PB6D/2   |     unused, PULL:UP |            |              | PB6D  |               |
+| PB7A/2   |     unused, PULL:UP |            |              | PB7A  |               |
+| PB7B/2   |     unused, PULL:UP |            |              | PB7B  |               |
+| PB7C/2   |     unused, PULL:UP |            |              | PB7C  |               |
+| PB7D/2   |     unused, PULL:UP |            |              | PB7D  |               |
+| PB7E/2   |     unused, PULL:UP |            |              | PB7E  |               |
+| PB7F/2   |     unused, PULL:UP |            |              | PB7F  |               |
+| PB8A/2   |     unused, PULL:UP |            |              | PB8A  |               |
+| PB9B/2   |     unused, PULL:UP |            |              | PB9B  |               |
+| PB9E/0   |     unused, PULL:UP |            |              | PB9E  |               |
+| PL4B/3   |     unused, PULL:UP |            |              | PL4B  |               |
+| PL5A/3   |     unused, PULL:UP |            |              | PL5A  |               |
+| PL5C/3   |     unused, PULL:UP |            |              | PL5C  |               |
+| PL5D/3   |     unused, PULL:UP |            |              | PL5D  |               |
+| PL6A/3   |     unused, PULL:UP |            |              | PL6A  |               |
+| PL6B/3   |     unused, PULL:UP |            |              | PL6B  |               |
+| PL6C/3   |     unused, PULL:UP |            |              | PL6C  |               |
+| PL6D/3   |     unused, PULL:UP |            |              | PL6D  |               |
+| PL7A/3   |     unused, PULL:UP |            |              | PL7A  |               |
+| PL7C/3   |     unused, PULL:UP |            |              | PL7C  |               |
+| PL7D/3   |     unused, PULL:UP |            |              | PL7D  |               |
+| PL8A/3   |     unused, PULL:UP |            |              | PL8A  |               |
+| PL8B/3   |     unused, PULL:UP |            |              | PL8B  |               |
+| PL9B/3   |     unused, PULL:UP |            |              | PL9B  |               |
+| PL9D/3   |     unused, PULL:UP |            |              | PL9D  |               |
+| PL10B/3  |     unused, PULL:UP |            |              | PL10B |               |
+| PL10D/3  |     unused, PULL:UP |            |              | PL10D |               |
+| PL11B/3  |     unused, PULL:UP |            |              | PL11B |               |
+| PL11D/3  |     unused, PULL:UP |            |              | PL11D |               |
+| PR2A/1   |     unused, PULL:UP |            |              | PR2A  |               |
+| PR2C/1   |     unused, PULL:UP |            |              | PR2C  |               |
+| PR3A/1   |     unused, PULL:UP |            |              | PR3A  |               |
+| PR3C/1   |     unused, PULL:UP |            |              | PR3C  |               |
+| PR4A/1   |     unused, PULL:UP |            |              | PR4A  |               |
+| PR4C/1   |     unused, PULL:UP |            |              | PR4C  |               |
+| PR5A/1   |     unused, PULL:UP |            |              | PR5A  |               |
+| PR5C/1   |     unused, PULL:UP |            |              | PR5C  |               |
+| PR6A/1   |     unused, PULL:UP |            |              | PR6A  |               |
+| PR6D/1   |     unused, PULL:UP |            |              | PR6D  |               |
+| PR7A/1   |     unused, PULL:UP |            |              | PR7A  |               |
+| PR7C/1   |     unused, PULL:UP |            |              | PR7C  |               |
+| PR7D/1   |     unused, PULL:UP |            |              | PR7D  |               |
+| PR8A/1   |     unused, PULL:UP |            |              | PR8A  |               |
+| PR8B/1   |     unused, PULL:UP |            |              | PR8B  |               |
+| PR8C/1   |     unused, PULL:UP |            |              | PR8C  |               |
+| PR8D/1   |     unused, PULL:UP |            |              | PR8D  |               |
+| PR9A/1   |     unused, PULL:UP |            |              | PR9A  |               |
+| PR9C/1   |     unused, PULL:UP |            |              | PR9C  |               |
+| PT2D/0   |     unused, PULL:UP |            |              | PT2D  |               |
+| PT3C/0   |     unused, PULL:UP |            |              | PT3C  |               |
+| PT3D/0   |     unused, PULL:UP |            |              | PT3D  |               |
+| PT3E/0   |     unused, PULL:UP |            |              | PT3E  |               |
+| PT4A/0   |     unused, PULL:UP |            |              | PT4A  |               |
+| PT4B/0   |     unused, PULL:UP |            |              | PT4B  |               |
+| PT4C/0   |     unused, PULL:UP |            |              | PT4C  |               |
+| PT4D/0   |     unused, PULL:UP |            |              | PT4D  |               |
+| PT4E/0   |     unused, PULL:UP |            |              | PT4E  |               |
+| PT5C/0   |     unused, PULL:UP |            |              | PT5C  |               |
+| PT5D/0   |     unused, PULL:UP |            |              | PT5D  |               |
+| PT6A/0   |     unused, PULL:UP |            |              | PT6A  |               |
+| PT6C/0   |     unused, PULL:UP |            |              | PT6C  |               |
+| PT6D/0   |     unused, PULL:UP |            |              | PT6D  |               |
+| PT7B/0   |     unused, PULL:UP |            |              | PT7B  |               |
+| PT7C/0   |     unused, PULL:UP |            |              | PT7C  |               |
+| PT7D/0   |     unused, PULL:UP |            |              | PT7D  |               |
+| PT7F/0   |     unused, PULL:UP |            |              | PT7F  |               |
+| PT8A/0   |     unused, PULL:UP |            |              | PT8A  |               |
+| PT8B/0   |     unused, PULL:UP |            |              | PT8B  |               |
+| PT8C/0   |     unused, PULL:UP |            |              | PT8C  |               |
+| PT8D/0   |     unused, PULL:UP |            |              | PT8D  |               |
+| PT9B/0   |     unused, PULL:UP |            |              | PT9B  |               |
+| PT9D/0   |     unused, PULL:UP |            |              | PT9D  |               |
+| TCK/2    |                     |            |              | TCK   | TCK           |
+| TDI/2    |                     |            |              | TDI   | TDID0         |
+| TDO/2    |                     |            |              | TDO   | TDO           |
+| TMS/2    |                     |            |              | TMS   | TMS           |
++----------+---------------------+------------+--------------+-------+---------------+
+
+
+List of All Pins' Locate Preferences Based on Final Placement After PAR 
+to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
+
+LOCATE  COMP  "CROW[0]"  SITE  "32";
+LOCATE  COMP  "CROW[1]"  SITE  "34";
+LOCATE  COMP  "Din[0]"  SITE  "21";
+LOCATE  COMP  "Din[1]"  SITE  "15";
+LOCATE  COMP  "Din[2]"  SITE  "14";
+LOCATE  COMP  "Din[3]"  SITE  "16";
+LOCATE  COMP  "Din[4]"  SITE  "18";
+LOCATE  COMP  "Din[5]"  SITE  "17";
+LOCATE  COMP  "Din[6]"  SITE  "20";
+LOCATE  COMP  "Din[7]"  SITE  "19";
+LOCATE  COMP  "Dout[0]"  SITE  "1";
+LOCATE  COMP  "Dout[1]"  SITE  "7";
+LOCATE  COMP  "Dout[2]"  SITE  "8";
+LOCATE  COMP  "Dout[3]"  SITE  "6";
+LOCATE  COMP  "Dout[4]"  SITE  "4";
+LOCATE  COMP  "Dout[5]"  SITE  "5";
+LOCATE  COMP  "Dout[6]"  SITE  "2";
+LOCATE  COMP  "Dout[7]"  SITE  "3";
+LOCATE  COMP  "LED"  SITE  "57";
+LOCATE  COMP  "MAin[0]"  SITE  "23";
+LOCATE  COMP  "MAin[1]"  SITE  "38";
+LOCATE  COMP  "MAin[2]"  SITE  "37";
+LOCATE  COMP  "MAin[3]"  SITE  "47";
+LOCATE  COMP  "MAin[4]"  SITE  "46";
+LOCATE  COMP  "MAin[5]"  SITE  "45";
+LOCATE  COMP  "MAin[6]"  SITE  "49";
+LOCATE  COMP  "MAin[7]"  SITE  "44";
+LOCATE  COMP  "MAin[8]"  SITE  "50";
+LOCATE  COMP  "MAin[9]"  SITE  "51";
+LOCATE  COMP  "PHI2"  SITE  "39";
+LOCATE  COMP  "RA[0]"  SITE  "98";
+LOCATE  COMP  "RA[10]"  SITE  "87";
+LOCATE  COMP  "RA[11]"  SITE  "79";
+LOCATE  COMP  "RA[1]"  SITE  "89";
+LOCATE  COMP  "RA[2]"  SITE  "94";
+LOCATE  COMP  "RA[3]"  SITE  "97";
+LOCATE  COMP  "RA[4]"  SITE  "99";
+LOCATE  COMP  "RA[5]"  SITE  "95";
+LOCATE  COMP  "RA[6]"  SITE  "91";
+LOCATE  COMP  "RA[7]"  SITE  "100";
+LOCATE  COMP  "RA[8]"  SITE  "96";
+LOCATE  COMP  "RA[9]"  SITE  "85";
+LOCATE  COMP  "RBA[0]"  SITE  "63";
+LOCATE  COMP  "RBA[1]"  SITE  "83";
+LOCATE  COMP  "RCKE"  SITE  "82";
+LOCATE  COMP  "RCLK"  SITE  "86";
+LOCATE  COMP  "RDQMH"  SITE  "76";
+LOCATE  COMP  "RDQML"  SITE  "61";
+LOCATE  COMP  "RD[0]"  SITE  "64";
+LOCATE  COMP  "RD[1]"  SITE  "65";
+LOCATE  COMP  "RD[2]"  SITE  "66";
+LOCATE  COMP  "RD[3]"  SITE  "67";
+LOCATE  COMP  "RD[4]"  SITE  "68";
+LOCATE  COMP  "RD[5]"  SITE  "69";
+LOCATE  COMP  "RD[6]"  SITE  "70";
+LOCATE  COMP  "RD[7]"  SITE  "71";
+LOCATE  COMP  "UFMCLK"  SITE  "58";
+LOCATE  COMP  "UFMSDI"  SITE  "56";
+LOCATE  COMP  "UFMSDO"  SITE  "55";
+LOCATE  COMP  "nCCAS"  SITE  "27";
+LOCATE  COMP  "nCRAS"  SITE  "43";
+LOCATE  COMP  "nFWE"  SITE  "22";
+LOCATE  COMP  "nRCAS"  SITE  "78";
+LOCATE  COMP  "nRCS"  SITE  "77";
+LOCATE  COMP  "nRRAS"  SITE  "73";
+LOCATE  COMP  "nRWE"  SITE  "72";
+LOCATE  COMP  "nUFMCS"  SITE  "53";
+
+
+
+
+
+PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Mon Aug 16 21:33:36 2021
+
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
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+
+
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_par.html b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_par.html
new file mode 100644
index 0000000..ec4ec76
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_par.html
@@ -0,0 +1,315 @@
+
+Place & Route Report
+
+
+
    PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Mon Aug 16 21:33:31 2021
+
+C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO640C_impl1.p2t
+RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir
+RAM2GS_LCMXO640C_impl1.prf -gui -msgset
+C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml
+
+
+Preference file: RAM2GS_LCMXO640C_impl1.prf.
+
+Cost Table Summary
+Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
+Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
+----------   --------     -----        ------       -----------  -----------  ----         ------
+5_1   *      0            1.213        0            0.339        0            06           Completed
+* : Design saved.
+
+Total (real) run time for 1-seed: 6 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Lattice Place and Route Report for Design "RAM2GS_LCMXO640C_impl1_map.ncd"
+Mon Aug 16 21:33:31 2021
+
+
+Best Par Run
+PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir/5_1.ncd RAM2GS_LCMXO640C_impl1.prf
+Preference file: RAM2GS_LCMXO640C_impl1.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file RAM2GS_LCMXO640C_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 3
+Loading device for application par from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+
+Device utilization summary:
+
+   PIO (prelim)      67/159          42% used
+                     67/74           90% bonded
+   SLICE             65/320          20% used
+
+
+
+Number of Signals: 252
+Number of Connections: 618
+
+Pin Constraint Summary:
+   67 out of 67 pins locked (100% locked).
+
+The following 4 signals are selected to use the primary clock routing resources:
+    RCLK_c (driver: RCLK, clk load #: 39)
+    PHI2_c (driver: PHI2, clk load #: 13)
+    nCCAS_c (driver: nCCAS, clk load #: 4)
+    nCRAS_c (driver: nCRAS, clk load #: 7)
+
+No signal is selected as secondary clock.
+
+No signal is selected as Global Set/Reset.
+Starting Placer Phase 0.
+.......
+Finished Placer Phase 0.  REAL time: 0 secs 
+
+Starting Placer Phase 1.
+...............
+Placer score = 1105164.
+Finished Placer Phase 1.  REAL time: 5 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  1103986
+Finished Placer Phase 2.  REAL time: 5 secs 
+
+
+
+Clock Report
+
+Global Clock Resources:
+  CLK_PIN    : 1 out of 4 (25%)
+  General PIO: 3 out of 160 (1%)
+
+Global Clocks:
+  PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT5B)", clk load = 39
+  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB6C)", clk load = 13
+  PRIMARY "nCCAS_c" from comp "nCCAS" on PIO site "27 (PB2C)", clk load = 4
+  PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB8B)", clk load = 7
+
+  PRIMARY  : 4 out of 4 (100%)
+  SECONDARY: 0 out of 4 (0%)
+
+
+
+
+I/O Usage Summary (final):
+   67 out of 159 (42.1%) PIO sites used.
+   67 out of 74 (90.5%) bonded PIO sites used.
+   Number of PIO comps: 67; differential: 0.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+----------------+------------+------------+------------+
+| I/O Bank | Usage          | Bank Vccio | Bank Vref1 | Bank Vref2 |
++----------+----------------+------------+------------+------------+
+| 0        | 18 / 18 (100%) | 3.3V       | -          | -          |
+| 1        | 18 / 21 ( 85%) | 3.3V       | -          | -          |
+| 2        | 13 / 14 ( 92%) | -          | -          | -          |
+| 3        | 18 / 21 ( 85%) | 3.3V       | -          | -          |
++----------+----------------+------------+------------+------------+
+
+Total placer CPU time: 5 secs 
+
+Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd.
+
+0 connections routed; 618 unrouted.
+Starting router resource preassignment
+WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks.  This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
+WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the PIO sites dedicated for primary clocks.  This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
+WARNING - par: The driver of primary clock net nCCAS_c is not placed on one of the PIO sites dedicated for primary clocks.  This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
+
+Completed router resource preassignment. Real time: 5 secs 
+
+Start NBR router at 21:33:36 08/16/21
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at 21:33:36 08/16/21
+
+Start NBR section for initial routing at 21:33:36 08/16/21
+Level 1, iteration 1
+0(0.00%) conflict; 535(86.57%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.302ns/0.000ns; real time: 5 secs 
+Level 2, iteration 1
+0(0.00%) conflict; 523(84.63%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.256ns/0.000ns; real time: 5 secs 
+Level 3, iteration 1
+0(0.00%) conflict; 511(82.69%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.228ns/0.000ns; real time: 5 secs 
+Level 4, iteration 1
+16(0.06%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.213ns/0.000ns; real time: 6 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 21:33:37 08/16/21
+Level 1, iteration 1
+0(0.00%) conflict; 16(2.59%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.213ns/0.000ns; real time: 6 secs 
+Level 2, iteration 1
+0(0.00%) conflict; 16(2.59%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.213ns/0.000ns; real time: 6 secs 
+Level 3, iteration 1
+0(0.00%) conflict; 16(2.59%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.213ns/0.000ns; real time: 6 secs 
+Level 4, iteration 1
+5(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.213ns/0.000ns; real time: 6 secs 
+Level 4, iteration 2
+2(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.213ns/0.000ns; real time: 6 secs 
+Level 4, iteration 3
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.213ns/0.000ns; real time: 6 secs 
+
+Start NBR section for setup/hold timing optimization with effort level 3 at 21:33:37 08/16/21
+
+Start NBR section for re-routing at 21:33:37 08/16/21
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.213ns/0.000ns; real time: 6 secs 
+
+Start NBR section for post-routing at 21:33:37 08/16/21
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 0 (0.00%)
+  Estimated worst slack<setup> : 1.213ns
+  Timing score<setup> : 0
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+Total CPU time 6 secs 
+Total REAL time: 6 secs 
+Completely routed.
+End of route.  618 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 0 
+
+Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = Completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack<setup/<ns>> = 1.213
+PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
+PAR_SUMMARY::Worst  slack<hold /<ns>> = 0.339
+PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 6 secs 
+Total REAL time to completion: 6 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
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diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_summary.html b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_summary.html
new file mode 100644
index 0000000..07ed1c1
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_summary.html
@@ -0,0 +1,83 @@
+
+Project Summary
+
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    RAM2GS_LCMXO640C project summary
    Module Name:RAM2GS_LCMXO640CSynthesis:Lattice LSE
    Implementation Name:impl1Strategy Name:Strategy1
    Last Process:JEDEC FileState:Passed
    Target Device:LCMXO640C-3T100CDevice Family:MachXO
    Device Type:LCMXO640CPackage Type:TQFP100
    Performance grade:3Operating conditions:COM
    Logic preference file:RAM2GS_LCMXO640C.lpf
    Physical Preference file:impl1/RAM2GS_LCMXO640C_impl1.prf
    Product Version:3.12.0.240.2Patch Version:
    Updated:2021/08/16 21:36:37
    Implementation Location:C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/impl1
    Project File:C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C.ldf
    
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diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_tw1.html b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_tw1.html
new file mode 100644
index 0000000..bdf2b16
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_tw1.html
@@ -0,0 +1,2740 @@
+
+Lattice Map TRACE Report
+
+
+
    Map TRACE Report
+
+Loading design for application trce from file ram2gs_lcmxo640c_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 3
+Loading device for application trce from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
+Mon Aug 16 21:33:31 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO640C_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.prf 
+Design file:     ram2gs_lcmxo640c_impl1_map.ncd
+Preference file: ram2gs_lcmxo640c_impl1.prf
+Device,speed:    LCMXO640C,3
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • PERIOD NET "PHI2_c" 350.000000 ns  (0 errors)
    •             113 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCCAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCRAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "RCLK_c" 16.000000 ns  (0 errors)
    •             395 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            113 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 161.862ns (weighted slack = 323.724ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdSubmitted_384  (to PHI2_c -)
+
+   Delay:              12.873ns  (21.6% logic, 78.4% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.873ns physical path delay SLICE_95 to SLICE_19 meets
+    175.000ns delay constraint less
+      0.265ns CE_SET requirement (totaling 174.735ns) by 161.862ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_95.CLK to    SLICE_95.Q1 SLICE_95 (from PHI2_c)
+ROUTE         1   e 1.441    SLICE_95.Q1 to    SLICE_67.A1 Bank_7
+CTOF_DEL    ---     0.371    SLICE_67.A1 to    SLICE_67.F1 SLICE_67
+ROUTE         1   e 1.441    SLICE_67.F1 to    SLICE_82.C1 n2154
+CTOF_DEL    ---     0.371    SLICE_82.C1 to    SLICE_82.F1 SLICE_82
+ROUTE         1   e 1.441    SLICE_82.F1 to    SLICE_76.B1 n26
+CTOF_DEL    ---     0.371    SLICE_76.B1 to    SLICE_76.F1 SLICE_76
+ROUTE         4   e 1.441    SLICE_76.F1 to    SLICE_89.B0 n1285
+CTOF_DEL    ---     0.371    SLICE_89.B0 to    SLICE_89.F0 SLICE_89
+ROUTE         3   e 1.441    SLICE_89.F0 to    SLICE_18.D1 n2290
+CTOF_DEL    ---     0.371    SLICE_18.D1 to    SLICE_18.F1 SLICE_18
+ROUTE         3   e 1.441    SLICE_18.F1 to    SLICE_90.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371    SLICE_90.C0 to    SLICE_90.F0 SLICE_90
+ROUTE         2   e 1.441    SLICE_90.F0 to    SLICE_19.CE PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                   12.873   (21.6% logic, 78.4% route), 7 logic levels.
+
+Report:   26.276ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 348.000ns
+         The internal maximum frequency of the following component is 500.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    FSLICE     CLK            SLICE_76
+
+   Delay:               2.000ns -- based on Minimum Pulse Width
+
+Report:    2.000ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 348.000ns
+         The internal maximum frequency of the following component is 500.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    FSLICE     CLK            SLICE_77
+
+   Delay:               2.000ns -- based on Minimum Pulse Width
+
+Report:    2.000ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            395 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 5.575ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i14  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_391  (to RCLK_c +)
+
+   Delay:              10.181ns  (23.7% logic, 76.3% route), 6 logic levels.
+
+ Constraint Details:
+
+     10.181ns physical path delay SLICE_7 to SLICE_56 meets
+     16.000ns delay constraint less
+      0.244ns CE_SET requirement (totaling 15.756ns) by 5.575ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560    SLICE_7.CLK to     SLICE_7.Q0 SLICE_7 (from RCLK_c)
+ROUTE         3   e 1.441     SLICE_7.Q0 to    SLICE_78.A0 FS_14
+CTOF_DEL    ---     0.371    SLICE_78.A0 to    SLICE_78.F0 SLICE_78
+ROUTE         3   e 1.441    SLICE_78.F0 to    SLICE_73.B1 n10
+CTOF_DEL    ---     0.371    SLICE_73.B1 to    SLICE_73.F1 SLICE_73
+ROUTE         4   e 0.561    SLICE_73.F1 to    SLICE_73.B0 n2300
+CTOF_DEL    ---     0.371    SLICE_73.B0 to    SLICE_73.F0 SLICE_73
+ROUTE         1   e 1.441    SLICE_73.F0 to    SLICE_75.C0 n11
+CTOF_DEL    ---     0.371    SLICE_75.C0 to    SLICE_75.F0 SLICE_75
+ROUTE         2   e 1.441    SLICE_75.F0 to    SLICE_33.D1 n2119
+CTOF_DEL    ---     0.371    SLICE_33.D1 to    SLICE_33.F1 SLICE_33
+ROUTE         1   e 1.441    SLICE_33.F1 to    SLICE_56.CE RCLK_c_enable_7 (to RCLK_c)
+                  --------
+                   10.181   (23.7% logic, 76.3% route), 6 logic levels.
+
+Report:   10.425ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_373  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_55 and
+      5.637ns delay SLICE_55 to RA[10] (totaling 8.141ns) meets
+     12.500ns offset RCLK to RA[10] by 4.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_55.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_55 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_55.CLK to    SLICE_55.Q0 SLICE_55 (from RCLK_c)
+ROUTE         1   e 1.441    SLICE_55.Q0 to       87.PADDO n980
+DOPAD_DEL   ---     3.636       87.PADDO to         87.PAD RA[10]
+                  --------
+                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    8.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[9] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[9] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_88.C1 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_88.C1 to    SLICE_88.F1 SLICE_88
+ROUTE         1   e 1.441    SLICE_88.F1 to       85.PADDO RA_c_9
+DOPAD_DEL   ---     3.636       85.PADDO to         85.PAD RA[9]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[8] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[8] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_95.C0 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_95.C0 to    SLICE_95.F0 SLICE_95
+ROUTE         1   e 1.441    SLICE_95.F0 to       96.PADDO RA_c_8
+DOPAD_DEL   ---     3.636       96.PADDO to         96.PAD RA[8]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[7] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[7] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_97.C0 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_97.C0 to    SLICE_97.F0 SLICE_97
+ROUTE         1   e 1.441    SLICE_97.F0 to      100.PADDO RA_c_7
+DOPAD_DEL   ---     3.636      100.PADDO to        100.PAD RA[7]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[6] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[6] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_98.C0 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_98.C0 to    SLICE_98.F0 SLICE_98
+ROUTE         1   e 1.441    SLICE_98.F0 to       91.PADDO RA_c_6
+DOPAD_DEL   ---     3.636       91.PADDO to         91.PAD RA[6]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[5] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[5] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_98.C1 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_98.C1 to    SLICE_98.F1 SLICE_98
+ROUTE         1   e 1.441    SLICE_98.F1 to       95.PADDO RA_c_5
+DOPAD_DEL   ---     3.636       95.PADDO to         95.PAD RA[5]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.427ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     6.569ns  (69.5% logic, 30.5% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      6.569ns delay SLICE_64 to RA[4] (totaling 9.073ns) meets
+     12.500ns offset RCLK to RA[4] by 3.427ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.561    SLICE_64.Q0 to    SLICE_64.C1 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_64.C1 to    SLICE_64.F1 SLICE_64
+ROUTE         1   e 1.441    SLICE_64.F1 to       99.PADDO RA_c_4
+DOPAD_DEL   ---     3.636       99.PADDO to         99.PAD RA[4]
+                  --------
+                    6.569   (69.5% logic, 30.5% route), 3 logic levels.
+
+Report:    9.073ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[3] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[3] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_94.C1 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_94.C1 to    SLICE_94.F1 SLICE_94
+ROUTE         1   e 1.441    SLICE_94.F1 to       97.PADDO RA_c_3
+DOPAD_DEL   ---     3.636       97.PADDO to         97.PAD RA[3]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[2] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[2] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_95.C1 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_95.C1 to    SLICE_95.F1 SLICE_95
+ROUTE         1   e 1.441    SLICE_95.F1 to       94.PADDO RA_c_2
+DOPAD_DEL   ---     3.636       94.PADDO to         94.PAD RA[2]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[1] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[1] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_94.C0 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_94.C0 to    SLICE_94.F0 SLICE_94
+ROUTE         1   e 1.441    SLICE_94.F0 to       89.PADDO RA_c_1
+DOPAD_DEL   ---     3.636       89.PADDO to         89.PAD RA[1]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RA[0] (totaling 9.953ns) meets
+     12.500ns offset RCLK to RA[0] by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_92.C1 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_92.C1 to    SLICE_92.F1 SLICE_92
+ROUTE         1   e 1.441    SLICE_92.F1 to       98.PADDO RA_c_0
+DOPAD_DEL   ---     3.636       98.PADDO to         98.PAD RA[0]
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_369  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_60 and
+      5.637ns delay SLICE_60 to nRCS (totaling 8.141ns) meets
+     12.500ns offset RCLK to nRCS by 4.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_60.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_60 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_60.CLK to    SLICE_60.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1   e 1.441    SLICE_60.Q0 to       77.PADDO nRCS_c
+DOPAD_DEL   ---     3.636       77.PADDO to         77.PAD nRCS
+                  --------
+                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    8.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_368  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_34 and
+      5.637ns delay SLICE_34 to RCKE (totaling 8.141ns) meets
+     12.500ns offset RCLK to RCKE by 4.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_34.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_34 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_34.CLK to    SLICE_34.Q0 SLICE_34 (from RCLK_c)
+ROUTE         4   e 1.441    SLICE_34.Q0 to       82.PADDO RCKE_c
+DOPAD_DEL   ---     3.636       82.PADDO to         82.PAD RCKE
+                  --------
+                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    8.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_372  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_63 and
+      5.637ns delay SLICE_63 to nRWE (totaling 8.141ns) meets
+     12.500ns offset RCLK to nRWE by 4.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_63 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE         1   e 1.441    SLICE_63.Q0 to       72.PADDO nRWE_c
+DOPAD_DEL   ---     3.636       72.PADDO to         72.PAD nRWE
+                  --------
+                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    8.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_61 and
+      5.637ns delay SLICE_61 to nRRAS (totaling 8.141ns) meets
+     12.500ns offset RCLK to nRRAS by 4.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_61.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_61 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_61.CLK to    SLICE_61.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2   e 1.441    SLICE_61.Q0 to       73.PADDO nRRAS_c
+DOPAD_DEL   ---     3.636       73.PADDO to         73.PAD nRRAS
+                  --------
+                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    8.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_371  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_58 and
+      5.637ns delay SLICE_58 to nRCAS (totaling 8.141ns) meets
+     12.500ns offset RCLK to nRCAS by 4.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_58.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_58 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_58.CLK to    SLICE_58.Q0 SLICE_58 (from RCLK_c)
+ROUTE         1   e 1.441    SLICE_58.Q0 to       78.PADDO nRCAS_c
+DOPAD_DEL   ---     3.636       78.PADDO to         78.PAD nRCAS
+                  --------
+                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    8.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RDQMH (totaling 9.953ns) meets
+     12.500ns offset RCLK to RDQMH by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_88.B0 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_88.B0 to    SLICE_88.F0 SLICE_88
+ROUTE         1   e 1.441    SLICE_88.F0 to       76.PADDO RDQMH_c
+DOPAD_DEL   ---     3.636       76.PADDO to         76.PAD RDQMH
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.547ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
+
+ Constraint Details:
+      2.504ns delay RCLK to SLICE_64 and
+      7.449ns delay SLICE_64 to RDQML (totaling 9.953ns) meets
+     12.500ns offset RCLK to RDQML by 2.547ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_92.B0 nRowColSel
+CTOF_DEL    ---     0.371    SLICE_92.B0 to    SLICE_92.F0 SLICE_92
+ROUTE         1   e 1.441    SLICE_92.F0 to       61.PADDO RDQML_c
+DOPAD_DEL   ---     3.636       61.PADDO to         61.PAD RDQML
+                  --------
+                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
+
+Report:    9.953ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |   350.000 ns|    26.276 ns|   7  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |    16.000 ns|    10.425 ns|   6  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.073 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 526 paths, 6 nets, and 420 connections (67.96% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
+Mon Aug 16 21:33:31 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO640C_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.prf 
+Design file:     ram2gs_lcmxo640c_impl1_map.ncd
+Preference file: ram2gs_lcmxo640c_impl1.prf
+Device,speed:    LCMXO640C,M
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • PERIOD NET "PHI2_c" 350.000000 ns  (0 errors)
    •             113 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCCAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCRAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "RCLK_c" 16.000000 ns  (0 errors)
    •             395 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            113 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.485ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_380  (from PHI2_c -)
+   Destination:    FF         Data in        ADSubmitted_380  (to PHI2_c -)
+
+   Delay:               0.462ns  (56.7% logic, 43.3% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.462ns physical path delay SLICE_9 to SLICE_9 meets
+     -0.023ns DIN_HLD and
+      0.000ns delay constraint requirement (totaling -0.023ns) by 0.485ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170    SLICE_9.CLK to     SLICE_9.Q0 SLICE_9 (from PHI2_c)
+ROUTE         2   e 0.199     SLICE_9.Q0 to     SLICE_9.C0 ADSubmitted
+CTOF_DEL    ---     0.092     SLICE_9.C0 to     SLICE_9.F0 SLICE_9
+ROUTE         1   e 0.001     SLICE_9.F0 to    SLICE_9.DI0 n1361 (to PHI2_c)
+                  --------
+                    0.462   (56.7% logic, 43.3% route), 2 logic levels.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            395 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.377ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i11  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i12  (to RCLK_c +)
+
+   Delay:               0.356ns  (44.1% logic, 55.9% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.356ns physical path delay SLICE_72 to SLICE_72 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint requirement (totaling -0.021ns) by 0.377ns
+
+ Physical Path Details:
+
+      Data path SLICE_72 to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_72.CLK to    SLICE_72.Q0 SLICE_72 (from RCLK_c)
+ROUTE         1   e 0.199    SLICE_72.Q0 to    SLICE_72.M1 n702 (to RCLK_c)
+                  --------
+                    0.356   (44.1% logic, 55.9% route), 1 logic levels.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_373  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_55 and
+      1.780ns delay SLICE_55 to RA[10] (totaling 2.559ns) meets
+      0.000ns hold offset RCLK to RA[10] by 2.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_55.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_55 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_55.CLK to    SLICE_55.Q0 SLICE_55 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_55.Q0 to       87.PADDO n980
+DOPAD_DEL   ---     1.108       87.PADDO to         87.PAD RA[10]
+                  --------
+                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
+
+Report:    2.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[9] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[9] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_88.C1 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_88.C1 to    SLICE_88.F1 SLICE_88
+ROUTE         1   e 0.515    SLICE_88.F1 to       85.PADDO RA_c_9
+DOPAD_DEL   ---     1.108       85.PADDO to         85.PAD RA[9]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[8] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[8] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_95.C0 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_95.C0 to    SLICE_95.F0 SLICE_95
+ROUTE         1   e 0.515    SLICE_95.F0 to       96.PADDO RA_c_8
+DOPAD_DEL   ---     1.108       96.PADDO to         96.PAD RA[8]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[7] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[7] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_97.C0 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_97.C0 to    SLICE_97.F0 SLICE_97
+ROUTE         1   e 0.515    SLICE_97.F0 to      100.PADDO RA_c_7
+DOPAD_DEL   ---     1.108      100.PADDO to        100.PAD RA[7]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[6] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[6] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_98.C0 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_98.C0 to    SLICE_98.F0 SLICE_98
+ROUTE         1   e 0.515    SLICE_98.F0 to       91.PADDO RA_c_6
+DOPAD_DEL   ---     1.108       91.PADDO to         91.PAD RA[6]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[5] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[5] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_98.C1 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_98.C1 to    SLICE_98.F1 SLICE_98
+ROUTE         1   e 0.515    SLICE_98.F1 to       95.PADDO RA_c_5
+DOPAD_DEL   ---     1.108       95.PADDO to         95.PAD RA[5]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.850ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     2.071ns  (65.5% logic, 34.5% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.071ns delay SLICE_64 to RA[4] (totaling 2.850ns) meets
+      0.000ns hold offset RCLK to RA[4] by 2.850ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.199    SLICE_64.Q0 to    SLICE_64.C1 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_64.C1 to    SLICE_64.F1 SLICE_64
+ROUTE         1   e 0.515    SLICE_64.F1 to       99.PADDO RA_c_4
+DOPAD_DEL   ---     1.108       99.PADDO to         99.PAD RA[4]
+                  --------
+                    2.071   (65.5% logic, 34.5% route), 3 logic levels.
+
+Report:    2.850ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[3] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[3] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_94.C1 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_94.C1 to    SLICE_94.F1 SLICE_94
+ROUTE         1   e 0.515    SLICE_94.F1 to       97.PADDO RA_c_3
+DOPAD_DEL   ---     1.108       97.PADDO to         97.PAD RA[3]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[2] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[2] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_95.C1 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_95.C1 to    SLICE_95.F1 SLICE_95
+ROUTE         1   e 0.515    SLICE_95.F1 to       94.PADDO RA_c_2
+DOPAD_DEL   ---     1.108       94.PADDO to         94.PAD RA[2]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[1] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[1] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_94.C0 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_94.C0 to    SLICE_94.F0 SLICE_94
+ROUTE         1   e 0.515    SLICE_94.F0 to       89.PADDO RA_c_1
+DOPAD_DEL   ---     1.108       89.PADDO to         89.PAD RA[1]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RA[0] (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RA[0] by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_92.C1 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_92.C1 to    SLICE_92.F1 SLICE_92
+ROUTE         1   e 0.515    SLICE_92.F1 to       98.PADDO RA_c_0
+DOPAD_DEL   ---     1.108       98.PADDO to         98.PAD RA[0]
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_369  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_60 and
+      1.780ns delay SLICE_60 to nRCS (totaling 2.559ns) meets
+      0.000ns hold offset RCLK to nRCS by 2.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_60.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_60 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_60.CLK to    SLICE_60.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_60.Q0 to       77.PADDO nRCS_c
+DOPAD_DEL   ---     1.108       77.PADDO to         77.PAD nRCS
+                  --------
+                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
+
+Report:    2.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_368  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_34 and
+      1.780ns delay SLICE_34 to RCKE (totaling 2.559ns) meets
+      0.000ns hold offset RCLK to RCKE by 2.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_34.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_34 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_34.CLK to    SLICE_34.Q0 SLICE_34 (from RCLK_c)
+ROUTE         4   e 0.515    SLICE_34.Q0 to       82.PADDO RCKE_c
+DOPAD_DEL   ---     1.108       82.PADDO to         82.PAD RCKE
+                  --------
+                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
+
+Report:    2.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_372  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_63 and
+      1.780ns delay SLICE_63 to nRWE (totaling 2.559ns) meets
+      0.000ns hold offset RCLK to nRWE by 2.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_63 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_63.Q0 to       72.PADDO nRWE_c
+DOPAD_DEL   ---     1.108       72.PADDO to         72.PAD nRWE
+                  --------
+                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
+
+Report:    2.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_61 and
+      1.780ns delay SLICE_61 to nRRAS (totaling 2.559ns) meets
+      0.000ns hold offset RCLK to nRRAS by 2.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_61.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_61 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_61.CLK to    SLICE_61.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2   e 0.515    SLICE_61.Q0 to       73.PADDO nRRAS_c
+DOPAD_DEL   ---     1.108       73.PADDO to         73.PAD nRRAS
+                  --------
+                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
+
+Report:    2.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_371  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_58 and
+      1.780ns delay SLICE_58 to nRCAS (totaling 2.559ns) meets
+      0.000ns hold offset RCLK to nRCAS by 2.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_58.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_58 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_58.CLK to    SLICE_58.Q0 SLICE_58 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_58.Q0 to       78.PADDO nRCAS_c
+DOPAD_DEL   ---     1.108       78.PADDO to         78.PAD nRCAS
+                  --------
+                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
+
+Report:    2.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RDQMH (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RDQMH by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_88.B0 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_88.B0 to    SLICE_88.F0 SLICE_88
+ROUTE         1   e 0.515    SLICE_88.F0 to       76.PADDO RDQMH_c
+DOPAD_DEL   ---     1.108       76.PADDO to         76.PAD RDQMH
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
+
+ Constraint Details:
+      0.779ns delay RCLK to SLICE_64 and
+      2.387ns delay SLICE_64 to RDQML (totaling 3.166ns) meets
+      0.000ns hold offset RCLK to RDQML by 3.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
+                  --------
+                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_92.B0 nRowColSel
+CTOF_DEL    ---     0.092    SLICE_92.B0 to    SLICE_92.F0 SLICE_92
+ROUTE         1   e 0.515    SLICE_92.F0 to       61.PADDO RDQML_c
+DOPAD_DEL   ---     1.108       61.PADDO to         61.PAD RDQML
+                  --------
+                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
+
+Report:    3.166ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |            -|            -|   2  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |            -|            -|   1  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.850 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 526 paths, 6 nets, and 420 connections (67.96% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 0 (setup), 0 (hold)
+Score: 0 (setup), 0 (hold)
+Cumulative negative slack: 0 (0+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
+
+
+
+
    
+
    
+
    
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+
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_twr.html b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_twr.html
new file mode 100644
index 0000000..1e50adc
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_twr.html
@@ -0,0 +1,4571 @@
+
+Lattice TRACE Report
+
+
+
    Place & Route TRACE Report
+
+Loading design for application trce from file ram2gs_lcmxo640c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 3
+Loading device for application trce from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
+Mon Aug 16 21:33:37 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO640C_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf 
+Design file:     ram2gs_lcmxo640c_impl1.ncd
+Preference file: ram2gs_lcmxo640c_impl1.prf
+Device,speed:    LCMXO640C,3
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • PERIOD NET "PHI2_c" 350.000000 ns  (0 errors)
    •             113 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCCAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCRAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "RCLK_c" 16.000000 ns  (0 errors)
    •             395 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            113 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 161.362ns (weighted slack = 322.724ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdSubmitted_384  (to PHI2_c -)
+
+   Delay:              13.373ns  (20.8% logic, 79.2% route), 7 logic levels.
+
+ Constraint Details:
+
+     13.373ns physical path delay SLICE_95 to SLICE_19 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 161.362ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
+ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
+CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
+ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
+CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
+CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
+ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
+CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.899       R5C5A.F1 to       R5C7C.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C7C.C0 to       R5C7C.F0 SLICE_90
+ROUTE         2     1.672       R5C7C.F0 to       R9C8B.CE PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                   13.373   (20.8% logic, 79.2% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R9C8B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 161.494ns (weighted slack = 322.988ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS_385  (to PHI2_c -)
+                   FF                        CmdUFMCLK_386
+
+   Delay:              13.241ns  (21.0% logic, 79.0% route), 7 logic levels.
+
+ Constraint Details:
+
+     13.241ns physical path delay SLICE_95 to SLICE_83 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 161.494ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
+ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
+CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
+ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
+CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
+CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
+ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
+CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.899       R5C5A.F1 to       R5C7A.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C7A.C0 to       R5C7A.F0 SLICE_72
+ROUTE         2     1.540       R5C7A.F0 to       R7C8B.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   13.241   (21.0% logic, 79.0% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R7C8B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 161.494ns (weighted slack = 322.988ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMSDI_387  (to PHI2_c -)
+
+   Delay:              13.241ns  (21.0% logic, 79.0% route), 7 logic levels.
+
+ Constraint Details:
+
+     13.241ns physical path delay SLICE_95 to SLICE_88 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 161.494ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
+ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
+CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
+ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
+CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
+CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
+ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
+CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.899       R5C5A.F1 to       R5C7A.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C7A.C0 to       R5C7A.F0 SLICE_72
+ROUTE         2     1.540       R5C7A.F0 to       R4C9A.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   13.241   (21.0% logic, 79.0% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R4C9A.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 161.945ns (weighted slack = 323.890ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        Cmdn8MEGEN_383  (to PHI2_c -)
+
+   Delay:              12.790ns  (21.8% logic, 78.2% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.790ns physical path delay SLICE_95 to SLICE_23 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 161.945ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
+ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
+CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
+ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
+CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
+CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
+ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
+CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.899       R5C5A.F1 to       R5C7C.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C7C.C0 to       R5C7C.F0 SLICE_90
+ROUTE         2     1.089       R5C7C.F0 to       R6C7B.CE PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                   12.790   (21.8% logic, 78.2% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R6C7B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 161.961ns (weighted slack = 323.922ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        XOR8MEG_381  (to PHI2_c -)
+
+   Delay:              12.774ns  (21.8% logic, 78.2% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.774ns physical path delay SLICE_95 to SLICE_96 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 161.961ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
+ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
+CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
+ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
+CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
+CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
+ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
+CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.899       R5C5A.F1 to       R5C7C.C1 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C7C.C1 to       R5C7C.F1 SLICE_90
+ROUTE         1     1.073       R5C7C.F1 to       R5C8B.CE PHI2_N_114_enable_2 (to PHI2_c)
+                  --------
+                   12.774   (21.8% logic, 78.2% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R5C8B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.123ns (weighted slack = 324.246ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_378  (to PHI2_c -)
+
+   Delay:              12.703ns  (21.9% logic, 78.1% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.703ns physical path delay SLICE_95 to SLICE_18 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.174ns DIN_SET requirement (totaling 174.826ns) by 162.123ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
+ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
+CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
+ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
+CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.134       R4C2A.F1 to       R6C9A.B1 n1285
+CTOF_DEL    ---     0.371       R6C9A.B1 to       R6C9A.F1 SLICE_80
+ROUTE         1     0.696       R6C9A.F1 to       R6C9A.B0 n2289
+CTOF_DEL    ---     0.371       R6C9A.B0 to       R6C9A.F0 SLICE_80
+ROUTE         2     2.112       R6C9A.F0 to       R5C5A.B0 ADSubmitted_N_234
+CTOF_DEL    ---     0.371       R5C5A.B0 to       R5C5A.F0 SLICE_18
+ROUTE         1     0.000       R5C5A.F0 to      R5C5A.DI0 CmdEnable_N_236 (to PHI2_c)
+                  --------
+                   12.703   (21.9% logic, 78.1% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R5C5A.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.123ns (weighted slack = 324.246ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        ADSubmitted_380  (to PHI2_c -)
+
+   Delay:              12.703ns  (21.9% logic, 78.1% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.703ns physical path delay SLICE_95 to SLICE_9 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.174ns DIN_SET requirement (totaling 174.826ns) by 162.123ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
+ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
+CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
+ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
+CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.134       R4C2A.F1 to       R6C9A.B1 n1285
+CTOF_DEL    ---     0.371       R6C9A.B1 to       R6C9A.F1 SLICE_80
+ROUTE         1     0.696       R6C9A.F1 to       R6C9A.B0 n2289
+CTOF_DEL    ---     0.371       R6C9A.B0 to       R6C9A.F0 SLICE_80
+ROUTE         2     2.112       R6C9A.F0 to       R5C5B.B0 ADSubmitted_N_234
+CTOF_DEL    ---     0.371       R5C5B.B0 to       R5C5B.F0 SLICE_9
+ROUTE         1     0.000       R5C5B.F0 to      R5C5B.DI0 n1361 (to PHI2_c)
+                  --------
+                   12.703   (21.9% logic, 78.1% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R5C5B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.710ns (weighted slack = 325.420ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i5  (from PHI2_c +)
+   Destination:    FF         Data in        CmdSubmitted_384  (to PHI2_c -)
+
+   Delay:              12.025ns  (23.2% logic, 76.8% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.025ns physical path delay SLICE_97 to SLICE_19 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 162.710ns
+
+ Physical Path Details:
+
+      Data path SLICE_97 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_97 (from PHI2_c)
+ROUTE         1     1.643       R2C2A.Q1 to       R3C2C.B0 Bank_5
+CTOF_DEL    ---     0.371       R3C2C.B0 to       R3C2C.F0 SLICE_82
+ROUTE         1     0.958       R3C2C.F0 to       R3C2C.A1 n2166
+CTOF_DEL    ---     0.371       R3C2C.A1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
+CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
+ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
+CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.899       R5C5A.F1 to       R5C7C.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C7C.C0 to       R5C7C.F0 SLICE_90
+ROUTE         2     1.672       R5C7C.F0 to       R9C8B.CE PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                   12.025   (23.2% logic, 76.8% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_97:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R2C2A.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R9C8B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.842ns (weighted slack = 325.684ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i5  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS_385  (to PHI2_c -)
+                   FF                        CmdUFMCLK_386
+
+   Delay:              11.893ns  (23.4% logic, 76.6% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.893ns physical path delay SLICE_97 to SLICE_83 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 162.842ns
+
+ Physical Path Details:
+
+      Data path SLICE_97 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_97 (from PHI2_c)
+ROUTE         1     1.643       R2C2A.Q1 to       R3C2C.B0 Bank_5
+CTOF_DEL    ---     0.371       R3C2C.B0 to       R3C2C.F0 SLICE_82
+ROUTE         1     0.958       R3C2C.F0 to       R3C2C.A1 n2166
+CTOF_DEL    ---     0.371       R3C2C.A1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
+CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
+ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
+CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.899       R5C5A.F1 to       R5C7A.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C7A.C0 to       R5C7A.F0 SLICE_72
+ROUTE         2     1.540       R5C7A.F0 to       R7C8B.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   11.893   (23.4% logic, 76.6% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_97:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R2C2A.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R7C8B.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.842ns (weighted slack = 325.684ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i5  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMSDI_387  (to PHI2_c -)
+
+   Delay:              11.893ns  (23.4% logic, 76.6% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.893ns physical path delay SLICE_97 to SLICE_88 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 162.842ns
+
+ Physical Path Details:
+
+      Data path SLICE_97 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_97 (from PHI2_c)
+ROUTE         1     1.643       R2C2A.Q1 to       R3C2C.B0 Bank_5
+CTOF_DEL    ---     0.371       R3C2C.B0 to       R3C2C.F0 SLICE_82
+ROUTE         1     0.958       R3C2C.F0 to       R3C2C.A1 n2166
+CTOF_DEL    ---     0.371       R3C2C.A1 to       R3C2C.F1 SLICE_82
+ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
+CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
+ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
+CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
+ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
+CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.899       R5C5A.F1 to       R5C7A.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C7A.C0 to       R5C7A.F0 SLICE_72
+ROUTE         2     1.540       R5C7A.F0 to       R4C9A.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   11.893   (23.4% logic, 76.6% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_97:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R2C2A.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to      R4C9A.CLK PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:   27.276ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 348.000ns
+         The internal maximum frequency of the following component is 500.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    FSLICE     CLK            SLICE_76
+
+   Delay:               2.000ns -- based on Minimum Pulse Width
+
+Report:    2.000ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 348.000ns
+         The internal maximum frequency of the following component is 500.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    FSLICE     CLK            SLICE_77
+
+   Delay:               2.000ns -- based on Minimum Pulse Width
+
+Report:    2.000ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            395 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 6.557ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S_FSM_i4  (from RCLK_c +)
+   Destination:    FF         Data in        nRRAS_370  (to RCLK_c +)
+
+   Delay:               9.262ns  (20.9% logic, 79.1% route), 4 logic levels.
+
+ Constraint Details:
+
+      9.262ns physical path delay SLICE_65 to SLICE_61 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 15.819ns) by 6.557ns
+
+ Physical Path Details:
+
+      Data path SLICE_65 to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9C.CLK to       R5C9C.Q0 SLICE_65 (from RCLK_c)
+ROUTE         7     2.149       R5C9C.Q0 to       R3C2A.B1 nRowColSel_N_32
+CTOF_DEL    ---     0.371       R3C2A.B1 to       R3C2A.F1 SLICE_61
+ROUTE         2     2.624       R3C2A.F1 to       R8C9D.B0 n50
+CTOOFX_DEL  ---     0.631       R8C9D.B0 to     R8C9D.OFX0 i1912/SLICE_70
+ROUTE         1     2.556     R8C9D.OFX0 to       R3C2A.A0 n2244
+CTOF_DEL    ---     0.371       R3C2A.A0 to       R3C2A.F0 SLICE_61
+ROUTE         1     0.000       R3C2A.F0 to      R3C2A.DI0 n33 (to RCLK_c)
+                  --------
+                    9.262   (20.9% logic, 79.1% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_65:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R5C9C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 6.573ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S_FSM_i4  (from RCLK_c +)
+   Destination:    FF         Data in        nRRAS_370  (to RCLK_c +)
+
+   Delay:               9.246ns  (20.7% logic, 79.3% route), 4 logic levels.
+
+ Constraint Details:
+
+      9.246ns physical path delay SLICE_65 to SLICE_61 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 15.819ns) by 6.573ns
+
+ Physical Path Details:
+
+      Data path SLICE_65 to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9C.CLK to       R5C9C.Q0 SLICE_65 (from RCLK_c)
+ROUTE         7     2.149       R5C9C.Q0 to       R3C2A.B1 nRowColSel_N_32
+CTOF_DEL    ---     0.371       R3C2A.B1 to       R3C2A.F1 SLICE_61
+ROUTE         2     2.624       R3C2A.F1 to       R8C9D.B1 n50
+CTOOFX_DEL  ---     0.615       R8C9D.B1 to     R8C9D.OFX0 i1912/SLICE_70
+ROUTE         1     2.556     R8C9D.OFX0 to       R3C2A.A0 n2244
+CTOF_DEL    ---     0.371       R3C2A.A0 to       R3C2A.F0 SLICE_61
+ROUTE         1     0.000       R3C2A.F0 to      R3C2A.DI0 n33 (to RCLK_c)
+                  --------
+                    9.246   (20.7% logic, 79.3% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_65:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R5C9C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 6.866ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i15  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_392  (to RCLK_c +)
+
+   Delay:               8.890ns  (27.2% logic, 72.8% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.890ns physical path delay SLICE_7 to SLICE_89 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 6.866ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560     R10C7D.CLK to      R10C7D.Q1 SLICE_7 (from RCLK_c)
+ROUTE         3     1.466      R10C7D.Q1 to      R10C8D.B0 FS_15
+CTOF_DEL    ---     0.371      R10C8D.B0 to      R10C8D.F0 SLICE_78
+ROUTE         3     1.117      R10C8D.F0 to       R9C8A.B1 n10
+CTOF_DEL    ---     0.371       R9C8A.B1 to       R9C8A.F1 SLICE_73
+ROUTE         4     0.727       R9C8A.F1 to       R9C8A.B0 n2300
+CTOF_DEL    ---     0.371       R9C8A.B0 to       R9C8A.F0 SLICE_73
+ROUTE         1     0.626       R9C8A.F0 to       R9C8D.D0 n11
+CTOF_DEL    ---     0.371       R9C8D.D0 to       R9C8D.F0 SLICE_75
+ROUTE         2     0.513       R9C8D.F0 to       R9C8D.C1 n2119
+CTOF_DEL    ---     0.371       R9C8D.C1 to       R9C8D.F1 SLICE_75
+ROUTE         1     2.026       R9C8D.F1 to       R5C6A.CE RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    8.890   (27.2% logic, 72.8% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to     R10C7D.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R5C6A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 6.963ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S_FSM_i3  (from RCLK_c +)
+   Destination:    FF         Data in        nRRAS_370  (to RCLK_c +)
+
+   Delay:               8.856ns  (21.8% logic, 78.2% route), 4 logic levels.
+
+ Constraint Details:
+
+      8.856ns physical path delay SLICE_66 to SLICE_61 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 15.819ns) by 6.963ns
+
+ Physical Path Details:
+
+      Data path SLICE_66 to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9D.CLK to       R5C9D.Q0 SLICE_66 (from RCLK_c)
+ROUTE         6     1.743       R5C9D.Q0 to       R3C2A.D1 nRowColSel_N_33
+CTOF_DEL    ---     0.371       R3C2A.D1 to       R3C2A.F1 SLICE_61
+ROUTE         2     2.624       R3C2A.F1 to       R8C9D.B0 n50
+CTOOFX_DEL  ---     0.631       R8C9D.B0 to     R8C9D.OFX0 i1912/SLICE_70
+ROUTE         1     2.556     R8C9D.OFX0 to       R3C2A.A0 n2244
+CTOF_DEL    ---     0.371       R3C2A.A0 to       R3C2A.F0 SLICE_61
+ROUTE         1     0.000       R3C2A.F0 to      R3C2A.DI0 n33 (to RCLK_c)
+                  --------
+                    8.856   (21.8% logic, 78.2% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_66:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R5C9D.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 6.979ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S_FSM_i3  (from RCLK_c +)
+   Destination:    FF         Data in        nRRAS_370  (to RCLK_c +)
+
+   Delay:               8.840ns  (21.7% logic, 78.3% route), 4 logic levels.
+
+ Constraint Details:
+
+      8.840ns physical path delay SLICE_66 to SLICE_61 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 15.819ns) by 6.979ns
+
+ Physical Path Details:
+
+      Data path SLICE_66 to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9D.CLK to       R5C9D.Q0 SLICE_66 (from RCLK_c)
+ROUTE         6     1.743       R5C9D.Q0 to       R3C2A.D1 nRowColSel_N_33
+CTOF_DEL    ---     0.371       R3C2A.D1 to       R3C2A.F1 SLICE_61
+ROUTE         2     2.624       R3C2A.F1 to       R8C9D.B1 n50
+CTOOFX_DEL  ---     0.615       R8C9D.B1 to     R8C9D.OFX0 i1912/SLICE_70
+ROUTE         1     2.556     R8C9D.OFX0 to       R3C2A.A0 n2244
+CTOF_DEL    ---     0.371       R3C2A.A0 to       R3C2A.F0 SLICE_61
+ROUTE         1     0.000       R3C2A.F0 to      R3C2A.DI0 n33 (to RCLK_c)
+                  --------
+                    8.840   (21.7% logic, 78.3% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_66:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R5C9D.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.065ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i14  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_392  (to RCLK_c +)
+
+   Delay:               8.691ns  (27.8% logic, 72.2% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.691ns physical path delay SLICE_7 to SLICE_89 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 7.065ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560     R10C7D.CLK to      R10C7D.Q0 SLICE_7 (from RCLK_c)
+ROUTE         3     1.267      R10C7D.Q0 to      R10C8D.C0 FS_14
+CTOF_DEL    ---     0.371      R10C8D.C0 to      R10C8D.F0 SLICE_78
+ROUTE         3     1.117      R10C8D.F0 to       R9C8A.B1 n10
+CTOF_DEL    ---     0.371       R9C8A.B1 to       R9C8A.F1 SLICE_73
+ROUTE         4     0.727       R9C8A.F1 to       R9C8A.B0 n2300
+CTOF_DEL    ---     0.371       R9C8A.B0 to       R9C8A.F0 SLICE_73
+ROUTE         1     0.626       R9C8A.F0 to       R9C8D.D0 n11
+CTOF_DEL    ---     0.371       R9C8D.D0 to       R9C8D.F0 SLICE_75
+ROUTE         2     0.513       R9C8D.F0 to       R9C8D.C1 n2119
+CTOF_DEL    ---     0.371       R9C8D.C1 to       R9C8D.F1 SLICE_75
+ROUTE         1     2.026       R9C8D.F1 to       R5C6A.CE RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    8.691   (27.8% logic, 72.2% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to     R10C7D.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R5C6A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.284ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i13  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_392  (to RCLK_c +)
+
+   Delay:               8.472ns  (28.5% logic, 71.5% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.472ns physical path delay SLICE_8 to SLICE_89 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 7.284ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560     R10C7C.CLK to      R10C7C.Q1 SLICE_8 (from RCLK_c)
+ROUTE         3     1.048      R10C7C.Q1 to      R10C8D.A0 FS_13
+CTOF_DEL    ---     0.371      R10C8D.A0 to      R10C8D.F0 SLICE_78
+ROUTE         3     1.117      R10C8D.F0 to       R9C8A.B1 n10
+CTOF_DEL    ---     0.371       R9C8A.B1 to       R9C8A.F1 SLICE_73
+ROUTE         4     0.727       R9C8A.F1 to       R9C8A.B0 n2300
+CTOF_DEL    ---     0.371       R9C8A.B0 to       R9C8A.F0 SLICE_73
+ROUTE         1     0.626       R9C8A.F0 to       R9C8D.D0 n11
+CTOF_DEL    ---     0.371       R9C8D.D0 to       R9C8D.F0 SLICE_75
+ROUTE         2     0.513       R9C8D.F0 to       R9C8D.C1 n2119
+CTOF_DEL    ---     0.371       R9C8D.C1 to       R9C8D.F1 SLICE_75
+ROUTE         1     2.026       R9C8D.F1 to       R5C6A.CE RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    8.472   (28.5% logic, 71.5% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to     R10C7C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R5C6A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.601ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_577__i12  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_392  (to RCLK_c +)
+
+   Delay:               8.155ns  (29.6% logic, 70.4% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.155ns physical path delay SLICE_8 to SLICE_89 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 7.601ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560     R10C7C.CLK to      R10C7C.Q0 SLICE_8 (from RCLK_c)
+ROUTE         3     0.731      R10C7C.Q0 to      R10C8D.D0 FS_12
+CTOF_DEL    ---     0.371      R10C8D.D0 to      R10C8D.F0 SLICE_78
+ROUTE         3     1.117      R10C8D.F0 to       R9C8A.B1 n10
+CTOF_DEL    ---     0.371       R9C8A.B1 to       R9C8A.F1 SLICE_73
+ROUTE         4     0.727       R9C8A.F1 to       R9C8A.B0 n2300
+CTOF_DEL    ---     0.371       R9C8A.B0 to       R9C8A.F0 SLICE_73
+ROUTE         1     0.626       R9C8A.F0 to       R9C8D.D0 n11
+CTOF_DEL    ---     0.371       R9C8D.D0 to       R9C8D.F0 SLICE_75
+ROUTE         2     0.513       R9C8D.F0 to       R9C8D.C1 n2119
+CTOF_DEL    ---     0.371       R9C8D.C1 to       R9C8D.F1 SLICE_75
+ROUTE         1     2.026       R9C8D.F1 to       R5C6A.CE RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    8.155   (29.6% logic, 70.4% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to     R10C7C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_89:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R5C6A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.732ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
+   Destination:    FF         Data in        nRRAS_370  (to RCLK_c +)
+
+   Delay:               8.087ns  (23.9% logic, 76.1% route), 4 logic levels.
+
+ Constraint Details:
+
+      8.087ns physical path delay SLICE_61 to SLICE_61 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 15.819ns) by 7.732ns
+
+ Physical Path Details:
+
+      Data path SLICE_61 to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2A.CLK to       R3C2A.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2     0.974       R3C2A.Q0 to       R3C2A.A1 nRRAS_c
+CTOF_DEL    ---     0.371       R3C2A.A1 to       R3C2A.F1 SLICE_61
+ROUTE         2     2.624       R3C2A.F1 to       R8C9D.B0 n50
+CTOOFX_DEL  ---     0.631       R8C9D.B0 to     R8C9D.OFX0 i1912/SLICE_70
+ROUTE         1     2.556     R8C9D.OFX0 to       R3C2A.A0 n2244
+CTOF_DEL    ---     0.371       R3C2A.A0 to       R3C2A.F0 SLICE_61
+ROUTE         1     0.000       R3C2A.F0 to      R3C2A.DI0 n33 (to RCLK_c)
+                  --------
+                    8.087   (23.9% logic, 76.1% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 7.748ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
+   Destination:    FF         Data in        nRRAS_370  (to RCLK_c +)
+
+   Delay:               8.071ns  (23.8% logic, 76.2% route), 4 logic levels.
+
+ Constraint Details:
+
+      8.071ns physical path delay SLICE_61 to SLICE_61 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 15.819ns) by 7.748ns
+
+ Physical Path Details:
+
+      Data path SLICE_61 to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2A.CLK to       R3C2A.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2     0.974       R3C2A.Q0 to       R3C2A.A1 nRRAS_c
+CTOF_DEL    ---     0.371       R3C2A.A1 to       R3C2A.F1 SLICE_61
+ROUTE         2     2.624       R3C2A.F1 to       R8C9D.B1 n50
+CTOOFX_DEL  ---     0.615       R8C9D.B1 to     R8C9D.OFX0 i1912/SLICE_70
+ROUTE         1     2.556     R8C9D.OFX0 to       R3C2A.A0 n2244
+CTOF_DEL    ---     0.371       R3C2A.A0 to       R3C2A.F0 SLICE_61
+ROUTE         1     0.000       R3C2A.F0 to      R3C2A.DI0 n33 (to RCLK_c)
+                  --------
+                    8.071   (23.8% logic, 76.2% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:    9.443ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.999ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_373  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_55 and
+      5.013ns delay SLICE_55 to RA[10] (totaling 7.501ns) meets
+     12.500ns offset RCLK to RA[10] by 4.999ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R2C5A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_55 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C5A.CLK to       R2C5A.Q0 SLICE_55 (from RCLK_c)
+ROUTE         1     0.817       R2C5A.Q0 to       87.PADDO n980
+DOPAD_DEL   ---     3.636       87.PADDO to         87.PAD RA[10]
+                  --------
+                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
+
+Report:    7.501ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.088ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     7.924ns  (57.6% logic, 42.4% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      7.924ns delay SLICE_64 to RA[9] (totaling 10.412ns) meets
+     12.500ns offset RCLK to RA[9] by 2.088ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.793       R5C9A.Q0 to       R4C9A.D1 nRowColSel
+CTOF_DEL    ---     0.371       R4C9A.D1 to       R4C9A.F1 SLICE_88
+ROUTE         1     2.564       R4C9A.F1 to       85.PADDO RA_c_9
+DOPAD_DEL   ---     3.636       85.PADDO to         85.PAD RA[9]
+                  --------
+                    7.924   (57.6% logic, 42.4% route), 3 logic levels.
+
+Report:   10.412ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.035ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     7.977ns  (57.3% logic, 42.7% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      7.977ns delay SLICE_64 to RA[8] (totaling 10.465ns) meets
+     12.500ns offset RCLK to RA[8] by 2.035ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.750       R5C9A.Q0 to       R3C2B.D0 nRowColSel
+CTOF_DEL    ---     0.371       R3C2B.D0 to       R3C2B.F0 SLICE_95
+ROUTE         1     1.660       R3C2B.F0 to       96.PADDO RA_c_8
+DOPAD_DEL   ---     3.636       96.PADDO to         96.PAD RA[8]
+                  --------
+                    7.977   (57.3% logic, 42.7% route), 3 logic levels.
+
+Report:   10.465ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.583ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     7.429ns  (61.5% logic, 38.5% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      7.429ns delay SLICE_64 to RA[7] (totaling 9.917ns) meets
+     12.500ns offset RCLK to RA[7] by 2.583ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     2.045       R5C9A.Q0 to       R2C2A.C0 nRowColSel
+CTOF_DEL    ---     0.371       R2C2A.C0 to       R2C2A.F0 SLICE_97
+ROUTE         1     0.817       R2C2A.F0 to      100.PADDO RA_c_7
+DOPAD_DEL   ---     3.636      100.PADDO to        100.PAD RA[7]
+                  --------
+                    7.429   (61.5% logic, 38.5% route), 3 logic levels.
+
+Report:    9.917ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     7.846ns  (58.2% logic, 41.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      7.846ns delay SLICE_64 to RA[6] (totaling 10.334ns) meets
+     12.500ns offset RCLK to RA[6] by 2.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.753       R5C9A.Q0 to       R2C3A.D0 nRowColSel
+CTOF_DEL    ---     0.371       R2C3A.D0 to       R2C3A.F0 SLICE_98
+ROUTE         1     1.526       R2C3A.F0 to       91.PADDO RA_c_6
+DOPAD_DEL   ---     3.636       91.PADDO to         91.PAD RA[6]
+                  --------
+                    7.846   (58.2% logic, 41.8% route), 3 logic levels.
+
+Report:   10.334ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     7.846ns  (58.2% logic, 41.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      7.846ns delay SLICE_64 to RA[5] (totaling 10.334ns) meets
+     12.500ns offset RCLK to RA[5] by 2.166ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.753       R5C9A.Q0 to       R2C3A.D1 nRowColSel
+CTOF_DEL    ---     0.371       R2C3A.D1 to       R2C3A.F1 SLICE_98
+ROUTE         1     1.526       R2C3A.F1 to       95.PADDO RA_c_5
+DOPAD_DEL   ---     3.636       95.PADDO to         95.PAD RA[5]
+                  --------
+                    7.846   (58.2% logic, 41.8% route), 3 logic levels.
+
+Report:   10.334ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.742ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     8.270ns  (55.2% logic, 44.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      8.270ns delay SLICE_64 to RA[4] (totaling 10.758ns) meets
+     12.500ns offset RCLK to RA[4] by 1.742ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.702       R5C9A.Q0 to       R5C9A.D1 nRowColSel
+CTOF_DEL    ---     0.371       R5C9A.D1 to       R5C9A.F1 SLICE_64
+ROUTE         1     3.001       R5C9A.F1 to       99.PADDO RA_c_4
+DOPAD_DEL   ---     3.636       99.PADDO to         99.PAD RA[4]
+                  --------
+                    8.270   (55.2% logic, 44.8% route), 3 logic levels.
+
+Report:   10.758ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.725ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     8.287ns  (55.1% logic, 44.9% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      8.287ns delay SLICE_64 to RA[3] (totaling 10.775ns) meets
+     12.500ns offset RCLK to RA[3] by 1.725ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     2.198       R5C9A.Q0 to       R2C2C.D1 nRowColSel
+CTOF_DEL    ---     0.371       R2C2C.D1 to       R2C2C.F1 SLICE_94
+ROUTE         1     1.522       R2C2C.F1 to       97.PADDO RA_c_3
+DOPAD_DEL   ---     3.636       97.PADDO to         97.PAD RA[3]
+                  --------
+                    8.287   (55.1% logic, 44.9% route), 3 logic levels.
+
+Report:   10.775ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.643ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     8.369ns  (54.6% logic, 45.4% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      8.369ns delay SLICE_64 to RA[2] (totaling 10.857ns) meets
+     12.500ns offset RCLK to RA[2] by 1.643ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.750       R5C9A.Q0 to       R3C2B.D1 nRowColSel
+CTOF_DEL    ---     0.371       R3C2B.D1 to       R3C2B.F1 SLICE_95
+ROUTE         1     2.052       R3C2B.F1 to       94.PADDO RA_c_2
+DOPAD_DEL   ---     3.636       94.PADDO to         94.PAD RA[2]
+                  --------
+                    8.369   (54.6% logic, 45.4% route), 3 logic levels.
+
+Report:   10.857ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.417ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     8.595ns  (53.1% logic, 46.9% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      8.595ns delay SLICE_64 to RA[1] (totaling 11.083ns) meets
+     12.500ns offset RCLK to RA[1] by 1.417ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     2.045       R5C9A.Q0 to       R2C2C.C0 nRowColSel
+CTOF_DEL    ---     0.371       R2C2C.C0 to       R2C2C.F0 SLICE_94
+ROUTE         1     1.983       R2C2C.F0 to       89.PADDO RA_c_1
+DOPAD_DEL   ---     3.636       89.PADDO to         89.PAD RA[1]
+                  --------
+                    8.595   (53.1% logic, 46.9% route), 3 logic levels.
+
+Report:   11.083ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.213ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     8.799ns  (51.9% logic, 48.1% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      8.799ns delay SLICE_64 to RA[0] (totaling 11.287ns) meets
+     12.500ns offset RCLK to RA[0] by 1.213ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.245       R5C9A.Q0 to       R8C9C.D1 nRowColSel
+CTOF_DEL    ---     0.371       R8C9C.D1 to       R8C9C.F1 SLICE_92
+ROUTE         1     2.987       R8C9C.F1 to       98.PADDO RA_c_0
+DOPAD_DEL   ---     3.636       98.PADDO to         98.PAD RA[0]
+                  --------
+                    8.799   (51.9% logic, 48.1% route), 3 logic levels.
+
+Report:   11.287ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.999ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_369  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_60 and
+      5.013ns delay SLICE_60 to nRCS (totaling 7.501ns) meets
+     12.500ns offset RCLK to nRCS by 4.999ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R2C9C.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_60 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C9C.CLK to       R2C9C.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1     0.817       R2C9C.Q0 to       77.PADDO nRCS_c
+DOPAD_DEL   ---     3.636       77.PADDO to         77.PAD nRCS
+                  --------
+                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
+
+Report:    7.501ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.999ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_368  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_34 and
+      5.013ns delay SLICE_34 to RCKE (totaling 7.501ns) meets
+     12.500ns offset RCLK to RCKE by 4.999ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R2C7C.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_34 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C7C.CLK to       R2C7C.Q0 SLICE_34 (from RCLK_c)
+ROUTE         4     0.817       R2C7C.Q0 to       82.PADDO RCKE_c
+DOPAD_DEL   ---     3.636       82.PADDO to         82.PAD RCKE
+                  --------
+                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
+
+Report:    7.501ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.359ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_372  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     6.653ns  (63.1% logic, 36.9% route), 2 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_63 and
+      6.653ns delay SLICE_63 to nRWE (totaling 9.141ns) meets
+     12.500ns offset RCLK to nRWE by 3.359ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to     R10C9C.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_63 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560     R10C9C.CLK to      R10C9C.Q0 SLICE_63 (from RCLK_c)
+ROUTE         1     2.457      R10C9C.Q0 to       72.PADDO nRWE_c
+DOPAD_DEL   ---     3.636       72.PADDO to         72.PAD nRWE
+                  --------
+                    6.653   (63.1% logic, 36.9% route), 2 logic levels.
+
+Report:    9.141ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.325ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     6.687ns  (62.7% logic, 37.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_61 and
+      6.687ns delay SLICE_61 to nRRAS (totaling 9.175ns) meets
+     12.500ns offset RCLK to nRRAS by 3.325ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_61 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C2A.CLK to       R3C2A.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2     2.491       R3C2A.Q0 to       73.PADDO nRRAS_c
+DOPAD_DEL   ---     3.636       73.PADDO to         73.PAD nRRAS
+                  --------
+                    6.687   (62.7% logic, 37.3% route), 2 logic levels.
+
+Report:    9.175ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.999ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_371  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_58 and
+      5.013ns delay SLICE_58 to nRCAS (totaling 7.501ns) meets
+     12.500ns offset RCLK to nRCAS by 4.999ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R2C9B.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_58 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C9B.CLK to       R2C9B.Q0 SLICE_58 (from RCLK_c)
+ROUTE         1     0.817       R2C9B.Q0 to       78.PADDO nRCAS_c
+DOPAD_DEL   ---     3.636       78.PADDO to         78.PAD nRCAS
+                  --------
+                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
+
+Report:    7.501ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.669ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     7.343ns  (62.2% logic, 37.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      7.343ns delay SLICE_64 to RDQMH (totaling 9.831ns) meets
+     12.500ns offset RCLK to RDQMH by 2.669ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.793       R5C9A.Q0 to       R4C9A.D0 nRowColSel
+CTOF_DEL    ---     0.371       R4C9A.D0 to       R4C9A.F0 SLICE_88
+ROUTE         1     1.983       R4C9A.F0 to       76.PADDO RDQMH_c
+DOPAD_DEL   ---     3.636       76.PADDO to         76.PAD RDQMH
+                  --------
+                    7.343   (62.2% logic, 37.8% route), 3 logic levels.
+
+Report:    9.831ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.383ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     6.629ns  (68.9% logic, 31.1% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      6.629ns delay SLICE_64 to RDQML (totaling 9.117ns) meets
+     12.500ns offset RCLK to RDQML by 3.383ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.245       R5C9A.Q0 to       R8C9C.D0 nRowColSel
+CTOF_DEL    ---     0.371       R8C9C.D0 to       R8C9C.F0 SLICE_92
+ROUTE         1     0.817       R8C9C.F0 to       61.PADDO RDQML_c
+DOPAD_DEL   ---     3.636       61.PADDO to         61.PAD RDQML
+                  --------
+                    6.629   (68.9% logic, 31.1% route), 3 logic levels.
+
+Report:    9.117ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |   350.000 ns|    27.276 ns|   7  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |    16.000 ns|     9.443 ns|   4  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     7.501 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.412 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.465 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.917 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.334 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.334 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.758 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.775 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.857 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    11.083 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    11.287 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     7.501 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     7.501 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.141 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.175 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     7.501 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.831 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.117 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 526 paths, 6 nets, and 444 connections (71.84% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
+Mon Aug 16 21:33:37 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO640C_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf 
+Design file:     ram2gs_lcmxo640c_impl1.ncd
+Preference file: ram2gs_lcmxo640c_impl1.prf
+Device,speed:    LCMXO640C,m
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • PERIOD NET "PHI2_c" 350.000000 ns  (0 errors)
    •             113 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCCAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCRAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "RCLK_c" 16.000000 ns  (0 errors)
    •             395 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            113 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.447ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_380  (from PHI2_c -)
+   Destination:    FF         Data in        ADSubmitted_380  (to PHI2_c -)
+
+   Delay:               0.424ns  (61.8% logic, 38.2% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.424ns physical path delay SLICE_9 to SLICE_9 meets
+     -0.023ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.023ns) by 0.447ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C5B.CLK to       R5C5B.Q0 SLICE_9 (from PHI2_c)
+ROUTE         2     0.162       R5C5B.Q0 to       R5C5B.A0 ADSubmitted
+CTOF_DEL    ---     0.092       R5C5B.A0 to       R5C5B.F0 SLICE_9
+ROUTE         1     0.000       R5C5B.F0 to      R5C5B.DI0 n1361 (to PHI2_c)
+                  --------
+                    0.424   (61.8% logic, 38.2% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5B.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5B.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.113ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
+   Destination:    FF         Data in        XOR8MEG_381  (to PHI2_c -)
+
+   Delay:               1.084ns  (32.7% logic, 67.3% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.084ns physical path delay SLICE_18 to SLICE_96 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.113ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C5A.CLK to       R5C5A.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.238       R5C5A.Q0 to       R5C5A.A1 CmdEnable
+CTOF_DEL    ---     0.092       R5C5A.A1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.225       R5C5A.F1 to       R5C7C.C1 XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R5C7C.C1 to       R5C7C.F1 SLICE_90
+ROUTE         1     0.267       R5C7C.F1 to       R5C8B.CE PHI2_N_114_enable_2 (to PHI2_c)
+                  --------
+                    1.084   (32.7% logic, 67.3% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C8B.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.118ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
+   Destination:    FF         Data in        Cmdn8MEGEN_383  (to PHI2_c -)
+
+   Delay:               1.089ns  (32.5% logic, 67.5% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.089ns physical path delay SLICE_18 to SLICE_23 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.118ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C5A.CLK to       R5C5A.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.238       R5C5A.Q0 to       R5C5A.A1 CmdEnable
+CTOF_DEL    ---     0.092       R5C5A.A1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.225       R5C5A.F1 to       R5C7C.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R5C7C.C0 to       R5C7C.F0 SLICE_90
+ROUTE         2     0.272       R5C7C.F0 to       R6C7B.CE PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                    1.089   (32.5% logic, 67.5% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R6C7B.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.238ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMCS_385  (to PHI2_c -)
+                   FF                        CmdUFMCLK_386
+
+   Delay:               1.209ns  (29.3% logic, 70.7% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.209ns physical path delay SLICE_18 to SLICE_83 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.238ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C5A.CLK to       R5C5A.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.238       R5C5A.Q0 to       R5C5A.A1 CmdEnable
+CTOF_DEL    ---     0.092       R5C5A.A1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.225       R5C5A.F1 to       R5C7A.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R5C7A.C0 to       R5C7A.F0 SLICE_72
+ROUTE         2     0.392       R5C7A.F0 to       R7C8B.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                    1.209   (29.3% logic, 70.7% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R7C8B.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.238ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMSDI_387  (to PHI2_c -)
+
+   Delay:               1.209ns  (29.3% logic, 70.7% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.209ns physical path delay SLICE_18 to SLICE_88 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.238ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C5A.CLK to       R5C5A.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.238       R5C5A.Q0 to       R5C5A.A1 CmdEnable
+CTOF_DEL    ---     0.092       R5C5A.A1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.225       R5C5A.F1 to       R5C7A.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R5C7A.C0 to       R5C7A.F0 SLICE_72
+ROUTE         2     0.392       R5C7A.F0 to       R4C9A.CE PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                    1.209   (29.3% logic, 70.7% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R4C9A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.270ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_380  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_378  (to PHI2_c -)
+
+   Delay:               1.241ns  (35.9% logic, 64.1% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.241ns physical path delay SLICE_9 to SLICE_18 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.270ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C5B.CLK to       R5C5B.Q0 SLICE_9 (from PHI2_c)
+ROUTE         2     0.258       R5C5B.Q0 to       R5C5B.B1 ADSubmitted
+CTOF_DEL    ---     0.092       R5C5B.B1 to       R5C5B.F1 SLICE_9
+ROUTE         1     0.123       R5C5B.F1 to       R5C5D.C1 n2080
+CTOF_DEL    ---     0.092       R5C5D.C1 to       R5C5D.F1 SLICE_77
+ROUTE         1     0.253       R5C5D.F1 to       R5C5D.B0 n2286
+CTOF_DEL    ---     0.092       R5C5D.B0 to       R5C5D.F0 SLICE_77
+ROUTE         1     0.161       R5C5D.F0 to       R5C5A.CE PHI2_N_114_enable_8 (to PHI2_c)
+                  --------
+                    1.241   (35.9% logic, 64.1% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5B.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.276ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
+   Destination:    FF         Data in        CmdSubmitted_384  (to PHI2_c -)
+
+   Delay:               1.247ns  (28.4% logic, 71.6% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.247ns physical path delay SLICE_18 to SLICE_19 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.276ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C5A.CLK to       R5C5A.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.238       R5C5A.Q0 to       R5C5A.A1 CmdEnable
+CTOF_DEL    ---     0.092       R5C5A.A1 to       R5C5A.F1 SLICE_18
+ROUTE         3     0.225       R5C5A.F1 to       R5C7C.C0 XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R5C7C.C0 to       R5C7C.F0 SLICE_90
+ROUTE         2     0.430       R5C7C.F0 to       R9C8B.CE PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                    1.247   (28.4% logic, 71.6% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R9C8B.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.299ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_379  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_378  (to PHI2_c -)
+
+   Delay:               1.270ns  (35.1% logic, 64.9% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.270ns physical path delay SLICE_14 to SLICE_18 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.299ns
+
+ Physical Path Details:
+
+      Data path SLICE_14 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C5C.CLK to       R5C5C.Q0 SLICE_14 (from PHI2_c)
+ROUTE         1     0.238       R5C5C.Q0 to       R5C5C.A1 C1Submitted
+CTOF_DEL    ---     0.092       R5C5C.A1 to       R5C5C.F1 SLICE_14
+ROUTE         1     0.172       R5C5C.F1 to       R5C5D.B1 n2098
+CTOF_DEL    ---     0.092       R5C5D.B1 to       R5C5D.F1 SLICE_77
+ROUTE         1     0.253       R5C5D.F1 to       R5C5D.B0 n2286
+CTOF_DEL    ---     0.092       R5C5D.B0 to       R5C5D.F0 SLICE_77
+ROUTE         1     0.161       R5C5D.F0 to       R5C5A.CE PHI2_N_114_enable_8 (to PHI2_c)
+                  --------
+                    1.270   (35.1% logic, 64.9% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5C.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 175.790ns (weighted slack = 351.580ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              XOR8MEG_381  (from PHI2_c -)
+   Destination:    FF         Data in        RA11_358  (to PHI2_c +)
+
+   Delay:               0.779ns  (33.6% logic, 66.4% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.779ns physical path delay SLICE_96 to SLICE_31 meets
+     -0.011ns DIN_HLD and
+    -175.000ns delay constraint less
+      0.000ns skew requirement (totaling -175.011ns) by 175.790ns
+
+ Physical Path Details:
+
+      Data path SLICE_96 to SLICE_31:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R5C8B.CLK to       R5C8B.Q0 SLICE_96 (from PHI2_c)
+ROUTE         1     0.517       R5C8B.Q0 to       R2C9A.B0 XOR8MEG
+CTOF_DEL    ---     0.092       R2C9A.B0 to       R2C9A.F0 SLICE_31
+ROUTE         1     0.000       R2C9A.F0 to      R2C9A.DI0 RA11_N_180 (to PHI2_c)
+                  --------
+                    0.779   (33.6% logic, 66.4% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C8B.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_31:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R2C9A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 176.484ns (weighted slack = 352.968ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i3  (from PHI2_c +)
+   Destination:    FF         Data in        C1Submitted_379  (to PHI2_c -)
+
+   Delay:               1.455ns  (23.4% logic, 76.6% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.455ns physical path delay SLICE_98 to SLICE_14 meets
+     -0.029ns CE_HLD and
+    -175.000ns delay constraint less
+      0.000ns skew requirement (totaling -175.029ns) by 176.484ns
+
+ Physical Path Details:
+
+      Data path SLICE_98 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C3A.CLK to       R2C3A.Q1 SLICE_98 (from PHI2_c)
+ROUTE         1     0.382       R2C3A.Q1 to       R4C2A.B1 Bank_3
+CTOF_DEL    ---     0.092       R4C2A.B1 to       R4C2A.F1 SLICE_76
+ROUTE         4     0.556       R4C2A.F1 to       R5C6A.B1 n1285
+CTOF_DEL    ---     0.092       R5C6A.B1 to       R5C6A.F1 SLICE_89
+ROUTE         1     0.176       R5C6A.F1 to       R5C5C.CE PHI2_N_114_enable_1 (to PHI2_c)
+                  --------
+                    1.455   (23.4% logic, 76.6% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_98:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R2C3A.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to      R5C5C.CLK PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            395 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i11  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i12  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_72 to SLICE_72 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_72 to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C7A.CLK to       R5C7A.Q0 SLICE_72 (from RCLK_c)
+ROUTE         1     0.161       R5C7A.Q0 to       R5C7A.M1 n702 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C7A.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C7A.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i12  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i13  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_72 to SLICE_90 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_72 to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C7A.CLK to       R5C7A.Q1 SLICE_72 (from RCLK_c)
+ROUTE         1     0.161       R5C7A.Q1 to       R5C7C.M0 n701 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C7A.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C7C.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i7  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i8  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_73 to SLICE_73 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_73 to SLICE_73:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R9C8A.CLK to       R9C8A.Q0 SLICE_73 (from RCLK_c)
+ROUTE         1     0.161       R9C8A.Q0 to       R9C8A.M1 n706 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_73:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R9C8A.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_73:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R9C8A.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i3  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i4  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_74 to SLICE_74 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_74 to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C6C.CLK to       R5C6C.Q0 SLICE_74 (from RCLK_c)
+ROUTE         1     0.161       R5C6C.Q0 to       R5C6C.M1 n710 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C6C.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C6C.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i6  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i7  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_75 to SLICE_73 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_75 to SLICE_73:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R9C8D.CLK to       R9C8D.Q1 SLICE_75 (from RCLK_c)
+ROUTE         1     0.161       R9C8D.Q1 to       R9C8A.M0 n707 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R9C8D.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_73:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R9C8A.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i5  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i6  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_75 to SLICE_75 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_75 to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R9C8D.CLK to       R9C8D.Q0 SLICE_75 (from RCLK_c)
+ROUTE         1     0.161       R9C8D.Q0 to       R9C8D.M1 n708 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R9C8D.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R9C8D.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              PHI2r_349  (from RCLK_c +)
+   Destination:    FF         Data in        PHI2r2_350  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_85 to SLICE_78 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_85 to SLICE_78:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157     R10C8C.CLK to      R10C8C.Q1 SLICE_85 (from RCLK_c)
+ROUTE         1     0.161      R10C8C.Q1 to      R10C8D.M1 PHI2r (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to     R10C8C.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_78:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to     R10C8D.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i2  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i3  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_87 to SLICE_74 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_87 to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C6B.CLK to       R5C6B.Q1 SLICE_87 (from RCLK_c)
+ROUTE         1     0.161       R5C6B.Q1 to       R5C6C.M0 n711 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_87:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C6B.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C6C.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.339ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i13  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i14  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_90 to SLICE_90 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_90 to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C7C.CLK to       R5C7C.Q0 SLICE_90 (from RCLK_c)
+ROUTE         1     0.161       R5C7C.Q0 to       R5C7C.M1 n700 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C7C.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to      R5C7C.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.345ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              PHI2r2_350  (from RCLK_c +)
+   Destination:    FF         Data in        PHI2r3_351  (to RCLK_c +)
+
+   Delay:               0.324ns  (48.5% logic, 51.5% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.324ns physical path delay SLICE_78 to SLICE_85 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.345ns
+
+ Physical Path Details:
+
+      Data path SLICE_78 to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157     R10C8D.CLK to      R10C8D.Q1 SLICE_78 (from RCLK_c)
+ROUTE         3     0.167      R10C8D.Q1 to      R10C8C.M0 PHI2r2 (to RCLK_c)
+                  --------
+                    0.324   (48.5% logic, 51.5% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_78:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to     R10C8D.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to     R10C8C.CLK RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.949ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_373  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_55 and
+      1.462ns delay SLICE_55 to RA[10] (totaling 1.949ns) meets
+      0.000ns hold offset RCLK to RA[10] by 1.949ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C5A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_55 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C5A.CLK to       R2C5A.Q0 SLICE_55 (from RCLK_c)
+ROUTE         1     0.197       R2C5A.Q0 to       87.PADDO n980
+DOPAD_DEL   ---     1.108       87.PADDO to         87.PAD RA[10]
+                  --------
+                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    1.949ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.668ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     2.181ns  (62.2% logic, 37.8% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.181ns delay SLICE_64 to RA[9] (totaling 2.668ns) meets
+      0.000ns hold offset RCLK to RA[9] by 2.668ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.199       R5C9A.Q0 to       R4C9A.D1 nRowColSel
+CTOF_DEL    ---     0.092       R4C9A.D1 to       R4C9A.F1 SLICE_88
+ROUTE         1     0.625       R4C9A.F1 to       85.PADDO RA_c_9
+DOPAD_DEL   ---     1.108       85.PADDO to         85.PAD RA[9]
+                  --------
+                    2.181   (62.2% logic, 37.8% route), 3 logic levels.
+
+Report:    2.668ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.689ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     2.202ns  (61.6% logic, 38.4% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.202ns delay SLICE_64 to RA[8] (totaling 2.689ns) meets
+      0.000ns hold offset RCLK to RA[8] by 2.689ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.451       R5C9A.Q0 to       R3C2B.D0 nRowColSel
+CTOF_DEL    ---     0.092       R3C2B.D0 to       R3C2B.F0 SLICE_95
+ROUTE         1     0.394       R3C2B.F0 to       96.PADDO RA_c_8
+DOPAD_DEL   ---     1.108       96.PADDO to         96.PAD RA[8]
+                  --------
+                    2.202   (61.6% logic, 38.4% route), 3 logic levels.
+
+Report:    2.689ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.572ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     2.085ns  (65.1% logic, 34.9% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.085ns delay SLICE_64 to RA[7] (totaling 2.572ns) meets
+      0.000ns hold offset RCLK to RA[7] by 2.572ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.531       R5C9A.Q0 to       R2C2A.C0 nRowColSel
+CTOF_DEL    ---     0.092       R2C2A.C0 to       R2C2A.F0 SLICE_97
+ROUTE         1     0.197       R2C2A.F0 to      100.PADDO RA_c_7
+DOPAD_DEL   ---     1.108      100.PADDO to        100.PAD RA[7]
+                  --------
+                    2.085   (65.1% logic, 34.9% route), 3 logic levels.
+
+Report:    2.572ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.652ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     2.165ns  (62.7% logic, 37.3% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.165ns delay SLICE_64 to RA[6] (totaling 2.652ns) meets
+      0.000ns hold offset RCLK to RA[6] by 2.652ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.452       R5C9A.Q0 to       R2C3A.D0 nRowColSel
+CTOF_DEL    ---     0.092       R2C3A.D0 to       R2C3A.F0 SLICE_98
+ROUTE         1     0.356       R2C3A.F0 to       91.PADDO RA_c_6
+DOPAD_DEL   ---     1.108       91.PADDO to         91.PAD RA[6]
+                  --------
+                    2.165   (62.7% logic, 37.3% route), 3 logic levels.
+
+Report:    2.652ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.652ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     2.165ns  (62.7% logic, 37.3% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.165ns delay SLICE_64 to RA[5] (totaling 2.652ns) meets
+      0.000ns hold offset RCLK to RA[5] by 2.652ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.452       R5C9A.Q0 to       R2C3A.D1 nRowColSel
+CTOF_DEL    ---     0.092       R2C3A.D1 to       R2C3A.F1 SLICE_98
+ROUTE         1     0.356       R2C3A.F1 to       95.PADDO RA_c_5
+DOPAD_DEL   ---     1.108       95.PADDO to         95.PAD RA[5]
+                  --------
+                    2.165   (62.7% logic, 37.3% route), 3 logic levels.
+
+Report:    2.652ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.776ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     2.289ns  (59.3% logic, 40.7% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.289ns delay SLICE_64 to RA[4] (totaling 2.776ns) meets
+      0.000ns hold offset RCLK to RA[4] by 2.776ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.178       R5C9A.Q0 to       R5C9A.D1 nRowColSel
+CTOF_DEL    ---     0.092       R5C9A.D1 to       R5C9A.F1 SLICE_64
+ROUTE         1     0.754       R5C9A.F1 to       99.PADDO RA_c_4
+DOPAD_DEL   ---     1.108       99.PADDO to         99.PAD RA[4]
+                  --------
+                    2.289   (59.3% logic, 40.7% route), 3 logic levels.
+
+Report:    2.776ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.772ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     2.285ns  (59.4% logic, 40.6% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.285ns delay SLICE_64 to RA[3] (totaling 2.772ns) meets
+      0.000ns hold offset RCLK to RA[3] by 2.772ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.571       R5C9A.Q0 to       R2C2C.D1 nRowColSel
+CTOF_DEL    ---     0.092       R2C2C.D1 to       R2C2C.F1 SLICE_94
+ROUTE         1     0.357       R2C2C.F1 to       97.PADDO RA_c_3
+DOPAD_DEL   ---     1.108       97.PADDO to         97.PAD RA[3]
+                  --------
+                    2.285   (59.4% logic, 40.6% route), 3 logic levels.
+
+Report:    2.772ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.787ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     2.300ns  (59.0% logic, 41.0% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.300ns delay SLICE_64 to RA[2] (totaling 2.787ns) meets
+      0.000ns hold offset RCLK to RA[2] by 2.787ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.451       R5C9A.Q0 to       R3C2B.D1 nRowColSel
+CTOF_DEL    ---     0.092       R3C2B.D1 to       R3C2B.F1 SLICE_95
+ROUTE         1     0.492       R3C2B.F1 to       94.PADDO RA_c_2
+DOPAD_DEL   ---     1.108       94.PADDO to         94.PAD RA[2]
+                  --------
+                    2.300   (59.0% logic, 41.0% route), 3 logic levels.
+
+Report:    2.787ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.855ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     2.368ns  (57.3% logic, 42.7% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.368ns delay SLICE_64 to RA[1] (totaling 2.855ns) meets
+      0.000ns hold offset RCLK to RA[1] by 2.855ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.531       R5C9A.Q0 to       R2C2C.C0 nRowColSel
+CTOF_DEL    ---     0.092       R2C2C.C0 to       R2C2C.F0 SLICE_94
+ROUTE         1     0.480       R2C2C.F0 to       89.PADDO RA_c_1
+DOPAD_DEL   ---     1.108       89.PADDO to         89.PAD RA[1]
+                  --------
+                    2.368   (57.3% logic, 42.7% route), 3 logic levels.
+
+Report:    2.855ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.893ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     2.406ns  (56.4% logic, 43.6% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.406ns delay SLICE_64 to RA[0] (totaling 2.893ns) meets
+      0.000ns hold offset RCLK to RA[0] by 2.893ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.310       R5C9A.Q0 to       R8C9C.D1 nRowColSel
+CTOF_DEL    ---     0.092       R8C9C.D1 to       R8C9C.F1 SLICE_92
+ROUTE         1     0.739       R8C9C.F1 to       98.PADDO RA_c_0
+DOPAD_DEL   ---     1.108       98.PADDO to         98.PAD RA[0]
+                  --------
+                    2.406   (56.4% logic, 43.6% route), 3 logic levels.
+
+Report:    2.893ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.949ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_369  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_60 and
+      1.462ns delay SLICE_60 to nRCS (totaling 1.949ns) meets
+      0.000ns hold offset RCLK to nRCS by 1.949ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C9C.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_60 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C9C.CLK to       R2C9C.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1     0.197       R2C9C.Q0 to       77.PADDO nRCS_c
+DOPAD_DEL   ---     1.108       77.PADDO to         77.PAD nRCS
+                  --------
+                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    1.949ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.949ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_368  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_34 and
+      1.462ns delay SLICE_34 to RCKE (totaling 1.949ns) meets
+      0.000ns hold offset RCLK to RCKE by 1.949ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C7C.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_34 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C7C.CLK to       R2C7C.Q0 SLICE_34 (from RCLK_c)
+ROUTE         4     0.197       R2C7C.Q0 to       82.PADDO RCKE_c
+DOPAD_DEL   ---     1.108       82.PADDO to         82.PAD RCKE
+                  --------
+                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    1.949ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.356ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_372  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     1.869ns  (67.7% logic, 32.3% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_63 and
+      1.869ns delay SLICE_63 to nRWE (totaling 2.356ns) meets
+      0.000ns hold offset RCLK to nRWE by 2.356ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to     R10C9C.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_63 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157     R10C9C.CLK to      R10C9C.Q0 SLICE_63 (from RCLK_c)
+ROUTE         1     0.604      R10C9C.Q0 to       72.PADDO nRWE_c
+DOPAD_DEL   ---     1.108       72.PADDO to         72.PAD nRWE
+                  --------
+                    1.869   (67.7% logic, 32.3% route), 2 logic levels.
+
+Report:    2.356ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.363ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     1.876ns  (67.4% logic, 32.6% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_61 and
+      1.876ns delay SLICE_61 to nRRAS (totaling 2.363ns) meets
+      0.000ns hold offset RCLK to nRRAS by 2.363ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R3C2A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_61 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R3C2A.CLK to       R3C2A.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2     0.611       R3C2A.Q0 to       73.PADDO nRRAS_c
+DOPAD_DEL   ---     1.108       73.PADDO to         73.PAD nRRAS
+                  --------
+                    1.876   (67.4% logic, 32.6% route), 2 logic levels.
+
+Report:    2.363ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.949ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_371  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_58 and
+      1.462ns delay SLICE_58 to nRCAS (totaling 1.949ns) meets
+      0.000ns hold offset RCLK to nRCAS by 1.949ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R2C9B.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_58 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C9B.CLK to       R2C9B.Q0 SLICE_58 (from RCLK_c)
+ROUTE         1     0.197       R2C9B.Q0 to       78.PADDO nRCAS_c
+DOPAD_DEL   ---     1.108       78.PADDO to         78.PAD nRCAS
+                  --------
+                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    1.949ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.523ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     2.036ns  (66.7% logic, 33.3% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.036ns delay SLICE_64 to RDQMH (totaling 2.523ns) meets
+      0.000ns hold offset RCLK to RDQMH by 2.523ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.199       R5C9A.Q0 to       R4C9A.D0 nRowColSel
+CTOF_DEL    ---     0.092       R4C9A.D0 to       R4C9A.F0 SLICE_88
+ROUTE         1     0.480       R4C9A.F0 to       76.PADDO RDQMH_c
+DOPAD_DEL   ---     1.108       76.PADDO to         76.PAD RDQMH
+                  --------
+                    2.036   (66.7% logic, 33.3% route), 3 logic levels.
+
+Report:    2.523ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.351ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     1.864ns  (72.8% logic, 27.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      1.864ns delay SLICE_64 to RDQML (totaling 2.351ns) meets
+      0.000ns hold offset RCLK to RDQML by 2.351ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.310       R5C9A.Q0 to       R8C9C.D0 nRowColSel
+CTOF_DEL    ---     0.092       R8C9C.D0 to       R8C9C.F0 SLICE_92
+ROUTE         1     0.197       R8C9C.F0 to       61.PADDO RDQML_c
+DOPAD_DEL   ---     1.108       61.PADDO to         61.PAD RDQML
+                  --------
+                    1.864   (72.8% logic, 27.2% route), 3 logic levels.
+
+Report:    2.351ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |            -|            -|   2  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |            -|            -|   1  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.668 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.689 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.572 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.652 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.652 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.776 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.772 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.787 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.855 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.893 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.356 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.363 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.523 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.351 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 526 paths, 6 nets, and 444 connections (71.84% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 0 (setup), 0 (hold)
+Score: 0 (setup), 0 (hold)
+Cumulative negative slack: 0 (0+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
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+
    
+
    
+
    
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+
    
+
    
+
    
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+
    
+
    
+
    
+
    
+
    
+
    
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+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
+
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_drc.log b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_drc.log
new file mode 100644
index 0000000..7932ec0
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_drc.log
@@ -0,0 +1,15 @@
+Results of NGD DRC are available in RAM2GS_drc.log.
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+
+
+Running DRC...
+
+DRC complete with no errors or warnings
+
+Design Results:
+    304 blocks expanded
+completed the first expansion
+All blocks are expanded and NGD expansion is successful.
+Writing NGD file RAM2GS_LCMXO640C_impl1.ngd.
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_lse.twr b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_lse.twr
new file mode 100644
index 0000000..0779fdc
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_lse.twr
@@ -0,0 +1,311 @@
+--------------------------------------------------------------------------------
+Lattice Synthesis Timing Report, Version  
+Mon Aug 16 21:33:30 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Design:     RAM2GS
+Constraint file:  
+Report level:    verbose report, limited to 3 items per constraint
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c]
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c]
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c]
+            122 items scored, 121 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error:  The following path violates requirements by 10.378ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i5  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdUFMCS_385  (to PHI2_c -)
+
+   Delay:                  12.614ns  (23.4% logic, 76.6% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.614ns data_path Bank_i5 to CmdUFMCS_385 violates
+      2.500ns delay constraint less
+      0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns
+
+ Path Details: Bank_i5 to CmdUFMCS_385
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              Bank_i5 (from PHI2_c)
+Route         1   e 1.220                                  Bank[5]
+LUT4        ---     0.390              B to Z              i1856_4_lut
+Route         1   e 1.220                                  n2166
+LUT4        ---     0.390              B to Z              i12_4_lut
+Route         1   e 1.220                                  n26
+LUT4        ---     0.390              B to Z              i13_4_lut
+Route         4   e 1.552                                  n1285
+LUT4        ---     0.390              B to Z              i1830_2_lut_rep_13
+Route         3   e 1.483                                  n2290
+LUT4        ---     0.390              D to Z              i3_4_lut
+Route         3   e 1.483                                  XOR8MEG_N_112
+LUT4        ---     0.390              A to Z              i2_3_lut_4_lut
+Route         3   e 1.483                                  PHI2_N_114_enable_7
+                  --------
+                   12.614  (23.4% logic, 76.6% route), 7 logic levels.
+
+
+Error:  The following path violates requirements by 10.378ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i5  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdUFMSDI_387  (to PHI2_c -)
+
+   Delay:                  12.614ns  (23.4% logic, 76.6% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.614ns data_path Bank_i5 to CmdUFMSDI_387 violates
+      2.500ns delay constraint less
+      0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns
+
+ Path Details: Bank_i5 to CmdUFMSDI_387
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              Bank_i5 (from PHI2_c)
+Route         1   e 1.220                                  Bank[5]
+LUT4        ---     0.390              B to Z              i1856_4_lut
+Route         1   e 1.220                                  n2166
+LUT4        ---     0.390              B to Z              i12_4_lut
+Route         1   e 1.220                                  n26
+LUT4        ---     0.390              B to Z              i13_4_lut
+Route         4   e 1.552                                  n1285
+LUT4        ---     0.390              B to Z              i1830_2_lut_rep_13
+Route         3   e 1.483                                  n2290
+LUT4        ---     0.390              D to Z              i3_4_lut
+Route         3   e 1.483                                  XOR8MEG_N_112
+LUT4        ---     0.390              A to Z              i2_3_lut_4_lut
+Route         3   e 1.483                                  PHI2_N_114_enable_7
+                  --------
+                   12.614  (23.4% logic, 76.6% route), 7 logic levels.
+
+
+Error:  The following path violates requirements by 10.378ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i5  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdUFMCLK_386  (to PHI2_c -)
+
+   Delay:                  12.614ns  (23.4% logic, 76.6% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.614ns data_path Bank_i5 to CmdUFMCLK_386 violates
+      2.500ns delay constraint less
+      0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns
+
+ Path Details: Bank_i5 to CmdUFMCLK_386
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              Bank_i5 (from PHI2_c)
+Route         1   e 1.220                                  Bank[5]
+LUT4        ---     0.390              B to Z              i1856_4_lut
+Route         1   e 1.220                                  n2166
+LUT4        ---     0.390              B to Z              i12_4_lut
+Route         1   e 1.220                                  n26
+LUT4        ---     0.390              B to Z              i13_4_lut
+Route         4   e 1.552                                  n1285
+LUT4        ---     0.390              B to Z              i1830_2_lut_rep_13
+Route         3   e 1.483                                  n2290
+LUT4        ---     0.390              D to Z              i3_4_lut
+Route         3   e 1.483                                  XOR8MEG_N_112
+LUT4        ---     0.390              A to Z              i2_3_lut_4_lut
+Route         3   e 1.483                                  PHI2_N_114_enable_7
+                  --------
+                   12.614  (23.4% logic, 76.6% route), 7 logic levels.
+
+Warning: 12.878 ns is the maximum delay for this constraint.
+
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c]
+            369 items scored, 244 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error:  The following path violates requirements by 6.291ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_577__i12  (from RCLK_c +)
+   Destination:    FD1P3AX    SP             LEDEN_392  (to RCLK_c +)
+
+   Delay:                  11.027ns  (23.2% logic, 76.8% route), 6 logic levels.
+
+ Constraint Details:
+
+     11.027ns data_path FS_577__i12 to LEDEN_392 violates
+      5.000ns delay constraint less
+      0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns
+
+ Path Details: FS_577__i12 to LEDEN_392
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              FS_577__i12 (from RCLK_c)
+Route         3   e 1.603                                  FS[12]
+LUT4        ---     0.390              C to Z              i4_4_lut
+Route         3   e 1.483                                  n10
+LUT4        ---     0.390              B to Z              i5_3_lut_rep_23
+Route         4   e 1.552                                  n2300
+LUT4        ---     0.390              B to Z              i4_3_lut_4_lut
+Route         1   e 1.220                                  n11
+LUT4        ---     0.390              C to Z              i2_4_lut_adj_4
+Route         2   e 1.386                                  n2119
+LUT4        ---     0.390              C to Z              i2_3_lut_3_lut
+Route         1   e 1.220                                  RCLK_c_enable_25
+                  --------
+                   11.027  (23.2% logic, 76.8% route), 6 logic levels.
+
+
+Error:  The following path violates requirements by 6.291ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_577__i12  (from RCLK_c +)
+   Destination:    FD1P3AX    SP             n8MEGEN_391  (to RCLK_c +)
+
+   Delay:                  11.027ns  (23.2% logic, 76.8% route), 6 logic levels.
+
+ Constraint Details:
+
+     11.027ns data_path FS_577__i12 to n8MEGEN_391 violates
+      5.000ns delay constraint less
+      0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns
+
+ Path Details: FS_577__i12 to n8MEGEN_391
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              FS_577__i12 (from RCLK_c)
+Route         3   e 1.603                                  FS[12]
+LUT4        ---     0.390              C to Z              i4_4_lut
+Route         3   e 1.483                                  n10
+LUT4        ---     0.390              B to Z              i5_3_lut_rep_23
+Route         4   e 1.552                                  n2300
+LUT4        ---     0.390              B to Z              i4_3_lut_4_lut
+Route         1   e 1.220                                  n11
+LUT4        ---     0.390              C to Z              i2_4_lut_adj_4
+Route         2   e 1.386                                  n2119
+LUT4        ---     0.390              D to Z              i1248_4_lut
+Route         1   e 1.220                                  RCLK_c_enable_7
+                  --------
+                   11.027  (23.2% logic, 76.8% route), 6 logic levels.
+
+
+Error:  The following path violates requirements by 6.291ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_577__i13  (from RCLK_c +)
+   Destination:    FD1P3AX    SP             LEDEN_392  (to RCLK_c +)
+
+   Delay:                  11.027ns  (23.2% logic, 76.8% route), 6 logic levels.
+
+ Constraint Details:
+
+     11.027ns data_path FS_577__i13 to LEDEN_392 violates
+      5.000ns delay constraint less
+      0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns
+
+ Path Details: FS_577__i13 to LEDEN_392
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              FS_577__i13 (from RCLK_c)
+Route         3   e 1.603                                  FS[13]
+LUT4        ---     0.390              B to Z              i4_4_lut
+Route         3   e 1.483                                  n10
+LUT4        ---     0.390              B to Z              i5_3_lut_rep_23
+Route         4   e 1.552                                  n2300
+LUT4        ---     0.390              B to Z              i4_3_lut_4_lut
+Route         1   e 1.220                                  n11
+LUT4        ---     0.390              C to Z              i2_4_lut_adj_4
+Route         2   e 1.386                                  n2119
+LUT4        ---     0.390              C to Z              i2_3_lut_3_lut
+Route         1   e 1.220                                  RCLK_c_enable_25
+                  --------
+                   11.027  (23.2% logic, 76.8% route), 6 logic levels.
+
+Warning: 11.291 ns is the maximum delay for this constraint.
+
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk1 [get_nets PHI2_c]                  |     5.000 ns|    25.756 ns|     7 *
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets RCLK_c]                  |     5.000 ns|    11.291 ns|     6 *
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+2 constraints not met.
+
+--------------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+--------------------------------------------------------------------------------
+n1285                                   |       4|     112|     30.68%
+                                        |        |        |
+n26                                     |       1|      70|     19.18%
+                                        |        |        |
+RCLK_c_enable_23                        |      16|      64|     17.53%
+                                        |        |        |
+n2290                                   |       3|      64|     17.53%
+                                        |        |        |
+XOR8MEG_N_112                           |       3|      54|     14.79%
+                                        |        |        |
+n2119                                   |       2|      48|     13.15%
+                                        |        |        |
+n2166                                   |       1|      42|     11.51%
+                                        |        |        |
+--------------------------------------------------------------------------------
+
+
+Timing summary:
+---------------
+
+Timing errors: 365  Score: 2309745
+
+Constraints cover  495 paths, 177 nets, and 464 connections (66.5% coverage)
+
+
+Peak memory: 52920320 bytes, TRCE: 1425408 bytes, DLYMAN: 163840 bytes
+CPU_TIME_REPORT: 0 secs 
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_lse_lsetwr.html b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_lse_lsetwr.html
new file mode 100644
index 0000000..93ec74e
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_lse_lsetwr.html
@@ -0,0 +1,376 @@
+
+Lattice Synthesis Timing Report
+
+
+
    Lattice Synthesis Timing Report
+--------------------------------------------------------------------------------
+Lattice Synthesis Timing Report, Version  
+Mon Aug 16 21:33:30 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Design:     RAM2GS
+Constraint file:  
+Report level:    verbose report, limited to 3 items per constraint
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c]
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c]
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c]
+            122 items scored, 121 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error:  The following path violates requirements by 10.378ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i5  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdUFMCS_385  (to PHI2_c -)
+
+   Delay:                  12.614ns  (23.4% logic, 76.6% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.614ns data_path Bank_i5 to CmdUFMCS_385 violates
+      2.500ns delay constraint less
+      0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns
+
+ Path Details: Bank_i5 to CmdUFMCS_385
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              Bank_i5 (from PHI2_c)
+Route         1   e 1.220                                  Bank[5]
+LUT4        ---     0.390              B to Z              i1856_4_lut
+Route         1   e 1.220                                  n2166
+LUT4        ---     0.390              B to Z              i12_4_lut
+Route         1   e 1.220                                  n26
+LUT4        ---     0.390              B to Z              i13_4_lut
+Route         4   e 1.552                                  n1285
+LUT4        ---     0.390              B to Z              i1830_2_lut_rep_13
+Route         3   e 1.483                                  n2290
+LUT4        ---     0.390              D to Z              i3_4_lut
+Route         3   e 1.483                                  XOR8MEG_N_112
+LUT4        ---     0.390              A to Z              i2_3_lut_4_lut
+Route         3   e 1.483                                  PHI2_N_114_enable_7
+                  --------
+                   12.614  (23.4% logic, 76.6% route), 7 logic levels.
+
+
+Error:  The following path violates requirements by 10.378ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i5  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdUFMSDI_387  (to PHI2_c -)
+
+   Delay:                  12.614ns  (23.4% logic, 76.6% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.614ns data_path Bank_i5 to CmdUFMSDI_387 violates
+      2.500ns delay constraint less
+      0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns
+
+ Path Details: Bank_i5 to CmdUFMSDI_387
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              Bank_i5 (from PHI2_c)
+Route         1   e 1.220                                  Bank[5]
+LUT4        ---     0.390              B to Z              i1856_4_lut
+Route         1   e 1.220                                  n2166
+LUT4        ---     0.390              B to Z              i12_4_lut
+Route         1   e 1.220                                  n26
+LUT4        ---     0.390              B to Z              i13_4_lut
+Route         4   e 1.552                                  n1285
+LUT4        ---     0.390              B to Z              i1830_2_lut_rep_13
+Route         3   e 1.483                                  n2290
+LUT4        ---     0.390              D to Z              i3_4_lut
+Route         3   e 1.483                                  XOR8MEG_N_112
+LUT4        ---     0.390              A to Z              i2_3_lut_4_lut
+Route         3   e 1.483                                  PHI2_N_114_enable_7
+                  --------
+                   12.614  (23.4% logic, 76.6% route), 7 logic levels.
+
+
+Error:  The following path violates requirements by 10.378ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i5  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdUFMCLK_386  (to PHI2_c -)
+
+   Delay:                  12.614ns  (23.4% logic, 76.6% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.614ns data_path Bank_i5 to CmdUFMCLK_386 violates
+      2.500ns delay constraint less
+      0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns
+
+ Path Details: Bank_i5 to CmdUFMCLK_386
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              Bank_i5 (from PHI2_c)
+Route         1   e 1.220                                  Bank[5]
+LUT4        ---     0.390              B to Z              i1856_4_lut
+Route         1   e 1.220                                  n2166
+LUT4        ---     0.390              B to Z              i12_4_lut
+Route         1   e 1.220                                  n26
+LUT4        ---     0.390              B to Z              i13_4_lut
+Route         4   e 1.552                                  n1285
+LUT4        ---     0.390              B to Z              i1830_2_lut_rep_13
+Route         3   e 1.483                                  n2290
+LUT4        ---     0.390              D to Z              i3_4_lut
+Route         3   e 1.483                                  XOR8MEG_N_112
+LUT4        ---     0.390              A to Z              i2_3_lut_4_lut
+Route         3   e 1.483                                  PHI2_N_114_enable_7
+                  --------
+                   12.614  (23.4% logic, 76.6% route), 7 logic levels.
+
+Warning: 12.878 ns is the maximum delay for this constraint.
+
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c]
+            369 items scored, 244 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error:  The following path violates requirements by 6.291ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_577__i12  (from RCLK_c +)
+   Destination:    FD1P3AX    SP             LEDEN_392  (to RCLK_c +)
+
+   Delay:                  11.027ns  (23.2% logic, 76.8% route), 6 logic levels.
+
+ Constraint Details:
+
+     11.027ns data_path FS_577__i12 to LEDEN_392 violates
+      5.000ns delay constraint less
+      0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns
+
+ Path Details: FS_577__i12 to LEDEN_392
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              FS_577__i12 (from RCLK_c)
+Route         3   e 1.603                                  FS[12]
+LUT4        ---     0.390              C to Z              i4_4_lut
+Route         3   e 1.483                                  n10
+LUT4        ---     0.390              B to Z              i5_3_lut_rep_23
+Route         4   e 1.552                                  n2300
+LUT4        ---     0.390              B to Z              i4_3_lut_4_lut
+Route         1   e 1.220                                  n11
+LUT4        ---     0.390              C to Z              i2_4_lut_adj_4
+Route         2   e 1.386                                  n2119
+LUT4        ---     0.390              C to Z              i2_3_lut_3_lut
+Route         1   e 1.220                                  RCLK_c_enable_25
+                  --------
+                   11.027  (23.2% logic, 76.8% route), 6 logic levels.
+
+
+Error:  The following path violates requirements by 6.291ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_577__i12  (from RCLK_c +)
+   Destination:    FD1P3AX    SP             n8MEGEN_391  (to RCLK_c +)
+
+   Delay:                  11.027ns  (23.2% logic, 76.8% route), 6 logic levels.
+
+ Constraint Details:
+
+     11.027ns data_path FS_577__i12 to n8MEGEN_391 violates
+      5.000ns delay constraint less
+      0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns
+
+ Path Details: FS_577__i12 to n8MEGEN_391
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              FS_577__i12 (from RCLK_c)
+Route         3   e 1.603                                  FS[12]
+LUT4        ---     0.390              C to Z              i4_4_lut
+Route         3   e 1.483                                  n10
+LUT4        ---     0.390              B to Z              i5_3_lut_rep_23
+Route         4   e 1.552                                  n2300
+LUT4        ---     0.390              B to Z              i4_3_lut_4_lut
+Route         1   e 1.220                                  n11
+LUT4        ---     0.390              C to Z              i2_4_lut_adj_4
+Route         2   e 1.386                                  n2119
+LUT4        ---     0.390              D to Z              i1248_4_lut
+Route         1   e 1.220                                  RCLK_c_enable_7
+                  --------
+                   11.027  (23.2% logic, 76.8% route), 6 logic levels.
+
+
+Error:  The following path violates requirements by 6.291ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_577__i13  (from RCLK_c +)
+   Destination:    FD1P3AX    SP             LEDEN_392  (to RCLK_c +)
+
+   Delay:                  11.027ns  (23.2% logic, 76.8% route), 6 logic levels.
+
+ Constraint Details:
+
+     11.027ns data_path FS_577__i13 to LEDEN_392 violates
+      5.000ns delay constraint less
+      0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns
+
+ Path Details: FS_577__i13 to LEDEN_392
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              FS_577__i13 (from RCLK_c)
+Route         3   e 1.603                                  FS[13]
+LUT4        ---     0.390              B to Z              i4_4_lut
+Route         3   e 1.483                                  n10
+LUT4        ---     0.390              B to Z              i5_3_lut_rep_23
+Route         4   e 1.552                                  n2300
+LUT4        ---     0.390              B to Z              i4_3_lut_4_lut
+Route         1   e 1.220                                  n11
+LUT4        ---     0.390              C to Z              i2_4_lut_adj_4
+Route         2   e 1.386                                  n2119
+LUT4        ---     0.390              C to Z              i2_3_lut_3_lut
+Route         1   e 1.220                                  RCLK_c_enable_25
+                  --------
+                   11.027  (23.2% logic, 76.8% route), 6 logic levels.
+
+Warning: 11.291 ns is the maximum delay for this constraint.
+
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk1 [get_nets PHI2_c]                  |     5.000 ns|    25.756 ns|     7 *
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets RCLK_c]                  |     5.000 ns|    11.291 ns|     6 *
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+2 constraints not met.
+
+--------------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+--------------------------------------------------------------------------------
+n1285                                   |       4|     112|     30.68%
+                                        |        |        |
+n26                                     |       1|      70|     19.18%
+                                        |        |        |
+RCLK_c_enable_23                        |      16|      64|     17.53%
+                                        |        |        |
+n2290                                   |       3|      64|     17.53%
+                                        |        |        |
+XOR8MEG_N_112                           |       3|      54|     14.79%
+                                        |        |        |
+n2119                                   |       2|      48|     13.15%
+                                        |        |        |
+n2166                                   |       1|      42|     11.51%
+                                        |        |        |
+--------------------------------------------------------------------------------
+
+
+Timing summary:
+---------------
+
+Timing errors: 365  Score: 2309745
+
+Constraints cover  495 paths, 177 nets, and 464 connections (66.5% coverage)
+
+
+Peak memory: 52920320 bytes, TRCE: 1425408 bytes, DLYMAN: 163840 bytes
+CPU_TIME_REPORT: 0 secs 
+
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diff --git a/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_prim.v b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_prim.v
new file mode 100644
index 0000000..9cec3ba
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_prim.v
@@ -0,0 +1,789 @@
+// Verilog netlist produced by program LSE :  version Diamond (64-bit) 3.12.0.240.2
+// Netlist written on Mon Aug 16 21:33:30 2021
+//
+// Verilog Description of module RAM2GS
+//
+
+module RAM2GS (PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, 
+            LED, RBA, RA, RD, nRCS, RCLK, RCKE, nRWE, nRRAS, 
+            nRCAS, RDQMH, RDQML, nUFMCS, UFMCLK, UFMSDI, UFMSDO) /* synthesis syn_module_defined=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(1[8:14])
+    input PHI2;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(8[8:12])
+    input [9:0]MAin;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
+    input [1:0]CROW;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(34[14:18])
+    input [7:0]Din;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17])
+    output [7:0]Dout;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
+    input nCCAS;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[8:13])
+    input nCRAS;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[15:20])
+    input nFWE;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(36[8:12])
+    output LED;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(12[9:12])
+    output [1:0]RBA;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(47[19:22])
+    output [11:0]RA;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
+    inout [7:0]RD;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16])
+    output nRCS;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[13:17])
+    input RCLK;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(41[8:12])
+    output RCKE;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(45[13:17])
+    output nRWE;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[45:49])
+    output nRRAS;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[23:28])
+    output nRCAS;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[34:39])
+    output RDQMH;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(56[16:21])
+    output RDQML;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(56[9:14])
+    output nUFMCS;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(63[13:19])
+    output UFMCLK;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(64[13:19])
+    output UFMSDI;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(65[13:19])
+    input UFMSDO;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(66[8:14])
+    
+    wire PHI2_c /* synthesis is_clock=1, SET_AS_NETWORK=PHI2_c */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(8[8:12])
+    wire nCCAS_c /* synthesis is_clock=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[8:13])
+    wire nCRAS_c /* synthesis is_clock=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[15:20])
+    wire RCLK_c /* synthesis SET_AS_NETWORK=RCLK_c, is_clock=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(41[8:12])
+    wire nCCAS_N_3 /* synthesis is_inv_clock=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
+    wire nCRAS_N_9 /* synthesis is_inv_clock=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(47[19:22])
+    wire PHI2_N_114 /* synthesis is_inv_clock=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(38[6:13])
+    
+    wire GND_net, VCC_net, LEDEN, PHI2r, PHI2r2, PHI2r3, RASr, 
+        RASr2, RASr3, CASr, CASr2, CASr3, FWEr, CBR, Din_c_7, 
+        Din_c_6, Din_c_5, Din_c_4, Din_c_3, Din_c_2, Din_c_1, Din_c_0, 
+        n2131, n33, PHI2_N_114_enable_2, n1;
+    wire [7:0]Bank;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(31[12:16])
+    
+    wire CROW_c_1, CROW_c_0, MAin_c_9, MAin_c_8, MAin_c_7, MAin_c_6, 
+        MAin_c_5, MAin_c_4, MAin_c_3, MAin_c_2, MAin_c_1, MAin_c_0, 
+        nFWE_c, n8MEGEN, XOR8MEG, RCKEEN, RCKE_c, nRCS_c, nRRAS_c, 
+        nRCAS_c, nRWE_c, RBA_c_1, RBA_c_0, nRowColSel, RA_c, n980;
+    wire [9:0]RowA;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(51[12:16])
+    
+    wire RA_c_9, RA_c_8, RA_c_7, RA_c_6, RA_c_5, RA_c_4, RA_c_3, 
+        RA_c_2, RA_c_1, RA_c_0, RDQML_c, RDQMH_c;
+    wire [7:0]WRD;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(59[12:15])
+    
+    wire nUFMCS_c, UFMCLK_c, UFMSDI_c, UFMSDO_c, C1Submitted, ADSubmitted, 
+        CmdEnable, CmdSubmitted, Cmdn8MEGEN, CmdUFMCLK, CmdUFMSDI, 
+        CmdUFMCS, InitReady, Ready;
+    wire [17:0]FS;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(86[13:15])
+    
+    wire LED_N_90, RA11_N_180, n2164, n1895, n2294, n4, PHI2_N_114_enable_6, 
+        n1881, RASr2_N_63, RCKE_N_128, nRowColSel_N_35, nRWE_N_178, 
+        RCKEEN_N_126, nRowColSel_N_34, nRowColSel_N_33, nRowColSel_N_32, 
+        nRowColSel_N_28, n1880, n4_adj_1, n2286, RCKEEN_N_117, nRWE_N_174, 
+        RCKEEN_N_116, nRCS_N_135, nRCAS_N_161, nRWE_N_173, nRWE_N_172, 
+        n1377, Ready_N_272, n2287, n26, Ready_N_268, nRCS_N_132, 
+        nRCAS_N_157, nRWE_N_167, RCKEEN_N_115, n2290, n2289, n1361, 
+        n1369, ADSubmitted_N_234, CmdEnable_N_236, C1Submitted_N_225, 
+        XOR8MEG_N_112, n2098, PHI2_N_114_enable_1, n2248, Cmdn8MEGEN_N_248, 
+        RCLK_c_enable_7, n2244, n2117, LEDEN_N_88, RCLK_c_enable_6, 
+        UFMSDO_N_74, n2243, RCLK_c_enable_24, n8MEGEN_N_94, UFMCLK_N_212, 
+        UFMSDI_N_219, n2242, n2114, n2080, PHI2_N_114_enable_7, n12, 
+        n699, n700, n701, n702, n703, n705, n706, n707, n708, 
+        n709, n710, n711, n11, n2076, n2119, n1368, n12_adj_2, 
+        n1878, PHI2_N_114_enable_8, n2308, n2291, n2307, n11_adj_3, 
+        n973, n1135, n78, n79, n80, n81, n82, n83, n84, n85, 
+        n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, 
+        n1348, n50, n1877, RCLK_c_enable_23, n1876, n1875, n2293, 
+        n2306, RCLK_c_enable_4, n2170, RCLK_c_enable_25, RCLK_c_enable_3, 
+        n2128, n2103, n2304, n2386, n1879, n1874, n2310, n974, 
+        n975, n962, n976, n2168, n977, n2245, n978, n2122, n979, 
+        Dout_c, n2166, n2302, n2108, n2301, n2387, n1285, n2300, 
+        n1628, n1627, n2299, n18, n2385, n2309, n2298, n2292, 
+        n2297, n2154, n10, n2296, n2295;
+    
+    VHI i2 (.Z(VCC_net));
+    INV i1963 (.A(nCCAS_c), .Z(nCCAS_N_3));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[8:13])
+    FD1S3AX PHI2r2_350 (.D(PHI2r), .CK(RCLK_c), .Q(PHI2r2));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
+    defparam PHI2r2_350.GSR = "ENABLED";
+    ORCALUT4 i2_3_lut_4_lut (.A(XOR8MEG_N_112), .B(n2298), .C(n2296), 
+            .D(Din_c_5), .Z(PHI2_N_114_enable_7)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ;
+    defparam i2_3_lut_4_lut.init = 16'h0800;
+    ORCALUT4 i1_2_lut_3_lut (.A(FS[11]), .B(n2300), .C(InitReady), .Z(n4)) /* synthesis lut_function=((B+(C))+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37])
+    defparam i1_2_lut_3_lut.init = 16'hfdfd;
+    FD1S3AX PHI2r3_351 (.D(PHI2r2), .CK(RCLK_c), .Q(PHI2r3));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
+    defparam PHI2r3_351.GSR = "ENABLED";
+    FD1S3AX RASr_352 (.D(nCRAS_N_9), .CK(RCLK_c), .Q(RASr));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
+    defparam RASr_352.GSR = "ENABLED";
+    FD1S3AX RASr2_353 (.D(RASr), .CK(RCLK_c), .Q(RASr2));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
+    defparam RASr2_353.GSR = "ENABLED";
+    FD1S3AX RASr3_354 (.D(RASr2), .CK(RCLK_c), .Q(RASr3));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
+    defparam RASr3_354.GSR = "ENABLED";
+    FD1S3AX CASr_355 (.D(nCCAS_N_3), .CK(RCLK_c), .Q(CASr));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
+    defparam CASr_355.GSR = "ENABLED";
+    FD1S3AX CASr2_356 (.D(CASr), .CK(RCLK_c), .Q(CASr2));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
+    defparam CASr2_356.GSR = "ENABLED";
+    FD1S3AX CASr3_357 (.D(CASr2), .CK(RCLK_c), .Q(CASr3));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
+    defparam CASr3_357.GSR = "ENABLED";
+    FD1S3IX RA11_358 (.D(RA11_N_180), .CK(PHI2_c), .CD(n2307), .Q(RA_c));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5])
+    defparam RA11_358.GSR = "ENABLED";
+    FD1S3IX RowA_i0 (.D(MAin_c_0), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[0]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
+    defparam RowA_i0.GSR = "ENABLED";
+    FD1S3AX WRD_i0 (.D(Din_c_0), .CK(nCCAS_N_3), .Q(WRD[0]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5])
+    defparam WRD_i0.GSR = "ENABLED";
+    FD1S3AX FWEr_362 (.D(n2306), .CK(nCRAS_N_9), .Q(FWEr));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
+    defparam FWEr_362.GSR = "ENABLED";
+    FD1S3AX CBR_363 (.D(nCCAS_N_3), .CK(nCRAS_N_9), .Q(CBR));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
+    defparam CBR_363.GSR = "ENABLED";
+    FD1S3IX ADSubmitted_380 (.D(n1361), .CK(PHI2_N_114), .CD(C1Submitted_N_225), 
+            .Q(ADSubmitted)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5])
+    defparam ADSubmitted_380.GSR = "ENABLED";
+    ORCALUT4 MAin_9__I_0_400_i5_3_lut (.A(RowA[4]), .B(MAin_c_4), .C(nRowColSel), 
+            .Z(RA_c_4)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
+    defparam MAin_9__I_0_400_i5_3_lut.init = 16'hcaca;
+    ORCALUT4 i1_2_lut (.A(FS[10]), .B(n2076), .Z(RCLK_c_enable_6)) /* synthesis lut_function=(A (B)) */ ;
+    defparam i1_2_lut.init = 16'h8888;
+    CCU2 FS_577_add_4_10 (.A0(FS[8]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
+         .A1(FS[9]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1877), 
+         .COUT1(n1878), .S0(n87), .S1(n86));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577_add_4_10.INIT0 = 16'hfaaa;
+    defparam FS_577_add_4_10.INIT1 = 16'hfaaa;
+    defparam FS_577_add_4_10.INJECT1_0 = "NO";
+    defparam FS_577_add_4_10.INJECT1_1 = "NO";
+    FD1S3AX RCKE_368 (.D(RCKE_N_128), .CK(RCLK_c), .Q(RCKE_c)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(141[9] 144[5])
+    defparam RCKE_368.GSR = "ENABLED";
+    FD1P3AY nRCS_369 (.D(nRCS_N_132), .SP(RCLK_c_enable_4), .CK(RCLK_c), 
+            .Q(nRCS_c)) /* synthesis lse_init_val=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
+    defparam nRCS_369.GSR = "ENABLED";
+    FD1S3IX nRowColSel_375 (.D(n1368), .CK(RCLK_c), .CD(n2299), .Q(nRowColSel));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
+    defparam nRowColSel_375.GSR = "ENABLED";
+    ORCALUT4 n1_bdd_4_lut (.A(n1), .B(n1627), .C(nRWE_N_178), .D(nRowColSel_N_35), 
+            .Z(nRWE_N_174)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))+!A (C+!(D))) */ ;
+    defparam n1_bdd_4_lut.init = 16'hf0dd;
+    ORCALUT4 i2_3_lut_rep_31 (.A(PHI2r3), .B(CmdSubmitted), .C(PHI2r2), 
+            .Z(n2308)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ;
+    defparam i2_3_lut_rep_31.init = 16'h0808;
+    ORCALUT4 i1_2_lut_2_lut_4_lut (.A(PHI2r3), .B(CmdSubmitted), .C(PHI2r2), 
+            .D(InitReady), .Z(RCLK_c_enable_24)) /* synthesis lut_function=(!(A (B (C (D))+!B (D))+!A (D))) */ ;
+    defparam i1_2_lut_2_lut_4_lut.init = 16'h08ff;
+    CCU2 FS_577_add_4_8 (.A0(FS[6]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
+         .A1(FS[7]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1876), 
+         .COUT1(n1877), .S0(n89), .S1(n88));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577_add_4_8.INIT0 = 16'hfaaa;
+    defparam FS_577_add_4_8.INIT1 = 16'hfaaa;
+    defparam FS_577_add_4_8.INJECT1_0 = "NO";
+    defparam FS_577_add_4_8.INJECT1_1 = "NO";
+    ORCALUT4 i1_4_lut (.A(nRowColSel_N_34), .B(n1), .C(n2304), .D(nRowColSel_N_33), 
+            .Z(n2117)) /* synthesis lut_function=(!(A+(B (C (D))+!B (C+!(D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(84[6:11])
+    defparam i1_4_lut.init = 16'h0544;
+    ORCALUT4 i3_4_lut (.A(MAin_c_1), .B(MAin_c_0), .C(CmdEnable), .D(n2290), 
+            .Z(XOR8MEG_N_112)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ;
+    defparam i3_4_lut.init = 16'h0040;
+    ORCALUT4 i4_3_lut_4_lut (.A(FS[11]), .B(n2300), .C(FS[6]), .D(n2168), 
+            .Z(n11)) /* synthesis lut_function=((B+(C+!(D)))+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37])
+    defparam i4_3_lut_4_lut.init = 16'hfdff;
+    FD1S3IX S_FSM_i2 (.D(n1135), .CK(RCLK_c), .CD(n2302), .Q(nRowColSel_N_34));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
+    defparam S_FSM_i2.GSR = "ENABLED";
+    ORCALUT4 i1_4_lut_adj_1 (.A(nRowColSel), .B(n1627), .C(nRowColSel_N_28), 
+            .D(nRowColSel_N_32), .Z(n1368)) /* synthesis lut_function=(A (B+!(C (D)))+!A (B+!(C+!(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
+    defparam i1_4_lut_adj_1.init = 16'hcfee;
+    FD1S3AY nRRAS_370 (.D(n33), .CK(RCLK_c), .Q(nRRAS_c)) /* synthesis lse_init_val=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
+    defparam nRRAS_370.GSR = "ENABLED";
+    ORCALUT4 i1055_3_lut_4_lut (.A(MAin_c_1), .B(n2290), .C(ADSubmitted), 
+            .D(ADSubmitted_N_234), .Z(n1361)) /* synthesis lut_function=(A (B (C+(D))+!B (D))+!A (C+(D))) */ ;
+    defparam i1055_3_lut_4_lut.init = 16'hffd0;
+    ORCALUT4 i2_3_lut (.A(FWEr), .B(CASr3), .C(CBR), .Z(nRowColSel_N_28)) /* synthesis lut_function=((B+(C))+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(230[16:37])
+    defparam i2_3_lut.init = 16'hfdfd;
+    BB Dout_pad_7__688 (.I(WRD[7]), .T(n962), .B(RD[7]), .O(n973));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16])
+    FD1P3AY nRCAS_371 (.D(nRCAS_N_157), .SP(RCLK_c_enable_4), .CK(RCLK_c), 
+            .Q(nRCAS_c)) /* synthesis lse_init_val=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
+    defparam nRCAS_371.GSR = "ENABLED";
+    FD1P3AY nRWE_372 (.D(nRWE_N_167), .SP(RCLK_c_enable_3), .CK(RCLK_c), 
+            .Q(nRWE_c)) /* synthesis lse_init_val=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
+    defparam nRWE_372.GSR = "ENABLED";
+    FD1S3JX RA10_373 (.D(n2128), .CK(RCLK_c), .PD(nRWE_N_172), .Q(n980));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
+    defparam RA10_373.GSR = "ENABLED";
+    FD1P3AX RCKEEN_374 (.D(RCKEEN_N_115), .SP(RCLK_c_enable_4), .CK(RCLK_c), 
+            .Q(RCKEEN));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
+    defparam RCKEEN_374.GSR = "ENABLED";
+    ORCALUT4 i2_4_lut (.A(n2122), .B(n2295), .C(Din_c_2), .D(n2131), 
+            .Z(C1Submitted_N_225)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ;
+    defparam i2_4_lut.init = 16'h0008;
+    FD1S3IX RBA__i1 (.D(CROW_c_0), .CK(nCRAS_N_9), .CD(n2307), .Q(RBA_c_0));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
+    defparam RBA__i1.GSR = "ENABLED";
+    ORCALUT4 Din_7__I_0_442_i6_2_lut_rep_32 (.A(Din_c_6), .B(Din_c_7), .Z(n2385)) /* synthesis lut_function=(A+(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(312[17:31])
+    defparam Din_7__I_0_442_i6_2_lut_rep_32.init = 16'heeee;
+    ORCALUT4 i1248_4_lut (.A(FS[5]), .B(n2308), .C(InitReady), .D(n2119), 
+            .Z(RCLK_c_enable_7)) /* synthesis lut_function=(A (B (C))+!A (B (C+(D))+!B !(C+!(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(83[6:15])
+    defparam i1248_4_lut.init = 16'hc5c0;
+    ORCALUT4 i2_3_lut_4_lut_adj_2 (.A(nRowColSel_N_32), .B(n2299), .C(nRowColSel_N_34), 
+            .D(nRowColSel_N_33), .Z(RCLK_c_enable_4)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
+    defparam i2_3_lut_4_lut_adj_2.init = 16'hfffe;
+    ORCALUT4 i1437_4_lut (.A(UFMSDO_c), .B(Cmdn8MEGEN), .C(FS[10]), .D(n4), 
+            .Z(n8MEGEN_N_94)) /* synthesis lut_function=(A (B ((D)+!C))+!A (B+!((D)+!C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(83[6:15])
+    defparam i1437_4_lut.init = 16'hcc5c;
+    FD1P3AX IS_FSM__i0 (.D(Ready_N_272), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
+            .Q(nRCS_N_135));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
+    defparam IS_FSM__i0.GSR = "ENABLED";
+    ORCALUT4 i1_2_lut_adj_3 (.A(RASr2), .B(RCKE_c), .Z(nRWE_N_178)) /* synthesis lut_function=(A+!(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
+    defparam i1_2_lut_adj_3.init = 16'hbbbb;
+    ORCALUT4 i2_4_lut_adj_4 (.A(n2294), .B(FS[10]), .C(n11), .D(n12), 
+            .Z(n2119)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37])
+    defparam i2_4_lut_adj_4.init = 16'h0008;
+    FD1P3JX C1Submitted_379 (.D(n2386), .SP(PHI2_N_114_enable_1), .PD(C1Submitted_N_225), 
+            .CK(PHI2_N_114), .Q(C1Submitted)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5])
+    defparam C1Submitted_379.GSR = "ENABLED";
+    FD1S3JX nUFMCS_388 (.D(n1348), .CK(RCLK_c), .PD(LEDEN_N_88), .Q(nUFMCS_c)) /* synthesis lse_init_val=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5])
+    defparam nUFMCS_388.GSR = "ENABLED";
+    ORCALUT4 m1_lut (.Z(n2387)) /* synthesis lut_function=1, syn_instantiated=1 */ ;
+    defparam m1_lut.init = 16'hffff;
+    ORCALUT4 i2_4_lut_adj_5 (.A(n2108), .B(MAin_c_1), .C(C1Submitted), 
+            .D(MAin_c_0), .Z(n2098)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ;
+    defparam i2_4_lut_adj_5.init = 16'h0800;
+    ORCALUT4 i5_4_lut (.A(FS[9]), .B(FS[4]), .C(FS[8]), .D(FS[7]), .Z(n12)) /* synthesis lut_function=(A+((C+(D))+!B)) */ ;
+    defparam i5_4_lut.init = 16'hfffb;
+    FD1S3AX FS_577__i0 (.D(n95), .CK(RCLK_c), .Q(FS[0])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577__i0.GSR = "ENABLED";
+    ORCALUT4 i2_3_lut_adj_6 (.A(n2122), .B(ADSubmitted), .C(MAin_c_0), 
+            .Z(n2080)) /* synthesis lut_function=(!((B+(C))+!A)) */ ;
+    defparam i2_3_lut_adj_6.init = 16'h0202;
+    ORCALUT4 i1419_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQMH_c)) /* synthesis lut_function=(A+!(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(58[17:46])
+    defparam i1419_2_lut.init = 16'hbbbb;
+    ORCALUT4 n50_bdd_4_lut_1911 (.A(n50), .B(RASr2), .C(RCKE_c), .D(nRowColSel_N_35), 
+            .Z(n2242)) /* synthesis lut_function=(!(A (B (D)+!B (C (D)))+!A (B+(C+!(D))))) */ ;
+    defparam n50_bdd_4_lut_1911.init = 16'h03aa;
+    ORCALUT4 i1893_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQML_c)) /* synthesis lut_function=(!(A (B))) */ ;
+    defparam i1893_2_lut.init = 16'h7777;
+    FD1S3AX Bank_i0 (.D(Din_c_0), .CK(PHI2_c), .Q(Bank[0]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5])
+    defparam Bank_i0.GSR = "ENABLED";
+    ORCALUT4 i1858_4_lut (.A(FS[1]), .B(FS[0]), .C(FS[2]), .D(FS[3]), 
+            .Z(n2168)) /* synthesis lut_function=(A (B (C (D)))) */ ;
+    defparam i1858_4_lut.init = 16'h8000;
+    ORCALUT4 i1_2_lut_3_lut_adj_7 (.A(MAin_c_1), .B(n1285), .C(MAin_c_0), 
+            .Z(n2131)) /* synthesis lut_function=((B+(C))+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(80[15:31])
+    defparam i1_2_lut_3_lut_adj_7.init = 16'hfdfd;
+    ORCALUT4 i22_4_lut (.A(FS[4]), .B(CmdUFMCLK), .C(InitReady), .D(n2076), 
+            .Z(UFMCLK_N_212)) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(83[6:15])
+    defparam i22_4_lut.init = 16'hc0ca;
+    ORCALUT4 i5_4_lut_adj_8 (.A(FS[14]), .B(FS[16]), .C(FS[13]), .D(FS[12]), 
+            .Z(n12_adj_2)) /* synthesis lut_function=(A (B (C (D)))) */ ;
+    defparam i5_4_lut_adj_8.init = 16'h8000;
+    ORCALUT4 i1889_4_lut_then_4_lut (.A(n2117), .B(RCKE_c), .C(RASr2), 
+            .D(nRowColSel_N_35), .Z(n2310)) /* synthesis lut_function=(!(A (B+(C+!(D)))+!A (B (D)+!B (C (D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(84[6:11])
+    defparam i1889_4_lut_then_4_lut.init = 16'h0355;
+    ORCALUT4 i1889_4_lut_else_4_lut (.A(InitReady), .B(nRCS_N_135), .C(RASr2), 
+            .D(nRowColSel_N_35), .Z(n2309)) /* synthesis lut_function=((B+!(C (D)))+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(84[6:11])
+    defparam i1889_4_lut_else_4_lut.init = 16'hdfff;
+    CCU2 FS_577_add_4_18 (.A0(FS[16]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
+         .A1(FS[17]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1881), 
+         .S0(n79), .S1(n78));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577_add_4_18.INIT0 = 16'hfaaa;
+    defparam FS_577_add_4_18.INIT1 = 16'hfaaa;
+    defparam FS_577_add_4_18.INJECT1_0 = "NO";
+    defparam FS_577_add_4_18.INJECT1_1 = "NO";
+    ORCALUT4 UFMSDO_I_0_1_lut (.A(UFMSDO_c), .Z(UFMSDO_N_74)) /* synthesis lut_function=(!(A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(378[53:60])
+    defparam UFMSDO_I_0_1_lut.init = 16'h5555;
+    FD1S3IX S_FSM_i3 (.D(n1135), .CK(RCLK_c), .CD(n1377), .Q(nRowColSel_N_33));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
+    defparam S_FSM_i3.GSR = "ENABLED";
+    ORCALUT4 i1897_2_lut_rep_14_3_lut (.A(FS[11]), .B(n2300), .C(InitReady), 
+            .Z(n2291)) /* synthesis lut_function=(!(A+(B+(C)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37])
+    defparam i1897_2_lut_rep_14_3_lut.init = 16'h0101;
+    ORCALUT4 i1878_2_lut_3_lut_4_lut (.A(FS[11]), .B(n2300), .C(FS[10]), 
+            .D(InitReady), .Z(LEDEN_N_88)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37])
+    defparam i1878_2_lut_3_lut_4_lut.init = 16'h0001;
+    ORCALUT4 i1884_4_lut (.A(MAin_c_0), .B(n2290), .C(n2286), .D(MAin_c_1), 
+            .Z(PHI2_N_114_enable_8)) /* synthesis lut_function=(!(A (B+(C))+!A (B+(C+!(D))))) */ ;
+    defparam i1884_4_lut.init = 16'h0302;
+    FD1S3AX PHI2r_349 (.D(PHI2_c), .CK(RCLK_c), .Q(PHI2r));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
+    defparam PHI2r_349.GSR = "ENABLED";
+    ORCALUT4 i2_3_lut_rep_21_4_lut (.A(Din_c_6), .B(Din_c_7), .C(Din_c_5), 
+            .D(Din_c_4), .Z(n2298)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(312[17:31])
+    defparam i2_3_lut_rep_21_4_lut.init = 16'hfffe;
+    ORCALUT4 i1830_2_lut_rep_13 (.A(nFWE_c), .B(n1285), .Z(n2290)) /* synthesis lut_function=(A+(B)) */ ;
+    defparam i1830_2_lut_rep_13.init = 16'heeee;
+    PFUMX i1912 (.BLUT(n2243), .ALUT(n2242), .C0(Ready), .Z(n2244));
+    FD1S3AX S_FSM_i1 (.D(RASr2_N_63), .CK(RCLK_c), .Q(nRowColSel_N_35));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
+    defparam S_FSM_i1.GSR = "ENABLED";
+    ORCALUT4 i1886_2_lut (.A(nRowColSel_N_32), .B(RASr2), .Z(n1135)) /* synthesis lut_function=(!(A+!(B))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
+    defparam i1886_2_lut.init = 16'h4444;
+    ORCALUT4 n50_bdd_4_lut (.A(n50), .B(InitReady), .C(RASr2), .D(nRowColSel_N_35), 
+            .Z(n2243)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B (C)))) */ ;
+    defparam n50_bdd_4_lut.init = 16'h3fbf;
+    ORCALUT4 i1034_2_lut (.A(ADSubmitted_N_234), .B(C1Submitted_N_225), 
+            .Z(CmdEnable_N_236)) /* synthesis lut_function=(A+(B)) */ ;
+    defparam i1034_2_lut.init = 16'heeee;
+    ORCALUT4 i2_3_lut_4_lut_adj_9 (.A(Din_c_6), .B(Din_c_7), .C(XOR8MEG_N_112), 
+            .D(Din_c_4), .Z(PHI2_N_114_enable_6)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(312[17:31])
+    defparam i2_3_lut_4_lut_adj_9.init = 16'h1000;
+    ORCALUT4 i1832_2_lut_rep_19_3_lut (.A(Din_c_6), .B(Din_c_7), .C(Din_c_4), 
+            .Z(n2296)) /* synthesis lut_function=(A+(B+!(C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(312[17:31])
+    defparam i1832_2_lut_rep_19_3_lut.init = 16'hefef;
+    FD1S3IX S_FSM_i4 (.D(n1628), .CK(RCLK_c), .CD(RASr2_N_63), .Q(nRowColSel_N_32));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
+    defparam S_FSM_i4.GSR = "ENABLED";
+    ORCALUT4 i1424_2_lut_rep_27 (.A(FWEr), .B(CBR), .Z(n2304)) /* synthesis lut_function=(A+(B)) */ ;
+    defparam i1424_2_lut_rep_27.init = 16'heeee;
+    ORCALUT4 i2_3_lut_adj_10 (.A(Din_c_3), .B(Din_c_6), .C(Din_c_5), .Z(n2122)) /* synthesis lut_function=(!(A+((C)+!B))) */ ;
+    defparam i2_3_lut_adj_10.init = 16'h0404;
+    ORCALUT4 i1429_2_lut_3_lut (.A(FWEr), .B(CBR), .C(RASr2), .Z(RCKEEN_N_126)) /* synthesis lut_function=(!(A (C)+!A (B (C)))) */ ;
+    defparam i1429_2_lut_3_lut.init = 16'h1f1f;
+    ORCALUT4 i4_4_lut (.A(FS[14]), .B(FS[13]), .C(FS[12]), .D(FS[15]), 
+            .Z(n10)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37])
+    defparam i4_4_lut.init = 16'hfffe;
+    ORCALUT4 i5_3_lut_rep_23 (.A(FS[16]), .B(n10), .C(FS[17]), .Z(n2300)) /* synthesis lut_function=(A+(B+(C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37])
+    defparam i5_3_lut_rep_23.init = 16'hfefe;
+    ORCALUT4 i1_4_lut_adj_11 (.A(n2244), .B(n2297), .C(n18), .D(Ready), 
+            .Z(n33)) /* synthesis lut_function=(A+(B (C+!(D))+!B (C (D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(84[6:11])
+    defparam i1_4_lut_adj_11.init = 16'hfaee;
+    ORCALUT4 i1_2_lut_rep_16_4_lut (.A(FS[16]), .B(n10), .C(FS[17]), .D(FS[11]), 
+            .Z(n2293)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37])
+    defparam i1_2_lut_rep_16_4_lut.init = 16'hfeff;
+    ORCALUT4 i3_4_lut_adj_12 (.A(CBR), .B(FWEr), .C(CASr2), .D(CASr3), 
+            .Z(n1)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ;
+    defparam i3_4_lut_adj_12.init = 16'h0040;
+    ORCALUT4 i1_2_lut_adj_13 (.A(nRowColSel_N_34), .B(nRowColSel_N_33), 
+            .Z(n1627)) /* synthesis lut_function=(A+(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
+    defparam i1_2_lut_adj_13.init = 16'heeee;
+    ORCALUT4 i1420_2_lut (.A(nCCAS_c), .B(nFWE_c), .Z(n962)) /* synthesis lut_function=(A+(B)) */ ;
+    defparam i1420_2_lut.init = 16'heeee;
+    ORCALUT4 i1_1_lut_rep_29 (.A(nFWE_c), .Z(n2306)) /* synthesis lut_function=(!(A)) */ ;
+    defparam i1_1_lut_rep_29.init = 16'h5555;
+    ORCALUT4 Cmdn8MEGEN_I_84_4_lut (.A(Din_c_0), .B(n8MEGEN), .C(Din_c_5), 
+            .D(n2296), .Z(Cmdn8MEGEN_N_248)) /* synthesis lut_function=(A (B (C+(D)))+!A (B+!(C+(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(316[13] 322[7])
+    defparam Cmdn8MEGEN_I_84_4_lut.init = 16'hccc5;
+    ORCALUT4 i1069_1_lut (.A(nRowColSel_N_34), .Z(n1377)) /* synthesis lut_function=(!(A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
+    defparam i1069_1_lut.init = 16'h5555;
+    ORCALUT4 n2080_bdd_4_lut (.A(n2080), .B(n2098), .C(Din_c_2), .D(n2114), 
+            .Z(n2286)) /* synthesis lut_function=(A (B (D)+!B !(C+!(D)))+!A (B (C (D)))) */ ;
+    defparam n2080_bdd_4_lut.init = 16'hca00;
+    ORCALUT4 RASr2_I_0_1_lut (.A(RASr2), .Z(RASr2_N_63)) /* synthesis lut_function=(!(A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(143[40:46])
+    defparam RASr2_I_0_1_lut.init = 16'h5555;
+    ORCALUT4 i847_2_lut_4_lut (.A(n2385), .B(Din_c_4), .C(Din_c_5), .D(XOR8MEG_N_112), 
+            .Z(PHI2_N_114_enable_2)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(310[8:22])
+    defparam i847_2_lut_4_lut.init = 16'h0100;
+    ORCALUT4 i1_4_lut_adj_14 (.A(n2108), .B(MAin_c_0), .C(n4_adj_1), .D(n2289), 
+            .Z(ADSubmitted_N_234)) /* synthesis lut_function=(!((((D)+!C)+!B)+!A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(309[7:24])
+    defparam i1_4_lut_adj_14.init = 16'h0080;
+    ORCALUT4 i1_2_lut_adj_15 (.A(nRowColSel_N_33), .B(CASr2), .Z(n11_adj_3)) /* synthesis lut_function=(A+!(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(48[6:16])
+    defparam i1_2_lut_adj_15.init = 16'hbbbb;
+    FD1S3AX FS_577__i17 (.D(n78), .CK(RCLK_c), .Q(FS[17])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577__i17.GSR = "ENABLED";
+    ORCALUT4 i1_2_lut_3_lut_3_lut (.A(nFWE_c), .B(Din_c_2), .C(n2114), 
+            .Z(n4_adj_1)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;
+    defparam i1_2_lut_3_lut_3_lut.init = 16'h4040;
+    FD1S3AX FS_577__i16 (.D(n79), .CK(RCLK_c), .Q(FS[16])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577__i16.GSR = "ENABLED";
+    FD1S3AX FS_577__i15 (.D(n80), .CK(RCLK_c), .Q(FS[15])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577__i15.GSR = "ENABLED";
+    ORCALUT4 nRWE_I_0_428_4_lut (.A(n2164), .B(nRWE_N_174), .C(Ready), 
+            .D(n2292), .Z(nRWE_N_167)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B+!(C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(232[12] 284[6])
+    defparam nRWE_I_0_428_4_lut.init = 16'hcfc5;
+    ORCALUT4 i1257_3_lut (.A(n1895), .B(CmdUFMSDI), .C(InitReady), .Z(UFMSDI_N_219)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(83[6:15])
+    defparam i1257_3_lut.init = 16'hcaca;
+    ORCALUT4 RCKE_I_0_423_4_lut (.A(RASr), .B(RCKEEN), .C(RASr2), .D(RASr3), 
+            .Z(RCKE_N_128)) /* synthesis lut_function=(A (B+!(C+!(D)))+!A (B (C+(D))+!B !(C+!(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(143[11:55])
+    defparam RCKE_I_0_423_4_lut.init = 16'hcfc8;
+    FD1P3AX InitReady_367 (.D(n2387), .SP(RCLK_c_enable_6), .CK(RCLK_c), 
+            .Q(InitReady)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(134[9] 138[5])
+    defparam InitReady_367.GSR = "ENABLED";
+    ORCALUT4 i1_2_lut_adj_16 (.A(nRowColSel_N_32), .B(nRowColSel_N_33), 
+            .Z(n1628)) /* synthesis lut_function=(A+(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
+    defparam i1_2_lut_adj_16.init = 16'heeee;
+    ORCALUT4 i1854_2_lut (.A(nRCAS_N_161), .B(nRWE_N_173), .Z(n2164)) /* synthesis lut_function=(A+(B)) */ ;
+    defparam i1854_2_lut.init = 16'heeee;
+    ORCALUT4 i1_2_lut_rep_17_4_lut (.A(FS[16]), .B(n10), .C(FS[17]), .D(FS[11]), 
+            .Z(n2294)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37])
+    defparam i1_2_lut_rep_17_4_lut.init = 16'hfffe;
+    ORCALUT4 i1881_2_lut_rep_24 (.A(RASr2), .B(InitReady), .Z(n2301)) /* synthesis lut_function=(!(A (B))) */ ;
+    defparam i1881_2_lut_rep_24.init = 16'h7777;
+    GSR GSR_INST (.GSR(VCC_net));
+    ORCALUT4 i1_2_lut_rep_18_2_lut (.A(nFWE_c), .B(n2114), .Z(n2295)) /* synthesis lut_function=(!(A+!(B))) */ ;
+    defparam i1_2_lut_rep_18_2_lut.init = 16'h4444;
+    FD1S3AX FS_577__i14 (.D(n81), .CK(RCLK_c), .Q(FS[14])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577__i14.GSR = "ENABLED";
+    ORCALUT4 i2_3_lut_3_lut (.A(InitReady), .B(FS[5]), .C(n2119), .Z(RCLK_c_enable_25)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(384[16:26])
+    defparam i2_3_lut_3_lut.init = 16'h4040;
+    ORCALUT4 i2_3_lut_adj_17 (.A(Din_c_6), .B(Din_c_5), .C(Din_c_3), .Z(n2108)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(309[7:24])
+    defparam i2_3_lut_adj_17.init = 16'h4040;
+    ORCALUT4 i2_4_lut_adj_18 (.A(FS[6]), .B(n2293), .C(n2103), .D(FS[10]), 
+            .Z(n1895)) /* synthesis lut_function=(!((B+((D)+!C))+!A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam i2_4_lut_adj_18.init = 16'h0020;
+    ORCALUT4 i1_4_lut_adj_19 (.A(FS[8]), .B(FS[7]), .C(FS[5]), .D(FS[9]), 
+            .Z(n2103)) /* synthesis lut_function=(!(A+(B (D)+!B !(C (D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(339[4] 372[11])
+    defparam i1_4_lut_adj_19.init = 16'h1044;
+    FD1P3AX XOR8MEG_381 (.D(Din_c_0), .SP(PHI2_N_114_enable_2), .CK(PHI2_N_114), 
+            .Q(XOR8MEG)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5])
+    defparam XOR8MEG_381.GSR = "ENABLED";
+    FD1P3AX n8MEGEN_391 (.D(n8MEGEN_N_94), .SP(RCLK_c_enable_7), .CK(RCLK_c), 
+            .Q(n8MEGEN)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5])
+    defparam n8MEGEN_391.GSR = "ENABLED";
+    FD1P3AX Ready_377 (.D(n2387), .SP(Ready_N_268), .CK(RCLK_c), .Q(Ready)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
+    defparam Ready_377.GSR = "ENABLED";
+    ORCALUT4 MAin_9__I_0_400_i2_3_lut (.A(RowA[1]), .B(MAin_c_1), .C(nRowColSel), 
+            .Z(RA_c_1)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
+    defparam MAin_9__I_0_400_i2_3_lut.init = 16'hcaca;
+    FD1P3AX CmdUFMCLK_386 (.D(Din_c_1), .SP(PHI2_N_114_enable_7), .CK(PHI2_N_114), 
+            .Q(CmdUFMCLK)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5])
+    defparam CmdUFMCLK_386.GSR = "ENABLED";
+    FD1P3AX CmdUFMSDI_387 (.D(Din_c_0), .SP(PHI2_N_114_enable_7), .CK(PHI2_N_114), 
+            .Q(CmdUFMSDI)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5])
+    defparam CmdUFMSDI_387.GSR = "ENABLED";
+    FD1P3AX Cmdn8MEGEN_383 (.D(Cmdn8MEGEN_N_248), .SP(PHI2_N_114_enable_6), 
+            .CK(PHI2_N_114), .Q(Cmdn8MEGEN)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5])
+    defparam Cmdn8MEGEN_383.GSR = "ENABLED";
+    FD1P3AX CmdSubmitted_384 (.D(n2387), .SP(PHI2_N_114_enable_6), .CK(PHI2_N_114), 
+            .Q(CmdSubmitted)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5])
+    defparam CmdSubmitted_384.GSR = "ENABLED";
+    CCU2 FS_577_add_4_6 (.A0(FS[4]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
+         .A1(FS[5]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1875), 
+         .COUT1(n1876), .S0(n91), .S1(n90));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577_add_4_6.INIT0 = 16'hfaaa;
+    defparam FS_577_add_4_6.INIT1 = 16'hfaaa;
+    defparam FS_577_add_4_6.INJECT1_0 = "NO";
+    defparam FS_577_add_4_6.INJECT1_1 = "NO";
+    FD1P3AX CmdUFMCS_385 (.D(Din_c_2), .SP(PHI2_N_114_enable_7), .CK(PHI2_N_114), 
+            .Q(CmdUFMCS)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5])
+    defparam CmdUFMCS_385.GSR = "ENABLED";
+    FD1S3AX FS_577__i13 (.D(n82), .CK(RCLK_c), .Q(FS[13])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577__i13.GSR = "ENABLED";
+    ORCALUT4 i1875_2_lut (.A(nCRAS_c), .B(LEDEN), .Z(LED_N_90)) /* synthesis lut_function=(A+!(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(13[15:34])
+    defparam i1875_2_lut.init = 16'hbbbb;
+    FD1S3AX FS_577__i12 (.D(n83), .CK(RCLK_c), .Q(FS[12])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577__i12.GSR = "ENABLED";
+    PFUMX RCKEEN_I_0_419 (.BLUT(RCKEEN_N_117), .ALUT(RCKEEN_N_126), .C0(nRowColSel_N_35), 
+          .Z(RCKEEN_N_116));
+    ORCALUT4 i1856_4_lut (.A(Bank[0]), .B(Bank[5]), .C(MAin_c_2), .D(Bank[6]), 
+            .Z(n2166)) /* synthesis lut_function=(A (B (C (D)))) */ ;
+    defparam i1856_4_lut.init = 16'h8000;
+    FD1S3AX FS_577__i11 (.D(n84), .CK(RCLK_c), .Q(FS[11])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577__i11.GSR = "ENABLED";
+    ORCALUT4 i1844_2_lut (.A(Bank[7]), .B(MAin_c_4), .Z(n2154)) /* synthesis lut_function=(A (B)) */ ;
+    defparam i1844_2_lut.init = 16'h8888;
+    ORCALUT4 RA11_I_53_3_lut (.A(Din_c_6), .B(XOR8MEG), .C(n8MEGEN), .Z(RA11_N_180)) /* synthesis lut_function=(A (B (C)+!B !(C))+!A (B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(99[22:51])
+    defparam RA11_I_53_3_lut.init = 16'hc6c6;
+    ORCALUT4 Ready_bdd_3_lut_1922 (.A(nRCAS_N_161), .B(nRCS_N_135), .C(InitReady), 
+            .Z(n2248)) /* synthesis lut_function=(A+(B+!(C))) */ ;
+    defparam Ready_bdd_3_lut_1922.init = 16'hefef;
+    FD1P3IX UFMSDI_390 (.D(UFMSDI_N_219), .SP(RCLK_c_enable_24), .CD(n2291), 
+            .CK(RCLK_c), .Q(UFMSDI_c)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5])
+    defparam UFMSDI_390.GSR = "ENABLED";
+    ORCALUT4 MAin_9__I_0_400_i10_3_lut (.A(RowA[9]), .B(MAin_c_9), .C(nRowColSel), 
+            .Z(RA_c_9)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
+    defparam MAin_9__I_0_400_i10_3_lut.init = 16'hcaca;
+    ORCALUT4 i604_1_lut_rep_30 (.A(Ready), .Z(n2307)) /* synthesis lut_function=(!(A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
+    defparam i604_1_lut_rep_30.init = 16'h5555;
+    FD1S3AX FS_577__i10 (.D(n85), .CK(RCLK_c), .Q(FS[10])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577__i10.GSR = "ENABLED";
+    FD1S3AX FS_577__i9 (.D(n86), .CK(RCLK_c), .Q(FS[9])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577__i9.GSR = "ENABLED";
+    FD1S3AX FS_577__i8 (.D(n87), .CK(RCLK_c), .Q(FS[8])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577__i8.GSR = "ENABLED";
+    FD1S3AX FS_577__i7 (.D(n88), .CK(RCLK_c), .Q(FS[7])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577__i7.GSR = "ENABLED";
+    FD1S3AX FS_577__i6 (.D(n89), .CK(RCLK_c), .Q(FS[6])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577__i6.GSR = "ENABLED";
+    FD1S3AX FS_577__i5 (.D(n90), .CK(RCLK_c), .Q(FS[5])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577__i5.GSR = "ENABLED";
+    FD1S3AX FS_577__i4 (.D(n91), .CK(RCLK_c), .Q(FS[4])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577__i4.GSR = "ENABLED";
+    FD1S3AX FS_577__i3 (.D(n92), .CK(RCLK_c), .Q(FS[3])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577__i3.GSR = "ENABLED";
+    FD1S3AX FS_577__i2 (.D(n93), .CK(RCLK_c), .Q(FS[2])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577__i2.GSR = "ENABLED";
+    FD1S3AX FS_577__i1 (.D(n94), .CK(RCLK_c), .Q(FS[1])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577__i1.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i15 (.D(n699), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
+            .Q(Ready_N_272));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
+    defparam IS_FSM__i15.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i14 (.D(n700), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
+            .Q(n699));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
+    defparam IS_FSM__i14.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i13 (.D(n701), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
+            .Q(n700));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
+    defparam IS_FSM__i13.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i12 (.D(n702), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
+            .Q(n701));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
+    defparam IS_FSM__i12.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i11 (.D(n703), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
+            .Q(n702));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
+    defparam IS_FSM__i11.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i10 (.D(nRWE_N_173), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
+            .Q(n703));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
+    defparam IS_FSM__i10.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i9 (.D(n705), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
+            .Q(nRWE_N_173));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
+    defparam IS_FSM__i9.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i8 (.D(n706), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
+            .Q(n705));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
+    defparam IS_FSM__i8.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i7 (.D(n707), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
+            .Q(n706));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
+    defparam IS_FSM__i7.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i6 (.D(n708), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
+            .Q(n707));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
+    defparam IS_FSM__i6.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i5 (.D(n709), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
+            .Q(n708));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
+    defparam IS_FSM__i5.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i4 (.D(n710), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
+            .Q(n709));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
+    defparam IS_FSM__i4.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i3 (.D(n711), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
+            .Q(n710));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
+    defparam IS_FSM__i3.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i2 (.D(nRCAS_N_161), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
+            .Q(n711));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
+    defparam IS_FSM__i2.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i1 (.D(nRCS_N_135), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
+            .Q(nRCAS_N_161));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
+    defparam IS_FSM__i1.GSR = "ENABLED";
+    FD1S3IX RBA__i2 (.D(CROW_c_1), .CK(nCRAS_N_9), .CD(n2307), .Q(RBA_c_1));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
+    defparam RBA__i2.GSR = "ENABLED";
+    FD1S3AX WRD_i7 (.D(Din_c_7), .CK(nCCAS_N_3), .Q(WRD[7]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5])
+    defparam WRD_i7.GSR = "ENABLED";
+    FD1S3AX WRD_i6 (.D(Din_c_6), .CK(nCCAS_N_3), .Q(WRD[6]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5])
+    defparam WRD_i6.GSR = "ENABLED";
+    FD1S3AX WRD_i5 (.D(Din_c_5), .CK(nCCAS_N_3), .Q(WRD[5]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5])
+    defparam WRD_i5.GSR = "ENABLED";
+    FD1S3AX WRD_i4 (.D(Din_c_4), .CK(nCCAS_N_3), .Q(WRD[4]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5])
+    defparam WRD_i4.GSR = "ENABLED";
+    FD1S3AX WRD_i3 (.D(Din_c_3), .CK(nCCAS_N_3), .Q(WRD[3]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5])
+    defparam WRD_i3.GSR = "ENABLED";
+    FD1S3AX WRD_i2 (.D(Din_c_2), .CK(nCCAS_N_3), .Q(WRD[2]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5])
+    defparam WRD_i2.GSR = "ENABLED";
+    FD1S3AX WRD_i1 (.D(Din_c_1), .CK(nCCAS_N_3), .Q(WRD[1]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5])
+    defparam WRD_i1.GSR = "ENABLED";
+    FD1S3JX RowA_i9 (.D(MAin_c_9), .CK(nCRAS_N_9), .PD(n2307), .Q(RowA[9]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
+    defparam RowA_i9.GSR = "ENABLED";
+    FD1S3IX RowA_i8 (.D(MAin_c_8), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[8]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
+    defparam RowA_i8.GSR = "ENABLED";
+    FD1S3IX RowA_i7 (.D(MAin_c_7), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[7]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
+    defparam RowA_i7.GSR = "ENABLED";
+    FD1S3IX RowA_i6 (.D(MAin_c_6), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[6]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
+    defparam RowA_i6.GSR = "ENABLED";
+    FD1S3JX RowA_i5 (.D(MAin_c_5), .CK(nCRAS_N_9), .PD(n2307), .Q(RowA[5]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
+    defparam RowA_i5.GSR = "ENABLED";
+    FD1S3IX RowA_i4 (.D(MAin_c_4), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[4]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
+    defparam RowA_i4.GSR = "ENABLED";
+    FD1S3IX RowA_i3 (.D(MAin_c_3), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[3]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
+    defparam RowA_i3.GSR = "ENABLED";
+    FD1S3IX RowA_i2 (.D(MAin_c_2), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[2]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
+    defparam RowA_i2.GSR = "ENABLED";
+    FD1S3IX RowA_i1 (.D(MAin_c_1), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[1]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
+    defparam RowA_i1.GSR = "ENABLED";
+    FD1S3AX Bank_i7 (.D(Din_c_7), .CK(PHI2_c), .Q(Bank[7]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5])
+    defparam Bank_i7.GSR = "ENABLED";
+    ORCALUT4 i1_2_lut_rep_12 (.A(MAin_c_1), .B(n1285), .Z(n2289)) /* synthesis lut_function=((B)+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(80[15:31])
+    defparam i1_2_lut_rep_12.init = 16'hdddd;
+    ORCALUT4 i1_2_lut_rep_15_3_lut_4_lut_4_lut (.A(nRowColSel_N_35), .B(nRCS_N_135), 
+            .C(InitReady), .D(RASr2), .Z(n2292)) /* synthesis lut_function=((B+!(C (D)))+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
+    defparam i1_2_lut_rep_15_3_lut_4_lut_4_lut.init = 16'hdfff;
+    ORCALUT4 i1_2_lut_4_lut_4_lut (.A(Ready), .B(nRowColSel_N_35), .C(RASr2), 
+            .D(InitReady), .Z(RCLK_c_enable_23)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
+    defparam i1_2_lut_4_lut_4_lut.init = 16'h4000;
+    FD1S3AX Bank_i6 (.D(Din_c_6), .CK(PHI2_c), .Q(Bank[6]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5])
+    defparam Bank_i6.GSR = "ENABLED";
+    FD1S3AX Bank_i5 (.D(Din_c_5), .CK(PHI2_c), .Q(Bank[5]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5])
+    defparam Bank_i5.GSR = "ENABLED";
+    FD1S3AX Bank_i4 (.D(Din_c_4), .CK(PHI2_c), .Q(Bank[4]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5])
+    defparam Bank_i4.GSR = "ENABLED";
+    FD1S3AX Bank_i3 (.D(Din_c_3), .CK(PHI2_c), .Q(Bank[3]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5])
+    defparam Bank_i3.GSR = "ENABLED";
+    FD1S3AX Bank_i2 (.D(Din_c_2), .CK(PHI2_c), .Q(Bank[2]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5])
+    defparam Bank_i2.GSR = "ENABLED";
+    FD1S3AX Bank_i1 (.D(Din_c_1), .CK(PHI2_c), .Q(Bank[1]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5])
+    defparam Bank_i1.GSR = "ENABLED";
+    BB Dout_pad_6__689 (.I(WRD[6]), .T(n962), .B(RD[6]), .O(n974));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16])
+    BB Dout_pad_5__690 (.I(WRD[5]), .T(n962), .B(RD[5]), .O(n975));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16])
+    BB Dout_pad_4__691 (.I(WRD[4]), .T(n962), .B(RD[4]), .O(n976));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16])
+    BB Dout_pad_3__692 (.I(WRD[3]), .T(n962), .B(RD[3]), .O(n977));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16])
+    BB Dout_pad_2__693 (.I(WRD[2]), .T(n962), .B(RD[2]), .O(n978));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16])
+    BB Dout_pad_1__694 (.I(WRD[1]), .T(n962), .B(RD[1]), .O(n979));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16])
+    ORCALUT4 nRWE_I_49_1_lut (.A(nRWE_N_173), .Z(nRWE_N_172)) /* synthesis lut_function=(!(A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(255[14] 262[8])
+    defparam nRWE_I_49_1_lut.init = 16'h5555;
+    BB Dout_pad_0__695 (.I(WRD[0]), .T(n962), .B(RD[0]), .O(Dout_c));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16])
+    OB Dout_pad_7 (.I(n973), .O(Dout[7]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
+    OB Dout_pad_6 (.I(n974), .O(Dout[6]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
+    OB Dout_pad_5 (.I(n975), .O(Dout[5]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
+    OB Dout_pad_4 (.I(n976), .O(Dout[4]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
+    OB Dout_pad_3 (.I(n977), .O(Dout[3]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
+    OB Dout_pad_2 (.I(n978), .O(Dout[2]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
+    OB Dout_pad_1 (.I(n979), .O(Dout[1]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
+    OB Dout_pad_0 (.I(Dout_c), .O(Dout[0]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
+    OB LED_pad (.I(LED_N_90), .O(LED));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(12[9:12])
+    OB RBA_pad_1 (.I(RBA_c_1), .O(RBA[1]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(47[19:22])
+    OB RBA_pad_0 (.I(RBA_c_0), .O(RBA[0]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(47[19:22])
+    OB RA_pad_11 (.I(RA_c), .O(RA[11]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
+    OB RA_pad_10 (.I(n980), .O(RA[10]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
+    OB RA_pad_9 (.I(RA_c_9), .O(RA[9]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
+    OB RA_pad_8 (.I(RA_c_8), .O(RA[8]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
+    OB RA_pad_7 (.I(RA_c_7), .O(RA[7]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
+    OB RA_pad_6 (.I(RA_c_6), .O(RA[6]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
+    OB RA_pad_5 (.I(RA_c_5), .O(RA[5]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
+    OB RA_pad_4 (.I(RA_c_4), .O(RA[4]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
+    OB RA_pad_3 (.I(RA_c_3), .O(RA[3]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
+    OB RA_pad_2 (.I(RA_c_2), .O(RA[2]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
+    OB RA_pad_1 (.I(RA_c_1), .O(RA[1]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
+    OB RA_pad_0 (.I(RA_c_0), .O(RA[0]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
+    OB nRCS_pad (.I(nRCS_c), .O(nRCS));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[13:17])
+    OB RCKE_pad (.I(RCKE_c), .O(RCKE));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(45[13:17])
+    OB nRWE_pad (.I(nRWE_c), .O(nRWE));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[45:49])
+    OB nRRAS_pad (.I(nRRAS_c), .O(nRRAS));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[23:28])
+    OB nRCAS_pad (.I(nRCAS_c), .O(nRCAS));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[34:39])
+    OB RDQMH_pad (.I(RDQMH_c), .O(RDQMH));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(56[16:21])
+    OB RDQML_pad (.I(RDQML_c), .O(RDQML));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(56[9:14])
+    OB nUFMCS_pad (.I(nUFMCS_c), .O(nUFMCS));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(63[13:19])
+    OB UFMCLK_pad (.I(UFMCLK_c), .O(UFMCLK));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(64[13:19])
+    OB UFMSDI_pad (.I(UFMSDI_c), .O(UFMSDI));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(65[13:19])
+    IB PHI2_pad (.I(PHI2), .O(PHI2_c));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(8[8:12])
+    IB MAin_pad_9 (.I(MAin[9]), .O(MAin_c_9));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
+    IB MAin_pad_8 (.I(MAin[8]), .O(MAin_c_8));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
+    IB MAin_pad_7 (.I(MAin[7]), .O(MAin_c_7));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
+    IB MAin_pad_6 (.I(MAin[6]), .O(MAin_c_6));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
+    IB MAin_pad_5 (.I(MAin[5]), .O(MAin_c_5));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
+    IB MAin_pad_4 (.I(MAin[4]), .O(MAin_c_4));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
+    IB MAin_pad_3 (.I(MAin[3]), .O(MAin_c_3));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
+    IB MAin_pad_2 (.I(MAin[2]), .O(MAin_c_2));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
+    IB MAin_pad_1 (.I(MAin[1]), .O(MAin_c_1));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
+    IB MAin_pad_0 (.I(MAin[0]), .O(MAin_c_0));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
+    IB CROW_pad_1 (.I(CROW[1]), .O(CROW_c_1));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(34[14:18])
+    IB CROW_pad_0 (.I(CROW[0]), .O(CROW_c_0));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(34[14:18])
+    IB Din_pad_7 (.I(Din[7]), .O(Din_c_7));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17])
+    IB Din_pad_6 (.I(Din[6]), .O(Din_c_6));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17])
+    IB Din_pad_5 (.I(Din[5]), .O(Din_c_5));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17])
+    IB Din_pad_4 (.I(Din[4]), .O(Din_c_4));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17])
+    IB Din_pad_3 (.I(Din[3]), .O(Din_c_3));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17])
+    IB Din_pad_2 (.I(Din[2]), .O(Din_c_2));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17])
+    IB Din_pad_1 (.I(Din[1]), .O(Din_c_1));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17])
+    IB Din_pad_0 (.I(Din[0]), .O(Din_c_0));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17])
+    IB nCCAS_pad (.I(nCCAS), .O(nCCAS_c));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[8:13])
+    IB nCRAS_pad (.I(nCRAS), .O(nCRAS_c));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[15:20])
+    IB nFWE_pad (.I(nFWE), .O(nFWE_c));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(36[8:12])
+    IB RCLK_pad (.I(RCLK), .O(RCLK_c));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(41[8:12])
+    IB UFMSDO_pad (.I(UFMSDO), .O(UFMSDO_c));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(66[8:14])
+    ORCALUT4 MAin_9__I_0_400_i9_3_lut (.A(RowA[8]), .B(MAin_c_8), .C(nRowColSel), 
+            .Z(RA_c_8)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
+    defparam MAin_9__I_0_400_i9_3_lut.init = 16'hcaca;
+    CCU2 FS_577_add_4_4 (.A0(FS[2]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
+         .A1(FS[3]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1874), 
+         .COUT1(n1875), .S0(n93), .S1(n92));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577_add_4_4.INIT0 = 16'hfaaa;
+    defparam FS_577_add_4_4.INIT1 = 16'hfaaa;
+    defparam FS_577_add_4_4.INJECT1_0 = "NO";
+    defparam FS_577_add_4_4.INJECT1_1 = "NO";
+    ORCALUT4 i1_2_lut_3_lut_4_lut_4_lut (.A(Ready), .B(nRowColSel_N_32), 
+            .C(n1627), .D(nRowColSel_N_35), .Z(RCLK_c_enable_3)) /* synthesis lut_function=((B+(C+(D)))+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
+    defparam i1_2_lut_3_lut_4_lut_4_lut.init = 16'hfffd;
+    FD1P3IX UFMCLK_389 (.D(UFMCLK_N_212), .SP(RCLK_c_enable_24), .CD(n2291), 
+            .CK(RCLK_c), .Q(UFMCLK_c)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5])
+    defparam UFMCLK_389.GSR = "ENABLED";
+    ORCALUT4 i2_2_lut_rep_22_2_lut (.A(Ready), .B(nRowColSel_N_35), .Z(n2299)) /* synthesis lut_function=((B)+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
+    defparam i2_2_lut_rep_22_2_lut.init = 16'hdddd;
+    ORCALUT4 i2_3_lut_4_lut_adj_20 (.A(n2297), .B(n2301), .C(nRCAS_N_161), 
+            .D(Ready), .Z(n2128)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
+    defparam i2_3_lut_4_lut_adj_20.init = 16'hfffe;
+    ORCALUT4 i2_3_lut_adj_21 (.A(nRowColSel_N_33), .B(nRRAS_c), .C(nRowColSel_N_32), 
+            .Z(n50)) /* synthesis lut_function=(A+(B+(C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
+    defparam i2_3_lut_adj_21.init = 16'hfefe;
+    ORCALUT4 MAin_9__I_0_400_i8_3_lut (.A(RowA[7]), .B(MAin_c_7), .C(nRowColSel), 
+            .Z(RA_c_7)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
+    defparam MAin_9__I_0_400_i8_3_lut.init = 16'hcaca;
+    ORCALUT4 Ready_bdd_4_lut (.A(Ready), .B(n2117), .C(n2287), .D(nRowColSel_N_35), 
+            .Z(nRCAS_N_157)) /* synthesis lut_function=(A (B (C (D))+!B (C+!(D)))+!A (C+!(D))) */ ;
+    defparam Ready_bdd_4_lut.init = 16'hf077;
+    ORCALUT4 i1366_3_lut (.A(InitReady), .B(RCKEEN_N_116), .C(Ready), 
+            .Z(RCKEEN_N_115)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(84[6:11])
+    defparam i1366_3_lut.init = 16'hcaca;
+    ORCALUT4 i6_4_lut (.A(FS[15]), .B(n12_adj_2), .C(FS[11]), .D(FS[17]), 
+            .Z(n2076)) /* synthesis lut_function=(A (B (C (D)))) */ ;
+    defparam i6_4_lut.init = 16'h8000;
+    ORCALUT4 i1_4_lut_4_lut (.A(CBR), .B(n11_adj_3), .C(FWEr), .D(nRowColSel_N_34), 
+            .Z(RCKEEN_N_117)) /* synthesis lut_function=(!(A+!(B (C+(D))+!B (D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(214[26:30])
+    defparam i1_4_lut_4_lut.init = 16'h5540;
+    ORCALUT4 i1_2_lut_rep_11_3_lut (.A(nFWE_c), .B(n1285), .C(MAin_c_1), 
+            .Z(PHI2_N_114_enable_1)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ;
+    defparam i1_2_lut_rep_11_3_lut.init = 16'h1010;
+    CCU2 FS_577_add_4_2 (.A0(FS[0]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
+         .A1(FS[1]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(GND_net), 
+         .COUT1(n1874), .S0(n95), .S1(n94));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577_add_4_2.INIT0 = 16'h0555;
+    defparam FS_577_add_4_2.INIT1 = 16'hfaaa;
+    defparam FS_577_add_4_2.INJECT1_0 = "NO";
+    defparam FS_577_add_4_2.INJECT1_1 = "NO";
+    ORCALUT4 i3_4_lut_adj_22 (.A(Din_c_0), .B(Din_c_1), .C(Din_c_4), .D(Din_c_7), 
+            .Z(n2114)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ;
+    defparam i3_4_lut_adj_22.init = 16'h0200;
+    ORCALUT4 Ready_bdd_4_lut_1960 (.A(nRowColSel_N_32), .B(RASr2), .C(Ready_N_272), 
+            .D(InitReady), .Z(n2245)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ;
+    defparam Ready_bdd_4_lut_1960.init = 16'h2000;
+    ORCALUT4 n2245_bdd_2_lut (.A(n2245), .B(Ready), .Z(Ready_N_268)) /* synthesis lut_function=(A+(B)) */ ;
+    defparam n2245_bdd_2_lut.init = 16'heeee;
+    ORCALUT4 n2248_bdd_4_lut_4_lut (.A(CBR), .B(RASr2), .C(Ready), .D(n2248), 
+            .Z(n2287)) /* synthesis lut_function=(!(A (B (C+!(D)))+!A !((C+(D))+!B))) */ ;
+    defparam n2248_bdd_4_lut_4_lut.init = 16'h7f73;
+    FD1P3AX LEDEN_392 (.D(UFMSDO_N_74), .SP(RCLK_c_enable_25), .CK(RCLK_c), 
+            .Q(LEDEN)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5])
+    defparam LEDEN_392.GSR = "ENABLED";
+    ORCALUT4 MAin_9__I_0_400_i7_3_lut (.A(RowA[6]), .B(MAin_c_6), .C(nRowColSel), 
+            .Z(RA_c_6)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
+    defparam MAin_9__I_0_400_i7_3_lut.init = 16'hcaca;
+    ORCALUT4 MAin_9__I_0_400_i6_3_lut (.A(RowA[5]), .B(MAin_c_5), .C(nRowColSel), 
+            .Z(RA_c_5)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
+    defparam MAin_9__I_0_400_i6_3_lut.init = 16'hcaca;
+    CCU2 FS_577_add_4_12 (.A0(FS[10]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
+         .A1(FS[11]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1878), 
+         .COUT1(n1879), .S0(n85), .S1(n84));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577_add_4_12.INIT0 = 16'hfaaa;
+    defparam FS_577_add_4_12.INIT1 = 16'hfaaa;
+    defparam FS_577_add_4_12.INJECT1_0 = "NO";
+    defparam FS_577_add_4_12.INJECT1_1 = "NO";
+    FD1P3AX CmdEnable_378 (.D(CmdEnable_N_236), .SP(PHI2_N_114_enable_8), 
+            .CK(PHI2_N_114), .Q(CmdEnable)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5])
+    defparam CmdEnable_378.GSR = "ENABLED";
+    CCU2 FS_577_add_4_16 (.A0(FS[14]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
+         .A1(FS[15]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1880), 
+         .COUT1(n1881), .S0(n81), .S1(n80));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577_add_4_16.INIT0 = 16'hfaaa;
+    defparam FS_577_add_4_16.INIT1 = 16'hfaaa;
+    defparam FS_577_add_4_16.INJECT1_0 = "NO";
+    defparam FS_577_add_4_16.INJECT1_1 = "NO";
+    CCU2 FS_577_add_4_14 (.A0(FS[12]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
+         .A1(FS[13]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1879), 
+         .COUT1(n1880), .S0(n83), .S1(n82));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
+    defparam FS_577_add_4_14.INIT0 = 16'hfaaa;
+    defparam FS_577_add_4_14.INIT1 = 16'hfaaa;
+    defparam FS_577_add_4_14.INJECT1_0 = "NO";
+    defparam FS_577_add_4_14.INJECT1_1 = "NO";
+    ORCALUT4 MAin_9__I_0_400_i3_3_lut (.A(RowA[2]), .B(MAin_c_2), .C(nRowColSel), 
+            .Z(RA_c_2)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
+    defparam MAin_9__I_0_400_i3_3_lut.init = 16'hcaca;
+    ORCALUT4 i1485_3_lut (.A(n2076), .B(n1369), .C(InitReady), .Z(n1348)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(83[6:15])
+    defparam i1485_3_lut.init = 16'hcaca;
+    ORCALUT4 i1_2_lut_2_lut (.A(nRowColSel_N_35), .B(nRowColSel_N_34), .Z(n18)) /* synthesis lut_function=(!(A+!(B))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
+    defparam i1_2_lut_2_lut.init = 16'h4444;
+    ORCALUT4 i1_2_lut_rep_20_2_lut (.A(nRowColSel_N_35), .B(nRCS_N_135), 
+            .Z(n2297)) /* synthesis lut_function=((B)+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
+    defparam i1_2_lut_rep_20_2_lut.init = 16'hdddd;
+    ORCALUT4 i1062_3_lut (.A(nUFMCS_c), .B(CmdUFMCS), .C(n2308), .Z(n1369)) /* synthesis lut_function=(!(A (B (C))+!A (B+!(C)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5])
+    defparam i1062_3_lut.init = 16'h3a3a;
+    ORCALUT4 MAin_9__I_0_400_i4_3_lut (.A(RowA[3]), .B(MAin_c_3), .C(nRowColSel), 
+            .Z(RA_c_3)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
+    defparam MAin_9__I_0_400_i4_3_lut.init = 16'hcaca;
+    ORCALUT4 MAin_9__I_0_400_i1_3_lut (.A(RowA[0]), .B(MAin_c_0), .C(nRowColSel), 
+            .Z(RA_c_0)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
+    defparam MAin_9__I_0_400_i1_3_lut.init = 16'hcaca;
+    INV i1961 (.A(nCRAS_c), .Z(nCRAS_N_9));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[15:20])
+    INV i1962 (.A(PHI2_c), .Z(PHI2_N_114));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(8[8:12])
+    VLO i1 (.Z(GND_net));
+    TSALL TSALL_INST (.TSALL(GND_net));
+    ORCALUT4 i1070_1_lut_rep_25 (.A(nRowColSel_N_35), .Z(n2302)) /* synthesis lut_function=(!(A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
+    defparam i1070_1_lut_rep_25.init = 16'h5555;
+    PUR PUR_INST (.PUR(VCC_net));
+    defparam PUR_INST.RST_PULSE = 1;
+    ORCALUT4 i13_4_lut (.A(Bank[3]), .B(n26), .C(n2170), .D(MAin_c_5), 
+            .Z(n1285)) /* synthesis lut_function=((B+!(C (D)))+!A) */ ;
+    defparam i13_4_lut.init = 16'hdfff;
+    ORCALUT4 i12_4_lut (.A(Bank[2]), .B(n2166), .C(n2154), .D(MAin_c_6), 
+            .Z(n26)) /* synthesis lut_function=(A+!(B (C (D)))) */ ;
+    defparam i12_4_lut.init = 16'hbfff;
+    ORCALUT4 i1860_4_lut (.A(MAin_c_7), .B(MAin_c_3), .C(Bank[4]), .D(Bank[1]), 
+            .Z(n2170)) /* synthesis lut_function=(A (B (C (D)))) */ ;
+    defparam i1860_4_lut.init = 16'h8000;
+    ORCALUT4 m0_lut (.Z(n2386)) /* synthesis lut_function=0, syn_instantiated=1 */ ;
+    defparam m0_lut.init = 16'h0000;
+    PFUMX i1934 (.BLUT(n2309), .ALUT(n2310), .C0(Ready), .Z(nRCS_N_132));
+    
+endmodule
+//
+// Verilog Description of module TSALL
+// module not written out since it is a black-box. 
+//
+
+//
+// Verilog Description of module PUR
+// module not written out since it is a black-box. 
+//
+
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/Untitled.tpf.prf b/CPLD/LCMXO/LCMXO640C/impl1/Untitled.tpf.prf
new file mode 100644
index 0000000..15d3b42
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/Untitled.tpf.prf
@@ -0,0 +1,89 @@
+PERIOD NET "PHI2_c" 350.000000 ns  ;
+PERIOD NET "nCCAS_c" 350.000000 ns  ;
+PERIOD NET "nCRAS_c" 350.000000 ns  ;
+PERIOD NET "RCLK_c" 16.000000 ns  ;
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+OUTPUT PORT "RD[7]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[0]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[1]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[2]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[3]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[4]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[5]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[6]" LOAD 20.000000 pF ;
+OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ;
+OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ;
+OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ;
+OUTPUT PORT "nRWE" LOAD 10.000000 pF ;
+OUTPUT PORT "nRCAS" LOAD 10.000000 pF ;
+OUTPUT PORT "nRCS" LOAD 10.000000 pF ;
+OUTPUT PORT "nRRAS" LOAD 10.000000 pF ;
+OUTPUT PORT "RDQML" LOAD 10.000000 pF ;
+OUTPUT PORT "RDQMH" LOAD 10.000000 pF ;
+OUTPUT PORT "RCKE" LOAD 10.000000 pF ;
+OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ;
+OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[11]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[10]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[9]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[8]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[7]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[6]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[5]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[4]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[3]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[2]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[1]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[0]" LOAD 10.000000 pF ;
+OUTPUT PORT "LED" LOAD 25.000000 pF ;
+OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ;
+VOLTAGE 3.300 V;
+VCCIO_DERATE BANK 0 PERCENT -5; 
+VCCIO_DERATE PERCENT -5; 
+VCCIO_DERATE BANK 1 PERCENT -5; 
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+COMMERCIAL ;
\ No newline at end of file
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/Untitled.tpf.prf_cdmp b/CPLD/LCMXO/LCMXO640C/impl1/Untitled.tpf.prf_cdmp
new file mode 100644
index 0000000..0f2c679
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/Untitled.tpf.prf_cdmp
@@ -0,0 +1,155 @@
+VOLTAGE 3.300 V;
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+IOBUF PORT "RD[7]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RD[6]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RD[5]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RD[4]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RD[3]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RD[2]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RD[1]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RD[0]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Dout[7]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Dout[6]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Dout[5]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Dout[4]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Dout[3]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Dout[2]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Dout[1]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Dout[0]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "LED" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RBA[1]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RBA[0]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[11]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[10]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[9]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[8]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[7]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[6]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[5]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[4]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[3]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[2]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[1]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[0]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "nRCS" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RCKE" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "nRWE" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "nRRAS" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "nRCAS" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RDQMH" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RDQML" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "nUFMCS" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "UFMCLK" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "UFMSDI" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "PHI2" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[9]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[8]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[7]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[6]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[5]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[4]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[3]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[2]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[1]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[0]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "CROW[1]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "CROW[0]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Din[7]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Din[6]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Din[5]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Din[4]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Din[3]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Din[2]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Din[1]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Din[0]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "nCCAS" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "nCRAS" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "nFWE" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RCLK" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "UFMSDO" IO_TYPE=LVCMOS25 ;
+PERIOD NET "PHI2_c" 350.000000 ns  ;
+PERIOD NET "nCCAS_c" 350.000000 ns  ;
+PERIOD NET "nCRAS_c" 350.000000 ns  ;
+PERIOD NET "RCLK_c" 16.000000 ns  ;
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+OUTPUT PORT "RD[7]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[0]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[1]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[2]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[3]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[4]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[5]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[6]" LOAD 20.000000 pF ;
+OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ;
+OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ;
+OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ;
+OUTPUT PORT "nRWE" LOAD 10.000000 pF ;
+OUTPUT PORT "nRCAS" LOAD 10.000000 pF ;
+OUTPUT PORT "nRCS" LOAD 10.000000 pF ;
+OUTPUT PORT "nRRAS" LOAD 10.000000 pF ;
+OUTPUT PORT "RDQML" LOAD 10.000000 pF ;
+OUTPUT PORT "RDQMH" LOAD 10.000000 pF ;
+OUTPUT PORT "RCKE" LOAD 10.000000 pF ;
+OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ;
+OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[11]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[10]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[9]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[8]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[7]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[6]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[5]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[4]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[3]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[2]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[1]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[0]" LOAD 10.000000 pF ;
+OUTPUT PORT "LED" LOAD 25.000000 pF ;
+OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ;
+VCCIO_DERATE BANK 0 PERCENT -5; 
+VCCIO_DERATE PERCENT -5; 
+VCCIO_DERATE BANK 1 PERCENT -5; 
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/Untitled.tpf.prf_cdmp0 b/CPLD/LCMXO/LCMXO640C/impl1/Untitled.tpf.prf_cdmp0
new file mode 100644
index 0000000..3564159
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/Untitled.tpf.prf_cdmp0
@@ -0,0 +1,88 @@
+PERIOD NET "PHI2_c" 350.000000 ns  ;
+PERIOD NET "nCCAS_c" 350.000000 ns  ;
+PERIOD NET "nCRAS_c" 350.000000 ns  ;
+PERIOD NET "RCLK_c" 16.000000 ns  ;
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+OUTPUT PORT "RD[7]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[0]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[1]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[2]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[3]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[4]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[5]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[6]" LOAD 20.000000 pF ;
+OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ;
+OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ;
+OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ;
+OUTPUT PORT "nRWE" LOAD 10.000000 pF ;
+OUTPUT PORT "nRCAS" LOAD 10.000000 pF ;
+OUTPUT PORT "nRCS" LOAD 10.000000 pF ;
+OUTPUT PORT "nRRAS" LOAD 10.000000 pF ;
+OUTPUT PORT "RDQML" LOAD 10.000000 pF ;
+OUTPUT PORT "RDQMH" LOAD 10.000000 pF ;
+OUTPUT PORT "RCKE" LOAD 10.000000 pF ;
+OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ;
+OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[11]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[10]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[9]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[8]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[7]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[6]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[5]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[4]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[3]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[2]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[1]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[0]" LOAD 10.000000 pF ;
+OUTPUT PORT "LED" LOAD 25.000000 pF ;
+OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ;
+VOLTAGE 3.300 V;
+VCCIO_DERATE BANK 0 PERCENT -5; 
+VCCIO_DERATE PERCENT -5; 
+VCCIO_DERATE BANK 1 PERCENT -5; 
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/Untitled.tpf.prf_cdmp2 b/CPLD/LCMXO/LCMXO640C/impl1/Untitled.tpf.prf_cdmp2
new file mode 100644
index 0000000..0f2c679
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/Untitled.tpf.prf_cdmp2
@@ -0,0 +1,155 @@
+VOLTAGE 3.300 V;
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+IOBUF PORT "RD[7]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RD[6]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RD[5]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RD[4]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RD[3]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RD[2]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RD[1]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RD[0]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Dout[7]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Dout[6]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Dout[5]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Dout[4]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Dout[3]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Dout[2]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Dout[1]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Dout[0]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "LED" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RBA[1]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RBA[0]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[11]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[10]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[9]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[8]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[7]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[6]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[5]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[4]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[3]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[2]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[1]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RA[0]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "nRCS" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RCKE" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "nRWE" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "nRRAS" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "nRCAS" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RDQMH" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RDQML" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "nUFMCS" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "UFMCLK" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "UFMSDI" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "PHI2" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[9]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[8]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[7]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[6]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[5]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[4]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[3]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[2]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[1]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "MAin[0]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "CROW[1]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "CROW[0]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Din[7]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Din[6]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Din[5]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Din[4]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Din[3]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Din[2]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Din[1]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "Din[0]" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "nCCAS" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "nCRAS" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "nFWE" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "RCLK" IO_TYPE=LVCMOS25 ;
+IOBUF PORT "UFMSDO" IO_TYPE=LVCMOS25 ;
+PERIOD NET "PHI2_c" 350.000000 ns  ;
+PERIOD NET "nCCAS_c" 350.000000 ns  ;
+PERIOD NET "nCRAS_c" 350.000000 ns  ;
+PERIOD NET "RCLK_c" 16.000000 ns  ;
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+OUTPUT PORT "RD[7]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[0]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[1]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[2]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[3]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[4]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[5]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[6]" LOAD 20.000000 pF ;
+OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ;
+OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ;
+OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ;
+OUTPUT PORT "nRWE" LOAD 10.000000 pF ;
+OUTPUT PORT "nRCAS" LOAD 10.000000 pF ;
+OUTPUT PORT "nRCS" LOAD 10.000000 pF ;
+OUTPUT PORT "nRRAS" LOAD 10.000000 pF ;
+OUTPUT PORT "RDQML" LOAD 10.000000 pF ;
+OUTPUT PORT "RDQMH" LOAD 10.000000 pF ;
+OUTPUT PORT "RCKE" LOAD 10.000000 pF ;
+OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ;
+OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[11]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[10]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[9]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[8]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[7]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[6]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[5]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[4]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[3]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[2]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[1]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[0]" LOAD 10.000000 pF ;
+OUTPUT PORT "LED" LOAD 25.000000 pF ;
+OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ;
+VCCIO_DERATE BANK 0 PERCENT -5; 
+VCCIO_DERATE PERCENT -5; 
+VCCIO_DERATE BANK 1 PERCENT -5; 
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/Untitled.tpf_hold.html b/CPLD/LCMXO/LCMXO640C/impl1/Untitled.tpf_hold.html
new file mode 100644
index 0000000..5e379e0
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/Untitled.tpf_hold.html
@@ -0,0 +1,2080 @@
+
+
+
+
+
+
+
+
    
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
+Mon Aug 16 20:38:58 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Design file:     RAM2GS
+Device,speed:    LCMXO640C,M
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            10 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+ 
+
+Passed: The following path meets requirements by 0.447ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_375  (from PHI2_c -)
+   Destination:    FF         Data in        ADSubmitted_375  (to PHI2_c -)
+
+   Delay:               0.424ns  (61.8% logic, 38.2% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.424ns physical path delay SLICE_9 to SLICE_9 meets
+     -0.023ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.023ns) by 0.447ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R4C5C.CLK to       R4C5C.Q0 SLICE_9 (from PHI2_c)
+ROUTE         2     0.162       R4C5C.Q0 to R4C5C.A0       ADSubmitted
+CTOF_DEL    ---     0.092       R4C5C.A0 to       R4C5C.F0 SLICE_9
+ROUTE         1     0.000       R4C5C.F0 to R4C5C.DI0      n1355 (to PHI2_c)
+                  --------
+                    0.424   (61.8% logic, 38.2% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R4C5C.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R4C5C.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 1.244ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_374  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_373  (to PHI2_c -)
+
+   Delay:               1.215ns  (41.6% logic, 58.4% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.215ns physical path delay SLICE_14 to SLICE_18 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.244ns
+
+ Physical Path Details:
+
+      Data path SLICE_14 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R4C5A.CLK to       R4C5A.Q0 SLICE_14 (from PHI2_c)
+ROUTE         1     0.222       R4C5A.Q0 to R4C6C.C1       C1Submitted
+CTOOFX_DEL  ---     0.151       R4C6C.C1 to     R4C6C.OFX0 i26/SLICE_70
+ROUTE         1     0.204     R4C6C.OFX0 to R4C6D.C1       n13
+CTOF_DEL    ---     0.092       R4C6D.C1 to       R4C6D.F1 SLICE_80
+ROUTE         1     0.123       R4C6D.F1 to R4C6D.C0       n6
+CTOF_DEL    ---     0.092       R4C6D.C0 to       R4C6D.F0 SLICE_80
+ROUTE         1     0.161       R4C6D.F0 to R4C6B.CE       PHI2_N_114_enable_8 (to PHI2_c)
+                  --------
+                    1.215   (41.6% logic, 58.4% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R4C5A.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R4C6B.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 1.249ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_373  (from PHI2_c -)
+   Destination:    FF         Data in        CmdSubmitted_378  (to PHI2_c -)
+
+   Delay:               1.220ns  (29.0% logic, 71.0% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.220ns physical path delay SLICE_18 to SLICE_19 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.249ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R4C6B.CLK to       R4C6B.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.271       R4C6B.Q0 to R4C5B.B1       CmdEnable
+CTOF_DEL    ---     0.092       R4C5B.B1 to       R4C5B.F1 SLICE_76
+ROUTE         3     0.132       R4C5B.F1 to R4C5B.C0       XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R4C5B.C0 to       R4C5B.F0 SLICE_76
+ROUTE         2     0.463       R4C5B.F0 to R7C7C.CE       PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                    1.220   (29.0% logic, 71.0% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R4C6B.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R7C7C.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 1.287ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_375  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_373  (to PHI2_c -)
+
+   Delay:               1.258ns  (40.5% logic, 59.5% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.258ns physical path delay SLICE_9 to SLICE_18 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.287ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R4C5C.CLK to       R4C5C.Q0 SLICE_9 (from PHI2_c)
+ROUTE         2     0.261       R4C5C.Q0 to R4C6C.A0       ADSubmitted
+CTOOFX_DEL  ---     0.155       R4C6C.A0 to     R4C6C.OFX0 i26/SLICE_70
+ROUTE         1     0.204     R4C6C.OFX0 to R4C6D.C1       n13
+CTOF_DEL    ---     0.092       R4C6D.C1 to       R4C6D.F1 SLICE_80
+ROUTE         1     0.123       R4C6D.F1 to R4C6D.C0       n6
+CTOF_DEL    ---     0.092       R4C6D.C0 to       R4C6D.F0 SLICE_80
+ROUTE         1     0.161       R4C6D.F0 to R4C6B.CE       PHI2_N_114_enable_8 (to PHI2_c)
+                  --------
+                    1.258   (40.5% logic, 59.5% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R4C5C.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R4C6B.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 1.372ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_373  (from PHI2_c -)
+   Destination:    FF         Data in        Cmdn8MEGEN_377  (to PHI2_c -)
+
+   Delay:               1.343ns  (26.4% logic, 73.6% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.343ns physical path delay SLICE_18 to SLICE_23 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.372ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R4C6B.CLK to       R4C6B.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.271       R4C6B.Q0 to R4C5B.B1       CmdEnable
+CTOF_DEL    ---     0.092       R4C5B.B1 to       R4C5B.F1 SLICE_76
+ROUTE         3     0.132       R4C5B.F1 to R4C5B.C0       XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R4C5B.C0 to       R4C5B.F0 SLICE_76
+ROUTE         2     0.586       R4C5B.F0 to R6C6A.CE       PHI2_N_114_enable_6 (to PHI2_c)
+                  --------
+                    1.343   (26.4% logic, 73.6% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R4C6B.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R6C6A.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 1.447ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_373  (from PHI2_c -)
+   Destination:    FF         Data in        XOR8MEG_376  (to PHI2_c -)
+
+   Delay:               1.418ns  (25.0% logic, 75.0% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.418ns physical path delay SLICE_18 to SLICE_94 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.447ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R4C6B.CLK to       R4C6B.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.271       R4C6B.Q0 to R4C5B.B1       CmdEnable
+CTOF_DEL    ---     0.092       R4C5B.B1 to       R4C5B.F1 SLICE_76
+ROUTE         3     0.383       R4C5B.F1 to R7C6D.C0       XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R7C6D.C0 to       R7C6D.F0 SLICE_97
+ROUTE         1     0.410       R7C6D.F0 to R8C9B.CE       PHI2_N_114_enable_2 (to PHI2_c)
+                  --------
+                    1.418   (25.0% logic, 75.0% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R4C6B.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R8C9B.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 1.656ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_373  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMSDI_381  (to PHI2_c -)
+
+   Delay:               1.627ns  (21.8% logic, 78.2% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.627ns physical path delay SLICE_18 to SLICE_77 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.656ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R4C6B.CLK to       R4C6B.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.271       R4C6B.Q0 to R4C5B.B1       CmdEnable
+CTOF_DEL    ---     0.092       R4C5B.B1 to       R4C5B.F1 SLICE_76
+ROUTE         3     0.335       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R5C2A.D1 to       R5C2A.F1 SLICE_73
+ROUTE         2     0.667       R5C2A.F1 to R9C9A.CE       PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                    1.627   (21.8% logic, 78.2% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R4C6B.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R9C9A.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 1.779ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_373  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMCS_379  (to PHI2_c -)
+                   FF                        CmdUFMCLK_380
+
+   Delay:               1.750ns  (20.2% logic, 79.8% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.750ns physical path delay SLICE_18 to SLICE_83 meets
+     -0.029ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.029ns) by 1.779ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R4C6B.CLK to       R4C6B.Q0 SLICE_18 (from PHI2_c)
+ROUTE         1     0.271       R4C6B.Q0 to R4C5B.B1       CmdEnable
+CTOF_DEL    ---     0.092       R4C5B.B1 to       R4C5B.F1 SLICE_76
+ROUTE         3     0.335       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
+CTOF_DEL    ---     0.092       R5C2A.D1 to       R5C2A.F1 SLICE_73
+ROUTE         2     0.790       R5C2A.F1 to R5C8B.CE       PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                    1.750   (20.2% logic, 79.8% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R4C6B.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R5C8B.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 175.792ns (weighted slack = 351.584ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              XOR8MEG_376  (from PHI2_c -)
+   Destination:    FF         Data in        RA11_353  (to PHI2_c +)
+
+   Delay:               0.781ns  (33.5% logic, 66.5% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.781ns physical path delay SLICE_94 to SLICE_31 meets
+     -0.011ns DIN_HLD and
+    -175.000ns delay constraint less
+      0.000ns skew requirement (totaling -175.011ns) by 175.792ns
+
+ Physical Path Details:
+
+      Data path SLICE_94 to SLICE_31:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.170      R8C9B.CLK to       R8C9B.Q0 SLICE_94 (from PHI2_c)
+ROUTE         1     0.519       R8C9B.Q0 to R2C9A.B0       XOR8MEG
+CTOF_DEL    ---     0.092       R2C9A.B0 to       R2C9A.F0 SLICE_31
+ROUTE         1     0.000       R2C9A.F0 to R2C9A.DI0      RA11_N_180 (to PHI2_c)
+                  --------
+                    0.781   (33.5% logic, 66.5% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R8C9B.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_31:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R2C9A.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 176.113ns (weighted slack = 352.226ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i3  (from PHI2_c +)
+   Destination:    FF         Data in        C1Submitted_374  (to PHI2_c -)
+
+   Delay:               1.084ns  (31.5% logic, 68.5% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.084ns physical path delay SLICE_92 to SLICE_14 meets
+     -0.029ns CE_HLD and
+    -175.000ns delay constraint less
+      0.000ns skew requirement (totaling -175.029ns) by 176.113ns
+
+ Physical Path Details:
+
+      Data path SLICE_92 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C3A.CLK to       R2C3A.Q1 SLICE_92 (from PHI2_c)
+ROUTE         1     0.344       R2C3A.Q1 to R2C5C.A1       Bank_3
+CTOF_DEL    ---     0.092       R2C5C.A1 to       R2C5C.F1 SLICE_74
+ROUTE         5     0.132       R2C5C.F1 to R2C5C.C0       n1279
+CTOF_DEL    ---     0.092       R2C5C.C0 to       R2C5C.F0 SLICE_74
+ROUTE         1     0.267       R2C5C.F0 to R4C5A.CE       PHI2_N_114_enable_1 (to PHI2_c)
+                  --------
+                    1.084   (31.5% logic, 68.5% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_92:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R2C3A.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.120       39.PADDI to R4C5A.CLK      PHI2_c
+                  --------
+                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            10 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+ 
+
+Passed: The following path meets requirements by 0.339ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i2  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i3  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_101 to SLICE_101 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_101 to SLICE_101:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C6C.CLK to       R2C6C.Q0 SLICE_101 (from RCLK_c)
+ROUTE         1     0.161       R2C6C.Q0 to R2C6C.M1       n705 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_101:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R2C6C.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_101:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R2C6C.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.339ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i3  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i4  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_101 to SLICE_81 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_101 to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C6C.CLK to       R2C6C.Q1 SLICE_101 (from RCLK_c)
+ROUTE         1     0.161       R2C6C.Q1 to R2C6B.M0       n704 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_101:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R2C6C.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R2C6B.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.339ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i6  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i7  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_80 to SLICE_80 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_80 to SLICE_80:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R4C6D.CLK to       R4C6D.Q0 SLICE_80 (from RCLK_c)
+ROUTE         1     0.161       R4C6D.Q0 to R4C6D.M1       n701 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_80:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R4C6D.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_80:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R4C6D.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.339ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i4  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i5  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_81 to SLICE_81 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_81 to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C6B.CLK to       R2C6B.Q0 SLICE_81 (from RCLK_c)
+ROUTE         1     0.161       R2C6B.Q0 to R2C6B.M1       n703 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R2C6B.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R2C6B.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.339ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i12  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i13  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_84 to SLICE_84 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_84 to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C5B.CLK to       R2C5B.Q0 SLICE_84 (from RCLK_c)
+ROUTE         1     0.161       R2C5B.Q0 to R2C5B.M1       n695 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R2C5B.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R2C5B.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.339ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i8  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i9  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_95 to SLICE_95 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R8C9C.CLK to       R8C9C.Q0 SLICE_95 (from RCLK_c)
+ROUTE         1     0.161       R8C9C.Q0 to R8C9C.M1       n699 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R8C9C.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R8C9C.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.339ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i10  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i11  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_96 to SLICE_96 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_96 to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R4C7A.CLK to       R4C7A.Q0 SLICE_96 (from RCLK_c)
+ROUTE         1     0.161       R4C7A.Q0 to R4C7A.M1       n697 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R4C7A.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_96:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R4C7A.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.339ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i14  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i15  (to RCLK_c +)
+
+   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.318ns physical path delay SLICE_99 to SLICE_99 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
+
+ Physical Path Details:
+
+      Data path SLICE_99 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C7B.CLK to       R2C7B.Q0 SLICE_99 (from RCLK_c)
+ROUTE         1     0.161       R2C7B.Q0 to R2C7B.M1       n693 (to RCLK_c)
+                  --------
+                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R2C7B.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R2C7B.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.345ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RASr2_348  (from RCLK_c +)
+   Destination:    FF         Data in        RASr3_349  (to RCLK_c +)
+
+   Delay:               0.324ns  (48.5% logic, 51.5% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.324ns physical path delay SLICE_61 to SLICE_29 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.345ns
+
+ Physical Path Details:
+
+      Data path SLICE_61 to SLICE_29:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R4C9B.CLK to       R4C9B.Q1 SLICE_61 (from RCLK_c)
+ROUTE        16     0.167       R4C9B.Q1 to R4C9D.M1       RASr2 (to RCLK_c)
+                  --------
+                    0.324   (48.5% logic, 51.5% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R4C9B.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_29:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R4C9D.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 0.345ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i0  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i1  (to RCLK_c +)
+
+   Delay:               0.324ns  (48.5% logic, 51.5% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.324ns physical path delay SLICE_87 to SLICE_87 meets
+     -0.021ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.021ns) by 0.345ns
+
+ Physical Path Details:
+
+      Data path SLICE_87 to SLICE_87:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R6C9A.CLK to       R6C9A.Q0 SLICE_87 (from RCLK_c)
+ROUTE         6     0.167       R6C9A.Q0 to R6C9A.M1       nRCS_N_135 (to RCLK_c)
+                  --------
+                    0.324   (48.5% logic, 51.5% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_87:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R6C9A.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_87:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     0.435       86.PADDI to R6C9A.CLK      RCLK_c
+                  --------
+                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.949ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_368  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_55 and
+      1.462ns delay SLICE_55 to RA[10] (totaling 1.949ns) meets
+      0.000ns hold offset RCLK to RA[10] by 1.949ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C5A.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_55 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C5A.CLK to       R2C5A.Q0 SLICE_55 (from RCLK_c)
+ROUTE         1     0.197       R2C5A.Q0 to 87.PADDO       n974
+DOPAD_DEL   ---     1.108       87.PADDO to         87.PAD RA[10]
+                  --------
+                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    1.949ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.844ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     2.357ns  (57.6% logic, 42.4% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.357ns delay SLICE_64 to RA[9] (totaling 2.844ns) meets
+      0.000ns hold offset RCLK to RA[9] by 2.844ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.473       R2C6A.Q0 to R6C9A.D1       nRowColSel
+CTOF_DEL    ---     0.092       R6C9A.D1 to       R6C9A.F1 SLICE_87
+ROUTE         1     0.527       R6C9A.F1 to 85.PADDO       RA_c_9
+DOPAD_DEL   ---     1.108       85.PADDO to         85.PAD RA[9]
+                  --------
+                    2.357   (57.6% logic, 42.4% route), 3 logic levels.
+
+Report:    2.844ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.575ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     2.088ns  (65.0% logic, 35.0% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.088ns delay SLICE_64 to RA[8] (totaling 2.575ns) meets
+      0.000ns hold offset RCLK to RA[8] by 2.575ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.375       R2C6A.Q0 to R2C2A.C0       nRowColSel
+CTOF_DEL    ---     0.092       R2C2A.C0 to       R2C2A.F0 SLICE_98
+ROUTE         1     0.356       R2C2A.F0 to 96.PADDO       RA_c_8
+DOPAD_DEL   ---     1.108       96.PADDO to         96.PAD RA[8]
+                  --------
+                    2.088   (65.0% logic, 35.0% route), 3 logic levels.
+
+Report:    2.575ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.673ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     2.186ns  (62.1% logic, 37.9% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.186ns delay SLICE_64 to RA[7] (totaling 2.673ns) meets
+      0.000ns hold offset RCLK to RA[7] by 2.673ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.226       R2C6A.Q0 to R2C6A.C1       nRowColSel
+CTOF_DEL    ---     0.092       R2C6A.C1 to       R2C6A.F1 SLICE_64
+ROUTE         1     0.603       R2C6A.F1 to 100.PADDO      RA_c_7
+DOPAD_DEL   ---     1.108      100.PADDO to        100.PAD RA[7]
+                  --------
+                    2.186   (62.1% logic, 37.9% route), 3 logic levels.
+
+Report:    2.673ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.687ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     2.200ns  (61.7% logic, 38.3% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.200ns delay SLICE_64 to RA[6] (totaling 2.687ns) meets
+      0.000ns hold offset RCLK to RA[6] by 2.687ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.375       R2C6A.Q0 to R2C2A.C1       nRowColSel
+CTOF_DEL    ---     0.092       R2C2A.C1 to       R2C2A.F1 SLICE_98
+ROUTE         1     0.468       R2C2A.F1 to 91.PADDO       RA_c_6
+DOPAD_DEL   ---     1.108       91.PADDO to         91.PAD RA[6]
+                  --------
+                    2.200   (61.7% logic, 38.3% route), 3 logic levels.
+
+Report:    2.687ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.915ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     2.428ns  (55.9% logic, 44.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.428ns delay SLICE_64 to RA[5] (totaling 2.915ns) meets
+      0.000ns hold offset RCLK to RA[5] by 2.915ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.447       R2C6A.Q0 to R8C9C.D1       nRowColSel
+CTOF_DEL    ---     0.092       R8C9C.D1 to       R8C9C.F1 SLICE_95
+ROUTE         1     0.624       R8C9C.F1 to 95.PADDO       RA_c_5
+DOPAD_DEL   ---     1.108       95.PADDO to         95.PAD RA[5]
+                  --------
+                    2.428   (55.9% logic, 44.1% route), 3 logic levels.
+
+Report:    2.915ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.574ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     2.087ns  (65.0% logic, 35.0% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.087ns delay SLICE_64 to RA[4] (totaling 2.574ns) meets
+      0.000ns hold offset RCLK to RA[4] by 2.574ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.375       R2C6A.Q0 to R2C2C.C1       nRowColSel
+CTOF_DEL    ---     0.092       R2C2C.C1 to       R2C2C.F1 SLICE_93
+ROUTE         1     0.355       R2C2C.F1 to 99.PADDO       RA_c_4
+DOPAD_DEL   ---     1.108       99.PADDO to         99.PAD RA[4]
+                  --------
+                    2.087   (65.0% logic, 35.0% route), 3 logic levels.
+
+Report:    2.574ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.622ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     2.135ns  (63.6% logic, 36.4% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.135ns delay SLICE_64 to RA[3] (totaling 2.622ns) meets
+      0.000ns hold offset RCLK to RA[3] by 2.622ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.310       R2C6A.Q0 to R2C3A.D1       nRowColSel
+CTOF_DEL    ---     0.092       R2C3A.D1 to       R2C3A.F1 SLICE_92
+ROUTE         1     0.468       R2C3A.F1 to 97.PADDO       RA_c_3
+DOPAD_DEL   ---     1.108       97.PADDO to         97.PAD RA[3]
+                  --------
+                    2.135   (63.6% logic, 36.4% route), 3 logic levels.
+
+Report:    2.622ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.698ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     2.211ns  (61.4% logic, 38.6% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.211ns delay SLICE_64 to RA[2] (totaling 2.698ns) meets
+      0.000ns hold offset RCLK to RA[2] by 2.698ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.375       R2C6A.Q0 to R2C2B.C0       nRowColSel
+CTOF_DEL    ---     0.092       R2C2B.C0 to       R2C2B.F0 SLICE_90
+ROUTE         1     0.479       R2C2B.F0 to 94.PADDO       RA_c_2
+DOPAD_DEL   ---     1.108       94.PADDO to         94.PAD RA[2]
+                  --------
+                    2.211   (61.4% logic, 38.6% route), 3 logic levels.
+
+Report:    2.698ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.622ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     2.135ns  (63.6% logic, 36.4% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.135ns delay SLICE_64 to RA[1] (totaling 2.622ns) meets
+      0.000ns hold offset RCLK to RA[1] by 2.622ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.310       R2C6A.Q0 to R2C3A.D0       nRowColSel
+CTOF_DEL    ---     0.092       R2C3A.D0 to       R2C3A.F0 SLICE_92
+ROUTE         1     0.468       R2C3A.F0 to 89.PADDO       RA_c_1
+DOPAD_DEL   ---     1.108       89.PADDO to         89.PAD RA[1]
+                  --------
+                    2.135   (63.6% logic, 36.4% route), 3 logic levels.
+
+Report:    2.622ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.573ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     2.086ns  (65.1% logic, 34.9% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.086ns delay SLICE_64 to RA[0] (totaling 2.573ns) meets
+      0.000ns hold offset RCLK to RA[0] by 2.573ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.375       R2C6A.Q0 to R2C2C.C0       nRowColSel
+CTOF_DEL    ---     0.092       R2C2C.C0 to       R2C2C.F0 SLICE_93
+ROUTE         1     0.354       R2C2C.F0 to 98.PADDO       RA_c_0
+DOPAD_DEL   ---     1.108       98.PADDO to         98.PAD RA[0]
+                  --------
+                    2.086   (65.1% logic, 34.9% route), 3 logic levels.
+
+Report:    2.573ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.949ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_364  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_60 and
+      1.462ns delay SLICE_60 to nRCS (totaling 1.949ns) meets
+      0.000ns hold offset RCLK to nRCS by 1.949ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C9C.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_60 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C9C.CLK to       R2C9C.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1     0.197       R2C9C.Q0 to 77.PADDO       nRCS_c
+DOPAD_DEL   ---     1.108       77.PADDO to         77.PAD nRCS
+                  --------
+                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    1.949ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.949ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_363  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_34 and
+      1.462ns delay SLICE_34 to RCKE (totaling 1.949ns) meets
+      0.000ns hold offset RCLK to RCKE by 1.949ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C7C.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_34 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C7C.CLK to       R2C7C.Q0 SLICE_34 (from RCLK_c)
+ROUTE         4     0.197       R2C7C.Q0 to 82.PADDO       RCKE_c
+DOPAD_DEL   ---     1.108       82.PADDO to         82.PAD RCKE
+                  --------
+                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    1.949ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.232ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_367  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     1.745ns  (72.5% logic, 27.5% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_63 and
+      1.745ns delay SLICE_63 to nRWE (totaling 2.232ns) meets
+      0.000ns hold offset RCLK to nRWE by 2.232ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C7A.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_63 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C7A.CLK to       R2C7A.Q0 SLICE_63 (from RCLK_c)
+ROUTE         1     0.480       R2C7A.Q0 to 72.PADDO       nRWE_c
+DOPAD_DEL   ---     1.108       72.PADDO to         72.PAD nRWE
+                  --------
+                    1.745   (72.5% logic, 27.5% route), 2 logic levels.
+
+Report:    2.232ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.236ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_365  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     1.749ns  (72.3% logic, 27.7% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_61 and
+      1.749ns delay SLICE_61 to nRRAS (totaling 2.236ns) meets
+      0.000ns hold offset RCLK to nRRAS by 2.236ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R4C9B.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_61 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R4C9B.CLK to       R4C9B.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2     0.484       R4C9B.Q0 to 73.PADDO       nRRAS_c
+DOPAD_DEL   ---     1.108       73.PADDO to         73.PAD nRRAS
+                  --------
+                    1.749   (72.3% logic, 27.7% route), 2 logic levels.
+
+Report:    2.236ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.949ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_366  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_58 and
+      1.462ns delay SLICE_58 to nRCAS (totaling 1.949ns) meets
+      0.000ns hold offset RCLK to nRCAS by 1.949ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C9B.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_58 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C9B.CLK to       R2C9B.Q0 SLICE_58 (from RCLK_c)
+ROUTE         1     0.197       R2C9B.Q0 to 78.PADDO       nRCAS_c
+DOPAD_DEL   ---     1.108       78.PADDO to         78.PAD nRCAS
+                  --------
+                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    1.949ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.711ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     2.224ns  (61.0% logic, 39.0% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.224ns delay SLICE_64 to RDQMH (totaling 2.711ns) meets
+      0.000ns hold offset RCLK to RDQMH by 2.711ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.473       R2C6A.Q0 to R6C9A.D0       nRowColSel
+CTOF_DEL    ---     0.092       R6C9A.D0 to       R6C9A.F0 SLICE_87
+ROUTE         1     0.394       R6C9A.F0 to 76.PADDO       RDQMH_c
+DOPAD_DEL   ---     1.108       76.PADDO to         76.PAD RDQMH
+                  --------
+                    2.224   (61.0% logic, 39.0% route), 3 logic levels.
+
+Report:    2.711ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.488ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     2.001ns  (67.8% logic, 32.2% route), 3 logic levels.
+
+   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      0.487ns delay RCLK to SLICE_64 and
+      2.001ns delay SLICE_64 to RDQML (totaling 2.488ns) meets
+      0.000ns hold offset RCLK to RDQML by 2.488ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.223       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.157      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.447       R2C6A.Q0 to R8C9C.D0       nRowColSel
+CTOF_DEL    ---     0.092       R8C9C.D0 to       R8C9C.F0 SLICE_95
+ROUTE         1     0.197       R8C9C.F0 to 61.PADDO       RDQML_c
+DOPAD_DEL   ---     1.108       61.PADDO to         61.PAD RDQML
+                  --------
+                    2.001   (67.8% logic, 32.2% route), 3 logic levels.
+
+Report:    2.488ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |            -|            -|   2  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |            -|            -|   1  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.844 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.575 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.673 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.687 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.915 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.574 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.622 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.698 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.622 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.573 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.232 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.236 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.711 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     2.488 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 520 paths, 6 nets, and 440 connections (71.54% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 0 (setup), 0 (hold)
+Score: 0 (setup), 0 (hold)
+Cumulative negative slack: 0 (0+0)
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/Untitled.tpf_setup.html b/CPLD/LCMXO/LCMXO640C/impl1/Untitled.tpf_setup.html
new file mode 100644
index 0000000..9090020
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/Untitled.tpf_setup.html
@@ -0,0 +1,3314 @@
+
+
+
+
+
+
+
+
    
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
+Mon Aug 16 20:38:58 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Design file:     RAM2GS
+Device,speed:    LCMXO640C,3
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            10 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+ 
+
+Passed: The following path meets requirements by 163.925ns (weighted slack = 327.850ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS_379  (to PHI2_c -)
+                   FF                        CmdUFMCLK_380
+
+   Delay:              10.810ns  (25.8% logic, 74.2% route), 7 logic levels.
+
+ Constraint Details:
+
+     10.810ns physical path delay SLICE_98 to SLICE_83 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 163.925ns
+
+ Physical Path Details:
+
+      Data path SLICE_98 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_98 (from PHI2_c)
+ROUTE         1     1.018       R2C2A.Q0 to R2C2B.B1       Bank_6
+CTOF_DEL    ---     0.371       R2C2B.B1 to       R2C2B.F1 SLICE_90
+ROUTE         1     1.155       R2C2B.F1 to R2C5B.D1       n2160
+CTOF_DEL    ---     0.371       R2C5B.D1 to       R2C5B.F1 SLICE_84
+ROUTE         1     0.304       R2C5B.F1 to R2C5C.D1       n26
+CTOF_DEL    ---     0.371       R2C5C.D1 to       R2C5C.F1 SLICE_74
+ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
+CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
+ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
+CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
+ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
+ROUTE         2     3.021       R5C2A.F1 to R5C8B.CE       PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   10.810   (25.8% logic, 74.2% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_98:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R2C2A.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R5C8B.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 164.114ns (weighted slack = 328.228ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS_379  (to PHI2_c -)
+                   FF                        CmdUFMCLK_380
+
+   Delay:              10.621ns  (26.2% logic, 73.8% route), 7 logic levels.
+
+ Constraint Details:
+
+     10.621ns physical path delay SLICE_98 to SLICE_83 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 164.114ns
+
+ Physical Path Details:
+
+      Data path SLICE_98 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_98 (from PHI2_c)
+ROUTE         1     1.487       R2C2A.Q1 to R2C5B.A0       Bank_7
+CTOF_DEL    ---     0.371       R2C5B.A0 to       R2C5B.F0 SLICE_84
+ROUTE         1     0.497       R2C5B.F0 to R2C5B.C1       n2136
+CTOF_DEL    ---     0.371       R2C5B.C1 to       R2C5B.F1 SLICE_84
+ROUTE         1     0.304       R2C5B.F1 to R2C5C.D1       n26
+CTOF_DEL    ---     0.371       R2C5C.D1 to       R2C5C.F1 SLICE_74
+ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
+CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
+ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
+CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
+ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
+ROUTE         2     3.021       R5C2A.F1 to R5C8B.CE       PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   10.621   (26.2% logic, 73.8% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_98:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R2C2A.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R5C8B.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 164.237ns (weighted slack = 328.474ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i4  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS_379  (to PHI2_c -)
+                   FF                        CmdUFMCLK_380
+
+   Delay:              10.498ns  (23.0% logic, 77.0% route), 6 logic levels.
+
+ Constraint Details:
+
+     10.498ns physical path delay SLICE_90 to SLICE_83 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 164.237ns
+
+ Physical Path Details:
+
+      Data path SLICE_90 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2B.CLK to       R2C2B.Q0 SLICE_90 (from PHI2_c)
+ROUTE         1     1.643       R2C2B.Q0 to R2C6C.B0       Bank_4
+CTOF_DEL    ---     0.371       R2C6C.B0 to       R2C6C.F0 SLICE_101
+ROUTE         1     0.893       R2C6C.F0 to R2C5C.C1       n2162
+CTOF_DEL    ---     0.371       R2C5C.C1 to       R2C5C.F1 SLICE_74
+ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
+CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
+ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
+CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
+ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
+ROUTE         2     3.021       R5C2A.F1 to R5C8B.CE       PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   10.498   (23.0% logic, 77.0% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R2C2B.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R5C8B.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 164.307ns (weighted slack = 328.614ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i5  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS_379  (to PHI2_c -)
+                   FF                        CmdUFMCLK_380
+
+   Delay:              10.428ns  (26.7% logic, 73.3% route), 7 logic levels.
+
+ Constraint Details:
+
+     10.428ns physical path delay SLICE_90 to SLICE_83 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 164.307ns
+
+ Physical Path Details:
+
+      Data path SLICE_90 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2B.CLK to       R2C2B.Q1 SLICE_90 (from PHI2_c)
+ROUTE         1     0.636       R2C2B.Q1 to R2C2B.A1       Bank_5
+CTOF_DEL    ---     0.371       R2C2B.A1 to       R2C2B.F1 SLICE_90
+ROUTE         1     1.155       R2C2B.F1 to R2C5B.D1       n2160
+CTOF_DEL    ---     0.371       R2C5B.D1 to       R2C5B.F1 SLICE_84
+ROUTE         1     0.304       R2C5B.F1 to R2C5C.D1       n26
+CTOF_DEL    ---     0.371       R2C5C.D1 to       R2C5C.F1 SLICE_74
+ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
+CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
+ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
+CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
+ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
+ROUTE         2     3.021       R5C2A.F1 to R5C8B.CE       PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   10.428   (26.7% logic, 73.3% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R2C2B.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R5C8B.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 164.317ns (weighted slack = 328.634ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i0  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS_379  (to PHI2_c -)
+                   FF                        CmdUFMCLK_380
+
+   Delay:              10.418ns  (26.7% logic, 73.3% route), 7 logic levels.
+
+ Constraint Details:
+
+     10.418ns physical path delay SLICE_93 to SLICE_83 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 164.317ns
+
+ Physical Path Details:
+
+      Data path SLICE_93 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2C.CLK to       R2C2C.Q0 SLICE_93 (from PHI2_c)
+ROUTE         1     0.626       R2C2C.Q0 to R2C2B.D1       Bank_0
+CTOF_DEL    ---     0.371       R2C2B.D1 to       R2C2B.F1 SLICE_90
+ROUTE         1     1.155       R2C2B.F1 to R2C5B.D1       n2160
+CTOF_DEL    ---     0.371       R2C5B.D1 to       R2C5B.F1 SLICE_84
+ROUTE         1     0.304       R2C5B.F1 to R2C5C.D1       n26
+CTOF_DEL    ---     0.371       R2C5C.D1 to       R2C5C.F1 SLICE_74
+ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
+CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
+ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
+CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
+ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
+ROUTE         2     3.021       R5C2A.F1 to R5C8B.CE       PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   10.418   (26.7% logic, 73.3% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R2C2C.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R5C8B.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 164.386ns (weighted slack = 328.772ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMSDI_381  (to PHI2_c -)
+
+   Delay:              10.349ns  (26.9% logic, 73.1% route), 7 logic levels.
+
+ Constraint Details:
+
+     10.349ns physical path delay SLICE_98 to SLICE_77 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 164.386ns
+
+ Physical Path Details:
+
+      Data path SLICE_98 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_98 (from PHI2_c)
+ROUTE         1     1.018       R2C2A.Q0 to R2C2B.B1       Bank_6
+CTOF_DEL    ---     0.371       R2C2B.B1 to       R2C2B.F1 SLICE_90
+ROUTE         1     1.155       R2C2B.F1 to R2C5B.D1       n2160
+CTOF_DEL    ---     0.371       R2C5B.D1 to       R2C5B.F1 SLICE_84
+ROUTE         1     0.304       R2C5B.F1 to R2C5C.D1       n26
+CTOF_DEL    ---     0.371       R2C5C.D1 to       R2C5C.F1 SLICE_74
+ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
+CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
+ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
+CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
+ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
+ROUTE         2     2.560       R5C2A.F1 to R9C9A.CE       PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   10.349   (26.9% logic, 73.1% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_98:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R2C2A.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R9C9A.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 164.575ns (weighted slack = 329.150ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMSDI_381  (to PHI2_c -)
+
+   Delay:              10.160ns  (27.4% logic, 72.6% route), 7 logic levels.
+
+ Constraint Details:
+
+     10.160ns physical path delay SLICE_98 to SLICE_77 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 164.575ns
+
+ Physical Path Details:
+
+      Data path SLICE_98 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_98 (from PHI2_c)
+ROUTE         1     1.487       R2C2A.Q1 to R2C5B.A0       Bank_7
+CTOF_DEL    ---     0.371       R2C5B.A0 to       R2C5B.F0 SLICE_84
+ROUTE         1     0.497       R2C5B.F0 to R2C5B.C1       n2136
+CTOF_DEL    ---     0.371       R2C5B.C1 to       R2C5B.F1 SLICE_84
+ROUTE         1     0.304       R2C5B.F1 to R2C5C.D1       n26
+CTOF_DEL    ---     0.371       R2C5C.D1 to       R2C5C.F1 SLICE_74
+ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
+CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
+ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
+CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
+ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
+ROUTE         2     2.560       R5C2A.F1 to R9C9A.CE       PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   10.160   (27.4% logic, 72.6% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_98:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R2C2A.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R9C9A.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 164.629ns (weighted slack = 329.258ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i1  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS_379  (to PHI2_c -)
+                   FF                        CmdUFMCLK_380
+
+   Delay:              10.106ns  (23.9% logic, 76.1% route), 6 logic levels.
+
+ Constraint Details:
+
+     10.106ns physical path delay SLICE_93 to SLICE_83 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 164.629ns
+
+ Physical Path Details:
+
+      Data path SLICE_93 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2C.CLK to       R2C2C.Q1 SLICE_93 (from PHI2_c)
+ROUTE         1     1.251       R2C2C.Q1 to R2C6C.D0       Bank_1
+CTOF_DEL    ---     0.371       R2C6C.D0 to       R2C6C.F0 SLICE_101
+ROUTE         1     0.893       R2C6C.F0 to R2C5C.C1       n2162
+CTOF_DEL    ---     0.371       R2C5C.C1 to       R2C5C.F1 SLICE_74
+ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
+CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
+ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
+CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
+ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
+ROUTE         2     3.021       R5C2A.F1 to R5C8B.CE       PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   10.106   (23.9% logic, 76.1% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R2C2C.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_83:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R5C8B.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 164.698ns (weighted slack = 329.396ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i4  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMSDI_381  (to PHI2_c -)
+
+   Delay:              10.037ns  (24.1% logic, 75.9% route), 6 logic levels.
+
+ Constraint Details:
+
+     10.037ns physical path delay SLICE_90 to SLICE_77 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 164.698ns
+
+ Physical Path Details:
+
+      Data path SLICE_90 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2B.CLK to       R2C2B.Q0 SLICE_90 (from PHI2_c)
+ROUTE         1     1.643       R2C2B.Q0 to R2C6C.B0       Bank_4
+CTOF_DEL    ---     0.371       R2C6C.B0 to       R2C6C.F0 SLICE_101
+ROUTE         1     0.893       R2C6C.F0 to R2C5C.C1       n2162
+CTOF_DEL    ---     0.371       R2C5C.C1 to       R2C5C.F1 SLICE_74
+ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
+CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
+ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
+CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
+ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
+ROUTE         2     2.560       R5C2A.F1 to R9C9A.CE       PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                   10.037   (24.1% logic, 75.9% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R2C2B.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R9C9A.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 164.768ns (weighted slack = 329.536ns)
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i5  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMSDI_381  (to PHI2_c -)
+
+   Delay:               9.967ns  (28.0% logic, 72.0% route), 7 logic levels.
+
+ Constraint Details:
+
+      9.967ns physical path delay SLICE_90 to SLICE_77 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 174.735ns) by 164.768ns
+
+ Physical Path Details:
+
+      Data path SLICE_90 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2B.CLK to       R2C2B.Q1 SLICE_90 (from PHI2_c)
+ROUTE         1     0.636       R2C2B.Q1 to R2C2B.A1       Bank_5
+CTOF_DEL    ---     0.371       R2C2B.A1 to       R2C2B.F1 SLICE_90
+ROUTE         1     1.155       R2C2B.F1 to R2C5B.D1       n2160
+CTOF_DEL    ---     0.371       R2C5B.D1 to       R2C5B.F1 SLICE_84
+ROUTE         1     0.304       R2C5B.F1 to R2C5C.D1       n26
+CTOF_DEL    ---     0.371       R2C5C.D1 to       R2C5C.F1 SLICE_74
+ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
+CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
+ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
+CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
+ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
+CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
+ROUTE         2     2.560       R5C2A.F1 to R9C9A.CE       PHI2_N_114_enable_7 (to PHI2_c)
+                  --------
+                    9.967   (28.0% logic, 72.0% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_90:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R2C2B.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.671       39.PADDI to R9C9A.CLK      PHI2_c
+                  --------
+                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:   22.150ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 348.000ns
+         The internal maximum frequency of the following component is 500.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    FSLICE     CLK            SLICE_73
+
+   Delay:               2.000ns -- based on Minimum Pulse Width
+
+Report:    2.000ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 348.000ns
+         The internal maximum frequency of the following component is 500.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    FSLICE     CLK            SLICE_74
+
+   Delay:               2.000ns -- based on Minimum Pulse Width
+
+Report:    2.000ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            10 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+ 
+
+Passed: The following path meets requirements by 7.341ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i15  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)
+
+   Delay:               8.415ns  (28.7% logic, 71.3% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.415ns physical path delay SLICE_7 to SLICE_56 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 7.341ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C8D.CLK to       R8C8D.Q1 SLICE_7 (from RCLK_c)
+ROUTE         3     1.475       R8C8D.Q1 to R8C9D.B1       FS_15
+CTOF_DEL    ---     0.371       R8C9D.B1 to       R8C9D.F1 SLICE_78
+ROUTE         3     1.057       R8C9D.F1 to R6C9B.A1       n10
+CTOF_DEL    ---     0.371       R6C9B.A1 to       R6C9B.F1 SLICE_75
+ROUTE         4     0.528       R6C9B.F1 to R6C9B.C0       n2298
+CTOF_DEL    ---     0.371       R6C9B.C0 to       R6C9B.F0 SLICE_75
+ROUTE         1     1.155       R6C9B.F0 to R9C9A.D1       n11
+CTOF_DEL    ---     0.371       R9C9A.D1 to       R9C9A.F1 SLICE_77
+ROUTE         2     0.712       R9C9A.F1 to R9C9A.B0       n2111
+CTOF_DEL    ---     0.371       R9C9A.B0 to       R9C9A.F0 SLICE_77
+ROUTE         1     1.073       R9C9A.F0 to R9C8D.CE       RCLK_c_enable_7 (to RCLK_c)
+                  --------
+                    8.415   (28.7% logic, 71.3% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R8C8D.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R9C8D.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 7.520ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i15  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_386  (to RCLK_c +)
+
+   Delay:               8.236ns  (29.3% logic, 70.7% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.236ns physical path delay SLICE_7 to SLICE_85 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 7.520ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C8D.CLK to       R8C8D.Q1 SLICE_7 (from RCLK_c)
+ROUTE         3     1.475       R8C8D.Q1 to R8C9D.B1       FS_15
+CTOF_DEL    ---     0.371       R8C9D.B1 to       R8C9D.F1 SLICE_78
+ROUTE         3     1.057       R8C9D.F1 to R6C9B.A1       n10
+CTOF_DEL    ---     0.371       R6C9B.A1 to       R6C9B.F1 SLICE_75
+ROUTE         4     0.528       R6C9B.F1 to R6C9B.C0       n2298
+CTOF_DEL    ---     0.371       R6C9B.C0 to       R6C9B.F0 SLICE_75
+ROUTE         1     1.155       R6C9B.F0 to R9C9A.D1       n11
+CTOF_DEL    ---     0.371       R9C9A.D1 to       R9C9A.F1 SLICE_77
+ROUTE         2     0.903       R9C9A.F1 to R10C9A.C1      n2111
+CTOF_DEL    ---     0.371      R10C9A.C1 to      R10C9A.F1 SLICE_100
+ROUTE         1     0.703      R10C9A.F1 to R9C9D.CE       RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    8.236   (29.3% logic, 70.7% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R8C8D.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R9C9D.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 7.549ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i14  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)
+
+   Delay:               8.207ns  (29.4% logic, 70.6% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.207ns physical path delay SLICE_7 to SLICE_56 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 7.549ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C8D.CLK to       R8C8D.Q0 SLICE_7 (from RCLK_c)
+ROUTE         3     1.267       R8C8D.Q0 to R8C9D.C1       FS_14
+CTOF_DEL    ---     0.371       R8C9D.C1 to       R8C9D.F1 SLICE_78
+ROUTE         3     1.057       R8C9D.F1 to R6C9B.A1       n10
+CTOF_DEL    ---     0.371       R6C9B.A1 to       R6C9B.F1 SLICE_75
+ROUTE         4     0.528       R6C9B.F1 to R6C9B.C0       n2298
+CTOF_DEL    ---     0.371       R6C9B.C0 to       R6C9B.F0 SLICE_75
+ROUTE         1     1.155       R6C9B.F0 to R9C9A.D1       n11
+CTOF_DEL    ---     0.371       R9C9A.D1 to       R9C9A.F1 SLICE_77
+ROUTE         2     0.712       R9C9A.F1 to R9C9A.B0       n2111
+CTOF_DEL    ---     0.371       R9C9A.B0 to       R9C9A.F0 SLICE_77
+ROUTE         1     1.073       R9C9A.F0 to R9C8D.CE       RCLK_c_enable_7 (to RCLK_c)
+                  --------
+                    8.207   (29.4% logic, 70.6% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R8C8D.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R9C8D.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 7.728ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i14  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_386  (to RCLK_c +)
+
+   Delay:               8.028ns  (30.1% logic, 69.9% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.028ns physical path delay SLICE_7 to SLICE_85 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 7.728ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C8D.CLK to       R8C8D.Q0 SLICE_7 (from RCLK_c)
+ROUTE         3     1.267       R8C8D.Q0 to R8C9D.C1       FS_14
+CTOF_DEL    ---     0.371       R8C9D.C1 to       R8C9D.F1 SLICE_78
+ROUTE         3     1.057       R8C9D.F1 to R6C9B.A1       n10
+CTOF_DEL    ---     0.371       R6C9B.A1 to       R6C9B.F1 SLICE_75
+ROUTE         4     0.528       R6C9B.F1 to R6C9B.C0       n2298
+CTOF_DEL    ---     0.371       R6C9B.C0 to       R6C9B.F0 SLICE_75
+ROUTE         1     1.155       R6C9B.F0 to R9C9A.D1       n11
+CTOF_DEL    ---     0.371       R9C9A.D1 to       R9C9A.F1 SLICE_77
+ROUTE         2     0.903       R9C9A.F1 to R10C9A.C1      n2111
+CTOF_DEL    ---     0.371      R10C9A.C1 to      R10C9A.F1 SLICE_100
+ROUTE         1     0.703      R10C9A.F1 to R9C9D.CE       RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    8.028   (30.1% logic, 69.9% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R8C8D.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R9C9D.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 7.768ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i13  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)
+
+   Delay:               7.988ns  (30.2% logic, 69.8% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.988ns physical path delay SLICE_8 to SLICE_56 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 7.768ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C8C.CLK to       R8C8C.Q1 SLICE_8 (from RCLK_c)
+ROUTE         3     1.048       R8C8C.Q1 to R8C9D.A1       FS_13
+CTOF_DEL    ---     0.371       R8C9D.A1 to       R8C9D.F1 SLICE_78
+ROUTE         3     1.057       R8C9D.F1 to R6C9B.A1       n10
+CTOF_DEL    ---     0.371       R6C9B.A1 to       R6C9B.F1 SLICE_75
+ROUTE         4     0.528       R6C9B.F1 to R6C9B.C0       n2298
+CTOF_DEL    ---     0.371       R6C9B.C0 to       R6C9B.F0 SLICE_75
+ROUTE         1     1.155       R6C9B.F0 to R9C9A.D1       n11
+CTOF_DEL    ---     0.371       R9C9A.D1 to       R9C9A.F1 SLICE_77
+ROUTE         2     0.712       R9C9A.F1 to R9C9A.B0       n2111
+CTOF_DEL    ---     0.371       R9C9A.B0 to       R9C9A.F0 SLICE_77
+ROUTE         1     1.073       R9C9A.F0 to R9C8D.CE       RCLK_c_enable_7 (to RCLK_c)
+                  --------
+                    7.988   (30.2% logic, 69.8% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R8C8C.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R9C8D.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 7.947ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i13  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_386  (to RCLK_c +)
+
+   Delay:               7.809ns  (30.9% logic, 69.1% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.809ns physical path delay SLICE_8 to SLICE_85 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 7.947ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C8C.CLK to       R8C8C.Q1 SLICE_8 (from RCLK_c)
+ROUTE         3     1.048       R8C8C.Q1 to R8C9D.A1       FS_13
+CTOF_DEL    ---     0.371       R8C9D.A1 to       R8C9D.F1 SLICE_78
+ROUTE         3     1.057       R8C9D.F1 to R6C9B.A1       n10
+CTOF_DEL    ---     0.371       R6C9B.A1 to       R6C9B.F1 SLICE_75
+ROUTE         4     0.528       R6C9B.F1 to R6C9B.C0       n2298
+CTOF_DEL    ---     0.371       R6C9B.C0 to       R6C9B.F0 SLICE_75
+ROUTE         1     1.155       R6C9B.F0 to R9C9A.D1       n11
+CTOF_DEL    ---     0.371       R9C9A.D1 to       R9C9A.F1 SLICE_77
+ROUTE         2     0.903       R9C9A.F1 to R10C9A.C1      n2111
+CTOF_DEL    ---     0.371      R10C9A.C1 to      R10C9A.F1 SLICE_100
+ROUTE         1     0.703      R10C9A.F1 to R9C9D.CE       RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    7.809   (30.9% logic, 69.1% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R8C8C.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_85:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R9C9D.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 8.079ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i15  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)
+
+   Delay:               7.677ns  (26.6% logic, 73.4% route), 5 logic levels.
+
+ Constraint Details:
+
+      7.677ns physical path delay SLICE_7 to SLICE_56 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 8.079ns
+
+ Physical Path Details:
+
+      Data path SLICE_7 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C8D.CLK to       R8C8D.Q1 SLICE_7 (from RCLK_c)
+ROUTE         3     1.475       R8C8D.Q1 to R8C9D.B1       FS_15
+CTOF_DEL    ---     0.371       R8C9D.B1 to       R8C9D.F1 SLICE_78
+ROUTE         3     0.989       R8C9D.F1 to R8C9B.A1       n10
+CTOF_DEL    ---     0.371       R8C9B.A1 to       R8C9B.F1 SLICE_94
+ROUTE         1     1.384       R8C9B.F1 to R9C9A.A1       n2292
+CTOF_DEL    ---     0.371       R9C9A.A1 to       R9C9A.F1 SLICE_77
+ROUTE         2     0.712       R9C9A.F1 to R9C9A.B0       n2111
+CTOF_DEL    ---     0.371       R9C9A.B0 to       R9C9A.F0 SLICE_77
+ROUTE         1     1.073       R9C9A.F0 to R9C8D.CE       RCLK_c_enable_7 (to RCLK_c)
+                  --------
+                    7.677   (26.6% logic, 73.4% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_7:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R8C8D.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R9C8D.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 8.092ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i12  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)
+
+   Delay:               7.664ns  (31.5% logic, 68.5% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.664ns physical path delay SLICE_8 to SLICE_56 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 8.092ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C8C.CLK to       R8C8C.Q0 SLICE_8 (from RCLK_c)
+ROUTE         3     0.724       R8C8C.Q0 to R8C9D.D1       FS_12
+CTOF_DEL    ---     0.371       R8C9D.D1 to       R8C9D.F1 SLICE_78
+ROUTE         3     1.057       R8C9D.F1 to R6C9B.A1       n10
+CTOF_DEL    ---     0.371       R6C9B.A1 to       R6C9B.F1 SLICE_75
+ROUTE         4     0.528       R6C9B.F1 to R6C9B.C0       n2298
+CTOF_DEL    ---     0.371       R6C9B.C0 to       R6C9B.F0 SLICE_75
+ROUTE         1     1.155       R6C9B.F0 to R9C9A.D1       n11
+CTOF_DEL    ---     0.371       R9C9A.D1 to       R9C9A.F1 SLICE_77
+ROUTE         2     0.712       R9C9A.F1 to R9C9A.B0       n2111
+CTOF_DEL    ---     0.371       R9C9A.B0 to       R9C9A.F0 SLICE_77
+ROUTE         1     1.073       R9C9A.F0 to R9C8D.CE       RCLK_c_enable_7 (to RCLK_c)
+                  --------
+                    7.664   (31.5% logic, 68.5% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R8C8C.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R9C8D.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 8.177ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i1  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)
+
+   Delay:               7.579ns  (27.0% logic, 73.0% route), 5 logic levels.
+
+ Constraint Details:
+
+      7.579ns physical path delay SLICE_5 to SLICE_56 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 8.177ns
+
+ Physical Path Details:
+
+      Data path SLICE_5 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C7A.CLK to       R8C7A.Q1 SLICE_5 (from RCLK_c)
+ROUTE         2     1.108       R8C7A.Q1 to R7C7D.B1       FS_1
+CTOF_DEL    ---     0.371       R7C7D.B1 to       R7C7D.F1 SLICE_68
+ROUTE         1     1.487       R7C7D.F1 to R6C9B.A0       n2164
+CTOF_DEL    ---     0.371       R6C9B.A0 to       R6C9B.F0 SLICE_75
+ROUTE         1     1.155       R6C9B.F0 to R9C9A.D1       n11
+CTOF_DEL    ---     0.371       R9C9A.D1 to       R9C9A.F1 SLICE_77
+ROUTE         2     0.712       R9C9A.F1 to R9C9A.B0       n2111
+CTOF_DEL    ---     0.371       R9C9A.B0 to       R9C9A.F0 SLICE_77
+ROUTE         1     1.073       R9C9A.F0 to R9C8D.CE       RCLK_c_enable_7 (to RCLK_c)
+                  --------
+                    7.579   (27.0% logic, 73.0% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R8C7A.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R9C8D.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+ 
+
+Passed: The following path meets requirements by 8.243ns
+ 
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_571__i2  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)
+
+   Delay:               7.513ns  (27.2% logic, 72.8% route), 5 logic levels.
+
+ Constraint Details:
+
+      7.513ns physical path delay SLICE_4 to SLICE_56 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 15.756ns) by 8.243ns
+
+ Physical Path Details:
+
+      Data path SLICE_4 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R8C7B.CLK to       R8C7B.Q0 SLICE_4 (from RCLK_c)
+ROUTE         2     1.042       R8C7B.Q0 to R7C7D.A1       FS_2
+CTOF_DEL    ---     0.371       R7C7D.A1 to       R7C7D.F1 SLICE_68
+ROUTE         1     1.487       R7C7D.F1 to R6C9B.A0       n2164
+CTOF_DEL    ---     0.371       R6C9B.A0 to       R6C9B.F0 SLICE_75
+ROUTE         1     1.155       R6C9B.F0 to R9C9A.D1       n11
+CTOF_DEL    ---     0.371       R9C9A.D1 to       R9C9A.F1 SLICE_77
+ROUTE         2     0.712       R9C9A.F1 to R9C9A.B0       n2111
+CTOF_DEL    ---     0.371       R9C9A.B0 to       R9C9A.F0 SLICE_77
+ROUTE         1     1.073       R9C9A.F0 to R9C8D.CE       RCLK_c_enable_7 (to RCLK_c)
+                  --------
+                    7.513   (27.2% logic, 72.8% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_4:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R8C7B.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        39     1.425       86.PADDI to R9C8D.CLK      RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:    8.659ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.999ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_368  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_55 and
+      5.013ns delay SLICE_55 to RA[10] (totaling 7.501ns) meets
+     12.500ns offset RCLK to RA[10] by 4.999ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to R2C5A.CLK      RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_55 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C5A.CLK to       R2C5A.Q0 SLICE_55 (from RCLK_c)
+ROUTE         1     0.817       R2C5A.Q0 to 87.PADDO       n974
+DOPAD_DEL   ---     3.636       87.PADDO to         87.PAD RA[10]
+                  --------
+                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
+
+Report:    7.501ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 6.396ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_368  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     4.797ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      1.599ns delay RCLK to SLICE_55 and
+      4.797ns delay SLICE_55 to RA[10] (totaling 6.396ns) meets
+      0.000ns hold offset RCLK to RA[10] by 6.396ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.732       86.PADDI to R2C5A.CLK      RCLK_c
+                  --------
+                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_55 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C5A.CLK to       R2C5A.Q0 SLICE_55 (from RCLK_c)
+ROUTE         1     0.646       R2C5A.Q0 to 87.PADDO       n974
+DOPAD_DEL   ---     3.636       87.PADDO to         87.PAD RA[10]
+                  --------
+                    4.797   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    6.396ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.477ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     8.535ns  (53.5% logic, 46.5% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      8.535ns delay SLICE_64 to RA[9] (totaling 11.023ns) meets
+     12.500ns offset RCLK to RA[9] by 1.477ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.796       R2C6A.Q0 to R6C9A.D1       nRowColSel
+CTOF_DEL    ---     0.371       R6C9A.D1 to       R6C9A.F1 SLICE_87
+ROUTE         1     2.172       R6C9A.F1 to 85.PADDO       RA_c_9
+DOPAD_DEL   ---     3.636       85.PADDO to         85.PAD RA[9]
+                  --------
+                    8.535   (53.5% logic, 46.5% route), 3 logic levels.
+
+Report:   11.023ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 9.323ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     7.724ns  (57.6% logic, 42.4% route), 3 logic levels.
+
+   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      1.599ns delay RCLK to SLICE_64 and
+      7.724ns delay SLICE_64 to RA[9] (totaling 9.323ns) meets
+      0.000ns hold offset RCLK to RA[9] by 9.323ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.549       R2C6A.Q0 to R6C9A.D1       nRowColSel
+CTOF_DEL    ---     0.301       R6C9A.D1 to       R6C9A.F1 SLICE_87
+ROUTE         1     1.723       R6C9A.F1 to 85.PADDO       RA_c_9
+DOPAD_DEL   ---     3.636       85.PADDO to         85.PAD RA[9]
+                  --------
+                    7.724   (57.6% logic, 42.4% route), 3 logic levels.
+
+Report:    9.323ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.460ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     7.552ns  (60.5% logic, 39.5% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      7.552ns delay SLICE_64 to RA[8] (totaling 10.040ns) meets
+     12.500ns offset RCLK to RA[8] by 2.460ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.459       R2C6A.Q0 to R2C2A.C0       nRowColSel
+CTOF_DEL    ---     0.371       R2C2A.C0 to       R2C2A.F0 SLICE_98
+ROUTE         1     1.526       R2C2A.F0 to 96.PADDO       RA_c_8
+DOPAD_DEL   ---     3.636       96.PADDO to         96.PAD RA[8]
+                  --------
+                    7.552   (60.5% logic, 39.5% route), 3 logic levels.
+
+Report:   10.040ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 8.446ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     6.847ns  (65.0% logic, 35.0% route), 3 logic levels.
+
+   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      1.599ns delay RCLK to SLICE_64 and
+      6.847ns delay SLICE_64 to RA[8] (totaling 8.446ns) meets
+      0.000ns hold offset RCLK to RA[8] by 8.446ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.230       R2C6A.Q0 to R2C2A.C0       nRowColSel
+CTOF_DEL    ---     0.301       R2C2A.C0 to       R2C2A.F0 SLICE_98
+ROUTE         1     1.165       R2C2A.F0 to 96.PADDO       RA_c_8
+DOPAD_DEL   ---     3.636       96.PADDO to         96.PAD RA[8]
+                  --------
+                    6.847   (65.0% logic, 35.0% route), 3 logic levels.
+
+Report:    8.446ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.106ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     7.906ns  (57.8% logic, 42.2% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      7.906ns delay SLICE_64 to RA[7] (totaling 10.394ns) meets
+     12.500ns offset RCLK to RA[7] by 2.106ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.895       R2C6A.Q0 to R2C6A.C1       nRowColSel
+CTOF_DEL    ---     0.371       R2C6A.C1 to       R2C6A.F1 SLICE_64
+ROUTE         1     2.444       R2C6A.F1 to 100.PADDO      RA_c_7
+DOPAD_DEL   ---     3.636      100.PADDO to        100.PAD RA[7]
+                  --------
+                    7.906   (57.8% logic, 42.2% route), 3 logic levels.
+
+Report:   10.394ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 8.766ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     7.167ns  (62.1% logic, 37.9% route), 3 logic levels.
+
+   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      1.599ns delay RCLK to SLICE_64 and
+      7.167ns delay SLICE_64 to RA[7] (totaling 8.766ns) meets
+      0.000ns hold offset RCLK to RA[7] by 8.766ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     0.741       R2C6A.Q0 to R2C6A.C1       nRowColSel
+CTOF_DEL    ---     0.301       R2C6A.C1 to       R2C6A.F1 SLICE_64
+ROUTE         1     1.974       R2C6A.F1 to 100.PADDO      RA_c_7
+DOPAD_DEL   ---     3.636      100.PADDO to        100.PAD RA[7]
+                  --------
+                    7.167   (62.1% logic, 37.9% route), 3 logic levels.
+
+Report:    8.766ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.002ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     8.010ns  (57.0% logic, 43.0% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      8.010ns delay SLICE_64 to RA[6] (totaling 10.498ns) meets
+     12.500ns offset RCLK to RA[6] by 2.002ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.459       R2C6A.Q0 to R2C2A.C1       nRowColSel
+CTOF_DEL    ---     0.371       R2C2A.C1 to       R2C2A.F1 SLICE_98
+ROUTE         1     1.984       R2C2A.F1 to 91.PADDO       RA_c_6
+DOPAD_DEL   ---     3.636       91.PADDO to         91.PAD RA[6]
+                  --------
+                    8.010   (57.0% logic, 43.0% route), 3 logic levels.
+
+Report:   10.498ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 8.813ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     7.214ns  (61.7% logic, 38.3% route), 3 logic levels.
+
+   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      1.599ns delay RCLK to SLICE_64 and
+      7.214ns delay SLICE_64 to RA[6] (totaling 8.813ns) meets
+      0.000ns hold offset RCLK to RA[6] by 8.813ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.230       R2C6A.Q0 to R2C2A.C1       nRowColSel
+CTOF_DEL    ---     0.301       R2C2A.C1 to       R2C2A.F1 SLICE_98
+ROUTE         1     1.532       R2C2A.F1 to 91.PADDO       RA_c_6
+DOPAD_DEL   ---     3.636       91.PADDO to         91.PAD RA[6]
+                  --------
+                    7.214   (61.7% logic, 38.3% route), 3 logic levels.
+
+Report:    8.813ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.141ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     8.871ns  (51.5% logic, 48.5% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      8.871ns delay SLICE_64 to RA[5] (totaling 11.359ns) meets
+     12.500ns offset RCLK to RA[5] by 1.141ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.736       R2C6A.Q0 to R8C9C.D1       nRowColSel
+CTOF_DEL    ---     0.371       R8C9C.D1 to       R8C9C.F1 SLICE_95
+ROUTE         1     2.568       R8C9C.F1 to 95.PADDO       RA_c_5
+DOPAD_DEL   ---     3.636       95.PADDO to         95.PAD RA[5]
+                  --------
+                    8.871   (51.5% logic, 48.5% route), 3 logic levels.
+
+Report:   11.359ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 9.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     7.960ns  (55.9% logic, 44.1% route), 3 logic levels.
+
+   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      1.599ns delay RCLK to SLICE_64 and
+      7.960ns delay SLICE_64 to RA[5] (totaling 9.559ns) meets
+      0.000ns hold offset RCLK to RA[5] by 9.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.466       R2C6A.Q0 to R8C9C.D1       nRowColSel
+CTOF_DEL    ---     0.301       R8C9C.D1 to       R8C9C.F1 SLICE_95
+ROUTE         1     2.042       R8C9C.F1 to 95.PADDO       RA_c_5
+DOPAD_DEL   ---     3.636       95.PADDO to         95.PAD RA[5]
+                  --------
+                    7.960   (55.9% logic, 44.1% route), 3 logic levels.
+
+Report:    9.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.458ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     7.554ns  (60.5% logic, 39.5% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      7.554ns delay SLICE_64 to RA[4] (totaling 10.042ns) meets
+     12.500ns offset RCLK to RA[4] by 2.458ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.459       R2C6A.Q0 to R2C2C.C1       nRowColSel
+CTOF_DEL    ---     0.371       R2C2C.C1 to       R2C2C.F1 SLICE_93
+ROUTE         1     1.528       R2C2C.F1 to 99.PADDO       RA_c_4
+DOPAD_DEL   ---     3.636       99.PADDO to         99.PAD RA[4]
+                  --------
+                    7.554   (60.5% logic, 39.5% route), 3 logic levels.
+
+Report:   10.042ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 8.445ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     6.846ns  (65.0% logic, 35.0% route), 3 logic levels.
+
+   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      1.599ns delay RCLK to SLICE_64 and
+      6.846ns delay SLICE_64 to RA[4] (totaling 8.445ns) meets
+      0.000ns hold offset RCLK to RA[4] by 8.445ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.230       R2C6A.Q0 to R2C2C.C1       nRowColSel
+CTOF_DEL    ---     0.301       R2C2C.C1 to       R2C2C.F1 SLICE_93
+ROUTE         1     1.164       R2C2C.F1 to 99.PADDO       RA_c_4
+DOPAD_DEL   ---     3.636       99.PADDO to         99.PAD RA[4]
+                  --------
+                    6.846   (65.0% logic, 35.0% route), 3 logic levels.
+
+Report:    8.445ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.216ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     7.796ns  (58.6% logic, 41.4% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      7.796ns delay SLICE_64 to RA[3] (totaling 10.284ns) meets
+     12.500ns offset RCLK to RA[3] by 2.216ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.245       R2C6A.Q0 to R2C3A.D1       nRowColSel
+CTOF_DEL    ---     0.371       R2C3A.D1 to       R2C3A.F1 SLICE_92
+ROUTE         1     1.984       R2C3A.F1 to 97.PADDO       RA_c_3
+DOPAD_DEL   ---     3.636       97.PADDO to         97.PAD RA[3]
+                  --------
+                    7.796   (58.6% logic, 41.4% route), 3 logic levels.
+
+Report:   10.284ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 8.599ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     7.000ns  (63.6% logic, 36.4% route), 3 logic levels.
+
+   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      1.599ns delay RCLK to SLICE_64 and
+      7.000ns delay SLICE_64 to RA[3] (totaling 8.599ns) meets
+      0.000ns hold offset RCLK to RA[3] by 8.599ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.016       R2C6A.Q0 to R2C3A.D1       nRowColSel
+CTOF_DEL    ---     0.301       R2C3A.D1 to       R2C3A.F1 SLICE_92
+ROUTE         1     1.532       R2C3A.F1 to 97.PADDO       RA_c_3
+DOPAD_DEL   ---     3.636       97.PADDO to         97.PAD RA[3]
+                  --------
+                    7.000   (63.6% logic, 36.4% route), 3 logic levels.
+
+Report:    8.599ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.999ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     8.013ns  (57.0% logic, 43.0% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      8.013ns delay SLICE_64 to RA[2] (totaling 10.501ns) meets
+     12.500ns offset RCLK to RA[2] by 1.999ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.459       R2C6A.Q0 to R2C2B.C0       nRowColSel
+CTOF_DEL    ---     0.371       R2C2B.C0 to       R2C2B.F0 SLICE_90
+ROUTE         1     1.987       R2C2B.F0 to 94.PADDO       RA_c_2
+DOPAD_DEL   ---     3.636       94.PADDO to         94.PAD RA[2]
+                  --------
+                    8.013   (57.0% logic, 43.0% route), 3 logic levels.
+
+Report:   10.501ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 8.849ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     7.250ns  (61.4% logic, 38.6% route), 3 logic levels.
+
+   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      1.599ns delay RCLK to SLICE_64 and
+      7.250ns delay SLICE_64 to RA[2] (totaling 8.849ns) meets
+      0.000ns hold offset RCLK to RA[2] by 8.849ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.230       R2C6A.Q0 to R2C2B.C0       nRowColSel
+CTOF_DEL    ---     0.301       R2C2B.C0 to       R2C2B.F0 SLICE_90
+ROUTE         1     1.568       R2C2B.F0 to 94.PADDO       RA_c_2
+DOPAD_DEL   ---     3.636       94.PADDO to         94.PAD RA[2]
+                  --------
+                    7.250   (61.4% logic, 38.6% route), 3 logic levels.
+
+Report:    8.849ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.216ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     7.796ns  (58.6% logic, 41.4% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      7.796ns delay SLICE_64 to RA[1] (totaling 10.284ns) meets
+     12.500ns offset RCLK to RA[1] by 2.216ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.245       R2C6A.Q0 to R2C3A.D0       nRowColSel
+CTOF_DEL    ---     0.371       R2C3A.D0 to       R2C3A.F0 SLICE_92
+ROUTE         1     1.984       R2C3A.F0 to 89.PADDO       RA_c_1
+DOPAD_DEL   ---     3.636       89.PADDO to         89.PAD RA[1]
+                  --------
+                    7.796   (58.6% logic, 41.4% route), 3 logic levels.
+
+Report:   10.284ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 8.599ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     7.000ns  (63.6% logic, 36.4% route), 3 logic levels.
+
+   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      1.599ns delay RCLK to SLICE_64 and
+      7.000ns delay SLICE_64 to RA[1] (totaling 8.599ns) meets
+      0.000ns hold offset RCLK to RA[1] by 8.599ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.016       R2C6A.Q0 to R2C3A.D0       nRowColSel
+CTOF_DEL    ---     0.301       R2C3A.D0 to       R2C3A.F0 SLICE_92
+ROUTE         1     1.532       R2C3A.F0 to 89.PADDO       RA_c_1
+DOPAD_DEL   ---     3.636       89.PADDO to         89.PAD RA[1]
+                  --------
+                    7.000   (63.6% logic, 36.4% route), 3 logic levels.
+
+Report:    8.599ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.454ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     7.558ns  (60.4% logic, 39.6% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      7.558ns delay SLICE_64 to RA[0] (totaling 10.046ns) meets
+     12.500ns offset RCLK to RA[0] by 2.454ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.459       R2C6A.Q0 to R2C2C.C0       nRowColSel
+CTOF_DEL    ---     0.371       R2C2C.C0 to       R2C2C.F0 SLICE_93
+ROUTE         1     1.532       R2C2C.F0 to 98.PADDO       RA_c_0
+DOPAD_DEL   ---     3.636       98.PADDO to         98.PAD RA[0]
+                  --------
+                    7.558   (60.4% logic, 39.6% route), 3 logic levels.
+
+Report:   10.046ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 8.442ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     6.843ns  (65.1% logic, 34.9% route), 3 logic levels.
+
+   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      1.599ns delay RCLK to SLICE_64 and
+      6.843ns delay SLICE_64 to RA[0] (totaling 8.442ns) meets
+      0.000ns hold offset RCLK to RA[0] by 8.442ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.230       R2C6A.Q0 to R2C2C.C0       nRowColSel
+CTOF_DEL    ---     0.301       R2C2C.C0 to       R2C2C.F0 SLICE_93
+ROUTE         1     1.161       R2C2C.F0 to 98.PADDO       RA_c_0
+DOPAD_DEL   ---     3.636       98.PADDO to         98.PAD RA[0]
+                  --------
+                    6.843   (65.1% logic, 34.9% route), 3 logic levels.
+
+Report:    8.442ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.999ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_364  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_60 and
+      5.013ns delay SLICE_60 to nRCS (totaling 7.501ns) meets
+     12.500ns offset RCLK to nRCS by 4.999ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to R2C9C.CLK      RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_60 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C9C.CLK to       R2C9C.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1     0.817       R2C9C.Q0 to 77.PADDO       nRCS_c
+DOPAD_DEL   ---     3.636       77.PADDO to         77.PAD nRCS
+                  --------
+                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
+
+Report:    7.501ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 6.396ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_364  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     4.797ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      1.599ns delay RCLK to SLICE_60 and
+      4.797ns delay SLICE_60 to nRCS (totaling 6.396ns) meets
+      0.000ns hold offset RCLK to nRCS by 6.396ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.732       86.PADDI to R2C9C.CLK      RCLK_c
+                  --------
+                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_60 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C9C.CLK to       R2C9C.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1     0.646       R2C9C.Q0 to 77.PADDO       nRCS_c
+DOPAD_DEL   ---     3.636       77.PADDO to         77.PAD nRCS
+                  --------
+                    4.797   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    6.396ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.999ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_363  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_34 and
+      5.013ns delay SLICE_34 to RCKE (totaling 7.501ns) meets
+     12.500ns offset RCLK to RCKE by 4.999ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to R2C7C.CLK      RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_34 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C7C.CLK to       R2C7C.Q0 SLICE_34 (from RCLK_c)
+ROUTE         4     0.817       R2C7C.Q0 to 82.PADDO       RCKE_c
+DOPAD_DEL   ---     3.636       82.PADDO to         82.PAD RCKE
+                  --------
+                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
+
+Report:    7.501ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 6.396ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_363  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     4.797ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      1.599ns delay RCLK to SLICE_34 and
+      4.797ns delay SLICE_34 to RCKE (totaling 6.396ns) meets
+      0.000ns hold offset RCLK to RCKE by 6.396ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.732       86.PADDI to R2C7C.CLK      RCLK_c
+                  --------
+                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_34 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C7C.CLK to       R2C7C.Q0 SLICE_34 (from RCLK_c)
+ROUTE         4     0.646       R2C7C.Q0 to 82.PADDO       RCKE_c
+DOPAD_DEL   ---     3.636       82.PADDO to         82.PAD RCKE
+                  --------
+                    4.797   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    6.396ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.833ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_367  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     6.179ns  (67.9% logic, 32.1% route), 2 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_63 and
+      6.179ns delay SLICE_63 to nRWE (totaling 8.667ns) meets
+     12.500ns offset RCLK to nRWE by 3.833ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to R2C7A.CLK      RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_63 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C7A.CLK to       R2C7A.Q0 SLICE_63 (from RCLK_c)
+ROUTE         1     1.983       R2C7A.Q0 to 72.PADDO       nRWE_c
+DOPAD_DEL   ---     3.636       72.PADDO to         72.PAD nRWE
+                  --------
+                    6.179   (67.9% logic, 32.1% route), 2 logic levels.
+
+Report:    8.667ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 7.321ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_367  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     5.722ns  (72.5% logic, 27.5% route), 2 logic levels.
+
+   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      1.599ns delay RCLK to SLICE_63 and
+      5.722ns delay SLICE_63 to nRWE (totaling 7.321ns) meets
+      0.000ns hold offset RCLK to nRWE by 7.321ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.732       86.PADDI to R2C7A.CLK      RCLK_c
+                  --------
+                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_63 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C7A.CLK to       R2C7A.Q0 SLICE_63 (from RCLK_c)
+ROUTE         1     1.571       R2C7A.Q0 to 72.PADDO       nRWE_c
+DOPAD_DEL   ---     3.636       72.PADDO to         72.PAD nRWE
+                  --------
+                    5.722   (72.5% logic, 27.5% route), 2 logic levels.
+
+Report:    7.321ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.813ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_365  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     6.199ns  (67.7% logic, 32.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_61 and
+      6.199ns delay SLICE_61 to nRRAS (totaling 8.687ns) meets
+     12.500ns offset RCLK to nRRAS by 3.813ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to R4C9B.CLK      RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_61 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R4C9B.CLK to       R4C9B.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2     2.003       R4C9B.Q0 to 73.PADDO       nRRAS_c
+DOPAD_DEL   ---     3.636       73.PADDO to         73.PAD nRRAS
+                  --------
+                    6.199   (67.7% logic, 32.3% route), 2 logic levels.
+
+Report:    8.687ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 7.334ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_365  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     5.735ns  (72.4% logic, 27.6% route), 2 logic levels.
+
+   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      1.599ns delay RCLK to SLICE_61 and
+      5.735ns delay SLICE_61 to nRRAS (totaling 7.334ns) meets
+      0.000ns hold offset RCLK to nRRAS by 7.334ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.732       86.PADDI to R4C9B.CLK      RCLK_c
+                  --------
+                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_61 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R4C9B.CLK to       R4C9B.Q0 SLICE_61 (from RCLK_c)
+ROUTE         2     1.584       R4C9B.Q0 to 73.PADDO       nRRAS_c
+DOPAD_DEL   ---     3.636       73.PADDO to         73.PAD nRRAS
+                  --------
+                    5.735   (72.4% logic, 27.6% route), 2 logic levels.
+
+Report:    7.334ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.999ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_366  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_58 and
+      5.013ns delay SLICE_58 to nRCAS (totaling 7.501ns) meets
+     12.500ns offset RCLK to nRCAS by 4.999ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to R2C9B.CLK      RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_58 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C9B.CLK to       R2C9B.Q0 SLICE_58 (from RCLK_c)
+ROUTE         1     0.817       R2C9B.Q0 to 78.PADDO       nRCAS_c
+DOPAD_DEL   ---     3.636       78.PADDO to         78.PAD nRCAS
+                  --------
+                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
+
+Report:    7.501ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 6.396ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_366  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     4.797ns  (86.5% logic, 13.5% route), 2 logic levels.
+
+   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      1.599ns delay RCLK to SLICE_58 and
+      4.797ns delay SLICE_58 to nRCAS (totaling 6.396ns) meets
+      0.000ns hold offset RCLK to nRCAS by 6.396ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_58:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.732       86.PADDI to R2C9B.CLK      RCLK_c
+                  --------
+                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_58 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C9B.CLK to       R2C9B.Q0 SLICE_58 (from RCLK_c)
+ROUTE         1     0.646       R2C9B.Q0 to 78.PADDO       nRCAS_c
+DOPAD_DEL   ---     3.636       78.PADDO to         78.PAD nRCAS
+                  --------
+                    4.797   (86.5% logic, 13.5% route), 2 logic levels.
+
+Report:    6.396ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.989ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     8.023ns  (56.9% logic, 43.1% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      8.023ns delay SLICE_64 to RDQMH (totaling 10.511ns) meets
+     12.500ns offset RCLK to RDQMH by 1.989ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.796       R2C6A.Q0 to R6C9A.D0       nRowColSel
+CTOF_DEL    ---     0.371       R6C9A.D0 to       R6C9A.F0 SLICE_87
+ROUTE         1     1.660       R6C9A.F0 to 76.PADDO       RDQMH_c
+DOPAD_DEL   ---     3.636       76.PADDO to         76.PAD RDQMH
+                  --------
+                    8.023   (56.9% logic, 43.1% route), 3 logic levels.
+
+Report:   10.511ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 8.888ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     7.289ns  (61.1% logic, 38.9% route), 3 logic levels.
+
+   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      1.599ns delay RCLK to SLICE_64 and
+      7.289ns delay SLICE_64 to RDQMH (totaling 8.888ns) meets
+      0.000ns hold offset RCLK to RDQMH by 8.888ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.549       R2C6A.Q0 to R6C9A.D0       nRowColSel
+CTOF_DEL    ---     0.301       R6C9A.D0 to       R6C9A.F0 SLICE_87
+ROUTE         1     1.288       R6C9A.F0 to 76.PADDO       RDQMH_c
+DOPAD_DEL   ---     3.636       76.PADDO to         76.PAD RDQMH
+                  --------
+                    7.289   (61.1% logic, 38.9% route), 3 logic levels.
+
+Report:    8.888ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.892ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     7.120ns  (64.1% logic, 35.9% route), 3 logic levels.
+
+   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
+
+ Constraint Details:
+      2.488ns delay RCLK to SLICE_64 and
+      7.120ns delay SLICE_64 to RDQML (totaling 9.608ns) meets
+     12.500ns offset RCLK to RDQML by 2.892ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
+ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.736       R2C6A.Q0 to R8C9C.D0       nRowColSel
+CTOF_DEL    ---     0.371       R8C9C.D0 to       R8C9C.F0 SLICE_95
+ROUTE         1     0.817       R8C9C.F0 to 61.PADDO       RDQML_c
+DOPAD_DEL   ---     3.636       61.PADDO to         61.PAD RDQML
+                  --------
+                    7.120   (64.1% logic, 35.9% route), 3 logic levels.
+
+Report:    9.608ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 8.163ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     6.564ns  (67.8% logic, 32.2% route), 3 logic levels.
+
+   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
+
+ Constraint Details:
+      1.599ns delay RCLK to SLICE_64 and
+      6.564ns delay SLICE_64 to RDQML (totaling 8.163ns) meets
+      0.000ns hold offset RCLK to RDQML by 8.163ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_64:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
+ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
+                  --------
+                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
+
+      Data path SLICE_64 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
+ROUTE        13     1.466       R2C6A.Q0 to R8C9C.D0       nRowColSel
+CTOF_DEL    ---     0.301       R8C9C.D0 to       R8C9C.F0 SLICE_95
+ROUTE         1     0.646       R8C9C.F0 to 61.PADDO       RDQML_c
+DOPAD_DEL   ---     3.636       61.PADDO to         61.PAD RDQML
+                  --------
+                    6.564   (67.8% logic, 32.2% route), 3 logic levels.
+
+Report:    8.163ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |   350.000 ns|    22.150 ns|   7  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |    16.000 ns|     8.659 ns|   6  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     7.501 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     6.396 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    11.023 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     9.323 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.040 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.446 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.394 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.766 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.498 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.813 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    11.359 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     9.559 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.042 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.445 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.284 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.599 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.501 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.849 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.284 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.599 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.046 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.442 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     7.501 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     6.396 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     7.501 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     6.396 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     8.667 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     7.321 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     8.687 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     7.334 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     7.501 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     6.396 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.511 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.888 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     9.608 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.163 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 538 paths, 6 nets, and 440 connections (71.54% coverage)
+
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/automake.log b/CPLD/LCMXO/LCMXO640C/impl1/automake.log
new file mode 100644
index 0000000..1165506
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/automake.log
@@ -0,0 +1,528 @@
+
+ibisgen "RAM2GS_LCMXO640C_impl1.pad" "C:/lscc/diamond/3.12/cae_library/ibis/machxo.ibs"   
+IBIS Models Generator: Lattice Diamond (64-bit) 3.12.0.240.2
+
+Mon Aug 16 21:36:33 2021
+
+Comp: CROW[0]
+ Site: 32
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: CROW[1]
+ Site: 34
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: Din[0]
+ Site: 21
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: Din[1]
+ Site: 15
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: Din[2]
+ Site: 14
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: Din[3]
+ Site: 16
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: Din[4]
+ Site: 18
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: Din[5]
+ Site: 17
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: Din[6]
+ Site: 20
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: Din[7]
+ Site: 19
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: Dout[0]
+ Site: 1
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[1]
+ Site: 7
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[2]
+ Site: 8
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[3]
+ Site: 6
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[4]
+ Site: 4
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[5]
+ Site: 5
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[6]
+ Site: 2
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[7]
+ Site: 3
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: LED
+ Site: 57
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=16mA 
+ SLEW=SLOW 
+-----------------------
+Comp: MAin[0]
+ Site: 23
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: MAin[1]
+ Site: 38
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: MAin[2]
+ Site: 37
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: MAin[3]
+ Site: 47
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: MAin[4]
+ Site: 46
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: MAin[5]
+ Site: 45
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: MAin[6]
+ Site: 49
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: MAin[7]
+ Site: 44
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: MAin[8]
+ Site: 50
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: MAin[9]
+ Site: 51
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: PHI2
+ Site: 39
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: RA[0]
+ Site: 98
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[10]
+ Site: 87
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[11]
+ Site: 79
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[1]
+ Site: 89
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[2]
+ Site: 94
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[3]
+ Site: 97
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[4]
+ Site: 99
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[5]
+ Site: 95
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[6]
+ Site: 91
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[7]
+ Site: 100
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[8]
+ Site: 96
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[9]
+ Site: 85
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RBA[0]
+ Site: 63
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RBA[1]
+ Site: 83
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RCKE
+ Site: 82
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RCLK
+ Site: 86
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: RDQMH
+ Site: 76
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RDQML
+ Site: 61
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RD[0]
+ Site: 64
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[1]
+ Site: 65
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[2]
+ Site: 66
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[3]
+ Site: 67
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[4]
+ Site: 68
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[5]
+ Site: 69
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[6]
+ Site: 70
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: RD[7]
+ Site: 71
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+ PULL=KEEPER 
+-----------------------
+Comp: UFMCLK
+ Site: 58
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: UFMSDI
+ Site: 56
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: UFMSDO
+ Site: 55
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+ PULL=KEEPER 
+-----------------------
+Comp: nCCAS
+ Site: 27
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: nCRAS
+ Site: 43
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: nFWE
+ Site: 22
+ Type: IN
+ IO_TYPE=LVTTL33 
+ SLEW=FAST 
+-----------------------
+Comp: nRCAS
+ Site: 78
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: nRCS
+ Site: 77
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: nRRAS
+ Site: 73
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: nRWE
+ Site: 72
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: nUFMCS
+ Site: 53
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Created design models.
+
+
+Generating: C:\Users\Dog\Documents\GitHub\RAM2GS\CPLD\LCMXO\LCMXO640C\impl1\IBIS\RAM2GS_LCMXO640C_im~.ibs
+
+
+    
+
+tmcheck -par "RAM2GS_LCMXO640C_impl1.par" 
+
+bitgen -w "RAM2GS_LCMXO640C_impl1.ncd" -f "RAM2GS_LCMXO640C_impl1.t2b" "RAM2GS_LCMXO640C_impl1.prf"
+
+
+BITGEN: Bitstream Generator Diamond (64-bit) 3.12.0.240.2
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+
+Loading design for application Bitgen from file RAM2GS_LCMXO640C_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 3
+Loading device for application Bitgen from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+
+Running DRC.
+DRC detected 0 errors and 0 warnings.
+Reading Preference File from RAM2GS_LCMXO640C_impl1.prf.
+
+Preference Summary:
++---------------------------------+---------------------------------+
+|  Preference                     |  Current Setting                |
++---------------------------------+---------------------------------+
+|                  CONFIG_SECURE  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                          INBUF  |                           ON**  |
++---------------------------------+---------------------------------+
+|                             ES  |                           No**  |
++---------------------------------+---------------------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+
+Creating bit map...
+Saving bit stream in "RAM2GS_LCMXO640C_impl1.bit".
+Total CPU Time: 0 secs 
+Total REAL Time: 0 secs 
+Peak Memory Usage: 46 MB
+
+ddtcmd -dev LCMXO640C-XXT100 -if "RAM2GS_LCMXO640C_impl1.bit" -oft -jed -of "RAM2GS_LCMXO640C_impl1.jed"  -comment "RAM2GS_LCMXO640C_impl1.alt" 
+Lattice Diamond Deployment Tool 3.12 Command Line
+
+Loading Programmer Device Database...
+
+Generating JED.....
+Device Name: LCMXO640C-XXT100
+Reading Input File: RAM2GS_LCMXO640C_impl1.bit
+Output File: RAM2GS_LCMXO640C_impl1.jed
+Comment file RAM2GS_LCMXO640C_impl1.alt.
+Generating JEDEC.....
+File RAM2GS_LCMXO640C_impl1.jed generated successfully.
+Lattice Diamond Deployment Tool has exited successfully.
+
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/hdla_gen_hierarchy.html b/CPLD/LCMXO/LCMXO640C/impl1/hdla_gen_hierarchy.html
new file mode 100644
index 0000000..ef94b54
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/hdla_gen_hierarchy.html
@@ -0,0 +1,9 @@
+         	                                   	                                                	                                                 	                                                  	
    Setting log file to 'C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/impl1/hdla_gen_hierarchy.html'.
+Starting: parse design source files
+(VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v'
+(VERI-1482) Analyzing Verilog file 'C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v'
+INFO - C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v(1,8-1,14) (VERI-1018) compiling module 'RAM2GS'
+INFO - C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v(1,1-397,10) (VERI-9000) elaborating module 'RAM2GS'
+Done: design load finished with (0) errors, and (0) warnings
+
+
    
\ No newline at end of file
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1.ior b/CPLD/LCMXO/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1.ior
new file mode 100644
index 0000000..4473ca1
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1.ior
@@ -0,0 +1,137 @@
+Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 4
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 5
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: M
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+// Design: RAM2GS
+// Package: TQFP100
+// ncd File: ram2gs_lcmxo640c_impl1.ncd
+// Version: Diamond (64-bit) 3.12.0.240.2
+// Written on Mon Aug 16 21:33:38 2021
+// M: Minimum Performance Grade
+// iotiming RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml
+
+I/O Timing Report (All units are in ns)
+
+Worst Case Results across Performance Grades (M, 5, 4, 3):
+
+// Input Setup and Hold Times
+
+Port    Clock Edge  Setup Performance_Grade  Hold Performance_Grade
+----------------------------------------------------------------------
+CROW[0] nCRAS F     0.474      3       1.625     3
+CROW[1] nCRAS F     0.104      3       1.925     3
+Din[0]  PHI2  F     6.682      3       1.613     3
+Din[0]  nCCAS F    -0.028      M       2.082     3
+Din[1]  PHI2  F     6.886      3       2.631     3
+Din[1]  nCCAS F    -0.025      M       2.074     3
+Din[2]  PHI2  F     5.426      3       1.921     3
+Din[2]  nCCAS F     1.175      3       1.003     3
+Din[3]  PHI2  F     5.699      3       1.852     3
+Din[3]  nCCAS F     0.331      3       1.707     3
+Din[4]  PHI2  F     6.556      3       1.438     3
+Din[4]  nCCAS F     0.706      3       1.406     3
+Din[5]  PHI2  F     6.281      3       1.959     3
+Din[5]  nCCAS F     0.246      3       1.807     3
+Din[6]  PHI2  F     5.585      3       1.441     3
+Din[6]  nCCAS F     0.799      3       1.341     3
+Din[7]  PHI2  F     7.980      3       1.725     3
+Din[7]  nCCAS F     0.333      3       1.707     3
+MAin[0] PHI2  F     4.994      3       1.265     3
+MAin[0] nCRAS F     0.662      3       1.471     3
+MAin[1] PHI2  F     6.056      3       1.867     3
+MAin[1] nCRAS F     1.180      3       0.990     3
+MAin[2] PHI2  F    10.634      3      -1.183     M
+MAin[2] nCRAS F    -0.218      M       2.631     3
+MAin[3] PHI2  F    10.902      3      -1.260     M
+MAin[3] nCRAS F     0.208      3       1.826     3
+MAin[4] PHI2  F    10.204      3      -1.072     M
+MAin[4] nCRAS F    -0.218      M       2.628     3
+MAin[5] PHI2  F     7.043      3      -0.270     M
+MAin[5] nCRAS F     0.123      3       1.925     3
+MAin[6] PHI2  F     9.465      3      -0.885     M
+MAin[6] nCRAS F     0.584      3       1.522     3
+MAin[7] PHI2  F     9.683      3      -0.938     M
+MAin[7] nCRAS F    -0.218      M       2.628     3
+MAin[8] nCRAS F     0.316      3       1.758     3
+MAin[9] nCRAS F    -0.058      M       2.185     3
+PHI2    RCLK  R     1.456      3       0.038     3
+UFMSDO  RCLK  R     2.953      3      -0.147     M
+nCCAS   RCLK  R     2.435      3      -0.244     M
+nCCAS   nCRAS F     0.156      3       1.902     3
+nCRAS   RCLK  R     5.307      3      -0.787     M
+nFWE    PHI2  F     5.614      3       1.072     3
+nFWE    nCRAS F    -0.101      M       2.317     3
+
+
+// Clock to Output Delay
+
+Port   Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
+------------------------------------------------------------------------
+LED    RCLK  R    11.635         3        3.019          M
+RA[0]  RCLK  R    11.287         3        2.893          M
+RA[0]  nCRAS F    15.323         3        3.902          M
+RA[10] RCLK  R     7.501         3        1.949          M
+RA[11] PHI2  R     9.747         3        2.487          M
+RA[1]  RCLK  R    11.083         3        2.855          M
+RA[1]  nCRAS F    12.034         3        3.047          M
+RA[2]  RCLK  R    10.857         3        2.787          M
+RA[2]  nCRAS F    13.411         3        3.403          M
+RA[3]  RCLK  R    10.775         3        2.772          M
+RA[3]  nCRAS F    12.977         3        3.296          M
+RA[4]  RCLK  R    10.758         3        2.776          M
+RA[4]  nCRAS F    14.192         3        3.619          M
+RA[5]  RCLK  R    10.334         3        2.652          M
+RA[5]  nCRAS F    13.484         3        3.424          M
+RA[6]  RCLK  R    10.334         3        2.652          M
+RA[6]  nCRAS F    12.972         3        3.291          M
+RA[7]  RCLK  R     9.917         3        2.572          M
+RA[7]  nCRAS F    12.327         3        3.147          M
+RA[8]  RCLK  R    10.465         3        2.689          M
+RA[8]  nCRAS F    12.559         3        3.170          M
+RA[9]  RCLK  R    10.412         3        2.668          M
+RA[9]  nCRAS F    14.019         3        3.564          M
+RBA[0] nCRAS F    11.063         3        2.809          M
+RBA[1] nCRAS F    11.902         3        3.028          M
+RCKE   RCLK  R     7.501         3        1.949          M
+RDQMH  RCLK  R     9.831         3        2.523          M
+RDQML  RCLK  R     9.117         3        2.351          M
+RD[0]  nCCAS F    12.575         3        3.249          M
+RD[1]  nCCAS F    13.016         3        3.365          M
+RD[2]  nCCAS F    11.602         3        2.993          M
+RD[3]  nCCAS F    10.893         3        2.834          M
+RD[4]  nCCAS F    12.063         3        3.116          M
+RD[5]  nCCAS F    12.555         3        3.242          M
+RD[6]  nCCAS F    12.537         3        3.240          M
+RD[7]  nCCAS F    12.524         3        3.239          M
+UFMCLK RCLK  R     8.079         3        2.126          M
+UFMSDI RCLK  R     8.079         3        2.126          M
+nRCAS  RCLK  R     7.501         3        1.949          M
+nRCS   RCLK  R     7.501         3        1.949          M
+nRRAS  RCLK  R     9.175         3        2.363          M
+nRWE   RCLK  R     9.141         3        2.356          M
+nUFMCS RCLK  R     8.804         3        2.290          M
+WARNING: you must also run trce with hold speed: 3
+WARNING: you must also run trce with setup speed: M
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1_trce.asd b/CPLD/LCMXO/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1_trce.asd
new file mode 100644
index 0000000..735293f
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1_trce.asd
@@ -0,0 +1,91 @@
+[ActiveSupport TRCE]
+; Setup Analysis
+Period_0 = 27.276 ns (350.000 ns);
+Period_1 = 2.000 ns (350.000 ns);
+Period_2 = 2.000 ns (350.000 ns);
+Period_3 = 9.443 ns (16.000 ns);
+Tco_4 = - (-);
+Tco_5 = - (-);
+Tco_6 = - (-);
+Tco_7 = - (-);
+Tco_8 = - (-);
+Tco_9 = - (-);
+Tco_10 = - (-);
+Tco_11 = - (-);
+Tco_12 = - (-);
+Tco_13 = - (-);
+Tco_14 = - (-);
+Tco_15 = - (-);
+Tco_16 = 7.501 ns (12.500 ns);
+Tco_17 = 10.412 ns (12.500 ns);
+Tco_18 = 10.465 ns (12.500 ns);
+Tco_19 = 9.917 ns (12.500 ns);
+Tco_20 = 10.334 ns (12.500 ns);
+Tco_21 = 10.334 ns (12.500 ns);
+Tco_22 = 10.758 ns (12.500 ns);
+Tco_23 = 10.775 ns (12.500 ns);
+Tco_24 = 10.857 ns (12.500 ns);
+Tco_25 = 11.083 ns (12.500 ns);
+Tco_26 = 11.287 ns (12.500 ns);
+Tco_27 = 7.501 ns (12.500 ns);
+Tco_28 = 7.501 ns (12.500 ns);
+Tco_29 = 9.141 ns (12.500 ns);
+Tco_30 = 9.175 ns (12.500 ns);
+Tco_31 = 7.501 ns (12.500 ns);
+Tco_32 = 9.831 ns (12.500 ns);
+Tco_33 = 9.117 ns (12.500 ns);
+Tco_34 = - (-);
+Tco_35 = - (-);
+Tco_36 = - (-);
+Tco_37 = - (-);
+Tco_38 = - (-);
+Tco_39 = - (-);
+Tco_40 = - (-);
+Failed = 0 (Total 41);
+Clock_ports = 4;
+Clock_nets = 4;
+; Hold Analysis
+Period_0 = - (-);
+Period_1 = - (-);
+Period_2 = - (-);
+Period_3 = - (-);
+Tco_4 = - (-);
+Tco_5 = - (-);
+Tco_6 = - (-);
+Tco_7 = - (-);
+Tco_8 = - (-);
+Tco_9 = - (-);
+Tco_10 = - (-);
+Tco_11 = - (-);
+Tco_12 = - (-);
+Tco_13 = - (-);
+Tco_14 = - (-);
+Tco_15 = - (-);
+Tco_16 = 1.949 ns (0.000 ns);
+Tco_17 = 2.668 ns (0.000 ns);
+Tco_18 = 2.689 ns (0.000 ns);
+Tco_19 = 2.572 ns (0.000 ns);
+Tco_20 = 2.652 ns (0.000 ns);
+Tco_21 = 2.652 ns (0.000 ns);
+Tco_22 = 2.776 ns (0.000 ns);
+Tco_23 = 2.772 ns (0.000 ns);
+Tco_24 = 2.787 ns (0.000 ns);
+Tco_25 = 2.855 ns (0.000 ns);
+Tco_26 = 2.893 ns (0.000 ns);
+Tco_27 = 1.949 ns (0.000 ns);
+Tco_28 = 1.949 ns (0.000 ns);
+Tco_29 = 2.356 ns (0.000 ns);
+Tco_30 = 2.363 ns (0.000 ns);
+Tco_31 = 1.949 ns (0.000 ns);
+Tco_32 = 2.523 ns (0.000 ns);
+Tco_33 = 2.351 ns (0.000 ns);
+Tco_34 = - (-);
+Tco_35 = - (-);
+Tco_36 = - (-);
+Tco_37 = - (-);
+Tco_38 = - (-);
+Tco_39 = - (-);
+Tco_40 = - (-);
+Failed = 0 (Total 41);
+Clock_ports = 4;
+Clock_nets = 4;
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/synthesis.log b/CPLD/LCMXO/LCMXO640C/impl1/synthesis.log
new file mode 100644
index 0000000..f808002
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/synthesis.log
@@ -0,0 +1,239 @@
+synthesis:  version Diamond (64-bit) 3.12.0.240.2
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Mon Aug 16 21:33:29 2021
+
+
+Command Line:  synthesis -f RAM2GS_LCMXO640C_impl1_lattice.synproj -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml 
+
+Synthesis options:
+The -a option is MachXO.
+The -s option is 3.
+The -t option is TQFP100.
+The -d option is LCMXO640C.
+Using package TQFP100.
+Using performance grade 3.
+                                                          
+
+##########################################################
+
+### Lattice Family : MachXO
+
+### Device  : LCMXO640C
+
+### Package : TQFP100
+
+### Speed   : 3
+
+##########################################################
+
+                                                          
+
+INFO - synthesis: User-Selected Strategy Settings
+Optimization goal = Balanced
+Top-level module name = RAM2GS.
+Target frequency = 200.000000 MHz.
+Maximum fanout = 1000.
+Timing path count = 3
+BRAM utilization = 100.000000 %
+DSP usage = true
+DSP utilization = 100.000000 %
+fsm_encoding_style = auto
+resolve_mixed_drivers = 0
+fix_gated_clocks = 1
+
+Mux style = Auto
+Use Carry Chain = true
+carry_chain_length = 0
+Loop Limit = 1950.
+Use IO Insertion = TRUE
+Use IO Reg = AUTO
+
+Resource Sharing = TRUE
+Propagate Constants = TRUE
+Remove Duplicate Registers = TRUE
+force_gsr = auto
+ROM style = auto
+RAM style = auto
+The -comp option is FALSE.
+The -syn option is FALSE.
+-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C (searchpath added)
+-p C:/lscc/diamond/3.12/ispfpga/mj5g00/data (searchpath added)
+-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/impl1 (searchpath added)
+-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C (searchpath added)
+Verilog design file = C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v
+NGD file = RAM2GS_LCMXO640C_impl1.ngd
+-sdc option: SDC file input not used.
+-lpf option: Output file option is ON.
+Hardtimer checking is enabled (default). The -dt option is not used.
+The -r option is OFF. [ Remove LOC Properties is OFF. ]
+Technology check ok...
+
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
+Compile design.
+Compile Design Begin
+Analyzing Verilog file c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v. VERI-1482
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
+Top module name (Verilog): RAM2GS
+INFO - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(1): compiling module RAM2GS. VERI-1018
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131): expression size 32 truncated to fit in target size 2. VERI-1209
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136): expression size 32 truncated to fit in target size 18. VERI-1209
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263): expression size 32 truncated to fit in target size 4. VERI-1209
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+Loading device for application map from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.17.
+Top-level module name = RAM2GS.
+INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 0000 -> 0000000000000001
+
+ 0001 -> 0000000000000010
+
+ 0010 -> 0000000000000100
+
+ 0011 -> 0000000000001000
+
+ 0100 -> 0000000000010000
+
+ 0101 -> 0000000000100000
+
+ 0110 -> 0000000001000000
+
+ 0111 -> 0000000010000000
+
+ 1000 -> 0000000100000000
+
+ 1001 -> 0000001000000000
+
+ 1010 -> 0000010000000000
+
+ 1011 -> 0000100000000000
+
+ 1100 -> 0001000000000000
+
+ 1101 -> 0010000000000000
+
+ 1110 -> 0100000000000000
+
+ 1111 -> 1000000000000000
+
+INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 00 -> 0001
+
+ 01 -> 0010
+
+ 10 -> 0100
+
+ 11 -> 1000
+
+
+
+
+GSR will not be inferred because no asynchronous signal was found in the netlist.
+WARNING - synthesis: Initial value found on instance C1Submitted_379 will be ignored.
+Applying 200.000000 MHz constraint to all clocks
+
+WARNING - synthesis: No user .sdc file.
+Results of NGD DRC are available in RAM2GS_drc.log.
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+All blocks are expanded and NGD expansion is successful.
+Writing NGD file RAM2GS_LCMXO640C_impl1.ngd.
+
+################### Begin Area Report (RAM2GS)######################
+Number of register bits => 102 of 862 (11 % )
+BB => 8
+CCU2 => 9
+FD1P3AX => 28
+FD1P3AY => 3
+FD1P3IX => 2
+FD1P3JX => 1
+FD1S3AX => 47
+FD1S3AY => 1
+FD1S3IX => 16
+FD1S3JX => 4
+GSR => 1
+IB => 26
+INV => 3
+OB => 33
+ORCALUT4 => 116
+PFUMX => 3
+################### End Area Report ##################
+
+################### Begin BlackBox Report ######################
+TSALL => 1
+################### End BlackBox Report ##################
+
+################### Begin Clock Report ######################
+Clock Nets
+Number of Clocks: 4
+  Net : RCLK_c, loads : 62
+  Net : PHI2_c, loads : 11
+  Net : nCCAS_c, loads : 2
+  Net : nCRAS_c, loads : 2
+Clock Enable Nets
+Number of Clock Enables: 13
+Top 10 highest fanout Clock Enables:
+  Net : RCLK_c_enable_23, loads : 16
+  Net : RCLK_c_enable_4, loads : 3
+  Net : PHI2_N_114_enable_7, loads : 3
+  Net : RCLK_c_enable_24, loads : 2
+  Net : PHI2_N_114_enable_6, loads : 2
+  Net : RCLK_c_enable_7, loads : 1
+  Net : RCLK_c_enable_6, loads : 1
+  Net : RCLK_c_enable_3, loads : 1
+  Net : PHI2_N_114_enable_2, loads : 1
+  Net : PHI2_N_114_enable_1, loads : 1
+Highest fanout non-clock nets
+Top 10 highest fanout non-clock nets:
+  Net : InitReady, loads : 17
+  Net : RCLK_c_enable_23, loads : 16
+  Net : RASr2, loads : 15
+  Net : nCRAS_N_9, loads : 15
+  Net : nRowColSel_N_35, loads : 14
+  Net : nRowColSel, loads : 13
+  Net : Ready, loads : 13
+  Net : n2307, loads : 13
+  Net : nCCAS_N_3, loads : 10
+  Net : Din_c_6, loads : 9
+################### End Clock Report ##################
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk1 [get_nets PHI2_c]                  |  200.000 MHz|   38.826 MHz|     7 *
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets RCLK_c]                  |  200.000 MHz|   88.566 MHz|     6 *
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+2 constraints not met.
+
+
+Peak Memory Usage: 50.699  MB
+
+--------------------------------------------------------------
+Elapsed CPU time for LSE flow : 0.515  secs
+--------------------------------------------------------------
diff --git a/CPLD/LCMXO/LCMXO640C/impl1/synthesis_lse.html b/CPLD/LCMXO/LCMXO640C/impl1/synthesis_lse.html
new file mode 100644
index 0000000..23a4fc7
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/synthesis_lse.html
@@ -0,0 +1,304 @@
+
+Synthesis and Ngdbuild Report
+
+
+
    Synthesis and Ngdbuild  Report
+synthesis:  version Diamond (64-bit) 3.12.0.240.2
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Mon Aug 16 21:33:29 2021
+
+
+Command Line:  synthesis -f RAM2GS_LCMXO640C_impl1_lattice.synproj -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml 
+
+Synthesis options:
+The -a option is MachXO.
+The -s option is 3.
+The -t option is TQFP100.
+The -d option is LCMXO640C.
+Using package TQFP100.
+Using performance grade 3.
+                                                          
+
+##########################################################
+
+### Lattice Family : MachXO
+
+### Device  : LCMXO640C
+
+### Package : TQFP100
+
+### Speed   : 3
+
+##########################################################
+
+                                                          
+
+INFO - synthesis: User-Selected Strategy Settings
+Optimization goal = Balanced
+Top-level module name = RAM2GS.
+Target frequency = 200.000000 MHz.
+Maximum fanout = 1000.
+Timing path count = 3
+BRAM utilization = 100.000000 %
+DSP usage = true
+DSP utilization = 100.000000 %
+fsm_encoding_style = auto
+resolve_mixed_drivers = 0
+fix_gated_clocks = 1
+
+Mux style = Auto
+Use Carry Chain = true
+carry_chain_length = 0
+Loop Limit = 1950.
+Use IO Insertion = TRUE
+Use IO Reg = AUTO
+
+Resource Sharing = TRUE
+Propagate Constants = TRUE
+Remove Duplicate Registers = TRUE
+force_gsr = auto
+ROM style = auto
+RAM style = auto
+The -comp option is FALSE.
+The -syn option is FALSE.
+-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C (searchpath added)
+-p C:/lscc/diamond/3.12/ispfpga/mj5g00/data (searchpath added)
+-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/impl1 (searchpath added)
+-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C (searchpath added)
+Verilog design file = C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v
+NGD file = RAM2GS_LCMXO640C_impl1.ngd
+-sdc option: SDC file input not used.
+-lpf option: Output file option is ON.
+Hardtimer checking is enabled (default). The -dt option is not used.
+The -r option is OFF. [ Remove LOC Properties is OFF. ]
+Technology check ok...
+
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
+Compile design.
+Compile Design Begin
+Analyzing Verilog file c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v. VERI-1482
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
+Top module name (Verilog): RAM2GS
+INFO - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(1): compiling module RAM2GS. VERI-1018
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131): expression size 32 truncated to fit in target size 2. VERI-1209
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136): expression size 32 truncated to fit in target size 18. VERI-1209
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263): expression size 32 truncated to fit in target size 4. VERI-1209
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+Loading device for application map from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.17.
+Top-level module name = RAM2GS.
+INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 0000 -> 0000000000000001
+
+ 0001 -> 0000000000000010
+
+ 0010 -> 0000000000000100
+
+ 0011 -> 0000000000001000
+
+ 0100 -> 0000000000010000
+
+ 0101 -> 0000000000100000
+
+ 0110 -> 0000000001000000
+
+ 0111 -> 0000000010000000
+
+ 1000 -> 0000000100000000
+
+ 1001 -> 0000001000000000
+
+ 1010 -> 0000010000000000
+
+ 1011 -> 0000100000000000
+
+ 1100 -> 0001000000000000
+
+ 1101 -> 0010000000000000
+
+ 1110 -> 0100000000000000
+
+ 1111 -> 1000000000000000
+
+INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 00 -> 0001
+
+ 01 -> 0010
+
+ 10 -> 0100
+
+ 11 -> 1000
+
+
+
+
+GSR will not be inferred because no asynchronous signal was found in the netlist.
+WARNING - synthesis: Initial value found on instance C1Submitted_379 will be ignored.
+Applying 200.000000 MHz constraint to all clocks
+
+WARNING - synthesis: No user .sdc file.
+Results of NGD DRC are available in RAM2GS_drc.log.
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+All blocks are expanded and NGD expansion is successful.
+Writing NGD file RAM2GS_LCMXO640C_impl1.ngd.
+
+################### Begin Area Report (RAM2GS)######################
+Number of register bits => 102 of 862 (11 % )
+BB => 8
+CCU2 => 9
+FD1P3AX => 28
+FD1P3AY => 3
+FD1P3IX => 2
+FD1P3JX => 1
+FD1S3AX => 47
+FD1S3AY => 1
+FD1S3IX => 16
+FD1S3JX => 4
+GSR => 1
+IB => 26
+INV => 3
+OB => 33
+ORCALUT4 => 116
+PFUMX => 3
+################### End Area Report ##################
+
+################### Begin BlackBox Report ######################
+TSALL => 1
+################### End BlackBox Report ##################
+
+################### Begin Clock Report ######################
+Clock Nets
+Number of Clocks: 4
+  Net : RCLK_c, loads : 62
+  Net : PHI2_c, loads : 11
+  Net : nCCAS_c, loads : 2
+  Net : nCRAS_c, loads : 2
+Clock Enable Nets
+Number of Clock Enables: 13
+Top 10 highest fanout Clock Enables:
+  Net : RCLK_c_enable_23, loads : 16
+  Net : RCLK_c_enable_4, loads : 3
+  Net : PHI2_N_114_enable_7, loads : 3
+  Net : RCLK_c_enable_24, loads : 2
+  Net : PHI2_N_114_enable_6, loads : 2
+  Net : RCLK_c_enable_7, loads : 1
+  Net : RCLK_c_enable_6, loads : 1
+  Net : RCLK_c_enable_3, loads : 1
+  Net : PHI2_N_114_enable_2, loads : 1
+  Net : PHI2_N_114_enable_1, loads : 1
+Highest fanout non-clock nets
+Top 10 highest fanout non-clock nets:
+  Net : InitReady, loads : 17
+  Net : RCLK_c_enable_23, loads : 16
+  Net : RASr2, loads : 15
+  Net : nCRAS_N_9, loads : 15
+  Net : nRowColSel_N_35, loads : 14
+  Net : nRowColSel, loads : 13
+  Net : Ready, loads : 13
+  Net : n2307, loads : 13
+  Net : nCCAS_N_3, loads : 10
+  Net : Din_c_6, loads : 9
+################### End Clock Report ##################
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk1 [get_nets PHI2_c]                  |  200.000 MHz|   38.826 MHz|     7 *
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets RCLK_c]                  |  200.000 MHz|   88.566 MHz|     6 *
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+2 constraints not met.
+
+
+Peak Memory Usage: 50.699  MB
+
+--------------------------------------------------------------
+Elapsed CPU time for LSE flow : 0.515  secs
+--------------------------------------------------------------
+
+
+
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diff --git a/CPLD/LCMXO/LCMXO640C/impl1/xxx_lse_cp_file_list b/CPLD/LCMXO/LCMXO640C/impl1/xxx_lse_cp_file_list
new file mode 100644
index 0000000..29f9161
--- /dev/null
+++ b/CPLD/LCMXO/LCMXO640C/impl1/xxx_lse_cp_file_list
@@ -0,0 +1,252 @@
+3	 c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v
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diff --git a/CPLD/LCMXO/LCMXO640C/impl1/xxx_lse_sign_file b/CPLD/LCMXO/LCMXO640C/impl1/xxx_lse_sign_file
new file mode 100644
index 0000000..47217b1
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diff --git a/CPLD/RAM4GS-ExtSPI.v b/CPLD/LCMXO/RAM2GS-LCMXO.v
old mode 100755
new mode 100644
similarity index 94%
rename from CPLD/RAM4GS-ExtSPI.v
rename to CPLD/LCMXO/RAM2GS-LCMXO.v
index 9677572..fce50cf
--- a/CPLD/RAM4GS-ExtSPI.v
+++ b/CPLD/LCMXO/RAM2GS-LCMXO.v
@@ -1,4 +1,4 @@
-module RAM4GS(PHI2, MAin, CROW, Din, Dout,
+module RAM2GS(PHI2, MAin, CROW, Din, Dout,
 			  nCCAS, nCRAS, nFWE, LED,
 			  RBA, RA, RD, nRCS, RCLK, RCKE,
 			  nRWE, nRRAS, nRCAS, RDQMH, RDQML,
@@ -9,7 +9,8 @@ module RAM4GS(PHI2, MAin, CROW, Din, Dout,
 
 	/* Activity LED */
 	reg LEDEN = 0;
-	output LED = ~(~nCRAS &&  LEDEN);
+	output LED;
+	assign LED = ~(~nCRAS &&  LEDEN);
 
 	/* Async. DRAM Control Inputs */
 	input nCCAS, nCRAS;
@@ -23,7 +24,8 @@ module RAM4GS(PHI2, MAin, CROW, Din, Dout,
 
 	/* 65816 Data */
 	input [7:0] Din;
-	output [7:0] Dout = RD[7:0];
+	output [7:0] Dout;
+	assign Dout[7:0] = RD[7:0];
 
 	/* Latched 65816 Bank Address */
 	reg [7:0] Bank;
@@ -51,8 +53,9 @@ module RAM4GS(PHI2, MAin, CROW, Din, Dout,
 	assign RA[11] = RA11;
 	assign RA[10] = RA10;
 	assign RA[9:0] = ~nRowColSel ? RowA[9:0] : MAin[9:0];
-	output RDQML = ~nRowColSel ? 1'b1 : ~MAin[9];
-	output RDQMH = ~nRowColSel ? 1'b1 : MAin[9];
+	output RDQML, RDQMH;
+	assign RDQML = ~nRowColSel ? 1'b1 : ~MAin[9];
+	assign RDQMH = ~nRowColSel ? 1'b1 :  MAin[9];
 	reg [7:0] WRD;
 	inout [7:0] RD = (~nCCAS & ~nFWE) ? WRD[7:0] : 8'bZ;
 
@@ -67,6 +70,7 @@ module RAM4GS(PHI2, MAin, CROW, Din, Dout,
 	reg ADSubmitted = 0;
 	reg CmdEnable = 0;
 	reg CmdSubmitted = 0;
+	reg CmdLEDEN = 0;
 	reg Cmdn8MEGEN = 0;
 	reg CmdUFMCLK = 0;
 	reg CmdUFMSDI = 0;
@@ -306,9 +310,11 @@ module RAM4GS(PHI2, MAin, CROW, Din, Dout,
 			if (Din[7:4]==4'h0) begin
 				XOR8MEG <= Din[0];
 			end else if (Din[7:4]==4'h1) begin
+				CmdLEDEN <= ~Din[1];
 				Cmdn8MEGEN <= ~Din[0];
 				CmdSubmitted <= 1'b1;
-			end else if (Din[7:4]==4'h3) begin
+			end else if (Din[7:4]==4'h3 && ~Din[3]) begin
+				CmdLEDEN <= LEDEN;
 				Cmdn8MEGEN <= n8MEGEN;
 				CmdUFMCS <= Din[2];
 				CmdUFMCLK <= Din[1];
@@ -372,17 +378,22 @@ module RAM4GS(PHI2, MAin, CROW, Din, Dout,
 			// Latch n8MEGEN and LEDEN
 			if (FS[9:5]==5'h00 && FS[4:0]==5'h1F) n8MEGEN <= ~UFMSDO;
 			if (FS[9:5]==5'h01 && FS[4:0]==5'h1F) LEDEN <= ~UFMSDO;
-		end else if (~InitReady && FS[17:10]!=8'hFE && FS[17:10]!=8'hFF) begin
+		end else if (~InitReady && FS[17:10]==8'h04) begin
 			nUFMCS <= 1'b0;
 			UFMCLK <= FS[4];
 			UFMSDI <= 1'b0;
+		end else if (~InitReady && FS[17:10]==8'h05) begin
+			nUFMCS <= 1'b1;
+			UFMCLK <= FS[4];
+			UFMSDI <= 1'b0;
 		end else if (~InitReady) begin
 			nUFMCS <= 1'b1;
 			UFMCLK <= 1'b0;
 			UFMSDI <= 1'b0;
 		end else if (~PHI2r2 & PHI2r3 & CmdSubmitted) begin
 			// Set user command signals after PHI2 falls
-			// Cmdn8MEGEN, CmdUFMCS, CmdUFMCLK, CmdUFMSDI
+			// CmdnLEDEN, Cmdn8MEGEN, CmdUFMCS, CmdUFMCLK, CmdUFMSDI
+			LEDEN <= CmdLEDEN;
 			n8MEGEN <= Cmdn8MEGEN;
 			nUFMCS <= ~CmdUFMCS;
 			UFMCLK <= CmdUFMCLK;
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/.run_manager.ini b/CPLD/LCMXO2/LCMXO2-640HC/.run_manager.ini
new file mode 100644
index 0000000..8c0aa7b
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/.run_manager.ini
@@ -0,0 +1,9 @@
+[Runmanager]
+Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0)
+windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)
+headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0)
+
+[impl1%3CStrategy1%3E]
+isChecked=false
+isHidden=false
+isExpanded=false
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/.setting.ini b/CPLD/LCMXO2/LCMXO2-640HC/.setting.ini
new file mode 100644
index 0000000..449a648
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/.setting.ini
@@ -0,0 +1,4 @@
+[General]
+Map.auto_tasks=MapTrace
+Export.auto_tasks=IBIS, Bitgen, Jedecgen
+PAR.auto_tasks=PARTrace, IOTiming
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/EFB.edn b/CPLD/LCMXO2/LCMXO2-640HC/EFB.edn
new file mode 100644
index 0000000..13d44b1
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/EFB.edn
@@ -0,0 +1,550 @@
+(edif EFB
+  (edifVersion 2 0 0)
+  (edifLevel 0)
+  (keywordMap (keywordLevel 0))
+  (status
+    (written
+      (timestamp 2021 8 17 5 48 29)
+      (program "SCUBA" (version "Diamond (64-bit) 3.12.0.240.2"))))
+      (comment "C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n EFB -lang verilog -synth lse -bus_exp 7 -bb -type efb -arch xo2c00 -freq 16 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640 ")
+  (library ORCLIB
+    (edifLevel 0)
+    (technology
+      (numberDefinition))
+    (cell VHI
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell VLO
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell EFB
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port WBCLKI
+            (direction INPUT))
+          (port WBRSTI
+            (direction INPUT))
+          (port WBCYCI
+            (direction INPUT))
+          (port WBSTBI
+            (direction INPUT))
+          (port WBWEI
+            (direction INPUT))
+          (port WBADRI7
+            (direction INPUT))
+          (port WBADRI6
+            (direction INPUT))
+          (port WBADRI5
+            (direction INPUT))
+          (port WBADRI4
+            (direction INPUT))
+          (port WBADRI3
+            (direction INPUT))
+          (port WBADRI2
+            (direction INPUT))
+          (port WBADRI1
+            (direction INPUT))
+          (port WBADRI0
+            (direction INPUT))
+          (port WBDATI7
+            (direction INPUT))
+          (port WBDATI6
+            (direction INPUT))
+          (port WBDATI5
+            (direction INPUT))
+          (port WBDATI4
+            (direction INPUT))
+          (port WBDATI3
+            (direction INPUT))
+          (port WBDATI2
+            (direction INPUT))
+          (port WBDATI1
+            (direction INPUT))
+          (port WBDATI0
+            (direction INPUT))
+          (port PLL0DATI7
+            (direction INPUT))
+          (port PLL0DATI6
+            (direction INPUT))
+          (port PLL0DATI5
+            (direction INPUT))
+          (port PLL0DATI4
+            (direction INPUT))
+          (port PLL0DATI3
+            (direction INPUT))
+          (port PLL0DATI2
+            (direction INPUT))
+          (port PLL0DATI1
+            (direction INPUT))
+          (port PLL0DATI0
+            (direction INPUT))
+          (port PLL0ACKI
+            (direction INPUT))
+          (port PLL1DATI7
+            (direction INPUT))
+          (port PLL1DATI6
+            (direction INPUT))
+          (port PLL1DATI5
+            (direction INPUT))
+          (port PLL1DATI4
+            (direction INPUT))
+          (port PLL1DATI3
+            (direction INPUT))
+          (port PLL1DATI2
+            (direction INPUT))
+          (port PLL1DATI1
+            (direction INPUT))
+          (port PLL1DATI0
+            (direction INPUT))
+          (port PLL1ACKI
+            (direction INPUT))
+          (port I2C1SCLI
+            (direction INPUT))
+          (port I2C1SDAI
+            (direction INPUT))
+          (port I2C2SCLI
+            (direction INPUT))
+          (port I2C2SDAI
+            (direction INPUT))
+          (port SPISCKI
+            (direction INPUT))
+          (port SPIMISOI
+            (direction INPUT))
+          (port SPIMOSII
+            (direction INPUT))
+          (port SPISCSN
+            (direction INPUT))
+          (port TCCLKI
+            (direction INPUT))
+          (port TCRSTN
+            (direction INPUT))
+          (port TCIC
+            (direction INPUT))
+          (port UFMSN
+            (direction INPUT))
+          (port WBDATO7
+            (direction OUTPUT))
+          (port WBDATO6
+            (direction OUTPUT))
+          (port WBDATO5
+            (direction OUTPUT))
+          (port WBDATO4
+            (direction OUTPUT))
+          (port WBDATO3
+            (direction OUTPUT))
+          (port WBDATO2
+            (direction OUTPUT))
+          (port WBDATO1
+            (direction OUTPUT))
+          (port WBDATO0
+            (direction OUTPUT))
+          (port WBACKO
+            (direction OUTPUT))
+          (port PLLCLKO
+            (direction OUTPUT))
+          (port PLLRSTO
+            (direction OUTPUT))
+          (port PLL0STBO
+            (direction OUTPUT))
+          (port PLL1STBO
+            (direction OUTPUT))
+          (port PLLWEO
+            (direction OUTPUT))
+          (port PLLADRO4
+            (direction OUTPUT))
+          (port PLLADRO3
+            (direction OUTPUT))
+          (port PLLADRO2
+            (direction OUTPUT))
+          (port PLLADRO1
+            (direction OUTPUT))
+          (port PLLADRO0
+            (direction OUTPUT))
+          (port PLLDATO7
+            (direction OUTPUT))
+          (port PLLDATO6
+            (direction OUTPUT))
+          (port PLLDATO5
+            (direction OUTPUT))
+          (port PLLDATO4
+            (direction OUTPUT))
+          (port PLLDATO3
+            (direction OUTPUT))
+          (port PLLDATO2
+            (direction OUTPUT))
+          (port PLLDATO1
+            (direction OUTPUT))
+          (port PLLDATO0
+            (direction OUTPUT))
+          (port I2C1SCLO
+            (direction OUTPUT))
+          (port I2C1SCLOEN
+            (direction OUTPUT))
+          (port I2C1SDAO
+            (direction OUTPUT))
+          (port I2C1SDAOEN
+            (direction OUTPUT))
+          (port I2C2SCLO
+            (direction OUTPUT))
+          (port I2C2SCLOEN
+            (direction OUTPUT))
+          (port I2C2SDAO
+            (direction OUTPUT))
+          (port I2C2SDAOEN
+            (direction OUTPUT))
+          (port I2C1IRQO
+            (direction OUTPUT))
+          (port I2C2IRQO
+            (direction OUTPUT))
+          (port SPISCKO
+            (direction OUTPUT))
+          (port SPISCKEN
+            (direction OUTPUT))
+          (port SPIMISOO
+            (direction OUTPUT))
+          (port SPIMISOEN
+            (direction OUTPUT))
+          (port SPIMOSIO
+            (direction OUTPUT))
+          (port SPIMOSIEN
+            (direction OUTPUT))
+          (port SPIMCSN7
+            (direction OUTPUT))
+          (port SPIMCSN6
+            (direction OUTPUT))
+          (port SPIMCSN5
+            (direction OUTPUT))
+          (port SPIMCSN4
+            (direction OUTPUT))
+          (port SPIMCSN3
+            (direction OUTPUT))
+          (port SPIMCSN2
+            (direction OUTPUT))
+          (port SPIMCSN1
+            (direction OUTPUT))
+          (port SPIMCSN0
+            (direction OUTPUT))
+          (port SPICSNEN
+            (direction OUTPUT))
+          (port SPIIRQO
+            (direction OUTPUT))
+          (port TCINT
+            (direction OUTPUT))
+          (port TCOC
+            (direction OUTPUT))
+          (port WBCUFMIRQ
+            (direction OUTPUT))
+          (port CFGWAKE
+            (direction OUTPUT))
+          (port CFGSTDBY
+            (direction OUTPUT)))))
+    (cell EFB
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port wb_clk_i
+            (direction INPUT))
+          (port wb_rst_i
+            (direction INPUT))
+          (port wb_cyc_i
+            (direction INPUT))
+          (port wb_stb_i
+            (direction INPUT))
+          (port wb_we_i
+            (direction INPUT))
+          (port (array (rename wb_adr_i "wb_adr_i(7:0)") 8)
+            (direction INPUT))
+          (port (array (rename wb_dat_i "wb_dat_i(7:0)") 8)
+            (direction INPUT))
+          (port (array (rename wb_dat_o "wb_dat_o(7:0)") 8)
+            (direction OUTPUT))
+          (port wb_ack_o
+            (direction OUTPUT))
+          (port wbc_ufm_irq
+            (direction OUTPUT)))
+        (property NGD_DRC_MASK (integer 1))
+        (contents
+          (instance scuba_vhi_inst
+            (viewRef view1 
+              (cellRef VHI)))
+          (instance scuba_vlo_inst
+            (viewRef view1 
+              (cellRef VLO)))
+          (instance EFBInst_0
+            (viewRef view1 
+              (cellRef EFB))
+            (property UFM_INIT_FILE_FORMAT
+              (string "HEX"))
+            (property UFM_INIT_FILE_NAME
+              (string "NONE"))
+            (property UFM_INIT_ALL_ZEROS
+              (string "ENABLED"))
+            (property UFM_INIT_START_PAGE
+              (string "190"))
+            (property UFM_INIT_PAGES
+              (string "1"))
+            (property DEV_DENSITY
+              (string "640L"))
+            (property EFB_UFM
+              (string "ENABLED"))
+            (property TC_ICAPTURE
+              (string "DISABLED"))
+            (property TC_OVERFLOW
+              (string "DISABLED"))
+            (property TC_ICR_INT
+              (string "OFF"))
+            (property TC_OCR_INT
+              (string "OFF"))
+            (property TC_OV_INT
+              (string "OFF"))
+            (property TC_TOP_SEL
+              (string "OFF"))
+            (property TC_RESETN
+              (string "ENABLED"))
+            (property TC_OC_MODE
+              (string "TOGGLE"))
+            (property TC_OCR_SET
+              (string "32767"))
+            (property TC_TOP_SET
+              (string "65535"))
+            (property GSR
+              (string "ENABLED"))
+            (property TC_CCLK_SEL
+              (string "1"))
+            (property TC_MODE
+              (string "CTCM"))
+            (property TC_SCLK_SEL
+              (string "PCLOCK"))
+            (property EFB_TC_PORTMODE
+              (string "WB"))
+            (property EFB_TC
+              (string "DISABLED"))
+            (property SPI_WAKEUP
+              (string "DISABLED"))
+            (property SPI_INTR_RXOVR
+              (string "DISABLED"))
+            (property SPI_INTR_TXOVR
+              (string "DISABLED"))
+            (property SPI_INTR_RXRDY
+              (string "DISABLED"))
+            (property SPI_INTR_TXRDY
+              (string "DISABLED"))
+            (property SPI_SLAVE_HANDSHAKE
+              (string "DISABLED"))
+            (property SPI_PHASE_ADJ
+              (string "DISABLED"))
+            (property SPI_CLK_INV
+              (string "DISABLED"))
+            (property SPI_LSB_FIRST
+              (string "DISABLED"))
+            (property SPI_CLK_DIVIDER
+              (string "1"))
+            (property SPI_MODE
+              (string "MASTER"))
+            (property EFB_SPI
+              (string "DISABLED"))
+            (property I2C2_WAKEUP
+              (string "DISABLED"))
+            (property I2C2_GEN_CALL
+              (string "DISABLED"))
+            (property I2C2_CLK_DIVIDER
+              (string "1"))
+            (property I2C2_BUS_PERF
+              (string "100kHz"))
+            (property I2C2_SLAVE_ADDR
+              (string "0b1000010"))
+            (property I2C2_ADDRESSING
+              (string "7BIT"))
+            (property EFB_I2C2
+              (string "DISABLED"))
+            (property I2C1_WAKEUP
+              (string "DISABLED"))
+            (property I2C1_GEN_CALL
+              (string "DISABLED"))
+            (property I2C1_CLK_DIVIDER
+              (string "1"))
+            (property I2C1_BUS_PERF
+              (string "100kHz"))
+            (property I2C1_SLAVE_ADDR
+              (string "0b1000001"))
+            (property I2C1_ADDRESSING
+              (string "7BIT"))
+            (property EFB_I2C1
+              (string "DISABLED"))
+            (property EFB_WB_CLK_FREQ
+              (string "16.0")))
+          (net scuba_vhi
+            (joined
+              (portRef Z (instanceRef scuba_vhi_inst))
+              (portRef UFMSN (instanceRef EFBInst_0))))
+          (net scuba_vlo
+            (joined
+              (portRef Z (instanceRef scuba_vlo_inst))
+              (portRef PLL1DATI7 (instanceRef EFBInst_0))
+              (portRef PLL1DATI6 (instanceRef EFBInst_0))
+              (portRef PLL1DATI5 (instanceRef EFBInst_0))
+              (portRef PLL1DATI4 (instanceRef EFBInst_0))
+              (portRef PLL1DATI3 (instanceRef EFBInst_0))
+              (portRef PLL1DATI2 (instanceRef EFBInst_0))
+              (portRef PLL1DATI1 (instanceRef EFBInst_0))
+              (portRef PLL1DATI0 (instanceRef EFBInst_0))
+              (portRef PLL1ACKI (instanceRef EFBInst_0))
+              (portRef PLL0DATI7 (instanceRef EFBInst_0))
+              (portRef PLL0DATI6 (instanceRef EFBInst_0))
+              (portRef PLL0DATI5 (instanceRef EFBInst_0))
+              (portRef PLL0DATI4 (instanceRef EFBInst_0))
+              (portRef PLL0DATI3 (instanceRef EFBInst_0))
+              (portRef PLL0DATI2 (instanceRef EFBInst_0))
+              (portRef PLL0DATI1 (instanceRef EFBInst_0))
+              (portRef PLL0DATI0 (instanceRef EFBInst_0))
+              (portRef PLL0ACKI (instanceRef EFBInst_0))
+              (portRef TCIC (instanceRef EFBInst_0))
+              (portRef TCRSTN (instanceRef EFBInst_0))
+              (portRef TCCLKI (instanceRef EFBInst_0))
+              (portRef SPISCSN (instanceRef EFBInst_0))
+              (portRef SPIMOSII (instanceRef EFBInst_0))
+              (portRef SPIMISOI (instanceRef EFBInst_0))
+              (portRef SPISCKI (instanceRef EFBInst_0))
+              (portRef I2C2SDAI (instanceRef EFBInst_0))
+              (portRef I2C2SCLI (instanceRef EFBInst_0))
+              (portRef I2C1SDAI (instanceRef EFBInst_0))
+              (portRef I2C1SCLI (instanceRef EFBInst_0))))
+          (net wbc_ufm_irq
+            (joined
+              (portRef wbc_ufm_irq)
+              (portRef WBCUFMIRQ (instanceRef EFBInst_0))))
+          (net wb_ack_o
+            (joined
+              (portRef wb_ack_o)
+              (portRef WBACKO (instanceRef EFBInst_0))))
+          (net wb_dat_o7
+            (joined
+              (portRef (member wb_dat_o 0))
+              (portRef WBDATO7 (instanceRef EFBInst_0))))
+          (net wb_dat_o6
+            (joined
+              (portRef (member wb_dat_o 1))
+              (portRef WBDATO6 (instanceRef EFBInst_0))))
+          (net wb_dat_o5
+            (joined
+              (portRef (member wb_dat_o 2))
+              (portRef WBDATO5 (instanceRef EFBInst_0))))
+          (net wb_dat_o4
+            (joined
+              (portRef (member wb_dat_o 3))
+              (portRef WBDATO4 (instanceRef EFBInst_0))))
+          (net wb_dat_o3
+            (joined
+              (portRef (member wb_dat_o 4))
+              (portRef WBDATO3 (instanceRef EFBInst_0))))
+          (net wb_dat_o2
+            (joined
+              (portRef (member wb_dat_o 5))
+              (portRef WBDATO2 (instanceRef EFBInst_0))))
+          (net wb_dat_o1
+            (joined
+              (portRef (member wb_dat_o 6))
+              (portRef WBDATO1 (instanceRef EFBInst_0))))
+          (net wb_dat_o0
+            (joined
+              (portRef (member wb_dat_o 7))
+              (portRef WBDATO0 (instanceRef EFBInst_0))))
+          (net wb_dat_i7
+            (joined
+              (portRef (member wb_dat_i 0))
+              (portRef WBDATI7 (instanceRef EFBInst_0))))
+          (net wb_dat_i6
+            (joined
+              (portRef (member wb_dat_i 1))
+              (portRef WBDATI6 (instanceRef EFBInst_0))))
+          (net wb_dat_i5
+            (joined
+              (portRef (member wb_dat_i 2))
+              (portRef WBDATI5 (instanceRef EFBInst_0))))
+          (net wb_dat_i4
+            (joined
+              (portRef (member wb_dat_i 3))
+              (portRef WBDATI4 (instanceRef EFBInst_0))))
+          (net wb_dat_i3
+            (joined
+              (portRef (member wb_dat_i 4))
+              (portRef WBDATI3 (instanceRef EFBInst_0))))
+          (net wb_dat_i2
+            (joined
+              (portRef (member wb_dat_i 5))
+              (portRef WBDATI2 (instanceRef EFBInst_0))))
+          (net wb_dat_i1
+            (joined
+              (portRef (member wb_dat_i 6))
+              (portRef WBDATI1 (instanceRef EFBInst_0))))
+          (net wb_dat_i0
+            (joined
+              (portRef (member wb_dat_i 7))
+              (portRef WBDATI0 (instanceRef EFBInst_0))))
+          (net wb_adr_i7
+            (joined
+              (portRef (member wb_adr_i 0))
+              (portRef WBADRI7 (instanceRef EFBInst_0))))
+          (net wb_adr_i6
+            (joined
+              (portRef (member wb_adr_i 1))
+              (portRef WBADRI6 (instanceRef EFBInst_0))))
+          (net wb_adr_i5
+            (joined
+              (portRef (member wb_adr_i 2))
+              (portRef WBADRI5 (instanceRef EFBInst_0))))
+          (net wb_adr_i4
+            (joined
+              (portRef (member wb_adr_i 3))
+              (portRef WBADRI4 (instanceRef EFBInst_0))))
+          (net wb_adr_i3
+            (joined
+              (portRef (member wb_adr_i 4))
+              (portRef WBADRI3 (instanceRef EFBInst_0))))
+          (net wb_adr_i2
+            (joined
+              (portRef (member wb_adr_i 5))
+              (portRef WBADRI2 (instanceRef EFBInst_0))))
+          (net wb_adr_i1
+            (joined
+              (portRef (member wb_adr_i 6))
+              (portRef WBADRI1 (instanceRef EFBInst_0))))
+          (net wb_adr_i0
+            (joined
+              (portRef (member wb_adr_i 7))
+              (portRef WBADRI0 (instanceRef EFBInst_0))))
+          (net wb_we_i
+            (joined
+              (portRef wb_we_i)
+              (portRef WBWEI (instanceRef EFBInst_0))))
+          (net wb_stb_i
+            (joined
+              (portRef wb_stb_i)
+              (portRef WBSTBI (instanceRef EFBInst_0))))
+          (net wb_cyc_i
+            (joined
+              (portRef wb_cyc_i)
+              (portRef WBCYCI (instanceRef EFBInst_0))))
+          (net wb_rst_i
+            (joined
+              (portRef wb_rst_i)
+              (portRef WBRSTI (instanceRef EFBInst_0))))
+          (net wb_clk_i
+            (joined
+              (portRef wb_clk_i)
+              (portRef WBCLKI (instanceRef EFBInst_0))))))))
+  (design EFB
+    (cellRef EFB
+      (libraryRef ORCLIB)))
+)
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/EFB.ipx b/CPLD/LCMXO2/LCMXO2-640HC/EFB.ipx
new file mode 100644
index 0000000..0954007
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/EFB.ipx
@@ -0,0 +1,8 @@
+
+
+  
+		
+		
+		
+  
+
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/EFB.lpc b/CPLD/LCMXO2/LCMXO2-640HC/EFB.lpc
new file mode 100644
index 0000000..ae74b18
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/EFB.lpc
@@ -0,0 +1,141 @@
+[Device]
+Family=machxo2
+PartType=LCMXO2-640HC
+PartName=LCMXO2-640HC-4TG100C
+SpeedGrade=4
+Package=TQFP100
+OperatingCondition=COM
+Status=S
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=EFB
+CoreRevision=1.2
+ModuleName=EFB
+SourceFormat=Verilog HDL
+ParameterFileVersion=1.0
+Date=08/17/2021
+Time=05:48:29
+
+[Parameters]
+Verilog=1
+VHDL=0
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+freq=
+i2c1=0
+i2c1config=0
+i2c1_addr=7-Bit Addressing
+i2c1_ce=0
+i2c1_freq=100
+i2c1_sa=10000
+i2c1_we=0
+i2c2=0
+i2c2_addr=7-Bit Addressing
+i2c2_ce=0
+i2c2_freq=100
+i2c2_sa=10000
+i2c2_we=0
+ufm_addr=7-Bit Addressing
+ufm_sa=10000
+pll=0
+pll_cnt=1
+spi=0
+spi_clkinv=0
+spi_cs=1
+spi_en=0
+spi_freq=1
+spi_lsb=0
+spi_mode=Slave
+spi_ib=0
+spi_ph=0
+spi_hs=0
+spi_rxo=0
+spi_rxr=0
+spi_txo=0
+spi_txr=0
+spi_we=0
+static_tc=Static
+tc=0
+tc_clkinv=Positive
+tc_ctr=1
+tc_div=1
+tc_ipcap=0
+tc_mode=CTCM
+tc_ocr=32767
+tc_oflow=1
+tc_o=TOGGLE
+tc_opcomp=0
+tc_osc=0
+tc_sa_oflow=0
+tc_top=65535
+ufm=1
+ufm0=0
+ufm1=0
+ufm2=0
+ufm3=0
+ufm_cfg0=0
+ufm_cfg1=0
+wb_clk_freq=16
+ufm_usage=SHARED_EBR_TAG
+ufm_ebr=190
+ufm_remain=
+mem_size=1
+ufm_start=
+ufm_init=0
+memfile=
+ufm_dt=hex
+ufm0_ebr=
+mem_size0=1
+ufm0_init=0
+memfile0=
+ufm0_dt=hex
+ufm1_ebr=
+mem_size1=1
+ufm1_init=0
+memfile1=
+ufm1_dt=hex
+ufm2_ebr=
+mem_size2=1
+ufm2_init=0
+memfile2=
+ufm2_dt=hex
+ufm3_ebr=
+mem_size3=1
+ufm3_init=0
+memfile3=
+ufm3_dt=hex
+ufm_cfg0_ebr=
+mem_size_cfg0=1
+ufm_cfg0_init=0
+memfile_cfg0=
+ufm_cfg0_dt=hex
+ufm_cfg1_ebr=
+mem_size_cfg1=1
+ufm_cfg1_init=0
+memfile_cfg1=
+ufm_cfg1_dt=hex
+wb=1
+boot_option=Internal
+efb_ufm=0
+boot_option_internal=Single Boot
+internal_ufm0=0
+internal_ufm1=0
+efb_ufm_boot=
+tamperdr=0
+t_pwd=0
+t_lockflash=0
+t_manmode=0
+t_jtagport=0
+t_sspiport=0
+t_sic2port=0
+t_wbport=0
+t_portlock=0
+
+[Command]
+cmd_line= -w -n EFB -lang verilog -synth lse -bus_exp 7 -bb -type efb -arch xo2c00 -freq 16 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/EFB.naf b/CPLD/LCMXO2/LCMXO2-640HC/EFB.naf
new file mode 100644
index 0000000..bf6d243
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/EFB.naf
@@ -0,0 +1,31 @@
+wb_clk_i  i
+wb_rst_i  i
+wb_cyc_i  i
+wb_stb_i  i
+wb_we_i  i
+wb_adr_i[7]  i
+wb_adr_i[6]  i
+wb_adr_i[5]  i
+wb_adr_i[4]  i
+wb_adr_i[3]  i
+wb_adr_i[2]  i
+wb_adr_i[1]  i
+wb_adr_i[0]  i
+wb_dat_i[7]  i
+wb_dat_i[6]  i
+wb_dat_i[5]  i
+wb_dat_i[4]  i
+wb_dat_i[3]  i
+wb_dat_i[2]  i
+wb_dat_i[1]  i
+wb_dat_i[0]  i
+wb_dat_o[7]  o
+wb_dat_o[6]  o
+wb_dat_o[5]  o
+wb_dat_o[4]  o
+wb_dat_o[3]  o
+wb_dat_o[2]  o
+wb_dat_o[1]  o
+wb_dat_o[0]  o
+wb_ack_o  o
+wbc_ufm_irq  o
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/EFB.sort b/CPLD/LCMXO2/LCMXO2-640HC/EFB.sort
new file mode 100644
index 0000000..8437cdd
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/EFB.sort
@@ -0,0 +1 @@
+EFB.v
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/EFB.srp b/CPLD/LCMXO2/LCMXO2-640HC/EFB.srp
new file mode 100644
index 0000000..650b29b
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/EFB.srp
@@ -0,0 +1,26 @@
+SCUBA, Version Diamond (64-bit) 3.12.0.240.2
+Tue Aug 17 05:48:29 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+    Issued command   : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n EFB -lang verilog -synth lse -bus_exp 7 -bb -type efb -arch xo2c00 -freq 16 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640 
+    Circuit name     : EFB
+    Module type      : efb
+    Module Version   : 1.2
+    Ports            : 
+	Inputs       : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0]
+	Outputs      : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq
+    I/O buffer       : not inserted
+    EDIF output      : EFB.edn
+    Verilog output   : EFB.v
+    Verilog template : EFB_tmpl.v
+    Verilog purpose  : for synthesis and simulation
+    Bus notation     : big endian
+    Report output    : EFB.srp
+    Element Usage    :
+            EFB : 1
+    Estimated Resource Usage:
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/EFB.sym b/CPLD/LCMXO2/LCMXO2-640HC/EFB.sym
new file mode 100644
index 0000000000000000000000000000000000000000..98635d35b1f64bfccca3395cd1f2b9bd133a0e8b
GIT binary patch
literal 464
zcmYk2F-yZx5Xb-52x>(r;?Th%Lnm=~gCIyJX)_6Cs3?fOwuwS$r7^7r!4J?eh##P{
zba3og#9162J2^T#`hTy~7&!9dckk}qz3~b7IgAfkG6+>@ii@fo3a~3xni;lHsS(!G
zwr+)qj?VV>)j1ke3f?@o!d%ep=m_Z2$GG_C?*rq9^se0Hy~5UD(QCwaQC6BX|ZFcYUCvD=sl
zdh=}-XUq%Cuq735N3fQ*1ATjSt)t}TuM4p0)V%}Lq%6MF>B~|=T~0+%Vy&qUEl=${
zv8>W(
+
+    
+    
+        
+        
+            
+        
+        
+            
+        
+    
+    
+
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf b/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf
new file mode 100644
index 0000000..746bae4
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf
@@ -0,0 +1,215 @@
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+LOCATE COMP "Dout[0]" SITE "76" ;
+LOCATE COMP "Dout[6]" SITE "78" ;
+LOCATE COMP "Dout[7]" SITE "82" ;
+LOCATE COMP "Dout[4]" SITE "83" ;
+LOCATE COMP "Dout[5]" SITE "84" ;
+LOCATE COMP "Dout[3]" SITE "85" ;
+LOCATE COMP "Dout[1]" SITE "86" ;
+LOCATE COMP "Dout[2]" SITE "87" ;
+LOCATE COMP "Din[2]" SITE "88" ;
+LOCATE COMP "Din[1]" SITE "96" ;
+LOCATE COMP "Din[3]" SITE "97" ;
+LOCATE COMP "Din[5]" SITE "98" ;
+LOCATE COMP "Din[4]" SITE "99" ;
+LOCATE COMP "Din[7]" SITE "1" ;
+LOCATE COMP "Din[6]" SITE "2" ;
+LOCATE COMP "Din[0]" SITE "3" ;
+LOCATE COMP "LED" SITE "34" ;
+LOCATE COMP "RA[0]" SITE "66" ;
+LOCATE COMP "RA[1]" SITE "67" ;
+LOCATE COMP "RA[2]" SITE "69" ;
+LOCATE COMP "RA[3]" SITE "71" ;
+LOCATE COMP "RA[4]" SITE "74" ;
+LOCATE COMP "RA[5]" SITE "70" ;
+LOCATE COMP "RA[6]" SITE "68" ;
+LOCATE COMP "RA[7]" SITE "75" ;
+LOCATE COMP "RA[8]" SITE "65" ;
+LOCATE COMP "RA[9]" SITE "62" ;
+LOCATE COMP "RA[10]" SITE "64" ;
+LOCATE COMP "RA[11]" SITE "59" ;
+LOCATE COMP "RBA[1]" SITE "60" ;
+LOCATE COMP "RBA[0]" SITE "58" ;
+LOCATE COMP "RCKE" SITE "53" ;
+LOCATE COMP "RDQMH" SITE "51" ;
+LOCATE COMP "RDQML" SITE "48" ;
+LOCATE COMP "nRCAS" SITE "52" ;
+LOCATE COMP "nRCS" SITE "57" ;
+LOCATE COMP "nRRAS" SITE "54" ;
+LOCATE COMP "nRWE" SITE "49" ;
+LOCATE COMP "RD[0]" SITE "36" ;
+LOCATE COMP "RD[1]" SITE "37" ;
+LOCATE COMP "RD[2]" SITE "38" ;
+LOCATE COMP "RD[3]" SITE "39" ;
+LOCATE COMP "RD[4]" SITE "40" ;
+LOCATE COMP "RD[5]" SITE "41" ;
+LOCATE COMP "RD[6]" SITE "42" ;
+LOCATE COMP "RD[7]" SITE "43" ;
+LOCATE COMP "PHI2" SITE "8" ;
+LOCATE COMP "RCLK" SITE "63" ;
+LOCATE COMP "nCCAS" SITE "9" ;
+LOCATE COMP "nCRAS" SITE "17" ;
+LOCATE COMP "CROW[0]" SITE "10" ;
+LOCATE COMP "CROW[1]" SITE "16" ;
+LOCATE COMP "nFWE" SITE "15" ;
+LOCATE COMP "MAin[0]" SITE "14" ;
+LOCATE COMP "MAin[1]" SITE "12" ;
+LOCATE COMP "MAin[2]" SITE "13" ;
+LOCATE COMP "MAin[3]" SITE "21" ;
+LOCATE COMP "MAin[4]" SITE "20" ;
+LOCATE COMP "MAin[5]" SITE "19" ;
+LOCATE COMP "MAin[6]" SITE "24" ;
+LOCATE COMP "MAin[7]" SITE "18" ;
+LOCATE COMP "MAin[8]" SITE "25" ;
+LOCATE COMP "MAin[9]" SITE "32" ;
+IOBUF PORT "CROW[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "CROW[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "nCRAS" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "nCCAS" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "RCLK" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "PHI2" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "Din[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "Din[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "Din[2]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "Din[3]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "Din[4]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "Din[5]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "Din[6]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "Din[7]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[2]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[3]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[4]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[5]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[6]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[7]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[8]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "MAin[9]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "nFWE" PULLMODE=NONE IO_TYPE=LVTTL33 ;
+IOBUF PORT "Dout[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "Dout[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "Dout[2]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "Dout[3]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "Dout[4]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "Dout[5]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "Dout[6]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "Dout[7]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "LED" PULLMODE=NONE IO_TYPE=LVTTL33 DRIVE=16 SLEWRATE=SLOW ;
+IOBUF PORT "RA[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[2]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[3]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[4]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[5]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[6]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[7]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[8]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[9]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[10]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RA[11]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RBA[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RBA[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RCKE" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RDQMH" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RDQML" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "nRCAS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "nRCS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "nRRAS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "nRWE" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "RD[0]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
+IOBUF PORT "RD[1]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
+IOBUF PORT "RD[2]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
+IOBUF PORT "RD[3]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
+IOBUF PORT "RD[4]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
+IOBUF PORT "RD[5]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
+IOBUF PORT "RD[6]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
+IOBUF PORT "RD[7]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
+OUTPUT PORT "RD[7]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[0]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[1]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[2]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[3]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[4]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[5]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[6]" LOAD 20.000000 pF ;
+OUTPUT PORT "nRWE" LOAD 10.000000 pF ;
+OUTPUT PORT "nRCAS" LOAD 10.000000 pF ;
+OUTPUT PORT "nRCS" LOAD 10.000000 pF ;
+OUTPUT PORT "nRRAS" LOAD 10.000000 pF ;
+OUTPUT PORT "RDQML" LOAD 10.000000 pF ;
+OUTPUT PORT "RDQMH" LOAD 10.000000 pF ;
+OUTPUT PORT "RCKE" LOAD 10.000000 pF ;
+OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ;
+OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[11]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[10]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[9]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[8]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[7]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[6]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[5]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[4]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[3]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[2]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[1]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[0]" LOAD 10.000000 pF ;
+OUTPUT PORT "LED" LOAD 25.000000 pF ;
+OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ;
+USE PRIMARY NET "PHI2_c" ;
+USE PRIMARY NET "RCLK_c" ;
+VOLTAGE 3.300 V;
+VCCIO_DERATE BANK 0 PERCENT -5; 
+VCCIO_DERATE PERCENT -5; 
+VCCIO_DERATE BANK 1 PERCENT -5; 
+PERIOD NET "PHI2_c" 350.000000 ns  ;
+PERIOD NET "nCCAS_c" 350.000000 ns  ;
+PERIOD NET "nCRAS_c" 350.000000 ns  ;
+PERIOD NET "RCLK_c" 16.000000 ns  ;
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+USE PRIMARY NET "nCCAS_c" ;
+USE PRIMARY NET "nCRAS_c" ;
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC1.sty b/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC1.sty
new file mode 100644
index 0000000..feec63c
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC1.sty
@@ -0,0 +1,205 @@
+
+
+
+    
+    
+    
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+    
+
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcl.html b/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcl.html
new file mode 100644
index 0000000..6fda9a0
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcl.html
@@ -0,0 +1,84 @@
+
+Lattice TCL Log
+
+
+
    pn210817003052
+#Start recording tcl command: 8/16/2021 23:26:11
+#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
+prj_project new -name "RAM2GS_LCMXO2_640HC" -impl "impl1" -dev LCMXO2-640HC-4TG100C -synthesis "lse"
+prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v"
+prj_project save
+#Stop recording: 8/17/2021 00:30:52
+
+
+
+pn210817054927
+#Start recording tcl command: 8/17/2021 00:30:55
+#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
+prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+#Stop recording: 8/17/2021 05:49:27
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
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+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
+
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn210817003052.tcr b/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn210817003052.tcr
new file mode 100644
index 0000000..ffbaf5f
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn210817003052.tcr
@@ -0,0 +1,6 @@
+#Start recording tcl command: 8/16/2021 23:26:11
+#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
+prj_project new -name "RAM2GS_LCMXO2_640HC" -impl "impl1" -dev LCMXO2-640HC-4TG100C -synthesis "lse"
+prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v"
+prj_project save
+#Stop recording: 8/17/2021 00:30:52
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn210817054927.tcr b/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn210817054927.tcr
new file mode 100644
index 0000000..76d8b28
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn210817054927.tcr
@@ -0,0 +1,9 @@
+#Start recording tcl command: 8/17/2021 00:30:55
+#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
+prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+#Stop recording: 8/17/2021 05:49:27
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn210817062320.tcr b/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn210817062320.tcr
new file mode 100644
index 0000000..9f6f1a8
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn210817062320.tcr
@@ -0,0 +1,24 @@
+#Start recording tcl command: 8/17/2021 05:49:30
+#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
+prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/EFB.v"
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+prj_src remove "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/EFB.v"
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+prj_run Synthesis -impl impl1
+prj_run Synthesis -impl impl1 -forceOne
+prj_run Map -impl impl1 -forceOne
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceOne
+#Stop recording: 8/17/2021 06:23:20
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/_math_real.vhd b/CPLD/LCMXO2/LCMXO2-640HC/_math_real.vhd
new file mode 100644
index 0000000..ad185b2
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/_math_real.vhd
@@ -0,0 +1,2574 @@
+
+
+------------------------------------------------------------------------
+--
+-- Copyright 1996 by IEEE. All rights reserved.
+--
+-- This source file is an essential part of IEEE Std 1076.2-1996, IEEE Standard 
+-- VHDL Mathematical Packages. This source file may not be copied, sold, or 
+-- included with software that is sold without written permission from the IEEE
+-- Standards Department. This source file may be used to implement this standard 
+-- and may be distributed in compiled form in any manner so long as the 
+-- compiled form does not allow direct decompilation of the original source file.
+-- This source file may be copied for individual use between licensed users. 
+-- This source file is provided on an AS IS basis. The IEEE disclaims ANY 
+-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY 
+-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source 
+-- file shall indemnify and hold IEEE harmless from any damages or liability 
+-- arising out of the use thereof.
+--
+-- Title:       Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996, 
+--              MATH_REAL)
+--
+-- Library:     This package shall be compiled into a library
+--              symbolically named IEEE.
+--
+-- Developers:  IEEE DASC VHDL Mathematical Packages Working Group
+--
+-- Purpose:     This package defines a standard for designers to use in
+--              describing VHDL models that make use of common REAL constants
+--              and common REAL elementary mathematical functions.
+--
+-- Limitation:  The values generated by the functions in this package may
+--              vary from platform to platform, and the precision of results
+--              is only guaranteed to be the minimum required by IEEE Std 1076-
+--              1993.
+--
+-- Notes:
+--              No declarations or definitions shall be included in, or
+--              excluded from, this package.
+--              The "package declaration" defines the types, subtypes, and
+--              declarations of MATH_REAL.
+--              The standard mathematical definition and conventional meaning
+--              of the mathematical functions that are part of this standard
+--              represent the formal semantics of the implementation of the
+--              MATH_REAL package declaration.  The purpose of the MATH_REAL
+--              package body is to provide a guideline for implementations to
+--              verify their implementation of MATH_REAL.  Tool developers may
+--              choose to implement the package body in the most efficient
+--              manner available to them.
+--
+-- -----------------------------------------------------------------------------
+-- Version    : 1.5
+-- Date       : 24 July 1996
+-- -----------------------------------------------------------------------------
+
+package MATH_REAL is
+    constant CopyRightNotice: STRING
+      := "Copyright 1996 IEEE. All rights reserved.";
+
+    --
+    -- Constant Definitions
+    --
+    constant  MATH_E : REAL := 2.71828_18284_59045_23536;
+                                                      -- Value of e
+    constant  MATH_1_OVER_E : REAL := 0.36787_94411_71442_32160;
+                                                      -- Value of 1/e
+    constant  MATH_PI : REAL := 3.14159_26535_89793_23846;
+                                                      -- Value of pi
+    constant  MATH_2_PI : REAL := 6.28318_53071_79586_47693;
+                                                      -- Value of 2*pi
+    constant  MATH_1_OVER_PI : REAL := 0.31830_98861_83790_67154;
+                                                      -- Value of 1/pi
+    constant  MATH_PI_OVER_2 : REAL := 1.57079_63267_94896_61923;
+                                                      -- Value of pi/2
+    constant  MATH_PI_OVER_3 : REAL := 1.04719_75511_96597_74615;
+                                                      -- Value of pi/3
+    constant  MATH_PI_OVER_4 : REAL := 0.78539_81633_97448_30962;
+                                                      -- Value of pi/4
+    constant  MATH_3_PI_OVER_2 : REAL := 4.71238_89803_84689_85769;
+                                                      -- Value 3*pi/2
+    constant  MATH_LOG_OF_2 : REAL := 0.69314_71805_59945_30942;
+                                                      -- Natural log of 2
+    constant  MATH_LOG_OF_10 : REAL := 2.30258_50929_94045_68402;
+                                                      -- Natural log of 10
+    constant  MATH_LOG2_OF_E : REAL := 1.44269_50408_88963_4074;
+                                                      -- Log base 2 of e
+    constant  MATH_LOG10_OF_E: REAL := 0.43429_44819_03251_82765;
+                                                      -- Log base 10 of e
+    constant  MATH_SQRT_2: REAL := 1.41421_35623_73095_04880;
+                                                      -- square root of 2
+    constant  MATH_1_OVER_SQRT_2: REAL := 0.70710_67811_86547_52440;
+                                                      -- square root of 1/2
+    constant  MATH_SQRT_PI: REAL := 1.77245_38509_05516_02730;
+                                                      -- square root of pi
+    constant  MATH_DEG_TO_RAD: REAL := 0.01745_32925_19943_29577;
+                                     -- Conversion factor from degree to radian
+    constant  MATH_RAD_TO_DEG: REAL := 57.29577_95130_82320_87680;
+                                     -- Conversion factor from radian to degree
+
+    --
+    -- Function Declarations
+    --
+    function SIGN (X: in REAL ) return REAL;
+        -- Purpose:
+        --         Returns 1.0 if X > 0.0; 0.0 if X = 0.0; -1.0 if X < 0.0
+        -- Special values:
+        --         None
+        -- Domain:
+        --         X in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         ABS(SIGN(X)) <= 1.0
+        -- Notes:
+        --         None
+
+    function CEIL (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns smallest INTEGER value (as REAL) not less than X
+        -- Special values:
+        --         None
+        -- Domain:
+        --         X in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         CEIL(X) is mathematically unbounded
+        -- Notes:
+        --         a) Implementations have to support at least the domain
+        --                ABS(X) < REAL(INTEGER'HIGH)
+
+    function FLOOR (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns largest INTEGER value (as REAL) not greater than X
+        -- Special values:
+        --         FLOOR(0.0) = 0.0
+        -- Domain:
+        --         X in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         FLOOR(X) is mathematically unbounded
+        -- Notes:
+        --         a) Implementations have to support at least the domain
+        --                ABS(X) < REAL(INTEGER'HIGH)
+
+    function ROUND (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Rounds X to the nearest integer value (as real). If X is
+        --         halfway between two integers, rounding is away from 0.0
+        -- Special values:
+        --         ROUND(0.0) = 0.0
+        -- Domain:
+        --         X in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         ROUND(X) is mathematically unbounded
+        -- Notes:
+        --         a) Implementations have to support at least the domain
+        --                ABS(X) < REAL(INTEGER'HIGH)
+
+    function TRUNC (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Truncates X towards 0.0 and returns truncated value
+        -- Special values:
+        --         TRUNC(0.0) = 0.0
+        -- Domain:
+        --         X in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         TRUNC(X) is mathematically unbounded
+        -- Notes:
+        --         a) Implementations have to support at least the domain
+        --                ABS(X) < REAL(INTEGER'HIGH)
+
+    function "MOD" (X, Y: in REAL ) return REAL;
+        -- Purpose:
+        --         Returns floating point modulus of X/Y, with the same sign as
+        --         Y, and absolute value less than the absolute value of Y, and
+        --         for some INTEGER value N the result satisfies the relation
+        --         X = Y*N + MOD(X,Y)
+        -- Special values:
+        --         None
+        -- Domain:
+        --         X in REAL; Y in REAL and Y /= 0.0
+        -- Error conditions:
+        --         Error if Y = 0.0
+        -- Range:
+        --         ABS(MOD(X,Y)) < ABS(Y)
+        -- Notes:
+        --         None
+
+    function REALMAX (X, Y : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns the algebraically larger of X and Y
+        -- Special values:
+        --         REALMAX(X,Y) = X when X = Y
+        -- Domain:
+        --         X in REAL; Y in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         REALMAX(X,Y) is mathematically unbounded
+        -- Notes:
+        --         None
+
+    function REALMIN (X, Y : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns the algebraically smaller of X and Y
+        -- Special values:
+        --         REALMIN(X,Y) = X when X = Y
+        -- Domain:
+        --         X in REAL; Y in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         REALMIN(X,Y) is mathematically unbounded
+        -- Notes:
+        --         None
+
+    procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE; variable X:out REAL);
+        -- Purpose:
+        --         Returns, in X, a pseudo-random number with uniform
+        --         distribution in the open interval (0.0, 1.0).
+        -- Special values:
+        --         None
+        -- Domain:
+        --         1 <= SEED1 <= 2147483562; 1 <= SEED2 <= 2147483398
+        -- Error conditions:
+        --         Error if SEED1 or SEED2 outside of valid domain
+        -- Range:
+        --         0.0 < X < 1.0
+        -- Notes:
+        --         a) The semantics for this function are described by the
+        --            algorithm published by Pierre L'Ecuyer in "Communications
+        --            of the ACM," vol. 31, no. 6, June 1988, pp. 742-774.
+        --            The algorithm is based on the combination of two
+        --            multiplicative linear congruential generators for 32-bit
+        --            platforms.
+        --
+        --         b) Before the first call to UNIFORM, the seed values
+        --            (SEED1, SEED2) have to be initialized to values in the range
+        --            [1, 2147483562] and [1, 2147483398] respectively.  The
+        --            seed values are modified after each call to UNIFORM.
+        --
+        --         c) This random number generator is portable for 32-bit
+        --            computers, and it has a period of ~2.30584*(10**18) for each
+        --            set of seed values.
+        --
+        --         d) For information on spectral tests for the algorithm, refer
+        --            to the L'Ecuyer article.
+
+    function SQRT (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns square root of X
+        -- Special values:
+        --         SQRT(0.0) = 0.0
+        --         SQRT(1.0) = 1.0
+        -- Domain:
+        --         X >= 0.0
+        -- Error conditions:
+        --         Error if X < 0.0
+        -- Range:
+        --         SQRT(X) >= 0.0
+        -- Notes:
+        --         a) The upper bound of the reachable range of SQRT is
+        --            approximately given by:
+        --                SQRT(X) <= SQRT(REAL'HIGH)
+
+    function CBRT (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns cube root of X
+        -- Special values:
+        --         CBRT(0.0) = 0.0
+        --         CBRT(1.0) = 1.0
+        --         CBRT(-1.0) = -1.0
+        -- Domain:
+        --         X in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         CBRT(X) is mathematically unbounded
+        -- Notes:
+        --         a) The reachable range of CBRT is approximately given by:
+        --                ABS(CBRT(X)) <= CBRT(REAL'HIGH)
+
+    function "**" (X : in INTEGER; Y : in REAL) return REAL;
+        -- Purpose:
+        --         Returns Y power of X ==>  X**Y
+        -- Special values:
+        --         X**0.0 = 1.0; X /= 0
+        --         0**Y = 0.0; Y > 0.0
+        --         X**1.0 = REAL(X); X >= 0
+        --         1**Y = 1.0
+        -- Domain:
+        --         X > 0
+        --         X = 0 for Y > 0.0
+        --         X < 0 for Y = 0.0
+        -- Error conditions:
+        --         Error if X < 0 and Y /= 0.0
+        --         Error if X = 0 and Y <= 0.0
+        -- Range:
+        --         X**Y >= 0.0
+        -- Notes:
+        --         a) The upper bound of the reachable range for "**" is
+        --            approximately given by:
+        --                X**Y <= REAL'HIGH
+
+    function "**" (X : in REAL; Y : in REAL) return REAL;
+        -- Purpose:
+        --         Returns Y power of X ==>  X**Y
+        -- Special values:
+        --         X**0.0 = 1.0; X /= 0.0
+        --         0.0**Y = 0.0; Y > 0.0
+        --         X**1.0 = X; X >= 0.0
+        --         1.0**Y = 1.0
+        -- Domain:
+        --         X > 0.0
+        --         X = 0.0 for Y > 0.0
+        --         X < 0.0 for Y = 0.0
+        -- Error conditions:
+        --         Error if X < 0.0 and Y /= 0.0
+        --         Error if X = 0.0 and Y <= 0.0
+        -- Range:
+        --         X**Y >= 0.0
+        -- Notes:
+        --         a) The upper bound of the reachable range for "**" is
+        --            approximately given by:
+        --                X**Y <= REAL'HIGH
+
+    function EXP (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns e**X; where e = MATH_E
+        -- Special values:
+        --         EXP(0.0) = 1.0
+        --         EXP(1.0) = MATH_E
+        --         EXP(-1.0) = MATH_1_OVER_E
+        --         EXP(X) = 0.0 for X <= -LOG(REAL'HIGH)
+        -- Domain:
+        --         X in REAL such that EXP(X) <= REAL'HIGH
+        -- Error conditions:
+        --         Error if X > LOG(REAL'HIGH)
+        -- Range:
+        --         EXP(X) >= 0.0
+        -- Notes:
+        --         a) The usable domain of EXP is approximately given by:
+        --                X <= LOG(REAL'HIGH)
+
+    function LOG (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns natural logarithm of X
+        -- Special values:
+        --         LOG(1.0) = 0.0
+        --         LOG(MATH_E) = 1.0
+        -- Domain:
+        --         X > 0.0
+        -- Error conditions:
+        --         Error if X <= 0.0
+        -- Range:
+        --         LOG(X) is mathematically unbounded
+        -- Notes:
+        --         a) The reachable range of LOG is approximately given by:
+        --                LOG(0+) <= LOG(X) <= LOG(REAL'HIGH)
+
+    function LOG2 (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns logarithm base 2 of X
+        -- Special values:
+        --         LOG2(1.0) = 0.0
+        --         LOG2(2.0) = 1.0
+        -- Domain:
+        --         X > 0.0
+        -- Error conditions:
+        --         Error if X <= 0.0
+        -- Range:
+        --         LOG2(X) is mathematically unbounded
+        -- Notes:
+        --         a) The reachable range of LOG2 is approximately given by:
+        --                LOG2(0+) <= LOG2(X) <= LOG2(REAL'HIGH)
+
+    function LOG10 (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns logarithm base 10 of X
+        -- Special values:
+        --         LOG10(1.0) = 0.0
+        --         LOG10(10.0) = 1.0
+        -- Domain:
+        --         X > 0.0
+        -- Error conditions:
+        --         Error if X <= 0.0
+        -- Range:
+        --         LOG10(X) is mathematically unbounded
+        -- Notes:
+        --         a) The reachable range of LOG10 is approximately given by:
+        --                LOG10(0+) <= LOG10(X) <= LOG10(REAL'HIGH)
+
+    function LOG (X: in REAL; BASE: in REAL) return REAL;
+        -- Purpose:
+        --         Returns logarithm base BASE of X
+        -- Special values:
+        --         LOG(1.0, BASE) = 0.0
+        --         LOG(BASE, BASE) = 1.0
+        -- Domain:
+        --         X > 0.0
+        --         BASE > 0.0
+        --         BASE /= 1.0
+        -- Error conditions:
+        --         Error if X <= 0.0
+        --         Error if BASE <= 0.0
+        --         Error if BASE = 1.0
+        -- Range:
+        --         LOG(X, BASE) is mathematically unbounded
+        -- Notes:
+        --         a) When BASE > 1.0, the reachable range of LOG is
+        --            approximately given by:
+        --                LOG(0+, BASE) <= LOG(X, BASE) <= LOG(REAL'HIGH, BASE)
+        --         b) When 0.0 < BASE < 1.0, the reachable range of LOG is
+        --            approximately given by:
+        --                LOG(REAL'HIGH, BASE) <= LOG(X, BASE) <= LOG(0+, BASE)
+
+    function  SIN (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns sine of X; X in radians
+        -- Special values:
+        --         SIN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
+        --         SIN(X) = 1.0 for X = (4*k+1)*MATH_PI_OVER_2, where k is an
+        --                                                           INTEGER
+        --         SIN(X) = -1.0 for X = (4*k+3)*MATH_PI_OVER_2, where k is an
+        --                                                           INTEGER
+        -- Domain:
+        --         X in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         ABS(SIN(X)) <= 1.0
+        -- Notes:
+        --         a) For larger values of ABS(X), degraded accuracy is allowed.
+
+    function  COS ( X : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns cosine of X; X in radians
+        -- Special values:
+        --         COS(X) = 0.0 for X = (2*k+1)*MATH_PI_OVER_2, where k is an
+        --                                                            INTEGER
+        --         COS(X) = 1.0 for X = (2*k)*MATH_PI, where k is an INTEGER
+        --         COS(X) = -1.0 for X = (2*k+1)*MATH_PI, where k is an INTEGER
+        -- Domain:
+        --         X in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         ABS(COS(X)) <= 1.0
+        -- Notes:
+        --         a) For larger values of ABS(X), degraded accuracy is allowed.
+
+    function  TAN (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns tangent of X; X in radians
+        -- Special values:
+        --         TAN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
+        -- Domain:
+        --         X in REAL and
+        --         X /= (2*k+1)*MATH_PI_OVER_2, where k is an INTEGER
+        -- Error conditions:
+        --         Error if X = ((2*k+1) * MATH_PI_OVER_2), where k is an
+        --                                                           INTEGER
+        -- Range:
+        --         TAN(X) is mathematically unbounded
+        -- Notes:
+        --         a) For larger values of ABS(X), degraded accuracy is allowed.
+
+    function  ARCSIN (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns inverse sine of X
+        -- Special values:
+        --         ARCSIN(0.0) = 0.0
+        --         ARCSIN(1.0) = MATH_PI_OVER_2
+        --         ARCSIN(-1.0) = -MATH_PI_OVER_2
+        -- Domain:
+        --         ABS(X) <= 1.0
+        -- Error conditions:
+        --         Error if ABS(X) > 1.0
+        -- Range:
+        --         ABS(ARCSIN(X) <= MATH_PI_OVER_2
+        -- Notes:
+        --         None
+
+    function  ARCCOS (X : in REAL ) return REAL;
+        -- Purpose:
+        --         Returns inverse cosine of X
+        -- Special values:
+        --         ARCCOS(1.0) = 0.0
+        --         ARCCOS(0.0) = MATH_PI_OVER_2
+        --         ARCCOS(-1.0) = MATH_PI
+        -- Domain:
+        --         ABS(X) <= 1.0
+        -- Error conditions:
+        --         Error if ABS(X) > 1.0
+        -- Range:
+        --         0.0 <= ARCCOS(X) <= MATH_PI
+        -- Notes:
+        --         None
+
+    function  ARCTAN (Y : in REAL) return REAL;
+        -- Purpose:
+        --         Returns the value of the angle in radians of the point
+        --        (1.0, Y), which is in rectangular coordinates
+        -- Special values:
+        --         ARCTAN(0.0) = 0.0
+        -- Domain:
+        --         Y in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         ABS(ARCTAN(Y)) <= MATH_PI_OVER_2
+        -- Notes:
+        --         None
+
+    function  ARCTAN (Y : in REAL; X : in REAL) return REAL;
+        -- Purpose:
+        --         Returns the principal value of the angle in radians of
+        --         the point (X, Y), which is in rectangular coordinates
+        -- Special values:
+        --         ARCTAN(0.0, X) = 0.0 if X > 0.0
+        --         ARCTAN(0.0, X) = MATH_PI if X < 0.0
+        --         ARCTAN(Y, 0.0) = MATH_PI_OVER_2 if Y > 0.0
+        --         ARCTAN(Y, 0.0) = -MATH_PI_OVER_2 if Y < 0.0
+        -- Domain:
+        --         Y in REAL
+        --         X in REAL, X /= 0.0 when Y = 0.0
+        -- Error conditions:
+        --         Error if X = 0.0 and Y = 0.0
+        -- Range:
+        --         -MATH_PI < ARCTAN(Y,X) <= MATH_PI
+        -- Notes:
+        --         None
+
+    function SINH (X : in REAL) return REAL;
+        -- Purpose:
+        --         Returns hyperbolic sine of X
+        -- Special values:
+        --         SINH(0.0) = 0.0
+        -- Domain:
+        --         X in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         SINH(X) is mathematically unbounded
+        -- Notes:
+        --         a) The usable domain of SINH is approximately given by:
+        --                ABS(X) <= LOG(REAL'HIGH)
+
+
+    function COSH (X : in REAL) return REAL;
+        -- Purpose:
+        --         Returns hyperbolic cosine of X
+        -- Special values:
+        --         COSH(0.0) = 1.0
+        -- Domain:
+        --         X in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         COSH(X) >= 1.0
+        -- Notes:
+        --         a) The usable domain of COSH is approximately given by:
+        --                ABS(X) <= LOG(REAL'HIGH)
+
+    function TANH (X : in REAL) return REAL;
+        -- Purpose:
+        --         Returns hyperbolic tangent of X
+        -- Special values:
+        --         TANH(0.0) = 0.0
+        -- Domain:
+        --         X in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         ABS(TANH(X)) <= 1.0
+        -- Notes:
+        --         None
+
+    function ARCSINH (X : in REAL) return REAL;
+        -- Purpose:
+        --         Returns inverse hyperbolic sine of X
+        -- Special values:
+        --         ARCSINH(0.0) = 0.0
+        -- Domain:
+        --         X in REAL
+        -- Error conditions:
+        --         None
+        -- Range:
+        --         ARCSINH(X) is mathematically unbounded
+        -- Notes:
+        --         a) The reachable range of ARCSINH is approximately given by:
+        --                ABS(ARCSINH(X)) <= LOG(REAL'HIGH)
+
+    function ARCCOSH (X : in REAL) return REAL;
+        -- Purpose:
+        --         Returns inverse hyperbolic cosine of X
+        -- Special values:
+        --         ARCCOSH(1.0) = 0.0
+        -- Domain:
+        --         X >= 1.0
+        -- Error conditions:
+        --         Error if X < 1.0
+        -- Range:
+        --         ARCCOSH(X) >= 0.0
+        -- Notes:
+        --         a) The upper bound of the reachable range of ARCCOSH is
+        --            approximately given by:   ARCCOSH(X) <= LOG(REAL'HIGH)
+
+    function ARCTANH (X : in REAL) return REAL;
+        -- Purpose:
+        --         Returns inverse hyperbolic tangent of X
+        -- Special values:
+        --         ARCTANH(0.0) = 0.0
+        -- Domain:
+        --         ABS(X) < 1.0
+        -- Error conditions:
+        --         Error if ABS(X) >= 1.0
+        -- Range:
+        --         ARCTANH(X) is mathematically unbounded
+        -- Notes:
+        --         a) The reachable range of ARCTANH is approximately given by:
+        --                ABS(ARCTANH(X)) < LOG(REAL'HIGH)
+
+end  MATH_REAL;
+
+
+
+------------------------------------------------------------------------
+--
+-- Copyright 1996 by IEEE. All rights reserved.
+
+-- This source file is an informative part of IEEE Std 1076.2-1996, IEEE Standard 
+-- VHDL Mathematical Packages. This source file may not be copied, sold, or 
+-- included with software that is sold without written permission from the IEEE
+-- Standards Department. This source file may be used to implement this standard 
+-- and may be distributed in compiled form in any manner so long as the 
+-- compiled form does not allow direct decompilation of the original source file.
+-- This source file may be copied for individual use between licensed users. 
+-- This source file is provided on an AS IS basis. The IEEE disclaims ANY 
+-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY 
+-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source 
+-- file shall indemnify and hold IEEE harmless from any damages or liability 
+-- arising out of the use thereof.
+
+--
+-- Title:       Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996,
+--              MATH_REAL)
+--
+-- Library:     This package shall be compiled into a library
+--              symbolically named IEEE.
+--
+-- Developers:  IEEE DASC VHDL Mathematical Packages Working Group
+--
+-- Purpose:     This package body is a nonnormative implementation of the 
+--              functionality defined in the MATH_REAL package declaration.
+--
+-- Limitation:  The values generated by the functions in this package may
+--              vary from platform to platform, and the precision of results
+--              is only guaranteed to be the minimum required by IEEE Std 1076
+--              -1993.
+--
+-- Notes:
+--              The "package declaration" defines the types, subtypes, and
+--              declarations of MATH_REAL.
+--              The standard mathematical definition and conventional meaning
+--              of the mathematical functions that are part of this standard
+--              represent the formal semantics of the implementation of the
+--              MATH_REAL package declaration.  The purpose of the MATH_REAL
+--              package body is to clarify such semantics and provide a
+--              guideline for implementations to verify their implementation
+--              of MATH_REAL.  Tool developers may choose to implement
+--              the package body in the most efficient manner available to them.
+--
+-- -----------------------------------------------------------------------------
+-- Version    : 1.5
+-- Date       : 24 July 1996
+-- -----------------------------------------------------------------------------
+
+package body MATH_REAL is
+
+    --
+    -- Local Constants for Use in the Package Body Only
+    --
+    constant  MATH_E_P2 :  REAL := 7.38905_60989_30650;   -- e**2
+    constant  MATH_E_P10 :  REAL := 22026.46579_48067_17; -- e**10
+    constant  MATH_EIGHT_PI : REAL := 25.13274_12287_18345_90770_115; --8*pi
+    constant  MAX_ITER:  INTEGER := 27;  -- Maximum precision factor for cordic
+    constant  MAX_COUNT: INTEGER := 150; -- Maximum count for number of tries
+    constant  BASE_EPS: REAL := 0.00001;  -- Factor for convergence criteria
+    constant  KC : REAL := 6.0725293500888142e-01; -- Constant for cordic
+
+    --
+    -- Local Type Declarations for Cordic Operations
+    --
+    type REAL_VECTOR is array (NATURAL range <>) of REAL;
+    type NATURAL_VECTOR is array (NATURAL range <>) of NATURAL;
+    subtype REAL_VECTOR_N is REAL_VECTOR (0 to MAX_ITER);
+    subtype REAL_ARR_2 is REAL_VECTOR (0 to 1);
+    subtype REAL_ARR_3 is REAL_VECTOR (0 to 2);
+    subtype QUADRANT is INTEGER range 0 to 3;
+    type CORDIC_MODE_TYPE is (ROTATION, VECTORING);
+
+    --
+    -- Auxiliary Functions for Cordic Algorithms
+    --
+    function POWER_OF_2_SERIES (D : in NATURAL_VECTOR; INITIAL_VALUE : in REAL;
+                NUMBER_OF_VALUES : in NATURAL) return REAL_VECTOR is
+        -- Description:
+        --        Returns power of two for a vector of values
+        -- Notes:
+        --        None
+        --
+        variable V : REAL_VECTOR (0 to NUMBER_OF_VALUES);
+        variable TEMP : REAL := INITIAL_VALUE;
+        variable FLAG : BOOLEAN := TRUE;
+    begin
+              for I in 0 to NUMBER_OF_VALUES loop
+                 V(I) := TEMP;
+                 for P in D'RANGE loop
+                            if I = D(P) then
+                                FLAG := FALSE;
+                                exit;
+                            end if;
+                 end loop;
+                 if FLAG then
+                            TEMP := TEMP/2.0;
+                 end if;
+                 FLAG := TRUE;
+              end loop;
+              return V;
+    end POWER_OF_2_SERIES;
+
+
+    constant TWO_AT_MINUS : REAL_VECTOR := POWER_OF_2_SERIES(
+                                               NATURAL_VECTOR'(100, 90),1.0,
+                                                                  MAX_ITER);
+
+    constant EPSILON : REAL_VECTOR_N := (
+                                        7.8539816339744827e-01,
+                                        4.6364760900080606e-01,
+                                        2.4497866312686413e-01,
+                                        1.2435499454676144e-01,
+                                        6.2418809995957351e-02,
+                                        3.1239833430268277e-02,
+                                        1.5623728620476830e-02,
+                                        7.8123410601011116e-03,
+                                        3.9062301319669717e-03,
+                                        1.9531225164788189e-03,
+                                        9.7656218955931937e-04,
+                                        4.8828121119489829e-04,
+                                        2.4414062014936175e-04,
+                                        1.2207031189367021e-04,
+                                        6.1035156174208768e-05,
+                                        3.0517578115526093e-05,
+                                        1.5258789061315760e-05,
+                                        7.6293945311019699e-06,
+                                        3.8146972656064960e-06,
+                                        1.9073486328101870e-06,
+                                        9.5367431640596080e-07,
+                                        4.7683715820308876e-07,
+                                        2.3841857910155801e-07,
+                                        1.1920928955078067e-07,
+                                        5.9604644775390553e-08,
+                                        2.9802322387695303e-08,
+                                        1.4901161193847654e-08,
+                                        7.4505805969238281e-09
+                                       );
+
+    function CORDIC ( X0 : in REAL;
+                      Y0 : in REAL;
+                      Z0 : in REAL;
+                      N : in NATURAL;                 --  Precision factor
+            CORDIC_MODE : in CORDIC_MODE_TYPE         --  Rotation (Z -> 0)
+                                                      --  or vectoring (Y -> 0)
+                    ) return REAL_ARR_3 is
+        -- Description:
+        --        Compute cordic values
+        -- Notes:
+        --         None
+             variable X : REAL := X0;
+             variable Y : REAL := Y0;
+             variable Z : REAL := Z0;
+             variable X_TEMP : REAL;
+    begin
+       if CORDIC_MODE = ROTATION then
+           for K in 0 to N loop
+                      X_TEMP := X;
+                      if ( Z >= 0.0) then
+                               X := X - Y * TWO_AT_MINUS(K);
+                               Y := Y + X_TEMP * TWO_AT_MINUS(K);
+                               Z := Z - EPSILON(K);
+                      else
+                               X := X + Y * TWO_AT_MINUS(K);
+                               Y := Y - X_TEMP * TWO_AT_MINUS(K);
+                               Z := Z + EPSILON(K);
+                      end if;
+            end loop;
+        else
+            for K in 0 to N loop
+                    X_TEMP := X;
+                    if ( Y < 0.0) then
+                               X := X - Y * TWO_AT_MINUS(K);
+                               Y := Y + X_TEMP * TWO_AT_MINUS(K);
+                               Z := Z - EPSILON(K);
+                    else
+                               X := X + Y * TWO_AT_MINUS(K);
+                               Y := Y - X_TEMP * TWO_AT_MINUS(K);
+                               Z := Z + EPSILON(K);
+                    end if;
+            end loop;
+        end if;
+        return REAL_ARR_3'(X, Y, Z);
+    end CORDIC;
+
+    --
+    -- Bodies for Global Mathematical Functions Start Here
+    --
+    function SIGN (X: in REAL ) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        None
+    begin
+           if  ( X > 0.0 )  then
+                return 1.0;
+           elsif ( X < 0.0 )  then
+                return -1.0;
+           else
+                return 0.0;
+           end if;
+    end SIGN;
+
+    function CEIL (X : in REAL ) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) No conversion to an INTEGER type is expected, so truncate
+        --           cannot overflow for large arguments
+        --        b) The domain supported by this function is X <= LARGE
+        --        c) Returns X if ABS(X) >= LARGE
+
+        constant LARGE: REAL  := REAL(INTEGER'HIGH);
+        variable RD: REAL;
+
+    begin
+         if ABS(X) >= LARGE then
+               return X;
+         end if;
+
+         RD := REAL ( INTEGER(X));
+         if RD = X then
+            return X;
+         end if;
+
+            if X > 0.0 then
+                       if RD >= X then
+                                  return RD;
+                       else
+                                  return RD + 1.0;
+                       end if;
+            elsif  X = 0.0  then
+                return 0.0;
+            else
+                       if RD <= X then
+                                  return RD + 1.0;
+                       else
+                                  return RD;
+                       end if;
+            end if;
+    end CEIL;
+
+    function FLOOR (X : in REAL ) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) No conversion to an INTEGER type is expected, so truncate
+        --           cannot overflow for large arguments
+        --        b) The domain supported by this function is ABS(X) <= LARGE
+        --        c) Returns X if ABS(X) >= LARGE
+
+        constant LARGE: REAL  := REAL(INTEGER'HIGH);
+        variable RD: REAL;
+
+    begin
+        if ABS( X ) >= LARGE then
+                    return X;
+        end if;
+
+        RD := REAL ( INTEGER(X));
+        if RD = X then
+                return X;
+        end if;
+
+        if X > 0.0 then
+                      if RD <= X then
+                                  return RD;
+                       else
+                                  return RD - 1.0;
+                       end if;
+        elsif  X = 0.0  then
+                return 0.0;
+        else
+                   if RD >= X then
+                                  return RD - 1.0;
+                   else
+                                  return RD;
+                   end if;
+        end if;
+    end FLOOR;
+
+    function ROUND (X : in REAL ) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --         a) Returns 0.0 if X = 0.0
+        --         b) Returns FLOOR(X + 0.5) if X > 0
+        --         c) Returns CEIL(X - 0.5) if X < 0
+
+    begin
+           if  X > 0.0  then
+                return FLOOR(X + 0.5);
+           elsif  X < 0.0  then
+                return CEIL( X - 0.5);
+           else
+                return 0.0;
+           end if;
+    end ROUND;
+
+    function TRUNC (X : in REAL ) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --         a) Returns 0.0 if X = 0.0
+        --         b) Returns FLOOR(X) if X > 0
+        --         c) Returns CEIL(X) if X < 0
+
+    begin
+           if  X > 0.0  then
+                return FLOOR(X);
+           elsif  X < 0.0  then
+                return CEIL( X);
+           else
+                return 0.0;
+           end if;
+    end TRUNC;
+
+
+
+
+    function "MOD" (X, Y: in REAL ) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Returns 0.0 on error
+
+        variable XNEGATIVE : BOOLEAN := X < 0.0;
+        variable YNEGATIVE : BOOLEAN := Y < 0.0;
+        variable VALUE : REAL;
+    begin
+        -- Check validity of input arguments
+            if (Y = 0.0) then
+                 assert FALSE
+                        report "MOD(X, 0.0) is undefined"
+                        severity ERROR;
+                 return 0.0;
+              end if;
+
+        -- Compute value
+        if ( XNEGATIVE ) then
+                if ( YNEGATIVE ) then
+                        VALUE := X + (FLOOR(ABS(X)/ABS(Y)))*ABS(Y);
+                else
+                        VALUE := X + (CEIL(ABS(X)/ABS(Y)))*ABS(Y);
+                end if;
+        else
+                if ( YNEGATIVE ) then
+                        VALUE := X - (CEIL(ABS(X)/ABS(Y)))*ABS(Y);
+                else
+                        VALUE := X - (FLOOR(ABS(X)/ABS(Y)))*ABS(Y);
+                end if;
+        end if;
+
+        return VALUE;
+    end "MOD";
+
+
+    function REALMAX (X, Y : in REAL ) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) REALMAX(X,Y) = X when X = Y
+        --
+    begin
+        if X >= Y then
+           return X;
+        else
+           return Y;
+        end if;
+    end REALMAX;
+
+    function REALMIN (X, Y : in REAL ) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) REALMIN(X,Y) = X when X = Y
+        --
+    begin
+        if X <= Y then
+           return X;
+        else
+           return Y;
+        end if;
+    end REALMIN;
+
+
+    procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE;variable X:out REAL)
+                                                                         is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Returns 0.0 on error
+        --
+        variable Z, K: INTEGER;
+        variable TSEED1 : INTEGER := INTEGER'(SEED1);
+        variable TSEED2 : INTEGER := INTEGER'(SEED2);
+    begin
+        -- Check validity of arguments
+        if SEED1 > 2147483562 then
+                assert FALSE
+                        report "SEED1 > 2147483562 in UNIFORM"
+                        severity ERROR;
+                X := 0.0;
+                return;
+        end if;
+
+        if SEED2 > 2147483398 then
+                assert FALSE
+                        report "SEED2 > 2147483398 in UNIFORM"
+                        severity ERROR;
+                X := 0.0;
+                return;
+        end if;
+
+        -- Compute new seed values and pseudo-random number
+        K := TSEED1/53668;
+        TSEED1 := 40014 * (TSEED1 - K * 53668) - K * 12211;
+
+        if TSEED1 < 0  then
+                TSEED1 := TSEED1 + 2147483563;
+        end if;
+
+        K := TSEED2/52774;
+        TSEED2 := 40692 * (TSEED2 - K * 52774) - K * 3791;
+
+        if TSEED2 < 0  then
+                TSEED2 := TSEED2 + 2147483399;
+        end if;
+
+        Z := TSEED1 - TSEED2;
+        if Z < 1 then
+                Z := Z + 2147483562;
+        end if;
+
+        -- Get output values
+        SEED1 := POSITIVE'(TSEED1);
+        SEED2 := POSITIVE'(TSEED2);
+        X :=  REAL(Z)*4.656613e-10;
+    end UNIFORM;
+
+
+
+    function SQRT (X : in REAL ) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Uses the Newton-Raphson approximation:
+        --            F(n+1) = 0.5*[F(n) + x/F(n)]
+        --        b) Returns 0.0 on error
+        --
+
+        constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence factor
+
+        variable INIVAL: REAL;
+        variable OLDVAL : REAL ;
+        variable NEWVAL : REAL ;
+        variable COUNT : INTEGER := 1;
+
+    begin
+        -- Check validity of argument
+        if ( X < 0.0 ) then
+                assert FALSE
+                        report "X < 0.0 in SQRT(X)"
+                        severity ERROR;
+                return 0.0;
+        end if;
+
+        -- Get the square root for special cases
+        if X = 0.0 then
+                  return 0.0;
+        else
+                if ( X = 1.0 ) then
+                        return 1.0;
+                end if;
+        end if;
+
+        -- Get the square root for general cases
+        INIVAL := EXP(LOG(X)*(0.5)); -- Mathematically correct but imprecise
+        OLDVAL := INIVAL;
+        NEWVAL := (X/OLDVAL + OLDVAL)*0.5;
+
+        -- Check for  relative and absolute error and max count
+        while  ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS) OR
+                   (ABS(NEWVAL - OLDVAL) > EPS) ) AND
+                   (COUNT < MAX_COUNT) )  loop
+                OLDVAL := NEWVAL;
+                NEWVAL := (X/OLDVAL + OLDVAL)*0.5;
+                COUNT := COUNT + 1;
+        end loop;
+        return NEWVAL;
+    end SQRT;
+
+    function CBRT (X : in REAL ) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Uses the Newton-Raphson approximation:
+        --            F(n+1) = (1/3)*[2*F(n) + x/F(n)**2];
+        --
+        constant EPS : REAL := BASE_EPS*BASE_EPS;
+
+        variable INIVAL: REAL;
+        variable XLOCAL : REAL := X;
+        variable NEGATIVE : BOOLEAN := X < 0.0;
+        variable OLDVAL : REAL ;
+        variable NEWVAL : REAL ;
+        variable COUNT : INTEGER := 1;
+
+    begin
+
+        -- Compute root for special cases
+        if X = 0.0 then
+                return 0.0;
+        elsif ( X = 1.0 ) then
+                return 1.0;
+        else
+                if X = -1.0 then
+                        return -1.0;
+                end if;
+        end if;
+
+        -- Compute root for general cases
+        if NEGATIVE then
+                XLOCAL := -X;
+        end if;
+
+        INIVAL := EXP(LOG(XLOCAL)/(3.0)); -- Mathematically correct but
+                                          -- imprecise
+        OLDVAL := INIVAL;
+        NEWVAL := (XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0;
+
+        -- Check for relative and absolute errors and max count
+        while ( (  (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS ) OR
+                   (ABS(NEWVAL - OLDVAL) > EPS ) )  AND
+                   ( COUNT < MAX_COUNT ) ) loop
+                OLDVAL := NEWVAL;
+                NEWVAL :=(XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0;
+                COUNT := COUNT + 1;
+        end loop;
+
+        if NEGATIVE then
+                NEWVAL := -NEWVAL;
+        end if;
+
+        return NEWVAL;
+    end CBRT;
+
+    function "**" (X : in INTEGER; Y : in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Returns 0.0 on error condition
+
+    begin
+        -- Check validity of argument
+        if ( ( X < 0  ) and ( Y /= 0.0 ) ) then
+                assert FALSE
+                        report "X < 0 and Y /= 0.0 in X**Y"
+                        severity ERROR;
+                return 0.0;
+        end if;
+
+        if ( ( X = 0  ) and ( Y <= 0.0 ) ) then
+                assert FALSE
+                        report "X = 0 and Y <= 0.0 in X**Y"
+                        severity ERROR;
+                return 0.0;
+        end if;
+
+        -- Get value for special cases
+        if ( X = 0  and  Y > 0.0 ) then
+                return 0.0;
+        end if;
+
+        if ( X = 1 ) then
+                return 1.0;
+        end if;
+
+        if ( Y = 0.0 and X /= 0 ) then
+                return 1.0;
+        end if;
+
+        if ( Y = 1.0) then
+                return (REAL(X));
+        end if;
+
+        -- Get value for general case
+        return EXP (Y * LOG (REAL(X)));
+    end "**";
+
+    function "**" (X : in REAL; Y : in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Returns 0.0 on error condition
+
+    begin
+        -- Check validity of argument
+        if ( ( X < 0.0  ) and ( Y /= 0.0 ) ) then
+                assert FALSE
+                        report "X < 0.0 and Y /= 0.0 in X**Y"
+                        severity ERROR;
+                return 0.0;
+        end if;
+
+        if ( ( X = 0.0  ) and ( Y <= 0.0 ) ) then
+                assert FALSE
+                        report "X = 0.0 and Y <= 0.0 in X**Y"
+                        severity ERROR;
+                return 0.0;
+        end if;
+
+        -- Get value for special cases
+        if ( X = 0.0  and  Y > 0.0 ) then
+                return 0.0;
+        end if;
+
+        if ( X = 1.0 ) then
+                return 1.0;
+        end if;
+
+        if ( Y = 0.0 and X /= 0.0 ) then
+                return 1.0;
+        end if;
+
+        if ( Y = 1.0) then
+                return (X);
+        end if;
+
+        -- Get value for general case
+        return EXP (Y * LOG (X));
+    end "**";
+
+    function EXP  (X : in REAL ) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) This function computes the exponential using the following
+        --           series:
+        --                exp(x) = 1 + x + x**2/2! + x**3/3! + ... ; |x| < 1.0
+        --           and reduces argument X to take advantage of exp(x+y) =
+        --           exp(x)*exp(y)
+        --
+        --        b) This implementation limits X to be less than LOG(REAL'HIGH)
+        --           to avoid overflow.  Returns REAL'HIGH when X reaches that
+        --           limit
+        --
+        constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;-- Precision criteria
+
+            variable RECIPROCAL: BOOLEAN := X < 0.0;-- Check sign of argument
+            variable XLOCAL : REAL := ABS(X);       -- Use positive value
+            variable OLDVAL: REAL ;
+            variable COUNT: INTEGER ;
+            variable NEWVAL: REAL ;
+            variable LAST_TERM: REAL ;
+        variable FACTOR : REAL := 1.0;
+
+     begin
+            -- Compute value for special cases
+        if X = 0.0 then
+                return 1.0;
+        end if;
+
+        if  XLOCAL = 1.0  then
+                if RECIPROCAL then
+                        return MATH_1_OVER_E;
+                else
+                        return MATH_E;
+                end if;
+        end if;
+
+        if  XLOCAL = 2.0  then
+                if RECIPROCAL then
+                        return 1.0/MATH_E_P2;
+                else
+                        return MATH_E_P2;
+                end if;
+        end if;
+
+        if  XLOCAL = 10.0  then
+                if RECIPROCAL then
+                        return 1.0/MATH_E_P10;
+                else
+                        return MATH_E_P10;
+                end if;
+        end if;
+
+        if XLOCAL > LOG(REAL'HIGH) then
+                if RECIPROCAL then
+                        return 0.0;
+                else
+                        assert FALSE
+                                report "X > LOG(REAL'HIGH) in EXP(X)"
+                                severity NOTE;
+                        return REAL'HIGH;
+                end if;
+        end if;
+
+        -- Reduce argument to ABS(X) < 1.0
+        while XLOCAL > 10.0 loop
+                XLOCAL := XLOCAL - 10.0;
+                FACTOR := FACTOR*MATH_E_P10;
+        end loop;
+
+        while XLOCAL > 1.0 loop
+                XLOCAL := XLOCAL - 1.0;
+                FACTOR := FACTOR*MATH_E;
+        end loop;
+
+        -- Compute value for case 0 < XLOCAL < 1
+        OLDVAL := 1.0;
+        LAST_TERM := XLOCAL;
+        NEWVAL:= OLDVAL + LAST_TERM;
+        COUNT := 2;
+
+        -- Check for relative and absolute errors and max count
+        while ( ( (ABS((NEWVAL - OLDVAL)/NEWVAL) > EPS) OR
+                  (ABS(NEWVAL - OLDVAL) > EPS) ) AND
+                  (COUNT < MAX_COUNT ) ) loop
+                OLDVAL := NEWVAL;
+                LAST_TERM := LAST_TERM*(XLOCAL / (REAL(COUNT)));
+                NEWVAL := OLDVAL + LAST_TERM;
+                COUNT := COUNT + 1;
+        end loop;
+
+        -- Compute final value using exp(x+y) = exp(x)*exp(y)
+        NEWVAL := NEWVAL*FACTOR;
+
+        if RECIPROCAL then
+                NEWVAL := 1.0/NEWVAL;
+        end if;
+
+        return NEWVAL;
+     end EXP;
+
+
+    --
+    -- Auxiliary Functions to Compute LOG
+    --
+    function ILOGB(X: in REAL) return INTEGER IS
+        -- Description:
+        --        Returns n such that -1 <= ABS(X)/2^n < 2
+        -- Notes:
+        --        None
+
+        variable N: INTEGER := 0;
+        variable Y: REAL := ABS(X);
+
+    begin
+        if(Y = 1.0 or Y = 0.0) then
+                return 0;
+        end if;
+
+        if( Y > 1.0) then
+                while Y >= 2.0 loop
+                        Y := Y/2.0;
+                        N := N+1;
+                end loop;
+                return N;
+        end if;
+
+        -- O < Y < 1
+        while Y < 1.0 loop
+                Y := Y*2.0;
+                N := N -1;
+        end loop;
+        return N;
+    end ILOGB;
+
+    function LDEXP(X: in REAL; N: in INTEGER) RETURN REAL IS
+        -- Description:
+        --        Returns X*2^n
+        -- Notes:
+        --         None
+    begin
+        return X*(2.0 ** N);
+    end LDEXP;
+
+    function LOG (X : in REAL ) return REAL IS
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        --
+        -- Notes:
+        --        a) Returns REAL'LOW on error
+        --
+        -- Copyright (c) 1992 Regents of the University of California.
+        -- All rights reserved.
+        --
+        -- Redistribution and use in source and binary forms, with or without
+        -- modification, are permitted provided that the following conditions
+        -- are met:
+        -- 1. Redistributions of source code must retain the above copyright
+        -- notice, this list of conditions and the following disclaimer.
+        -- 2. Redistributions in binary form must reproduce the above copyright
+        -- notice, this list of conditions and the following disclaimer in the
+        -- documentation and/or other materials provided with the distribution.
+        -- 3. All advertising materials mentioning features or use of this
+        -- software must display the following acknowledgement:
+        -- This product includes software developed by the University of
+        -- California, Berkeley and its contributors.
+        -- 4. Neither the name of the University nor the names of its
+        -- contributors may be used to endorse or promote products derived
+        -- from this software without specific prior written permission.
+        --
+        -- THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS''
+        -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+        -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+        -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR
+        -- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+        -- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+        -- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+        -- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+        -- OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+        -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+        -- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+        -- DAMAGE.
+        --
+        -- NOTE: This VHDL version was generated using the C version of the
+        --         original function by the IEEE VHDL Mathematical Package
+        --         Working Group (CS/JT)
+
+        constant N: INTEGER := 128;
+
+        -- Table of log(Fj) = logF_head[j] + logF_tail[j], for Fj = 1+j/128.
+        -- Used for generation of extend precision logarithms.
+        -- The constant 35184372088832 is 2^45, so the divide is exact.
+        -- It ensures correct reading of logF_head, even for inaccurate
+        -- decimal-to-binary conversion routines. (Everybody gets the
+        -- right answer for INTEGERs less than 2^53.)
+        -- Values for LOG(F) were generated using error < 10^-57 absolute
+        -- with the bc -l package.
+
+        type REAL_VECTOR is array (NATURAL range <>) of REAL;
+
+        constant A1:REAL := 0.08333333333333178827;
+        constant A2:REAL := 0.01250000000377174923;
+        constant A3:REAL := 0.002232139987919447809;
+        constant A4:REAL := 0.0004348877777076145742;
+
+        constant LOGF_HEAD: REAL_VECTOR(0 TO N) := (
+                0.0,
+                0.007782140442060381246,
+                0.015504186535963526694,
+                0.023167059281547608406,
+                0.030771658666765233647,
+                0.038318864302141264488,
+                0.045809536031242714670,
+                0.053244514518837604555,
+                0.060624621816486978786,
+                0.067950661908525944454,
+                0.075223421237524235039,
+                0.082443669210988446138,
+                0.089612158689760690322,
+                0.096729626458454731618,
+                0.103796793681567578460,
+                0.110814366340264314203,
+                0.117783035656430001836,
+                0.124703478501032805070,
+                0.131576357788617315236,
+                0.138402322859292326029,
+                0.145182009844575077295,
+                0.151916042025732167530,
+                0.158605030176659056451,
+                0.165249572895390883786,
+                0.171850256926518341060,
+                0.178407657472689606947,
+                0.184922338493834104156,
+                0.191394852999565046047,
+                0.197825743329758552135,
+                0.204215541428766300668,
+                0.210564769107350002741,
+                0.216873938300523150246,
+                0.223143551314024080056,
+                0.229374101064877322642,
+                0.235566071312860003672,
+                0.241719936886966024758,
+                0.247836163904594286577,
+                0.253915209980732470285,
+                0.259957524436686071567,
+                0.265963548496984003577,
+                0.271933715484010463114,
+                0.277868451003087102435,
+                0.283768173130738432519,
+                0.289633292582948342896,
+                0.295464212893421063199,
+                0.301261330578199704177,
+                0.307025035294827830512,
+                0.312755710004239517729,
+                0.318453731118097493890,
+                0.324119468654316733591,
+                0.329753286372579168528,
+                0.335355541920762334484,
+                0.340926586970454081892,
+                0.346466767346100823488,
+                0.351976423156884266063,
+                0.357455888922231679316,
+                0.362905493689140712376,
+                0.368325561158599157352,
+                0.373716409793814818840,
+                0.379078352934811846353,
+                0.384411698910298582632,
+                0.389716751140440464951,
+                0.394993808240542421117,
+                0.400243164127459749579,
+                0.405465108107819105498,
+                0.410659924985338875558,
+                0.415827895143593195825,
+                0.420969294644237379543,
+                0.426084395310681429691,
+                0.431173464818130014464,
+                0.436236766774527495726,
+                0.441274560805140936281,
+                0.446287102628048160113,
+                0.451274644139630254358,
+                0.456237433481874177232,
+                0.461175715122408291790,
+                0.466089729924533457960,
+                0.470979715219073113985,
+                0.475845904869856894947,
+                0.480688529345570714212,
+                0.485507815781602403149,
+                0.490303988045525329653,
+                0.495077266798034543171,
+                0.499827869556611403822,
+                0.504556010751912253908,
+                0.509261901790523552335,
+                0.513945751101346104405,
+                0.518607764208354637958,
+                0.523248143765158602036,
+                0.527867089620485785417,
+                0.532464798869114019908,
+                0.537041465897345915436,
+                0.541597282432121573947,
+                0.546132437597407260909,
+                0.550647117952394182793,
+                0.555141507540611200965,
+                0.559615787935399566777,
+                0.564070138285387656651,
+                0.568504735352689749561,
+                0.572919753562018740922,
+                0.577315365035246941260,
+                0.581691739635061821900,
+                0.586049045003164792433,
+                0.590387446602107957005,
+                0.594707107746216934174,
+                0.599008189645246602594,
+                0.603290851438941899687,
+                0.607555250224322662688,
+                0.611801541106615331955,
+                0.616029877215623855590,
+                0.620240409751204424537,
+                0.624433288012369303032,
+                0.628608659422752680256,
+                0.632766669570628437213,
+                0.636907462236194987781,
+                0.641031179420679109171,
+                0.645137961373620782978,
+                0.649227946625615004450,
+                0.653301272011958644725,
+                0.657358072709030238911,
+                0.661398482245203922502,
+                0.665422632544505177065,
+                0.669430653942981734871,
+                0.673422675212350441142,
+                0.677398823590920073911,
+                0.681359224807238206267,
+                0.685304003098281100392,
+                0.689233281238557538017,
+                0.693147180560117703862);
+
+        constant LOGF_TAIL: REAL_VECTOR(0 TO N) := (
+                0.0,
+                -0.00000000000000543229938420049,
+                0.00000000000000172745674997061,
+                -0.00000000000001323017818229233,
+                -0.00000000000001154527628289872,
+                -0.00000000000000466529469958300,
+                0.00000000000005148849572685810,
+                -0.00000000000002532168943117445,
+                -0.00000000000005213620639136504,
+                -0.00000000000001819506003016881,
+                0.00000000000006329065958724544,
+                0.00000000000008614512936087814,
+                -0.00000000000007355770219435028,
+                0.00000000000009638067658552277,
+                0.00000000000007598636597194141,
+                0.00000000000002579999128306990,
+                -0.00000000000004654729747598444,
+                -0.00000000000007556920687451336,
+                0.00000000000010195735223708472,
+                -0.00000000000017319034406422306,
+                -0.00000000000007718001336828098,
+                0.00000000000010980754099855238,
+                -0.00000000000002047235780046195,
+                -0.00000000000008372091099235912,
+                0.00000000000014088127937111135,
+                0.00000000000012869017157588257,
+                0.00000000000017788850778198106,
+                0.00000000000006440856150696891,
+                0.00000000000016132822667240822,
+                -0.00000000000007540916511956188,
+                -0.00000000000000036507188831790,
+                0.00000000000009120937249914984,
+                0.00000000000018567570959796010,
+                -0.00000000000003149265065191483,
+                -0.00000000000009309459495196889,
+                0.00000000000017914338601329117,
+                -0.00000000000001302979717330866,
+                0.00000000000023097385217586939,
+                0.00000000000023999540484211737,
+                0.00000000000015393776174455408,
+                -0.00000000000036870428315837678,
+                0.00000000000036920375082080089,
+                -0.00000000000009383417223663699,
+                0.00000000000009433398189512690,
+                0.00000000000041481318704258568,
+                -0.00000000000003792316480209314,
+                0.00000000000008403156304792424,
+                -0.00000000000034262934348285429,
+                0.00000000000043712191957429145,
+                -0.00000000000010475750058776541,
+                -0.00000000000011118671389559323,
+                0.00000000000037549577257259853,
+                0.00000000000013912841212197565,
+                0.00000000000010775743037572640,
+                0.00000000000029391859187648000,
+                -0.00000000000042790509060060774,
+                0.00000000000022774076114039555,
+                0.00000000000010849569622967912,
+                -0.00000000000023073801945705758,
+                0.00000000000015761203773969435,
+                0.00000000000003345710269544082,
+                -0.00000000000041525158063436123,
+                0.00000000000032655698896907146,
+                -0.00000000000044704265010452446,
+                0.00000000000034527647952039772,
+                -0.00000000000007048962392109746,
+                0.00000000000011776978751369214,
+                -0.00000000000010774341461609578,
+                0.00000000000021863343293215910,
+                0.00000000000024132639491333131,
+                0.00000000000039057462209830700,
+                -0.00000000000026570679203560751,
+                0.00000000000037135141919592021,
+                -0.00000000000017166921336082431,
+                -0.00000000000028658285157914353,
+                -0.00000000000023812542263446809,
+                0.00000000000006576659768580062,
+                -0.00000000000028210143846181267,
+                0.00000000000010701931762114254,
+                0.00000000000018119346366441110,
+                0.00000000000009840465278232627,
+                -0.00000000000033149150282752542,
+                -0.00000000000018302857356041668,
+                -0.00000000000016207400156744949,
+                0.00000000000048303314949553201,
+                -0.00000000000071560553172382115,
+                0.00000000000088821239518571855,
+                -0.00000000000030900580513238244,
+                -0.00000000000061076551972851496,
+                0.00000000000035659969663347830,
+                0.00000000000035782396591276383,
+                -0.00000000000046226087001544578,
+                0.00000000000062279762917225156,
+                0.00000000000072838947272065741,
+                0.00000000000026809646615211673,
+                -0.00000000000010960825046059278,
+                0.00000000000002311949383800537,
+                -0.00000000000058469058005299247,
+                -0.00000000000002103748251144494,
+                -0.00000000000023323182945587408,
+                -0.00000000000042333694288141916,
+                -0.00000000000043933937969737844,
+                0.00000000000041341647073835565,
+                0.00000000000006841763641591466,
+                0.00000000000047585534004430641,
+                0.00000000000083679678674757695,
+                -0.00000000000085763734646658640,
+                0.00000000000021913281229340092,
+                -0.00000000000062242842536431148,
+                -0.00000000000010983594325438430,
+                0.00000000000065310431377633651,
+                -0.00000000000047580199021710769,
+                -0.00000000000037854251265457040,
+                0.00000000000040939233218678664,
+                0.00000000000087424383914858291,
+                0.00000000000025218188456842882,
+                -0.00000000000003608131360422557,
+                -0.00000000000050518555924280902,
+                0.00000000000078699403323355317,
+                -0.00000000000067020876961949060,
+                0.00000000000016108575753932458,
+                0.00000000000058527188436251509,
+                -0.00000000000035246757297904791,
+                -0.00000000000018372084495629058,
+                0.00000000000088606689813494916,
+                0.00000000000066486268071468700,
+                0.00000000000063831615170646519,
+                0.00000000000025144230728376072,
+                -0.00000000000017239444525614834);
+
+        variable M, J:INTEGER;
+        variable F1, F2, G, Q, U, U2, V: REAL;
+        variable ZERO: REAL := 0.0;--Made variable so no constant folding occurs
+        variable ONE: REAL := 1.0; --Made variable so no constant folding occurs
+
+        -- double logb(), ldexp();
+
+        variable U1:REAL;
+
+     begin
+
+        -- Check validity of argument
+        if ( X <= 0.0 ) then
+                assert FALSE
+                        report "X <= 0.0 in LOG(X)"
+                        severity ERROR;
+                return(REAL'LOW);
+        end if;
+
+        -- Compute value for special cases
+        if ( X = 1.0 ) then
+                return 0.0;
+        end if;
+
+        if ( X = MATH_E ) then
+                return 1.0;
+        end if;
+
+        -- Argument reduction: 1 <= g < 2; x/2^m = g;
+        -- y = F*(1 + f/F) for |f| <= 2^-8
+
+        M := ILOGB(X);
+        G := LDEXP(X, -M);
+        J := INTEGER(REAL(N)*(G-1.0)); -- C code adds 0.5 for rounding
+        F1 := (1.0/REAL(N)) * REAL(J) + 1.0; --F1*128 is an INTEGER in [128,512]
+        F2 := G - F1;
+
+        -- Approximate expansion for log(1+f2/F1) ~= u + q
+        G := 1.0/(2.0*F1+F2);
+        U := 2.0*F2*G;
+        V := U*U;
+        Q := U*V*(A1 + V*(A2 + V*(A3 + V*A4)));
+
+        -- Case 1: u1 = u rounded to 2^-43 absolute. Since u < 2^-8,
+        --       u1 has at most 35 bits, and F1*u1 is exact, as F1 has < 8 bits.
+        --       It also adds exactly to |m*log2_hi + log_F_head[j] | < 750.
+        --
+        if ( J /= 0 or M /= 0) then
+                U1 := U + 513.0;
+                U1 := U1 - 513.0;
+
+                -- Case 2: |1-x| < 1/256. The m- and j- dependent terms are zero
+                --        u1 = u to 24 bits.
+                --
+        else
+                U1 := U;
+                --TRUNC(U1); --In c this is u1 = (double) (float) (u1)
+        end if;
+
+        U2 := (2.0*(F2 - F1*U1) - U1*F2) * G;
+        -- u1 + u2 = 2f/(2F+f) to extra precision.
+
+        -- log(x) = log(2^m*F1*(1+f2/F1)) =
+        -- (m*log2_hi+LOGF_HEAD(j)+u1) + (m*log2_lo+LOGF_TAIL(j)+q);
+        -- (exact) + (tiny)
+
+        U1 := U1 + REAL(M)*LOGF_HEAD(N) + LOGF_HEAD(J);        -- Exact
+        U2 := (U2 + LOGF_TAIL(J)) + Q;        -- Tiny
+        U2 := U2 + LOGF_TAIL(N)*REAL(M);
+        return (U1 + U2);
+    end LOG;
+
+
+    function LOG2 (X: in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Returns REAL'LOW on error
+    begin
+        -- Check validity of arguments
+        if ( X <= 0.0 )  then
+                assert FALSE
+                        report "X <= 0.0 in LOG2(X)"
+                        severity ERROR;
+                return(REAL'LOW);
+        end if;
+
+        -- Compute value for special cases
+        if ( X = 1.0 ) then
+                return 0.0;
+        end if;
+
+        if ( X = 2.0 ) then
+                return 1.0;
+        end if;
+
+        -- Compute value for general case
+        return ( MATH_LOG2_OF_E*LOG(X) );
+    end LOG2;
+
+
+    function LOG10 (X: in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Returns REAL'LOW on error
+    begin
+        -- Check validity of arguments
+        if ( X <= 0.0 )  then
+                   assert FALSE
+                        report "X <= 0.0 in LOG10(X)"
+                        severity ERROR;
+                   return(REAL'LOW);
+        end if;
+
+        -- Compute value for special cases
+        if ( X = 1.0 ) then
+                return 0.0;
+        end if;
+
+        if ( X = 10.0 ) then
+                return 1.0;
+        end if;
+
+        -- Compute value for general case
+        return ( MATH_LOG10_OF_E*LOG(X) );
+    end LOG10;
+
+
+    function LOG (X: in REAL; BASE: in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Returns REAL'LOW on error
+    begin
+        -- Check validity of arguments
+        if ( X <= 0.0 )  then
+                 assert FALSE
+                        report "X <= 0.0 in LOG(X, BASE)"
+                        severity ERROR;
+                 return(REAL'LOW);
+        end if;
+
+        if ( BASE <= 0.0 or BASE = 1.0 )  then
+                 assert FALSE
+                        report "BASE <= 0.0 or BASE = 1.0 in LOG(X, BASE)"
+                        severity ERROR;
+                 return(REAL'LOW);
+        end if;
+
+        -- Compute value for special cases
+        if ( X = 1.0 ) then
+                return 0.0;
+        end if;
+
+        if ( X = BASE ) then
+                return 1.0;
+        end if;
+
+        -- Compute value for general case
+        return ( LOG(X)/LOG(BASE));
+    end LOG;
+
+
+    function  SIN (X : in REAL ) return REAL is
+        -- Description:
+        --         See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --         a) SIN(-X) = -SIN(X)
+        --         b) SIN(X) = X if ABS(X) < EPS
+        --         c) SIN(X) = X - X**3/3! if EPS < ABS(X) < BASE_EPS
+        --         d) SIN(MATH_PI_OVER_2 - X) = COS(X)
+        --         e) COS(X) = 1.0 - 0.5*X**2 if ABS(X) < EPS
+        --         f) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if
+        --                                         EPS< ABS(X)  MATH_2_PI then
+                TEMP := FLOOR(XLOCAL/MATH_2_PI);
+                XLOCAL := XLOCAL - TEMP*MATH_2_PI;
+        end if;
+
+        if XLOCAL < 0.0 then
+                assert FALSE
+                        report "XLOCAL <= 0.0 after reduction in SIN(X)"
+                        severity ERROR;
+                XLOCAL := -XLOCAL;
+        end if;
+
+        -- Compute value for special cases
+        if XLOCAL = 0.0  or XLOCAL = MATH_2_PI or XLOCAL = MATH_PI  then
+                return 0.0;
+        end if;
+
+        if  XLOCAL = MATH_PI_OVER_2 then
+                if NEGATIVE then
+                        return -1.0;
+                else
+                        return 1.0;
+                end if;
+        end if;
+
+        if  XLOCAL = MATH_3_PI_OVER_2 then
+                if NEGATIVE then
+                        return 1.0;
+                else
+                        return -1.0;
+                end if;
+        end if;
+
+        if XLOCAL < EPS then
+                if NEGATIVE then
+                        return -XLOCAL;
+                else
+                        return XLOCAL;
+                end if;
+        else
+                if XLOCAL < BASE_EPS then
+                        TEMP := XLOCAL - (XLOCAL*XLOCAL*XLOCAL)/6.0;
+                        if NEGATIVE then
+                                return -TEMP;
+                        else
+                                return TEMP;
+                        end if;
+                end if;
+        end if;
+
+        TEMP := MATH_PI - XLOCAL;
+        if ABS(TEMP) < EPS then
+                if NEGATIVE then
+                        return -TEMP;
+                else
+                        return TEMP;
+                end if;
+        else
+                if ABS(TEMP) < BASE_EPS then
+                        TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0;
+                        if NEGATIVE then
+                                return -TEMP;
+                        else
+                                return TEMP;
+                        end if;
+                end if;
+        end if;
+
+        TEMP := MATH_2_PI - XLOCAL;
+        if ABS(TEMP) < EPS then
+                if NEGATIVE then
+                        return TEMP;
+                else
+                        return -TEMP;
+                end if;
+        else
+                if ABS(TEMP) < BASE_EPS then
+                        TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0;
+                        if NEGATIVE then
+                                return TEMP;
+                        else
+                                return -TEMP;
+                        end if;
+                end if;
+        end if;
+
+        TEMP := ABS(MATH_PI_OVER_2 - XLOCAL);
+        if TEMP < EPS then
+                TEMP := 1.0 - TEMP*TEMP*0.5;
+                if NEGATIVE then
+                        return -TEMP;
+                else
+                        return TEMP;
+                end if;
+        else
+                if TEMP < BASE_EPS then
+                        TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0;
+                        if NEGATIVE then
+                                return -TEMP;
+                        else
+                                return TEMP;
+                        end if;
+                end if;
+        end if;
+
+        TEMP := ABS(MATH_3_PI_OVER_2 - XLOCAL);
+        if TEMP < EPS then
+                TEMP := 1.0 - TEMP*TEMP*0.5;
+                if NEGATIVE then
+                        return TEMP;
+                else
+                        return -TEMP;
+                end if;
+        else
+                if TEMP < BASE_EPS then
+                        TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0;
+                        if NEGATIVE then
+                                return TEMP;
+                        else
+                                return -TEMP;
+                        end if;
+                end if;
+        end if;
+
+        -- Compute value for general cases
+        if ((XLOCAL < MATH_PI_OVER_2 ) and (XLOCAL > 0.0)) then
+                 VALUE:=  CORDIC( KC, 0.0, x, 27, ROTATION)(1);
+        end if;
+
+        N := INTEGER ( FLOOR(XLOCAL/MATH_PI_OVER_2));
+        case QUADRANT( N mod 4) is
+           when 0 =>
+                VALUE := CORDIC( KC, 0.0, XLOCAL, 27, ROTATION)(1);
+           when 1 =>
+                VALUE := CORDIC( KC, 0.0, XLOCAL - MATH_PI_OVER_2, 27,
+                                                                ROTATION)(0);
+           when 2 =>
+                VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_PI, 27, ROTATION)(1);
+           when 3 =>
+                VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_3_PI_OVER_2, 27,
+                                                                ROTATION)(0);
+        end case;
+
+        if NEGATIVE then
+                return -VALUE;
+        else
+                return VALUE;
+        end if;
+    end SIN;
+
+
+   function COS (X : in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) COS(-X) = COS(X)
+        --        b) COS(X) = SIN(MATH_PI_OVER_2 - X)
+        --        c) COS(MATH_PI + X)  = -COS(X)
+        --        d) COS(X) = 1.0 - X*X/2.0 if ABS(X) < EPS
+        --        e) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if
+        --                                           EPS< ABS(X)  MATH_2_PI then
+                TEMP := FLOOR(XLOCAL/MATH_2_PI);
+                XLOCAL := XLOCAL - TEMP*MATH_2_PI;
+        end if;
+
+        if XLOCAL < 0.0 then
+                assert FALSE
+                        report "XLOCAL <= 0.0 after reduction in COS(X)"
+                        severity ERROR;
+                XLOCAL := -XLOCAL;
+        end if;
+
+        -- Compute value for special cases
+        if XLOCAL = 0.0  or XLOCAL = MATH_2_PI then
+                return 1.0;
+        end if;
+
+        if  XLOCAL = MATH_PI then
+                return -1.0;
+        end if;
+
+        if XLOCAL = MATH_PI_OVER_2 or XLOCAL = MATH_3_PI_OVER_2 then
+                return 0.0;
+        end if;
+
+        TEMP := ABS(XLOCAL);
+        if ( TEMP < EPS) then
+                return (1.0 - 0.5*TEMP*TEMP);
+        else
+                if (TEMP < BASE_EPS) then
+                        return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0);
+                end if;
+        end if;
+
+        TEMP := ABS(XLOCAL -MATH_2_PI);
+        if ( TEMP < EPS) then
+                return (1.0 - 0.5*TEMP*TEMP);
+        else
+                if (TEMP < BASE_EPS) then
+                        return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0);
+                end if;
+        end if;
+
+        TEMP := ABS (XLOCAL - MATH_PI);
+        if TEMP < EPS then
+                return (-1.0 + 0.5*TEMP*TEMP);
+        else
+                if (TEMP < BASE_EPS) then
+                        return (-1.0 +0.5*TEMP*TEMP - TEMP*TEMP*TEMP*TEMP/24.0);
+                end if;
+        end if;
+
+        -- Compute value for general cases
+        return SIN(MATH_PI_OVER_2 - XLOCAL);
+   end COS;
+
+   function TAN (X : in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) TAN(0.0) = 0.0
+        --        b) TAN(-X) = -TAN(X)
+        --        c) Returns REAL'LOW on error if X < 0.0
+        --        d) Returns REAL'HIGH on error if X > 0.0
+
+        variable NEGATIVE : BOOLEAN := X < 0.0;
+        variable XLOCAL : REAL := ABS(X) ;
+        variable VALUE: REAL;
+        variable TEMP : REAL;
+
+    begin
+        -- Make 0.0 <= XLOCAL <= MATH_2_PI
+        if XLOCAL > MATH_2_PI then
+                TEMP := FLOOR(XLOCAL/MATH_2_PI);
+                XLOCAL := XLOCAL - TEMP*MATH_2_PI;
+        end if;
+
+        if XLOCAL < 0.0 then
+                assert FALSE
+                        report "XLOCAL <= 0.0 after reduction in TAN(X)"
+                        severity ERROR;
+                XLOCAL := -XLOCAL;
+        end if;
+
+        -- Check validity of argument
+        if XLOCAL = MATH_PI_OVER_2 then
+                assert FALSE
+                        report "X is a multiple of MATH_PI_OVER_2 in TAN(X)"
+                        severity ERROR;
+                if NEGATIVE then
+                        return(REAL'LOW);
+                else
+                        return(REAL'HIGH);
+                end if;
+        end if;
+
+        if XLOCAL = MATH_3_PI_OVER_2 then
+                assert FALSE
+                        report "X is a multiple of MATH_3_PI_OVER_2 in TAN(X)"
+                        severity ERROR;
+                if NEGATIVE then
+                        return(REAL'HIGH);
+                else
+                        return(REAL'LOW);
+                end if;
+        end if;
+
+        -- Compute value for special cases
+        if XLOCAL = 0.0 or XLOCAL = MATH_PI then
+                return 0.0;
+        end if;
+
+        -- Compute value for general cases
+        VALUE := SIN(XLOCAL)/COS(XLOCAL);
+        if NEGATIVE then
+                return -VALUE;
+        else
+                return VALUE;
+        end if;
+   end TAN;
+
+   function ARCSIN (X : in REAL ) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) ARCSIN(-X) = -ARCSIN(X)
+        --        b) Returns X on error
+
+        variable NEGATIVE : BOOLEAN := X < 0.0;
+        variable XLOCAL : REAL := ABS(X);
+        variable VALUE : REAL;
+
+   begin
+      -- Check validity of arguments
+      if XLOCAL > 1.0 then
+         assert FALSE
+                report "ABS(X) > 1.0 in ARCSIN(X)"
+                severity ERROR;
+         return X;
+      end if;
+
+      -- Compute value for special cases
+      if XLOCAL = 0.0 then
+         return 0.0;
+      elsif XLOCAL = 1.0 then
+         if NEGATIVE then
+                return -MATH_PI_OVER_2;
+         else
+                return MATH_PI_OVER_2;
+         end if;
+      end if;
+
+      -- Compute value for general cases
+      if XLOCAL < 0.9 then
+         VALUE := ARCTAN(XLOCAL/(SQRT(1.0 - XLOCAL*XLOCAL)));
+      else
+         VALUE := MATH_PI_OVER_2 - ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL);
+      end if;
+
+      if NEGATIVE then
+         VALUE := -VALUE;
+      end if;
+
+      return VALUE;
+   end ARCSIN;
+
+   function ARCCOS (X : in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) ARCCOS(-X) = MATH_PI - ARCCOS(X)
+        --        b) Returns X on error
+
+        variable NEGATIVE : BOOLEAN := X < 0.0;
+        variable XLOCAL : REAL := ABS(X);
+        variable VALUE : REAL;
+
+   begin
+      -- Check validity of argument
+      if XLOCAL > 1.0 then
+         assert FALSE
+                report "ABS(X) > 1.0 in ARCCOS(X)"
+                severity ERROR;
+         return X;
+      end if;
+
+      -- Compute value for special cases
+      if X = 1.0 then
+         return 0.0;
+      elsif X = 0.0 then
+         return MATH_PI_OVER_2;
+      elsif X = -1.0 then
+         return MATH_PI;
+      end if;
+
+      -- Compute value for general cases
+      if XLOCAL > 0.9 then
+         VALUE := ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL);
+      else
+         VALUE := MATH_PI_OVER_2 - ARCTAN(XLOCAL/SQRT(1.0 - XLOCAL*XLOCAL));
+      end if;
+
+
+      if NEGATIVE then
+         VALUE := MATH_PI - VALUE;
+      end if;
+
+      return VALUE;
+   end ARCCOS;
+
+
+   function ARCTAN (Y : in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) ARCTAN(-Y) = -ARCTAN(Y)
+        --        b) ARCTAN(Y) = -ARCTAN(1.0/Y) + MATH_PI_OVER_2 for |Y| > 1.0
+        --        c) ARCTAN(Y) = Y for |Y| < EPS
+
+        constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;
+
+        variable NEGATIVE : BOOLEAN := Y < 0.0;
+        variable RECIPROCAL : BOOLEAN;
+        variable YLOCAL : REAL := ABS(Y);
+        variable VALUE : REAL;
+
+   begin
+      -- Make argument |Y| <=1.0
+      if YLOCAL > 1.0 then
+                YLOCAL := 1.0/YLOCAL;
+                RECIPROCAL := TRUE;
+      else
+                RECIPROCAL := FALSE;
+      end if;
+
+      -- Compute value for special cases
+      if YLOCAL = 0.0 then
+         if RECIPROCAL then
+                if NEGATIVE then
+                        return (-MATH_PI_OVER_2);
+                else
+                        return (MATH_PI_OVER_2);
+                end if;
+         else
+                return 0.0;
+         end if;
+      end if;
+
+      if YLOCAL < EPS then
+         if NEGATIVE then
+                if RECIPROCAL then
+                        return (-MATH_PI_OVER_2 + YLOCAL);
+                else
+                        return -YLOCAL;
+                end if;
+         else
+                if RECIPROCAL then
+                        return (MATH_PI_OVER_2 - YLOCAL);
+                else
+                        return YLOCAL;
+                end if;
+         end if;
+      end if;
+
+      -- Compute value for general cases
+      VALUE :=  CORDIC( 1.0, YLOCAL, 0.0, 27, VECTORING )(2);
+
+      if RECIPROCAL then
+         VALUE := MATH_PI_OVER_2 - VALUE;
+      end if;
+
+      if NEGATIVE then
+        VALUE := -VALUE;
+      end if;
+
+      return VALUE;
+   end ARCTAN;
+
+
+   function ARCTAN (Y : in REAL; X : in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --         a) Returns 0.0 on error
+
+        variable YLOCAL : REAL;
+        variable VALUE : REAL;
+   begin
+
+     -- Check validity of arguments
+     if (Y = 0.0 and X = 0.0 ) then
+           assert FALSE report
+                "ARCTAN(0.0, 0.0) is undetermined"
+                severity ERROR;
+           return 0.0;
+     end if;
+
+     -- Compute value for special cases
+     if Y = 0.0 then
+        if X > 0.0 then
+           return 0.0;
+        else
+           return MATH_PI;
+        end if;
+     end if;
+
+     if X = 0.0 then
+        if Y > 0.0 then
+           return MATH_PI_OVER_2;
+        else
+           return -MATH_PI_OVER_2;
+        end if;
+     end if;
+
+
+     -- Compute value for general cases
+     YLOCAL := ABS(Y/X);
+
+     VALUE := ARCTAN(YLOCAL);
+
+     if X < 0.0 then
+         VALUE := MATH_PI - VALUE;
+     end if;
+
+     if Y < 0.0 then
+         VALUE := -VALUE;
+     end if;
+
+     return VALUE;
+   end ARCTAN;
+
+
+    function SINH (X : in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Returns (EXP(X) - EXP(-X))/2.0
+        --        b) SINH(-X) = SINH(X)
+
+        variable NEGATIVE : BOOLEAN := X < 0.0;
+        variable XLOCAL : REAL := ABS(X);
+        variable TEMP : REAL;
+        variable VALUE : REAL;
+
+    begin
+        -- Compute value for special cases
+        if XLOCAL = 0.0 then
+                return 0.0;
+        end if;
+
+        -- Compute value for general cases
+        TEMP := EXP(XLOCAL);
+        VALUE := (TEMP - 1.0/TEMP)*0.5;
+
+         if NEGATIVE then
+                VALUE := -VALUE;
+        end if;
+
+        return VALUE;
+    end SINH;
+
+    function  COSH (X : in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Returns (EXP(X) + EXP(-X))/2.0
+        --        b) COSH(-X) = COSH(X)
+
+        variable XLOCAL : REAL := ABS(X);
+        variable TEMP : REAL;
+        variable VALUE : REAL;
+    begin
+        -- Compute value for special cases
+        if XLOCAL = 0.0 then
+                return 1.0;
+        end if;
+
+
+        -- Compute value for general cases
+        TEMP := EXP(XLOCAL);
+        VALUE := (TEMP + 1.0/TEMP)*0.5;
+
+        return VALUE;
+    end COSH;
+
+    function  TANH (X : in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Returns (EXP(X) - EXP(-X))/(EXP(X) + EXP(-X))
+        --        b) TANH(-X) = -TANH(X)
+
+        variable NEGATIVE : BOOLEAN := X < 0.0;
+        variable XLOCAL : REAL := ABS(X);
+        variable TEMP : REAL;
+        variable VALUE : REAL;
+
+    begin
+        -- Compute value for special cases
+        if XLOCAL = 0.0 then
+                return 0.0;
+        end if;
+
+        -- Compute value for general cases
+        TEMP := EXP(XLOCAL);
+        VALUE := (TEMP - 1.0/TEMP)/(TEMP + 1.0/TEMP);
+
+        if NEGATIVE then
+            return -VALUE;
+        else
+            return VALUE;
+        end if;
+    end TANH;
+
+    function ARCSINH (X : in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Returns LOG( X + SQRT( X*X + 1.0))
+
+    begin
+        -- Compute value for special cases
+        if X = 0.0 then
+                return 0.0;
+        end if;
+
+        -- Compute value for general cases
+        return ( LOG( X + SQRT( X*X + 1.0)) );
+    end ARCSINH;
+
+
+
+   function ARCCOSH (X : in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Returns LOG( X + SQRT( X*X - 1.0));   X >= 1.0
+        --        b) Returns X on error
+
+    begin
+        -- Check validity of arguments
+        if X < 1.0 then
+                 assert FALSE
+                        report "X < 1.0 in ARCCOSH(X)"
+                        severity ERROR;
+                 return X;
+        end if;
+
+        -- Compute value for special cases
+        if X = 1.0 then
+                return 0.0;
+        end if;
+
+        -- Compute value for general cases
+        return ( LOG( X + SQRT( X*X - 1.0)));
+    end ARCCOSH;
+
+    function ARCTANH (X : in REAL) return REAL is
+        -- Description:
+        --        See function declaration in IEEE Std 1076.2-1996
+        -- Notes:
+        --        a) Returns (LOG( (1.0 + X)/(1.0 - X)))/2.0 ; | X | < 1.0
+        --        b) Returns X on error
+    begin
+        -- Check validity of arguments
+        if ABS(X) >= 1.0 then
+                assert FALSE
+                        report "ABS(X) >= 1.0 in ARCTANH(X)"
+                        severity ERROR;
+                return X;
+        end if;
+
+        -- Compute value for special cases
+        if X = 0.0 then
+                return 0.0;
+        end if;
+
+        -- Compute value for general cases
+        return( 0.5*LOG( (1.0+X)/(1.0-X) ) );
+    end ARCTANH;
+
+end  MATH_REAL;
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/generate_core.tcl b/CPLD/LCMXO2/LCMXO2-640HC/generate_core.tcl
new file mode 100644
index 0000000..264a94e
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/generate_core.tcl
@@ -0,0 +1,100 @@
+#!/usr/local/bin/wish
+
+proc GetPlatform {} {
+	global tcl_platform
+
+	set cpu  $tcl_platform(machine)
+
+	switch $cpu {
+		intel -
+		i*86* {
+			set cpu ix86
+		}
+		x86_64 {
+			if {$tcl_platform(wordSize) == 4} {
+				set cpu ix86
+			}
+		}
+	}
+
+	switch $tcl_platform(platform) {
+		windows {
+			if {$cpu == "amd64"} {
+				# Do not check wordSize, win32-x64 is an IL32P64 platform.
+				set cpu x86_64
+			}
+			if {$cpu == "x86_64"} {
+				return "nt64"
+			} else {
+				return "nt"
+			}
+		}
+		unix {
+			if {$tcl_platform(os) == "Linux"}  {
+				if {$cpu == "x86_64"} {
+					return "lin64"
+				} else {
+					return "lin"
+				}
+			} else  {
+				return "sol"
+			}
+		}
+	}
+	return "nt"
+}
+
+proc GetCmdLine {lpcfile} {
+	global Para
+
+	if [catch {open $lpcfile r} fileid] {
+		puts "Cannot open $para_file file!"
+		exit -1
+	}
+
+	seek $fileid 0 start
+	set default_match 0
+	while {[gets $fileid line] >= 0} {
+		if {[string first "\[Command\]" $line] == 0} {
+			set default_match 1
+			continue
+		}
+		if {[string first "\[" $line] == 0} {
+			set default_match 0
+		}
+		if {$default_match == 1} {
+			if [regexp {([^=]*)=(.*)} $line match parameter value] {
+				if [regexp {([ |\t]*;)} $parameter match] {continue}
+				if [regexp {(.*)[ |\t]*;} $value match temp] {
+					set Para($parameter) $temp
+				} else {
+					set Para($parameter) $value
+				}
+			}
+		}
+	}
+	set default_match 0
+	close $fileid
+
+	return $Para(cmd_line)
+}
+
+set platformpath [GetPlatform]
+set Para(sbp_path) [file dirname [info script]]
+set Para(install_dir) $env(TOOLRTF)
+set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
+
+set scuba "$Para(FPGAPath)/scuba"
+set modulename "EFB"
+set lang "verilog"
+set lpcfile "$Para(sbp_path)/$modulename.lpc"
+set arch "xo2c00"
+set cmd_line [GetCmdLine $lpcfile]
+set fdcfile "$Para(sbp_path)/$modulename.fdc"
+if {[file exists $fdcfile] == 0} {
+	append scuba " " $cmd_line
+} else {
+	append scuba " " $cmd_line " " -fdc " " \"$fdcfile\"
+}
+set Para(result) [catch {eval exec "$scuba"} msg]
+#puts $msg
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/generate_ngd.tcl b/CPLD/LCMXO2/LCMXO2-640HC/generate_ngd.tcl
new file mode 100644
index 0000000..ffa641e
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/generate_ngd.tcl
@@ -0,0 +1,124 @@
+#!/usr/local/bin/wish
+
+proc GetPlatform {} {
+	global tcl_platform
+
+	set cpu  $tcl_platform(machine)
+
+	switch $cpu {
+		intel -
+		i*86* {
+			set cpu ix86
+		}
+		x86_64 {
+			if {$tcl_platform(wordSize) == 4} {
+				set cpu ix86
+			}
+		}
+	}
+
+	switch $tcl_platform(platform) {
+		windows {
+			if {$cpu == "amd64"} {
+				# Do not check wordSize, win32-x64 is an IL32P64 platform.
+				set cpu x86_64
+			}
+			if {$cpu == "x86_64"} {
+				return "nt64"
+			} else {
+				return "nt"
+			}
+		}
+		unix {
+			if {$tcl_platform(os) == "Linux"}  {
+				if {$cpu == "x86_64"} {
+					return "lin64"
+				} else {
+					return "lin"
+				}
+			} else  {
+				return "sol"
+			}
+		}
+	}
+	return "nt"
+}
+
+set platformpath [GetPlatform]
+set Para(sbp_path) [file dirname [info script]]
+set Para(install_dir) $env(TOOLRTF)
+set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
+set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]"
+
+set Para(ModuleName) "EFB"
+set Para(Module) "EFB"
+set Para(libname) machxo2
+set Para(arch_name) xo2c00
+set Para(PartType) "LCMXO2-640HC"
+
+set Para(tech_syn) machxo2
+set Para(tech_cae) machxo2
+set Para(Package) "TQFP100"
+set Para(SpeedGrade) "4"
+set Para(FMax) "100"
+set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc"
+
+#create LSE project file(*.synproj)
+proc CreateSynprojFile {} {
+	global Para
+
+	if [catch {open $Para(ModuleName).synproj w} synprojFile] {
+		puts "Cannot create LSE project file $Para(ModuleName).synproj."
+		exit -1
+	} else {
+		puts $synprojFile "-a \"$Para(tech_syn)\"
+-d $Para(PartType)
+-t $Para(Package)
+-s $Para(SpeedGrade)
+-frequency 200
+-optimization_goal Balanced
+-bram_utilization 100
+-ramstyle auto
+-romstyle auto
+-use_carry_chain 1
+-carry_chain_length 0
+-force_gsr auto
+-resource_sharing 1
+-propagate_constants 1
+-remove_duplicate_regs 1
+-mux_style Auto
+-max_fanout 1000
+-fsm_encoding_style Auto
+-twr_paths 3
+-fix_gated_clocks 1
+-use_io_insertion 0
+-resolve_mixed_drivers 0
+-use_io_reg 1
+
+-lpf 1
+-p $Para(sbp_path)
+-ver \"$Para(install_dir)/cae_library/synthesis/verilog/$Para(tech_cae).v\"
+\"$Para(install_dir)/cae_library/synthesis/verilog/pmi_def.v\"
+\"$Para(sbp_path)/$Para(ModuleName).v\"
+-top $Para(ModuleName)
+-ngo \"$Para(sbp_path)/$Para(ModuleName).ngo\"
+		"
+		close $synprojFile
+	}
+}
+
+#LSE
+CreateSynprojFile
+set ldcfile "$Para(sbp_path)/$Para(ModuleName).ldc"
+set synthesis "$Para(FPGAPath)/synthesis"
+if {[file exists $ldcfile] == 0} {
+	set Para(result) [catch {eval exec $synthesis -f \"$Para(ModuleName).synproj\" -gui} msg]
+} else {
+	set Para(result) [catch {eval exec $synthesis -f \"$Para(ModuleName).synproj\" -sdc \"$ldcfile\" -gui} msg]
+}
+#puts $msg
+
+#ngdbuild
+set ngdbuild "$Para(FPGAPath)/ngdbuild"
+set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg]
+#puts $msg
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/.build_status b/CPLD/LCMXO2/LCMXO2-640HC/impl1/.build_status
new file mode 100644
index 0000000..d4ddfec
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/.build_status
@@ -0,0 +1,46 @@
+
+
+    
+        
+            
+            
+            
+            
+            
+        
+        
+            
+            
+            
+            
+        
+        
+            
+            
+            
+        
+        
+            
+            
+        
+        
+            
+            
+            
+            
+            
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+    
+
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/.vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb b/CPLD/LCMXO2/LCMXO2-640HC/impl1/.vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb
new file mode 100644
index 0000000000000000000000000000000000000000..3d236f208ca40ba5260380a927880289747aeafe
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diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/.vdbs/RAM2GS_rtl.vdb b/CPLD/LCMXO2/LCMXO2-640HC/impl1/.vdbs/RAM2GS_rtl.vdb
new file mode 100644
index 0000000000000000000000000000000000000000..4d0f7d5e344627d3e12626b447fa0be6c46e46b1
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literal 0
HcmV?d00001

diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/.vdbs/dbStat.txt b/CPLD/LCMXO2/LCMXO2-640HC/impl1/.vdbs/dbStat.txt
new file mode 100644
index 0000000..0a575a4
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/.vdbs/dbStat.txt
@@ -0,0 +1 @@
+RAM2GS_rtl.vdb
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/IBIS/RAM2GS_LCMXO2_640HC~.ibs b/CPLD/LCMXO2/LCMXO2-640HC/impl1/IBIS/RAM2GS_LCMXO2_640HC~.ibs
new file mode 100644
index 0000000..4b06874
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/IBIS/RAM2GS_LCMXO2_640HC~.ibs
@@ -0,0 +1,2837 @@
+|************************************************************************
+| IBIS Models Generator: Lattice Diamond (64-bit) 3.12.0.240.2
+| Generate date: Tue Aug 17 06:21:03 2021
+|************************************************************************
+| IBIS File LibisMaker.ibs
+| LibisGen v2.0.1.0, 02/25/2008, Lattice Semiconductor Corporation
+| Modified by LibisMaker v2.0.1.0, 02/25/2008, Lattice Semiconductor
+| North Carolina State University, ERL, 2006
+|************************************************************************
+[IBIS ver]       3.2
+[File Name]     RAM2GS_LCMXO2_640HC~.ibs
+[File Rev]       3.5
+[Date]           Thu Sep 10 07:33:23 PDT 2020
+[Source]         Lattice Semiconductor cs200fl Process
+                 LCMXO2-640HC     FINAL
+                 Lattice Semiconductor has worked hard to ensure the
+                 models below are accurate and complete.  However, the
+                 data below was generated using simulation of the
+                 input/output model files for the silicon.  Therefore,
+                 the data below is for reference and initial design
+                 purposes only.
+|
+                 Lattice Semiconductor grants permission to use this
+                 data for use in printed circuit design using this
+                 Lattice programmable logic device.  Other use of this
+                 code, including the selling or duplication of any
+                 portion is strictly prohibited.
+|
+|                NAMING CONVENTION
+|
+        The IBIS [Model] header is limited by the specification to a
+        total of characters.  With such a set of characters available
+        for naming models it becomes important to attempt to
+        meaningfully encode the IO standards so they fit within the
+        twenty character limit.  It would seem that twenty characters
+        would provide room enough for describing IO's.  However, the
+        PLD IO structure continues to grow more and more complex.  The
+        complexity is making the twenty characters insuffiently
+        descriptive.  In order to overcome this issue the naming
+        convention described below is implemented to resolve the issue.
+|
+The twenty character space is managed as follows:
+                 bbbvvvsdddprugtcoixx
+|
+                 b = standard
+                 v = voltage (x.xx V)
+                 s = slew code
+                 d = drive (xx.x ma)
+                 p = pullup code
+                 r = series resistance  or bank_vccio code
+                 u = terminate to vcc code
+                 g = terminate to gnd code
+                 t = terminate to vtt code
+                 c = common mode termination mode
+                 o = diff resistor code
+                 i = diff resistor current code
+                 x = reserved
+|
+|
+                 standard
+|
+                 lvcmos                   lvc
+                 lvcmosd                  lvd
+                 lvcmosr                  lvr             
+                 lvds25e                  lve
+                 lvttl                    lvt
+                 lvttld                   ltd
+                 pci                      pci
+                 sstl_I                   ss1
+                 sstl_II                  ss2
+                 sstld_I                  s1d
+                 sstld_II                 s2d
+                 hstl_i                   hs1
+                 hstl_ii                  hs2
+                 hstld_i                  h1d
+                 hstld_ii                 h2d
+                 lvds25                   lvs
+                 blvds25                  blv
+                 blvds25e                 blv
+                 mlvds25                  mlv
+                 mlvds25e                 mlv
+                 lvpecl33                 lvp
+                 lvpecl33e                lvp
+                 rsds25                   rsd
+                 rsds25e                  rse
+                 mipi                     mip
+                 mipi_lp                  mip
+                 vref1                    vr1
+                 vref2                    vr2
+                 ref_res                  rer
+|
+|
+                 slew
+                 na                       a
+                 fast                     f
+                 slow                     s
+|
+                 pullmode
+                 off                      a
+                 pullup                   b
+                 pulldown                 c
+                 bushold                  d
+                 clamp                    e
+                 up_clamp                 f
+                 down_clamp               g
+                 keeper_clamp             h
+|
+                 impedance or Bank_vccio
+                 off                      a
+                 25                       b
+                 33                       c
+                 50                       d
+                 100                      e
+                 3.3                      f
+                 2.5                      g
+                 1.8                      h
+                 1.5                      i
+                 1.2                      j
+|
+                 termVCC
+                 off                      a
+                 50                       b
+                 100                      c
+                 120                      d
+|
+                 termGND
+                 off                      a
+                 50                       b
+                 100                      c
+                 120                      d
+|
+                 termVTT
+                 off                      a
+                 60                       b
+                 75                       c
+                 120                      d
+                 150                      e
+                 210                      f
+|
+                 VCMT
+                 off                      a
+                 VCMT                     b
+                 VTT                      c
+                 DDR-2                    d
+|
+                 differential resistor
+                 off                      a
+                 100                      b
+|
+                 diff drive
+                 NA                       a
+                 2.0                      b
+                 3.5                      c
+                 1.25                     f
+                 2.5                      g
+|
+                 Reserved                 IO type
+                 in                       input only
+                 ou                       output
+                 io                       I/O
+                 od                       Open drain
+                 on                       Inverting differential I/O
+                                          (signal name only)
+                 op                       Non-Inverting differential I/O
+                                          (signal name only)
+|
+                 Lattice Semiconductor Corporation
+                 5555 NE Moore Court
+                 Hillsboro, OR 97214
+                 U.S.A
+|
+                 TEL: 1-800-Lattice (USA and Canada)
+                      408-826-6000 (other locations)
+|
+                 web: http://www.latticesemi.com/
+                 email: techsupport@latticesemi.com
+|
+|
+|
+[Disclaimer]     This IBIS source code is intended as a design reference
+   which illustrates how the Lattice Semiconductor device operates.
+   It is the user's responsibility to verify their design for
+   consistency and functionality through the use of formal
+   verification methods.  Lattice Semiconductor provides no warranty
+   regarding the use or functionality of this data.
+|
+[Copyright]      Copyright 2007 by Lattice Semiconductor Corporation
+|
+|  
+|************************************************************************
+|                       Component XO2
+|************************************************************************
+|                                                               
+[Component]       XO2                                           
+[Manufacturer]    Lattice Semiconductor Corp.                   
+[Package]
+|TQFP100
+| variable            typ              min              max     
+R_pkg                150.5m           124.0m           187.0m
+L_pkg                6.27nH           5.50nH           7.16nH
+C_pkg                0.95pF           0.87pF           1.07pF
+|
+[Pin] signal_name           model_name           R_pin     L_pin     C_pin
+10            CROW[0]              lvt330axxxefaaaaaain
+16            CROW[1]              lvt330axxxefaaaaaain
+3             Din[0]               lvt330axxxefaaaaaain
+96            Din[1]               lvt330axxxefaaaaaain
+88            Din[2]               lvt330axxxefaaaaaain
+97            Din[3]               lvt330axxxefaaaaaain
+99            Din[4]               lvt330axxxefaaaaaain
+98            Din[5]               lvt330axxxefaaaaaain
+2             Din[6]               lvt330axxxefaaaaaain
+1             Din[7]               lvt330axxxefaaaaaain
+76            Dout[0]              lvt330s040aaaaaaaaou
+86            Dout[1]              lvt330s040aaaaaaaaou
+87            Dout[2]              lvt330s040aaaaaaaaou
+85            Dout[3]              lvt330s040aaaaaaaaou
+83            Dout[4]              lvt330s040aaaaaaaaou
+84            Dout[5]              lvt330s040aaaaaaaaou
+78            Dout[6]              lvt330s040aaaaaaaaou
+82            Dout[7]              lvt330s040aaaaaaaaou
+34            LED                  lvt330s160aaaaaaaaou
+14            MAin[0]              lvt330axxxefaaaaaain
+12            MAin[1]              lvt330axxxefaaaaaain
+13            MAin[2]              lvt330axxxefaaaaaain
+21            MAin[3]              lvt330axxxefaaaaaain
+20            MAin[4]              lvt330axxxefaaaaaain
+19            MAin[5]              lvt330axxxefaaaaaain
+24            MAin[6]              lvt330axxxefaaaaaain
+18            MAin[7]              lvt330axxxefaaaaaain
+25            MAin[8]              lvt330axxxefaaaaaain
+32            MAin[9]              lvt330axxxefaaaaaain
+8             PHI2                 lvt330axxxefaaaaaain
+66            RA[0]                lvt330s040aaaaaaaaou
+64            RA[10]               lvt330s040aaaaaaaaou
+59            RA[11]               lvt330s040aaaaaaaaou
+67            RA[1]                lvt330s040aaaaaaaaou
+69            RA[2]                lvt330s040aaaaaaaaou
+71            RA[3]                lvt330s040aaaaaaaaou
+74            RA[4]                lvt330s040aaaaaaaaou
+70            RA[5]                lvt330s040aaaaaaaaou
+68            RA[6]                lvt330s040aaaaaaaaou
+75            RA[7]                lvt330s040aaaaaaaaou
+65            RA[8]                lvt330s040aaaaaaaaou
+62            RA[9]                lvt330s040aaaaaaaaou
+58            RBA[0]               lvt330s040aaaaaaaaou
+60            RBA[1]               lvt330s040aaaaaaaaou
+53            RCKE                 lvt330s040aaaaaaaaou
+63            RCLK                 lvt330axxxefaaaaaain
+51            RDQMH                lvt330s040aaaaaaaaou
+48            RDQML                lvt330s040aaaaaaaaou
+36            RD[0]                lvt330s040haaaaaaaio
+37            RD[1]                lvt330s040haaaaaaaio
+38            RD[2]                lvt330s040haaaaaaaio
+39            RD[3]                lvt330s040haaaaaaaio
+40            RD[4]                lvt330s040haaaaaaaio
+41            RD[5]                lvt330s040haaaaaaaio
+42            RD[6]                lvt330s040haaaaaaaio
+43            RD[7]                lvt330s040haaaaaaaio
+9             nCCAS                lvt330axxxefaaaaaain
+17            nCRAS                lvt330axxxefaaaaaain
+15            nFWE                 lvt330axxxefaaaaaain
+52            nRCAS                lvt330s040aaaaaaaaou
+57            nRCS                 lvt330s040aaaaaaaaou
+54            nRRAS                lvt330s040aaaaaaaaou
+49            nRWE                 lvt330s040aaaaaaaaou
+|************************************************************************
+[Model]           lvt330axxxefaaaaaain
+Model_type        Input
+Polarity          Non-Inverting
+Enable            Active-Low
+Vinl =            0.8000V
+Vinh =            2.0000V
+C_comp            4.2000pF          3.8000pF             7.5000pF
+|  
+|  
+[Temperature Range]     25.0000           0.1050k              -40.0000
+[Voltage Range]         3.3000V           3.1400V              3.4700V
+[GND_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    -0.9553A          -0.9303A             -0.978A
+  -3.25    -0.9307A          -0.9059A             -0.9534A
+  -3.20    -0.9062A          -0.8815A             -0.9287A
+  -3.15    -0.8816A          -0.8571A             -0.9041A
+  -3.10    -0.8571A          -0.8328A             -0.8794A
+  -3.05    -0.8326A          -0.8084A             -0.8548A
+  -3.00    -0.8081A          -0.7841A             -0.8302A
+  -2.95    -0.7837A          -0.7598A             -0.8056A
+  -2.90    -0.7592A          -0.7356A             -0.781A
+  -2.85    -0.7348A          -0.7113A             -0.7565A
+  -2.80    -0.7104A          -0.6872A             -0.7319A
+  -2.75    -0.686A           -0.663A              -0.7074A
+  -2.70    -0.6617A          -0.6389A             -0.6829A
+  -2.65    -0.6374A          -0.6149A             -0.6584A
+  -2.60    -0.6131A          -0.5909A             -0.634A
+  -2.55    -0.5889A          -0.5669A             -0.6096A
+  -2.50    -0.5647A          -0.5431A             -0.5852A
+  -2.45    -0.5406A          -0.5193A             -0.5609A
+  -2.40    -0.5166A          -0.4956A             -0.5366A
+  -2.35    -0.4926A          -0.472A              -0.5124A
+  -2.30    -0.4687A          -0.4485A             -0.4882A
+  -2.25    -0.4449A          -0.4251A             -0.4641A
+  -2.20    -0.4211A          -0.4019A             -0.44A
+  -2.15    -0.3976A          -0.3789A             -0.4161A
+  -2.10    -0.3741A          -0.3562A             -0.3923A
+  -2.05    -0.3509A          -0.3337A             -0.3686A
+  -2.00    -0.3279A          -0.3116A             -0.3451A
+  -1.95    -0.3052A          -0.2899A             -0.3218A
+  -1.90    -0.283A           -0.2689A             -0.2988A
+  -1.85    -0.2612A          -0.2486A             -0.2762A
+  -1.80    -0.2402A          -0.2294A             -0.2543A
+  -1.75    -0.2204A          -0.2116A             -0.2332A
+  -1.70    -0.202A           -0.1954A             -0.2135A
+  -1.65    -0.1857A          -0.181A              -0.1959A
+  -1.60    -0.1717A          -0.1682A             -0.181A
+  -1.55    -0.1594A          -0.1563A             -0.1685A
+  -1.50    -0.1481A          -0.1452A             -0.1571A
+  -1.45    -0.1372A          -0.1343A             -0.1462A
+  -1.40    -0.1266A          -0.1237A             -0.1355A
+  -1.35    -0.1162A          -0.1132A             -0.125A
+  -1.30    -0.106A           -0.1029A             -0.1146A
+  -1.25    -95.9599mA        -92.8329mA           -0.1046A
+  -1.20    -86.1849mA        -82.9339mA           -94.9069mA
+  -1.15    -76.7349mA        -73.2869mA           -85.7379mA
+  -1.10    -67.7089mA        -63.9519mA           -77.2789mA
+  -1.05    -59.2439mA        -55.0099mA           -69.7479mA
+  -1.00    -51.5159mA        -46.5729mA           -63.2139mA
+  -0.95    -44.7119mA        -38.7979mA           -57.3089mA
+  -0.90    -38.8659mA        -31.8819mA           -51.2599mA
+  -0.85    -33.5299mA        -25.9129mA           -44.7209mA
+  -0.80    -28.2499mA        -20.5839mA           -37.9699mA
+  -0.75    -23.0669mA        -15.7839mA           -31.2789mA
+  -0.70    -18.0989mA        -11.6329mA           -24.8089mA
+  -0.65    -13.4569mA        -8.1389mA            -18.6889mA
+  -0.60    -9.2667mA         -5.2646mA            -13.0589mA
+  -0.55    -5.6915mA         -3.0244mA            -8.1194mA
+  -0.50    -2.937mA          -1.4709mA            -4.1747mA
+  -0.45    -1.1814mA         -0.5866mA            -1.592mA
+  -0.40    -0.3589mA         -0.1961mA            -0.4238mA
+  -0.35    -88.3674uA        -58.3595uA           -88.5118uA
+  -0.30    -18.8304uA        -15.9765uA           -16.7268uA
+  -0.25    -3.5316uA         -4.0546uA            -3.0027uA
+  -0.20    -0.6045uA         -0.9665uA            -0.4941uA
+  -0.15    -99.742nA         -0.2204uA            -76.537nA
+  -0.10    -17.537nA         -48.631nA            -14.0860nA
+  -0.05    -3.547nA          -9.5380nA            -3.817nA
+  0.00    0.0A              0.0A                 0.0A
+  6.60    0.0A              0.0A                 0.0A
+|  
+[POWER_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.25    0.1216A           0.1237A              0.1238A
+  -3.15    0.1196A           0.1223A              0.1209A
+  -3.05    0.1173A           0.1206A              0.1178A
+  -2.95    0.1149A           0.1187A              0.1145A
+  -2.85    0.1124A           0.1167A              0.1111A
+  -2.75    0.1096A           0.1144A              0.1076A
+  -2.65    0.1067A           0.1119A              0.1038A
+  -2.55    0.1036A           0.1092A              99.9050mA
+  -2.45    0.1003A           0.1063A              95.7580mA
+  -2.35    96.7690mA         0.1032A              91.3580mA
+  -2.25    92.9860mA         99.8100mA            86.6530mA
+  -2.15    88.9230mA         96.2310mA            81.5730mA
+  -2.05    84.5480mA         92.4190mA            76.0140mA
+  -1.95    79.8300mA         88.3720mA            69.8490mA
+  -1.85    74.7460mA         84.0930mA            62.9770mA
+  -1.75    69.2870mA         79.5850mA            55.3980mA
+  -1.65    63.4650mA         74.8610mA            47.2410mA
+  -1.55    57.3080mA         69.9360mA            38.7130mA
+  -1.45    50.8520mA         64.8290mA            30.0630mA
+  -1.35    44.1410mA         59.5630mA            21.7860mA
+  -1.25    37.2260mA         54.1610mA            15.4630mA
+  -1.15    30.1740mA         48.6420mA            11.3590mA
+  -1.05    23.0900mA         43.0210mA            6.9249mA
+  -0.95    16.2170mA         37.3010mA            3.1428mA
+  -0.85    10.2220mA         31.4860mA            0.8130mA
+  -0.75    6.0667mA          25.5900mA            0.1206mA
+  -0.65    3.1215mA          19.6580mA            19.6640uA
+  -0.55    1.0958mA          13.7970mA            3.9127uA
+  -0.45    0.2189mA          8.2788mA             1.9769uA
+  -0.35    37.5650uA         3.8148mA             1.5352uA
+  -0.25    5.9156uA          1.3265mA             1.2603uA
+  -0.15    0.9342uA          0.3367mA             1.0262uA
+  -0.05    0.2497uA          63.0770uA            0.8243uA
+  0.00    0.1905uA          26.3140uA            0.7347uA
+  0.05    0.1661uA          10.7330uA            0.6522uA
+  0.15    0.1377uA          1.6689uA             0.5077uA
+  0.25    0.1149uA          0.2675uA             0.3882uA
+  0.35    95.5840nA         94.4800nA            0.2911uA
+  0.45    79.2300nA         72.9410nA            0.2139uA
+  0.55    65.5240nA         63.7780nA            0.1539uA
+  0.65    54.1200nA         56.2440nA            0.1084uA
+  0.75    44.6720nA         49.6060nA            74.7270nA
+  0.85    36.8450nA         43.7060nA            50.5340nA
+  0.95    30.3210nA         38.4180nA            33.5490nA
+  1.05    24.8050nA         33.6240nA            21.8000nA
+  1.15    20.0360nA         29.2180nA            13.6290nA
+  1.25    15.7920nA         25.1030nA            7.7259nA
+  1.35    11.8920nA         21.1950nA            3.1291nA
+  1.45    8.2001nA          17.4270nA            -0.8025nA
+  1.55    4.6215nA          13.7460nA            -4.4469nA
+  1.65    1.0974nA          10.1160nA            -7.9944nA
+  1.75    -2.4045nA         6.5107nA             -11.5260nA
+  1.85    -5.8986nA         2.9177nA             -15.0700nA
+  1.95    -9.3903nA         -0.6705nA            -18.6430nA
+  2.05    -12.8810nA        -4.2566nA            -22.2600nA
+  2.15    -16.3730nA        -7.8413nA            -25.9390nA
+  2.25    -19.8660nA        -11.4260nA           -29.7010nA
+  2.35    -23.3620nA        -15.0100nA           -33.5700nA
+  2.45    -26.8630nA        -18.5940nA           -37.5740nA
+  2.55    -30.3710nA        -22.1800nA           -41.7450nA
+  2.65    -33.8890nA        -25.7670nA           -46.1170nA
+  2.75    -37.4190nA        -29.3570nA           -50.7240nA
+  2.85    -40.9640nA        -32.9520nA           -55.6060nA
+  2.95    -44.5300nA        -36.5540nA           -60.8020nA
+  3.05    -48.1210nA        -40.1670nA           -66.3570nA
+  3.15    -51.7470nA        -43.7980nA           -72.4990nA
+  3.25    -55.4690nA        -47.4690nA           -97.5860nA
+  6.60    -57.5580nA        -49.34nA             -0.2325uA
+|  
+| End [Model] lvt330axxxefaaaaaain
+|************************************************************************
+[Model]           lvt330s040aaaaaaaaou
+Model_type        Output
+Polarity          Non-Inverting
+Enable            Active-Low
+Vmeas =           1.500000V
+Cref =            0.0F
+Rref =            1.0000M
+Vref =            0.0V
+C_comp            4.2000pF          3.8000pF             7.5000pF
+|  
+[Temperature Range]     25.0000           0.1050k              -40.0000
+[Voltage Range]         3.3000V           3.1400V              3.4700V
+[Pulldown] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    -11.9500mA        -8.6650mA            -15.6420mA
+  -3.20    -11.9500mA        -8.6650mA            -15.6420mA
+  -3.10    -11.9500mA        -8.6650mA            -15.6420mA
+  -3.00    -11.9500mA        -8.6650mA            -15.6420mA
+  -2.90    -11.9500mA        -8.6650mA            -15.6420mA
+  -2.80    -11.9500mA        -8.6650mA            -15.6420mA
+  -2.70    -11.9500mA        -8.6650mA            -15.6420mA
+  -2.60    -11.9500mA        -8.6650mA            -15.6420mA
+  -2.50    -11.9500mA        -8.6650mA            -15.6420mA
+  -2.40    -11.9500mA        -8.6650mA            -15.6420mA
+  -2.30    -11.9500mA        -8.6650mA            -15.6420mA
+  -2.20    -11.9500mA        -8.6650mA            -15.6420mA
+  -2.10    -11.9500mA        -8.6650mA            -15.6420mA
+  -2.00    -11.9500mA        -8.6650mA            -15.6420mA
+  -1.90    -11.9500mA        -8.6650mA            -15.6420mA
+  -1.80    -11.9500mA        -8.6650mA            -15.6420mA
+  -1.70    -11.9500mA        -8.6650mA            -15.6420mA
+  -1.60    -11.9500mA        -8.6650mA            -15.6420mA
+  -1.50    -11.9500mA        -8.6650mA            -15.6420mA
+  -1.40    -11.9500mA        -8.6650mA            -15.6420mA
+  -1.30    -11.9500mA        -8.6650mA            -15.6420mA
+  -1.20    -11.9500mA        -8.6650mA            -15.6420mA
+  -1.10    -11.9500mA        -8.6650mA            -15.6420mA
+  -1.00    -11.9500mA        -8.6650mA            -15.6420mA
+  -0.90    -11.9260mA        -8.6650mA            -14.3050mA
+  -0.80    -11.2400mA        -8.5300mA            -13.3800mA
+  -0.70    -10.7050mA        -8.3490mA            -12.9130mA
+  -0.60    -10.2262mA        -7.9463mA            -12.5750mA
+  -0.50    -9.6879mA         -7.2722mA            -12.3552mA
+  -0.40    -8.5353mA         -6.1307mA            -11.3241mA
+  -0.30    -6.5715mA         -4.6600mA            -8.7716mA
+  -0.20    -4.4298mA         -3.1245mA            -5.9312mA
+  -0.10    -2.2389mA         -1.5709mA            -3.0077mA
+  0.00    2.6070nA          1.8160nA             4.3450nA
+  0.10    2.2086mA          1.5382mA             2.9824mA
+  0.20    4.3047mA          2.9922mA             5.8245mA
+  0.30    6.2890mA          4.3627mA             8.5260mA
+  0.40    8.1616mA          5.6502mA             11.0870mA
+  0.50    9.9232mA          6.8553mA             13.5060mA
+  0.60    11.5740mA         7.9787mA             15.7840mA
+  0.70    13.1130mA         9.0208mA             17.9190mA
+  0.80    14.5410mA         9.9819mA             19.9070mA
+  0.90    15.8560mA         10.8620mA            21.7440mA
+  1.00    17.0540mA         11.6600mA            23.4200mA
+  1.10    18.1290mA         12.3750mA            24.9200mA
+  1.20    19.0710mA         13.0030mA            26.2250mA
+  1.30    19.8710mA         13.5400mA            27.3150mA
+  1.40    20.5280mA         13.9880mA            28.1920mA
+  1.50    21.0520mA         14.3520mA            28.8770mA
+  1.60    21.4690mA         14.6450mA            29.4110mA
+  1.70    21.8020mA         14.8830mA            29.8330mA
+  1.80    22.0750mA         15.0800mA            30.1740mA
+  1.90    22.3020mA         15.2450mA            30.4550mA
+  2.00    22.4950mA         15.3870mA            30.6940mA
+  2.10    22.6630mA         15.5110mA            30.8990mA
+  2.20    22.8110mA         15.6210mA            31.0780mA
+  2.30    22.9430mA         15.7190mA            31.2379mA
+  2.40    23.0630mA         15.8080mA            31.3819mA
+  2.50    23.1710mA         15.8900mA            31.5119mA
+  2.60    23.2710mA         15.9650mA            31.6318mA
+  2.70    23.3639mA         16.0350mA            31.7418mA
+  2.80    23.4499mA         16.0999mA            31.8447mA
+  2.90    23.5309mA         16.1609mA            31.9406mA
+  3.00    23.6069mA         16.2189mA            32.0305mA
+  3.10    23.6789mA         16.2739mA            32.1163mA
+  3.20    23.7478mA         16.3258mA            32.1981mA
+  3.30    23.8138mA         16.3756mA            32.2769mA
+  3.40    23.8786mA         16.4213mA            32.3557mA
+  3.50    23.9417mA         16.4526mA            32.4354mA
+  3.60    24.0002mA         16.6876mA            32.5189mA
+  3.70    24.0309mA         17.3426mA            32.6070mA
+  3.80    24.3774mA         19.1285mA            32.6921mA
+  3.90    25.3543mA         22.9154mA            32.7222mA
+  4.00    27.4942mA         28.3023mA            33.3062mA
+  4.10    30.5709mA         34.3240mA            34.9817mA
+  4.20    34.9446mA         40.5557mA            38.3579mA
+  4.30    41.2761mA         46.8344mA            42.8549mA
+  4.40    48.5706mA         53.0950mA            47.3478mA
+  4.50    56.1500mA         59.3125mA            52.6274mA
+  4.60    63.7762mA         65.4900mA            60.8279mA
+  4.70    71.3464mA         71.6374mA            70.1182mA
+  4.80    78.8056mA         77.7568mA            79.6014mA
+  4.90    86.1136mA         83.8381mA            88.9754mA
+  5.00    93.2445mA         89.8594mA            98.0452mA
+  5.10    0.1002A           95.7986mA            0.1067A
+  5.20    0.1069A           0.1016A              0.1148A
+  5.30    0.1134A           0.1074A              0.1224A
+  5.40    0.1197A           0.1130A              0.1298A
+  5.50    0.1258A           0.1184A              0.1369A
+  5.60    0.1318A           0.1237A              0.1439A
+  5.70    0.1376A           0.1289A              0.1508A
+  5.80    0.1432A           0.1340A              0.1576A
+  5.90    0.1488A           0.1390A              0.1644A
+  6.00    0.1544A           0.1438A              0.1712A
+  6.10    0.1598A           0.1485A              0.1780A
+  6.20    0.1652A           0.1530A              0.1848A
+  6.30    0.1706A           0.1575A              0.1916A
+  6.40    0.1760A           0.1620A              0.1984A
+  6.50    0.1813A           0.1663A              0.2053A
+  6.60    0.1867A           0.1705A              0.2122A
+|  
+[Pullup] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+-3.30       0.1819A       0.1298A        0.2190A    
+-3.20       0.1819A       0.1298A        0.2177A    
+-3.10       0.1819A       0.1298A        0.2139A    
+-3.00       0.1785A       0.1298A        0.2092A    
+-2.90       0.1743A       0.1298A        0.2039A    
+-2.80       0.1697A       0.1298A        0.1982A    
+-2.70       0.1647A       0.1298A        0.1922A    
+-2.60       0.1594A       0.1298A        0.1860A    
+-2.50       0.1538A       0.1298A        0.1795A    
+-2.40       0.1479A       0.1298A        0.1728A    
+-2.30       0.1418A       0.1259A        0.1658A    
+-2.20       0.1353A       0.1198A        0.1586A    
+-2.10       0.1286A       0.1135A        0.1512A    
+-2.00       0.1216A       0.1069A        0.1435A    
+-1.90       0.1142A       0.1002A        0.1355A    
+-1.80       0.1066A       93.3488mA        0.1271A    
+-1.70       93.5831mA       86.3555mA        0.1182A    
+-1.60       85.8190mA       79.2592mA        0.1088A    
+-1.50       77.8471mA       72.0828mA        98.7659mA    
+-1.40       69.6957mA       64.8453mA        88.3330mA    
+-1.30       61.4020mA       57.5538mA        77.6100mA    
+-1.20       53.0124mA       50.2142mA        66.7828mA    
+-1.10       44.6065mA       42.8446mA        56.1774mA    
+-1.00       36.3505mA       35.4829mA        46.7939mA    
+-0.90       28.6912mA       28.2232mA        39.5361mA    
+-0.80       22.4746mA       21.3014mA        32.3042mA    
+-0.70       17.6024mA       15.3245mA        25.5251mA    
+-0.60       13.5809mA       11.1535mA        19.7918mA    
+-0.50       10.4816mA       8.4310mA        14.7443mA    
+-0.40       8.0206mA       6.4251mA        11.9096mA    
+-0.30       5.9614mA       4.6861mA        8.8891mA    
+-0.20       3.9365mA       3.0816mA        5.8934mA    
+-0.10       1.9506mA       1.5203mA        2.9319mA    
+0.00       -7.7700nA       -3.4200nA        -87.8000nA    
+0.10       -1.8904mA       -1.4640mA        -2.8585mA    
+0.20       -3.6938mA       -2.8556mA        -5.5960mA    
+0.30       -5.4106mA       -4.1752mA        -8.2131mA    
+0.40       -7.0415mA       -5.4235mA        -10.7106mA    
+0.50       -8.5871mA       -6.6009mA        -13.0875mA    
+0.60       -10.0478mA       -7.7082mA        -15.3464mA    
+0.70       -11.4233mA       -8.7458mA        -17.4873mA    
+0.80       -12.7164mA       -9.7144mA        -19.5102mA    
+0.90       -13.9250mA       -10.6140mA        -21.4151mA    
+1.00       -15.0511mA       -11.4460mA        -23.2041mA    
+1.10       -16.0947mA       -12.2110mA        -24.8771mA    
+1.20       -17.0567mA       -12.9090mA        -26.4350mA    
+1.30       -17.9380mA       -13.5400mA        -27.8770mA    
+1.40       -18.7378mA       -14.1060mA        -29.2060mA    
+1.50       -19.4578mA       -14.6060mA        -30.4200mA    
+1.60       -20.0982mA       -15.0420mA        -31.5220mA    
+1.70       -20.6608mA       -15.4150mA        -32.5110mA    
+1.80       -21.1446mA       -15.7260mA        -33.3890mA    
+1.90       -21.5526mA       -15.9770mA        -34.1570mA    
+2.00       -21.8875mA       -16.1730mA        -34.8170mA    
+2.10       -22.1540mA       -16.3230mA        -35.3710mA    
+2.20       -22.3628mA       -16.4420mA        -35.8270mA    
+2.30       -22.5316mA       -16.5430mA        -36.1970mA    
+2.40       -22.6758mA       -16.6340mA        -36.5020mA    
+2.50       -22.8058mA       -16.7200mA        -36.7650mA    
+2.60       -22.9282mA       -16.8010mA        -37.0040mA    
+2.70       -23.0458mA       -16.8800mA        -37.2270mA    
+2.80       -23.1578mA       -16.9560mA        -37.4390mA    
+2.90       -23.2659mA       -17.0290mA        -37.6420mA    
+3.00       -23.3712mA       -17.1009mA        -37.8370mA    
+3.10       -23.4737mA       -17.1709mA        -38.0259mA    
+3.20       -23.5732mA       -17.2379mA        -38.2079mA    
+3.30       -23.6690mA       -17.3046mA        -38.3849mA    
+3.40       -23.7639mA       -17.3656mA        -38.5569mA    
+3.50       -23.8544mA       -17.3881mA        -38.7229mA    
+3.60       -23.9301mA       -17.3881mA        -38.8849mA    
+3.70       -23.9301mA       -17.3881mA        -39.0415mA    
+3.80       -23.9301mA       -17.3881mA        -39.1532mA    
+3.90       -23.9301mA       -17.3881mA        -39.1532mA    
+4.00       -23.9301mA       -17.3881mA        -39.1532mA    
+4.10       -23.9301mA       -17.3881mA        -39.1532mA    
+4.20       -23.9301mA       -17.3881mA        -39.1532mA    
+4.30       -23.9301mA       -17.3881mA        -39.1532mA    
+4.40       -23.9301mA       -17.3881mA        -39.1532mA    
+4.50       -23.9301mA       -17.3881mA        -39.1532mA    
+4.60       -23.9301mA       -17.3881mA        -39.1532mA    
+4.70       -23.9301mA       -17.3881mA        -39.1532mA    
+4.80       -23.9301mA       -17.3881mA        -39.1532mA    
+4.90       -23.9301mA       -17.3881mA        -39.1532mA    
+5.00       -23.9301mA       -17.3881mA        -39.1532mA    
+5.10       -23.9301mA       -17.3881mA        -39.1532mA    
+5.20       -23.9301mA       -17.3881mA        -39.1532mA    
+5.30       -23.9301mA       -17.3881mA        -39.1532mA    
+5.40       -23.9301mA       -17.3881mA        -39.1532mA    
+5.50       -23.9301mA       -17.3881mA        -39.1532mA    
+5.60       -23.9301mA       -17.3881mA        -39.1532mA    
+5.70       -23.9301mA       -17.3881mA        -39.1532mA    
+5.80       -23.9301mA       -17.3881mA        -39.1532mA    
+5.90       -23.9301mA       -17.3881mA        -39.1532mA    
+6.00       -23.9301mA       -17.3881mA        -39.1532mA    
+6.10       -23.9301mA       -17.3881mA        -39.1532mA    
+6.20       -23.9301mA       -17.3881mA        -39.1532mA    
+6.30       -23.9301mA       -17.3881mA        -39.1532mA    
+6.40       -23.9301mA       -17.3881mA        -39.1532mA    
+6.50       -23.9301mA       -17.3881mA        -39.1532mA    
+6.55       -23.9301mA       -17.3881mA        -39.1532mA    
+[GND_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    -0.9553A          -0.9303A             -0.978A
+  -3.25    -0.9307A          -0.9059A             -0.9534A
+  -3.20    -0.9062A          -0.8815A             -0.9287A
+  -3.15    -0.8816A          -0.8571A             -0.9041A
+  -3.10    -0.8571A          -0.8328A             -0.8794A
+  -3.05    -0.8326A          -0.8084A             -0.8548A
+  -3.00    -0.8081A          -0.7841A             -0.8302A
+  -2.95    -0.7837A          -0.7598A             -0.8056A
+  -2.90    -0.7592A          -0.7356A             -0.781A
+  -2.85    -0.7348A          -0.7113A             -0.7565A
+  -2.80    -0.7104A          -0.6872A             -0.7319A
+  -2.75    -0.686A           -0.663A              -0.7074A
+  -2.70    -0.6617A          -0.6389A             -0.6829A
+  -2.65    -0.6374A          -0.6149A             -0.6584A
+  -2.60    -0.6131A          -0.5909A             -0.634A
+  -2.55    -0.5889A          -0.5669A             -0.6096A
+  -2.50    -0.5647A          -0.5431A             -0.5852A
+  -2.45    -0.5406A          -0.5193A             -0.5609A
+  -2.40    -0.5166A          -0.4956A             -0.5366A
+  -2.35    -0.4926A          -0.472A              -0.5124A
+  -2.30    -0.4687A          -0.4485A             -0.4882A
+  -2.25    -0.4449A          -0.4251A             -0.4641A
+  -2.20    -0.4211A          -0.4019A             -0.44A
+  -2.15    -0.3976A          -0.3789A             -0.4161A
+  -2.10    -0.3741A          -0.3562A             -0.3923A
+  -2.05    -0.3509A          -0.3337A             -0.3686A
+  -2.00    -0.3279A          -0.3116A             -0.3451A
+  -1.95    -0.3052A          -0.2899A             -0.3218A
+  -1.90    -0.283A           -0.2689A             -0.2988A
+  -1.85    -0.2612A          -0.2486A             -0.2762A
+  -1.80    -0.2402A          -0.2294A             -0.2543A
+  -1.75    -0.2204A          -0.2116A             -0.2332A
+  -1.70    -0.202A           -0.1954A             -0.2135A
+  -1.65    -0.1857A          -0.181A              -0.1959A
+  -1.60    -0.1717A          -0.1682A             -0.181A
+  -1.55    -0.1594A          -0.1563A             -0.1685A
+  -1.50    -0.1481A          -0.1452A             -0.1571A
+  -1.45    -0.1372A          -0.1343A             -0.1462A
+  -1.40    -0.1266A          -0.1237A             -0.1355A
+  -1.35    -0.1162A          -0.1132A             -0.125A
+  -1.30    -0.106A           -0.1029A             -0.1146A
+  -1.25    -95.9599mA        -92.8329mA           -0.1046A
+  -1.20    -86.1849mA        -82.9339mA           -94.9069mA
+  -1.15    -76.7349mA        -73.2869mA           -85.7379mA
+  -1.10    -67.7089mA        -63.9519mA           -77.2789mA
+  -1.05    -59.2439mA        -55.0099mA           -69.7479mA
+  -1.00    -51.5159mA        -46.5729mA           -63.2139mA
+  -0.95    -44.7119mA        -38.7979mA           -57.3089mA
+  -0.90    -38.8659mA        -31.8819mA           -51.2599mA
+  -0.85    -33.5299mA        -25.9129mA           -44.7209mA
+  -0.80    -28.2499mA        -20.5839mA           -37.9699mA
+  -0.75    -23.0669mA        -15.7839mA           -31.2789mA
+  -0.70    -18.0989mA        -11.6329mA           -24.8089mA
+  -0.65    -13.4569mA        -8.1389mA            -18.6889mA
+  -0.60    -9.2667mA         -5.2646mA            -13.0589mA
+  -0.55    -5.6915mA         -3.0244mA            -8.1194mA
+  -0.50    -2.937mA          -1.4709mA            -4.1747mA
+  -0.45    -1.1814mA         -0.5866mA            -1.592mA
+  -0.40    -0.3589mA         -0.1961mA            -0.4238mA
+  -0.35    -88.3674uA        -58.3595uA           -88.5118uA
+  -0.30    -18.8304uA        -15.9765uA           -16.7268uA
+  -0.25    -3.5316uA         -4.0546uA            -3.0027uA
+  -0.20    -0.6045uA         -0.9665uA            -0.4941uA
+  -0.15    -99.742nA         -0.2204uA            -76.537nA
+  -0.10    -17.537nA         -48.631nA            -14.0860nA
+  -0.05    -3.547nA          -9.5380nA            -3.817nA
+  0.00    0.0A              0.0A                 0.0A
+  6.60    0.0A              0.0A                 0.0A
+|  
+[POWER_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.25    0.6648mA          0.7494mA             0.5971mA
+  -3.15    0.5464mA          0.6392mA             0.4620mA
+  -3.05    0.4320mA          0.5325mA             0.3346mA
+  -2.95    0.3223mA          0.4288mA             0.2203mA
+  -2.85    0.2202mA          0.3288mA             0.1294mA
+  -2.75    0.1318mA          0.2341mA             72.8310uA
+  -2.65    67.1930uA         0.1484mA             47.8290uA
+  -2.55    33.3830uA         79.2120uA            38.1420uA
+  -2.45    21.1010uA         36.2260uA            33.4220uA
+  -2.35    16.7340uA         18.9530uA            30.1320uA
+  -2.25    14.6010uA         13.5620uA            27.2560uA
+  -2.15    13.0520uA         11.4690uA            24.5640uA
+  -2.05    11.6720uA         10.2210uA            22.0120uA
+  -1.95    10.3780uA         9.1893uA             19.5960uA
+  -1.85    9.1543uA          8.2396uA             17.3210uA
+  -1.75    8.0014uA          7.3461uA             15.1920uA
+  -1.65    6.9210uA          6.5045uA             13.2170uA
+  -1.55    5.9158uA          5.7141uA             11.4020uA
+  -1.45    4.9887uA          4.9753uA             9.7529uA
+  -1.35    4.1426uA          4.2887uA             8.2767uA
+  -1.25    3.3804uA          3.6548uA             6.9786uA
+  -1.15    2.7049uA          3.0746uA             5.8648uA
+  -1.05    2.1189uA          2.5487uA             4.9428uA
+  -0.95    1.6251uA          2.0780uA             4.2177uA
+  -0.85    1.2274uA          1.6631uA             3.6560uA
+  -0.75    0.9313uA          1.3051uA             3.6560uA
+  -0.65    0.7398uA          1.0056uA             3.6560uA
+  -0.55    0.6327uA          0.7679uA             3.6560uA
+  -0.45    0.5649uA          0.5968uA             1.9769uA
+  -0.35    0.5649uA          0.4927uA             1.5352uA
+  -0.25    0.5649uA          0.4380uA             1.2603uA
+  -0.15    0.5649uA          0.4056uA             1.0262uA
+  -0.05    0.2497uA          0.3924uA             0.8243uA
+  0.00    0.1905uA          0.3924uA             0.7347uA
+  0.05    0.1661uA          0.3924uA             0.6522uA
+  0.15    0.1377uA          0.3924uA             0.5077uA
+  0.25    0.1149uA          0.2673uA             0.3882uA
+  0.35    95.5840nA         94.4790nA            0.2911uA
+  0.45    79.2300nA         72.9410nA            0.2139uA
+  0.55    65.5240nA         63.7780nA            0.1539uA
+  0.65    54.1200nA         56.2440nA            0.1084uA
+  0.75    44.6720nA         49.6060nA            74.7270nA
+  0.85    36.8450nA         43.7060nA            50.5340nA
+  0.95    30.3210nA         38.4180nA            33.5490nA
+  1.05    24.8050nA         33.6240nA            21.8000nA
+  1.15    20.0360nA         29.2180nA            13.6290nA
+  1.25    15.7920nA         25.1030nA            7.7259nA
+  1.35    11.8920nA         21.1950nA            3.1291nA
+  1.45    8.2001nA          17.4270nA            -0.8025nA
+  1.55    4.6216nA          13.7460nA            -4.4469nA
+  1.65    1.0975nA          10.1160nA            -7.9944nA
+  1.75    -2.4045nA         6.5107nA             -11.5260nA
+  1.85    -5.8985nA         2.9177nA             -15.0700nA
+  1.95    -9.3903nA         -0.6705nA            -18.6430nA
+  2.05    -12.8810nA        -4.2565nA            -22.2600nA
+  2.15    -16.3730nA        -7.8414nA            -25.9390nA
+  2.25    -19.8660nA        -11.4260nA           -29.7010nA
+  2.35    -23.3620nA        -15.0100nA           -33.5700nA
+  2.45    -26.8630nA        -18.5940nA           -37.5740nA
+  2.55    -30.3710nA        -22.1800nA           -41.7450nA
+  2.65    -33.8890nA        -25.7670nA           -46.1170nA
+  2.75    -37.4190nA        -29.3570nA           -50.7240nA
+  2.85    -40.9640nA        -32.9520nA           -55.6060nA
+  2.95    -44.5300nA        -36.5540nA           -60.8020nA
+  3.05    -48.1210nA        -40.1670nA           -66.3570nA
+  3.15    -51.7470nA        -43.7980nA           -72.4990nA
+  3.25    -55.4690nA        -47.4690nA           -97.5860nA
+  6.60    -57.5580nA        -49.34nA             -0.2325uA
+|  
+[Ramp]  
+| variable       typ                 min                 max 
+dV/dt_r  0.7026/0.4330n      0.4966/0.5731n      1.0018/0.3242n
+dV/dt_f  0.6827/0.4387n      0.4730/0.5599n      0.9168/0.3576n
+R_load = 50.0000
+|  
+[Rising Waveform] 
+R_fixture=       50.0000
+V_fixture=       3.3000
+V_fixture_min=   3.1400
+V_fixture_max=   3.4700
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              2.1621V           2.3517V              1.9420V
+0.1010nS          2.1621V           2.3517V              1.9420V
+0.2020nS          2.1621V           2.3517V              1.9420V
+0.3030nS          2.1621V           2.3517V              1.9420V
+0.4040nS          2.1621V           2.3517V              1.9420V
+0.5051nS          2.1622V           2.3517V              2.2421V
+0.6061nS          2.1615V           2.3517V              2.8060V
+0.7071nS          2.2762V           2.3517V              3.1342V
+0.8081nS          2.7361V           2.3522V              3.3164V
+0.9091nS          2.9561V           2.3515V              3.3898V
+1.0101nS          3.0907V           2.3704V              3.4244V
+1.1111nS          3.1772V           2.6051V              3.4432V
+1.2121nS          3.2242V           2.8360V              3.4539V
+1.3131nS          3.2509V           2.9413V              3.4602V
+1.4141nS          3.2670V           3.0020V              3.4639V
+1.5152nS          3.2775V           3.0439V              3.4662V
+1.6162nS          3.2845V           3.0714V              3.4676V
+1.7172nS          3.2892V           3.0897V              3.4685V
+1.8182nS          3.2924V           3.1025V              3.4690V
+1.9192nS          3.2946V           3.1117V              3.4694V
+2.0202nS          3.2961V           3.1186V              3.4696V
+2.1212nS          3.2972V           3.1237V              3.4697V
+2.2222nS          3.2980V           3.1276V              3.4698V
+2.3232nS          3.2986V           3.1305V              3.4699V
+2.4242nS          3.2989V           3.1327V              3.4699V
+2.5253nS          3.2992V           3.1344V              3.4699V
+2.6263nS          3.2994V           3.1356V              3.4699V
+2.7273nS          3.2996V           3.1366V              3.4699V
+2.8283nS          3.2997V           3.1373V              3.4699V
+2.9293nS          3.2998V           3.1379V              3.4700V
+3.0303nS          3.2998V           3.1383V              3.4699V
+3.1313nS          3.2999V           3.1387V              3.4700V
+3.2323nS          3.2999V           3.1390V              3.4699V
+3.3333nS          3.2999V           3.1392V              3.4700V
+3.4343nS          3.2999V           3.1393V              3.4699V
+3.5354nS          3.2999V           3.1395V              3.4700V
+3.6364nS          3.3000V           3.1396V              3.4699V
+3.7374nS          3.3000V           3.1397V              3.4700V
+3.8384nS          3.3000V           3.1397V              3.4700V
+3.9394nS          3.3000V           3.1398V              3.4700V
+4.0404nS          3.3000V           3.1398V              3.4700V
+4.1414nS          3.3000V           3.1399V              3.4700V
+4.2424nS          3.3000V           3.1399V              3.4700V
+4.3434nS          3.3000V           3.1399V              3.4700V
+4.4444nS          3.3000V           3.1400V              3.4700V
+4.5455nS          3.3000V           3.1400V              3.4700V
+4.6465nS          3.3000V           3.1399V              3.4700V
+4.7475nS          3.3000V           3.1400V              3.4700V
+4.8485nS          3.3000V           3.1400V              3.4700V
+4.9495nS          3.3000V           3.1400V              3.4700V
+5.0505nS          3.3000V           3.1400V              3.4700V
+5.1515nS          3.3000V           3.1400V              3.4699V
+5.2525nS          3.3000V           3.1400V              3.4700V
+5.3535nS          3.3000V           3.1400V              3.4700V
+5.4545nS          3.3000V           3.1400V              3.4700V
+5.5556nS          3.3000V           3.1400V              3.4699V
+5.6566nS          3.3000V           3.1400V              3.4700V
+5.7576nS          3.3000V           3.1400V              3.4700V
+5.8586nS          3.3000V           3.1400V              3.4700V
+5.9596nS          3.3000V           3.1400V              3.4699V
+6.0606nS          3.3000V           3.1400V              3.4700V
+6.1616nS          3.3000V           3.1400V              3.4700V
+6.2626nS          3.3000V           3.1400V              3.4700V
+6.3636nS          3.3000V           3.1400V              3.4699V
+6.4646nS          3.3000V           3.1400V              3.4700V
+6.5657nS          3.3000V           3.1400V              3.4700V
+6.6667nS          3.3000V           3.1400V              3.4700V
+6.7677nS          3.3000V           3.1400V              3.4699V
+6.8687nS          3.3000V           3.1400V              3.4700V
+6.9697nS          3.3000V           3.1400V              3.4700V
+7.0707nS          3.3000V           3.1400V              3.4700V
+7.1717nS          3.3000V           3.1400V              3.4700V
+7.2727nS          3.3000V           3.1400V              3.4700V
+7.3737nS          3.3000V           3.1400V              3.4700V
+7.4747nS          3.3000V           3.1400V              3.4700V
+7.5758nS          3.3000V           3.1400V              3.4700V
+7.6768nS          3.3000V           3.1400V              3.4700V
+7.7778nS          3.3000V           3.1400V              3.4700V
+7.8788nS          3.3000V           3.1400V              3.4700V
+7.9798nS          3.3000V           3.1400V              3.4699V
+8.0808nS          3.3000V           3.1400V              3.4700V
+8.1818nS          3.3000V           3.1400V              3.4700V
+8.2828nS          3.3000V           3.1400V              3.4700V
+8.3838nS          3.3000V           3.1400V              3.4700V
+8.4848nS          3.3000V           3.1400V              3.4700V
+8.5859nS          3.3000V           3.1400V              3.4700V
+8.6869nS          3.3000V           3.1400V              3.4700V
+8.7879nS          3.3000V           3.1400V              3.4700V
+8.8889nS          3.3000V           3.1400V              3.4700V
+8.9899nS          3.3000V           3.1400V              3.4700V
+9.0909nS          3.3000V           3.1400V              3.4700V
+9.1919nS          3.3000V           3.1400V              3.4700V
+9.2929nS          3.3000V           3.1400V              3.4700V
+9.3939nS          3.3000V           3.1400V              3.4700V
+9.4949nS          3.3000V           3.1400V              3.4700V
+9.5960nS          3.3000V           3.1400V              3.4700V
+9.6970nS          3.3000V           3.1400V              3.4700V
+9.7980nS          3.3000V           3.1400V              3.4700V
+9.8990nS          3.3000V           3.1400V              3.4700V
+10.0000nS         3.3000V           3.1400V              3.4700V
+|  
+[Rising Waveform] 
+R_fixture=       50.0000
+V_fixture=       0.0
+V_fixture_min=   0.0
+V_fixture_max=   0.0
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              1.2884uV          1.5543uV             1.3225uV
+0.1010nS          0.5355uV          0.8430uV             0.6254uV
+0.2020nS          -3.0614uV         0.1113uV             0.5701uV
+0.3030nS          0.6806uV          -1.9546uV            10.3860uV
+0.4040nS          3.2624uV          1.2769uV             -0.2118mV
+0.5051nS          32.7230uV         1.5286uV             -24.1640mV
+0.6061nS          -0.3955mV         2.8080uV             -9.9395mV
+0.7071nS          -15.7200mV        17.6660uV            0.1561V
+0.8081nS          -19.9850mV        99.9200uV            0.5397V
+0.9091nS          -0.4586mV         -0.2072mV            0.9226V
+1.0101nS          88.3420mV         -6.1838mV            1.2091V
+1.1111nS          0.2478V          -18.1000mV            1.3886V   
+1.2121nS          0.4471V          -16.0430mV            1.4951V   
+1.3131nS          0.6318V          -10.1180mV            1.5589V   
+1.4141nS          0.7749V          8.8815mV            1.5984V   
+1.5152nS          0.8766V          55.5920mV            1.6234V   
+1.6162nS          0.9465V          0.1340V            1.6394V   
+1.7172nS          0.9942V          0.2360V            1.6498V   
+1.8182nS          1.0272V          0.3461V            1.6566V   
+1.9192nS          1.0502V          0.4492V            1.6613V   
+2.0202nS          1.0667V          0.5367V            1.6638V   
+2.1212nS          1.0785V          0.6066V            1.6656V   
+2.2222nS          1.0871V          0.6605V            1.6667V   
+2.3232nS          1.0934V          0.7013V            1.6675V   
+2.4242nS          1.0979V          0.7318V            1.6680V   
+2.5253nS          1.1013V          0.7546V            1.6684V   
+2.6263nS          1.1038V          0.7716V            1.6687V   
+2.7273nS          1.1056V          0.7845V            1.6689V   
+2.8283nS          1.1069V          0.7942V            1.6691V   
+2.9293nS          1.1080V          0.8016V            1.6693V   
+3.0303nS          1.1087V          0.8073V            1.6693V   
+3.1313nS          1.1093V          0.8118V            1.6694V   
+3.2323nS          1.1097V          0.8152V            1.6695V   
+3.3333nS          1.1100V          0.8178V            1.6695V   
+3.4343nS          1.1103V          0.8199V            1.6695V   
+3.5354nS          1.1104V          0.8215V            1.6696V   
+3.6364nS          1.1105V          0.8228V            1.6695V   
+3.7374nS          1.1106V          0.8238V            1.6696V   
+3.8384nS          1.1107V          0.8246V            1.6696V   
+3.9394nS          1.1107V          0.8252V            1.6696V   
+4.0404nS          1.1108V          0.8257V            1.6696V   
+4.1414nS          1.1108V          0.8261V            1.6696V   
+4.2424nS          1.1108V          0.8265V            1.6696V   
+4.3434nS          1.1109V          0.8267V            1.6696V   
+4.4444nS          1.1109V          0.8269V            1.6696V   
+4.5455nS          1.1109V          0.8271V            1.6696V   
+4.6465nS          1.1109V          0.8272V            1.6696V   
+4.7475nS          1.1109V          0.8273V            1.6696V   
+4.8485nS          1.1109V          0.8274V            1.6696V   
+4.9495nS          1.1109V          0.8274V            1.6696V   
+5.0505nS          1.1109V          0.8276V            1.6696V   
+5.1515nS          1.1109V          0.8276V            1.6696V   
+5.2525nS          1.1109V          0.8276V            1.6696V   
+5.3535nS          1.1109V          0.8276V            1.6696V   
+5.4545nS          1.1109V          0.8276V            1.6696V   
+5.5556nS          1.1109V          0.8276V            1.6696V   
+5.6566nS          1.1109V          0.8276V            1.6696V   
+5.7576nS          1.1109V          0.8277V            1.6696V   
+5.8586nS          1.1109V          0.8277V            1.6696V   
+5.9596nS          1.1109V          0.8277V            1.6696V   
+6.0606nS          1.1109V          0.8277V            1.6696V   
+6.1616nS          1.1109V          0.8277V            1.6696V   
+6.2626nS          1.1109V          0.8277V            1.6696V   
+6.3636nS          1.1109V          0.8277V            1.6696V   
+6.4646nS          1.1109V          0.8277V            1.6696V   
+6.5657nS          1.1109V          0.8277V            1.6696V   
+6.6667nS          1.1110V          0.8277V            1.6696V   
+6.7677nS          1.1109V          0.8277V            1.6696V   
+6.8687nS          1.1109V          0.8277V            1.6696V   
+6.9697nS          1.1109V          0.8277V            1.6696V   
+7.0707nS          1.1110V          0.8277V            1.6696V   
+7.1717nS          1.1109V          0.8277V            1.6696V   
+7.2727nS          1.1110V          0.8277V            1.6696V   
+7.3737nS          1.1110V          0.8277V            1.6696V   
+7.4747nS          1.1110V          0.8277V            1.6696V   
+7.5758nS          1.1110V          0.8277V            1.6696V   
+7.6768nS          1.1110V          0.8277V            1.6696V   
+7.7778nS          1.1109V          0.8277V            1.6696V   
+7.8788nS          1.1110V          0.8277V            1.6696V   
+7.9798nS          1.1110V          0.8277V            1.6696V   
+8.0808nS          1.1110V          0.8277V            1.6696V   
+8.1818nS          1.1109V          0.8277V            1.6696V   
+8.2828nS          1.1110V          0.8277V            1.6696V   
+8.3838nS          1.1110V          0.8277V            1.6696V   
+8.4848nS          1.1110V          0.8277V            1.6696V   
+8.5859nS          1.1110V          0.8277V            1.6696V   
+8.6869nS          1.1110V          0.8277V            1.6696V   
+8.7879nS          1.1109V          0.8277V            1.6696V   
+8.8889nS          1.1109V          0.8277V            1.6696V   
+8.9899nS          1.1109V          0.8277V            1.6696V   
+9.0909nS          1.1109V          0.8277V            1.6696V   
+9.1919nS          1.1109V          0.8277V            1.6696V   
+9.2929nS          1.1109V          0.8277V            1.6696V   
+9.3939nS          1.1109V          0.8277V            1.6696V   
+9.4949nS          1.1109V          0.8277V            1.6696V   
+9.5960nS          1.1109V          0.8277V            1.6696V   
+9.6970nS          1.1110V          0.8277V            1.6696V   
+9.7980nS          1.1110V          0.8277V            1.6696V   
+9.8990nS          1.1110V          0.8277V            1.6696V   
+10.0000nS          1.1109V          0.8277V            1.6696V   
+[Falling Waveform] 
+R_fixture=       50.0000
+V_fixture=       0.0
+V_fixture_min=   0.0
+V_fixture_max=   0.0
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S          1.1109V          0.8277V            1.6696V   
+0.1010nS          1.1109V          0.8277V            1.6696V   
+0.2020nS          1.1109V          0.8277V            1.6696V   
+0.3030nS          1.1110V          0.8277V            1.6696V   
+0.4040nS          1.1110V          0.8277V            1.6696V   
+0.5051nS          1.1109V          0.8277V            1.6644V   
+0.6061nS          1.1110V          0.8277V            1.0431V   
+0.7071nS          1.1113V          0.8277V            0.4157V   
+0.8081nS          0.9851V          0.8277V            0.1612V   
+0.9091nS          0.5727V          0.8276V            77.0900mV   
+1.0101nS          0.2814V          0.8282V            40.8740mV   
+1.1111nS          0.1329V          0.8285V            22.9430mV   
+1.2121nS          73.6840mV         0.7997V              12.4510mV
+1.3131nS          43.0370mV         0.5895V              6.8313mV
+1.4141nS          26.7550mV         0.3604V              3.7992mV
+1.5152nS          17.0970mV         0.2116V              2.1510mV
+1.6162nS          11.1140mV         0.1248V              1.2529mV
+1.7172nS          7.2776mV          75.3210mV            0.7544mV
+1.8182nS          4.8176mV          47.2290mV            0.4826mV
+1.9192nS          3.1888mV          31.3570mV            0.3253mV
+2.0202nS          2.1519mV          21.8020mV            0.2392mV
+2.1212nS          1.4430mV          15.5850mV            0.1806mV
+2.2222nS          1.0065mV          11.3310mV            0.1485mV
+2.3232nS          0.6888mV          8.3187mV             0.1251mV
+2.4242nS          0.5069mV          6.1527mV             0.1108mV
+2.5253nS          0.3566mV          4.5704mV             0.1026mV
+2.6263nS          0.2717mV          3.4134mV             96.2470uV
+2.7273nS          0.1995mV          2.5569mV             87.3860uV
+2.8283nS          0.1853mV          1.9272mV             82.9260uV
+2.9293nS          0.1277mV          1.4565mV             68.6140uV
+3.0303nS          0.1252mV          1.1098mV             60.2230uV
+3.1313nS          89.5590uV         0.8485mV             49.7170uV
+3.2323nS          94.4160uV         0.6561mV             56.7570uV
+3.3333nS          49.7470uV         0.5093mV             54.1530uV
+3.4343nS          57.0870uV         0.3863mV             49.3370uV
+3.5354nS          52.4280uV         0.3073mV             42.7020uV
+3.6364nS          77.0030uV         0.2451mV             40.7070uV
+3.7374nS          46.1550uV         0.1875mV             33.9890uV
+3.8384nS          63.3650uV         0.1621mV             34.0740uV
+3.9394nS          31.9750uV         0.1378mV             27.5110uV
+4.0404nS          46.0820uV         0.1176mV             33.5240uV
+4.1414nS          14.0450uV         0.1002mV             26.4520uV
+4.2424nS          30.8440uV         91.6770uV            22.6270uV
+4.3434nS          23.9580uV         76.4830uV            15.2880uV
+4.4444nS          37.9550uV         66.7720uV            22.2140uV
+4.5455nS          20.1420uV         54.3060uV            29.8260uV
+4.6465nS          38.7320uV         46.2710uV            31.2670uV
+4.7475nS          7.9010uV          34.7060uV            23.8310uV
+4.8485nS          28.9680uV         27.4260uV            23.1060uV
+4.9495nS          3.7079uV          16.8370uV            10.7150uV
+5.0505nS          4.6522uV          25.8205uV            14.7445uV
+5.1515nS          12.5270uV         19.1810uV            11.7510uV
+5.2525nS          10.5410uV         17.0160uV            5.4213uV
+5.3535nS          42.1190uV         11.8180uV            8.5329uV
+5.4545nS          11.4930uV         19.2340uV            13.1240uV
+5.5556nS          38.3480uV         27.0890uV            18.1120uV
+5.6566nS          1.7742uV          38.8120uV            11.7850uV
+5.7576nS          22.6050uV         31.4050uV            7.1004uV
+5.8586nS          -3.9145uV         19.9240uV            -7.3305uV
+5.9596nS          13.3160uV         7.4008uV             0.4354uV
+6.0606nS          7.3534uV          -0.9538uV            7.7540uV
+6.1616nS          33.4920uV         -8.2614uV            8.9420uV
+6.2626nS          9.8852uV          1.6769uV             5.0332uV
+6.3636nS          25.5040uV         16.3790uV            2.4944uV
+6.4646nS          -2.5946uV         32.5920uV            -5.3283uV
+6.5657nS          4.1073uV          30.8730uV            6.9637uV
+6.6667nS          2.1062uV          21.8930uV            7.5789uV
+6.7677nS          10.6270uV         5.1201uV             6.5788uV
+6.8687nS          -19.4020uV        -8.0928uV            0.9709uV
+6.9697nS          3.6023uV          5.3486uV             -0.4159uV
+7.0707nS          -20.2800uV        10.3380uV            -4.1503uV
+7.1717nS          19.4790uV         23.0950uV            -4.9697uV
+7.2727nS          -10.7860uV        7.5118uV             -8.6698uV
+7.3737nS          21.7550uV         9.0311uV             -7.4803uV
+7.4747nS          12.4390uV         -5.6908uV            -10.4050uV
+7.5758nS          18.3510uV         -4.5175uV            -8.2164uV
+7.6768nS          -7.8114uV         1.1510uV             -10.8020uV
+7.7778nS          2.0275uV          12.3600uV            -1.5528uV
+7.8788nS          -76.1190nV        12.0690uV            6.6952uV
+7.9798nS          4.0097uV          8.9861uV             10.0890uV
+8.0808nS          0.4972uV          -1.8875uV            0.6130uV
+8.1818nS          0.5840uV          -11.3150uV           -1.5820uV
+8.2828nS          -12.7280uV        -15.9390uV           -8.5048uV
+8.3838nS          3.4867uV          -5.2058uV            -1.9719uV
+8.4848nS          -4.5739uV         2.6217uV             0.5424uV
+8.5859nS          4.1249uV          2.6585uV             4.0878uV
+8.6869nS          -12.0140uV        -0.6919uV            6.4732uV
+8.7879nS          -3.8915uV         -10.4690uV           7.0541uV
+8.8889nS          -10.5260uV        -22.7580uV           2.8919uV
+8.9899nS          2.5661uV          -25.3070uV           -3.3709uV
+9.0909nS          -2.9240uV         -11.4390uV           -5.9996uV
+9.1919nS          -3.0241uV         -1.1643uV            0.8082uV
+9.2929nS          -7.9366uV         5.3328uV             0.4492uV
+9.3939nS          -2.3621uV         8.5118uV             5.8039uV
+9.4949nS          -9.1146uV         -8.6006uV            -2.4704uV
+9.5960nS          -3.7574uV         -19.3450uV           -0.8494uV
+9.6970nS          -16.6030uV        -15.4900uV           -2.2380uV
+9.7980nS          -2.4824uV         -3.6242uV            4.0030uV
+9.8990nS          -18.6820uV        15.5490uV            1.5950uV
+10.0000nS         -1.0707uV         8.4164uV             -6.6712uV
+|  
+[Falling Waveform] 
+R_fixture=       50.0000
+V_fixture=       3.3000
+V_fixture_min=   3.1400
+V_fixture_max=   3.4700
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              3.3000V           3.1400V              3.4700V
+0.1010nS          3.3000V           3.1400V              3.4700V
+0.2020nS          3.3000V           3.1400V              3.4700V
+0.3030nS          3.3000V           3.1400V              3.4700V
+0.4040nS          3.3000V           3.1400V              3.4700V
+0.5051nS          3.3000V           3.1400V              3.4758V
+0.6061nS          3.3001V           3.1400V              3.4570V
+0.7071nS          3.2983V           3.1400V              3.0951V
+0.8081nS          3.3299V           3.1400V              2.7403V
+0.9091nS          3.2987V           3.1398V              2.4747V
+1.0101nS          3.1080V           3.1409V              2.2935V
+1.1111nS          2.8866V           3.1388V              2.1742V
+1.2121nS          2.6919V           3.1507V              2.0966V
+1.3131nS          2.5414V           3.1748V              2.0453V
+1.4141nS          2.4321V           3.1565V              2.0112V
+1.5152nS          2.3547V           3.0752V              1.9884V
+1.6162nS          2.3001V           2.9642V              1.9732V
+1.7172nS          2.2616V           2.8458V              1.9629V
+1.8182nS          2.2341V           2.7389V              1.9561V
+1.9192nS          2.2145V           2.6506V              1.9515V
+2.0202nS          2.2003V           2.5809V              1.9484V
+2.1212nS          2.1900V           2.5272V              1.9463V
+2.2222nS          2.1826V           2.4862V              1.9450V
+2.3232nS          2.1771V           2.4551V              1.9440V
+2.4242nS          2.1731V           2.4314V              1.9434V
+2.5253nS          2.1702V           2.4134V              1.9430V
+2.6263nS          2.1681V           2.3996V              1.9427V
+2.7273nS          2.1665V           2.3890V              1.9425V
+2.8283nS          2.1654V           2.3808V              1.9424V
+2.9293nS          2.1646V           2.3745V              1.9423V
+3.0303nS          2.1639V           2.3696V              1.9422V
+3.1313nS          2.1635V           2.3658V              1.9422V
+3.2323nS          2.1631V           2.3628V              1.9421V
+3.3333nS          2.1629V           2.3604V              1.9421V
+3.4343nS          2.1627V           2.3586V              1.9421V
+3.5354nS          2.1626V           2.3572V              1.9420V
+3.6364nS          2.1625V           2.3560V              1.9421V
+3.7374nS          2.1624V           2.3551V              1.9421V
+3.8384nS          2.1623V           2.3544V              1.9421V
+3.9394nS          2.1623V           2.3539V              1.9420V
+4.0404nS          2.1622V           2.3534V              1.9420V
+4.1414nS          2.1622V           2.3531V              1.9420V
+4.2424nS          2.1622V           2.3528V              1.9420V
+4.3434nS          2.1622V           2.3526V              1.9420V
+4.4444nS          2.1622V           2.3524V              1.9420V
+4.5455nS          2.1622V           2.3523V              1.9420V
+4.6465nS          2.1622V           2.3522V              1.9420V
+4.7475nS          2.1622V           2.3521V              1.9420V
+4.8485nS          2.1622V           2.3520V              1.9420V
+4.9495nS          2.1622V           2.3519V              1.9420V
+5.0505nS          2.1622V           2.3519V              1.9420V
+5.1515nS          2.1622V           2.3518V              1.9420V
+5.2525nS          2.1622V           2.3518V              1.9420V
+5.3535nS          2.1622V           2.3518V              1.9420V
+5.4545nS          2.1622V           2.3518V              1.9420V
+5.5556nS          2.1622V           2.3518V              1.9420V
+5.6566nS          2.1622V           2.3517V              1.9420V
+5.7576nS          2.1621V           2.3517V              1.9420V
+5.8586nS          2.1621V           2.3517V              1.9420V
+5.9596nS          2.1621V           2.3517V              1.9420V
+6.0606nS          2.1621V           2.3517V              1.9420V
+6.1616nS          2.1621V           2.3517V              1.9420V
+6.2626nS          2.1621V           2.3517V              1.9420V
+6.3636nS          2.1621V           2.3517V              1.9420V
+6.4646nS          2.1621V           2.3517V              1.9420V
+6.5657nS          2.1621V           2.3517V              1.9420V
+6.6667nS          2.1622V           2.3517V              1.9420V
+6.7677nS          2.1621V           2.3517V              1.9420V
+6.8687nS          2.1621V           2.3517V              1.9420V
+6.9697nS          2.1621V           2.3517V              1.9420V
+7.0707nS          2.1621V           2.3517V              1.9420V
+7.1717nS          2.1621V           2.3517V              1.9420V
+7.2727nS          2.1621V           2.3517V              1.9420V
+7.3737nS          2.1621V           2.3517V              1.9420V
+7.4747nS          2.1621V           2.3517V              1.9420V
+7.5758nS          2.1621V           2.3517V              1.9420V
+7.6768nS          2.1621V           2.3517V              1.9420V
+7.7778nS          2.1621V           2.3517V              1.9420V
+7.8788nS          2.1621V           2.3517V              1.9420V
+7.9798nS          2.1621V           2.3517V              1.9420V
+8.0808nS          2.1621V           2.3517V              1.9420V
+8.1818nS          2.1621V           2.3517V              1.9420V
+8.2828nS          2.1621V           2.3517V              1.9420V
+8.3838nS          2.1621V           2.3517V              1.9420V
+8.4848nS          2.1621V           2.3517V              1.9420V
+8.5859nS          2.1621V           2.3517V              1.9420V
+8.6869nS          2.1621V           2.3517V              1.9420V
+8.7879nS          2.1621V           2.3517V              1.9420V
+8.8889nS          2.1621V           2.3517V              1.9420V
+8.9899nS          2.1621V           2.3517V              1.9420V
+9.0909nS          2.1621V           2.3517V              1.9420V
+9.1919nS          2.1621V           2.3517V              1.9420V
+9.2929nS          2.1621V           2.3517V              1.9420V
+9.3939nS          2.1621V           2.3517V              1.9420V
+9.4949nS          2.1621V           2.3517V              1.9420V
+9.5960nS          2.1621V           2.3517V              1.9420V
+9.6970nS          2.1621V           2.3517V              1.9420V
+9.7980nS          2.1621V           2.3517V              1.9420V
+9.8990nS          2.1621V           2.3517V              1.9420V
+10.0000nS         2.1621V           2.3517V              1.9420V
+|  
+| End [Model] lvt330s040aaaaaaaaou
+|************************************************************************
+[Model]           lvt330s040haaaaaaaio
+Model_type        I/O
+Polarity          Non-Inverting
+Enable            Active-Low
+Vinl =            0.8000V
+Vinh =            2.0000V
+Vmeas =           1.500000V
+Cref =            0.0F
+Rref =            1.0000M
+Vref =            0.0V
+C_comp            4.2000pF          3.8000pF             7.5000pF
+|  
+[Temperature Range]     25.0000           0.1050k              -40.0000
+[Voltage Range]         3.3000V           3.1400V              3.4700V
+[Pulldown] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    -13.0175mA        -9.4589mA            -17.0245mA
+  -3.20    -12.9707mA        -9.4248mA            -16.9624mA
+  -3.10    -12.9240mA        -9.3908mA            -16.9003mA
+  -3.00    -12.8773mA        -9.3568mA            -16.8383mA
+  -2.90    -12.8305mA        -9.3227mA            -16.7762mA
+  -2.80    -12.7838mA        -9.2887mA            -16.7142mA
+  -2.70    -12.7370mA        -9.2546mA            -16.6521mA
+  -2.60    -12.6903mA        -9.2206mA            -16.5900mA
+  -2.50    -12.6435mA        -9.1866mA            -16.5280mA
+  -2.40    -12.5968mA        -9.1525mA            -16.4659mA
+  -2.30    -12.5500mA        -9.1185mA            -16.4038mA
+  -2.20    -12.5033mA        -9.0845mA            -16.3418mA
+  -2.10    -12.4566mA        -9.0504mA            -16.2797mA
+  -2.00    -12.4098mA        -9.0164mA            -16.2176mA
+  -1.90    -12.3631mA        -8.9824mA            -16.1556mA
+  -1.80    -12.3163mA        -8.9483mA            -16.0935mA
+  -1.70    -12.2696mA        -8.9143mA            -16.0314mA
+  -1.60    -12.2228mA        -8.8803mA            -15.9694mA
+  -1.50    -12.1761mA        -8.8462mA            -15.9073mA
+  -1.40    -12.1293mA        -8.8122mA            -15.8453mA
+  -1.30    -12.0826mA        -8.7781mA            -15.7832mA
+  -1.20    -12.0359mA        -8.7441mA            -15.7211mA
+  -1.10    -11.9891mA        -8.7101mA            -15.6591mA
+  -1.00    -11.9424mA        -8.6760mA            -15.5970mA
+  -0.90    -11.8920mA        -8.6420mA            -14.2580mA
+  -0.80    -11.2030mA        -8.5040mA            -13.3310mA
+  -0.70    -10.6640mA        -8.3180mA            -12.8580mA
+  -0.60    -10.1775mA        -7.9085mA            -12.5090mA
+  -0.50    -9.6242mA         -7.2249mA            -12.2652mA
+  -0.40    -8.4558mA         -6.0810mA            -11.1990mA
+  -0.30    -6.5017mA         -4.6206mA            -8.6527mA
+  -0.20    -4.3829mA         -3.0989mA            -5.8476mA
+  -0.10    -2.2159mA         -1.5586mA            -2.9656mA
+  0.00    1.3970nA          1.1420nA             1.8430nA
+  0.10    2.1875mA          1.5273mA             2.9429mA
+  0.20    4.2657mA          2.9723mA             5.7511mA
+  0.30    6.2349mA          4.3353mA             8.4238mA
+  0.40    8.0952mA          5.6169mA             10.9612mA
+  0.50    9.8472mA          6.8175mA             13.3613mA
+  0.60    11.4909mA         7.9379mA             15.6250mA
+  0.70    13.0251mA         8.9781mA             17.7500mA
+  0.80    14.4502mA         9.9381mA             19.7321mA
+  0.90    15.7635mA         10.8176mA            21.5658mA
+  1.00    16.9605mA         11.6151mA            23.2399mA
+  1.10    18.0347mA         12.3297mA            24.7385mA
+  1.20    18.9760mA         12.9574mA            26.0423mA
+  1.30    19.7754mA         13.4941mA            27.1313mA
+  1.40    20.4319mA         13.9418mA            28.0074mA
+  1.50    21.1825mA         14.4344mA            28.6916mA
+  1.60    21.5959mA         14.7249mA            29.6115mA
+  1.70    21.9250mA         14.9601mA            30.0279mA
+  1.80    22.1935mA         15.1539mA            30.3626mA
+  1.90    22.4157mA         15.3154mA            30.6368mA
+  2.00    22.6034mA         15.4536mA            30.8683mA
+  2.10    22.7656mA         15.5735mA            31.0653mA
+  2.20    22.9074mA         15.6790mA            31.2357mA
+  2.30    23.0328mA         15.7722mA            31.3865mA
+  2.40    23.1458mA         15.8561mA            31.5207mA
+  2.50    23.2463mA         15.9326mA            31.6404mA
+  2.60    23.3383mA         16.0018mA            31.7495mA
+  2.70    23.4230mA         16.0657mA            31.8480mA
+  2.80    23.5002mA         16.1243mA            31.9389mA
+  2.90    23.5720mA         16.1785mA            32.0223mA
+  3.00    23.6383mA         16.2294mA            32.0991mA
+  3.10    23.7003mA         16.2770mA            32.1714mA
+  3.20    23.7588mA         16.3211mA            32.2390mA
+  3.30    23.8138mA         16.3630mA            32.3031mA
+  3.40    23.8674mA         16.4006mA            32.3667mA
+  3.50    23.9193mA         16.4233mA            32.4306mA
+  3.60    23.9674mA         16.4889mA            32.4982mA
+  3.70    23.9882mA         16.5546mA            32.5708mA
+  3.80    24.0840mA         16.6202mA            32.6441mA
+  3.90    24.1798mA         16.6859mA            32.7359mA
+  4.00    24.2756mA         16.7515mA            32.8665mA
+  4.10    24.3714mA         16.8172mA            32.9972mA
+  4.20    24.4672mA         16.8828mA            33.1278mA
+  4.30    24.5630mA         16.9485mA            33.2584mA
+  4.40    24.6588mA         17.0142mA            33.3891mA
+  4.50    24.7546mA         17.0798mA            33.5197mA
+  4.60    24.8504mA         17.1455mA            33.6503mA
+  4.70    24.9462mA         17.2111mA            33.7810mA
+  4.80    25.0420mA         17.2768mA            33.9116mA
+  4.90    25.1378mA         17.3424mA            34.0423mA
+  5.00    25.2336mA         17.4081mA            34.1729mA
+  5.10    25.3294mA         17.4737mA            34.3035mA
+  5.20    25.4252mA         17.5394mA            34.4342mA
+  5.30    25.5210mA         17.6051mA            34.5648mA
+  5.40    25.6168mA         17.6707mA            34.6955mA
+  5.50    25.7126mA         17.7364mA            34.8261mA
+  5.60    25.8084mA         17.8020mA            34.9567mA
+  5.70    25.9042mA         17.8677mA            35.0874mA
+  5.80    25.9999mA         17.9333mA            35.2180mA
+  5.90    26.0957mA         17.9990mA            35.3486mA
+  6.00    26.1915mA         18.0647mA            35.4793mA
+  6.10    26.2873mA         18.1303mA            35.6099mA
+  6.20    26.3831mA         18.1960mA            35.7406mA
+  6.30    26.4789mA         18.2616mA            35.8712mA
+  6.40    26.5747mA         18.3273mA            36.0018mA
+  6.50    26.6705mA         18.3929mA            36.1325mA
+  6.60    26.7663mA         18.4586mA            36.2631mA
+|  
+[Pullup] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+-3.30       60.9662mA       46.6308mA        87.0217mA    
+-3.20       60.7240mA       46.4472mA        86.7600mA    
+-3.10       60.2994mA       46.2636mA        85.3500mA    
+-3.00       59.0755mA       46.0800mA        83.1700mA    
+-2.90       57.3963mA       45.5300mA        80.5900mA    
+-2.80       55.4705mA       44.3800mA        77.7700mA    
+-2.70       53.3739mA       42.9200mA        74.8000mA    
+-2.60       51.1729mA       41.2800mA        71.7300mA    
+-2.50       48.8960mA       39.5320mA        68.6000mA    
+-2.40       46.5650mA       37.7130mA        65.4100mA    
+-2.30       44.2113mA       35.8570mA        62.2000mA    
+-2.20       41.8320mA       33.9950mA        58.9610mA    
+-2.10       39.4555mA       32.1310mA        55.7110mA    
+-2.00       37.1056mA       30.2880mA        52.4470mA    
+-1.90       34.7793mA       28.4710mA        49.1720mA    
+-1.80       32.5319mA       26.6850mA        45.8900mA    
+-1.70       30.3631mA       24.9360mA        42.6060mA    
+-1.60       28.2959mA       23.2280mA        39.3910mA    
+-1.50       26.3236mA       21.5600mA        36.3540mA    
+-1.40       24.4385mA       19.9360mA        33.5720mA    
+-1.30       22.6312mA       18.3560mA        31.0630mA    
+-1.20       20.8932mA       16.8240mA        28.8020mA    
+-1.10       19.2273mA       15.3490mA        26.8550mA    
+-1.00       17.6525mA       13.9360mA        25.6750mA    
+-0.90       16.2417mA       12.5950mA        24.4660mA    
+-0.80       14.9068mA       11.3600mA        21.3180mA    
+-0.70       13.2931mA       10.2971mA        18.9703mA    
+-0.60       11.6685mA       9.2483mA        16.9105mA    
+-0.50       9.9513mA       7.8709mA        14.6683mA    
+-0.40       7.9801mA       6.2914mA        11.8564mA    
+-0.30       5.9303mA       4.6622mA        8.8439mA    
+-0.20       3.9153mA       3.0657mA        5.8617mA    
+-0.10       1.9400mA       1.5124mA        2.9160mA    
+0.00       -6.9700nA       -2.5700nA        -86.5000nA    
+0.10       -1.8799mA       -1.4564mA        -2.8429mA    
+0.20       -3.6735mA       -2.8408mA        -5.5653mA    
+0.30       -5.3808mA       -4.1535mA        -8.1679mA    
+0.40       -7.0025mA       -5.3952mA        -10.6515mA    
+0.50       -8.5393mA       -6.5665mA        -13.0149mA    
+0.60       -9.9917mA       -7.6679mA        -15.2608mA    
+0.70       -11.3594mA       -8.6999mA        -17.3894mA    
+0.80       -12.6449mA       -9.6632mA        -19.4005mA    
+0.90       -13.8465mA       -10.5579mA        -21.2942mA    
+1.00       -14.9659mA       -11.3853mA        -23.0724mA    
+1.10       -16.0032mA       -12.1460mA        -24.7353mA    
+1.20       -16.9593mA       -12.8401mA        -26.2837mA    
+1.30       -17.8352mA       -13.4675mA        -27.7167mA    
+1.40       -18.6299mA       -14.0302mA        -29.0372mA    
+1.50       -19.3454mA       -14.5272mA        -30.2434mA    
+1.60       -19.9815mA       -14.9606mA        -31.3381mA    
+1.70       -20.5404mA       -15.3313mA        -32.3204mA    
+1.80       -21.0208mA       -15.7720mA        -33.1924mA    
+1.90       -21.6437mA       -16.0228mA        -34.3429mA    
+2.00       -21.9782mA       -16.2184mA        -35.0021mA    
+2.10       -22.2442mA       -16.3681mA        -35.5553mA    
+2.20       -22.4522mA       -16.4866mA        -36.0104mA    
+2.30       -22.6203mA       -16.5871mA        -36.3794mA    
+2.40       -22.7636mA       -16.6772mA        -36.6831mA    
+2.50       -22.8919mA       -16.7617mA        -36.9446mA    
+2.60       -23.0116mA       -16.8402mA        -37.1814mA    
+2.70       -23.1247mA       -16.9153mA        -37.4005mA    
+2.80       -23.2299mA       -16.9860mA        -37.6054mA    
+2.90       -23.3289mA       -17.0521mA        -37.7972mA    
+3.00       -23.4225mA       -17.1156mA        -37.9765mA    
+3.10       -23.5107mA       -17.1755mA        -38.1452mA    
+3.20       -23.5932mA       -17.2307mA        -38.3020mA    
+3.30       -23.6690mA       -17.2845mA        -38.4487mA    
+3.40       -23.7421mA       -17.3317mA        -38.5851mA    
+3.50       -23.8099mA       -17.3821mA        -38.7103mA    
+3.60       -23.8639mA       -17.4515mA        -38.8302mA    
+3.70       -23.9593mA       -17.5209mA        -38.9459mA    
+3.80       -24.0548mA       -17.5902mA        -39.0277mA    
+3.90       -24.1501mA       -17.6596mA        -39.1834mA    
+4.00       -24.2455mA       -17.7290mA        -39.3392mA    
+4.10       -24.3409mA       -17.7983mA        -39.4949mA    
+4.20       -24.4363mA       -17.8677mA        -39.6506mA    
+4.30       -24.5317mA       -17.9371mA        -39.8063mA    
+4.40       -24.6271mA       -18.0064mA        -39.9620mA    
+4.50       -24.7225mA       -18.0758mA        -40.1178mA    
+4.60       -24.8179mA       -18.1452mA        -40.2735mA    
+4.70       -24.9133mA       -18.2145mA        -40.4292mA    
+4.80       -25.0087mA       -18.2839mA        -40.5849mA    
+4.90       -25.1041mA       -18.3532mA        -40.7406mA    
+5.00       -25.1995mA       -18.4226mA        -40.8964mA    
+5.10       -25.2949mA       -18.4920mA        -41.0521mA    
+5.20       -25.3902mA       -18.5613mA        -41.2078mA    
+5.30       -25.4857mA       -18.6307mA        -41.3635mA    
+5.40       -25.5810mA       -18.7001mA        -41.5192mA    
+5.50       -25.6765mA       -18.7694mA        -41.6750mA    
+5.60       -25.7719mA       -18.8388mA        -41.8307mA    
+5.70       -25.8673mA       -18.9082mA        -41.9864mA    
+5.80       -25.9627mA       -18.9775mA        -42.1421mA    
+5.90       -26.0580mA       -19.0469mA        -42.2978mA    
+6.00       -26.1535mA       -19.1163mA        -42.4536mA    
+6.10       -26.2488mA       -19.1856mA        -42.6093mA    
+6.20       -26.3443mA       -19.2550mA        -42.7650mA    
+6.30       -26.4396mA       -19.3244mA        -42.9207mA    
+6.40       -26.5350mA       -19.3937mA        -43.0764mA    
+6.50       -26.6305mA       -19.4631mA        -43.2322mA    
+6.55       -26.6781mA       -19.4978mA        -43.3100mA    
+[GND_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    -0.9552A          -0.9302A             -0.9778A
+  -3.25    -0.9306A          -0.9058A             -0.9532A
+  -3.20    -0.9061A          -0.8814A             -0.9285A
+  -3.15    -0.8815A          -0.857A              -0.9039A
+  -3.10    -0.857A           -0.8327A             -0.8792A
+  -3.05    -0.8325A          -0.8083A             -0.8546A
+  -3.00    -0.808A           -0.784A              -0.83A
+  -2.95    -0.7836A          -0.7597A             -0.8054A
+  -2.90    -0.7591A          -0.7355A             -0.7808A
+  -2.85    -0.7347A          -0.7112A             -0.7563A
+  -2.80    -0.7103A          -0.6871A             -0.7317A
+  -2.75    -0.6859A          -0.6629A             -0.7072A
+  -2.70    -0.6616A          -0.6388A             -0.6827A
+  -2.65    -0.6373A          -0.6148A             -0.6582A
+  -2.60    -0.613A           -0.5908A             -0.6338A
+  -2.55    -0.5888A          -0.5668A             -0.6094A
+  -2.50    -0.5646A          -0.543A              -0.585A
+  -2.45    -0.5405A          -0.5192A             -0.5607A
+  -2.40    -0.5165A          -0.4955A             -0.5364A
+  -2.35    -0.4925A          -0.4719A             -0.5122A
+  -2.30    -0.4686A          -0.4484A             -0.488A
+  -2.25    -0.4448A          -0.425A              -0.4639A
+  -2.20    -0.421A           -0.4018A             -0.4398A
+  -2.15    -0.3975A          -0.3788A             -0.4159A
+  -2.10    -0.374A           -0.3561A             -0.3921A
+  -2.05    -0.3508A          -0.3336A             -0.3684A
+  -2.00    -0.3278A          -0.3115A             -0.3449A
+  -1.95    -0.3051A          -0.2898A             -0.3216A
+  -1.90    -0.2829A          -0.2688A             -0.2986A
+  -1.85    -0.2611A          -0.2485A             -0.276A
+  -1.80    -0.2402A          -0.2293A             -0.2541A
+  -1.75    -0.2203A          -0.2115A             -0.233A
+  -1.70    -0.2019A          -0.1953A             -0.2133A
+  -1.65    -0.1856A          -0.1809A             -0.1957A
+  -1.60    -0.1716A          -0.1681A             -0.1809A
+  -1.55    -0.1593A          -0.1563A             -0.1683A
+  -1.50    -0.148A           -0.1451A             -0.157A
+  -1.45    -0.1371A          -0.1342A             -0.146A
+  -1.40    -0.1266A          -0.1236A             -0.1353A
+  -1.35    -0.1161A          -0.1131A             -0.1248A
+  -1.30    -0.1059A          -0.1029A             -0.1145A
+  -1.25    -95.8525mA        -92.7685mA           -0.1044A
+  -1.20    -86.0775mA        -82.8695mA           -94.7415mA
+  -1.15    -76.6285mA        -73.2225mA           -85.5735mA
+  -1.10    -67.6045mA        -63.8875mA           -77.1175mA
+  -1.05    -59.1405mA        -54.9455mA           -69.5895mA
+  -1.00    -51.4145mA        -46.5095mA           -63.0585mA
+  -0.95    -44.6125mA        -38.7355mA           -57.1555mA
+  -0.90    -38.7695mA        -31.8215mA           -51.1065mA
+  -0.85    -33.4345mA        -25.8545mA           -44.5675mA
+  -0.80    -28.1565mA        -20.5265mA           -37.8185mA
+  -0.75    -22.9755mA        -15.7285mA           -31.1295mA
+  -0.70    -18.0095mA        -11.5805mA           -24.6635mA
+  -0.65    -13.3705mA        -8.0894mA            -18.5475mA
+  -0.60    -9.185mA          -5.219mA             -12.9245mA
+  -0.55    -5.6163mA         -2.9834mA            -7.9946mA
+  -0.50    -2.8703mA         -1.4348mA            -4.0643mA
+  -0.45    -1.1245mA         -0.5536mA            -1.5008mA
+  -0.40    -0.308mA          -0.1624mA            -0.3485mA
+  -0.35    -35.6uA           -20.3890uA           -16.0uA
+  -0.30    0.0A              0.0A                 0.0A
+  -0.25    0.0A              0.0A                 0.0A
+  -0.20    0.0A              0.0A                 0.0A
+  -0.15    0.0A              0.0A                 0.0A
+  -0.10    0.0A              0.0A                 0.0A
+  -0.05    0.0A              0.0A                 0.0A
+  0.00    0.0A              0.0A                 0.0A
+  6.60    0.0A              0.0A                 0.0A
+|  
+[POWER_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.25    0.1221A           0.1248A              0.1242A
+  -3.15    0.1200A           0.1232A              0.1212A
+  -3.05    0.1178A           0.1215A              0.1181A
+  -2.95    0.1153A           0.1196A              0.1148A
+  -2.85    0.1128A           0.1174A              0.1114A
+  -2.75    0.1100A           0.1151A              0.1078A
+  -2.65    0.1071A           0.1126A              0.1041A
+  -2.55    0.1039A           0.1098A              0.1001A
+  -2.45    0.1006A           0.1069A              95.9680mA
+  -2.35    97.0630mA         0.1037A              91.5590mA
+  -2.25    93.2670mA         0.1003A              86.8480mA
+  -2.15    89.1920mA         96.7010mA            81.7630mA
+  -2.05    84.8070mA         92.8600mA            76.2010mA
+  -1.95    80.0800mA         88.7860mA            70.0340mA
+  -1.85    74.9870mA         84.4790mA            63.1570mA
+  -1.75    69.5180mA         79.9450mA            55.5700mA
+  -1.65    63.6850mA         75.1950mA            47.4010mA
+  -1.55    57.5160mA         70.2440mA            38.8580mA
+  -1.45    51.0440mA         65.1120mA            30.1910mA
+  -1.35    44.3150mA         59.8210mA            21.8920mA
+  -1.25    37.3820mA         54.3940mA            15.5340mA
+  -1.15    30.3110mA         48.8520mA            11.4230mA
+  -1.05    23.2090mA         43.2090mA            6.9858mA
+  -0.95    16.3160mA         37.4680mA            3.1948mA
+  -0.85    10.2960mA         31.6320mA            0.8600mA
+  -0.75    6.1213mA          25.7150mA            0.1694mA
+  -0.65    3.1679mA          19.7630mA            65.5350uA
+  -0.55    1.1362mA          13.8830mA            37.1010uA
+  -0.45    0.2574mA          8.3464mA             19.4580uA
+  -0.35    73.3430uA         3.8624mA             3.1206uA
+  -0.25    33.6580uA         1.3608mA             -12.8040uA
+  -0.15    17.7650uA         0.3668mA             -28.1570uA
+  -0.05    5.8276uA          90.2420uA            -42.9420uA
+  0.00    0.1897uA          50.8660uA            -50.1210uA
+  0.05    -5.3380uA         31.9340uA            -57.1590uA
+  0.15    -16.0560uA        15.1110uA            -70.8070uA
+  0.25    -26.3450uA        5.7330uA             -83.8870uA
+  0.35    -36.2070uA        -2.2074uA            -96.3970uA
+  0.45    -45.6400uA        -9.6847uA            -0.1083mA
+  0.55    -54.6440uA        -16.8200uA           -0.1197mA
+  0.65    -63.2180uA        -23.6240uA           -0.1305mA
+  0.75    -71.3610uA        -30.0980uA           -0.1407mA
+  0.85    -79.0710uA        -36.2430uA           -0.1504mA
+  0.95    -86.3480uA        -42.0600uA           -0.1594mA
+  1.05    -93.1890uA        -47.5470uA           -0.1679mA
+  1.15    -99.5930uA        -52.7050uA           -0.1758mA
+  1.25    -0.1056mA         -57.5350uA           -0.1832mA
+  1.35    -0.1111mA         -62.0370uA           -0.1899mA
+  1.45    -0.1162mA         -66.2090uA           -0.1961mA
+  1.55    -0.1208mA         -70.0530uA           -0.2016mA
+  1.65    -0.1250mA         -73.5690uA           -0.2016mA
+  1.75    -0.1287mA         -76.7560uA           -0.2016mA
+  1.85    -0.1305mA         -79.6150uA           -0.2016mA
+  1.95    -0.1305mA         -82.1480uA           -0.2016mA
+  2.05    -0.1305mA         -83.2920uA           -0.2016mA
+  2.15    -0.1305mA         -83.2920uA           -0.2016mA
+  2.25    -0.1305mA         -83.2920uA           -0.2016mA
+  2.35    -0.1305mA         -83.2920uA           -0.2016mA
+  2.45    -0.1305mA         -83.2920uA           -0.2016mA
+  2.55    -0.1305mA         -83.2920uA           -0.2016mA
+  2.65    -0.1305mA         -83.2920uA           -0.2016mA
+  2.75    -0.1305mA         -83.2920uA           -0.2016mA
+  2.85    -0.1305mA         -83.2920uA           -0.2016mA
+  2.95    -0.1305mA         -83.2920uA           -0.2016mA
+  3.05    -0.1305mA         -83.2920uA           -0.2016mA
+  3.15    -0.1305mA         -83.2920uA           -0.2016mA
+  3.25    -0.1305mA         -83.2920uA           -0.2016mA
+  6.60    -0.1305mA         -83.292uA            -0.2016mA
+|  
+[Ramp]  
+| variable       typ                 min                 max 
+dV/dt_r  0.7026/0.4330n      0.4966/0.5731n      1.0018/0.3242n
+dV/dt_f  0.6827/0.4387n      0.4730/0.5599n      0.9168/0.3576n
+R_load = 50.0000
+|  
+[Rising Waveform] 
+R_fixture=       50.0000
+V_fixture=       3.3000
+V_fixture_min=   3.1400
+V_fixture_max=   3.4700
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              2.1621V           2.3517V              1.9420V
+0.1010nS          2.1621V           2.3517V              1.9420V
+0.2020nS          2.1621V           2.3517V              1.9420V
+0.3030nS          2.1621V           2.3517V              1.9420V
+0.4040nS          2.1621V           2.3517V              1.9420V
+0.5051nS          2.1622V           2.3517V              2.2421V
+0.6061nS          2.1615V           2.3517V              2.8060V
+0.7071nS          2.2762V           2.3517V              3.1342V
+0.8081nS          2.7361V           2.3522V              3.3164V
+0.9091nS          2.9561V           2.3515V              3.3898V
+1.0101nS          3.0907V           2.3704V              3.4244V
+1.1111nS          3.1772V           2.6051V              3.4432V
+1.2121nS          3.2242V           2.8360V              3.4539V
+1.3131nS          3.2509V           2.9413V              3.4602V
+1.4141nS          3.2670V           3.0020V              3.4639V
+1.5152nS          3.2775V           3.0439V              3.4662V
+1.6162nS          3.2845V           3.0714V              3.4676V
+1.7172nS          3.2892V           3.0897V              3.4685V
+1.8182nS          3.2924V           3.1025V              3.4690V
+1.9192nS          3.2946V           3.1117V              3.4694V
+2.0202nS          3.2961V           3.1186V              3.4696V
+2.1212nS          3.2972V           3.1237V              3.4697V
+2.2222nS          3.2980V           3.1276V              3.4698V
+2.3232nS          3.2986V           3.1305V              3.4699V
+2.4242nS          3.2989V           3.1327V              3.4699V
+2.5253nS          3.2992V           3.1344V              3.4699V
+2.6263nS          3.2994V           3.1356V              3.4699V
+2.7273nS          3.2996V           3.1366V              3.4699V
+2.8283nS          3.2997V           3.1373V              3.4699V
+2.9293nS          3.2998V           3.1379V              3.4700V
+3.0303nS          3.2998V           3.1383V              3.4699V
+3.1313nS          3.2999V           3.1387V              3.4700V
+3.2323nS          3.2999V           3.1390V              3.4699V
+3.3333nS          3.2999V           3.1392V              3.4700V
+3.4343nS          3.2999V           3.1393V              3.4699V
+3.5354nS          3.2999V           3.1395V              3.4700V
+3.6364nS          3.3000V           3.1396V              3.4699V
+3.7374nS          3.3000V           3.1397V              3.4700V
+3.8384nS          3.3000V           3.1397V              3.4700V
+3.9394nS          3.3000V           3.1398V              3.4700V
+4.0404nS          3.3000V           3.1398V              3.4700V
+4.1414nS          3.3000V           3.1399V              3.4700V
+4.2424nS          3.3000V           3.1399V              3.4700V
+4.3434nS          3.3000V           3.1399V              3.4700V
+4.4444nS          3.3000V           3.1400V              3.4700V
+4.5455nS          3.3000V           3.1400V              3.4700V
+4.6465nS          3.3000V           3.1399V              3.4700V
+4.7475nS          3.3000V           3.1400V              3.4700V
+4.8485nS          3.3000V           3.1400V              3.4700V
+4.9495nS          3.3000V           3.1400V              3.4700V
+5.0505nS          3.3000V           3.1400V              3.4700V
+5.1515nS          3.3000V           3.1400V              3.4699V
+5.2525nS          3.3000V           3.1400V              3.4700V
+5.3535nS          3.3000V           3.1400V              3.4700V
+5.4545nS          3.3000V           3.1400V              3.4700V
+5.5556nS          3.3000V           3.1400V              3.4699V
+5.6566nS          3.3000V           3.1400V              3.4700V
+5.7576nS          3.3000V           3.1400V              3.4700V
+5.8586nS          3.3000V           3.1400V              3.4700V
+5.9596nS          3.3000V           3.1400V              3.4699V
+6.0606nS          3.3000V           3.1400V              3.4700V
+6.1616nS          3.3000V           3.1400V              3.4700V
+6.2626nS          3.3000V           3.1400V              3.4700V
+6.3636nS          3.3000V           3.1400V              3.4699V
+6.4646nS          3.3000V           3.1400V              3.4700V
+6.5657nS          3.3000V           3.1400V              3.4700V
+6.6667nS          3.3000V           3.1400V              3.4700V
+6.7677nS          3.3000V           3.1400V              3.4699V
+6.8687nS          3.3000V           3.1400V              3.4700V
+6.9697nS          3.3000V           3.1400V              3.4700V
+7.0707nS          3.3000V           3.1400V              3.4700V
+7.1717nS          3.3000V           3.1400V              3.4700V
+7.2727nS          3.3000V           3.1400V              3.4700V
+7.3737nS          3.3000V           3.1400V              3.4700V
+7.4747nS          3.3000V           3.1400V              3.4700V
+7.5758nS          3.3000V           3.1400V              3.4700V
+7.6768nS          3.3000V           3.1400V              3.4700V
+7.7778nS          3.3000V           3.1400V              3.4700V
+7.8788nS          3.3000V           3.1400V              3.4700V
+7.9798nS          3.3000V           3.1400V              3.4699V
+8.0808nS          3.3000V           3.1400V              3.4700V
+8.1818nS          3.3000V           3.1400V              3.4700V
+8.2828nS          3.3000V           3.1400V              3.4700V
+8.3838nS          3.3000V           3.1400V              3.4700V
+8.4848nS          3.3000V           3.1400V              3.4700V
+8.5859nS          3.3000V           3.1400V              3.4700V
+8.6869nS          3.3000V           3.1400V              3.4700V
+8.7879nS          3.3000V           3.1400V              3.4700V
+8.8889nS          3.3000V           3.1400V              3.4700V
+8.9899nS          3.3000V           3.1400V              3.4700V
+9.0909nS          3.3000V           3.1400V              3.4700V
+9.1919nS          3.3000V           3.1400V              3.4700V
+9.2929nS          3.3000V           3.1400V              3.4700V
+9.3939nS          3.3000V           3.1400V              3.4700V
+9.4949nS          3.3000V           3.1400V              3.4700V
+9.5960nS          3.3000V           3.1400V              3.4700V
+9.6970nS          3.3000V           3.1400V              3.4700V
+9.7980nS          3.3000V           3.1400V              3.4700V
+9.8990nS          3.3000V           3.1400V              3.4700V
+10.0000nS         3.3000V           3.1400V              3.4700V
+|  
+[Rising Waveform] 
+R_fixture=       50.0000
+V_fixture=       0.0
+V_fixture_min=   0.0
+V_fixture_max=   0.0
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              1.2884uV          1.5543uV             1.3225uV
+0.1010nS          0.5355uV          0.8430uV             0.6254uV
+0.2020nS          -3.0614uV         0.1113uV             0.5701uV
+0.3030nS          0.6806uV          -1.9546uV            10.3860uV
+0.4040nS          3.2624uV          1.2769uV             -0.2118mV
+0.5051nS          32.7230uV         1.5286uV             -24.1640mV
+0.6061nS          -0.3955mV         2.8080uV             -9.9395mV
+0.7071nS          -15.7200mV        17.6660uV            0.1561V
+0.8081nS          -19.9850mV        99.9200uV            0.5397V
+0.9091nS          -0.4586mV         -0.2072mV            0.9226V
+1.0101nS          88.3420mV         -6.1838mV            1.2091V
+1.1111nS          0.2478V          -18.1000mV            1.3886V   
+1.2121nS          0.4471V          -16.0430mV            1.4951V   
+1.3131nS          0.6318V          -10.1180mV            1.5589V   
+1.4141nS          0.7749V          8.8815mV            1.5984V   
+1.5152nS          0.8766V          55.5920mV            1.6234V   
+1.6162nS          0.9465V          0.1340V            1.6394V   
+1.7172nS          0.9942V          0.2360V            1.6498V   
+1.8182nS          1.0272V          0.3461V            1.6566V   
+1.9192nS          1.0502V          0.4492V            1.6613V   
+2.0202nS          1.0667V          0.5367V            1.6638V   
+2.1212nS          1.0785V          0.6066V            1.6656V   
+2.2222nS          1.0871V          0.6605V            1.6667V   
+2.3232nS          1.0934V          0.7013V            1.6675V   
+2.4242nS          1.0979V          0.7318V            1.6680V   
+2.5253nS          1.1013V          0.7546V            1.6684V   
+2.6263nS          1.1038V          0.7716V            1.6687V   
+2.7273nS          1.1056V          0.7845V            1.6689V   
+2.8283nS          1.1069V          0.7942V            1.6691V   
+2.9293nS          1.1080V          0.8016V            1.6693V   
+3.0303nS          1.1087V          0.8073V            1.6693V   
+3.1313nS          1.1093V          0.8118V            1.6694V   
+3.2323nS          1.1097V          0.8152V            1.6695V   
+3.3333nS          1.1100V          0.8178V            1.6695V   
+3.4343nS          1.1103V          0.8199V            1.6695V   
+3.5354nS          1.1104V          0.8215V            1.6696V   
+3.6364nS          1.1105V          0.8228V            1.6695V   
+3.7374nS          1.1106V          0.8238V            1.6696V   
+3.8384nS          1.1107V          0.8246V            1.6696V   
+3.9394nS          1.1107V          0.8252V            1.6696V   
+4.0404nS          1.1108V          0.8257V            1.6696V   
+4.1414nS          1.1108V          0.8261V            1.6696V   
+4.2424nS          1.1108V          0.8265V            1.6696V   
+4.3434nS          1.1109V          0.8267V            1.6696V   
+4.4444nS          1.1109V          0.8269V            1.6696V   
+4.5455nS          1.1109V          0.8271V            1.6696V   
+4.6465nS          1.1109V          0.8272V            1.6696V   
+4.7475nS          1.1109V          0.8273V            1.6696V   
+4.8485nS          1.1109V          0.8274V            1.6696V   
+4.9495nS          1.1109V          0.8274V            1.6696V   
+5.0505nS          1.1109V          0.8276V            1.6696V   
+5.1515nS          1.1109V          0.8276V            1.6696V   
+5.2525nS          1.1109V          0.8276V            1.6696V   
+5.3535nS          1.1109V          0.8276V            1.6696V   
+5.4545nS          1.1109V          0.8276V            1.6696V   
+5.5556nS          1.1109V          0.8276V            1.6696V   
+5.6566nS          1.1109V          0.8276V            1.6696V   
+5.7576nS          1.1109V          0.8277V            1.6696V   
+5.8586nS          1.1109V          0.8277V            1.6696V   
+5.9596nS          1.1109V          0.8277V            1.6696V   
+6.0606nS          1.1109V          0.8277V            1.6696V   
+6.1616nS          1.1109V          0.8277V            1.6696V   
+6.2626nS          1.1109V          0.8277V            1.6696V   
+6.3636nS          1.1109V          0.8277V            1.6696V   
+6.4646nS          1.1109V          0.8277V            1.6696V   
+6.5657nS          1.1109V          0.8277V            1.6696V   
+6.6667nS          1.1110V          0.8277V            1.6696V   
+6.7677nS          1.1109V          0.8277V            1.6696V   
+6.8687nS          1.1109V          0.8277V            1.6696V   
+6.9697nS          1.1109V          0.8277V            1.6696V   
+7.0707nS          1.1110V          0.8277V            1.6696V   
+7.1717nS          1.1109V          0.8277V            1.6696V   
+7.2727nS          1.1110V          0.8277V            1.6696V   
+7.3737nS          1.1110V          0.8277V            1.6696V   
+7.4747nS          1.1110V          0.8277V            1.6696V   
+7.5758nS          1.1110V          0.8277V            1.6696V   
+7.6768nS          1.1110V          0.8277V            1.6696V   
+7.7778nS          1.1109V          0.8277V            1.6696V   
+7.8788nS          1.1110V          0.8277V            1.6696V   
+7.9798nS          1.1110V          0.8277V            1.6696V   
+8.0808nS          1.1110V          0.8277V            1.6696V   
+8.1818nS          1.1109V          0.8277V            1.6696V   
+8.2828nS          1.1110V          0.8277V            1.6696V   
+8.3838nS          1.1110V          0.8277V            1.6696V   
+8.4848nS          1.1110V          0.8277V            1.6696V   
+8.5859nS          1.1110V          0.8277V            1.6696V   
+8.6869nS          1.1110V          0.8277V            1.6696V   
+8.7879nS          1.1109V          0.8277V            1.6696V   
+8.8889nS          1.1109V          0.8277V            1.6696V   
+8.9899nS          1.1109V          0.8277V            1.6696V   
+9.0909nS          1.1109V          0.8277V            1.6696V   
+9.1919nS          1.1109V          0.8277V            1.6696V   
+9.2929nS          1.1109V          0.8277V            1.6696V   
+9.3939nS          1.1109V          0.8277V            1.6696V   
+9.4949nS          1.1109V          0.8277V            1.6696V   
+9.5960nS          1.1109V          0.8277V            1.6696V   
+9.6970nS          1.1110V          0.8277V            1.6696V   
+9.7980nS          1.1110V          0.8277V            1.6696V   
+9.8990nS          1.1110V          0.8277V            1.6696V   
+10.0000nS          1.1109V          0.8277V            1.6696V   
+[Falling Waveform] 
+R_fixture=       50.0000
+V_fixture=       0.0
+V_fixture_min=   0.0
+V_fixture_max=   0.0
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S          1.1109V          0.8277V            1.6696V   
+0.1010nS          1.1109V          0.8277V            1.6696V   
+0.2020nS          1.1109V          0.8277V            1.6696V   
+0.3030nS          1.1110V          0.8277V            1.6696V   
+0.4040nS          1.1110V          0.8277V            1.6696V   
+0.5051nS          1.1109V          0.8277V            1.6644V   
+0.6061nS          1.1110V          0.8277V            1.0431V   
+0.7071nS          1.1113V          0.8277V            0.4157V   
+0.8081nS          0.9851V          0.8277V            0.1612V   
+0.9091nS          0.5727V          0.8276V            77.0900mV   
+1.0101nS          0.2814V          0.8282V            40.8740mV   
+1.1111nS          0.1329V          0.8285V            22.9430mV   
+1.2121nS          73.6840mV         0.7997V              12.4510mV
+1.3131nS          43.0370mV         0.5895V              6.8313mV
+1.4141nS          26.7550mV         0.3604V              3.7992mV
+1.5152nS          17.0970mV         0.2116V              2.1510mV
+1.6162nS          11.1140mV         0.1248V              1.2529mV
+1.7172nS          7.2776mV          75.3210mV            0.7544mV
+1.8182nS          4.8176mV          47.2290mV            0.4826mV
+1.9192nS          3.1888mV          31.3570mV            0.3253mV
+2.0202nS          2.1519mV          21.8020mV            0.2392mV
+2.1212nS          1.4430mV          15.5850mV            0.1806mV
+2.2222nS          1.0065mV          11.3310mV            0.1485mV
+2.3232nS          0.6888mV          8.3187mV             0.1251mV
+2.4242nS          0.5069mV          6.1527mV             0.1108mV
+2.5253nS          0.3566mV          4.5704mV             0.1026mV
+2.6263nS          0.2717mV          3.4134mV             96.2470uV
+2.7273nS          0.1995mV          2.5569mV             87.3860uV
+2.8283nS          0.1853mV          1.9272mV             82.9260uV
+2.9293nS          0.1277mV          1.4565mV             68.6140uV
+3.0303nS          0.1252mV          1.1098mV             60.2230uV
+3.1313nS          89.5590uV         0.8485mV             49.7170uV
+3.2323nS          94.4160uV         0.6561mV             56.7570uV
+3.3333nS          49.7470uV         0.5093mV             54.1530uV
+3.4343nS          57.0870uV         0.3863mV             49.3370uV
+3.5354nS          52.4280uV         0.3073mV             42.7020uV
+3.6364nS          77.0030uV         0.2451mV             40.7070uV
+3.7374nS          46.1550uV         0.1875mV             33.9890uV
+3.8384nS          63.3650uV         0.1621mV             34.0740uV
+3.9394nS          31.9750uV         0.1378mV             27.5110uV
+4.0404nS          46.0820uV         0.1176mV             33.5240uV
+4.1414nS          14.0450uV         0.1002mV             26.4520uV
+4.2424nS          30.8440uV         91.6770uV            22.6270uV
+4.3434nS          23.9580uV         76.4830uV            15.2880uV
+4.4444nS          37.9550uV         66.7720uV            22.2140uV
+4.5455nS          20.1420uV         54.3060uV            29.8260uV
+4.6465nS          38.7320uV         46.2710uV            31.2670uV
+4.7475nS          7.9010uV          34.7060uV            23.8310uV
+4.8485nS          28.9680uV         27.4260uV            23.1060uV
+4.9495nS          3.7079uV          16.8370uV            10.7150uV
+5.0505nS          4.6522uV          25.8205uV            14.7445uV
+5.1515nS          12.5270uV         19.1810uV            11.7510uV
+5.2525nS          10.5410uV         17.0160uV            5.4213uV
+5.3535nS          42.1190uV         11.8180uV            8.5329uV
+5.4545nS          11.4930uV         19.2340uV            13.1240uV
+5.5556nS          38.3480uV         27.0890uV            18.1120uV
+5.6566nS          1.7742uV          38.8120uV            11.7850uV
+5.7576nS          22.6050uV         31.4050uV            7.1004uV
+5.8586nS          -3.9145uV         19.9240uV            -7.3305uV
+5.9596nS          13.3160uV         7.4008uV             0.4354uV
+6.0606nS          7.3534uV          -0.9538uV            7.7540uV
+6.1616nS          33.4920uV         -8.2614uV            8.9420uV
+6.2626nS          9.8852uV          1.6769uV             5.0332uV
+6.3636nS          25.5040uV         16.3790uV            2.4944uV
+6.4646nS          -2.5946uV         32.5920uV            -5.3283uV
+6.5657nS          4.1073uV          30.8730uV            6.9637uV
+6.6667nS          2.1062uV          21.8930uV            7.5789uV
+6.7677nS          10.6270uV         5.1201uV             6.5788uV
+6.8687nS          -19.4020uV        -8.0928uV            0.9709uV
+6.9697nS          3.6023uV          5.3486uV             -0.4159uV
+7.0707nS          -20.2800uV        10.3380uV            -4.1503uV
+7.1717nS          19.4790uV         23.0950uV            -4.9697uV
+7.2727nS          -10.7860uV        7.5118uV             -8.6698uV
+7.3737nS          21.7550uV         9.0311uV             -7.4803uV
+7.4747nS          12.4390uV         -5.6908uV            -10.4050uV
+7.5758nS          18.3510uV         -4.5175uV            -8.2164uV
+7.6768nS          -7.8114uV         1.1510uV             -10.8020uV
+7.7778nS          2.0275uV          12.3600uV            -1.5528uV
+7.8788nS          -76.1190nV        12.0690uV            6.6952uV
+7.9798nS          4.0097uV          8.9861uV             10.0890uV
+8.0808nS          0.4972uV          -1.8875uV            0.6130uV
+8.1818nS          0.5840uV          -11.3150uV           -1.5820uV
+8.2828nS          -12.7280uV        -15.9390uV           -8.5048uV
+8.3838nS          3.4867uV          -5.2058uV            -1.9719uV
+8.4848nS          -4.5739uV         2.6217uV             0.5424uV
+8.5859nS          4.1249uV          2.6585uV             4.0878uV
+8.6869nS          -12.0140uV        -0.6919uV            6.4732uV
+8.7879nS          -3.8915uV         -10.4690uV           7.0541uV
+8.8889nS          -10.5260uV        -22.7580uV           2.8919uV
+8.9899nS          2.5661uV          -25.3070uV           -3.3709uV
+9.0909nS          -2.9240uV         -11.4390uV           -5.9996uV
+9.1919nS          -3.0241uV         -1.1643uV            0.8082uV
+9.2929nS          -7.9366uV         5.3328uV             0.4492uV
+9.3939nS          -2.3621uV         8.5118uV             5.8039uV
+9.4949nS          -9.1146uV         -8.6006uV            -2.4704uV
+9.5960nS          -3.7574uV         -19.3450uV           -0.8494uV
+9.6970nS          -16.6030uV        -15.4900uV           -2.2380uV
+9.7980nS          -2.4824uV         -3.6242uV            4.0030uV
+9.8990nS          -18.6820uV        15.5490uV            1.5950uV
+10.0000nS         -1.0707uV         8.4164uV             -6.6712uV
+|  
+[Falling Waveform] 
+R_fixture=       50.0000
+V_fixture=       3.3000
+V_fixture_min=   3.1400
+V_fixture_max=   3.4700
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              3.3000V           3.1400V              3.4700V
+0.1010nS          3.3000V           3.1400V              3.4700V
+0.2020nS          3.3000V           3.1400V              3.4700V
+0.3030nS          3.3000V           3.1400V              3.4700V
+0.4040nS          3.3000V           3.1400V              3.4700V
+0.5051nS          3.3000V           3.1400V              3.4758V
+0.6061nS          3.3001V           3.1400V              3.4570V
+0.7071nS          3.2983V           3.1400V              3.0951V
+0.8081nS          3.3299V           3.1400V              2.7403V
+0.9091nS          3.2987V           3.1398V              2.4747V
+1.0101nS          3.1080V           3.1409V              2.2935V
+1.1111nS          2.8866V           3.1388V              2.1742V
+1.2121nS          2.6919V           3.1507V              2.0966V
+1.3131nS          2.5414V           3.1748V              2.0453V
+1.4141nS          2.4321V           3.1565V              2.0112V
+1.5152nS          2.3547V           3.0752V              1.9884V
+1.6162nS          2.3001V           2.9642V              1.9732V
+1.7172nS          2.2616V           2.8458V              1.9629V
+1.8182nS          2.2341V           2.7389V              1.9561V
+1.9192nS          2.2145V           2.6506V              1.9515V
+2.0202nS          2.2003V           2.5809V              1.9484V
+2.1212nS          2.1900V           2.5272V              1.9463V
+2.2222nS          2.1826V           2.4862V              1.9450V
+2.3232nS          2.1771V           2.4551V              1.9440V
+2.4242nS          2.1731V           2.4314V              1.9434V
+2.5253nS          2.1702V           2.4134V              1.9430V
+2.6263nS          2.1681V           2.3996V              1.9427V
+2.7273nS          2.1665V           2.3890V              1.9425V
+2.8283nS          2.1654V           2.3808V              1.9424V
+2.9293nS          2.1646V           2.3745V              1.9423V
+3.0303nS          2.1639V           2.3696V              1.9422V
+3.1313nS          2.1635V           2.3658V              1.9422V
+3.2323nS          2.1631V           2.3628V              1.9421V
+3.3333nS          2.1629V           2.3604V              1.9421V
+3.4343nS          2.1627V           2.3586V              1.9421V
+3.5354nS          2.1626V           2.3572V              1.9420V
+3.6364nS          2.1625V           2.3560V              1.9421V
+3.7374nS          2.1624V           2.3551V              1.9421V
+3.8384nS          2.1623V           2.3544V              1.9421V
+3.9394nS          2.1623V           2.3539V              1.9420V
+4.0404nS          2.1622V           2.3534V              1.9420V
+4.1414nS          2.1622V           2.3531V              1.9420V
+4.2424nS          2.1622V           2.3528V              1.9420V
+4.3434nS          2.1622V           2.3526V              1.9420V
+4.4444nS          2.1622V           2.3524V              1.9420V
+4.5455nS          2.1622V           2.3523V              1.9420V
+4.6465nS          2.1622V           2.3522V              1.9420V
+4.7475nS          2.1622V           2.3521V              1.9420V
+4.8485nS          2.1622V           2.3520V              1.9420V
+4.9495nS          2.1622V           2.3519V              1.9420V
+5.0505nS          2.1622V           2.3519V              1.9420V
+5.1515nS          2.1622V           2.3518V              1.9420V
+5.2525nS          2.1622V           2.3518V              1.9420V
+5.3535nS          2.1622V           2.3518V              1.9420V
+5.4545nS          2.1622V           2.3518V              1.9420V
+5.5556nS          2.1622V           2.3518V              1.9420V
+5.6566nS          2.1622V           2.3517V              1.9420V
+5.7576nS          2.1621V           2.3517V              1.9420V
+5.8586nS          2.1621V           2.3517V              1.9420V
+5.9596nS          2.1621V           2.3517V              1.9420V
+6.0606nS          2.1621V           2.3517V              1.9420V
+6.1616nS          2.1621V           2.3517V              1.9420V
+6.2626nS          2.1621V           2.3517V              1.9420V
+6.3636nS          2.1621V           2.3517V              1.9420V
+6.4646nS          2.1621V           2.3517V              1.9420V
+6.5657nS          2.1621V           2.3517V              1.9420V
+6.6667nS          2.1622V           2.3517V              1.9420V
+6.7677nS          2.1621V           2.3517V              1.9420V
+6.8687nS          2.1621V           2.3517V              1.9420V
+6.9697nS          2.1621V           2.3517V              1.9420V
+7.0707nS          2.1621V           2.3517V              1.9420V
+7.1717nS          2.1621V           2.3517V              1.9420V
+7.2727nS          2.1621V           2.3517V              1.9420V
+7.3737nS          2.1621V           2.3517V              1.9420V
+7.4747nS          2.1621V           2.3517V              1.9420V
+7.5758nS          2.1621V           2.3517V              1.9420V
+7.6768nS          2.1621V           2.3517V              1.9420V
+7.7778nS          2.1621V           2.3517V              1.9420V
+7.8788nS          2.1621V           2.3517V              1.9420V
+7.9798nS          2.1621V           2.3517V              1.9420V
+8.0808nS          2.1621V           2.3517V              1.9420V
+8.1818nS          2.1621V           2.3517V              1.9420V
+8.2828nS          2.1621V           2.3517V              1.9420V
+8.3838nS          2.1621V           2.3517V              1.9420V
+8.4848nS          2.1621V           2.3517V              1.9420V
+8.5859nS          2.1621V           2.3517V              1.9420V
+8.6869nS          2.1621V           2.3517V              1.9420V
+8.7879nS          2.1621V           2.3517V              1.9420V
+8.8889nS          2.1621V           2.3517V              1.9420V
+8.9899nS          2.1621V           2.3517V              1.9420V
+9.0909nS          2.1621V           2.3517V              1.9420V
+9.1919nS          2.1621V           2.3517V              1.9420V
+9.2929nS          2.1621V           2.3517V              1.9420V
+9.3939nS          2.1621V           2.3517V              1.9420V
+9.4949nS          2.1621V           2.3517V              1.9420V
+9.5960nS          2.1621V           2.3517V              1.9420V
+9.6970nS          2.1621V           2.3517V              1.9420V
+9.7980nS          2.1621V           2.3517V              1.9420V
+9.8990nS          2.1621V           2.3517V              1.9420V
+10.0000nS         2.1621V           2.3517V              1.9420V
+|  
+| End [Model] lvt330s040haaaaaaaio
+|************************************************************************
+[Model]           lvt330s160aaaaaaaaou
+Model_type        Output
+Polarity          Non-Inverting
+Enable            Active-Low
+Vmeas =           1.500000V
+Cref =            0.0F
+Rref =            1.0000M
+Vref =            0.0V
+C_comp            4.2000pF          3.8000pF             7.5000pF
+|  
+|  
+[Temperature Range]     25.0000           0.1050k              -40.0000
+[Voltage Range]         3.3000V           3.1400V              3.4700V
+[Pulldown] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    -46.0510mA        -33.7410mA           -59.5510mA
+  -3.20    -46.0510mA        -33.7410mA           -59.5510mA
+  -3.10    -46.0510mA        -33.7410mA           -59.5510mA
+  -3.00    -46.0510mA        -33.7410mA           -59.5510mA
+  -2.90    -46.0510mA        -33.7410mA           -59.5510mA
+  -2.80    -46.0510mA        -33.7410mA           -59.5510mA
+  -2.70    -46.0510mA        -33.7410mA           -59.5510mA
+  -2.60    -46.0510mA        -33.7410mA           -59.5510mA
+  -2.50    -46.0510mA        -33.7410mA           -59.5510mA
+  -2.40    -46.0510mA        -33.7410mA           -59.5510mA
+  -2.30    -46.0510mA        -33.7410mA           -59.5510mA
+  -2.20    -46.0510mA        -33.7410mA           -59.5510mA
+  -2.10    -46.0510mA        -33.7410mA           -59.5510mA
+  -2.00    -46.0510mA        -33.7410mA           -59.5510mA
+  -1.90    -46.0510mA        -33.7410mA           -59.5510mA
+  -1.80    -46.0510mA        -33.7410mA           -59.5510mA
+  -1.70    -46.0510mA        -33.7410mA           -59.5510mA
+  -1.60    -46.0510mA        -33.7410mA           -59.5510mA
+  -1.50    -46.0510mA        -33.7410mA           -59.5510mA
+  -1.40    -46.0510mA        -33.7410mA           -59.5510mA
+  -1.30    -46.0510mA        -33.7410mA           -59.5510mA
+  -1.20    -46.0510mA        -33.7410mA           -59.5510mA
+  -1.10    -46.0510mA        -33.7410mA           -59.5510mA
+  -1.00    -46.0510mA        -33.7410mA           -57.7460mA
+  -0.90    -45.1960mA        -33.7410mA           -53.3800mA
+  -0.80    -42.7900mA        -33.0880mA           -50.7690mA
+  -0.70    -40.7010mA        -32.1190mA           -48.9510mA
+  -0.60    -38.5892mA        -30.1763mA           -47.3570mA
+  -0.50    -35.7989mA        -27.1490mA           -45.2332mA
+  -0.40    -30.5530mA        -22.5448mA           -39.2561mA
+  -0.30    -23.3101mA        -17.0730mA           -30.0082mA
+  -0.20    -15.6753mA        -11.4360mA           -20.2124mA
+  -0.10    -7.9044mA         -5.7449mA            -10.2109mA
+  0.00    9.1810nA          6.6370nA             14.6880nA
+  0.10    7.8212mA          5.6449mA             10.1501mA
+  0.20    15.3310mA         11.0300mA            19.9541mA
+  0.30    22.5240mA         16.1530mA            29.4071mA
+  0.40    29.3980mA         21.0130mA            38.5000mA
+  0.50    35.9480mA         25.6080mA            47.2270mA
+  0.60    42.1700mA         29.9370mA            55.5800mA
+  0.70    48.0590mA         33.9980mA            63.5490mA
+  0.80    53.6080mA         37.7880mA            71.1220mA
+  0.90    58.8090mA         41.3050mA            78.2850mA
+  1.00    63.6510mA         44.5440mA            85.0150mA
+  1.10    68.1160mA         47.4970mA            91.2820mA
+  1.20    72.1780mA         50.1540mA            97.0390mA
+  1.30    75.8000mA         52.4980mA            0.1022A
+  1.40    78.9390mA         54.5150mA            0.1067A
+  1.50    81.5710mA         56.2010mA            0.1106A
+  1.60    83.7180mA         57.5820mA            0.1137A
+  1.70    85.4430mA         58.7040mA            0.1161A
+  1.80    86.8340mA         59.6220mA            0.1181A
+  1.90    87.9720mA         60.3850mA            0.1196A
+  2.00    88.9210mA         61.0310mA            0.1209A
+  2.10    89.7270mA         61.5880mA            0.1220A
+  2.20    90.4240mA         62.0750mA            0.1229A
+  2.30    91.0370mA         62.5080mA            0.1237A
+  2.40    91.5820mA         62.8970mA            0.1244A
+  2.50    92.0740mA         63.2500mA            0.1250A
+  2.60    92.5210mA         63.5730mA            0.1256A
+  2.70    92.9309mA         63.8720mA            0.1261A
+  2.80    93.3099mA         64.1499mA            0.1266A
+  2.90    93.6629mA         64.4089mA            0.1270A
+  3.00    93.9929mA         64.6529mA            0.1274A
+  3.10    94.3029mA         64.8829mA            0.1278A
+  3.20    94.5958mA         65.1008mA            0.1281A
+  3.30    94.8758mA         65.3076mA            0.1285A
+  3.40    95.1436mA         65.5013mA            0.1288A
+  3.50    95.4017mA         65.6576mA            0.1291A
+  3.60    95.6462mA         65.9236mA            0.1294A
+  3.70    95.8369mA         66.2546mA            0.1298A
+  3.80    96.2034mA         67.0655mA            0.1301A
+  3.90    96.5733mA         69.0584mA            0.1303A
+  4.00    97.3652mA         73.2123mA            0.1309A
+  4.10    99.2509mA         79.1820mA            0.1314A
+  4.20    0.1022A           85.9597mA            0.1322A
+  4.30    0.1063A           93.0914mA            0.1344A
+  4.40    0.1126A           0.1004A              0.1384A
+  4.50    0.1206A           0.1078A              0.1435A
+  4.60    0.1294A           0.1153A              0.1489A
+  4.70    0.1385A           0.1229A              0.1551A
+  4.80    0.1479A           0.1307A              0.1648A
+  4.90    0.1573A           0.1386A              0.1760A
+  5.00    0.1669A           0.1467A              0.1878A
+  5.10    0.1765A           0.1550A              0.1999A
+  5.20    0.1863A           0.1634A              0.2120A
+  5.30    0.1961A           0.1719A              0.2241A
+  5.40    0.2062A           0.1805A              0.2362A
+  5.50    0.2163A           0.1892A              0.2482A
+  5.60    0.2265A           0.1980A              0.2603A
+  5.70    0.2369A           0.2068A              0.2726A
+  5.80    0.2473A           0.2158A              0.2851A
+  5.90    0.2579A           0.2248A              0.2978A
+  6.00    0.2687A           0.2339A              0.3108A
+  6.10    0.2796A           0.2431A              0.3240A
+  6.20    0.2907A           0.2524A              0.3374A
+  6.30    0.3021A           0.2618A              0.3511A
+  6.40    0.3136A           0.2714A              0.3652A
+  6.50    0.3254A           0.2811A              0.3794A
+  6.60    0.3374A           0.2909A              0.3940A
+|  
+[Pullup] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    0.3688A           0.3085A              0.4482A
+  -3.20    0.3595A           0.3039A              0.4356A
+  -3.10    0.3495A           0.2972A              0.4227A
+  -3.00    0.3390A           0.2892A              0.4094A
+  -2.90    0.3282A           0.2805A              0.3959A
+  -2.80    0.3171A           0.2712A              0.3822A
+  -2.70    0.3056A           0.2615A              0.3683A
+  -2.60    0.2939A           0.2514A              0.3543A
+  -2.50    0.2819A           0.2409A              0.3400A
+  -2.40    0.2697A           0.2303A              0.3256A
+  -2.30    0.2573A           0.2194A              0.3110A
+  -2.20    0.2447A           0.2084A              0.2962A
+  -2.10    0.2318A           0.1972A              0.2811A
+  -2.00    0.2189A           0.1859A              0.2659A
+  -1.90    0.2058A           0.1745A              0.2504A
+  -1.80    0.1927A           0.1631A              0.2346A
+  -1.70    0.1795A           0.1517A              0.2186A
+  -1.60    0.1662A           0.1402A              0.2025A
+  -1.50    0.1528A           0.1288A              0.1863A
+  -1.40    0.1394A           0.1175A              0.1702A
+  -1.30    0.1260A           0.1062A              0.1543A
+  -1.20    0.1126A           94.9202mA            0.1391A
+  -1.10    99.3436mA         83.7786mA            0.1252A
+  -1.00    86.4581mA         72.7899mA            0.1110A
+  -0.90    74.6466mA         62.0952mA            97.2911mA
+  -0.80    64.2979mA         52.0534mA            84.6162mA
+  -0.70    54.8762mA         43.3265mA            72.7261mA
+  -0.60    46.1133mA         35.9755mA            61.5078mA
+  -0.50    37.8734mA         29.3476mA            50.1553mA
+  -0.40    29.8849mA         23.1046mA            40.2866mA
+  -0.30    22.2622mA         17.0802mA            30.1199mA
+  -0.20    14.7337mA         11.2591mA            20.0045mA
+  -0.10    7.3149mA          5.5671mA             9.9673mA
+  0.00    -27.6800nA        -12.5600nA           -0.2990uA
+  0.10    -7.1350mA         -5.3932mA            -9.7862mA
+  0.20    -14.0071mA        -10.5601mA           -19.2690mA
+  0.30    -20.6131mA        -15.4991mA           -28.4448mA
+  0.40    -26.9531mA        -20.2101mA           -37.3096mA
+  0.50    -33.0231mA        -24.6920mA           -45.8605mA
+  0.60    -38.8211mA        -28.9440mA           -54.0924mA
+  0.70    -44.3460mA        -32.9660mA           -62.0013mA
+  0.80    -49.5950mA        -36.7560mA           -69.5842mA
+  0.90    -54.5660mA        -40.3130mA           -76.8361mA
+  1.00    -59.2570mA        -43.6380mA           -83.7531mA
+  1.10    -63.6650mA        -46.7280mA           -90.3311mA
+  1.20    -67.7890mA        -49.5840mA           -96.5660mA
+  1.30    -71.6270mA        -52.2040mA           -0.1025A
+  1.40    -75.1760mA        -54.5890mA           -0.1080A
+  1.50    -78.4330mA        -56.7370mA           -0.1132A
+  1.60    -81.3980mA        -58.6480mA           -0.1180A
+  1.70    -84.0680mA        -60.3220mA           -0.1224A
+  1.80    -86.4420mA        -61.7600mA           -0.1265A
+  1.90    -88.5180mA        -62.9650mA           -0.1302A
+  2.00    -90.2990mA        -63.9430mA           -0.1335A
+  2.10    -91.7860mA        -64.7110mA           -0.1365A
+  2.20    -92.9940mA        -65.3040mA           -0.1391A
+  2.30    -93.9530mA        -65.7740mA           -0.1412A
+  2.40    -94.7160mA        -66.1750mA           -0.1431A
+  2.50    -95.3540mA        -66.5370mA           -0.1446A
+  2.60    -95.9200mA        -66.8780mA           -0.1458A
+  2.70    -96.4460mA        -67.2020mA           -0.1469A
+  2.80    -96.9450mA        -67.5150mA           -0.1478A
+  2.90    -97.4230mA        -67.8180mA           -0.1487A
+  3.00    -97.8850mA        -68.1109mA           -0.1495A
+  3.10    -98.3320mA        -68.3969mA           -0.1504A
+  3.20    -98.7659mA        -68.6739mA           -0.1511A
+  3.30    -99.1879mA        -68.9436mA           -0.1519A
+  3.40    -99.5979mA        -69.2026mA           -0.1526A
+  3.50    -99.9963mA        -69.3920mA           -0.1533A
+  3.60    -0.1004A          -69.3920mA           -0.1540A
+  3.70    -0.1005A          -69.3920mA           -0.1547A
+  3.80    -0.1005A          -69.3920mA           -0.1553A
+  3.90    -0.1005A          -69.3920mA           -0.1554A
+  4.00    -0.1005A          -69.3920mA           -0.1554A
+  4.10    -0.1005A          -69.3920mA           -0.1554A
+  4.20    -0.1005A          -69.3920mA           -0.1554A
+  4.30    -0.1005A          -69.3920mA           -0.1554A
+  4.40    -0.1005A          -69.3920mA           -0.1554A
+  4.50    -0.1005A          -69.3920mA           -0.1554A
+  4.60    -0.1005A          -69.3920mA           -0.1554A
+  4.70    -0.1005A          -69.3920mA           -0.1554A
+  4.80    -0.1005A          -69.3920mA           -0.1554A
+  4.90    -0.1005A          -69.3920mA           -0.1554A
+  5.00    -0.1005A          -69.3920mA           -0.1554A
+  5.10    -0.1005A          -69.3920mA           -0.1554A
+  5.20    -0.1005A          -69.3920mA           -0.1554A
+  5.30    -0.1005A          -69.3920mA           -0.1554A
+  5.40    -0.1005A          -69.3920mA           -0.1554A
+  5.50    -0.1005A          -69.3920mA           -0.1554A
+  5.60    -0.1005A          -69.3920mA           -0.1554A
+  5.70    -0.1005A          -69.3920mA           -0.1554A
+  5.80    -0.1005A          -69.3920mA           -0.1554A
+  5.90    -0.1005A          -69.3920mA           -0.1554A
+  6.00    -0.1005A          -69.3920mA           -0.1554A
+  6.10    -0.1005A          -69.3920mA           -0.1554A
+  6.20    -0.1005A          -69.3920mA           -0.1554A
+  6.30    -0.1005A          -69.3920mA           -0.1554A
+  6.40    -0.1005A          -69.3920mA           -0.1554A
+  6.50    -0.1005A          -69.3920mA           -0.1554A
+  6.55    -0.1005A          -69.3920mA           -0.1554A
+|  
+[GND_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.30    -0.9553A          -0.9303A             -0.978A
+  -3.25    -0.9307A          -0.9059A             -0.9534A
+  -3.20    -0.9062A          -0.8815A             -0.9287A
+  -3.15    -0.8816A          -0.8571A             -0.9041A
+  -3.10    -0.8571A          -0.8328A             -0.8794A
+  -3.05    -0.8326A          -0.8084A             -0.8548A
+  -3.00    -0.8081A          -0.7841A             -0.8302A
+  -2.95    -0.7837A          -0.7598A             -0.8056A
+  -2.90    -0.7592A          -0.7356A             -0.781A
+  -2.85    -0.7348A          -0.7113A             -0.7565A
+  -2.80    -0.7104A          -0.6872A             -0.7319A
+  -2.75    -0.686A           -0.663A              -0.7074A
+  -2.70    -0.6617A          -0.6389A             -0.6829A
+  -2.65    -0.6374A          -0.6149A             -0.6584A
+  -2.60    -0.6131A          -0.5909A             -0.634A
+  -2.55    -0.5889A          -0.5669A             -0.6096A
+  -2.50    -0.5647A          -0.5431A             -0.5852A
+  -2.45    -0.5406A          -0.5193A             -0.5609A
+  -2.40    -0.5166A          -0.4956A             -0.5366A
+  -2.35    -0.4926A          -0.472A              -0.5124A
+  -2.30    -0.4687A          -0.4485A             -0.4882A
+  -2.25    -0.4449A          -0.4251A             -0.4641A
+  -2.20    -0.4211A          -0.4019A             -0.44A
+  -2.15    -0.3976A          -0.3789A             -0.4161A
+  -2.10    -0.3741A          -0.3562A             -0.3923A
+  -2.05    -0.3509A          -0.3337A             -0.3686A
+  -2.00    -0.3279A          -0.3116A             -0.3451A
+  -1.95    -0.3052A          -0.2899A             -0.3218A
+  -1.90    -0.283A           -0.2689A             -0.2988A
+  -1.85    -0.2612A          -0.2486A             -0.2762A
+  -1.80    -0.2402A          -0.2294A             -0.2543A
+  -1.75    -0.2204A          -0.2116A             -0.2332A
+  -1.70    -0.202A           -0.1954A             -0.2135A
+  -1.65    -0.1857A          -0.181A              -0.1959A
+  -1.60    -0.1717A          -0.1682A             -0.181A
+  -1.55    -0.1594A          -0.1563A             -0.1685A
+  -1.50    -0.1481A          -0.1452A             -0.1571A
+  -1.45    -0.1372A          -0.1343A             -0.1462A
+  -1.40    -0.1266A          -0.1237A             -0.1355A
+  -1.35    -0.1162A          -0.1132A             -0.125A
+  -1.30    -0.106A           -0.1029A             -0.1146A
+  -1.25    -95.9599mA        -92.8329mA           -0.1046A
+  -1.20    -86.1849mA        -82.9339mA           -94.9069mA
+  -1.15    -76.7349mA        -73.2869mA           -85.7379mA
+  -1.10    -67.7089mA        -63.9519mA           -77.2789mA
+  -1.05    -59.2439mA        -55.0099mA           -69.7479mA
+  -1.00    -51.5159mA        -46.5729mA           -63.2139mA
+  -0.95    -44.7119mA        -38.7979mA           -57.3089mA
+  -0.90    -38.8659mA        -31.8819mA           -51.2599mA
+  -0.85    -33.5299mA        -25.9129mA           -44.7209mA
+  -0.80    -28.2499mA        -20.5839mA           -37.9699mA
+  -0.75    -23.0669mA        -15.7839mA           -31.2789mA
+  -0.70    -18.0989mA        -11.6329mA           -24.8089mA
+  -0.65    -13.4569mA        -8.1389mA            -18.6889mA
+  -0.60    -9.2667mA         -5.2646mA            -13.0589mA
+  -0.55    -5.6915mA         -3.0244mA            -8.1194mA
+  -0.50    -2.937mA          -1.4709mA            -4.1747mA
+  -0.45    -1.1814mA         -0.5866mA            -1.592mA
+  -0.40    -0.3589mA         -0.1961mA            -0.4238mA
+  -0.35    -88.3674uA        -58.3595uA           -88.5118uA
+  -0.30    -18.8304uA        -15.9765uA           -16.7268uA
+  -0.25    -3.5316uA         -4.0546uA            -3.0027uA
+  -0.20    -0.6045uA         -0.9665uA            -0.4941uA
+  -0.15    -99.742nA         -0.2204uA            -76.537nA
+  -0.10    -17.537nA         -48.631nA            -14.0860nA
+  -0.05    -3.547nA          -9.5380nA            -3.817nA
+  0.00    0.0A              0.0A                 0.0A
+  6.60    0.0A              0.0A                 0.0A
+|  
+[POWER_clamp] 
+|Voltage   I(typ)              I(min)              I(max)
+|  
+  -3.25    0.6648mA          0.7494mA             0.5971mA
+  -3.15    0.5464mA          0.6392mA             0.4620mA
+  -3.05    0.4320mA          0.5325mA             0.3346mA
+  -2.95    0.3223mA          0.4288mA             0.2203mA
+  -2.85    0.2202mA          0.3288mA             0.1294mA
+  -2.75    0.1318mA          0.2341mA             72.8320uA
+  -2.65    67.1940uA         0.1484mA             47.8300uA
+  -2.55    33.3840uA         79.2130uA            38.1430uA
+  -2.45    21.1020uA         36.2270uA            33.4230uA
+  -2.35    16.7350uA         18.9540uA            30.1320uA
+  -2.25    14.6020uA         13.5630uA            27.2570uA
+  -2.15    13.0530uA         11.4700uA            24.5650uA
+  -2.05    11.6730uA         10.2220uA            22.0130uA
+  -1.95    10.3790uA         9.1903uA             19.5970uA
+  -1.85    9.1554uA          8.2406uA             17.3220uA
+  -1.75    8.0024uA          7.3472uA             15.1930uA
+  -1.65    6.9220uA          6.5055uA             13.2180uA
+  -1.55    5.9168uA          5.7151uA             11.4030uA
+  -1.45    4.9897uA          4.9762uA             9.7538uA
+  -1.35    4.1435uA          4.2896uA             8.2775uA
+  -1.25    3.3813uA          3.6558uA             6.9794uA
+  -1.15    2.7058uA          3.0755uA             5.8656uA
+  -1.05    2.1197uA          2.5496uA             4.9436uA
+  -0.95    1.6260uA          2.0788uA             4.2185uA
+  -0.85    1.2282uA          1.6639uA             3.6568uA
+  -0.75    0.9321uA          1.3059uA             3.6568uA
+  -0.65    0.7406uA          1.0064uA             3.6568uA
+  -0.55    0.6334uA          0.7687uA             3.6568uA
+  -0.45    0.5657uA          0.5976uA             1.9769uA
+  -0.35    0.5657uA          0.4934uA             1.5352uA
+  -0.25    0.5657uA          0.4388uA             1.2603uA
+  -0.15    0.5657uA          0.4063uA             1.0262uA
+  -0.05    0.2497uA          0.3931uA             0.8243uA
+  0.00    0.1905uA          0.3931uA             0.7347uA
+  0.05    0.1661uA          0.3931uA             0.6522uA
+  0.15    0.1377uA          0.3931uA             0.5077uA
+  0.25    0.1149uA          0.2673uA             0.3882uA
+  0.35    95.5840nA         94.4790nA            0.2911uA
+  0.45    79.2300nA         72.9410nA            0.2139uA
+  0.55    65.5240nA         63.7780nA            0.1539uA
+  0.65    54.1200nA         56.2440nA            0.1084uA
+  0.75    44.6720nA         49.6060nA            74.7270nA
+  0.85    36.8450nA         43.7060nA            50.5340nA
+  0.95    30.3210nA         38.4180nA            33.5490nA
+  1.05    24.8050nA         33.6240nA            21.8000nA
+  1.15    20.0360nA         29.2180nA            13.6290nA
+  1.25    15.7920nA         25.1030nA            7.7259nA
+  1.35    11.8920nA         21.1950nA            3.1291nA
+  1.45    8.2000nA          17.4270nA            -0.8025nA
+  1.55    4.6215nA          13.7460nA            -4.4469nA
+  1.65    1.0974nA          10.1160nA            -7.9944nA
+  1.75    -2.4045nA         6.5107nA             -11.5260nA
+  1.85    -5.8986nA         2.9177nA             -15.0700nA
+  1.95    -9.3903nA         -0.6705nA            -18.6430nA
+  2.05    -12.8810nA        -4.2566nA            -22.2600nA
+  2.15    -16.3730nA        -7.8413nA            -25.9390nA
+  2.25    -19.8660nA        -11.4260nA           -29.7010nA
+  2.35    -23.3620nA        -15.0100nA           -33.5700nA
+  2.45    -26.8630nA        -18.5940nA           -37.5740nA
+  2.55    -30.3710nA        -22.1800nA           -41.7450nA
+  2.65    -33.8890nA        -25.7670nA           -46.1170nA
+  2.75    -37.4190nA        -29.3570nA           -50.7240nA
+  2.85    -40.9640nA        -32.9520nA           -55.6060nA
+  2.95    -44.5300nA        -36.5540nA           -60.8020nA
+  3.05    -48.1210nA        -40.1670nA           -66.3570nA
+  3.15    -51.7470nA        -43.7980nA           -72.4990nA
+  3.25    -55.4690nA        -47.4690nA           -97.5860nA
+  6.60    -57.5580nA        -49.34nA             -0.2325uA
+|  
+[Ramp]  
+| variable       typ                 min                 max 
+dV/dt_r  1.4966/0.2592n      1.2936/0.4087n      1.7021/0.1678n
+dV/dt_f  1.5290/0.2281n      1.3043/0.3741n      1.7112/0.1501n
+R_load = 50.0000
+|  
+[Rising Waveform] 
+R_fixture=       50.0000
+V_fixture=       3.3000
+V_fixture_min=   3.1400
+V_fixture_max=   3.4700
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              0.7516V           0.9661V              0.6180V
+0.1010nS          0.7516V           0.9661V              0.6180V
+0.2020nS          0.7516V           0.9661V              0.6180V
+0.3030nS          0.7516V           0.9661V              0.6180V
+0.4040nS          0.7516V           0.9661V              0.6171V
+0.5051nS          0.7517V           0.9661V              0.7829V
+0.6061nS          0.7505V           0.9661V              2.0255V
+0.7071nS          0.7950V           0.9661V              2.8797V
+0.8081nS          1.7861V           0.9664V              3.3462V
+0.9091nS          2.4193V           0.9655V              3.4176V
+1.0101nS          2.8512V           0.9681V              3.4439V
+1.1111nS          3.1357V           1.3754V              3.4564V
+1.2121nS          3.2249V           2.1421V              3.4627V
+1.3131nS          3.2565V           2.5293V              3.4661V
+1.4141nS          3.2737V           2.7345V              3.4678V
+1.5152nS          3.2838V           2.8969V              3.4688V
+1.6162nS          3.2896V           3.0120V              3.4693V
+1.7172nS          3.2934V           3.0632V              3.4696V
+1.8182nS          3.2957V           3.0894V              3.4697V
+1.9192nS          3.2972V           3.1045V              3.4698V
+2.0202nS          3.2981V           3.1151V              3.4699V
+2.1212nS          3.2987V           3.1221V              3.4699V
+2.2222nS          3.2991V           3.1274V              3.4699V
+2.3232nS          3.2994V           3.1308V              3.4699V
+2.4242nS          3.2996V           3.1334V              3.4700V
+2.5253nS          3.2997V           3.1352V              3.4700V
+2.6263nS          3.2998V           3.1365V              3.4700V
+2.7273nS          3.2998V           3.1374V              3.4700V
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+5.0505nS          3.3000V           3.1400V              3.4700V
+5.1515nS          3.3000V           3.1400V              3.4700V
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+8.8889nS          3.3000V           3.1400V              3.4700V
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+9.0909nS          3.3000V           3.1400V              3.4700V
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+9.3939nS          3.3000V           3.1400V              3.4700V
+9.4949nS          3.3000V           3.1400V              3.4700V
+9.5960nS          3.3000V           3.1400V              3.4700V
+9.6970nS          3.3000V           3.1400V              3.4700V
+9.7980nS          3.3000V           3.1400V              3.4700V
+9.8990nS          3.3000V           3.1400V              3.4700V
+10.0000nS         3.3000V           3.1400V              3.4700V
+|  
+[Rising Waveform] 
+R_fixture=       50.0000
+V_fixture=       0.0
+V_fixture_min=   0.0
+V_fixture_max=   0.0
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              0.4849uV          0.6538uV             0.4584uV
+0.1010nS          -91.8400nV        63.2160nV            -25.7920nV
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+0.3030nS          -0.1263uV         -1.9171uV            9.8177uV
+0.4040nS          2.2148uV          0.3884uV             -0.7508mV
+0.5051nS          17.9080uV         0.4320uV             -54.9180mV
+0.6061nS          -0.9283mV         2.0154uV             -38.8140mV
+0.7071nS          -36.0310mV        19.4020uV            0.5590V
+0.8081nS          -59.6090mV        49.7370uV            1.7463V
+0.9091nS          -7.5013mV         -0.5918mV            2.5098V
+1.0101nS          0.3035V           -13.7970mV           2.7118V
+1.1111nS          0.8765V           -46.7140mV           2.7764V
+1.2121nS          1.5353V           -51.2590mV           2.8047V
+1.3131nS          2.0287V           -34.8250mV           2.8192V
+1.4141nS          2.2720V           25.7290mV            2.8271V
+1.5152nS          2.3732V           0.1849V              2.8315V
+1.6162nS          2.4197V           0.4573V              2.8339V
+1.7172nS          2.4473V           0.8065V              2.8353V
+1.8182nS          2.4633V           1.1645V              2.8360V
+1.9192nS          2.4738V           1.4818V              2.8364V
+2.0202nS          2.4810V           1.7269V              2.8366V
+2.1212nS          2.4853V           1.8846V              2.8368V
+2.2222nS          2.4883V           1.9770V              2.8368V
+2.3232nS          2.4902V           2.0335V              2.8369V
+2.4242nS          2.4916V           2.0698V              2.8369V
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+2.8283nS          2.4937V           2.1316V              2.8369V
+2.9293nS          2.4938V           2.1374V              2.8370V
+3.0303nS          2.4940V           2.1420V              2.8369V
+3.1313nS          2.4940V           2.1455V              2.8370V
+3.2323nS          2.4942V           2.1480V              2.8369V
+3.3333nS          2.4941V           2.1499V              2.8370V
+3.4343nS          2.4942V           2.1514V              2.8369V
+3.5354nS          2.4942V           2.1525V              2.8370V
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+3.7374nS          2.4942V           2.1539V              2.8370V
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+3.9394nS          2.4942V           2.1548V              2.8370V
+4.0404nS          2.4943V           2.1551V              2.8369V
+4.1414nS          2.4942V           2.1553V              2.8370V
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+4.3434nS          2.4942V           2.1556V              2.8370V
+4.4444nS          2.4943V           2.1557V              2.8369V
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+4.6465nS          2.4943V           2.1558V              2.8369V
+4.7475nS          2.4942V           2.1558V              2.8370V
+4.8485nS          2.4943V           2.1559V              2.8369V
+4.9495nS          2.4942V           2.1559V              2.8370V
+5.0505nS          2.4942V           2.1559V              2.8369V
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+9.8990nS          2.4943V           2.1560V              2.8370V
+10.0000nS         2.4943V           2.1560V              2.8369V
+|  
+[Falling Waveform] 
+R_fixture=       50.0000
+V_fixture=       0.0
+V_fixture_min=   0.0
+V_fixture_max=   0.0
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              2.4943V           2.1560V              2.8370V
+0.1010nS          2.4943V           2.1560V              2.8370V
+0.2020nS          2.4943V           2.1560V              2.8370V
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+0.7071nS          2.4905V           2.1560V              0.3637V
+0.8081nS          2.4067V           2.1560V              67.8100mV
+0.9091nS          1.4125V           2.1561V              29.4150mV
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+1.2121nS          43.6680mV         2.1382V              3.8422mV
+1.3131nS          26.1960mV         1.7150V              1.8945mV
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+1.9192nS          1.5559mV          28.7760mV            93.0170uV
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+8.9899nS          2.9239uV          9.1095uV             0.1500uV
+9.0909nS          2.8023uV          6.8319uV             7.0838uV
+9.1919nS          8.4026uV          3.9617uV             5.4861uV
+9.2929nS          4.3812uV          7.2141uV             -1.7852uV
+9.3939nS          2.8463uV          -53.3950nV           -0.4309uV
+9.4949nS          0.5257uV          12.7920uV            -1.2755uV
+9.5960nS          6.2361uV          11.5200uV            6.5424uV
+9.6970nS          8.1020uV          10.1450uV            2.3600uV
+9.7980nS          11.5310uV         9.4795uV             0.8669uV
+9.8990nS          9.9990uV          13.4000uV            1.3956uV
+10.0000nS         9.1292uV          5.3100uV             7.4741uV
+|  
+[Falling Waveform] 
+R_fixture=       50.0000
+V_fixture=       3.3000
+V_fixture_min=   3.1400
+V_fixture_max=   3.4700
+|time     V(typ)              V(min)              V(max)
+|  
+0.0S              3.3000V           3.1400V              3.4700V
+0.1010nS          3.3000V           3.1400V              3.4700V
+0.2020nS          3.3000V           3.1400V              3.4700V
+0.3030nS          3.3000V           3.1400V              3.4700V
+0.4040nS          3.3000V           3.1400V              3.4709V
+0.5051nS          3.3000V           3.1400V              3.4873V
+0.6061nS          3.3010V           3.1400V              3.3893V
+0.7071nS          3.2951V           3.1400V              2.0959V
+0.8081nS          3.3780V           3.1400V              1.0643V
+0.9091nS          3.2704V           3.1400V              0.7316V
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+|  
+| End [Model] lvt330s160aaaaaaaaou
+|************************************************************************
+| End [Component]
+[End]
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.alt b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.alt
new file mode 100644
index 0000000..46f0e3d
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.alt
@@ -0,0 +1,71 @@
+NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
+NOTE All Rights Reserved *
+NOTE DATE CREATED: Tue Aug 17 06:21:09 2021 *
+NOTE DESIGN NAME: RAM2GS *
+NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100 *
+NOTE PIN ASSIGNMENTS *
+NOTE PINS RCLK : 63 : in *
+NOTE PINS nFWE : 15 : in *
+NOTE PINS nCRAS : 17 : in *
+NOTE PINS nCCAS : 9 : in *
+NOTE PINS Din[0] : 3 : in *
+NOTE PINS Din[1] : 96 : in *
+NOTE PINS Din[2] : 88 : in *
+NOTE PINS Din[3] : 97 : in *
+NOTE PINS Din[4] : 99 : in *
+NOTE PINS Din[5] : 98 : in *
+NOTE PINS Din[6] : 2 : in *
+NOTE PINS Din[7] : 1 : in *
+NOTE PINS CROW[0] : 10 : in *
+NOTE PINS CROW[1] : 16 : in *
+NOTE PINS MAin[0] : 14 : in *
+NOTE PINS MAin[1] : 12 : in *
+NOTE PINS MAin[2] : 13 : in *
+NOTE PINS MAin[3] : 21 : in *
+NOTE PINS MAin[4] : 20 : in *
+NOTE PINS MAin[5] : 19 : in *
+NOTE PINS MAin[6] : 24 : in *
+NOTE PINS MAin[7] : 18 : in *
+NOTE PINS MAin[8] : 25 : in *
+NOTE PINS MAin[9] : 32 : in *
+NOTE PINS PHI2 : 8 : in *
+NOTE PINS RDQML : 48 : out *
+NOTE PINS RDQMH : 51 : out *
+NOTE PINS nRCAS : 52 : out *
+NOTE PINS nRRAS : 54 : out *
+NOTE PINS nRWE : 49 : out *
+NOTE PINS RCKE : 53 : out *
+NOTE PINS nRCS : 57 : out *
+NOTE PINS RA[0] : 66 : out *
+NOTE PINS RA[1] : 67 : out *
+NOTE PINS RA[2] : 69 : out *
+NOTE PINS RA[3] : 71 : out *
+NOTE PINS RA[4] : 74 : out *
+NOTE PINS RA[5] : 70 : out *
+NOTE PINS RA[6] : 68 : out *
+NOTE PINS RA[7] : 75 : out *
+NOTE PINS RA[8] : 65 : out *
+NOTE PINS RA[9] : 62 : out *
+NOTE PINS RA[10] : 64 : out *
+NOTE PINS RA[11] : 59 : out *
+NOTE PINS RBA[0] : 58 : out *
+NOTE PINS RBA[1] : 60 : out *
+NOTE PINS LED : 34 : out *
+NOTE PINS Dout[0] : 76 : out *
+NOTE PINS Dout[1] : 86 : out *
+NOTE PINS Dout[2] : 87 : out *
+NOTE PINS Dout[3] : 85 : out *
+NOTE PINS Dout[4] : 83 : out *
+NOTE PINS Dout[5] : 84 : out *
+NOTE PINS Dout[6] : 78 : out *
+NOTE PINS Dout[7] : 82 : out *
+NOTE PINS RD[0] : 36 : inout *
+NOTE PINS RD[1] : 37 : inout *
+NOTE PINS RD[2] : 38 : inout *
+NOTE PINS RD[3] : 39 : inout *
+NOTE PINS RD[4] : 40 : inout *
+NOTE PINS RD[5] : 41 : inout *
+NOTE PINS RD[6] : 42 : inout *
+NOTE PINS RD[7] : 43 : inout *
+NOTE CONFIGURATION MODE: NONE *
+NOTE COMPRESSION: on *
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.arearep b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.arearep
new file mode 100644
index 0000000..e5894f8
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.arearep
@@ -0,0 +1,22 @@
+----------------------------------------------------------------------
+Report for cell RAM2GS.TECH
+Register bits:  119 of 877 (13.569%)
+I/O cells:      63
+                                  Cell usage:
+                               cell     count   Res Usage(%)
+                                 BB         8          100.0
+                              CCU2D        10          100.0
+                                EFB         1          100.0
+                            FD1P3AX        30          100.0
+                            FD1P3AY         4          100.0
+                            FD1P3IX         3          100.0
+                            FD1S3AX        64          100.0
+                            FD1S3IX        14          100.0
+                            FD1S3JX         4          100.0
+                                GSR         1          100.0
+                                 IB        25          100.0
+                                INV         3          100.0
+                               LUT4       236          100.0
+                                 OB        30          100.0
+                              PFUMX        16          100.0
+                              TOTAL       449
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.bgn b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.bgn
new file mode 100644
index 0000000..86c3161
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.bgn
@@ -0,0 +1,86 @@
+BITGEN: Bitstream Generator Diamond (64-bit) 3.12.0.240.2
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 17 06:21:07 2021
+
+
+Command: bitgen -g RamCfg:Reset -path C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC -w -jedec -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+
+Loading design for application Bitgen from file RAM2GS_LCMXO2_640HC_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+
+Running DRC.
+DRC detected 0 errors and 0 warnings.
+Reading Preference File from RAM2GS_LCMXO2_640HC_impl1.prf.
+
+Preference Summary:
++---------------------------------+---------------------------------+
+|  Preference                     |  Current Setting                |
++---------------------------------+---------------------------------+
+|                         RamCfg  |                        Reset**  |
++---------------------------------+---------------------------------+
+|                     MCCLK_FREQ  |                         2.08**  |
++---------------------------------+---------------------------------+
+|                  CONFIG_SECURE  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                          INBUF  |                           ON**  |
++---------------------------------+---------------------------------+
+|                      JTAG_PORT  |                       ENABLE**  |
++---------------------------------+---------------------------------+
+|                       SDM_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                 SLAVE_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                MASTER_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                       I2C_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|        MUX_CONFIGURATION_PORTS  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  CONFIGURATION  |                          CFG**  |
++---------------------------------+---------------------------------+
+|                COMPRESS_CONFIG  |                           ON**  |
++---------------------------------+---------------------------------+
+|                        MY_ASSP  |                          OFF**  |
++---------------------------------+---------------------------------+
+|               ONE_TIME_PROGRAM  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                 ENABLE_TRANSFR  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  SHAREDEBRINIT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|            BACKGROUND_RECONFIG  |                          OFF**  |
++---------------------------------+---------------------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+
+Creating bit map...
+ 
+Bitstream Status: Final           Version 1.95.
+ 
+Saving bit stream in "RAM2GS_LCMXO2_640HC_impl1.jed".
+ 
+===========
+UFM Summary.
+===========
+UFM Size:        191 Pages (128*191 Bits).
+UFM Utilization: General Purpose Flash Memory.
+ 
+Available General Purpose Flash Memory:  191 Pages (Page 0 to Page 190).
+Initialized UFM Pages:                     0 Page.
+ 
+Total CPU Time: 1 secs 
+Total REAL Time: 2 secs 
+Peak Memory Usage: 245 MB
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.bit b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.bit
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HcmV?d00001

diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.pad b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.pad
new file mode 100644
index 0000000..36624e7
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.pad
@@ -0,0 +1,273 @@
+PAD Specification File
+***************************
+
+PART TYPE:        LCMXO2-640HC
+Performance Grade:      4
+PACKAGE:          TQFP100
+Package Status:                     Final          Version 1.39
+
+Tue Aug 17 06:20:57 2021
+
+Pinout by Port Name:
++-----------+----------+--------------+-------+-----------+-----------+------------------------------------------------------------+
+| Port Name | Pin/Bank | Buffer Type  | Site  | PG Enable | BC Enable | Properties                                                 |
++-----------+----------+--------------+-------+-----------+-----------+------------------------------------------------------------+
+| CROW[0]   | 10/3     | LVTTL33_IN   | PL3D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| CROW[1]   | 16/3     | LVTTL33_IN   | PL6A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[0]    | 3/3      | LVTTL33_IN   | PL2C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[1]    | 96/0     | LVTTL33_IN   | PT6D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[2]    | 88/0     | LVTTL33_IN   | PT9A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[3]    | 97/0     | LVTTL33_IN   | PT6C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[4]    | 99/0     | LVTTL33_IN   | PT6A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[5]    | 98/0     | LVTTL33_IN   | PT6B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[6]    | 2/3      | LVTTL33_IN   | PL2B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[7]    | 1/3      | LVTTL33_IN   | PL2A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Dout[0]   | 76/0     | LVTTL33_OUT  | PT11D |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[1]   | 86/0     | LVTTL33_OUT  | PT9C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[2]   | 87/0     | LVTTL33_OUT  | PT9B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[3]   | 85/0     | LVTTL33_OUT  | PT9D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[4]   | 83/0     | LVTTL33_OUT  | PT10B |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[5]   | 84/0     | LVTTL33_OUT  | PT10A |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[6]   | 78/0     | LVTTL33_OUT  | PT11A |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[7]   | 82/0     | LVTTL33_OUT  | PT10C |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| LED       | 34/2     | LVTTL33_OUT  | PB6C  |           |           | DRIVE:16mA SLEW:SLOW                                       |
+| MAin[0]   | 14/3     | LVTTL33_IN   | PL5C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[1]   | 12/3     | LVTTL33_IN   | PL5A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[2]   | 13/3     | LVTTL33_IN   | PL5B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[3]   | 21/3     | LVTTL33_IN   | PL7B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[4]   | 20/3     | LVTTL33_IN   | PL7A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[5]   | 19/3     | LVTTL33_IN   | PL6D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[6]   | 24/3     | LVTTL33_IN   | PL7C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[7]   | 18/3     | LVTTL33_IN   | PL6C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[8]   | 25/3     | LVTTL33_IN   | PL7D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[9]   | 32/2     | LVTTL33_IN   | PB6B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| PHI2      | 8/3      | LVTTL33_IN   | PL3B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[0]     | 66/1     | LVTTL33_OUT  | PR3D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[10]    | 64/1     | LVTTL33_OUT  | PR5B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[11]    | 59/1     | LVTTL33_OUT  | PR6B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[1]     | 67/1     | LVTTL33_OUT  | PR3C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[2]     | 69/1     | LVTTL33_OUT  | PR3A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[3]     | 71/1     | LVTTL33_OUT  | PR2C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[4]     | 74/1     | LVTTL33_OUT  | PR2B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[5]     | 70/1     | LVTTL33_OUT  | PR2D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[6]     | 68/1     | LVTTL33_OUT  | PR3B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[7]     | 75/1     | LVTTL33_OUT  | PR2A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[8]     | 65/1     | LVTTL33_OUT  | PR5A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[9]     | 62/1     | LVTTL33_OUT  | PR5D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RBA[0]    | 58/1     | LVTTL33_OUT  | PR6C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RBA[1]    | 60/1     | LVTTL33_OUT  | PR6A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RCKE      | 53/1     | LVTTL33_OUT  | PR7B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RCLK      | 63/1     | LVTTL33_IN   | PR5C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RDQMH     | 51/1     | LVTTL33_OUT  | PR7D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RDQML     | 48/2     | LVTTL33_OUT  | PB14C |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RD[0]     | 36/2     | LVTTL33_BIDI | PB10A |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[1]     | 37/2     | LVTTL33_BIDI | PB10B |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[2]     | 38/2     | LVTTL33_BIDI | PB10C |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[3]     | 39/2     | LVTTL33_BIDI | PB10D |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[4]     | 40/2     | LVTTL33_BIDI | PB12A |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[5]     | 41/2     | LVTTL33_BIDI | PB12B |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[6]     | 42/2     | LVTTL33_BIDI | PB12C |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[7]     | 43/2     | LVTTL33_BIDI | PB12D |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| nCCAS     | 9/3      | LVTTL33_IN   | PL3C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| nCRAS     | 17/3     | LVTTL33_IN   | PL6B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| nFWE      | 15/3     | LVTTL33_IN   | PL5D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| nRCAS     | 52/1     | LVTTL33_OUT  | PR7C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nRCS      | 57/1     | LVTTL33_OUT  | PR6D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nRRAS     | 54/1     | LVTTL33_OUT  | PR7A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nRWE      | 49/2     | LVTTL33_OUT  | PB14D |           |           | DRIVE:4mA SLEW:SLOW                                        |
++-----------+----------+--------------+-------+-----------+-----------+------------------------------------------------------------+
+
+Vccio by Bank:
++------+-------+
+| Bank | Vccio |
++------+-------+
+| 0    | 3.3V  |
+| 1    | 3.3V  |
+| 2    | 3.3V  |
+| 3    | 3.3V  |
++------+-------+
+
+Vref by Bank:
++------+-----+-----------------+---------+
+| Vref | Pin | Bank # / Vref # | Load(s) |
++------+-----+-----------------+---------+
++------+-----+-----------------+---------+
+
+Pinout by Pin Number:
++----------+-----------------------+------------+--------------+-------+---------------+-----------+-----------+
+| Pin/Bank | Pin Info              | Preference | Buffer Type  | Site  | Dual Function | PG Enable | BC Enable |
++----------+-----------------------+------------+--------------+-------+---------------+-----------+-----------+
+| 1/3      | Din[7]                | LOCATED    | LVTTL33_IN   | PL2A  |               |           |           |
+| 2/3      | Din[6]                | LOCATED    | LVTTL33_IN   | PL2B  |               |           |           |
+| 3/3      | Din[0]                | LOCATED    | LVTTL33_IN   | PL2C  | PCLKT3_2      |           |           |
+| 4/3      |     unused, PULL:DOWN |            |              | PL2D  | PCLKC3_2      |           |           |
+| 7/3      |     unused, PULL:DOWN |            |              | PL3A  |               |           |           |
+| 8/3      | PHI2                  | LOCATED    | LVTTL33_IN   | PL3B  |               |           |           |
+| 9/3      | nCCAS                 | LOCATED    | LVTTL33_IN   | PL3C  |               |           |           |
+| 10/3     | CROW[0]               | LOCATED    | LVTTL33_IN   | PL3D  |               |           |           |
+| 12/3     | MAin[1]               | LOCATED    | LVTTL33_IN   | PL5A  | PCLKT3_1      |           |           |
+| 13/3     | MAin[2]               | LOCATED    | LVTTL33_IN   | PL5B  | PCLKC3_1      |           |           |
+| 14/3     | MAin[0]               | LOCATED    | LVTTL33_IN   | PL5C  |               |           |           |
+| 15/3     | nFWE                  | LOCATED    | LVTTL33_IN   | PL5D  |               |           |           |
+| 16/3     | CROW[1]               | LOCATED    | LVTTL33_IN   | PL6A  |               |           |           |
+| 17/3     | nCRAS                 | LOCATED    | LVTTL33_IN   | PL6B  |               |           |           |
+| 18/3     | MAin[7]               | LOCATED    | LVTTL33_IN   | PL6C  |               |           |           |
+| 19/3     | MAin[5]               | LOCATED    | LVTTL33_IN   | PL6D  |               |           |           |
+| 20/3     | MAin[4]               | LOCATED    | LVTTL33_IN   | PL7A  | PCLKT3_0      |           |           |
+| 21/3     | MAin[3]               | LOCATED    | LVTTL33_IN   | PL7B  | PCLKC3_0      |           |           |
+| 24/3     | MAin[6]               | LOCATED    | LVTTL33_IN   | PL7C  |               |           |           |
+| 25/3     | MAin[8]               | LOCATED    | LVTTL33_IN   | PL7D  |               |           |           |
+| 27/2     |     unused, PULL:DOWN |            |              | PB4A  | CSSPIN        |           |           |
+| 28/2     |     unused, PULL:DOWN |            |              | PB4B  |               |           |           |
+| 29/2     |     unused, PULL:DOWN |            |              | PB4C  |               |           |           |
+| 30/2     |     unused, PULL:DOWN |            |              | PB4D  |               |           |           |
+| 31/2     |     unused, PULL:DOWN |            |              | PB6A  | MCLK/CCLK     |           |           |
+| 32/2     | MAin[9]               | LOCATED    | LVTTL33_IN   | PB6B  | SO/SPISO      |           |           |
+| 34/2     | LED                   | LOCATED    | LVTTL33_OUT  | PB6C  | PCLKT2_0      |           |           |
+| 35/2     |     unused, PULL:DOWN |            |              | PB6D  | PCLKC2_0      |           |           |
+| 36/2     | RD[0]                 | LOCATED    | LVTTL33_BIDI | PB10A |               |           |           |
+| 37/2     | RD[1]                 | LOCATED    | LVTTL33_BIDI | PB10B |               |           |           |
+| 38/2     | RD[2]                 | LOCATED    | LVTTL33_BIDI | PB10C | PCLKT2_1      |           |           |
+| 39/2     | RD[3]                 | LOCATED    | LVTTL33_BIDI | PB10D | PCLKC2_1      |           |           |
+| 40/2     | RD[4]                 | LOCATED    | LVTTL33_BIDI | PB12A |               |           |           |
+| 41/2     | RD[5]                 | LOCATED    | LVTTL33_BIDI | PB12B |               |           |           |
+| 42/2     | RD[6]                 | LOCATED    | LVTTL33_BIDI | PB12C |               |           |           |
+| 43/2     | RD[7]                 | LOCATED    | LVTTL33_BIDI | PB12D |               |           |           |
+| 45/2     |     unused, PULL:DOWN |            |              | PB14A |               |           |           |
+| 47/2     |     unused, PULL:DOWN |            |              | PB14B |               |           |           |
+| 48/2     | RDQML                 | LOCATED    | LVTTL33_OUT  | PB14C | SN            |           |           |
+| 49/2     | nRWE                  | LOCATED    | LVTTL33_OUT  | PB14D | SI/SISPI      |           |           |
+| 51/1     | RDQMH                 | LOCATED    | LVTTL33_OUT  | PR7D  |               |           |           |
+| 52/1     | nRCAS                 | LOCATED    | LVTTL33_OUT  | PR7C  |               |           |           |
+| 53/1     | RCKE                  | LOCATED    | LVTTL33_OUT  | PR7B  |               |           |           |
+| 54/1     | nRRAS                 | LOCATED    | LVTTL33_OUT  | PR7A  |               |           |           |
+| 57/1     | nRCS                  | LOCATED    | LVTTL33_OUT  | PR6D  |               |           |           |
+| 58/1     | RBA[0]                | LOCATED    | LVTTL33_OUT  | PR6C  |               |           |           |
+| 59/1     | RA[11]                | LOCATED    | LVTTL33_OUT  | PR6B  |               |           |           |
+| 60/1     | RBA[1]                | LOCATED    | LVTTL33_OUT  | PR6A  |               |           |           |
+| 62/1     | RA[9]                 | LOCATED    | LVTTL33_OUT  | PR5D  | PCLKC1_0      |           |           |
+| 63/1     | RCLK                  | LOCATED    | LVTTL33_IN   | PR5C  | PCLKT1_0      |           |           |
+| 64/1     | RA[10]                | LOCATED    | LVTTL33_OUT  | PR5B  |               |           |           |
+| 65/1     | RA[8]                 | LOCATED    | LVTTL33_OUT  | PR5A  |               |           |           |
+| 66/1     | RA[0]                 | LOCATED    | LVTTL33_OUT  | PR3D  |               |           |           |
+| 67/1     | RA[1]                 | LOCATED    | LVTTL33_OUT  | PR3C  |               |           |           |
+| 68/1     | RA[6]                 | LOCATED    | LVTTL33_OUT  | PR3B  |               |           |           |
+| 69/1     | RA[2]                 | LOCATED    | LVTTL33_OUT  | PR3A  |               |           |           |
+| 70/1     | RA[5]                 | LOCATED    | LVTTL33_OUT  | PR2D  |               |           |           |
+| 71/1     | RA[3]                 | LOCATED    | LVTTL33_OUT  | PR2C  |               |           |           |
+| 74/1     | RA[4]                 | LOCATED    | LVTTL33_OUT  | PR2B  |               |           |           |
+| 75/1     | RA[7]                 | LOCATED    | LVTTL33_OUT  | PR2A  |               |           |           |
+| 76/0     | Dout[0]               | LOCATED    | LVTTL33_OUT  | PT11D | DONE          |           |           |
+| 77/0     |     unused, PULL:DOWN |            |              | PT11C | INITN         |           |           |
+| 78/0     | Dout[6]               | LOCATED    | LVTTL33_OUT  | PT11A |               |           |           |
+| 81/0     |     unused, PULL:DOWN |            |              | PT10D | PROGRAMN      |           |           |
+| 82/0     | Dout[7]               | LOCATED    | LVTTL33_OUT  | PT10C | JTAGENB       |           |           |
+| 83/0     | Dout[4]               | LOCATED    | LVTTL33_OUT  | PT10B |               |           |           |
+| 84/0     | Dout[5]               | LOCATED    | LVTTL33_OUT  | PT10A |               |           |           |
+| 85/0     | Dout[3]               | LOCATED    | LVTTL33_OUT  | PT9D  | SDA/PCLKC0_0  |           |           |
+| 86/0     | Dout[1]               | LOCATED    | LVTTL33_OUT  | PT9C  | SCL/PCLKT0_0  |           |           |
+| 87/0     | Dout[2]               | LOCATED    | LVTTL33_OUT  | PT9B  | PCLKC0_1      |           |           |
+| 88/0     | Din[2]                | LOCATED    | LVTTL33_IN   | PT9A  | PCLKT0_1      |           |           |
+| 90/0     | Reserved: sysCONFIG   |            |              | PT7D  | TMS           |           |           |
+| 91/0     | Reserved: sysCONFIG   |            |              | PT7C  | TCK           |           |           |
+| 94/0     | Reserved: sysCONFIG   |            |              | PT7B  | TDI           |           |           |
+| 95/0     | Reserved: sysCONFIG   |            |              | PT7A  | TDO           |           |           |
+| 96/0     | Din[1]                | LOCATED    | LVTTL33_IN   | PT6D  |               |           |           |
+| 97/0     | Din[3]                | LOCATED    | LVTTL33_IN   | PT6C  |               |           |           |
+| 98/0     | Din[5]                | LOCATED    | LVTTL33_IN   | PT6B  |               |           |           |
+| 99/0     | Din[4]                | LOCATED    | LVTTL33_IN   | PT6A  |               |           |           |
+| PT11B/0  |     unused, PULL:DOWN |            |              | PT11B |               |           |           |
++----------+-----------------------+------------+--------------+-------+---------------+-----------+-----------+
+
+sysCONFIG Pins:
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode  |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| PT7D     | TMS                | JTAG_PORT=ENABLE   | 90/0     |             | PULLUP            |
+| PT7C     | TCK/TEST_CLK       | JTAG_PORT=ENABLE   | 91/0     |             | NO pull up/down   |
+| PT7B     | TDI/MD7            | JTAG_PORT=ENABLE   | 94/0     |             | PULLUP            |
+| PT7A     | TDO                | JTAG_PORT=ENABLE   | 95/0     |             | PULLUP            |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+
+Dedicated sysCONFIG Pins:
+
+
+List of All Pins' Locate Preferences Based on Final Placement After PAR 
+to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
+
+LOCATE  COMP  "CROW[0]"  SITE  "10";
+LOCATE  COMP  "CROW[1]"  SITE  "16";
+LOCATE  COMP  "Din[0]"  SITE  "3";
+LOCATE  COMP  "Din[1]"  SITE  "96";
+LOCATE  COMP  "Din[2]"  SITE  "88";
+LOCATE  COMP  "Din[3]"  SITE  "97";
+LOCATE  COMP  "Din[4]"  SITE  "99";
+LOCATE  COMP  "Din[5]"  SITE  "98";
+LOCATE  COMP  "Din[6]"  SITE  "2";
+LOCATE  COMP  "Din[7]"  SITE  "1";
+LOCATE  COMP  "Dout[0]"  SITE  "76";
+LOCATE  COMP  "Dout[1]"  SITE  "86";
+LOCATE  COMP  "Dout[2]"  SITE  "87";
+LOCATE  COMP  "Dout[3]"  SITE  "85";
+LOCATE  COMP  "Dout[4]"  SITE  "83";
+LOCATE  COMP  "Dout[5]"  SITE  "84";
+LOCATE  COMP  "Dout[6]"  SITE  "78";
+LOCATE  COMP  "Dout[7]"  SITE  "82";
+LOCATE  COMP  "LED"  SITE  "34";
+LOCATE  COMP  "MAin[0]"  SITE  "14";
+LOCATE  COMP  "MAin[1]"  SITE  "12";
+LOCATE  COMP  "MAin[2]"  SITE  "13";
+LOCATE  COMP  "MAin[3]"  SITE  "21";
+LOCATE  COMP  "MAin[4]"  SITE  "20";
+LOCATE  COMP  "MAin[5]"  SITE  "19";
+LOCATE  COMP  "MAin[6]"  SITE  "24";
+LOCATE  COMP  "MAin[7]"  SITE  "18";
+LOCATE  COMP  "MAin[8]"  SITE  "25";
+LOCATE  COMP  "MAin[9]"  SITE  "32";
+LOCATE  COMP  "PHI2"  SITE  "8";
+LOCATE  COMP  "RA[0]"  SITE  "66";
+LOCATE  COMP  "RA[10]"  SITE  "64";
+LOCATE  COMP  "RA[11]"  SITE  "59";
+LOCATE  COMP  "RA[1]"  SITE  "67";
+LOCATE  COMP  "RA[2]"  SITE  "69";
+LOCATE  COMP  "RA[3]"  SITE  "71";
+LOCATE  COMP  "RA[4]"  SITE  "74";
+LOCATE  COMP  "RA[5]"  SITE  "70";
+LOCATE  COMP  "RA[6]"  SITE  "68";
+LOCATE  COMP  "RA[7]"  SITE  "75";
+LOCATE  COMP  "RA[8]"  SITE  "65";
+LOCATE  COMP  "RA[9]"  SITE  "62";
+LOCATE  COMP  "RBA[0]"  SITE  "58";
+LOCATE  COMP  "RBA[1]"  SITE  "60";
+LOCATE  COMP  "RCKE"  SITE  "53";
+LOCATE  COMP  "RCLK"  SITE  "63";
+LOCATE  COMP  "RDQMH"  SITE  "51";
+LOCATE  COMP  "RDQML"  SITE  "48";
+LOCATE  COMP  "RD[0]"  SITE  "36";
+LOCATE  COMP  "RD[1]"  SITE  "37";
+LOCATE  COMP  "RD[2]"  SITE  "38";
+LOCATE  COMP  "RD[3]"  SITE  "39";
+LOCATE  COMP  "RD[4]"  SITE  "40";
+LOCATE  COMP  "RD[5]"  SITE  "41";
+LOCATE  COMP  "RD[6]"  SITE  "42";
+LOCATE  COMP  "RD[7]"  SITE  "43";
+LOCATE  COMP  "nCCAS"  SITE  "9";
+LOCATE  COMP  "nCRAS"  SITE  "17";
+LOCATE  COMP  "nFWE"  SITE  "15";
+LOCATE  COMP  "nRCAS"  SITE  "52";
+LOCATE  COMP  "nRCS"  SITE  "57";
+LOCATE  COMP  "nRRAS"  SITE  "54";
+LOCATE  COMP  "nRWE"  SITE  "49";
+
+
+
+
+
+PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 17 06:20:59 2021
+
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.par b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.par
new file mode 100644
index 0000000..f2f6100
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.par
@@ -0,0 +1,233 @@
+
+Lattice Place and Route Report for Design "RAM2GS_LCMXO2_640HC_impl1_map.ncd"
+Tue Aug 17 06:20:51 2021
+
+PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
+Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file RAM2GS_LCMXO2_640HC_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+Device utilization summary:
+
+   PIO (prelim)   63+4(JTAG)/80      84% used
+                  63+4(JTAG)/79      85% bonded
+
+   SLICE            131/320          40% used
+
+   EFB                1/1           100% used
+
+
+Number of Signals: 401
+Number of Connections: 1131
+
+Pin Constraint Summary:
+   63 out of 63 pins locked (100% locked).
+
+The following 4 signals are selected to use the primary clock routing resources:
+    RCLK_c (driver: RCLK, clk load #: 52)
+    PHI2_c (driver: PHI2, clk load #: 13)
+    nCRAS_c (driver: nCRAS, clk load #: 7)
+    nCCAS_c (driver: nCCAS, clk load #: 4)
+
+WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
+WARNING - par: Signal "nCRAS_c" is selected to use Primary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
+WARNING - par: Signal "nCCAS_c" is selected to use Primary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
+
+No signal is selected as secondary clock.
+
+No signal is selected as Global Set/Reset.
+Starting Placer Phase 0.
+............
+Finished Placer Phase 0.  REAL time: 0 secs 
+
+Starting Placer Phase 1.
+....................
+Placer score = 65362.
+Finished Placer Phase 1.  REAL time: 6 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  65089
+Finished Placer Phase 2.  REAL time: 6 secs 
+
+
+------------------ Clock Report ------------------
+
+Global Clock Resources:
+  CLK_PIN    : 1 out of 8 (12%)
+  General PIO: 3 out of 80 (3%)
+  DCM        : 0 out of 2 (0%)
+  DCC        : 0 out of 8 (0%)
+
+Global Clocks:
+  PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "63 (PR5C)", clk load = 52
+  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 13
+  PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 7
+  PRIMARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 4
+
+  PRIMARY  : 4 out of 8 (50%)
+  SECONDARY: 0 out of 8 (0%)
+
+--------------- End of Clock Report ---------------
+
+
+I/O Usage Summary (final):
+   63 + 4(JTAG) out of 80 (83.8%) PIO sites used.
+   63 + 4(JTAG) out of 79 (84.8%) bonded PIO sites used.
+   Number of PIO comps: 63; differential: 0.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+----------------+------------+-----------+
+| I/O Bank | Usage          | Bank Vccio | Bank Vref |
++----------+----------------+------------+-----------+
+| 0        | 13 / 19 ( 68%) | 3.3V       | -         |
+| 1        | 20 / 20 (100%) | 3.3V       | -         |
+| 2        | 12 / 20 ( 60%) | 3.3V       | -         |
+| 3        | 18 / 20 ( 90%) | 3.3V       | -         |
++----------+----------------+------------+-----------+
+
+Total placer CPU time: 5 secs 
+
+Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
+
+0 connections routed; 1131 unrouted.
+Starting router resource preassignment
+WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
+WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
+WARNING - par: The driver of primary clock net nCCAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
+
+WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
+   Signal=wb_clk loads=1 clock_loads=1
+
+Completed router resource preassignment. Real time: 8 secs 
+
+Start NBR router at 06:20:59 08/17/21
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at 06:20:59 08/17/21
+
+Start NBR section for initial routing at 06:20:59 08/17/21
+Level 1, iteration 1
+0(0.00%) conflict; 980(86.65%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.167ns/0.000ns; real time: 8 secs 
+Level 2, iteration 1
+1(0.00%) conflict; 970(85.76%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.141ns/0.000ns; real time: 9 secs 
+Level 3, iteration 1
+1(0.00%) conflict; 904(79.93%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+Level 4, iteration 1
+26(0.06%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 06:21:00 08/17/21
+Level 1, iteration 1
+1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+Level 2, iteration 1
+1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+Level 3, iteration 1
+1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+Level 4, iteration 1
+12(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+Level 4, iteration 2
+5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+Level 4, iteration 3
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+
+Start NBR section for setup/hold timing optimization with effort level 3 at 06:21:00 08/17/21
+
+Start NBR section for re-routing at 06:21:00 08/17/21
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+
+Start NBR section for post-routing at 06:21:00 08/17/21
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 0 (0.00%)
+  Estimated worst slack : 1.135ns
+  Timing score : 0
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
+   Signal=wb_clk loads=1 clock_loads=1
+
+Total CPU time 9 secs 
+Total REAL time: 10 secs 
+Completely routed.
+End of route.  1131 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 0 
+
+Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = Completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack> = 1.135
+PAR_SUMMARY::Timing score> = 0.000
+PAR_SUMMARY::Worst  slack> = 0.304
+PAR_SUMMARY::Timing score> = 0.000
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 9 secs 
+Total REAL time to completion: 10 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1_par.asd b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1_par.asd
new file mode 100644
index 0000000..c0f7313
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1_par.asd
@@ -0,0 +1,41 @@
+[ActiveSupport PAR]
+; Global primary clocks
+GLOBAL_PRIMARY_USED = 4;
+; Global primary clock #0
+GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c;
+GLOBAL_PRIMARY_0_DRIVERTYPE = CLK_PIN;
+GLOBAL_PRIMARY_0_LOADNUM = 52;
+; Global primary clock #1
+GLOBAL_PRIMARY_1_SIGNALNAME = PHI2_c;
+GLOBAL_PRIMARY_1_DRIVERTYPE = PIO;
+GLOBAL_PRIMARY_1_LOADNUM = 13;
+; Global primary clock #2
+GLOBAL_PRIMARY_2_SIGNALNAME = nCRAS_c;
+GLOBAL_PRIMARY_2_DRIVERTYPE = PIO;
+GLOBAL_PRIMARY_2_LOADNUM = 7;
+; Global primary clock #3
+GLOBAL_PRIMARY_3_SIGNALNAME = nCCAS_c;
+GLOBAL_PRIMARY_3_DRIVERTYPE = PIO;
+GLOBAL_PRIMARY_3_LOADNUM = 4;
+; # of global secondary clocks
+GLOBAL_SECONDARY_USED = 0;
+; I/O Bank 0 Usage
+BANK_0_USED = 13;
+BANK_0_AVAIL = 19;
+BANK_0_VCCIO = 3.3V;
+BANK_0_VREF1 = NA;
+; I/O Bank 1 Usage
+BANK_1_USED = 20;
+BANK_1_AVAIL = 20;
+BANK_1_VCCIO = 3.3V;
+BANK_1_VREF1 = NA;
+; I/O Bank 2 Usage
+BANK_2_USED = 12;
+BANK_2_AVAIL = 20;
+BANK_2_VCCIO = 3.3V;
+BANK_2_VREF1 = NA;
+; I/O Bank 3 Usage
+BANK_3_USED = 18;
+BANK_3_AVAIL = 20;
+BANK_3_VCCIO = 3.3V;
+BANK_3_VREF1 = NA;
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/RAM2GS_LCMXO2_640HC_impl1.par b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/RAM2GS_LCMXO2_640HC_impl1.par
new file mode 100644
index 0000000..edce2f7
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/RAM2GS_LCMXO2_640HC_impl1.par
@@ -0,0 +1,28 @@
+PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 17 06:20:51 2021
+
+C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_640HC_impl1.p2t
+RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir
+RAM2GS_LCMXO2_640HC_impl1.prf -gui -msgset
+C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml
+
+
+Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
+
+Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
+Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
+----------   --------     -----        ------       -----------  -----------  ----         ------
+5_1   *      0            1.135        0            0.304        0            10           Completed
+
+* : Design saved.
+
+Total (real) run time for 1-seed: 10 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.drc b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.drc
new file mode 100644
index 0000000..ec074a2
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.drc
@@ -0,0 +1 @@
+DRC detected 0 errors and 0 warnings.
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.jed b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.jed
new file mode 100644
index 0000000..3343732
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.jed
@@ -0,0 +1,1431 @@
+*
+NOTE Diamond (64-bit) 3.12.0.240.2 JEDEC Compatible Fuse File.*
+NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation.*
+NOTE All Rights Reserved.*
+NOTE DATE CREATED:	Tue Aug 17 06:21:07 2021*
+NOTE DESIGN NAME:	RAM2GS_LCMXO2_640HC_impl1.ncd*
+NOTE DEVICE NAME:	LCMXO2-640HC-4TQFP100*
+NOTE JEDEC FILE STATUS:	Final   Version 1.95*
+NOTE PIN ASSIGNMENTS*
+NOTE PINS RCLK : 63 : in*
+NOTE PINS nFWE : 15 : in*
+NOTE PINS nCRAS : 17 : in*
+NOTE PINS nCCAS : 9 : in*
+NOTE PINS Din[0] : 3 : in*
+NOTE PINS Din[1] : 96 : in*
+NOTE PINS Din[2] : 88 : in*
+NOTE PINS Din[3] : 97 : in*
+NOTE PINS Din[4] : 99 : in*
+NOTE PINS Din[5] : 98 : in*
+NOTE PINS Din[6] : 2 : in*
+NOTE PINS Din[7] : 1 : in*
+NOTE PINS CROW[0] : 10 : in*
+NOTE PINS CROW[1] : 16 : in*
+NOTE PINS MAin[0] : 14 : in*
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+NOTE PINS MAin[2] : 13 : in*
+NOTE PINS MAin[3] : 21 : in*
+NOTE PINS MAin[4] : 20 : in*
+NOTE PINS MAin[5] : 19 : in*
+NOTE PINS MAin[6] : 24 : in*
+NOTE PINS MAin[7] : 18 : in*
+NOTE PINS MAin[8] : 25 : in*
+NOTE PINS MAin[9] : 32 : in*
+NOTE PINS PHI2 : 8 : in*
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+NOTE PINS RA[7] : 75 : out*
+NOTE PINS RA[8] : 65 : out*
+NOTE PINS RA[9] : 62 : out*
+NOTE PINS RA[10] : 64 : out*
+NOTE PINS RA[11] : 59 : out*
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+NOTE PINS Dout[2] : 87 : out*
+NOTE PINS Dout[3] : 85 : out*
+NOTE PINS Dout[4] : 83 : out*
+NOTE PINS Dout[5] : 84 : out*
+NOTE PINS Dout[6] : 78 : out*
+NOTE PINS Dout[7] : 82 : out*
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+NOTE PINS RD[2] : 38 : inout*
+NOTE PINS RD[3] : 39 : inout*
+NOTE PINS RD[4] : 40 : inout*
+NOTE PINS RD[5] : 41 : inout*
+NOTE PINS RD[6] : 42 : inout*
+NOTE PINS RD[7] : 43 : inout*
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diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.log b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.log
new file mode 100644
index 0000000..d0353b8
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.log
@@ -0,0 +1,4 @@
+---- MParTrce Tool Log File ----
+
+==== Par Standard Out ====
+==== End of Par Standard Out ====
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lpf b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lpf
new file mode 100644
index 0000000..2743d95
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lpf
@@ -0,0 +1,4 @@
+#BLOCK ASYNCPATHS;
+#BLOCK RESETPATHS;
+
+#FREQUENCY 200.000000 MHz;
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lsedata b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lsedata
new file mode 100644
index 0000000..641fd41
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lsedata
@@ -0,0 +1,9954 @@
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diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mrp b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mrp
new file mode 100644
index 0000000..e49c545
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mrp
@@ -0,0 +1,402 @@
+
+            Lattice Mapping Report File for Design Module 'RAM2GS'
+
+
+Design Information
+------------------
+
+Command line:   map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
+     RAM2GS_LCMXO2_640HC_impl1.ngd -o RAM2GS_LCMXO2_640HC_impl1_map.ncd -pr
+     RAM2GS_LCMXO2_640HC_impl1.prf -mp RAM2GS_LCMXO2_640HC_impl1.mrp -lpf C:/Use
+     rs/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2
+     _640HC_impl1.lpf -lpf C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMX
+     O2-640HC/RAM2GS_LCMXO2_640HC.lpf -c 0 -gui -msgset
+     C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml 
+Target Vendor:  LATTICE
+Target Device:  LCMXO2-640HCTQFP100
+Target Performance:   4
+Mapper:  xo2c00,  version:  Diamond (64-bit) 3.12.0.240.2
+Mapped on:  08/17/21  06:20:50
+
+Design Summary
+--------------
+
+   Number of registers:    119 out of   877 (14%)
+      PFU registers:          119 out of   640 (19%)
+      PIO registers:            0 out of   237 (0%)
+   Number of SLICEs:       131 out of   320 (41%)
+      SLICEs as Logic/ROM:    131 out of   320 (41%)
+      SLICEs as RAM:            0 out of   240 (0%)
+      SLICEs as Carry:         10 out of   320 (3%)
+   Number of LUT4s:        255 out of   640 (40%)
+      Number used as logic LUTs:        235
+      Number used as distributed RAM:     0
+      Number used as ripple logic:       20
+      Number used as shift registers:     0
+   Number of PIO sites used: 63 + 4(JTAG) out of 79 (85%)
+   Number of block RAMs:  0 out of 2 (0%)
+   Number of GSRs:        0 out of 1 (0%)
+   EFB used :        Yes
+   JTAG used :       No
+   Readback used :   No
+   Oscillator used : No
+   Startup used :    No
+   POR :             On
+   Bandgap :         On
+   Number of Power Controller:  0 out of 1 (0%)
+   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
+   Number of DCCA:  0 out of 8 (0%)
+   Number of DCMA:  0 out of 2 (0%)
+   Notes:-
+      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
+     distributed RAMs) + 2*(Number of ripple logic)
+      2. Number of logic LUT4s does not include count of distributed RAM and
+     ripple logic.
+   Number of clocks:  5
+     Net RCLK_c: 52 loads, 52 rising, 0 falling (Driver: PIO RCLK )
+     Net wb_clk: 1 loads, 1 rising, 0 falling (Driver: wb_clk_550 )
+     Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 )
+     Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS )
+     Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
+   Number of Clock Enables:  14
+     Net RCLK_c_enable_27: 8 loads, 8 LSLICEs
+
+                                    Page 1
+
+
+
+
+Design:  RAM2GS                                        Date:  08/17/21  06:20:50
+
+Design Summary (cont)
+---------------------
+     Net RCLK_c_enable_20: 4 loads, 4 LSLICEs
+     Net RCLK_c_enable_29: 2 loads, 2 LSLICEs
+     Net RCLK_c_enable_25: 2 loads, 2 LSLICEs
+     Net InitReady: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_24: 2 loads, 2 LSLICEs
+     Net PHI2_N_151_enable_1: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_26: 1 loads, 1 LSLICEs
+     Net PHI2_N_151_enable_3: 1 loads, 1 LSLICEs
+     Net PHI2_N_151_enable_5: 2 loads, 2 LSLICEs
+     Net Ready_N_280: 1 loads, 1 LSLICEs
+     Net PHI2_N_151_enable_6: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_28: 1 loads, 1 LSLICEs
+     Net PHI2_N_151_enable_7: 1 loads, 1 LSLICEs
+   Number of LSRs:  8
+     Net RASr2: 1 loads, 1 LSLICEs
+     Net nRowColSel_N_34: 1 loads, 1 LSLICEs
+     Net wb_rst: 1 loads, 0 LSLICEs
+     Net nRWE_N_210: 1 loads, 1 LSLICEs
+     Net C1Submitted_N_232: 2 loads, 2 LSLICEs
+     Net wb_adr_7__N_92: 2 loads, 2 LSLICEs
+     Net nRowColSel_N_35: 1 loads, 1 LSLICEs
+     Net Ready: 7 loads, 7 LSLICEs
+   Number of nets driven by tri-state buffers:  0
+   Top 10 highest fanout non-clock nets:
+     Net InitReady: 36 loads
+     Net FS_10: 32 loads
+     Net FS_11: 32 loads
+     Net FS_9: 26 loads
+     Net FS_7: 25 loads
+     Net FS_8: 23 loads
+     Net FS_5: 21 loads
+     Net FS_6: 21 loads
+     Net FS_12: 20 loads
+     Net Ready: 18 loads
+
+
+
+
+   Number of warnings:  0
+   Number of errors:    0
+     
+
+Design Errors/Warnings
+----------------------
+
+   No errors or warnings present.
+
+IO (PIO) Attributes
+-------------------
+
++---------------------+-----------+-----------+------------+
+| IO Name             | Direction | Levelmode | IO         |
+|                     |           |  IO_TYPE  | Register   |
++---------------------+-----------+-----------+------------+
+| RCLK                | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+
+                                    Page 2
+
+
+
+
+Design:  RAM2GS                                        Date:  08/17/21  06:20:50
+
+IO (PIO) Attributes (cont)
+--------------------------
+| nFWE                | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| nCRAS               | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| nCCAS               | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Din[0]              | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Din[1]              | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Din[2]              | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Din[3]              | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Din[4]              | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Din[5]              | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Din[6]              | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Din[7]              | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| CROW[0]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| CROW[1]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[0]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[1]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[2]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[3]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[4]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[5]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[6]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[7]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[8]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[9]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| PHI2                | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RDQML               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RDQMH               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| nRCAS               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| nRRAS               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+
+                                    Page 3
+
+
+
+
+Design:  RAM2GS                                        Date:  08/17/21  06:20:50
+
+IO (PIO) Attributes (cont)
+--------------------------
+| nRWE                | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RCKE                | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| nRCS                | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[0]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[1]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[2]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[3]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[4]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[5]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[6]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[7]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[8]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[9]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[10]              | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[11]              | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RBA[0]              | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RBA[1]              | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| LED                 | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Dout[0]             | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Dout[1]             | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Dout[2]             | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Dout[3]             | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Dout[4]             | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Dout[5]             | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Dout[6]             | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Dout[7]             | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RD[0]               | BIDIR     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RD[1]               | BIDIR     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+
+                                    Page 4
+
+
+
+
+Design:  RAM2GS                                        Date:  08/17/21  06:20:50
+
+IO (PIO) Attributes (cont)
+--------------------------
+| RD[2]               | BIDIR     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RD[3]               | BIDIR     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RD[4]               | BIDIR     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RD[5]               | BIDIR     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RD[6]               | BIDIR     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RD[7]               | BIDIR     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+
+Removed logic
+-------------
+
+Block i2 undriven or does not drive anything - clipped.
+Block GSR_INST undriven or does not drive anything - clipped.
+Signal PHI2_N_151 was merged into signal PHI2_c
+Signal nRWE_N_209 was merged into signal nRWE_N_210
+Signal RCLK_c_enable_22 was merged into signal InitReady
+Signal n2557 was merged into signal nRowColSel_N_34
+Signal n4935 was merged into signal Ready
+Signal n4933 was merged into signal nRowColSel_N_35
+Signal GND_net undriven or does not drive anything - clipped.
+Signal VCC_net undriven or does not drive anything - clipped.
+Signal FS_972_add_4_1/S0 undriven or does not drive anything - clipped.
+Signal FS_972_add_4_1/CI undriven or does not drive anything - clipped.
+Signal FS_972_add_4_19/S1 undriven or does not drive anything - clipped.
+Signal FS_972_add_4_19/CO undriven or does not drive anything - clipped.
+Block i4008 was optimized away.
+Block nRWE_I_53_1_lut was optimized away.
+Block InitReady_I_0_586_1_lut_rep_73 was optimized away.
+Block i1683_1_lut was optimized away.
+Block i1044_1_lut_rep_86 was optimized away.
+Block i1684_1_lut_rep_84 was optimized away.
+Block i1 was optimized away.
+
+     
+
+Embedded Functional Block Connection Summary
+--------------------------------------------
+
+   Desired WISHBONE clock frequency: 50.0 MHz
+   Clock source:                     wb_clk
+   Reset source:                     wb_rst
+   Functions mode:
+      I2C #1 (Primary) Function:     DISABLED
+      I2C #2 (Secondary) Function:   DISABLED
+      SPI Function:                  DISABLED
+      Timer/Counter Function:        DISABLED
+      Timer/Counter Mode:            NO_WB
+      UFM Connection:                DISABLED
+      PLL0 Connection:               DISABLED
+      PLL1 Connection:               DISABLED
+   I2C Function Summary:
+
+                                    Page 5
+
+
+
+
+Design:  RAM2GS                                        Date:  08/17/21  06:20:50
+
+Embedded Functional Block Connection Summary (cont)
+---------------------------------------------------
+   --------------------
+      None
+   SPI Function Summary:
+   --------------------
+      None
+   Timer/Counter Function Summary:
+   ------------------------------
+      None
+   UFM Function Summary:
+   --------------------
+      UFM Utilization:        General Purpose Flash Memory
+      Available General
+      Purpose Flash Memory:   191 Pages (191*128 Bits)
+
+           EBR Blocks with Unique
+      Initialization Data:    0
+
+           WID		EBR Instance
+      ---		------------
+
+
+ASIC Components
+---------------
+
+Instance Name: ufmefb
+         Type: EFB
+
+Run Time and Memory Usage
+-------------------------
+
+   Total CPU Time: 0 secs  
+   Total REAL Time: 0 secs  
+   Peak Memory Usage: 36 MB
+        
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+                                    Page 6
+
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+     Copyright (c) 1995 AT&T Corp.   All rights reserved.
+     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+     Copyright (c) 2001 Agere Systems   All rights reserved.
+     Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights
+     reserved.
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mt b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mt
new file mode 100644
index 0000000..2d70ad1
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mt
@@ -0,0 +1,9 @@
+-v
+1
+
+
+-gt
+
+
+-mapchkpnt 0
+-sethld
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.ncd b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.ncd
new file mode 100644
index 0000000000000000000000000000000000000000..352b225eb29e8ecbfcb2e640beec10959dc89e97
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diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.ngd b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.ngd
new file mode 100644
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zrqu@!MKby@x9h@CMt{lest;uJQEt}^Uq*k;?V9Px=;Pe3S+: 1.167ns/0.000ns; real time: 8 secs 
+Level 2, iteration 1
+1(0.00%) conflict; 970(85.76%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.141ns/0.000ns; real time: 9 secs 
+Level 3, iteration 1
+1(0.00%) conflict; 904(79.93%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+Level 4, iteration 1
+26(0.06%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 06:21:00 08/17/21
+Level 1, iteration 1
+1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+Level 2, iteration 1
+1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+Level 3, iteration 1
+1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+Level 4, iteration 1
+12(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+Level 4, iteration 2
+5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+Level 4, iteration 3
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+
+Start NBR section for setup/hold timing optimization with effort level 3 at 06:21:00 08/17/21
+
+Start NBR section for re-routing at 06:21:00 08/17/21
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+
+Start NBR section for post-routing at 06:21:00 08/17/21
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 0 (0.00%)
+  Estimated worst slack : 1.135ns
+  Timing score : 0
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
+   Signal=wb_clk loads=1 clock_loads=1
+
+Total CPU time 9 secs 
+Total REAL time: 10 secs 
+Completely routed.
+End of route.  1131 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 0 
+
+Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = Completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack> = 1.135
+PAR_SUMMARY::Timing score> = 0.000
+PAR_SUMMARY::Worst  slack> = 0.304
+PAR_SUMMARY::Timing score> = 0.000
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 9 secs 
+Total REAL time to completion: 10 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.prf b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.prf
new file mode 100644
index 0000000..dbb9d92
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.prf
@@ -0,0 +1,158 @@
+SCHEMATIC START ;
+# map:  version Diamond (64-bit) 3.12.0.240.2 -- WARNING: Map write only section -- Tue Aug 17 06:20:50 2021
+
+SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
+LOCATE COMP "RCLK" SITE "63" ;
+LOCATE COMP "nFWE" SITE "15" ;
+LOCATE COMP "nCRAS" SITE "17" ;
+LOCATE COMP "nCCAS" SITE "9" ;
+LOCATE COMP "Din[0]" SITE "3" ;
+LOCATE COMP "Din[1]" SITE "96" ;
+LOCATE COMP "Din[2]" SITE "88" ;
+LOCATE COMP "Din[3]" SITE "97" ;
+LOCATE COMP "Din[4]" SITE "99" ;
+LOCATE COMP "Din[5]" SITE "98" ;
+LOCATE COMP "Din[6]" SITE "2" ;
+LOCATE COMP "Din[7]" SITE "1" ;
+LOCATE COMP "CROW[0]" SITE "10" ;
+LOCATE COMP "CROW[1]" SITE "16" ;
+LOCATE COMP "MAin[0]" SITE "14" ;
+LOCATE COMP "MAin[1]" SITE "12" ;
+LOCATE COMP "MAin[2]" SITE "13" ;
+LOCATE COMP "MAin[3]" SITE "21" ;
+LOCATE COMP "MAin[4]" SITE "20" ;
+LOCATE COMP "MAin[5]" SITE "19" ;
+LOCATE COMP "MAin[6]" SITE "24" ;
+LOCATE COMP "MAin[7]" SITE "18" ;
+LOCATE COMP "MAin[8]" SITE "25" ;
+LOCATE COMP "MAin[9]" SITE "32" ;
+LOCATE COMP "PHI2" SITE "8" ;
+LOCATE COMP "RDQML" SITE "48" ;
+LOCATE COMP "RDQMH" SITE "51" ;
+LOCATE COMP "nRCAS" SITE "52" ;
+LOCATE COMP "nRRAS" SITE "54" ;
+LOCATE COMP "nRWE" SITE "49" ;
+LOCATE COMP "RCKE" SITE "53" ;
+LOCATE COMP "nRCS" SITE "57" ;
+LOCATE COMP "RA[0]" SITE "66" ;
+LOCATE COMP "RA[1]" SITE "67" ;
+LOCATE COMP "RA[2]" SITE "69" ;
+LOCATE COMP "RA[3]" SITE "71" ;
+LOCATE COMP "RA[4]" SITE "74" ;
+LOCATE COMP "RA[5]" SITE "70" ;
+LOCATE COMP "RA[6]" SITE "68" ;
+LOCATE COMP "RA[7]" SITE "75" ;
+LOCATE COMP "RA[8]" SITE "65" ;
+LOCATE COMP "RA[9]" SITE "62" ;
+LOCATE COMP "RA[10]" SITE "64" ;
+LOCATE COMP "RA[11]" SITE "59" ;
+LOCATE COMP "RBA[0]" SITE "58" ;
+LOCATE COMP "RBA[1]" SITE "60" ;
+LOCATE COMP "LED" SITE "34" ;
+LOCATE COMP "Dout[0]" SITE "76" ;
+LOCATE COMP "Dout[1]" SITE "86" ;
+LOCATE COMP "Dout[2]" SITE "87" ;
+LOCATE COMP "Dout[3]" SITE "85" ;
+LOCATE COMP "Dout[4]" SITE "83" ;
+LOCATE COMP "Dout[5]" SITE "84" ;
+LOCATE COMP "Dout[6]" SITE "78" ;
+LOCATE COMP "Dout[7]" SITE "82" ;
+LOCATE COMP "RD[0]" SITE "36" ;
+LOCATE COMP "RD[1]" SITE "37" ;
+LOCATE COMP "RD[2]" SITE "38" ;
+LOCATE COMP "RD[3]" SITE "39" ;
+LOCATE COMP "RD[4]" SITE "40" ;
+LOCATE COMP "RD[5]" SITE "41" ;
+LOCATE COMP "RD[6]" SITE "42" ;
+LOCATE COMP "RD[7]" SITE "43" ;
+PERIOD NET "PHI2_c" 350.000000 ns  ;
+USE PRIMARY NET "RCLK_c" ;
+PERIOD NET "nCCAS_c" 350.000000 ns  ;
+USE PRIMARY NET "PHI2_c" ;
+PERIOD NET "nCRAS_c" 350.000000 ns  ;
+USE PRIMARY NET "nCRAS_c" ;
+PERIOD NET "RCLK_c" 16.000000 ns  ;
+USE PRIMARY NET "nCCAS_c" ;
+SCHEMATIC END ;
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+OUTPUT PORT "RD[7]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[0]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[1]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[2]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[3]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[4]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[5]" LOAD 20.000000 pF ;
+OUTPUT PORT "RD[6]" LOAD 20.000000 pF ;
+OUTPUT PORT "nRWE" LOAD 10.000000 pF ;
+OUTPUT PORT "nRCAS" LOAD 10.000000 pF ;
+OUTPUT PORT "nRCS" LOAD 10.000000 pF ;
+OUTPUT PORT "nRRAS" LOAD 10.000000 pF ;
+OUTPUT PORT "RDQML" LOAD 10.000000 pF ;
+OUTPUT PORT "RDQMH" LOAD 10.000000 pF ;
+OUTPUT PORT "RCKE" LOAD 10.000000 pF ;
+OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ;
+OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[11]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[10]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[9]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[8]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[7]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[6]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[5]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[4]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[3]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[2]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[1]" LOAD 10.000000 pF ;
+OUTPUT PORT "RA[0]" LOAD 10.000000 pF ;
+OUTPUT PORT "LED" LOAD 25.000000 pF ;
+OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ;
+OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ;
+VOLTAGE 3.300 V;
+VCCIO_DERATE BANK 0 PERCENT -5; 
+VCCIO_DERATE PERCENT -5; 
+VCCIO_DERATE BANK 1 PERCENT -5; 
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+COMMERCIAL ;
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.pt b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.pt
new file mode 100644
index 0000000..e5e32de
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.pt
@@ -0,0 +1,10 @@
+-v
+10
+
+
+
+
+-gt
+-sethld
+-sp 4
+-sphld m
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.t2b b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.t2b
new file mode 100644
index 0000000..2579ff8
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.t2b
@@ -0,0 +1,5 @@
+
+
+-g RamCfg:Reset
+
+-path "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC"  
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.tw1 b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.tw1
new file mode 100644
index 0000000..0cce058
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.tw1
@@ -0,0 +1,2547 @@
+
+Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
+Tue Aug 17 06:20:51 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_640hc_impl1_map.ncd
+Preference file: ram2gs_lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,4
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+VCCIO Voltage:
+                   3.135 V (Bank 0)
+                   3.135 V (Bank 1)
+                   3.135 V (Bank 2)
+                   3.135 V (Bank 3)
+                   2.375 V (Bank 4)
+                   2.375 V (Bank 5)
+                   2.375 V (Bank 6)
+                   2.375 V (Bank 7)
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            121 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 161.658ns (weighted slack = 323.316ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i5  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_541  (to PHI2_c -)
+
+   Delay:              13.035ns  (30.0% logic, 70.0% route), 8 logic levels.
+
+ Constraint Details:
+
+     13.035ns physical path delay SLICE_111 to SLICE_19 meets
+    175.000ns delay constraint less
+      0.307ns CE_SET requirement (totaling 174.693ns) by 161.658ns
+
+ Physical Path Details:
+
+      Data path SLICE_111 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452  SLICE_111.CLK to   SLICE_111.Q1 SLICE_111 (from PHI2_c)
+ROUTE         1   e 1.234   SLICE_111.Q1 to   SLICE_158.B0 Bank_5
+CTOF_DEL    ---     0.495   SLICE_158.B0 to   SLICE_158.F0 SLICE_158
+ROUTE         1   e 1.234   SLICE_158.F0 to   SLICE_139.B0 n4610
+CTOF_DEL    ---     0.495   SLICE_139.B0 to   SLICE_139.F0 SLICE_139
+ROUTE         2   e 1.234   SLICE_139.F0 to   SLICE_114.B1 n4628
+CTOF_DEL    ---     0.495   SLICE_114.B1 to   SLICE_114.F1 SLICE_114
+ROUTE         4   e 1.234   SLICE_114.F1 to   SLICE_116.B1 n2384
+CTOF_DEL    ---     0.495   SLICE_116.B1 to   SLICE_116.F1 SLICE_116
+ROUTE         2   e 0.480   SLICE_116.F1 to   SLICE_116.D0 n4888
+CTOF_DEL    ---     0.495   SLICE_116.D0 to   SLICE_116.F0 SLICE_116
+ROUTE         1   e 1.234   SLICE_116.F0 to    SLICE_19.B1 n4624
+CTOF_DEL    ---     0.495    SLICE_19.B1 to    SLICE_19.F1 SLICE_19
+ROUTE         4   e 1.234    SLICE_19.F1 to   SLICE_130.C0 C1Submitted_N_232
+CTOF_DEL    ---     0.495   SLICE_130.C0 to   SLICE_130.F0 SLICE_130
+ROUTE         1   e 1.234   SLICE_130.F0 to    SLICE_19.CE PHI2_N_151_enable_1 (to PHI2_c)
+                  --------
+                   13.035   (30.0% logic, 70.0% route), 8 logic levels.
+
+Report:   26.684ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 347.500ns
+         The internal maximum frequency of the following component is 400.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    SLICE      CLK            SLICE_122
+
+   Delay:               2.500ns -- based on Minimum Pulse Width
+
+Report:    2.500ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 347.500ns
+         The internal maximum frequency of the following component is 400.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    SLICE      CLK            SLICE_25
+
+   Delay:               2.500ns -- based on Minimum Pulse Width
+
+Report:    2.500ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            1409 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 2.077ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i8  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i4  (to RCLK_c +)
+
+   Delay:              13.757ns  (33.7% logic, 66.3% route), 9 logic levels.
+
+ Constraint Details:
+
+     13.757ns physical path delay SLICE_5 to SLICE_70 meets
+     16.000ns delay constraint less
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 2.077ns
+
+ Physical Path Details:
+
+      Data path SLICE_5 to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452    SLICE_5.CLK to     SLICE_5.Q1 SLICE_5 (from RCLK_c)
+ROUTE        23   e 1.234     SLICE_5.Q1 to    SLICE_98.B1 FS_8
+CTOF_DEL    ---     0.495    SLICE_98.B1 to    SLICE_98.F1 SLICE_98
+ROUTE         4   e 1.234    SLICE_98.F1 to    SLICE_93.B1 n4924
+CTOF_DEL    ---     0.495    SLICE_93.B1 to    SLICE_93.F1 SLICE_93
+ROUTE         1   e 1.234    SLICE_93.F1 to   SLICE_133.D0 n98
+CTOF_DEL    ---     0.495   SLICE_133.D0 to   SLICE_133.F0 SLICE_133
+ROUTE         2   e 0.480   SLICE_133.F0 to   SLICE_133.B1 n2199
+CTOF_DEL    ---     0.495   SLICE_133.B1 to   SLICE_133.F1 SLICE_133
+ROUTE         1   e 1.234   SLICE_133.F1 to *9/SLICE_84.C1 n53
+CTOOFX_DEL  ---     0.721 *9/SLICE_84.C1 to *SLICE_84.OFX0 i29/SLICE_84
+ROUTE         1   e 1.234 *SLICE_84.OFX0 to   SLICE_148.C1 n14_adj_3
+CTOF_DEL    ---     0.495   SLICE_148.C1 to   SLICE_148.F1 SLICE_148
+ROUTE         2   e 1.234   SLICE_148.F1 to   SLICE_135.C0 n12_adj_8
+CTOF_DEL    ---     0.495   SLICE_135.C0 to   SLICE_135.F0 SLICE_135
+ROUTE         2   e 1.234   SLICE_135.F0 to    SLICE_70.A1 n14_adj_7
+CTOF_DEL    ---     0.495    SLICE_70.A1 to    SLICE_70.F1 SLICE_70
+ROUTE         1   e 0.001    SLICE_70.F1 to   SLICE_70.DI1 wb_adr_7_N_60_4 (to RCLK_c)
+                  --------
+                   13.757   (33.7% logic, 66.3% route), 9 logic levels.
+
+Report:   13.923ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.343ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_536  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     5.791ns  (78.7% logic, 21.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_54 and
+      5.791ns delay SLICE_54 to RA[10] (totaling 8.157ns) meets
+     12.500ns offset RCLK to RA[10] by 4.343ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_54:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_54.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_54 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_54.CLK to    SLICE_54.Q0 SLICE_54 (from RCLK_c)
+ROUTE         1   e 1.234    SLICE_54.Q0 to       64.PADDO n1975
+DOPAD_DEL   ---     4.105       64.PADDO to         64.PAD RA[10]
+                  --------
+                    5.791   (78.7% logic, 21.3% route), 2 logic levels.
+
+Report:    8.157ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[9] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[9] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_151.C0 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_151.C0 to   SLICE_151.F0 SLICE_151
+ROUTE         1   e 1.234   SLICE_151.F0 to       62.PADDO RA_c_9
+DOPAD_DEL   ---     4.105       62.PADDO to         62.PAD RA[9]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[8] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[8] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_163.C1 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_163.C1 to   SLICE_163.F1 SLICE_163
+ROUTE         1   e 1.234   SLICE_163.F1 to       65.PADDO RA_c_8
+DOPAD_DEL   ---     4.105       65.PADDO to         65.PAD RA[8]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[7] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[7] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_155.C1 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_155.C1 to   SLICE_155.F1 SLICE_155
+ROUTE         1   e 1.234   SLICE_155.F1 to       75.PADDO RA_c_7
+DOPAD_DEL   ---     4.105       75.PADDO to         75.PAD RA[7]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[6] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[6] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_163.C0 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_163.C0 to   SLICE_163.F0 SLICE_163
+ROUTE         1   e 1.234   SLICE_163.F0 to       68.PADDO RA_c_6
+DOPAD_DEL   ---     4.105       68.PADDO to         68.PAD RA[6]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[5] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[5] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_157.C1 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_157.C1 to   SLICE_157.F1 SLICE_157
+ROUTE         1   e 1.234   SLICE_157.F1 to       70.PADDO RA_c_5
+DOPAD_DEL   ---     4.105       70.PADDO to         70.PAD RA[5]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[4] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[4] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_158.C1 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_158.C1 to   SLICE_158.F1 SLICE_158
+ROUTE         1   e 1.234   SLICE_158.F1 to       74.PADDO RA_c_4
+DOPAD_DEL   ---     4.105       74.PADDO to         74.PAD RA[4]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[3] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[3] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_162.C0 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_162.C0 to   SLICE_162.F0 SLICE_162
+ROUTE         1   e 1.234   SLICE_162.F0 to       71.PADDO RA_c_3
+DOPAD_DEL   ---     4.105       71.PADDO to         71.PAD RA[3]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[2] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[2] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_161.C0 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_161.C0 to   SLICE_161.F0 SLICE_161
+ROUTE         1   e 1.234   SLICE_161.F0 to       69.PADDO RA_c_2
+DOPAD_DEL   ---     4.105       69.PADDO to         69.PAD RA[2]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[1] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[1] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_162.C1 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_162.C1 to   SLICE_162.F1 SLICE_162
+ROUTE         1   e 1.234   SLICE_162.F1 to       67.PADDO RA_c_1
+DOPAD_DEL   ---     4.105       67.PADDO to         67.PAD RA[1]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[0] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[0] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_159.C1 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_159.C1 to   SLICE_159.F1 SLICE_159
+ROUTE         1   e 1.234   SLICE_159.F1 to       66.PADDO RA_c_0
+DOPAD_DEL   ---     4.105       66.PADDO to         66.PAD RA[0]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.343ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_532  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     5.791ns  (78.7% logic, 21.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_59 and
+      5.791ns delay SLICE_59 to nRCS (totaling 8.157ns) meets
+     12.500ns offset RCLK to nRCS by 4.343ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_59:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_59.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_59 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_59.CLK to    SLICE_59.Q0 SLICE_59 (from RCLK_c)
+ROUTE         1   e 1.234    SLICE_59.Q0 to       57.PADDO nRCS_c
+DOPAD_DEL   ---     4.105       57.PADDO to         57.PAD nRCS
+                  --------
+                    5.791   (78.7% logic, 21.3% route), 2 logic levels.
+
+Report:    8.157ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.343ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_531  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     5.791ns  (78.7% logic, 21.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_35 and
+      5.791ns delay SLICE_35 to RCKE (totaling 8.157ns) meets
+     12.500ns offset RCLK to RCKE by 4.343ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_35:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_35.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_35 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_35.CLK to    SLICE_35.Q0 SLICE_35 (from RCLK_c)
+ROUTE         4   e 1.234    SLICE_35.Q0 to       53.PADDO RCKE_c
+DOPAD_DEL   ---     4.105       53.PADDO to         53.PAD RCKE
+                  --------
+                    5.791   (78.7% logic, 21.3% route), 2 logic levels.
+
+Report:    8.157ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.343ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_535  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     5.791ns  (78.7% logic, 21.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_62 and
+      5.791ns delay SLICE_62 to nRWE (totaling 8.157ns) meets
+     12.500ns offset RCLK to nRWE by 4.343ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_62:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_62.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_62 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_62.CLK to    SLICE_62.Q0 SLICE_62 (from RCLK_c)
+ROUTE         1   e 1.234    SLICE_62.Q0 to       49.PADDO nRWE_c
+DOPAD_DEL   ---     4.105       49.PADDO to         49.PAD nRWE
+                  --------
+                    5.791   (78.7% logic, 21.3% route), 2 logic levels.
+
+Report:    8.157ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.343ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_533  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     5.791ns  (78.7% logic, 21.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_60 and
+      5.791ns delay SLICE_60 to nRRAS (totaling 8.157ns) meets
+     12.500ns offset RCLK to nRRAS by 4.343ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_60.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_60 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_60.CLK to    SLICE_60.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1   e 1.234    SLICE_60.Q0 to       54.PADDO nRRAS_c
+DOPAD_DEL   ---     4.105       54.PADDO to         54.PAD nRRAS
+                  --------
+                    5.791   (78.7% logic, 21.3% route), 2 logic levels.
+
+Report:    8.157ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.343ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_534  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     5.791ns  (78.7% logic, 21.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_57 and
+      5.791ns delay SLICE_57 to nRCAS (totaling 8.157ns) meets
+     12.500ns offset RCLK to nRCAS by 4.343ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_57.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_57 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_57.CLK to    SLICE_57.Q0 SLICE_57 (from RCLK_c)
+ROUTE         1   e 1.234    SLICE_57.Q0 to       52.PADDO nRCAS_c
+DOPAD_DEL   ---     4.105       52.PADDO to         52.PAD nRCAS
+                  --------
+                    5.791   (78.7% logic, 21.3% route), 2 logic levels.
+
+Report:    8.157ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RDQMH (totaling 9.886ns) meets
+     12.500ns offset RCLK to RDQMH by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_151.B1 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_151.B1 to   SLICE_151.F1 SLICE_151
+ROUTE         1   e 1.234   SLICE_151.F1 to       51.PADDO RDQMH_c
+DOPAD_DEL   ---     4.105       51.PADDO to         51.PAD RDQMH
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RDQML (totaling 9.886ns) meets
+     12.500ns offset RCLK to RDQML by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_161.B1 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_161.B1 to   SLICE_161.F1 SLICE_161
+ROUTE         1   e 1.234   SLICE_161.F1 to       48.PADDO RDQML_c
+DOPAD_DEL   ---     4.105       48.PADDO to         48.PAD RDQML
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |   350.000 ns|    26.684 ns|   8  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |   350.000 ns|     2.500 ns|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |   350.000 ns|     2.500 ns|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |    16.000 ns|    13.923 ns|   9  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.157 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.157 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.157 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.157 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.157 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.157 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 5 clocks:
+
+Clock Domain: wb_clk   Source: SLICE_73.Q0   Loads: 1
+   No transfer within this clock domain is found
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 52
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: wb_clk   Source: SLICE_73.Q0
+      Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;   Transfers: 2
+
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 1548 paths, 9 nets, and 889 connections (78.60% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
+Tue Aug 17 06:20:51 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_640hc_impl1_map.ncd
+Preference file: ram2gs_lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,M
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+VCCIO Voltage:
+                   3.135 V (Bank 0)
+                   3.135 V (Bank 1)
+                   3.135 V (Bank 2)
+                   3.135 V (Bank 3)
+                   2.375 V (Bank 4)
+                   2.375 V (Bank 5)
+                   2.375 V (Bank 6)
+                   2.375 V (Bank 7)
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            121 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.447ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_542  (from PHI2_c -)
+   Destination:    FF         Data in        C1Submitted_542  (to PHI2_c -)
+
+   Delay:               0.434ns  (53.9% logic, 46.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.434ns physical path delay SLICE_15 to SLICE_15 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
+
+ Physical Path Details:
+
+      Data path SLICE_15 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_15.CLK to    SLICE_15.Q0 SLICE_15 (from PHI2_c)
+ROUTE         2   e 0.199    SLICE_15.Q0 to    SLICE_15.D0 C1Submitted
+CTOF_DEL    ---     0.101    SLICE_15.D0 to    SLICE_15.F0 SLICE_15
+ROUTE         1   e 0.001    SLICE_15.F0 to   SLICE_15.DI0 n2549 (to PHI2_c)
+                  --------
+                    0.434   (53.9% logic, 46.1% route), 2 logic levels.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            1409 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.351ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i2  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i3  (to RCLK_c +)
+
+   Delay:               0.332ns  (40.1% logic, 59.9% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.332ns physical path delay SLICE_118 to SLICE_118 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns
+
+ Physical Path Details:
+
+      Data path SLICE_118 to SLICE_118:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133  SLICE_118.CLK to   SLICE_118.Q0 SLICE_118 (from RCLK_c)
+ROUTE         1   e 0.199   SLICE_118.Q0 to   SLICE_118.M1 n1197 (to RCLK_c)
+                  --------
+                    0.332   (40.1% logic, 59.9% route), 1 logic levels.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.284ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_536  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     2.321ns  (77.8% logic, 22.2% route), 2 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_54 and
+      2.321ns delay SLICE_54 to RA[10] (totaling 3.284ns) meets
+      0.000ns hold offset RCLK to RA[10] by 3.284ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_54:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_54.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_54 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_54.CLK to    SLICE_54.Q0 SLICE_54 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_54.Q0 to       64.PADDO n1975
+DOPAD_DEL   ---     1.673       64.PADDO to         64.PAD RA[10]
+                  --------
+                    2.321   (77.8% logic, 22.2% route), 2 logic levels.
+
+Report:    3.284ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[9] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[9] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_151.C0 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_151.C0 to   SLICE_151.F0 SLICE_151
+ROUTE         1   e 0.515   SLICE_151.F0 to       62.PADDO RA_c_9
+DOPAD_DEL   ---     1.673       62.PADDO to         62.PAD RA[9]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[8] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[8] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_163.C1 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_163.C1 to   SLICE_163.F1 SLICE_163
+ROUTE         1   e 0.515   SLICE_163.F1 to       65.PADDO RA_c_8
+DOPAD_DEL   ---     1.673       65.PADDO to         65.PAD RA[8]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[7] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[7] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_155.C1 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_155.C1 to   SLICE_155.F1 SLICE_155
+ROUTE         1   e 0.515   SLICE_155.F1 to       75.PADDO RA_c_7
+DOPAD_DEL   ---     1.673       75.PADDO to         75.PAD RA[7]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[6] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[6] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_163.C0 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_163.C0 to   SLICE_163.F0 SLICE_163
+ROUTE         1   e 0.515   SLICE_163.F0 to       68.PADDO RA_c_6
+DOPAD_DEL   ---     1.673       68.PADDO to         68.PAD RA[6]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[5] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[5] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_157.C1 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_157.C1 to   SLICE_157.F1 SLICE_157
+ROUTE         1   e 0.515   SLICE_157.F1 to       70.PADDO RA_c_5
+DOPAD_DEL   ---     1.673       70.PADDO to         70.PAD RA[5]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[4] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[4] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_158.C1 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_158.C1 to   SLICE_158.F1 SLICE_158
+ROUTE         1   e 0.515   SLICE_158.F1 to       74.PADDO RA_c_4
+DOPAD_DEL   ---     1.673       74.PADDO to         74.PAD RA[4]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[3] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[3] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_162.C0 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_162.C0 to   SLICE_162.F0 SLICE_162
+ROUTE         1   e 0.515   SLICE_162.F0 to       71.PADDO RA_c_3
+DOPAD_DEL   ---     1.673       71.PADDO to         71.PAD RA[3]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[2] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[2] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_161.C0 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_161.C0 to   SLICE_161.F0 SLICE_161
+ROUTE         1   e 0.515   SLICE_161.F0 to       69.PADDO RA_c_2
+DOPAD_DEL   ---     1.673       69.PADDO to         69.PAD RA[2]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[1] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[1] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_162.C1 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_162.C1 to   SLICE_162.F1 SLICE_162
+ROUTE         1   e 0.515   SLICE_162.F1 to       67.PADDO RA_c_1
+DOPAD_DEL   ---     1.673       67.PADDO to         67.PAD RA[1]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[0] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[0] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_159.C1 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_159.C1 to   SLICE_159.F1 SLICE_159
+ROUTE         1   e 0.515   SLICE_159.F1 to       66.PADDO RA_c_0
+DOPAD_DEL   ---     1.673       66.PADDO to         66.PAD RA[0]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.284ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_532  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     2.321ns  (77.8% logic, 22.2% route), 2 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_59 and
+      2.321ns delay SLICE_59 to nRCS (totaling 3.284ns) meets
+      0.000ns hold offset RCLK to nRCS by 3.284ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_59:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_59.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_59 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_59.CLK to    SLICE_59.Q0 SLICE_59 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_59.Q0 to       57.PADDO nRCS_c
+DOPAD_DEL   ---     1.673       57.PADDO to         57.PAD nRCS
+                  --------
+                    2.321   (77.8% logic, 22.2% route), 2 logic levels.
+
+Report:    3.284ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.284ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_531  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     2.321ns  (77.8% logic, 22.2% route), 2 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_35 and
+      2.321ns delay SLICE_35 to RCKE (totaling 3.284ns) meets
+      0.000ns hold offset RCLK to RCKE by 3.284ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_35:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_35.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_35 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_35.CLK to    SLICE_35.Q0 SLICE_35 (from RCLK_c)
+ROUTE         4   e 0.515    SLICE_35.Q0 to       53.PADDO RCKE_c
+DOPAD_DEL   ---     1.673       53.PADDO to         53.PAD RCKE
+                  --------
+                    2.321   (77.8% logic, 22.2% route), 2 logic levels.
+
+Report:    3.284ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.284ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_535  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     2.321ns  (77.8% logic, 22.2% route), 2 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_62 and
+      2.321ns delay SLICE_62 to nRWE (totaling 3.284ns) meets
+      0.000ns hold offset RCLK to nRWE by 3.284ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_62:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_62.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_62 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_62.CLK to    SLICE_62.Q0 SLICE_62 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_62.Q0 to       49.PADDO nRWE_c
+DOPAD_DEL   ---     1.673       49.PADDO to         49.PAD nRWE
+                  --------
+                    2.321   (77.8% logic, 22.2% route), 2 logic levels.
+
+Report:    3.284ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.284ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_533  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     2.321ns  (77.8% logic, 22.2% route), 2 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_60 and
+      2.321ns delay SLICE_60 to nRRAS (totaling 3.284ns) meets
+      0.000ns hold offset RCLK to nRRAS by 3.284ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_60.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_60 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_60.CLK to    SLICE_60.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_60.Q0 to       54.PADDO nRRAS_c
+DOPAD_DEL   ---     1.673       54.PADDO to         54.PAD nRRAS
+                  --------
+                    2.321   (77.8% logic, 22.2% route), 2 logic levels.
+
+Report:    3.284ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.284ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_534  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     2.321ns  (77.8% logic, 22.2% route), 2 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_57 and
+      2.321ns delay SLICE_57 to nRCAS (totaling 3.284ns) meets
+      0.000ns hold offset RCLK to nRCAS by 3.284ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_57.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_57 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_57.CLK to    SLICE_57.Q0 SLICE_57 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_57.Q0 to       52.PADDO nRCAS_c
+DOPAD_DEL   ---     1.673       52.PADDO to         52.PAD nRCAS
+                  --------
+                    2.321   (77.8% logic, 22.2% route), 2 logic levels.
+
+Report:    3.284ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RDQMH (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RDQMH by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_151.B1 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_151.B1 to   SLICE_151.F1 SLICE_151
+ROUTE         1   e 0.515   SLICE_151.F1 to       51.PADDO RDQMH_c
+DOPAD_DEL   ---     1.673       51.PADDO to         51.PAD RDQMH
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RDQML (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RDQML by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_161.B1 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_161.B1 to   SLICE_161.F1 SLICE_161
+ROUTE         1   e 0.515   SLICE_161.F1 to       48.PADDO RDQML_c
+DOPAD_DEL   ---     1.673       48.PADDO to         48.PAD RDQML
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |            -|            -|   2  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |            -|            -|   1  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.284 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.284 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.284 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.284 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.284 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.284 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 5 clocks:
+
+Clock Domain: wb_clk   Source: SLICE_73.Q0   Loads: 1
+   No transfer within this clock domain is found
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 52
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: wb_clk   Source: SLICE_73.Q0
+      Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;   Transfers: 2
+
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 1548 paths, 9 nets, and 889 connections (78.60% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 0 (setup), 0 (hold)
+Score: 0 (setup), 0 (hold)
+Cumulative negative slack: 0 (0+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.twr b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.twr
new file mode 100644
index 0000000..56e0a5c
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.twr
@@ -0,0 +1,4466 @@
+
+Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
+Tue Aug 17 06:21:01 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_640hc_impl1.ncd
+Preference file: ram2gs_lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,4
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+VCCIO Voltage:
+                   3.135 V (Bank 0)
+                   3.135 V (Bank 1)
+                   3.135 V (Bank 2)
+                   3.135 V (Bank 3)
+                   2.375 V (Bank 4)
+                   2.375 V (Bank 5)
+                   2.375 V (Bank 6)
+                   2.375 V (Bank 7)
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            121 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 162.100ns (weighted slack = 324.200ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        CmdLEDEN_545  (to PHI2_c -)
+
+   Delay:              12.593ns  (31.1% logic, 68.9% route), 8 logic levels.
+
+ Constraint Details:
+
+     12.593ns physical path delay SLICE_151 to SLICE_20 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 162.100ns
+
+ Physical Path Details:
+
+      Data path SLICE_151 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R5C9B.CLK to       R5C9B.Q0 SLICE_151 (from PHI2_c)
+ROUTE         1     1.278       R5C9B.Q0 to       R2C8B.C0 Bank_6
+CTOF_DEL    ---     0.495       R2C8B.C0 to       R2C8B.F0 SLICE_158
+ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
+CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
+CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
+ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
+CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
+ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     1.084       R5C8D.F1 to       R5C6A.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                   12.593   (31.1% logic, 68.9% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_151:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C9B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C6A.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.100ns (weighted slack = 324.200ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        Cmdn8MEGEN_546  (to PHI2_c -)
+
+   Delay:              12.593ns  (31.1% logic, 68.9% route), 8 logic levels.
+
+ Constraint Details:
+
+     12.593ns physical path delay SLICE_151 to SLICE_24 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 162.100ns
+
+ Physical Path Details:
+
+      Data path SLICE_151 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R5C9B.CLK to       R5C9B.Q0 SLICE_151 (from PHI2_c)
+ROUTE         1     1.278       R5C9B.Q0 to       R2C8B.C0 Bank_6
+CTOF_DEL    ---     0.495       R2C8B.C0 to       R2C8B.F0 SLICE_158
+ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
+CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
+CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
+ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
+CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
+ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     1.084       R5C8D.F1 to       R5C6B.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                   12.593   (31.1% logic, 68.9% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_151:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C9B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C6B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.374ns (weighted slack = 324.748ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i4  (from PHI2_c +)
+   Destination:    FF         Data in        CmdLEDEN_545  (to PHI2_c -)
+
+   Delay:              12.319ns  (31.8% logic, 68.2% route), 8 logic levels.
+
+ Constraint Details:
+
+     12.319ns physical path delay SLICE_111 to SLICE_20 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 162.374ns
+
+ Physical Path Details:
+
+      Data path SLICE_111 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q0 SLICE_111 (from PHI2_c)
+ROUTE         1     1.004       R2C8C.Q0 to       R2C8B.B0 Bank_4
+CTOF_DEL    ---     0.495       R2C8B.B0 to       R2C8B.F0 SLICE_158
+ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
+CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
+CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
+ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
+CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
+ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     1.084       R5C8D.F1 to       R5C6A.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                   12.319   (31.8% logic, 68.2% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_111:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R2C8C.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C6A.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.374ns (weighted slack = 324.748ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i4  (from PHI2_c +)
+   Destination:    FF         Data in        Cmdn8MEGEN_546  (to PHI2_c -)
+
+   Delay:              12.319ns  (31.8% logic, 68.2% route), 8 logic levels.
+
+ Constraint Details:
+
+     12.319ns physical path delay SLICE_111 to SLICE_24 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 162.374ns
+
+ Physical Path Details:
+
+      Data path SLICE_111 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q0 SLICE_111 (from PHI2_c)
+ROUTE         1     1.004       R2C8C.Q0 to       R2C8B.B0 Bank_4
+CTOF_DEL    ---     0.495       R2C8B.B0 to       R2C8B.F0 SLICE_158
+ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
+CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
+CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
+ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
+CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
+ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     1.084       R5C8D.F1 to       R5C6B.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                   12.319   (31.8% logic, 68.2% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_111:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R2C8C.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C6B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.411ns (weighted slack = 324.822ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i5  (from PHI2_c +)
+   Destination:    FF         Data in        CmdLEDEN_545  (to PHI2_c -)
+
+   Delay:              12.282ns  (31.9% logic, 68.1% route), 8 logic levels.
+
+ Constraint Details:
+
+     12.282ns physical path delay SLICE_111 to SLICE_20 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 162.411ns
+
+ Physical Path Details:
+
+      Data path SLICE_111 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q1 SLICE_111 (from PHI2_c)
+ROUTE         1     0.967       R2C8C.Q1 to       R2C8B.A0 Bank_5
+CTOF_DEL    ---     0.495       R2C8B.A0 to       R2C8B.F0 SLICE_158
+ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
+CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
+CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
+ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
+CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
+ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     1.084       R5C8D.F1 to       R5C6A.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                   12.282   (31.9% logic, 68.1% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_111:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R2C8C.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C6A.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.411ns (weighted slack = 324.822ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i5  (from PHI2_c +)
+   Destination:    FF         Data in        Cmdn8MEGEN_546  (to PHI2_c -)
+
+   Delay:              12.282ns  (31.9% logic, 68.1% route), 8 logic levels.
+
+ Constraint Details:
+
+     12.282ns physical path delay SLICE_111 to SLICE_24 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 162.411ns
+
+ Physical Path Details:
+
+      Data path SLICE_111 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q1 SLICE_111 (from PHI2_c)
+ROUTE         1     0.967       R2C8C.Q1 to       R2C8B.A0 Bank_5
+CTOF_DEL    ---     0.495       R2C8B.A0 to       R2C8B.F0 SLICE_158
+ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
+CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
+CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
+ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
+CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
+ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     1.084       R5C8D.F1 to       R5C6B.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                   12.282   (31.9% logic, 68.1% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_111:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R2C8C.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C6B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 163.336ns (weighted slack = 326.672ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_541  (to PHI2_c -)
+
+   Delay:              11.357ns  (34.5% logic, 65.5% route), 8 logic levels.
+
+ Constraint Details:
+
+     11.357ns physical path delay SLICE_151 to SLICE_19 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 163.336ns
+
+ Physical Path Details:
+
+      Data path SLICE_151 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R5C9B.CLK to       R5C9B.Q0 SLICE_151 (from PHI2_c)
+ROUTE         1     1.278       R5C9B.Q0 to       R2C8B.C0 Bank_6
+CTOF_DEL    ---     0.495       R2C8B.C0 to       R2C8B.F0 SLICE_158
+ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
+CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.756       R2C9D.F1 to       R2C9B.C1 n2384
+CTOF_DEL    ---     0.495       R2C9B.C1 to       R2C9B.F1 SLICE_116
+ROUTE         2     0.445       R2C9B.F1 to       R2C9B.C0 n4888
+CTOF_DEL    ---     0.495       R2C9B.C0 to       R2C9B.F0 SLICE_116
+ROUTE         1     0.645       R2C9B.F0 to       R3C9A.D1 n4624
+CTOF_DEL    ---     0.495       R3C9A.D1 to       R3C9A.F1 SLICE_19
+ROUTE         4     1.042       R3C9A.F1 to       R3C9D.B0 C1Submitted_N_232
+CTOF_DEL    ---     0.495       R3C9D.B0 to       R3C9D.F0 SLICE_130
+ROUTE         1     0.653       R3C9D.F0 to       R3C9A.CE PHI2_N_151_enable_1 (to PHI2_c)
+                  --------
+                   11.357   (34.5% logic, 65.5% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_151:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C9B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R3C9A.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 163.510ns (weighted slack = 327.020ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdLEDEN_545  (to PHI2_c -)
+
+   Delay:              11.183ns  (35.0% logic, 65.0% route), 8 logic levels.
+
+ Constraint Details:
+
+     11.183ns physical path delay SLICE_151 to SLICE_20 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 163.510ns
+
+ Physical Path Details:
+
+      Data path SLICE_151 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R5C9B.CLK to       R5C9B.Q1 SLICE_151 (from PHI2_c)
+ROUTE         1     0.967       R5C9B.Q1 to       R5C9D.A1 Bank_7
+CTOF_DEL    ---     0.495       R5C9D.A1 to       R5C9D.F1 SLICE_139
+ROUTE         1     0.436       R5C9D.F1 to       R5C9D.C0 n4574
+CTOF_DEL    ---     0.495       R5C9D.C0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
+CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
+ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
+CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
+ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     1.084       R5C8D.F1 to       R5C6A.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                   11.183   (35.0% logic, 65.0% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_151:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C9B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C6A.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 163.510ns (weighted slack = 327.020ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        Cmdn8MEGEN_546  (to PHI2_c -)
+
+   Delay:              11.183ns  (35.0% logic, 65.0% route), 8 logic levels.
+
+ Constraint Details:
+
+     11.183ns physical path delay SLICE_151 to SLICE_24 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 163.510ns
+
+ Physical Path Details:
+
+      Data path SLICE_151 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R5C9B.CLK to       R5C9B.Q1 SLICE_151 (from PHI2_c)
+ROUTE         1     0.967       R5C9B.Q1 to       R5C9D.A1 Bank_7
+CTOF_DEL    ---     0.495       R5C9D.A1 to       R5C9D.F1 SLICE_139
+ROUTE         1     0.436       R5C9D.F1 to       R5C9D.C0 n4574
+CTOF_DEL    ---     0.495       R5C9D.C0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
+CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
+ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
+CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
+ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     1.084       R5C8D.F1 to       R5C6B.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                   11.183   (35.0% logic, 65.0% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_151:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C9B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C6B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 163.610ns (weighted slack = 327.220ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i4  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_541  (to PHI2_c -)
+
+   Delay:              11.083ns  (35.3% logic, 64.7% route), 8 logic levels.
+
+ Constraint Details:
+
+     11.083ns physical path delay SLICE_111 to SLICE_19 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 163.610ns
+
+ Physical Path Details:
+
+      Data path SLICE_111 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q0 SLICE_111 (from PHI2_c)
+ROUTE         1     1.004       R2C8C.Q0 to       R2C8B.B0 Bank_4
+CTOF_DEL    ---     0.495       R2C8B.B0 to       R2C8B.F0 SLICE_158
+ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
+CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.756       R2C9D.F1 to       R2C9B.C1 n2384
+CTOF_DEL    ---     0.495       R2C9B.C1 to       R2C9B.F1 SLICE_116
+ROUTE         2     0.445       R2C9B.F1 to       R2C9B.C0 n4888
+CTOF_DEL    ---     0.495       R2C9B.C0 to       R2C9B.F0 SLICE_116
+ROUTE         1     0.645       R2C9B.F0 to       R3C9A.D1 n4624
+CTOF_DEL    ---     0.495       R3C9A.D1 to       R3C9A.F1 SLICE_19
+ROUTE         4     1.042       R3C9A.F1 to       R3C9D.B0 C1Submitted_N_232
+CTOF_DEL    ---     0.495       R3C9D.B0 to       R3C9D.F0 SLICE_130
+ROUTE         1     0.653       R3C9D.F0 to       R3C9A.CE PHI2_N_151_enable_1 (to PHI2_c)
+                  --------
+                   11.083   (35.3% logic, 64.7% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_111:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R2C8C.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R3C9A.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:   25.800ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 347.500ns
+         The internal maximum frequency of the following component is 400.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    SLICE      CLK            SLICE_122
+
+   Delay:               2.500ns -- based on Minimum Pulse Width
+
+Report:    2.500ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 347.500ns
+         The internal maximum frequency of the following component is 400.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    SLICE      CLK            SLICE_25
+
+   Delay:               2.500ns -- based on Minimum Pulse Width
+
+Report:    2.500ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            1409 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 3.573ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i6  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i4  (to RCLK_c +)
+
+   Delay:              12.261ns  (37.8% logic, 62.2% route), 9 logic levels.
+
+ Constraint Details:
+
+     12.261ns physical path delay SLICE_6 to SLICE_70 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 3.573ns
+
+ Physical Path Details:
+
+      Data path SLICE_6 to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C6D.CLK to       R6C6D.Q1 SLICE_6 (from RCLK_c)
+ROUTE        21     1.808       R6C6D.Q1 to       R3C7A.B1 FS_6
+CTOF_DEL    ---     0.495       R3C7A.B1 to       R3C7A.F1 SLICE_98
+ROUTE         4     1.021       R3C7A.F1 to       R3C7D.B1 n4924
+CTOF_DEL    ---     0.495       R3C7D.B1 to       R3C7D.F1 SLICE_93
+ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
+CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
+ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
+CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3A.D1 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3A.D1 to       R2C3A.F1 SLICE_70
+ROUTE         1     0.000       R2C3A.F1 to      R2C3A.DI1 wb_adr_7_N_60_4 (to RCLK_c)
+                  --------
+                   12.261   (37.8% logic, 62.2% route), 9 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C6D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3A.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 3.573ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i6  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i6  (to RCLK_c +)
+
+   Delay:              12.261ns  (37.8% logic, 62.2% route), 9 logic levels.
+
+ Constraint Details:
+
+     12.261ns physical path delay SLICE_6 to SLICE_72 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 3.573ns
+
+ Physical Path Details:
+
+      Data path SLICE_6 to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C6D.CLK to       R6C6D.Q1 SLICE_6 (from RCLK_c)
+ROUTE        21     1.808       R6C6D.Q1 to       R3C7A.B1 FS_6
+CTOF_DEL    ---     0.495       R3C7A.B1 to       R3C7A.F1 SLICE_98
+ROUTE         4     1.021       R3C7A.F1 to       R3C7D.B1 n4924
+CTOF_DEL    ---     0.495       R3C7D.B1 to       R3C7D.F1 SLICE_93
+ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
+CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
+ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
+CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3D.D0 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3D.D0 to       R2C3D.F0 SLICE_72
+ROUTE         1     0.000       R2C3D.F0 to      R2C3D.DI0 wb_adr_7_N_60_6 (to RCLK_c)
+                  --------
+                   12.261   (37.8% logic, 62.2% route), 9 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C6D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 4.370ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i7  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i4  (to RCLK_c +)
+
+   Delay:              11.464ns  (36.1% logic, 63.9% route), 8 logic levels.
+
+ Constraint Details:
+
+     11.464ns physical path delay SLICE_5 to SLICE_70 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.370ns
+
+ Physical Path Details:
+
+      Data path SLICE_5 to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C7A.CLK to       R6C7A.Q0 SLICE_5 (from RCLK_c)
+ROUTE        25     2.442       R6C7A.Q0 to       R2C8D.C1 FS_7
+CTOF_DEL    ---     0.495       R2C8D.C1 to       R2C8D.F1 SLICE_143
+ROUTE         2     1.427       R2C8D.F1 to       R2C6A.B1 n4915
+CTOF_DEL    ---     0.495       R2C6A.B1 to       R2C6A.F1 SLICE_113
+ROUTE         5     0.672       R2C6A.F1 to       R2C7D.D1 n4890
+CTOF_DEL    ---     0.495       R2C7D.D1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3A.D1 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3A.D1 to       R2C3A.F1 SLICE_70
+ROUTE         1     0.000       R2C3A.F1 to      R2C3A.DI1 wb_adr_7_N_60_4 (to RCLK_c)
+                  --------
+                   11.464   (36.1% logic, 63.9% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C7A.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3A.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 4.370ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i7  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i6  (to RCLK_c +)
+
+   Delay:              11.464ns  (36.1% logic, 63.9% route), 8 logic levels.
+
+ Constraint Details:
+
+     11.464ns physical path delay SLICE_5 to SLICE_72 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.370ns
+
+ Physical Path Details:
+
+      Data path SLICE_5 to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C7A.CLK to       R6C7A.Q0 SLICE_5 (from RCLK_c)
+ROUTE        25     2.442       R6C7A.Q0 to       R2C8D.C1 FS_7
+CTOF_DEL    ---     0.495       R2C8D.C1 to       R2C8D.F1 SLICE_143
+ROUTE         2     1.427       R2C8D.F1 to       R2C6A.B1 n4915
+CTOF_DEL    ---     0.495       R2C6A.B1 to       R2C6A.F1 SLICE_113
+ROUTE         5     0.672       R2C6A.F1 to       R2C7D.D1 n4890
+CTOF_DEL    ---     0.495       R2C7D.D1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3D.D0 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3D.D0 to       R2C3D.F0 SLICE_72
+ROUTE         1     0.000       R2C3D.F0 to      R2C3D.DI0 wb_adr_7_N_60_6 (to RCLK_c)
+                  --------
+                   11.464   (36.1% logic, 63.9% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C7A.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 4.376ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i8  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i4  (to RCLK_c +)
+
+   Delay:              11.458ns  (40.5% logic, 59.5% route), 9 logic levels.
+
+ Constraint Details:
+
+     11.458ns physical path delay SLICE_5 to SLICE_70 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.376ns
+
+ Physical Path Details:
+
+      Data path SLICE_5 to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C7A.CLK to       R6C7A.Q1 SLICE_5 (from RCLK_c)
+ROUTE        23     1.005       R6C7A.Q1 to       R3C7A.D1 FS_8
+CTOF_DEL    ---     0.495       R3C7A.D1 to       R3C7A.F1 SLICE_98
+ROUTE         4     1.021       R3C7A.F1 to       R3C7D.B1 n4924
+CTOF_DEL    ---     0.495       R3C7D.B1 to       R3C7D.F1 SLICE_93
+ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
+CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
+ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
+CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3A.D1 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3A.D1 to       R2C3A.F1 SLICE_70
+ROUTE         1     0.000       R2C3A.F1 to      R2C3A.DI1 wb_adr_7_N_60_4 (to RCLK_c)
+                  --------
+                   11.458   (40.5% logic, 59.5% route), 9 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C7A.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3A.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 4.376ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i8  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i6  (to RCLK_c +)
+
+   Delay:              11.458ns  (40.5% logic, 59.5% route), 9 logic levels.
+
+ Constraint Details:
+
+     11.458ns physical path delay SLICE_5 to SLICE_72 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.376ns
+
+ Physical Path Details:
+
+      Data path SLICE_5 to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C7A.CLK to       R6C7A.Q1 SLICE_5 (from RCLK_c)
+ROUTE        23     1.005       R6C7A.Q1 to       R3C7A.D1 FS_8
+CTOF_DEL    ---     0.495       R3C7A.D1 to       R3C7A.F1 SLICE_98
+ROUTE         4     1.021       R3C7A.F1 to       R3C7D.B1 n4924
+CTOF_DEL    ---     0.495       R3C7D.B1 to       R3C7D.F1 SLICE_93
+ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
+CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
+ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
+CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3D.D0 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3D.D0 to       R2C3D.F0 SLICE_72
+ROUTE         1     0.000       R2C3D.F0 to      R2C3D.DI0 wb_adr_7_N_60_6 (to RCLK_c)
+                  --------
+                   11.458   (40.5% logic, 59.5% route), 9 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C7A.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 4.398ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i6  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i4  (to RCLK_c +)
+
+   Delay:              11.436ns  (40.6% logic, 59.4% route), 9 logic levels.
+
+ Constraint Details:
+
+     11.436ns physical path delay SLICE_6 to SLICE_70 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.398ns
+
+ Physical Path Details:
+
+      Data path SLICE_6 to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C6D.CLK to       R6C6D.Q1 SLICE_6 (from RCLK_c)
+ROUTE        21     1.551       R6C6D.Q1 to       R3C7D.C0 FS_6
+CTOF_DEL    ---     0.495       R3C7D.C0 to       R3C7D.F0 SLICE_93
+ROUTE         3     0.453       R3C7D.F0 to       R3C7D.C1 n53_adj_9
+CTOF_DEL    ---     0.495       R3C7D.C1 to       R3C7D.F1 SLICE_93
+ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
+CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
+ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
+CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3A.D1 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3A.D1 to       R2C3A.F1 SLICE_70
+ROUTE         1     0.000       R2C3A.F1 to      R2C3A.DI1 wb_adr_7_N_60_4 (to RCLK_c)
+                  --------
+                   11.436   (40.6% logic, 59.4% route), 9 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C6D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3A.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 4.398ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i6  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i6  (to RCLK_c +)
+
+   Delay:              11.436ns  (40.6% logic, 59.4% route), 9 logic levels.
+
+ Constraint Details:
+
+     11.436ns physical path delay SLICE_6 to SLICE_72 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.398ns
+
+ Physical Path Details:
+
+      Data path SLICE_6 to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C6D.CLK to       R6C6D.Q1 SLICE_6 (from RCLK_c)
+ROUTE        21     1.551       R6C6D.Q1 to       R3C7D.C0 FS_6
+CTOF_DEL    ---     0.495       R3C7D.C0 to       R3C7D.F0 SLICE_93
+ROUTE         3     0.453       R3C7D.F0 to       R3C7D.C1 n53_adj_9
+CTOF_DEL    ---     0.495       R3C7D.C1 to       R3C7D.F1 SLICE_93
+ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
+CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
+ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
+CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3D.D0 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3D.D0 to       R2C3D.F0 SLICE_72
+ROUTE         1     0.000       R2C3D.F0 to      R2C3D.DI0 wb_adr_7_N_60_6 (to RCLK_c)
+                  --------
+                   11.436   (40.6% logic, 59.4% route), 9 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C6D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 4.449ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i5  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i4  (to RCLK_c +)
+
+   Delay:              11.385ns  (40.7% logic, 59.3% route), 9 logic levels.
+
+ Constraint Details:
+
+     11.385ns physical path delay SLICE_6 to SLICE_70 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.449ns
+
+ Physical Path Details:
+
+      Data path SLICE_6 to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C6D.CLK to       R6C6D.Q0 SLICE_6 (from RCLK_c)
+ROUTE        21     1.500       R6C6D.Q0 to       R3C7D.D0 FS_5
+CTOF_DEL    ---     0.495       R3C7D.D0 to       R3C7D.F0 SLICE_93
+ROUTE         3     0.453       R3C7D.F0 to       R3C7D.C1 n53_adj_9
+CTOF_DEL    ---     0.495       R3C7D.C1 to       R3C7D.F1 SLICE_93
+ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
+CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
+ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
+CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3A.D1 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3A.D1 to       R2C3A.F1 SLICE_70
+ROUTE         1     0.000       R2C3A.F1 to      R2C3A.DI1 wb_adr_7_N_60_4 (to RCLK_c)
+                  --------
+                   11.385   (40.7% logic, 59.3% route), 9 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C6D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3A.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 4.449ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i5  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i6  (to RCLK_c +)
+
+   Delay:              11.385ns  (40.7% logic, 59.3% route), 9 logic levels.
+
+ Constraint Details:
+
+     11.385ns physical path delay SLICE_6 to SLICE_72 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.449ns
+
+ Physical Path Details:
+
+      Data path SLICE_6 to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C6D.CLK to       R6C6D.Q0 SLICE_6 (from RCLK_c)
+ROUTE        21     1.500       R6C6D.Q0 to       R3C7D.D0 FS_5
+CTOF_DEL    ---     0.495       R3C7D.D0 to       R3C7D.F0 SLICE_93
+ROUTE         3     0.453       R3C7D.F0 to       R3C7D.C1 n53_adj_9
+CTOF_DEL    ---     0.495       R3C7D.C1 to       R3C7D.F1 SLICE_93
+ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
+CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
+ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
+CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3D.D0 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3D.D0 to       R2C3D.F0 SLICE_72
+ROUTE         1     0.000       R2C3D.F0 to      R2C3D.DI0 wb_adr_7_N_60_6 (to RCLK_c)
+                  --------
+                   11.385   (40.7% logic, 59.3% route), 9 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C6D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:   12.427ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.015ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_536  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     6.334ns  (71.9% logic, 28.1% route), 2 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_54 and
+      6.334ns delay SLICE_54 to RA[10] (totaling 9.485ns) meets
+     12.500ns offset RCLK to RA[10] by 3.015ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_54:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R4C11D.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_54 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R4C11D.CLK to      R4C11D.Q0 SLICE_54 (from RCLK_c)
+ROUTE         1     1.777      R4C11D.Q0 to       64.PADDO n1975
+DOPAD_DEL   ---     4.105       64.PADDO to         64.PAD RA[10]
+                  --------
+                    6.334   (71.9% logic, 28.1% route), 2 logic levels.
+
+Report:    9.485ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.495ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     7.854ns  (64.3% logic, 35.7% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      7.854ns delay SLICE_63 to RA[9] (totaling 11.005ns) meets
+     12.500ns offset RCLK to RA[9] by 1.495ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     1.016      R5C10A.Q0 to       R5C9B.A0 nRowColSel
+CTOF_DEL    ---     0.495       R5C9B.A0 to       R5C9B.F0 SLICE_151
+ROUTE         1     1.786       R5C9B.F0 to       62.PADDO RA_c_9
+DOPAD_DEL   ---     4.105       62.PADDO to         62.PAD RA[9]
+                  --------
+                    7.854   (64.3% logic, 35.7% route), 3 logic levels.
+
+Report:   11.005ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.386ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     7.963ns  (63.4% logic, 36.6% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      7.963ns delay SLICE_63 to RA[8] (totaling 11.114ns) meets
+     12.500ns offset RCLK to RA[8] by 1.386ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     1.053      R5C10A.Q0 to      R4C10D.B1 nRowColSel
+CTOF_DEL    ---     0.495      R4C10D.B1 to      R4C10D.F1 SLICE_163
+ROUTE         1     1.858      R4C10D.F1 to       65.PADDO RA_c_8
+DOPAD_DEL   ---     4.105       65.PADDO to         65.PAD RA[8]
+                  --------
+                    7.963   (63.4% logic, 36.6% route), 3 logic levels.
+
+Report:   11.114ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.552ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     7.797ns  (64.8% logic, 35.2% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      7.797ns delay SLICE_63 to RA[7] (totaling 10.948ns) meets
+     12.500ns offset RCLK to RA[7] by 1.552ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     1.017      R5C10A.Q0 to      R2C10D.D1 nRowColSel
+CTOF_DEL    ---     0.495      R2C10D.D1 to      R2C10D.F1 SLICE_155
+ROUTE         1     1.728      R2C10D.F1 to       75.PADDO RA_c_7
+DOPAD_DEL   ---     4.105       75.PADDO to         75.PAD RA[7]
+                  --------
+                    7.797   (64.8% logic, 35.2% route), 3 logic levels.
+
+Report:   10.948ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.401ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     7.948ns  (63.6% logic, 36.4% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      7.948ns delay SLICE_63 to RA[6] (totaling 11.099ns) meets
+     12.500ns offset RCLK to RA[6] by 1.401ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     1.053      R5C10A.Q0 to      R4C10D.B0 nRowColSel
+CTOF_DEL    ---     0.495      R4C10D.B0 to      R4C10D.F0 SLICE_163
+ROUTE         1     1.843      R4C10D.F0 to       68.PADDO RA_c_6
+DOPAD_DEL   ---     4.105       68.PADDO to         68.PAD RA[6]
+                  --------
+                    7.948   (63.6% logic, 36.4% route), 3 logic levels.
+
+Report:   11.099ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.135ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     8.214ns  (61.5% logic, 38.5% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      8.214ns delay SLICE_63 to RA[5] (totaling 11.365ns) meets
+     12.500ns offset RCLK to RA[5] by 1.135ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     1.310      R5C10A.Q0 to       R2C9A.C1 nRowColSel
+CTOF_DEL    ---     0.495       R2C9A.C1 to       R2C9A.F1 SLICE_157
+ROUTE         1     1.852       R2C9A.F1 to       70.PADDO RA_c_5
+DOPAD_DEL   ---     4.105       70.PADDO to         70.PAD RA[5]
+                  --------
+                    8.214   (61.5% logic, 38.5% route), 3 logic levels.
+
+Report:   11.365ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.135ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     8.214ns  (61.5% logic, 38.5% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      8.214ns delay SLICE_63 to RA[4] (totaling 11.365ns) meets
+     12.500ns offset RCLK to RA[4] by 1.135ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     1.310      R5C10A.Q0 to       R2C8B.C1 nRowColSel
+CTOF_DEL    ---     0.495       R2C8B.C1 to       R2C8B.F1 SLICE_158
+ROUTE         1     1.852       R2C8B.F1 to       74.PADDO RA_c_4
+DOPAD_DEL   ---     4.105       74.PADDO to         74.PAD RA[4]
+                  --------
+                    8.214   (61.5% logic, 38.5% route), 3 logic levels.
+
+Report:   11.365ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.322ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     8.027ns  (62.9% logic, 37.1% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      8.027ns delay SLICE_63 to RA[3] (totaling 11.178ns) meets
+     12.500ns offset RCLK to RA[3] by 1.322ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.990      R5C10A.Q0 to      R3C10C.D0 nRowColSel
+CTOF_DEL    ---     0.495      R3C10C.D0 to      R3C10C.F0 SLICE_162
+ROUTE         1     1.985      R3C10C.F0 to       71.PADDO RA_c_3
+DOPAD_DEL   ---     4.105       71.PADDO to         71.PAD RA[3]
+                  --------
+                    8.027   (62.9% logic, 37.1% route), 3 logic levels.
+
+Report:   11.178ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.577ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     7.772ns  (65.0% logic, 35.0% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      7.772ns delay SLICE_63 to RA[2] (totaling 10.923ns) meets
+     12.500ns offset RCLK to RA[2] by 1.577ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.796      R5C10A.Q0 to       R5C9C.C0 nRowColSel
+CTOF_DEL    ---     0.495       R5C9C.C0 to       R5C9C.F0 SLICE_161
+ROUTE         1     1.924       R5C9C.F0 to       69.PADDO RA_c_2
+DOPAD_DEL   ---     4.105       69.PADDO to         69.PAD RA[2]
+                  --------
+                    7.772   (65.0% logic, 35.0% route), 3 logic levels.
+
+Report:   10.923ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.579ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     7.770ns  (65.0% logic, 35.0% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      7.770ns delay SLICE_63 to RA[1] (totaling 10.921ns) meets
+     12.500ns offset RCLK to RA[1] by 1.579ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.990      R5C10A.Q0 to      R3C10C.D1 nRowColSel
+CTOF_DEL    ---     0.495      R3C10C.D1 to      R3C10C.F1 SLICE_162
+ROUTE         1     1.728      R3C10C.F1 to       67.PADDO RA_c_1
+DOPAD_DEL   ---     4.105       67.PADDO to         67.PAD RA[1]
+                  --------
+                    7.770   (65.0% logic, 35.0% route), 3 logic levels.
+
+Report:   10.921ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.855ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     7.494ns  (67.4% logic, 32.6% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      7.494ns delay SLICE_63 to RA[0] (totaling 10.645ns) meets
+     12.500ns offset RCLK to RA[0] by 1.855ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     1.017      R5C10A.Q0 to      R3C10D.D1 nRowColSel
+CTOF_DEL    ---     0.495      R3C10D.D1 to      R3C10D.F1 SLICE_159
+ROUTE         1     1.425      R3C10D.F1 to       66.PADDO RA_c_0
+DOPAD_DEL   ---     4.105       66.PADDO to         66.PAD RA[0]
+                  --------
+                    7.494   (67.4% logic, 32.6% route), 3 logic levels.
+
+Report:   10.645ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.826ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_532  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     6.523ns  (69.9% logic, 30.1% route), 2 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_59 and
+      6.523ns delay SLICE_59 to nRCS (totaling 9.674ns) meets
+     12.500ns offset RCLK to nRCS by 2.826ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_59:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R4C11B.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_59 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R4C11B.CLK to      R4C11B.Q0 SLICE_59 (from RCLK_c)
+ROUTE         1     1.966      R4C11B.Q0 to       57.PADDO nRCS_c
+DOPAD_DEL   ---     4.105       57.PADDO to         57.PAD nRCS
+                  --------
+                    6.523   (69.9% logic, 30.1% route), 2 logic levels.
+
+Report:    9.674ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.616ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_531  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     6.733ns  (67.7% logic, 32.3% route), 2 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_35 and
+      6.733ns delay SLICE_35 to RCKE (totaling 9.884ns) meets
+     12.500ns offset RCLK to RCKE by 2.616ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_35:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to      R4C7B.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_35 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R4C7B.CLK to       R4C7B.Q0 SLICE_35 (from RCLK_c)
+ROUTE         4     2.176       R4C7B.Q0 to       53.PADDO RCKE_c
+DOPAD_DEL   ---     4.105       53.PADDO to         53.PAD RCKE
+                  --------
+                    6.733   (67.7% logic, 32.3% route), 2 logic levels.
+
+Report:    9.884ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.225ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_535  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     6.124ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_62 and
+      6.124ns delay SLICE_62 to nRWE (totaling 9.275ns) meets
+     12.500ns offset RCLK to nRWE by 3.225ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_62:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C11A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_62 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C11A.CLK to      R5C11A.Q0 SLICE_62 (from RCLK_c)
+ROUTE         1     1.567      R5C11A.Q0 to       49.PADDO nRWE_c
+DOPAD_DEL   ---     4.105       49.PADDO to         49.PAD nRWE
+                  --------
+                    6.124   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    9.275ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.703ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_533  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     6.646ns  (68.6% logic, 31.4% route), 2 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_60 and
+      6.646ns delay SLICE_60 to nRRAS (totaling 9.797ns) meets
+     12.500ns offset RCLK to nRRAS by 2.703ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R4C11A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_60 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R4C11A.CLK to      R4C11A.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1     2.089      R4C11A.Q0 to       54.PADDO nRRAS_c
+DOPAD_DEL   ---     4.105       54.PADDO to         54.PAD nRRAS
+                  --------
+                    6.646   (68.6% logic, 31.4% route), 2 logic levels.
+
+Report:    9.797ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.826ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_534  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     6.523ns  (69.9% logic, 30.1% route), 2 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_57 and
+      6.523ns delay SLICE_57 to nRCAS (totaling 9.674ns) meets
+     12.500ns offset RCLK to nRCAS by 2.826ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C11B.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_57 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C11B.CLK to      R5C11B.Q0 SLICE_57 (from RCLK_c)
+ROUTE         1     1.966      R5C11B.Q0 to       52.PADDO nRCAS_c
+DOPAD_DEL   ---     4.105       52.PADDO to         52.PAD nRCAS
+                  --------
+                    6.523   (69.9% logic, 30.1% route), 2 logic levels.
+
+Report:    9.674ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     7.790ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      7.790ns delay SLICE_63 to RDQMH (totaling 10.941ns) meets
+     12.500ns offset RCLK to RDQMH by 1.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.648      R5C10A.Q0 to       R5C9B.D1 nRowColSel
+CTOF_DEL    ---     0.495       R5C9B.D1 to       R5C9B.F1 SLICE_151
+ROUTE         1     2.090       R5C9B.F1 to       51.PADDO RDQMH_c
+DOPAD_DEL   ---     4.105       51.PADDO to         51.PAD RDQMH
+                  --------
+                    7.790   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:   10.941ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.859ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     7.490ns  (67.4% logic, 32.6% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      7.490ns delay SLICE_63 to RDQML (totaling 10.641ns) meets
+     12.500ns offset RCLK to RDQML by 1.859ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.796      R5C10A.Q0 to       R5C9C.C1 nRowColSel
+CTOF_DEL    ---     0.495       R5C9C.C1 to       R5C9C.F1 SLICE_161
+ROUTE         1     1.642       R5C9C.F1 to       48.PADDO RDQML_c
+DOPAD_DEL   ---     4.105       48.PADDO to         48.PAD RDQML
+                  --------
+                    7.490   (67.4% logic, 32.6% route), 3 logic levels.
+
+Report:   10.641ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |   350.000 ns|    25.800 ns|   8  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |   350.000 ns|     2.500 ns|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |   350.000 ns|     2.500 ns|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |    16.000 ns|    12.427 ns|   9  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.485 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    11.005 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    11.114 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.948 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    11.099 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    11.365 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    11.365 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    11.178 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.923 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.921 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.645 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.674 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.884 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.275 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.797 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.674 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.941 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.641 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 5 clocks:
+
+Clock Domain: wb_clk   Source: SLICE_73.Q0   Loads: 1
+   No transfer within this clock domain is found
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 52
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: wb_clk   Source: SLICE_73.Q0
+      Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;   Transfers: 2
+
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 1548 paths, 9 nets, and 900 connections (79.58% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
+Tue Aug 17 06:21:01 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_640hc_impl1.ncd
+Preference file: ram2gs_lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,m
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+VCCIO Voltage:
+                   3.135 V (Bank 0)
+                   3.135 V (Bank 1)
+                   3.135 V (Bank 2)
+                   3.135 V (Bank 3)
+                   2.375 V (Bank 4)
+                   2.375 V (Bank 5)
+                   2.375 V (Bank 6)
+                   2.375 V (Bank 7)
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            121 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_542  (from PHI2_c -)
+   Destination:    FF         Data in        C1Submitted_542  (to PHI2_c -)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_15 to SLICE_15 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_15 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C9C.CLK to       R3C9C.Q0 SLICE_15 (from PHI2_c)
+ROUTE         2     0.132       R3C9C.Q0 to       R3C9C.A0 C1Submitted
+CTOF_DEL    ---     0.101       R3C9C.A0 to       R3C9C.F0 SLICE_15
+ROUTE         1     0.000       R3C9C.F0 to      R3C9C.DI0 n2549 (to PHI2_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9C.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9C.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.474ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_541  (from PHI2_c -)
+   Destination:    FF         Data in        CmdSubmitted_549  (to PHI2_c -)
+
+   Delay:               0.461ns  (50.8% logic, 49.2% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.461ns physical path delay SLICE_19 to SLICE_21 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.474ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_21:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C9A.CLK to       R3C9A.Q0 SLICE_19 (from PHI2_c)
+ROUTE         1     0.224       R3C9A.Q0 to       R4C9B.B0 CmdEnable
+CTOF_DEL    ---     0.101       R4C9B.B0 to       R4C9B.F0 SLICE_21
+ROUTE         4     0.003       R4C9B.F0 to      R4C9B.DI0 XOR8MEG_N_149 (to PHI2_c)
+                  --------
+                    0.461   (50.8% logic, 49.2% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_21:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R4C9B.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.538ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_543  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_541  (to PHI2_c -)
+
+   Delay:               0.510ns  (45.9% logic, 54.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.510ns physical path delay SLICE_10 to SLICE_19 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 0.538ns
+
+ Physical Path Details:
+
+      Data path SLICE_10 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C9B.CLK to       R3C9B.Q0 SLICE_10 (from PHI2_c)
+ROUTE         1     0.133       R3C9B.Q0 to       R3C9D.D0 ADSubmitted
+CTOF_DEL    ---     0.101       R3C9D.D0 to       R3C9D.F0 SLICE_130
+ROUTE         1     0.143       R3C9D.F0 to       R3C9A.CE PHI2_N_151_enable_1 (to PHI2_c)
+                  --------
+                    0.510   (45.9% logic, 54.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9B.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.860ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_542  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_541  (to PHI2_c -)
+
+   Delay:               0.832ns  (40.3% logic, 59.7% route), 3 logic levels.
+
+ Constraint Details:
+
+      0.832ns physical path delay SLICE_15 to SLICE_19 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 0.860ns
+
+ Physical Path Details:
+
+      Data path SLICE_15 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C9C.CLK to       R3C9C.Q0 SLICE_15 (from PHI2_c)
+ROUTE         2     0.224       R3C9C.Q0 to       R3C9C.B1 C1Submitted
+CTOF_DEL    ---     0.101       R3C9C.B1 to       R3C9C.F1 SLICE_15
+ROUTE         1     0.130       R3C9C.F1 to       R3C9D.A0 n7
+CTOF_DEL    ---     0.101       R3C9D.A0 to       R3C9D.F0 SLICE_130
+ROUTE         1     0.143       R3C9D.F0 to       R3C9A.CE PHI2_N_151_enable_1 (to PHI2_c)
+                  --------
+                    0.832   (40.3% logic, 59.7% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9C.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.873ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_541  (from PHI2_c -)
+   Destination:    FF         Data in        XOR8MEG_544  (to PHI2_c -)
+
+   Delay:               0.845ns  (39.6% logic, 60.4% route), 3 logic levels.
+
+ Constraint Details:
+
+      0.845ns physical path delay SLICE_19 to SLICE_145 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 0.873ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_145:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C9A.CLK to       R3C9A.Q0 SLICE_19 (from PHI2_c)
+ROUTE         1     0.224       R3C9A.Q0 to       R4C9B.B0 CmdEnable
+CTOF_DEL    ---     0.101       R4C9B.B0 to       R4C9B.F0 SLICE_21
+ROUTE         4     0.141       R4C9B.F0 to       R5C9A.D1 XOR8MEG_N_149
+CTOF_DEL    ---     0.101       R5C9A.D1 to       R5C9A.F1 SLICE_110
+ROUTE         1     0.145       R5C9A.F1 to       R5C8A.CE PHI2_N_151_enable_6 (to PHI2_c)
+                  --------
+                    0.845   (39.6% logic, 60.4% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_145:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C8A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.009ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_541  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMShift_547  (to PHI2_c -)
+                   FF                        CmdUFMData_548
+
+   Delay:               0.981ns  (34.1% logic, 65.9% route), 3 logic levels.
+
+ Constraint Details:
+
+      0.981ns physical path delay SLICE_19 to SLICE_161 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 1.009ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_161:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C9A.CLK to       R3C9A.Q0 SLICE_19 (from PHI2_c)
+ROUTE         1     0.224       R3C9A.Q0 to       R4C9B.B0 CmdEnable
+CTOF_DEL    ---     0.101       R4C9B.B0 to       R4C9B.F0 SLICE_21
+ROUTE         4     0.059       R4C9B.F0 to       R4C9B.C1 XOR8MEG_N_149
+CTOF_DEL    ---     0.101       R4C9B.C1 to       R4C9B.F1 SLICE_21
+ROUTE         1     0.363       R4C9B.F1 to       R5C9C.CE PHI2_N_151_enable_3 (to PHI2_c)
+                  --------
+                    0.981   (34.1% logic, 65.9% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_161:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C9C.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.341ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_541  (from PHI2_c -)
+   Destination:    FF         Data in        CmdLEDEN_545  (to PHI2_c -)
+
+   Delay:               1.313ns  (33.2% logic, 66.8% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.313ns physical path delay SLICE_19 to SLICE_20 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 1.341ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C9A.CLK to       R3C9A.Q0 SLICE_19 (from PHI2_c)
+ROUTE         1     0.224       R3C9A.Q0 to       R4C9B.B0 CmdEnable
+CTOF_DEL    ---     0.101       R4C9B.B0 to       R4C9B.F0 SLICE_21
+ROUTE         4     0.335       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.101       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.056       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.101       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     0.262       R5C8D.F1 to       R5C6A.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                    1.313   (33.2% logic, 66.8% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C6A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.341ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_541  (from PHI2_c -)
+   Destination:    FF         Data in        Cmdn8MEGEN_546  (to PHI2_c -)
+
+   Delay:               1.313ns  (33.2% logic, 66.8% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.313ns physical path delay SLICE_19 to SLICE_24 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 1.341ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C9A.CLK to       R3C9A.Q0 SLICE_19 (from PHI2_c)
+ROUTE         1     0.224       R3C9A.Q0 to       R4C9B.B0 CmdEnable
+CTOF_DEL    ---     0.101       R4C9B.B0 to       R4C9B.F0 SLICE_21
+ROUTE         4     0.335       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.101       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.056       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.101       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     0.262       R5C8D.F1 to       R5C6B.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                    1.313   (33.2% logic, 66.8% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C6B.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 175.457ns (weighted slack = 350.914ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              XOR8MEG_544  (from PHI2_c -)
+   Destination:    FF         Data in        RA11_521  (to PHI2_c +)
+
+   Delay:               0.444ns  (52.7% logic, 47.3% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.444ns physical path delay SLICE_145 to SLICE_32 meets
+     -0.013ns DIN_HLD and
+    -175.000ns delay constraint less
+      0.000ns skew requirement (totaling -175.013ns) by 175.457ns
+
+ Physical Path Details:
+
+      Data path SLICE_145 to SLICE_32:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R5C8A.CLK to       R5C8A.Q0 SLICE_145 (from PHI2_c)
+ROUTE         1     0.210       R5C8A.Q0 to       R5C8C.A0 XOR8MEG
+CTOF_DEL    ---     0.101       R5C8C.A0 to       R5C8C.F0 SLICE_32
+ROUTE         1     0.000       R5C8C.F0 to      R5C8C.DI0 RA11_N_217 (to PHI2_c)
+                  --------
+                    0.444   (52.7% logic, 47.3% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_145:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C8A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_32:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C8C.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 175.815ns (weighted slack = 351.630ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i2  (from PHI2_c +)
+   Destination:    FF         Data in        ADSubmitted_543  (to PHI2_c -)
+
+   Delay:               0.787ns  (42.6% logic, 57.4% route), 3 logic levels.
+
+ Constraint Details:
+
+      0.787ns physical path delay SLICE_143 to SLICE_10 meets
+     -0.028ns CE_HLD and
+    -175.000ns delay constraint less
+      0.000ns skew requirement (totaling -175.028ns) by 175.815ns
+
+ Physical Path Details:
+
+      Data path SLICE_143 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R2C8D.CLK to       R2C8D.Q0 SLICE_143 (from PHI2_c)
+ROUTE         2     0.139       R2C8D.Q0 to       R2C9C.C1 Bank_2
+CTOF_DEL    ---     0.101       R2C9C.C1 to       R2C9C.F1 SLICE_132
+ROUTE         1     0.056       R2C9C.F1 to       R2C9C.C0 n4782
+CTOF_DEL    ---     0.101       R2C9C.C0 to       R2C9C.F0 SLICE_132
+ROUTE         1     0.257       R2C9C.F0 to       R3C9B.CE PHI2_N_151_enable_7 (to PHI2_c)
+                  --------
+                    0.787   (42.6% logic, 57.4% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_143:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R2C8D.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9B.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            1409 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i2  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i3  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_118 to SLICE_118 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_118 to SLICE_118:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R4C9C.CLK to       R4C9C.Q0 SLICE_118 (from RCLK_c)
+ROUTE         1     0.152       R4C9C.Q0 to       R4C9C.M1 n1197 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_118:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R4C9C.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_118:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R4C9C.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i4  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i5  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_127 to SLICE_127 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_127 to SLICE_127:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R4C10B.CLK to      R4C10B.Q0 SLICE_127 (from RCLK_c)
+ROUTE         1     0.152      R4C10B.Q0 to      R4C10B.M1 n1195 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_127:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to     R4C10B.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_127:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to     R4C10B.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CASr_518  (from RCLK_c +)
+   Destination:    FF         Data in        CASr2_519  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_16 to SLICE_16 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_16 to SLICE_16:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R6C10C.CLK to      R6C10C.Q0 SLICE_16 (from RCLK_c)
+ROUTE         1     0.152      R6C10C.Q0 to      R6C10C.M1 CASr (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_16:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to     R6C10C.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_16:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to     R6C10C.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i10  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i11  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_163 to SLICE_163 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_163 to SLICE_163:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R4C10D.CLK to      R4C10D.Q0 SLICE_163 (from RCLK_c)
+ROUTE         1     0.152      R4C10D.Q0 to      R4C10D.M1 n1189 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_163:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to     R4C10D.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_163:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to     R4C10D.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i14  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i15  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_91 to SLICE_91 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_91 to SLICE_91:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R4C8D.CLK to       R4C8D.Q0 SLICE_91 (from RCLK_c)
+ROUTE         1     0.152       R4C8D.Q0 to       R4C8D.M1 n1185 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_91:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R4C8D.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_91:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R4C8D.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i12  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i13  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_94 to SLICE_94 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_94 to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R4C7D.CLK to       R4C7D.Q0 SLICE_94 (from RCLK_c)
+ROUTE         1     0.152       R4C7D.Q0 to       R4C7D.M1 n1187 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R4C7D.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R4C7D.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              PHI2r_512  (from RCLK_c +)
+   Destination:    FF         Data in        PHI2r2_513  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_95 to SLICE_35 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_35:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R4C7A.CLK to       R4C7A.Q0 SLICE_95 (from RCLK_c)
+ROUTE         1     0.152       R4C7A.Q0 to       R4C7B.M1 PHI2r (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R4C7A.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_35:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R4C7B.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.306ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RASr_515  (from RCLK_c +)
+   Destination:    FF         Data in        RASr2_516  (to RCLK_c +)
+
+   Delay:               0.287ns  (46.3% logic, 53.7% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.287ns physical path delay SLICE_30 to SLICE_30 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.306ns
+
+ Physical Path Details:
+
+      Data path SLICE_30 to SLICE_30:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R5C7A.CLK to       R5C7A.Q0 SLICE_30 (from RCLK_c)
+ROUTE         2     0.154       R5C7A.Q0 to       R5C7A.M1 RASr (to RCLK_c)
+                  --------
+                    0.287   (46.3% logic, 53.7% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_30:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R5C7A.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_30:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R5C7A.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.307ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i0  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i1  (to RCLK_c +)
+
+   Delay:               0.288ns  (46.2% logic, 53.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.288ns physical path delay SLICE_162 to SLICE_162 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.307ns
+
+ Physical Path Details:
+
+      Data path SLICE_162 to SLICE_162:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R3C10C.CLK to      R3C10C.Q0 SLICE_162 (from RCLK_c)
+ROUTE         4     0.155      R3C10C.Q0 to      R3C10C.M1 nRCS_N_172 (to RCLK_c)
+                  --------
+                    0.288   (46.2% logic, 53.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_162:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to     R3C10C.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_162:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to     R3C10C.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i2  (from RCLK_c +)
+   Destination:    FF         Data in        FS_972__i2  (to RCLK_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_0 to SLICE_0 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_0 to SLICE_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R6C6B.CLK to       R6C6B.Q1 SLICE_0 (from RCLK_c)
+ROUTE         3     0.132       R6C6B.Q1 to       R6C6B.A1 FS_2
+CTOF_DEL    ---     0.101       R6C6B.A1 to       R6C6B.F1 SLICE_0
+ROUTE         1     0.000       R6C6B.F1 to      R6C6B.DI1 n93 (to RCLK_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R6C6B.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R6C6B.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.236ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_536  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     2.217ns  (81.5% logic, 18.5% route), 2 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_54 and
+      2.217ns delay SLICE_54 to RA[10] (totaling 3.236ns) meets
+      0.000ns hold offset RCLK to RA[10] by 3.236ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_54:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R4C11D.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_54 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R4C11D.CLK to      R4C11D.Q0 SLICE_54 (from RCLK_c)
+ROUTE         1     0.411      R4C11D.Q0 to       64.PADDO n1975
+DOPAD_DEL   ---     1.673       64.PADDO to         64.PAD RA[10]
+                  --------
+                    2.217   (81.5% logic, 18.5% route), 2 logic levels.
+
+Report:    3.236ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.561ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     2.542ns  (75.0% logic, 25.0% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.542ns delay SLICE_63 to RA[9] (totaling 3.561ns) meets
+      0.000ns hold offset RCLK to RA[9] by 3.561ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.219      R5C10A.Q0 to       R5C9B.A0 nRowColSel
+CTOF_DEL    ---     0.101       R5C9B.A0 to       R5C9B.F0 SLICE_151
+ROUTE         1     0.416       R5C9B.F0 to       62.PADDO RA_c_9
+DOPAD_DEL   ---     1.673       62.PADDO to         62.PAD RA[9]
+                  --------
+                    2.542   (75.0% logic, 25.0% route), 3 logic levels.
+
+Report:    3.561ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.608ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     2.589ns  (73.7% logic, 26.3% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.589ns delay SLICE_63 to RA[8] (totaling 3.608ns) meets
+      0.000ns hold offset RCLK to RA[8] by 3.608ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.231      R5C10A.Q0 to      R4C10D.B1 nRowColSel
+CTOF_DEL    ---     0.101      R4C10D.B1 to      R4C10D.F1 SLICE_163
+ROUTE         1     0.451      R4C10D.F1 to       65.PADDO RA_c_8
+DOPAD_DEL   ---     1.673       65.PADDO to         65.PAD RA[8]
+                  --------
+                    2.589   (73.7% logic, 26.3% route), 3 logic levels.
+
+Report:    3.608ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.552ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     2.533ns  (75.3% logic, 24.7% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.533ns delay SLICE_63 to RA[7] (totaling 3.552ns) meets
+      0.000ns hold offset RCLK to RA[7] by 3.552ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.229      R5C10A.Q0 to      R2C10D.D1 nRowColSel
+CTOF_DEL    ---     0.101      R2C10D.D1 to      R2C10D.F1 SLICE_155
+ROUTE         1     0.397      R2C10D.F1 to       75.PADDO RA_c_7
+DOPAD_DEL   ---     1.673       75.PADDO to         75.PAD RA[7]
+                  --------
+                    2.533   (75.3% logic, 24.7% route), 3 logic levels.
+
+Report:    3.552ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.573ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     2.554ns  (74.7% logic, 25.3% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.554ns delay SLICE_63 to RA[6] (totaling 3.573ns) meets
+      0.000ns hold offset RCLK to RA[6] by 3.573ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.231      R5C10A.Q0 to      R4C10D.B0 nRowColSel
+CTOF_DEL    ---     0.101      R4C10D.B0 to      R4C10D.F0 SLICE_163
+ROUTE         1     0.416      R4C10D.F0 to       68.PADDO RA_c_6
+DOPAD_DEL   ---     1.673       68.PADDO to         68.PAD RA[6]
+                  --------
+                    2.554   (74.7% logic, 25.3% route), 3 logic levels.
+
+Report:    3.573ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.630ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     2.611ns  (73.0% logic, 27.0% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.611ns delay SLICE_63 to RA[5] (totaling 3.630ns) meets
+      0.000ns hold offset RCLK to RA[5] by 3.630ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.283      R5C10A.Q0 to       R2C9A.C1 nRowColSel
+CTOF_DEL    ---     0.101       R2C9A.C1 to       R2C9A.F1 SLICE_157
+ROUTE         1     0.421       R2C9A.F1 to       70.PADDO RA_c_5
+DOPAD_DEL   ---     1.673       70.PADDO to         70.PAD RA[5]
+                  --------
+                    2.611   (73.0% logic, 27.0% route), 3 logic levels.
+
+Report:    3.630ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.630ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     2.611ns  (73.0% logic, 27.0% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.611ns delay SLICE_63 to RA[4] (totaling 3.630ns) meets
+      0.000ns hold offset RCLK to RA[4] by 3.630ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.283      R5C10A.Q0 to       R2C8B.C1 nRowColSel
+CTOF_DEL    ---     0.101       R2C8B.C1 to       R2C8B.F1 SLICE_158
+ROUTE         1     0.421       R2C8B.F1 to       74.PADDO RA_c_4
+DOPAD_DEL   ---     1.673       74.PADDO to         74.PAD RA[4]
+                  --------
+                    2.611   (73.0% logic, 27.0% route), 3 logic levels.
+
+Report:    3.630ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.615ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     2.596ns  (73.5% logic, 26.5% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.596ns delay SLICE_63 to RA[3] (totaling 3.615ns) meets
+      0.000ns hold offset RCLK to RA[3] by 3.615ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.226      R5C10A.Q0 to      R3C10C.D0 nRowColSel
+CTOF_DEL    ---     0.101      R3C10C.D0 to      R3C10C.F0 SLICE_162
+ROUTE         1     0.463      R3C10C.F0 to       71.PADDO RA_c_3
+DOPAD_DEL   ---     1.673       71.PADDO to         71.PAD RA[3]
+                  --------
+                    2.596   (73.5% logic, 26.5% route), 3 logic levels.
+
+Report:    3.615ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.527ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     2.508ns  (76.0% logic, 24.0% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.508ns delay SLICE_63 to RA[2] (totaling 3.527ns) meets
+      0.000ns hold offset RCLK to RA[2] by 3.527ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.145      R5C10A.Q0 to       R5C9C.C0 nRowColSel
+CTOF_DEL    ---     0.101       R5C9C.C0 to       R5C9C.F0 SLICE_161
+ROUTE         1     0.456       R5C9C.F0 to       69.PADDO RA_c_2
+DOPAD_DEL   ---     1.673       69.PADDO to         69.PAD RA[2]
+                  --------
+                    2.508   (76.0% logic, 24.0% route), 3 logic levels.
+
+Report:    3.527ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.549ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     2.530ns  (75.4% logic, 24.6% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.530ns delay SLICE_63 to RA[1] (totaling 3.549ns) meets
+      0.000ns hold offset RCLK to RA[1] by 3.549ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.226      R5C10A.Q0 to      R3C10C.D1 nRowColSel
+CTOF_DEL    ---     0.101      R3C10C.D1 to      R3C10C.F1 SLICE_162
+ROUTE         1     0.397      R3C10C.F1 to       67.PADDO RA_c_1
+DOPAD_DEL   ---     1.673       67.PADDO to         67.PAD RA[1]
+                  --------
+                    2.530   (75.4% logic, 24.6% route), 3 logic levels.
+
+Report:    3.549ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.471ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     2.452ns  (77.8% logic, 22.2% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.452ns delay SLICE_63 to RA[0] (totaling 3.471ns) meets
+      0.000ns hold offset RCLK to RA[0] by 3.471ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.229      R5C10A.Q0 to      R3C10D.D1 nRowColSel
+CTOF_DEL    ---     0.101      R3C10D.D1 to      R3C10D.F1 SLICE_159
+ROUTE         1     0.316      R3C10D.F1 to       66.PADDO RA_c_0
+DOPAD_DEL   ---     1.673       66.PADDO to         66.PAD RA[0]
+                  --------
+                    2.452   (77.8% logic, 22.2% route), 3 logic levels.
+
+Report:    3.471ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.300ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_532  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     2.281ns  (79.2% logic, 20.8% route), 2 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_59 and
+      2.281ns delay SLICE_59 to nRCS (totaling 3.300ns) meets
+      0.000ns hold offset RCLK to nRCS by 3.300ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_59:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R4C11B.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_59 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R4C11B.CLK to      R4C11B.Q0 SLICE_59 (from RCLK_c)
+ROUTE         1     0.475      R4C11B.Q0 to       57.PADDO nRCS_c
+DOPAD_DEL   ---     1.673       57.PADDO to         57.PAD nRCS
+                  --------
+                    2.281   (79.2% logic, 20.8% route), 2 logic levels.
+
+Report:    3.300ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.362ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_531  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     2.343ns  (77.1% logic, 22.9% route), 2 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_35 and
+      2.343ns delay SLICE_35 to RCKE (totaling 3.362ns) meets
+      0.000ns hold offset RCLK to RCKE by 3.362ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_35:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to      R4C7B.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_35 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R4C7B.CLK to       R4C7B.Q0 SLICE_35 (from RCLK_c)
+ROUTE         4     0.537       R4C7B.Q0 to       53.PADDO RCKE_c
+DOPAD_DEL   ---     1.673       53.PADDO to         53.PAD RCKE
+                  --------
+                    2.343   (77.1% logic, 22.9% route), 2 logic levels.
+
+Report:    3.362ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.194ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_535  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     2.175ns  (83.0% logic, 17.0% route), 2 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_62 and
+      2.175ns delay SLICE_62 to nRWE (totaling 3.194ns) meets
+      0.000ns hold offset RCLK to nRWE by 3.194ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_62:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C11A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_62 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C11A.CLK to      R5C11A.Q0 SLICE_62 (from RCLK_c)
+ROUTE         1     0.369      R5C11A.Q0 to       49.PADDO nRWE_c
+DOPAD_DEL   ---     1.673       49.PADDO to         49.PAD nRWE
+                  --------
+                    2.175   (83.0% logic, 17.0% route), 2 logic levels.
+
+Report:    3.194ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.322ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_533  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     2.303ns  (78.4% logic, 21.6% route), 2 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_60 and
+      2.303ns delay SLICE_60 to nRRAS (totaling 3.322ns) meets
+      0.000ns hold offset RCLK to nRRAS by 3.322ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R4C11A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_60 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R4C11A.CLK to      R4C11A.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1     0.497      R4C11A.Q0 to       54.PADDO nRRAS_c
+DOPAD_DEL   ---     1.673       54.PADDO to         54.PAD nRRAS
+                  --------
+                    2.303   (78.4% logic, 21.6% route), 2 logic levels.
+
+Report:    3.322ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.300ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_534  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     2.281ns  (79.2% logic, 20.8% route), 2 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_57 and
+      2.281ns delay SLICE_57 to nRCAS (totaling 3.300ns) meets
+      0.000ns hold offset RCLK to nRCAS by 3.300ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C11B.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_57 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C11B.CLK to      R5C11B.Q0 SLICE_57 (from RCLK_c)
+ROUTE         1     0.475      R5C11B.Q0 to       52.PADDO nRCAS_c
+DOPAD_DEL   ---     1.673       52.PADDO to         52.PAD nRCAS
+                  --------
+                    2.281   (79.2% logic, 20.8% route), 2 logic levels.
+
+Report:    3.300ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     2.540ns  (75.1% logic, 24.9% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.540ns delay SLICE_63 to RDQMH (totaling 3.559ns) meets
+      0.000ns hold offset RCLK to RDQMH by 3.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.139      R5C10A.Q0 to       R5C9B.D1 nRowColSel
+CTOF_DEL    ---     0.101       R5C9B.D1 to       R5C9B.F1 SLICE_151
+ROUTE         1     0.494       R5C9B.F1 to       51.PADDO RDQMH_c
+DOPAD_DEL   ---     1.673       51.PADDO to         51.PAD RDQMH
+                  --------
+                    2.540   (75.1% logic, 24.9% route), 3 logic levels.
+
+Report:    3.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.470ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     2.451ns  (77.8% logic, 22.2% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.451ns delay SLICE_63 to RDQML (totaling 3.470ns) meets
+      0.000ns hold offset RCLK to RDQML by 3.470ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.145      R5C10A.Q0 to       R5C9C.C1 nRowColSel
+CTOF_DEL    ---     0.101       R5C9C.C1 to       R5C9C.F1 SLICE_161
+ROUTE         1     0.399       R5C9C.F1 to       48.PADDO RDQML_c
+DOPAD_DEL   ---     1.673       48.PADDO to         48.PAD RDQML
+                  --------
+                    2.451   (77.8% logic, 22.2% route), 3 logic levels.
+
+Report:    3.470ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |            -|            -|   2  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |            -|            -|   1  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.236 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.561 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.608 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.552 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.573 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.630 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.630 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.615 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.527 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.549 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.471 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.300 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.362 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.194 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.322 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.300 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.559 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.470 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 5 clocks:
+
+Clock Domain: wb_clk   Source: SLICE_73.Q0   Loads: 1
+   No transfer within this clock domain is found
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 52
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: wb_clk   Source: SLICE_73.Q0
+      Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;   Transfers: 2
+
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 1548 paths, 9 nets, and 900 connections (79.58% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 0 (setup), 0 (hold)
+Score: 0 (setup), 0 (hold)
+Cumulative negative slack: 0 (0+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_bgn.html b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_bgn.html
new file mode 100644
index 0000000..7a7fffc
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_bgn.html
@@ -0,0 +1,152 @@
+
+Bitgen Report
+
+
+
+
+
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_iotiming.html b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_iotiming.html
new file mode 100644
index 0000000..eeaaea8
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_iotiming.html
@@ -0,0 +1,198 @@
+
+I/O Timing Report
+
+
+
    I/O Timing Report
+Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 5
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 6
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: M
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+// Design: RAM2GS
+// Package: TQFP100
+// ncd File: ram2gs_lcmxo2_640hc_impl1.ncd
+// Version: Diamond (64-bit) 3.12.0.240.2
+// Written on Tue Aug 17 06:21:03 2021
+// M: Minimum Performance Grade
+// iotiming RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml
+
+I/O Timing Report (All units are in ns)
+
+Worst Case Results across Performance Grades (M, 6, 5, 4):
+
+// Input Setup and Hold Times
+
+Port    Clock Edge  Setup Performance_Grade  Hold Performance_Grade
+----------------------------------------------------------------------
+CROW[0] nCRAS F    -0.195      M       1.729     4
+CROW[1] nCRAS F    -0.218      M       1.801     4
+Din[0]  PHI2  F     6.339      4       1.186     4
+Din[0]  nCCAS F     1.641      4       0.107     M
+Din[1]  PHI2  F     6.084      4       1.570     4
+Din[1]  nCCAS F     0.198      4       1.314     4
+Din[2]  PHI2  F     3.778      4       1.771     4
+Din[2]  nCCAS F     0.075      4       1.431     4
+Din[3]  PHI2  F     4.331      4       1.705     4
+Din[3]  nCCAS F    -0.116      M       1.722     4
+Din[4]  PHI2  F     6.176      4       1.711     4
+Din[4]  nCCAS F     1.065      4       0.575     4
+Din[5]  PHI2  F     4.684      4       1.261     4
+Din[5]  nCCAS F    -0.081      M       1.625     4
+Din[6]  PHI2  F     5.243      4       0.356     4
+Din[6]  nCCAS F     1.414      4       0.309     4
+Din[7]  PHI2  F     6.602      4       1.175     4
+Din[7]  nCCAS F    -0.286      M       2.137     4
+MAin[0] PHI2  F     5.034      4       0.629     4
+MAin[0] nCRAS F     1.094      4       0.380     4
+MAin[1] PHI2  F     6.081      4       1.157     4
+MAin[1] nCRAS F     0.544      4       0.877     4
+MAin[2] PHI2  F     9.979      4      -0.319     M
+MAin[2] nCRAS F    -0.050      M       1.401     4
+MAin[3] PHI2  F     9.162      4      -0.219     M
+MAin[3] nCRAS F     1.032      4       0.440     4
+MAin[4] PHI2  F    11.678      4      -0.770     M
+MAin[4] nCRAS F    -0.150      M       1.620     4
+MAin[5] PHI2  F     8.668      4      -0.081     M
+MAin[5] nCRAS F    -0.050      M       1.401     4
+MAin[6] PHI2  F     8.516      4      -0.025     M
+MAin[6] nCRAS F     1.003      4       0.478     4
+MAin[7] PHI2  F     9.320      4      -0.061     M
+MAin[7] nCRAS F     1.001      4       0.478     4
+MAin[8] nCRAS F    -0.146      M       1.657     4
+MAin[9] nCRAS F    -0.360      M       2.140     4
+PHI2    RCLK  R     3.079      4      -0.602     M
+nCCAS   RCLK  R     3.574      4      -0.705     M
+nCCAS   nCRAS F     3.232      4      -0.351     M
+nCRAS   RCLK  R     2.757      4      -0.470     M
+nFWE    PHI2  F     5.913      4       0.723     4
+nFWE    nCRAS F     0.547      4       0.890     4
+
+
+// Clock to Output Delay
+
+Port   Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
+------------------------------------------------------------------------
+LED    RCLK  R    10.062         4        3.164          M
+RA[0]  RCLK  R    10.645         4        3.471          M
+RA[0]  nCRAS F    11.744         4        3.770          M
+RA[10] RCLK  R     9.485         4        3.236          M
+RA[11] PHI2  R    11.513         4        3.824          M
+RA[1]  RCLK  R    10.921         4        3.549          M
+RA[1]  nCRAS F    12.664         4        4.036          M
+RA[2]  RCLK  R    10.923         4        3.527          M
+RA[2]  nCRAS F    12.463         4        3.984          M
+RA[3]  RCLK  R    11.178         4        3.615          M
+RA[3]  nCRAS F    12.304         4        3.917          M
+RA[4]  RCLK  R    11.365         4        3.630          M
+RA[4]  nCRAS F    13.243         4        4.179          M
+RA[5]  RCLK  R    11.365         4        3.630          M
+RA[5]  nCRAS F    12.940         4        4.098          M
+RA[6]  RCLK  R    11.099         4        3.573          M
+RA[6]  nCRAS F    12.162         4        3.870          M
+RA[7]  RCLK  R    10.948         4        3.552          M
+RA[7]  nCRAS F    12.282         4        3.936          M
+RA[8]  RCLK  R    11.114         4        3.608          M
+RA[8]  nCRAS F    12.909         4        4.116          M
+RA[9]  RCLK  R    11.005         4        3.561          M
+RA[9]  nCRAS F    12.959         4        4.081          M
+RBA[0] nCRAS F    11.842         4        3.911          M
+RBA[1] nCRAS F    11.343         4        3.771          M
+RCKE   RCLK  R     9.884         4        3.362          M
+RDQMH  RCLK  R    10.941         4        3.559          M
+RDQML  RCLK  R    10.641         4        3.470          M
+RD[0]  nCCAS F    12.628         4        4.413          M
+RD[1]  nCCAS F    12.231         4        4.302          M
+RD[2]  nCCAS F    12.231         4        4.302          M
+RD[3]  nCCAS F    11.928         4        4.221          M
+RD[4]  nCCAS F    12.427         4        4.361          M
+RD[5]  nCCAS F    12.697         4        4.400          M
+RD[6]  nCCAS F    12.427         4        4.361          M
+RD[7]  nCCAS F    12.427         4        4.361          M
+nRCAS  RCLK  R     9.674         4        3.300          M
+nRCS   RCLK  R     9.674         4        3.300          M
+nRRAS  RCLK  R     9.797         4        3.322          M
+nRWE   RCLK  R     9.275         4        3.194          M
+WARNING: you must also run trce with hold speed: 4
+WARNING: you must also run trce with setup speed: M
+
+
+
+
    
+
    
+
    
+
    
+
    
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+
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_lattice.synproj b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_lattice.synproj
new file mode 100644
index 0000000..547499e
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_lattice.synproj
@@ -0,0 +1,41 @@
+-a "MachXO2"
+-d LCMXO2-640HC
+-t TQFP100
+-s 4
+-frequency 200
+-optimization_goal Balanced
+-bram_utilization 100
+-ramstyle Auto
+-romstyle auto
+-dsp_utilization 100
+-use_dsp 1
+-use_carry_chain 1
+-carry_chain_length 0
+-force_gsr Auto
+-resource_sharing 1
+-propagate_constants 1
+-remove_duplicate_regs 1
+-mux_style Auto
+-max_fanout 1000
+-fsm_encoding_style Auto
+-twr_paths 3
+-fix_gated_clocks 1
+-loop_limit 1950
+
+
+
+-use_io_insertion 1
+-resolve_mixed_drivers 0
+-use_io_reg auto
+
+
+-lpf 1
+-p "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC"
+-ver "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v"
+-top RAM2GS
+
+
+-p "C:/lscc/diamond/3.12/ispfpga/xo2c00/data" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC"
+
+-ngd "RAM2GS_LCMXO2_640HC_impl1.ngd"
+
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.asd b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.asd
new file mode 100644
index 0000000..a89e71e
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.asd
@@ -0,0 +1,24 @@
+[ActiveSupport MAP]
+Device = LCMXO2-640HC;
+Package = TQFP100;
+Performance = 4;
+LUTS_avail = 640;
+LUTS_used = 255;
+FF_avail = 719;
+FF_used = 119;
+INPUT_LVTTL33 = 25;
+OUTPUT_LVTTL33 = 30;
+BIDI_LVTTL33 = 8;
+IO_avail = 79;
+IO_used = 63;
+EBR_avail = 2;
+EBR_used = 0;
+;
+; start of EFB statistics
+I2C = 0;
+SPI = 0;
+TimerCounter = 0;
+UFM = 0;
+PLL = 0;
+; end of EFB statistics
+;
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.cam b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.cam
new file mode 100644
index 0000000..7137797
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.cam
@@ -0,0 +1,94 @@
+[ START MERGED ]
+n4935 Ready
+n4933 nRowColSel_N_35
+n2557 nRowColSel_N_34
+nRWE_N_209 nRWE_N_210
+PHI2_N_151 PHI2_c
+RCLK_c_enable_22 InitReady
+[ END MERGED ]
+[ START CLIPPED ]
+GND_net
+VCC_net
+FS_972_add_4_1/S0
+FS_972_add_4_1/CI
+FS_972_add_4_19/S1
+FS_972_add_4_19/CO
+[ END CLIPPED ]
+[ START DESIGN PREFS ]
+SCHEMATIC START ;
+# map:  version Diamond (64-bit) 3.12.0.240.2 -- WARNING: Map write only section -- Tue Aug 17 06:20:50 2021
+
+SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
+LOCATE COMP "RCLK" SITE "63" ;
+LOCATE COMP "nFWE" SITE "15" ;
+LOCATE COMP "nCRAS" SITE "17" ;
+LOCATE COMP "nCCAS" SITE "9" ;
+LOCATE COMP "Din[0]" SITE "3" ;
+LOCATE COMP "Din[1]" SITE "96" ;
+LOCATE COMP "Din[2]" SITE "88" ;
+LOCATE COMP "Din[3]" SITE "97" ;
+LOCATE COMP "Din[4]" SITE "99" ;
+LOCATE COMP "Din[5]" SITE "98" ;
+LOCATE COMP "Din[6]" SITE "2" ;
+LOCATE COMP "Din[7]" SITE "1" ;
+LOCATE COMP "CROW[0]" SITE "10" ;
+LOCATE COMP "CROW[1]" SITE "16" ;
+LOCATE COMP "MAin[0]" SITE "14" ;
+LOCATE COMP "MAin[1]" SITE "12" ;
+LOCATE COMP "MAin[2]" SITE "13" ;
+LOCATE COMP "MAin[3]" SITE "21" ;
+LOCATE COMP "MAin[4]" SITE "20" ;
+LOCATE COMP "MAin[5]" SITE "19" ;
+LOCATE COMP "MAin[6]" SITE "24" ;
+LOCATE COMP "MAin[7]" SITE "18" ;
+LOCATE COMP "MAin[8]" SITE "25" ;
+LOCATE COMP "MAin[9]" SITE "32" ;
+LOCATE COMP "PHI2" SITE "8" ;
+LOCATE COMP "RDQML" SITE "48" ;
+LOCATE COMP "RDQMH" SITE "51" ;
+LOCATE COMP "nRCAS" SITE "52" ;
+LOCATE COMP "nRRAS" SITE "54" ;
+LOCATE COMP "nRWE" SITE "49" ;
+LOCATE COMP "RCKE" SITE "53" ;
+LOCATE COMP "nRCS" SITE "57" ;
+LOCATE COMP "RA[0]" SITE "66" ;
+LOCATE COMP "RA[1]" SITE "67" ;
+LOCATE COMP "RA[2]" SITE "69" ;
+LOCATE COMP "RA[3]" SITE "71" ;
+LOCATE COMP "RA[4]" SITE "74" ;
+LOCATE COMP "RA[5]" SITE "70" ;
+LOCATE COMP "RA[6]" SITE "68" ;
+LOCATE COMP "RA[7]" SITE "75" ;
+LOCATE COMP "RA[8]" SITE "65" ;
+LOCATE COMP "RA[9]" SITE "62" ;
+LOCATE COMP "RA[10]" SITE "64" ;
+LOCATE COMP "RA[11]" SITE "59" ;
+LOCATE COMP "RBA[0]" SITE "58" ;
+LOCATE COMP "RBA[1]" SITE "60" ;
+LOCATE COMP "LED" SITE "34" ;
+LOCATE COMP "Dout[0]" SITE "76" ;
+LOCATE COMP "Dout[1]" SITE "86" ;
+LOCATE COMP "Dout[2]" SITE "87" ;
+LOCATE COMP "Dout[3]" SITE "85" ;
+LOCATE COMP "Dout[4]" SITE "83" ;
+LOCATE COMP "Dout[5]" SITE "84" ;
+LOCATE COMP "Dout[6]" SITE "78" ;
+LOCATE COMP "Dout[7]" SITE "82" ;
+LOCATE COMP "RD[0]" SITE "36" ;
+LOCATE COMP "RD[1]" SITE "37" ;
+LOCATE COMP "RD[2]" SITE "38" ;
+LOCATE COMP "RD[3]" SITE "39" ;
+LOCATE COMP "RD[4]" SITE "40" ;
+LOCATE COMP "RD[5]" SITE "41" ;
+LOCATE COMP "RD[6]" SITE "42" ;
+LOCATE COMP "RD[7]" SITE "43" ;
+PERIOD NET "PHI2_c" 350.000000 ns  ;
+USE PRIMARY NET "RCLK_c" ;
+PERIOD NET "nCCAS_c" 350.000000 ns  ;
+USE PRIMARY NET "PHI2_c" ;
+PERIOD NET "nCRAS_c" 350.000000 ns  ;
+USE PRIMARY NET "nCRAS_c" ;
+PERIOD NET "RCLK_c" 16.000000 ns  ;
+USE PRIMARY NET "nCCAS_c" ;
+SCHEMATIC END ;
+[ END DESIGN PREFS ]
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.hrr b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.hrr
new file mode 100644
index 0000000..1264102
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.hrr
@@ -0,0 +1,10 @@
+---------------------------------------------------
+Report for cell RAM2GS
+   Instance path: RAM2GS
+                     Cell usage:
+                                  cell	      count    Res Usage(%)
+                                  SLIC	     131.00        100.0
+                                  LUT4	     235.00        100.0
+                                 IOBUF	         63        100.0
+                                PFUREG	        119        100.0
+                                RIPPLE	         10        100.0
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.ncd b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.ncd
new file mode 100644
index 0000000000000000000000000000000000000000..953ea66735f31dda20b743abfbe899d231d85ee0
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literal 0
HcmV?d00001

diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mrp.html b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mrp.html
new file mode 100644
index 0000000..f2e71ae
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mrp.html
@@ -0,0 +1,428 @@
+
+Project Summary
+
+
+
    
+            Lattice Mapping Report File for Design Module 'RAM2GS'
+
+
+
+Design Information
+
+Command line:   map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
+     RAM2GS_LCMXO2_640HC_impl1.ngd -o RAM2GS_LCMXO2_640HC_impl1_map.ncd -pr
+     RAM2GS_LCMXO2_640HC_impl1.prf -mp RAM2GS_LCMXO2_640HC_impl1.mrp -lpf C:/Use
+     rs/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2
+     _640HC_impl1.lpf -lpf C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMX
+     O2-640HC/RAM2GS_LCMXO2_640HC.lpf -c 0 -gui -msgset
+     C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml 
+Target Vendor:  LATTICE
+Target Device:  LCMXO2-640HCTQFP100
+Target Performance:   4
+Mapper:  xo2c00,  version:  Diamond (64-bit) 3.12.0.240.2
+Mapped on:  08/17/21  06:20:50
+
+
+Design Summary
+   Number of registers:    119 out of   877 (14%)
+      PFU registers:          119 out of   640 (19%)
+      PIO registers:            0 out of   237 (0%)
+   Number of SLICEs:       131 out of   320 (41%)
+      SLICEs as Logic/ROM:    131 out of   320 (41%)
+      SLICEs as RAM:            0 out of   240 (0%)
+      SLICEs as Carry:         10 out of   320 (3%)
+   Number of LUT4s:        255 out of   640 (40%)
+      Number used as logic LUTs:        235
+      Number used as distributed RAM:     0
+      Number used as ripple logic:       20
+      Number used as shift registers:     0
+   Number of PIO sites used: 63 + 4(JTAG) out of 79 (85%)
+   Number of block RAMs:  0 out of 2 (0%)
+   Number of GSRs:        0 out of 1 (0%)
+   EFB used :        Yes
+   JTAG used :       No
+   Readback used :   No
+   Oscillator used : No
+   Startup used :    No
+   POR :             On
+   Bandgap :         On
+   Number of Power Controller:  0 out of 1 (0%)
+   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
+   Number of DCCA:  0 out of 8 (0%)
+   Number of DCMA:  0 out of 2 (0%)
+   Notes:-
+      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
+     distributed RAMs) + 2*(Number of ripple logic)
+      2. Number of logic LUT4s does not include count of distributed RAM and
+     ripple logic.
+   Number of clocks:  5
+     Net RCLK_c: 52 loads, 52 rising, 0 falling (Driver: PIO RCLK )
+     Net wb_clk: 1 loads, 1 rising, 0 falling (Driver: wb_clk_550 )
+     Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 )
+     Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS )
+     Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
+   Number of Clock Enables:  14
+     Net RCLK_c_enable_27: 8 loads, 8 LSLICEs
+
+     Net RCLK_c_enable_20: 4 loads, 4 LSLICEs
+     Net RCLK_c_enable_29: 2 loads, 2 LSLICEs
+     Net RCLK_c_enable_25: 2 loads, 2 LSLICEs
+     Net InitReady: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_24: 2 loads, 2 LSLICEs
+     Net PHI2_N_151_enable_1: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_26: 1 loads, 1 LSLICEs
+     Net PHI2_N_151_enable_3: 1 loads, 1 LSLICEs
+     Net PHI2_N_151_enable_5: 2 loads, 2 LSLICEs
+     Net Ready_N_280: 1 loads, 1 LSLICEs
+     Net PHI2_N_151_enable_6: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_28: 1 loads, 1 LSLICEs
+     Net PHI2_N_151_enable_7: 1 loads, 1 LSLICEs
+   Number of LSRs:  8
+     Net RASr2: 1 loads, 1 LSLICEs
+     Net nRowColSel_N_34: 1 loads, 1 LSLICEs
+     Net wb_rst: 1 loads, 0 LSLICEs
+     Net nRWE_N_210: 1 loads, 1 LSLICEs
+     Net C1Submitted_N_232: 2 loads, 2 LSLICEs
+     Net wb_adr_7__N_92: 2 loads, 2 LSLICEs
+     Net nRowColSel_N_35: 1 loads, 1 LSLICEs
+     Net Ready: 7 loads, 7 LSLICEs
+   Number of nets driven by tri-state buffers:  0
+   Top 10 highest fanout non-clock nets:
+     Net InitReady: 36 loads
+     Net FS_10: 32 loads
+     Net FS_11: 32 loads
+     Net FS_9: 26 loads
+     Net FS_7: 25 loads
+     Net FS_8: 23 loads
+     Net FS_5: 21 loads
+     Net FS_6: 21 loads
+     Net FS_12: 20 loads
+     Net Ready: 18 loads
+
+
+
+
+   Number of warnings:  0
+   Number of errors:    0
+     
+
+
+
+
+Design Errors/Warnings
+
+   No errors or warnings present.
+
+
+
+IO (PIO) Attributes
+
++---------------------+-----------+-----------+------------+
+| IO Name             | Direction | Levelmode | IO         |
+|                     |           |  IO_TYPE  | Register   |
++---------------------+-----------+-----------+------------+
+| RCLK                | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+
+| nFWE                | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| nCRAS               | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| nCCAS               | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Din[0]              | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Din[1]              | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Din[2]              | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Din[3]              | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Din[4]              | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Din[5]              | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Din[6]              | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Din[7]              | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| CROW[0]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| CROW[1]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[0]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[1]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[2]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[3]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[4]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[5]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[6]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[7]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[8]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| MAin[9]             | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| PHI2                | INPUT     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RDQML               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RDQMH               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| nRCAS               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| nRRAS               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+
+| nRWE                | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RCKE                | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| nRCS                | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[0]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[1]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[2]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[3]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[4]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[5]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[6]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[7]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[8]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[9]               | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[10]              | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RA[11]              | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RBA[0]              | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RBA[1]              | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| LED                 | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Dout[0]             | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Dout[1]             | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Dout[2]             | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Dout[3]             | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Dout[4]             | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Dout[5]             | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Dout[6]             | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| Dout[7]             | OUTPUT    | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RD[0]               | BIDIR     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RD[1]               | BIDIR     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+
+| RD[2]               | BIDIR     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RD[3]               | BIDIR     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RD[4]               | BIDIR     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RD[5]               | BIDIR     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RD[6]               | BIDIR     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+| RD[7]               | BIDIR     | LVTTL33   |            |
++---------------------+-----------+-----------+------------+
+
+
+
+Removed logic
+
+Block i2 undriven or does not drive anything - clipped.
+Block GSR_INST undriven or does not drive anything - clipped.
+Signal PHI2_N_151 was merged into signal PHI2_c
+Signal nRWE_N_209 was merged into signal nRWE_N_210
+Signal RCLK_c_enable_22 was merged into signal InitReady
+Signal n2557 was merged into signal nRowColSel_N_34
+Signal n4935 was merged into signal Ready
+Signal n4933 was merged into signal nRowColSel_N_35
+Signal GND_net undriven or does not drive anything - clipped.
+Signal VCC_net undriven or does not drive anything - clipped.
+Signal FS_972_add_4_1/S0 undriven or does not drive anything - clipped.
+Signal FS_972_add_4_1/CI undriven or does not drive anything - clipped.
+Signal FS_972_add_4_19/S1 undriven or does not drive anything - clipped.
+Signal FS_972_add_4_19/CO undriven or does not drive anything - clipped.
+Block i4008 was optimized away.
+Block nRWE_I_53_1_lut was optimized away.
+Block InitReady_I_0_586_1_lut_rep_73 was optimized away.
+Block i1683_1_lut was optimized away.
+Block i1044_1_lut_rep_86 was optimized away.
+Block i1684_1_lut_rep_84 was optimized away.
+Block i1 was optimized away.
+
+     
+
+
+
+Embedded Functional Block Connection Summary
+
+   Desired WISHBONE clock frequency: 50.0 MHz
+   Clock source:                     wb_clk
+   Reset source:                     wb_rst
+   Functions mode:
+      I2C #1 (Primary) Function:     DISABLED
+      I2C #2 (Secondary) Function:   DISABLED
+      SPI Function:                  DISABLED
+      Timer/Counter Function:        DISABLED
+      Timer/Counter Mode:            NO_WB
+      UFM Connection:                DISABLED
+      PLL0 Connection:               DISABLED
+      PLL1 Connection:               DISABLED
+   I2C Function Summary:
+
+   --------------------
+      None
+   SPI Function Summary:
+   --------------------
+      None
+   Timer/Counter Function Summary:
+   ------------------------------
+      None
+   UFM Function Summary:
+   --------------------
+      UFM Utilization:        General Purpose Flash Memory
+      Available General
+      Purpose Flash Memory:   191 Pages (191*128 Bits)
+
+           EBR Blocks with Unique
+      Initialization Data:    0
+
+           WID		EBR Instance
+      ---		------------
+
+
+
+
+ASIC Components
+---------------
+
+Instance Name: ufmefb
+         Type: EFB
+
+
+
+Run Time and Memory Usage
+-------------------------
+
+   Total CPU Time: 0 secs  
+   Total REAL Time: 0 secs  
+   Peak Memory Usage: 36 MB
+        
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+     Copyright (c) 1995 AT&T Corp.   All rights reserved.
+     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+     Copyright (c) 2001 Agere Systems   All rights reserved.
+     Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights
+     reserved.
+
+
+
+
    
+
    
+
    
+
    
+
    
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+
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_pad.html b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_pad.html
new file mode 100644
index 0000000..23f37c5
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_pad.html
@@ -0,0 +1,338 @@
+
+PAD Specification File
+
+
+
    PAD Specification File
+***************************
+
+PART TYPE:        LCMXO2-640HC
+Performance Grade:      4
+PACKAGE:          TQFP100
+Package Status:                     Final          Version 1.39
+
+Tue Aug 17 06:20:57 2021
+
+Pinout by Port Name:
++-----------+----------+--------------+-------+-----------+-----------+------------------------------------------------------------+
+| Port Name | Pin/Bank | Buffer Type  | Site  | PG Enable | BC Enable | Properties                                                 |
++-----------+----------+--------------+-------+-----------+-----------+------------------------------------------------------------+
+| CROW[0]   | 10/3     | LVTTL33_IN   | PL3D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| CROW[1]   | 16/3     | LVTTL33_IN   | PL6A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[0]    | 3/3      | LVTTL33_IN   | PL2C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[1]    | 96/0     | LVTTL33_IN   | PT6D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[2]    | 88/0     | LVTTL33_IN   | PT9A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[3]    | 97/0     | LVTTL33_IN   | PT6C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[4]    | 99/0     | LVTTL33_IN   | PT6A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[5]    | 98/0     | LVTTL33_IN   | PT6B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[6]    | 2/3      | LVTTL33_IN   | PL2B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[7]    | 1/3      | LVTTL33_IN   | PL2A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Dout[0]   | 76/0     | LVTTL33_OUT  | PT11D |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[1]   | 86/0     | LVTTL33_OUT  | PT9C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[2]   | 87/0     | LVTTL33_OUT  | PT9B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[3]   | 85/0     | LVTTL33_OUT  | PT9D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[4]   | 83/0     | LVTTL33_OUT  | PT10B |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[5]   | 84/0     | LVTTL33_OUT  | PT10A |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[6]   | 78/0     | LVTTL33_OUT  | PT11A |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[7]   | 82/0     | LVTTL33_OUT  | PT10C |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| LED       | 34/2     | LVTTL33_OUT  | PB6C  |           |           | DRIVE:16mA SLEW:SLOW                                       |
+| MAin[0]   | 14/3     | LVTTL33_IN   | PL5C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[1]   | 12/3     | LVTTL33_IN   | PL5A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[2]   | 13/3     | LVTTL33_IN   | PL5B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[3]   | 21/3     | LVTTL33_IN   | PL7B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[4]   | 20/3     | LVTTL33_IN   | PL7A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[5]   | 19/3     | LVTTL33_IN   | PL6D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[6]   | 24/3     | LVTTL33_IN   | PL7C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[7]   | 18/3     | LVTTL33_IN   | PL6C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[8]   | 25/3     | LVTTL33_IN   | PL7D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MAin[9]   | 32/2     | LVTTL33_IN   | PB6B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| PHI2      | 8/3      | LVTTL33_IN   | PL3B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[0]     | 66/1     | LVTTL33_OUT  | PR3D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[10]    | 64/1     | LVTTL33_OUT  | PR5B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[11]    | 59/1     | LVTTL33_OUT  | PR6B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[1]     | 67/1     | LVTTL33_OUT  | PR3C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[2]     | 69/1     | LVTTL33_OUT  | PR3A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[3]     | 71/1     | LVTTL33_OUT  | PR2C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[4]     | 74/1     | LVTTL33_OUT  | PR2B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[5]     | 70/1     | LVTTL33_OUT  | PR2D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[6]     | 68/1     | LVTTL33_OUT  | PR3B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[7]     | 75/1     | LVTTL33_OUT  | PR2A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[8]     | 65/1     | LVTTL33_OUT  | PR5A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[9]     | 62/1     | LVTTL33_OUT  | PR5D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RBA[0]    | 58/1     | LVTTL33_OUT  | PR6C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RBA[1]    | 60/1     | LVTTL33_OUT  | PR6A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RCKE      | 53/1     | LVTTL33_OUT  | PR7B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RCLK      | 63/1     | LVTTL33_IN   | PR5C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RDQMH     | 51/1     | LVTTL33_OUT  | PR7D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RDQML     | 48/2     | LVTTL33_OUT  | PB14C |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RD[0]     | 36/2     | LVTTL33_BIDI | PB10A |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[1]     | 37/2     | LVTTL33_BIDI | PB10B |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[2]     | 38/2     | LVTTL33_BIDI | PB10C |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[3]     | 39/2     | LVTTL33_BIDI | PB10D |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[4]     | 40/2     | LVTTL33_BIDI | PB12A |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[5]     | 41/2     | LVTTL33_BIDI | PB12B |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[6]     | 42/2     | LVTTL33_BIDI | PB12C |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[7]     | 43/2     | LVTTL33_BIDI | PB12D |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| nCCAS     | 9/3      | LVTTL33_IN   | PL3C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| nCRAS     | 17/3     | LVTTL33_IN   | PL6B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| nFWE      | 15/3     | LVTTL33_IN   | PL5D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| nRCAS     | 52/1     | LVTTL33_OUT  | PR7C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nRCS      | 57/1     | LVTTL33_OUT  | PR6D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nRRAS     | 54/1     | LVTTL33_OUT  | PR7A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nRWE      | 49/2     | LVTTL33_OUT  | PB14D |           |           | DRIVE:4mA SLEW:SLOW                                        |
++-----------+----------+--------------+-------+-----------+-----------+------------------------------------------------------------+
+
+Vccio by Bank:
++------+-------+
+| Bank | Vccio |
++------+-------+
+| 0    | 3.3V  |
+| 1    | 3.3V  |
+| 2    | 3.3V  |
+| 3    | 3.3V  |
++------+-------+
+
+
+Vref by Bank:
++------+-----+-----------------+---------+
+| Vref | Pin | Bank # / Vref # | Load(s) |
++------+-----+-----------------+---------+
++------+-----+-----------------+---------+
+
+Pinout by Pin Number:
++----------+-----------------------+------------+--------------+-------+---------------+-----------+-----------+
+| Pin/Bank | Pin Info              | Preference | Buffer Type  | Site  | Dual Function | PG Enable | BC Enable |
++----------+-----------------------+------------+--------------+-------+---------------+-----------+-----------+
+| 1/3      | Din[7]                | LOCATED    | LVTTL33_IN   | PL2A  |               |           |           |
+| 2/3      | Din[6]                | LOCATED    | LVTTL33_IN   | PL2B  |               |           |           |
+| 3/3      | Din[0]                | LOCATED    | LVTTL33_IN   | PL2C  | PCLKT3_2      |           |           |
+| 4/3      |     unused, PULL:DOWN |            |              | PL2D  | PCLKC3_2      |           |           |
+| 7/3      |     unused, PULL:DOWN |            |              | PL3A  |               |           |           |
+| 8/3      | PHI2                  | LOCATED    | LVTTL33_IN   | PL3B  |               |           |           |
+| 9/3      | nCCAS                 | LOCATED    | LVTTL33_IN   | PL3C  |               |           |           |
+| 10/3     | CROW[0]               | LOCATED    | LVTTL33_IN   | PL3D  |               |           |           |
+| 12/3     | MAin[1]               | LOCATED    | LVTTL33_IN   | PL5A  | PCLKT3_1      |           |           |
+| 13/3     | MAin[2]               | LOCATED    | LVTTL33_IN   | PL5B  | PCLKC3_1      |           |           |
+| 14/3     | MAin[0]               | LOCATED    | LVTTL33_IN   | PL5C  |               |           |           |
+| 15/3     | nFWE                  | LOCATED    | LVTTL33_IN   | PL5D  |               |           |           |
+| 16/3     | CROW[1]               | LOCATED    | LVTTL33_IN   | PL6A  |               |           |           |
+| 17/3     | nCRAS                 | LOCATED    | LVTTL33_IN   | PL6B  |               |           |           |
+| 18/3     | MAin[7]               | LOCATED    | LVTTL33_IN   | PL6C  |               |           |           |
+| 19/3     | MAin[5]               | LOCATED    | LVTTL33_IN   | PL6D  |               |           |           |
+| 20/3     | MAin[4]               | LOCATED    | LVTTL33_IN   | PL7A  | PCLKT3_0      |           |           |
+| 21/3     | MAin[3]               | LOCATED    | LVTTL33_IN   | PL7B  | PCLKC3_0      |           |           |
+| 24/3     | MAin[6]               | LOCATED    | LVTTL33_IN   | PL7C  |               |           |           |
+| 25/3     | MAin[8]               | LOCATED    | LVTTL33_IN   | PL7D  |               |           |           |
+| 27/2     |     unused, PULL:DOWN |            |              | PB4A  | CSSPIN        |           |           |
+| 28/2     |     unused, PULL:DOWN |            |              | PB4B  |               |           |           |
+| 29/2     |     unused, PULL:DOWN |            |              | PB4C  |               |           |           |
+| 30/2     |     unused, PULL:DOWN |            |              | PB4D  |               |           |           |
+| 31/2     |     unused, PULL:DOWN |            |              | PB6A  | MCLK/CCLK     |           |           |
+| 32/2     | MAin[9]               | LOCATED    | LVTTL33_IN   | PB6B  | SO/SPISO      |           |           |
+| 34/2     | LED                   | LOCATED    | LVTTL33_OUT  | PB6C  | PCLKT2_0      |           |           |
+| 35/2     |     unused, PULL:DOWN |            |              | PB6D  | PCLKC2_0      |           |           |
+| 36/2     | RD[0]                 | LOCATED    | LVTTL33_BIDI | PB10A |               |           |           |
+| 37/2     | RD[1]                 | LOCATED    | LVTTL33_BIDI | PB10B |               |           |           |
+| 38/2     | RD[2]                 | LOCATED    | LVTTL33_BIDI | PB10C | PCLKT2_1      |           |           |
+| 39/2     | RD[3]                 | LOCATED    | LVTTL33_BIDI | PB10D | PCLKC2_1      |           |           |
+| 40/2     | RD[4]                 | LOCATED    | LVTTL33_BIDI | PB12A |               |           |           |
+| 41/2     | RD[5]                 | LOCATED    | LVTTL33_BIDI | PB12B |               |           |           |
+| 42/2     | RD[6]                 | LOCATED    | LVTTL33_BIDI | PB12C |               |           |           |
+| 43/2     | RD[7]                 | LOCATED    | LVTTL33_BIDI | PB12D |               |           |           |
+| 45/2     |     unused, PULL:DOWN |            |              | PB14A |               |           |           |
+| 47/2     |     unused, PULL:DOWN |            |              | PB14B |               |           |           |
+| 48/2     | RDQML                 | LOCATED    | LVTTL33_OUT  | PB14C | SN            |           |           |
+| 49/2     | nRWE                  | LOCATED    | LVTTL33_OUT  | PB14D | SI/SISPI      |           |           |
+| 51/1     | RDQMH                 | LOCATED    | LVTTL33_OUT  | PR7D  |               |           |           |
+| 52/1     | nRCAS                 | LOCATED    | LVTTL33_OUT  | PR7C  |               |           |           |
+| 53/1     | RCKE                  | LOCATED    | LVTTL33_OUT  | PR7B  |               |           |           |
+| 54/1     | nRRAS                 | LOCATED    | LVTTL33_OUT  | PR7A  |               |           |           |
+| 57/1     | nRCS                  | LOCATED    | LVTTL33_OUT  | PR6D  |               |           |           |
+| 58/1     | RBA[0]                | LOCATED    | LVTTL33_OUT  | PR6C  |               |           |           |
+| 59/1     | RA[11]                | LOCATED    | LVTTL33_OUT  | PR6B  |               |           |           |
+| 60/1     | RBA[1]                | LOCATED    | LVTTL33_OUT  | PR6A  |               |           |           |
+| 62/1     | RA[9]                 | LOCATED    | LVTTL33_OUT  | PR5D  | PCLKC1_0      |           |           |
+| 63/1     | RCLK                  | LOCATED    | LVTTL33_IN   | PR5C  | PCLKT1_0      |           |           |
+| 64/1     | RA[10]                | LOCATED    | LVTTL33_OUT  | PR5B  |               |           |           |
+| 65/1     | RA[8]                 | LOCATED    | LVTTL33_OUT  | PR5A  |               |           |           |
+| 66/1     | RA[0]                 | LOCATED    | LVTTL33_OUT  | PR3D  |               |           |           |
+| 67/1     | RA[1]                 | LOCATED    | LVTTL33_OUT  | PR3C  |               |           |           |
+| 68/1     | RA[6]                 | LOCATED    | LVTTL33_OUT  | PR3B  |               |           |           |
+| 69/1     | RA[2]                 | LOCATED    | LVTTL33_OUT  | PR3A  |               |           |           |
+| 70/1     | RA[5]                 | LOCATED    | LVTTL33_OUT  | PR2D  |               |           |           |
+| 71/1     | RA[3]                 | LOCATED    | LVTTL33_OUT  | PR2C  |               |           |           |
+| 74/1     | RA[4]                 | LOCATED    | LVTTL33_OUT  | PR2B  |               |           |           |
+| 75/1     | RA[7]                 | LOCATED    | LVTTL33_OUT  | PR2A  |               |           |           |
+| 76/0     | Dout[0]               | LOCATED    | LVTTL33_OUT  | PT11D | DONE          |           |           |
+| 77/0     |     unused, PULL:DOWN |            |              | PT11C | INITN         |           |           |
+| 78/0     | Dout[6]               | LOCATED    | LVTTL33_OUT  | PT11A |               |           |           |
+| 81/0     |     unused, PULL:DOWN |            |              | PT10D | PROGRAMN      |           |           |
+| 82/0     | Dout[7]               | LOCATED    | LVTTL33_OUT  | PT10C | JTAGENB       |           |           |
+| 83/0     | Dout[4]               | LOCATED    | LVTTL33_OUT  | PT10B |               |           |           |
+| 84/0     | Dout[5]               | LOCATED    | LVTTL33_OUT  | PT10A |               |           |           |
+| 85/0     | Dout[3]               | LOCATED    | LVTTL33_OUT  | PT9D  | SDA/PCLKC0_0  |           |           |
+| 86/0     | Dout[1]               | LOCATED    | LVTTL33_OUT  | PT9C  | SCL/PCLKT0_0  |           |           |
+| 87/0     | Dout[2]               | LOCATED    | LVTTL33_OUT  | PT9B  | PCLKC0_1      |           |           |
+| 88/0     | Din[2]                | LOCATED    | LVTTL33_IN   | PT9A  | PCLKT0_1      |           |           |
+| 90/0     | Reserved: sysCONFIG   |            |              | PT7D  | TMS           |           |           |
+| 91/0     | Reserved: sysCONFIG   |            |              | PT7C  | TCK           |           |           |
+| 94/0     | Reserved: sysCONFIG   |            |              | PT7B  | TDI           |           |           |
+| 95/0     | Reserved: sysCONFIG   |            |              | PT7A  | TDO           |           |           |
+| 96/0     | Din[1]                | LOCATED    | LVTTL33_IN   | PT6D  |               |           |           |
+| 97/0     | Din[3]                | LOCATED    | LVTTL33_IN   | PT6C  |               |           |           |
+| 98/0     | Din[5]                | LOCATED    | LVTTL33_IN   | PT6B  |               |           |           |
+| 99/0     | Din[4]                | LOCATED    | LVTTL33_IN   | PT6A  |               |           |           |
+| PT11B/0  |     unused, PULL:DOWN |            |              | PT11B |               |           |           |
++----------+-----------------------+------------+--------------+-------+---------------+-----------+-----------+
+
+sysCONFIG Pins:
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode  |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| PT7D     | TMS                | JTAG_PORT=ENABLE   | 90/0     |             | PULLUP            |
+| PT7C     | TCK/TEST_CLK       | JTAG_PORT=ENABLE   | 91/0     |             | NO pull up/down   |
+| PT7B     | TDI/MD7            | JTAG_PORT=ENABLE   | 94/0     |             | PULLUP            |
+| PT7A     | TDO                | JTAG_PORT=ENABLE   | 95/0     |             | PULLUP            |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+
+Dedicated sysCONFIG Pins:
+
+
+List of All Pins' Locate Preferences Based on Final Placement After PAR 
+to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
+
+LOCATE  COMP  "CROW[0]"  SITE  "10";
+LOCATE  COMP  "CROW[1]"  SITE  "16";
+LOCATE  COMP  "Din[0]"  SITE  "3";
+LOCATE  COMP  "Din[1]"  SITE  "96";
+LOCATE  COMP  "Din[2]"  SITE  "88";
+LOCATE  COMP  "Din[3]"  SITE  "97";
+LOCATE  COMP  "Din[4]"  SITE  "99";
+LOCATE  COMP  "Din[5]"  SITE  "98";
+LOCATE  COMP  "Din[6]"  SITE  "2";
+LOCATE  COMP  "Din[7]"  SITE  "1";
+LOCATE  COMP  "Dout[0]"  SITE  "76";
+LOCATE  COMP  "Dout[1]"  SITE  "86";
+LOCATE  COMP  "Dout[2]"  SITE  "87";
+LOCATE  COMP  "Dout[3]"  SITE  "85";
+LOCATE  COMP  "Dout[4]"  SITE  "83";
+LOCATE  COMP  "Dout[5]"  SITE  "84";
+LOCATE  COMP  "Dout[6]"  SITE  "78";
+LOCATE  COMP  "Dout[7]"  SITE  "82";
+LOCATE  COMP  "LED"  SITE  "34";
+LOCATE  COMP  "MAin[0]"  SITE  "14";
+LOCATE  COMP  "MAin[1]"  SITE  "12";
+LOCATE  COMP  "MAin[2]"  SITE  "13";
+LOCATE  COMP  "MAin[3]"  SITE  "21";
+LOCATE  COMP  "MAin[4]"  SITE  "20";
+LOCATE  COMP  "MAin[5]"  SITE  "19";
+LOCATE  COMP  "MAin[6]"  SITE  "24";
+LOCATE  COMP  "MAin[7]"  SITE  "18";
+LOCATE  COMP  "MAin[8]"  SITE  "25";
+LOCATE  COMP  "MAin[9]"  SITE  "32";
+LOCATE  COMP  "PHI2"  SITE  "8";
+LOCATE  COMP  "RA[0]"  SITE  "66";
+LOCATE  COMP  "RA[10]"  SITE  "64";
+LOCATE  COMP  "RA[11]"  SITE  "59";
+LOCATE  COMP  "RA[1]"  SITE  "67";
+LOCATE  COMP  "RA[2]"  SITE  "69";
+LOCATE  COMP  "RA[3]"  SITE  "71";
+LOCATE  COMP  "RA[4]"  SITE  "74";
+LOCATE  COMP  "RA[5]"  SITE  "70";
+LOCATE  COMP  "RA[6]"  SITE  "68";
+LOCATE  COMP  "RA[7]"  SITE  "75";
+LOCATE  COMP  "RA[8]"  SITE  "65";
+LOCATE  COMP  "RA[9]"  SITE  "62";
+LOCATE  COMP  "RBA[0]"  SITE  "58";
+LOCATE  COMP  "RBA[1]"  SITE  "60";
+LOCATE  COMP  "RCKE"  SITE  "53";
+LOCATE  COMP  "RCLK"  SITE  "63";
+LOCATE  COMP  "RDQMH"  SITE  "51";
+LOCATE  COMP  "RDQML"  SITE  "48";
+LOCATE  COMP  "RD[0]"  SITE  "36";
+LOCATE  COMP  "RD[1]"  SITE  "37";
+LOCATE  COMP  "RD[2]"  SITE  "38";
+LOCATE  COMP  "RD[3]"  SITE  "39";
+LOCATE  COMP  "RD[4]"  SITE  "40";
+LOCATE  COMP  "RD[5]"  SITE  "41";
+LOCATE  COMP  "RD[6]"  SITE  "42";
+LOCATE  COMP  "RD[7]"  SITE  "43";
+LOCATE  COMP  "nCCAS"  SITE  "9";
+LOCATE  COMP  "nCRAS"  SITE  "17";
+LOCATE  COMP  "nFWE"  SITE  "15";
+LOCATE  COMP  "nRCAS"  SITE  "52";
+LOCATE  COMP  "nRCS"  SITE  "57";
+LOCATE  COMP  "nRRAS"  SITE  "54";
+LOCATE  COMP  "nRWE"  SITE  "49";
+
+
+
+
+
+PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 17 06:20:59 2021
+
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
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+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
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+
    
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+
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_par.html b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_par.html
new file mode 100644
index 0000000..65dfab2
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_par.html
@@ -0,0 +1,329 @@
+
+Place & Route Report
+
+
+
    PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 17 06:20:51 2021
+
+C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_640HC_impl1.p2t
+RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir
+RAM2GS_LCMXO2_640HC_impl1.prf -gui -msgset
+C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml
+
+
+Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
+
+Cost Table Summary
+Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
+Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
+----------   --------     -----        ------       -----------  -----------  ----         ------
+5_1   *      0            1.135        0            0.304        0            10           Completed
+* : Design saved.
+
+Total (real) run time for 1-seed: 10 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Lattice Place and Route Report for Design "RAM2GS_LCMXO2_640HC_impl1_map.ncd"
+Tue Aug 17 06:20:51 2021
+
+
+Best Par Run
+PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
+Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file RAM2GS_LCMXO2_640HC_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+
+Device utilization summary:
+
+   PIO (prelim)   63+4(JTAG)/80      84% used
+                  63+4(JTAG)/79      85% bonded
+
+   SLICE            131/320          40% used
+
+   EFB                1/1           100% used
+
+
+Number of Signals: 401
+Number of Connections: 1131
+
+Pin Constraint Summary:
+   63 out of 63 pins locked (100% locked).
+
+The following 4 signals are selected to use the primary clock routing resources:
+    RCLK_c (driver: RCLK, clk load #: 52)
+    PHI2_c (driver: PHI2, clk load #: 13)
+    nCRAS_c (driver: nCRAS, clk load #: 7)
+    nCCAS_c (driver: nCCAS, clk load #: 4)
+
+WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
+WARNING - par: Signal "nCRAS_c" is selected to use Primary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
+WARNING - par: Signal "nCCAS_c" is selected to use Primary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
+
+No signal is selected as secondary clock.
+
+No signal is selected as Global Set/Reset.
+Starting Placer Phase 0.
+............
+Finished Placer Phase 0.  REAL time: 0 secs 
+
+Starting Placer Phase 1.
+....................
+Placer score = 65362.
+Finished Placer Phase 1.  REAL time: 6 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  65089
+Finished Placer Phase 2.  REAL time: 6 secs 
+
+
+
+Clock Report
+
+Global Clock Resources:
+  CLK_PIN    : 1 out of 8 (12%)
+  General PIO: 3 out of 80 (3%)
+  DCM        : 0 out of 2 (0%)
+  DCC        : 0 out of 8 (0%)
+
+Global Clocks:
+  PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "63 (PR5C)", clk load = 52
+  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 13
+  PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 7
+  PRIMARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 4
+
+  PRIMARY  : 4 out of 8 (50%)
+  SECONDARY: 0 out of 8 (0%)
+
+
+
+
+I/O Usage Summary (final):
+   63 + 4(JTAG) out of 80 (83.8%) PIO sites used.
+   63 + 4(JTAG) out of 79 (84.8%) bonded PIO sites used.
+   Number of PIO comps: 63; differential: 0.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+----------------+------------+-----------+
+| I/O Bank | Usage          | Bank Vccio | Bank Vref |
++----------+----------------+------------+-----------+
+| 0        | 13 / 19 ( 68%) | 3.3V       | -         |
+| 1        | 20 / 20 (100%) | 3.3V       | -         |
+| 2        | 12 / 20 ( 60%) | 3.3V       | -         |
+| 3        | 18 / 20 ( 90%) | 3.3V       | -         |
++----------+----------------+------------+-----------+
+
+Total placer CPU time: 5 secs 
+
+Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
+
+0 connections routed; 1131 unrouted.
+Starting router resource preassignment
+WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
+WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
+WARNING - par: The driver of primary clock net nCCAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
+
+WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
+   Signal=wb_clk loads=1 clock_loads=1
+
+Completed router resource preassignment. Real time: 8 secs 
+
+Start NBR router at 06:20:59 08/17/21
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at 06:20:59 08/17/21
+
+Start NBR section for initial routing at 06:20:59 08/17/21
+Level 1, iteration 1
+0(0.00%) conflict; 980(86.65%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.167ns/0.000ns; real time: 8 secs 
+Level 2, iteration 1
+1(0.00%) conflict; 970(85.76%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.141ns/0.000ns; real time: 9 secs 
+Level 3, iteration 1
+1(0.00%) conflict; 904(79.93%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs 
+Level 4, iteration 1
+26(0.06%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 06:21:00 08/17/21
+Level 1, iteration 1
+1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs 
+Level 2, iteration 1
+1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs 
+Level 3, iteration 1
+1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs 
+Level 4, iteration 1
+12(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs 
+Level 4, iteration 2
+5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs 
+Level 4, iteration 3
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs 
+
+Start NBR section for setup/hold timing optimization with effort level 3 at 06:21:00 08/17/21
+
+Start NBR section for re-routing at 06:21:00 08/17/21
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs 
+
+Start NBR section for post-routing at 06:21:00 08/17/21
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 0 (0.00%)
+  Estimated worst slack<setup> : 1.135ns
+  Timing score<setup> : 0
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
+   Signal=wb_clk loads=1 clock_loads=1
+
+Total CPU time 9 secs 
+Total REAL time: 10 secs 
+Completely routed.
+End of route.  1131 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 0 
+
+Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = Completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack<setup/<ns>> = 1.135
+PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
+PAR_SUMMARY::Worst  slack<hold /<ns>> = 0.304
+PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 9 secs 
+Total REAL time to completion: 10 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
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diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_summary.html b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_summary.html
new file mode 100644
index 0000000..e426f18
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_summary.html
@@ -0,0 +1,83 @@
+
+Project Summary
+
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    RAM2GS_LCMXO2_640HC project summary
    Module Name:RAM2GS_LCMXO2_640HCSynthesis:Lattice LSE
    Implementation Name:impl1Strategy Name:Strategy1
    Last Process:JEDEC FileState:Passed
    Target Device:LCMXO2-640HC-4TG100CDevice Family:MachXO2
    Device Type:LCMXO2-640HCPackage Type:TQFP100
    Performance grade:4Operating conditions:COM
    Logic preference file:RAM2GS_LCMXO2_640HC.lpf
    Physical Preference file:impl1/RAM2GS_LCMXO2_640HC_impl1.prf
    Product Version:3.12.0.240.2Patch Version:
    Updated:2021/08/17 06:21:51
    Implementation Location:C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1
    Project File:C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf
    
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diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_tw1.html b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_tw1.html
new file mode 100644
index 0000000..8f5276d
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_tw1.html
@@ -0,0 +1,2780 @@
+
+Lattice Map TRACE Report
+
+
+
    Map TRACE Report
+
+Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
+Tue Aug 17 06:20:51 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_640hc_impl1_map.ncd
+Preference file: ram2gs_lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,4
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • PERIOD NET "PHI2_c" 350.000000 ns  (0 errors)
    •             121 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCCAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCRAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "RCLK_c" 16.000000 ns  (0 errors)
    •             1409 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+VCCIO Voltage:
+                   3.135 V (Bank 0)
+                   3.135 V (Bank 1)
+                   3.135 V (Bank 2)
+                   3.135 V (Bank 3)
+                   2.375 V (Bank 4)
+                   2.375 V (Bank 5)
+                   2.375 V (Bank 6)
+                   2.375 V (Bank 7)
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            121 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 161.658ns (weighted slack = 323.316ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i5  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_541  (to PHI2_c -)
+
+   Delay:              13.035ns  (30.0% logic, 70.0% route), 8 logic levels.
+
+ Constraint Details:
+
+     13.035ns physical path delay SLICE_111 to SLICE_19 meets
+    175.000ns delay constraint less
+      0.307ns CE_SET requirement (totaling 174.693ns) by 161.658ns
+
+ Physical Path Details:
+
+      Data path SLICE_111 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452  SLICE_111.CLK to   SLICE_111.Q1 SLICE_111 (from PHI2_c)
+ROUTE         1   e 1.234   SLICE_111.Q1 to   SLICE_158.B0 Bank_5
+CTOF_DEL    ---     0.495   SLICE_158.B0 to   SLICE_158.F0 SLICE_158
+ROUTE         1   e 1.234   SLICE_158.F0 to   SLICE_139.B0 n4610
+CTOF_DEL    ---     0.495   SLICE_139.B0 to   SLICE_139.F0 SLICE_139
+ROUTE         2   e 1.234   SLICE_139.F0 to   SLICE_114.B1 n4628
+CTOF_DEL    ---     0.495   SLICE_114.B1 to   SLICE_114.F1 SLICE_114
+ROUTE         4   e 1.234   SLICE_114.F1 to   SLICE_116.B1 n2384
+CTOF_DEL    ---     0.495   SLICE_116.B1 to   SLICE_116.F1 SLICE_116
+ROUTE         2   e 0.480   SLICE_116.F1 to   SLICE_116.D0 n4888
+CTOF_DEL    ---     0.495   SLICE_116.D0 to   SLICE_116.F0 SLICE_116
+ROUTE         1   e 1.234   SLICE_116.F0 to    SLICE_19.B1 n4624
+CTOF_DEL    ---     0.495    SLICE_19.B1 to    SLICE_19.F1 SLICE_19
+ROUTE         4   e 1.234    SLICE_19.F1 to   SLICE_130.C0 C1Submitted_N_232
+CTOF_DEL    ---     0.495   SLICE_130.C0 to   SLICE_130.F0 SLICE_130
+ROUTE         1   e 1.234   SLICE_130.F0 to    SLICE_19.CE PHI2_N_151_enable_1 (to PHI2_c)
+                  --------
+                   13.035   (30.0% logic, 70.0% route), 8 logic levels.
+
+Report:   26.684ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 347.500ns
+         The internal maximum frequency of the following component is 400.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    SLICE      CLK            SLICE_122
+
+   Delay:               2.500ns -- based on Minimum Pulse Width
+
+Report:    2.500ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 347.500ns
+         The internal maximum frequency of the following component is 400.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    SLICE      CLK            SLICE_25
+
+   Delay:               2.500ns -- based on Minimum Pulse Width
+
+Report:    2.500ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            1409 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 2.077ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i8  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i4  (to RCLK_c +)
+
+   Delay:              13.757ns  (33.7% logic, 66.3% route), 9 logic levels.
+
+ Constraint Details:
+
+     13.757ns physical path delay SLICE_5 to SLICE_70 meets
+     16.000ns delay constraint less
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 2.077ns
+
+ Physical Path Details:
+
+      Data path SLICE_5 to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452    SLICE_5.CLK to     SLICE_5.Q1 SLICE_5 (from RCLK_c)
+ROUTE        23   e 1.234     SLICE_5.Q1 to    SLICE_98.B1 FS_8
+CTOF_DEL    ---     0.495    SLICE_98.B1 to    SLICE_98.F1 SLICE_98
+ROUTE         4   e 1.234    SLICE_98.F1 to    SLICE_93.B1 n4924
+CTOF_DEL    ---     0.495    SLICE_93.B1 to    SLICE_93.F1 SLICE_93
+ROUTE         1   e 1.234    SLICE_93.F1 to   SLICE_133.D0 n98
+CTOF_DEL    ---     0.495   SLICE_133.D0 to   SLICE_133.F0 SLICE_133
+ROUTE         2   e 0.480   SLICE_133.F0 to   SLICE_133.B1 n2199
+CTOF_DEL    ---     0.495   SLICE_133.B1 to   SLICE_133.F1 SLICE_133
+ROUTE         1   e 1.234   SLICE_133.F1 to *9/SLICE_84.C1 n53
+CTOOFX_DEL  ---     0.721 *9/SLICE_84.C1 to *SLICE_84.OFX0 i29/SLICE_84
+ROUTE         1   e 1.234 *SLICE_84.OFX0 to   SLICE_148.C1 n14_adj_3
+CTOF_DEL    ---     0.495   SLICE_148.C1 to   SLICE_148.F1 SLICE_148
+ROUTE         2   e 1.234   SLICE_148.F1 to   SLICE_135.C0 n12_adj_8
+CTOF_DEL    ---     0.495   SLICE_135.C0 to   SLICE_135.F0 SLICE_135
+ROUTE         2   e 1.234   SLICE_135.F0 to    SLICE_70.A1 n14_adj_7
+CTOF_DEL    ---     0.495    SLICE_70.A1 to    SLICE_70.F1 SLICE_70
+ROUTE         1   e 0.001    SLICE_70.F1 to   SLICE_70.DI1 wb_adr_7_N_60_4 (to RCLK_c)
+                  --------
+                   13.757   (33.7% logic, 66.3% route), 9 logic levels.
+
+Report:   13.923ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.343ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_536  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     5.791ns  (78.7% logic, 21.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_54 and
+      5.791ns delay SLICE_54 to RA[10] (totaling 8.157ns) meets
+     12.500ns offset RCLK to RA[10] by 4.343ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_54:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_54.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_54 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_54.CLK to    SLICE_54.Q0 SLICE_54 (from RCLK_c)
+ROUTE         1   e 1.234    SLICE_54.Q0 to       64.PADDO n1975
+DOPAD_DEL   ---     4.105       64.PADDO to         64.PAD RA[10]
+                  --------
+                    5.791   (78.7% logic, 21.3% route), 2 logic levels.
+
+Report:    8.157ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[9] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[9] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_151.C0 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_151.C0 to   SLICE_151.F0 SLICE_151
+ROUTE         1   e 1.234   SLICE_151.F0 to       62.PADDO RA_c_9
+DOPAD_DEL   ---     4.105       62.PADDO to         62.PAD RA[9]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[8] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[8] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_163.C1 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_163.C1 to   SLICE_163.F1 SLICE_163
+ROUTE         1   e 1.234   SLICE_163.F1 to       65.PADDO RA_c_8
+DOPAD_DEL   ---     4.105       65.PADDO to         65.PAD RA[8]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[7] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[7] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_155.C1 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_155.C1 to   SLICE_155.F1 SLICE_155
+ROUTE         1   e 1.234   SLICE_155.F1 to       75.PADDO RA_c_7
+DOPAD_DEL   ---     4.105       75.PADDO to         75.PAD RA[7]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[6] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[6] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_163.C0 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_163.C0 to   SLICE_163.F0 SLICE_163
+ROUTE         1   e 1.234   SLICE_163.F0 to       68.PADDO RA_c_6
+DOPAD_DEL   ---     4.105       68.PADDO to         68.PAD RA[6]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[5] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[5] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_157.C1 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_157.C1 to   SLICE_157.F1 SLICE_157
+ROUTE         1   e 1.234   SLICE_157.F1 to       70.PADDO RA_c_5
+DOPAD_DEL   ---     4.105       70.PADDO to         70.PAD RA[5]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[4] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[4] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_158.C1 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_158.C1 to   SLICE_158.F1 SLICE_158
+ROUTE         1   e 1.234   SLICE_158.F1 to       74.PADDO RA_c_4
+DOPAD_DEL   ---     4.105       74.PADDO to         74.PAD RA[4]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[3] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[3] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_162.C0 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_162.C0 to   SLICE_162.F0 SLICE_162
+ROUTE         1   e 1.234   SLICE_162.F0 to       71.PADDO RA_c_3
+DOPAD_DEL   ---     4.105       71.PADDO to         71.PAD RA[3]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[2] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[2] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_161.C0 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_161.C0 to   SLICE_161.F0 SLICE_161
+ROUTE         1   e 1.234   SLICE_161.F0 to       69.PADDO RA_c_2
+DOPAD_DEL   ---     4.105       69.PADDO to         69.PAD RA[2]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[1] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[1] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_162.C1 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_162.C1 to   SLICE_162.F1 SLICE_162
+ROUTE         1   e 1.234   SLICE_162.F1 to       67.PADDO RA_c_1
+DOPAD_DEL   ---     4.105       67.PADDO to         67.PAD RA[1]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RA[0] (totaling 9.886ns) meets
+     12.500ns offset RCLK to RA[0] by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_159.C1 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_159.C1 to   SLICE_159.F1 SLICE_159
+ROUTE         1   e 1.234   SLICE_159.F1 to       66.PADDO RA_c_0
+DOPAD_DEL   ---     4.105       66.PADDO to         66.PAD RA[0]
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.343ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_532  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     5.791ns  (78.7% logic, 21.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_59 and
+      5.791ns delay SLICE_59 to nRCS (totaling 8.157ns) meets
+     12.500ns offset RCLK to nRCS by 4.343ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_59:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_59.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_59 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_59.CLK to    SLICE_59.Q0 SLICE_59 (from RCLK_c)
+ROUTE         1   e 1.234    SLICE_59.Q0 to       57.PADDO nRCS_c
+DOPAD_DEL   ---     4.105       57.PADDO to         57.PAD nRCS
+                  --------
+                    5.791   (78.7% logic, 21.3% route), 2 logic levels.
+
+Report:    8.157ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.343ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_531  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     5.791ns  (78.7% logic, 21.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_35 and
+      5.791ns delay SLICE_35 to RCKE (totaling 8.157ns) meets
+     12.500ns offset RCLK to RCKE by 4.343ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_35:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_35.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_35 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_35.CLK to    SLICE_35.Q0 SLICE_35 (from RCLK_c)
+ROUTE         4   e 1.234    SLICE_35.Q0 to       53.PADDO RCKE_c
+DOPAD_DEL   ---     4.105       53.PADDO to         53.PAD RCKE
+                  --------
+                    5.791   (78.7% logic, 21.3% route), 2 logic levels.
+
+Report:    8.157ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.343ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_535  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     5.791ns  (78.7% logic, 21.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_62 and
+      5.791ns delay SLICE_62 to nRWE (totaling 8.157ns) meets
+     12.500ns offset RCLK to nRWE by 4.343ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_62:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_62.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_62 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_62.CLK to    SLICE_62.Q0 SLICE_62 (from RCLK_c)
+ROUTE         1   e 1.234    SLICE_62.Q0 to       49.PADDO nRWE_c
+DOPAD_DEL   ---     4.105       49.PADDO to         49.PAD nRWE
+                  --------
+                    5.791   (78.7% logic, 21.3% route), 2 logic levels.
+
+Report:    8.157ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.343ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_533  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     5.791ns  (78.7% logic, 21.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_60 and
+      5.791ns delay SLICE_60 to nRRAS (totaling 8.157ns) meets
+     12.500ns offset RCLK to nRRAS by 4.343ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_60.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_60 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_60.CLK to    SLICE_60.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1   e 1.234    SLICE_60.Q0 to       54.PADDO nRRAS_c
+DOPAD_DEL   ---     4.105       54.PADDO to         54.PAD nRRAS
+                  --------
+                    5.791   (78.7% logic, 21.3% route), 2 logic levels.
+
+Report:    8.157ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 4.343ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_534  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     5.791ns  (78.7% logic, 21.3% route), 2 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_57 and
+      5.791ns delay SLICE_57 to nRCAS (totaling 8.157ns) meets
+     12.500ns offset RCLK to nRCAS by 4.343ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_57.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_57 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_57.CLK to    SLICE_57.Q0 SLICE_57 (from RCLK_c)
+ROUTE         1   e 1.234    SLICE_57.Q0 to       52.PADDO nRCAS_c
+DOPAD_DEL   ---     4.105       52.PADDO to         52.PAD nRCAS
+                  --------
+                    5.791   (78.7% logic, 21.3% route), 2 logic levels.
+
+Report:    8.157ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RDQMH (totaling 9.886ns) meets
+     12.500ns offset RCLK to RDQMH by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_151.B1 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_151.B1 to   SLICE_151.F1 SLICE_151
+ROUTE         1   e 1.234   SLICE_151.F1 to       51.PADDO RDQMH_c
+DOPAD_DEL   ---     4.105       51.PADDO to         51.PAD RDQMH
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.614ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
+
+   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
+
+ Constraint Details:
+      2.366ns delay RCLK to SLICE_63 and
+      7.520ns delay SLICE_63 to RDQML (totaling 9.886ns) meets
+     12.500ns offset RCLK to RDQML by 2.614ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
+
+      Data path SLICE_63 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_161.B1 nRowColSel
+CTOF_DEL    ---     0.495   SLICE_161.B1 to   SLICE_161.F1 SLICE_161
+ROUTE         1   e 1.234   SLICE_161.F1 to       48.PADDO RDQML_c
+DOPAD_DEL   ---     4.105       48.PADDO to         48.PAD RDQML
+                  --------
+                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
+
+Report:    9.886ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |   350.000 ns|    26.684 ns|   8  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |   350.000 ns|     2.500 ns|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |   350.000 ns|     2.500 ns|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |    16.000 ns|    13.923 ns|   9  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.157 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.157 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.157 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.157 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.157 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     8.157 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 5 clocks:
+
+Clock Domain: wb_clk   Source: SLICE_73.Q0   Loads: 1
+   No transfer within this clock domain is found
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 52
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: wb_clk   Source: SLICE_73.Q0
+      Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;   Transfers: 2
+
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 1548 paths, 9 nets, and 889 connections (78.60% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
+Tue Aug 17 06:20:51 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_640hc_impl1_map.ncd
+Preference file: ram2gs_lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,M
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • PERIOD NET "PHI2_c" 350.000000 ns  (0 errors)
    •             121 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCCAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCRAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "RCLK_c" 16.000000 ns  (0 errors)
    •             1409 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+VCCIO Voltage:
+                   3.135 V (Bank 0)
+                   3.135 V (Bank 1)
+                   3.135 V (Bank 2)
+                   3.135 V (Bank 3)
+                   2.375 V (Bank 4)
+                   2.375 V (Bank 5)
+                   2.375 V (Bank 6)
+                   2.375 V (Bank 7)
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            121 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.447ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_542  (from PHI2_c -)
+   Destination:    FF         Data in        C1Submitted_542  (to PHI2_c -)
+
+   Delay:               0.434ns  (53.9% logic, 46.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.434ns physical path delay SLICE_15 to SLICE_15 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
+
+ Physical Path Details:
+
+      Data path SLICE_15 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_15.CLK to    SLICE_15.Q0 SLICE_15 (from PHI2_c)
+ROUTE         2   e 0.199    SLICE_15.Q0 to    SLICE_15.D0 C1Submitted
+CTOF_DEL    ---     0.101    SLICE_15.D0 to    SLICE_15.F0 SLICE_15
+ROUTE         1   e 0.001    SLICE_15.F0 to   SLICE_15.DI0 n2549 (to PHI2_c)
+                  --------
+                    0.434   (53.9% logic, 46.1% route), 2 logic levels.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            1409 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.351ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i2  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i3  (to RCLK_c +)
+
+   Delay:               0.332ns  (40.1% logic, 59.9% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.332ns physical path delay SLICE_118 to SLICE_118 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns
+
+ Physical Path Details:
+
+      Data path SLICE_118 to SLICE_118:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133  SLICE_118.CLK to   SLICE_118.Q0 SLICE_118 (from RCLK_c)
+ROUTE         1   e 0.199   SLICE_118.Q0 to   SLICE_118.M1 n1197 (to RCLK_c)
+                  --------
+                    0.332   (40.1% logic, 59.9% route), 1 logic levels.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.284ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_536  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     2.321ns  (77.8% logic, 22.2% route), 2 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_54 and
+      2.321ns delay SLICE_54 to RA[10] (totaling 3.284ns) meets
+      0.000ns hold offset RCLK to RA[10] by 3.284ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_54:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_54.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_54 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_54.CLK to    SLICE_54.Q0 SLICE_54 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_54.Q0 to       64.PADDO n1975
+DOPAD_DEL   ---     1.673       64.PADDO to         64.PAD RA[10]
+                  --------
+                    2.321   (77.8% logic, 22.2% route), 2 logic levels.
+
+Report:    3.284ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[9] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[9] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_151.C0 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_151.C0 to   SLICE_151.F0 SLICE_151
+ROUTE         1   e 0.515   SLICE_151.F0 to       62.PADDO RA_c_9
+DOPAD_DEL   ---     1.673       62.PADDO to         62.PAD RA[9]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[8] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[8] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_163.C1 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_163.C1 to   SLICE_163.F1 SLICE_163
+ROUTE         1   e 0.515   SLICE_163.F1 to       65.PADDO RA_c_8
+DOPAD_DEL   ---     1.673       65.PADDO to         65.PAD RA[8]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[7] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[7] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_155.C1 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_155.C1 to   SLICE_155.F1 SLICE_155
+ROUTE         1   e 0.515   SLICE_155.F1 to       75.PADDO RA_c_7
+DOPAD_DEL   ---     1.673       75.PADDO to         75.PAD RA[7]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[6] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[6] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_163.C0 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_163.C0 to   SLICE_163.F0 SLICE_163
+ROUTE         1   e 0.515   SLICE_163.F0 to       68.PADDO RA_c_6
+DOPAD_DEL   ---     1.673       68.PADDO to         68.PAD RA[6]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[5] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[5] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_157.C1 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_157.C1 to   SLICE_157.F1 SLICE_157
+ROUTE         1   e 0.515   SLICE_157.F1 to       70.PADDO RA_c_5
+DOPAD_DEL   ---     1.673       70.PADDO to         70.PAD RA[5]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[4] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[4] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_158.C1 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_158.C1 to   SLICE_158.F1 SLICE_158
+ROUTE         1   e 0.515   SLICE_158.F1 to       74.PADDO RA_c_4
+DOPAD_DEL   ---     1.673       74.PADDO to         74.PAD RA[4]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[3] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[3] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_162.C0 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_162.C0 to   SLICE_162.F0 SLICE_162
+ROUTE         1   e 0.515   SLICE_162.F0 to       71.PADDO RA_c_3
+DOPAD_DEL   ---     1.673       71.PADDO to         71.PAD RA[3]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[2] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[2] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_161.C0 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_161.C0 to   SLICE_161.F0 SLICE_161
+ROUTE         1   e 0.515   SLICE_161.F0 to       69.PADDO RA_c_2
+DOPAD_DEL   ---     1.673       69.PADDO to         69.PAD RA[2]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[1] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[1] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_162.C1 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_162.C1 to   SLICE_162.F1 SLICE_162
+ROUTE         1   e 0.515   SLICE_162.F1 to       67.PADDO RA_c_1
+DOPAD_DEL   ---     1.673       67.PADDO to         67.PAD RA[1]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RA[0] (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RA[0] by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_159.C1 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_159.C1 to   SLICE_159.F1 SLICE_159
+ROUTE         1   e 0.515   SLICE_159.F1 to       66.PADDO RA_c_0
+DOPAD_DEL   ---     1.673       66.PADDO to         66.PAD RA[0]
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.284ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_532  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     2.321ns  (77.8% logic, 22.2% route), 2 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_59 and
+      2.321ns delay SLICE_59 to nRCS (totaling 3.284ns) meets
+      0.000ns hold offset RCLK to nRCS by 3.284ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_59:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_59.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_59 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_59.CLK to    SLICE_59.Q0 SLICE_59 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_59.Q0 to       57.PADDO nRCS_c
+DOPAD_DEL   ---     1.673       57.PADDO to         57.PAD nRCS
+                  --------
+                    2.321   (77.8% logic, 22.2% route), 2 logic levels.
+
+Report:    3.284ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.284ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_531  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     2.321ns  (77.8% logic, 22.2% route), 2 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_35 and
+      2.321ns delay SLICE_35 to RCKE (totaling 3.284ns) meets
+      0.000ns hold offset RCLK to RCKE by 3.284ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_35:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_35.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_35 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_35.CLK to    SLICE_35.Q0 SLICE_35 (from RCLK_c)
+ROUTE         4   e 0.515    SLICE_35.Q0 to       53.PADDO RCKE_c
+DOPAD_DEL   ---     1.673       53.PADDO to         53.PAD RCKE
+                  --------
+                    2.321   (77.8% logic, 22.2% route), 2 logic levels.
+
+Report:    3.284ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.284ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_535  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     2.321ns  (77.8% logic, 22.2% route), 2 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_62 and
+      2.321ns delay SLICE_62 to nRWE (totaling 3.284ns) meets
+      0.000ns hold offset RCLK to nRWE by 3.284ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_62:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_62.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_62 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_62.CLK to    SLICE_62.Q0 SLICE_62 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_62.Q0 to       49.PADDO nRWE_c
+DOPAD_DEL   ---     1.673       49.PADDO to         49.PAD nRWE
+                  --------
+                    2.321   (77.8% logic, 22.2% route), 2 logic levels.
+
+Report:    3.284ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.284ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_533  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     2.321ns  (77.8% logic, 22.2% route), 2 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_60 and
+      2.321ns delay SLICE_60 to nRRAS (totaling 3.284ns) meets
+      0.000ns hold offset RCLK to nRRAS by 3.284ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_60.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_60 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_60.CLK to    SLICE_60.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_60.Q0 to       54.PADDO nRRAS_c
+DOPAD_DEL   ---     1.673       54.PADDO to         54.PAD nRRAS
+                  --------
+                    2.321   (77.8% logic, 22.2% route), 2 logic levels.
+
+Report:    3.284ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.284ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_534  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     2.321ns  (77.8% logic, 22.2% route), 2 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_57 and
+      2.321ns delay SLICE_57 to nRCAS (totaling 3.284ns) meets
+      0.000ns hold offset RCLK to nRCAS by 3.284ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_57.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_57 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_57.CLK to    SLICE_57.Q0 SLICE_57 (from RCLK_c)
+ROUTE         1   e 0.515    SLICE_57.Q0 to       52.PADDO nRCAS_c
+DOPAD_DEL   ---     1.673       52.PADDO to         52.PAD nRCAS
+                  --------
+                    2.321   (77.8% logic, 22.2% route), 2 logic levels.
+
+Report:    3.284ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RDQMH (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RDQMH by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_151.B1 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_151.B1 to   SLICE_151.F1 SLICE_151
+ROUTE         1   e 0.515   SLICE_151.F1 to       51.PADDO RDQMH_c
+DOPAD_DEL   ---     1.673       51.PADDO to         51.PAD RDQMH
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.900ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+      0.963ns delay RCLK to SLICE_63 and
+      2.937ns delay SLICE_63 to RDQML (totaling 3.900ns) meets
+      0.000ns hold offset RCLK to RDQML by 3.900ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
+                  --------
+                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
+
+      Data path SLICE_63 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_161.B1 nRowColSel
+CTOF_DEL    ---     0.101   SLICE_161.B1 to   SLICE_161.F1 SLICE_161
+ROUTE         1   e 0.515   SLICE_161.F1 to       48.PADDO RDQML_c
+DOPAD_DEL   ---     1.673       48.PADDO to         48.PAD RDQML
+                  --------
+                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:    3.900ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |            -|            -|   2  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |            -|            -|   1  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.284 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.284 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.284 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.284 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.284 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.284 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 5 clocks:
+
+Clock Domain: wb_clk   Source: SLICE_73.Q0   Loads: 1
+   No transfer within this clock domain is found
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 52
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: wb_clk   Source: SLICE_73.Q0
+      Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;   Transfers: 2
+
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 1548 paths, 9 nets, and 889 connections (78.60% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 0 (setup), 0 (hold)
+Score: 0 (setup), 0 (hold)
+Cumulative negative slack: 0 (0+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
+
+
+
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diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_twr.html b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_twr.html
new file mode 100644
index 0000000..774a443
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_twr.html
@@ -0,0 +1,4699 @@
+
+Lattice TRACE Report
+
+
+
    Place & Route TRACE Report
+
+Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
+Tue Aug 17 06:21:01 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_640hc_impl1.ncd
+Preference file: ram2gs_lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,4
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • PERIOD NET "PHI2_c" 350.000000 ns  (0 errors)
    •             121 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCCAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCRAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "RCLK_c" 16.000000 ns  (0 errors)
    •             1409 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+VCCIO Voltage:
+                   3.135 V (Bank 0)
+                   3.135 V (Bank 1)
+                   3.135 V (Bank 2)
+                   3.135 V (Bank 3)
+                   2.375 V (Bank 4)
+                   2.375 V (Bank 5)
+                   2.375 V (Bank 6)
+                   2.375 V (Bank 7)
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            121 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 162.100ns (weighted slack = 324.200ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        CmdLEDEN_545  (to PHI2_c -)
+
+   Delay:              12.593ns  (31.1% logic, 68.9% route), 8 logic levels.
+
+ Constraint Details:
+
+     12.593ns physical path delay SLICE_151 to SLICE_20 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 162.100ns
+
+ Physical Path Details:
+
+      Data path SLICE_151 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R5C9B.CLK to       R5C9B.Q0 SLICE_151 (from PHI2_c)
+ROUTE         1     1.278       R5C9B.Q0 to       R2C8B.C0 Bank_6
+CTOF_DEL    ---     0.495       R2C8B.C0 to       R2C8B.F0 SLICE_158
+ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
+CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
+CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
+ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
+CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
+ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     1.084       R5C8D.F1 to       R5C6A.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                   12.593   (31.1% logic, 68.9% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_151:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C9B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C6A.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.100ns (weighted slack = 324.200ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        Cmdn8MEGEN_546  (to PHI2_c -)
+
+   Delay:              12.593ns  (31.1% logic, 68.9% route), 8 logic levels.
+
+ Constraint Details:
+
+     12.593ns physical path delay SLICE_151 to SLICE_24 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 162.100ns
+
+ Physical Path Details:
+
+      Data path SLICE_151 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R5C9B.CLK to       R5C9B.Q0 SLICE_151 (from PHI2_c)
+ROUTE         1     1.278       R5C9B.Q0 to       R2C8B.C0 Bank_6
+CTOF_DEL    ---     0.495       R2C8B.C0 to       R2C8B.F0 SLICE_158
+ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
+CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
+CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
+ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
+CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
+ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     1.084       R5C8D.F1 to       R5C6B.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                   12.593   (31.1% logic, 68.9% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_151:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C9B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C6B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.374ns (weighted slack = 324.748ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i4  (from PHI2_c +)
+   Destination:    FF         Data in        CmdLEDEN_545  (to PHI2_c -)
+
+   Delay:              12.319ns  (31.8% logic, 68.2% route), 8 logic levels.
+
+ Constraint Details:
+
+     12.319ns physical path delay SLICE_111 to SLICE_20 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 162.374ns
+
+ Physical Path Details:
+
+      Data path SLICE_111 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q0 SLICE_111 (from PHI2_c)
+ROUTE         1     1.004       R2C8C.Q0 to       R2C8B.B0 Bank_4
+CTOF_DEL    ---     0.495       R2C8B.B0 to       R2C8B.F0 SLICE_158
+ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
+CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
+CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
+ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
+CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
+ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     1.084       R5C8D.F1 to       R5C6A.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                   12.319   (31.8% logic, 68.2% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_111:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R2C8C.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C6A.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.374ns (weighted slack = 324.748ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i4  (from PHI2_c +)
+   Destination:    FF         Data in        Cmdn8MEGEN_546  (to PHI2_c -)
+
+   Delay:              12.319ns  (31.8% logic, 68.2% route), 8 logic levels.
+
+ Constraint Details:
+
+     12.319ns physical path delay SLICE_111 to SLICE_24 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 162.374ns
+
+ Physical Path Details:
+
+      Data path SLICE_111 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q0 SLICE_111 (from PHI2_c)
+ROUTE         1     1.004       R2C8C.Q0 to       R2C8B.B0 Bank_4
+CTOF_DEL    ---     0.495       R2C8B.B0 to       R2C8B.F0 SLICE_158
+ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
+CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
+CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
+ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
+CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
+ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     1.084       R5C8D.F1 to       R5C6B.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                   12.319   (31.8% logic, 68.2% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_111:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R2C8C.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C6B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.411ns (weighted slack = 324.822ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i5  (from PHI2_c +)
+   Destination:    FF         Data in        CmdLEDEN_545  (to PHI2_c -)
+
+   Delay:              12.282ns  (31.9% logic, 68.1% route), 8 logic levels.
+
+ Constraint Details:
+
+     12.282ns physical path delay SLICE_111 to SLICE_20 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 162.411ns
+
+ Physical Path Details:
+
+      Data path SLICE_111 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q1 SLICE_111 (from PHI2_c)
+ROUTE         1     0.967       R2C8C.Q1 to       R2C8B.A0 Bank_5
+CTOF_DEL    ---     0.495       R2C8B.A0 to       R2C8B.F0 SLICE_158
+ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
+CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
+CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
+ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
+CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
+ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     1.084       R5C8D.F1 to       R5C6A.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                   12.282   (31.9% logic, 68.1% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_111:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R2C8C.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C6A.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 162.411ns (weighted slack = 324.822ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i5  (from PHI2_c +)
+   Destination:    FF         Data in        Cmdn8MEGEN_546  (to PHI2_c -)
+
+   Delay:              12.282ns  (31.9% logic, 68.1% route), 8 logic levels.
+
+ Constraint Details:
+
+     12.282ns physical path delay SLICE_111 to SLICE_24 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 162.411ns
+
+ Physical Path Details:
+
+      Data path SLICE_111 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q1 SLICE_111 (from PHI2_c)
+ROUTE         1     0.967       R2C8C.Q1 to       R2C8B.A0 Bank_5
+CTOF_DEL    ---     0.495       R2C8B.A0 to       R2C8B.F0 SLICE_158
+ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
+CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
+CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
+ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
+CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
+ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     1.084       R5C8D.F1 to       R5C6B.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                   12.282   (31.9% logic, 68.1% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_111:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R2C8C.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C6B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 163.336ns (weighted slack = 326.672ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_541  (to PHI2_c -)
+
+   Delay:              11.357ns  (34.5% logic, 65.5% route), 8 logic levels.
+
+ Constraint Details:
+
+     11.357ns physical path delay SLICE_151 to SLICE_19 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 163.336ns
+
+ Physical Path Details:
+
+      Data path SLICE_151 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R5C9B.CLK to       R5C9B.Q0 SLICE_151 (from PHI2_c)
+ROUTE         1     1.278       R5C9B.Q0 to       R2C8B.C0 Bank_6
+CTOF_DEL    ---     0.495       R2C8B.C0 to       R2C8B.F0 SLICE_158
+ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
+CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.756       R2C9D.F1 to       R2C9B.C1 n2384
+CTOF_DEL    ---     0.495       R2C9B.C1 to       R2C9B.F1 SLICE_116
+ROUTE         2     0.445       R2C9B.F1 to       R2C9B.C0 n4888
+CTOF_DEL    ---     0.495       R2C9B.C0 to       R2C9B.F0 SLICE_116
+ROUTE         1     0.645       R2C9B.F0 to       R3C9A.D1 n4624
+CTOF_DEL    ---     0.495       R3C9A.D1 to       R3C9A.F1 SLICE_19
+ROUTE         4     1.042       R3C9A.F1 to       R3C9D.B0 C1Submitted_N_232
+CTOF_DEL    ---     0.495       R3C9D.B0 to       R3C9D.F0 SLICE_130
+ROUTE         1     0.653       R3C9D.F0 to       R3C9A.CE PHI2_N_151_enable_1 (to PHI2_c)
+                  --------
+                   11.357   (34.5% logic, 65.5% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_151:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C9B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R3C9A.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 163.510ns (weighted slack = 327.020ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdLEDEN_545  (to PHI2_c -)
+
+   Delay:              11.183ns  (35.0% logic, 65.0% route), 8 logic levels.
+
+ Constraint Details:
+
+     11.183ns physical path delay SLICE_151 to SLICE_20 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 163.510ns
+
+ Physical Path Details:
+
+      Data path SLICE_151 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R5C9B.CLK to       R5C9B.Q1 SLICE_151 (from PHI2_c)
+ROUTE         1     0.967       R5C9B.Q1 to       R5C9D.A1 Bank_7
+CTOF_DEL    ---     0.495       R5C9D.A1 to       R5C9D.F1 SLICE_139
+ROUTE         1     0.436       R5C9D.F1 to       R5C9D.C0 n4574
+CTOF_DEL    ---     0.495       R5C9D.C0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
+CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
+ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
+CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
+ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     1.084       R5C8D.F1 to       R5C6A.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                   11.183   (35.0% logic, 65.0% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_151:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C9B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C6A.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 163.510ns (weighted slack = 327.020ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        Cmdn8MEGEN_546  (to PHI2_c -)
+
+   Delay:              11.183ns  (35.0% logic, 65.0% route), 8 logic levels.
+
+ Constraint Details:
+
+     11.183ns physical path delay SLICE_151 to SLICE_24 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 163.510ns
+
+ Physical Path Details:
+
+      Data path SLICE_151 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R5C9B.CLK to       R5C9B.Q1 SLICE_151 (from PHI2_c)
+ROUTE         1     0.967       R5C9B.Q1 to       R5C9D.A1 Bank_7
+CTOF_DEL    ---     0.495       R5C9D.A1 to       R5C9D.F1 SLICE_139
+ROUTE         1     0.436       R5C9D.F1 to       R5C9D.C0 n4574
+CTOF_DEL    ---     0.495       R5C9D.C0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
+CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
+ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
+CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
+ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     1.084       R5C8D.F1 to       R5C6B.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                   11.183   (35.0% logic, 65.0% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_151:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C9B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C6B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 163.610ns (weighted slack = 327.220ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i4  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_541  (to PHI2_c -)
+
+   Delay:              11.083ns  (35.3% logic, 64.7% route), 8 logic levels.
+
+ Constraint Details:
+
+     11.083ns physical path delay SLICE_111 to SLICE_19 meets
+    175.000ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 174.693ns) by 163.610ns
+
+ Physical Path Details:
+
+      Data path SLICE_111 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q0 SLICE_111 (from PHI2_c)
+ROUTE         1     1.004       R2C8C.Q0 to       R2C8B.B0 Bank_4
+CTOF_DEL    ---     0.495       R2C8B.B0 to       R2C8B.F0 SLICE_158
+ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
+CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
+ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
+CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
+ROUTE         4     0.756       R2C9D.F1 to       R2C9B.C1 n2384
+CTOF_DEL    ---     0.495       R2C9B.C1 to       R2C9B.F1 SLICE_116
+ROUTE         2     0.445       R2C9B.F1 to       R2C9B.C0 n4888
+CTOF_DEL    ---     0.495       R2C9B.C0 to       R2C9B.F0 SLICE_116
+ROUTE         1     0.645       R2C9B.F0 to       R3C9A.D1 n4624
+CTOF_DEL    ---     0.495       R3C9A.D1 to       R3C9A.F1 SLICE_19
+ROUTE         4     1.042       R3C9A.F1 to       R3C9D.B0 C1Submitted_N_232
+CTOF_DEL    ---     0.495       R3C9D.B0 to       R3C9D.F0 SLICE_130
+ROUTE         1     0.653       R3C9D.F0 to       R3C9A.CE PHI2_N_151_enable_1 (to PHI2_c)
+                  --------
+                   11.083   (35.3% logic, 64.7% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_111:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R2C8C.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R3C9A.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:   25.800ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 347.500ns
+         The internal maximum frequency of the following component is 400.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    SLICE      CLK            SLICE_122
+
+   Delay:               2.500ns -- based on Minimum Pulse Width
+
+Report:    2.500ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 347.500ns
+         The internal maximum frequency of the following component is 400.000 MHz
+
+ Logical Details:  Cell type  Pin name       Component name
+
+   Destination:    SLICE      CLK            SLICE_25
+
+   Delay:               2.500ns -- based on Minimum Pulse Width
+
+Report:    2.500ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            1409 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 3.573ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i6  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i4  (to RCLK_c +)
+
+   Delay:              12.261ns  (37.8% logic, 62.2% route), 9 logic levels.
+
+ Constraint Details:
+
+     12.261ns physical path delay SLICE_6 to SLICE_70 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 3.573ns
+
+ Physical Path Details:
+
+      Data path SLICE_6 to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C6D.CLK to       R6C6D.Q1 SLICE_6 (from RCLK_c)
+ROUTE        21     1.808       R6C6D.Q1 to       R3C7A.B1 FS_6
+CTOF_DEL    ---     0.495       R3C7A.B1 to       R3C7A.F1 SLICE_98
+ROUTE         4     1.021       R3C7A.F1 to       R3C7D.B1 n4924
+CTOF_DEL    ---     0.495       R3C7D.B1 to       R3C7D.F1 SLICE_93
+ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
+CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
+ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
+CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3A.D1 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3A.D1 to       R2C3A.F1 SLICE_70
+ROUTE         1     0.000       R2C3A.F1 to      R2C3A.DI1 wb_adr_7_N_60_4 (to RCLK_c)
+                  --------
+                   12.261   (37.8% logic, 62.2% route), 9 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C6D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3A.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 3.573ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i6  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i6  (to RCLK_c +)
+
+   Delay:              12.261ns  (37.8% logic, 62.2% route), 9 logic levels.
+
+ Constraint Details:
+
+     12.261ns physical path delay SLICE_6 to SLICE_72 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 3.573ns
+
+ Physical Path Details:
+
+      Data path SLICE_6 to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C6D.CLK to       R6C6D.Q1 SLICE_6 (from RCLK_c)
+ROUTE        21     1.808       R6C6D.Q1 to       R3C7A.B1 FS_6
+CTOF_DEL    ---     0.495       R3C7A.B1 to       R3C7A.F1 SLICE_98
+ROUTE         4     1.021       R3C7A.F1 to       R3C7D.B1 n4924
+CTOF_DEL    ---     0.495       R3C7D.B1 to       R3C7D.F1 SLICE_93
+ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
+CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
+ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
+CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3D.D0 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3D.D0 to       R2C3D.F0 SLICE_72
+ROUTE         1     0.000       R2C3D.F0 to      R2C3D.DI0 wb_adr_7_N_60_6 (to RCLK_c)
+                  --------
+                   12.261   (37.8% logic, 62.2% route), 9 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C6D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 4.370ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i7  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i4  (to RCLK_c +)
+
+   Delay:              11.464ns  (36.1% logic, 63.9% route), 8 logic levels.
+
+ Constraint Details:
+
+     11.464ns physical path delay SLICE_5 to SLICE_70 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.370ns
+
+ Physical Path Details:
+
+      Data path SLICE_5 to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C7A.CLK to       R6C7A.Q0 SLICE_5 (from RCLK_c)
+ROUTE        25     2.442       R6C7A.Q0 to       R2C8D.C1 FS_7
+CTOF_DEL    ---     0.495       R2C8D.C1 to       R2C8D.F1 SLICE_143
+ROUTE         2     1.427       R2C8D.F1 to       R2C6A.B1 n4915
+CTOF_DEL    ---     0.495       R2C6A.B1 to       R2C6A.F1 SLICE_113
+ROUTE         5     0.672       R2C6A.F1 to       R2C7D.D1 n4890
+CTOF_DEL    ---     0.495       R2C7D.D1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3A.D1 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3A.D1 to       R2C3A.F1 SLICE_70
+ROUTE         1     0.000       R2C3A.F1 to      R2C3A.DI1 wb_adr_7_N_60_4 (to RCLK_c)
+                  --------
+                   11.464   (36.1% logic, 63.9% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C7A.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3A.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 4.370ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i7  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i6  (to RCLK_c +)
+
+   Delay:              11.464ns  (36.1% logic, 63.9% route), 8 logic levels.
+
+ Constraint Details:
+
+     11.464ns physical path delay SLICE_5 to SLICE_72 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.370ns
+
+ Physical Path Details:
+
+      Data path SLICE_5 to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C7A.CLK to       R6C7A.Q0 SLICE_5 (from RCLK_c)
+ROUTE        25     2.442       R6C7A.Q0 to       R2C8D.C1 FS_7
+CTOF_DEL    ---     0.495       R2C8D.C1 to       R2C8D.F1 SLICE_143
+ROUTE         2     1.427       R2C8D.F1 to       R2C6A.B1 n4915
+CTOF_DEL    ---     0.495       R2C6A.B1 to       R2C6A.F1 SLICE_113
+ROUTE         5     0.672       R2C6A.F1 to       R2C7D.D1 n4890
+CTOF_DEL    ---     0.495       R2C7D.D1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3D.D0 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3D.D0 to       R2C3D.F0 SLICE_72
+ROUTE         1     0.000       R2C3D.F0 to      R2C3D.DI0 wb_adr_7_N_60_6 (to RCLK_c)
+                  --------
+                   11.464   (36.1% logic, 63.9% route), 8 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C7A.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 4.376ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i8  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i4  (to RCLK_c +)
+
+   Delay:              11.458ns  (40.5% logic, 59.5% route), 9 logic levels.
+
+ Constraint Details:
+
+     11.458ns physical path delay SLICE_5 to SLICE_70 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.376ns
+
+ Physical Path Details:
+
+      Data path SLICE_5 to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C7A.CLK to       R6C7A.Q1 SLICE_5 (from RCLK_c)
+ROUTE        23     1.005       R6C7A.Q1 to       R3C7A.D1 FS_8
+CTOF_DEL    ---     0.495       R3C7A.D1 to       R3C7A.F1 SLICE_98
+ROUTE         4     1.021       R3C7A.F1 to       R3C7D.B1 n4924
+CTOF_DEL    ---     0.495       R3C7D.B1 to       R3C7D.F1 SLICE_93
+ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
+CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
+ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
+CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3A.D1 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3A.D1 to       R2C3A.F1 SLICE_70
+ROUTE         1     0.000       R2C3A.F1 to      R2C3A.DI1 wb_adr_7_N_60_4 (to RCLK_c)
+                  --------
+                   11.458   (40.5% logic, 59.5% route), 9 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C7A.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3A.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 4.376ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i8  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i6  (to RCLK_c +)
+
+   Delay:              11.458ns  (40.5% logic, 59.5% route), 9 logic levels.
+
+ Constraint Details:
+
+     11.458ns physical path delay SLICE_5 to SLICE_72 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.376ns
+
+ Physical Path Details:
+
+      Data path SLICE_5 to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C7A.CLK to       R6C7A.Q1 SLICE_5 (from RCLK_c)
+ROUTE        23     1.005       R6C7A.Q1 to       R3C7A.D1 FS_8
+CTOF_DEL    ---     0.495       R3C7A.D1 to       R3C7A.F1 SLICE_98
+ROUTE         4     1.021       R3C7A.F1 to       R3C7D.B1 n4924
+CTOF_DEL    ---     0.495       R3C7D.B1 to       R3C7D.F1 SLICE_93
+ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
+CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
+ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
+CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3D.D0 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3D.D0 to       R2C3D.F0 SLICE_72
+ROUTE         1     0.000       R2C3D.F0 to      R2C3D.DI0 wb_adr_7_N_60_6 (to RCLK_c)
+                  --------
+                   11.458   (40.5% logic, 59.5% route), 9 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C7A.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 4.398ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i6  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i4  (to RCLK_c +)
+
+   Delay:              11.436ns  (40.6% logic, 59.4% route), 9 logic levels.
+
+ Constraint Details:
+
+     11.436ns physical path delay SLICE_6 to SLICE_70 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.398ns
+
+ Physical Path Details:
+
+      Data path SLICE_6 to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C6D.CLK to       R6C6D.Q1 SLICE_6 (from RCLK_c)
+ROUTE        21     1.551       R6C6D.Q1 to       R3C7D.C0 FS_6
+CTOF_DEL    ---     0.495       R3C7D.C0 to       R3C7D.F0 SLICE_93
+ROUTE         3     0.453       R3C7D.F0 to       R3C7D.C1 n53_adj_9
+CTOF_DEL    ---     0.495       R3C7D.C1 to       R3C7D.F1 SLICE_93
+ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
+CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
+ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
+CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3A.D1 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3A.D1 to       R2C3A.F1 SLICE_70
+ROUTE         1     0.000       R2C3A.F1 to      R2C3A.DI1 wb_adr_7_N_60_4 (to RCLK_c)
+                  --------
+                   11.436   (40.6% logic, 59.4% route), 9 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C6D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3A.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 4.398ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i6  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i6  (to RCLK_c +)
+
+   Delay:              11.436ns  (40.6% logic, 59.4% route), 9 logic levels.
+
+ Constraint Details:
+
+     11.436ns physical path delay SLICE_6 to SLICE_72 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.398ns
+
+ Physical Path Details:
+
+      Data path SLICE_6 to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C6D.CLK to       R6C6D.Q1 SLICE_6 (from RCLK_c)
+ROUTE        21     1.551       R6C6D.Q1 to       R3C7D.C0 FS_6
+CTOF_DEL    ---     0.495       R3C7D.C0 to       R3C7D.F0 SLICE_93
+ROUTE         3     0.453       R3C7D.F0 to       R3C7D.C1 n53_adj_9
+CTOF_DEL    ---     0.495       R3C7D.C1 to       R3C7D.F1 SLICE_93
+ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
+CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
+ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
+CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3D.D0 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3D.D0 to       R2C3D.F0 SLICE_72
+ROUTE         1     0.000       R2C3D.F0 to      R2C3D.DI0 wb_adr_7_N_60_6 (to RCLK_c)
+                  --------
+                   11.436   (40.6% logic, 59.4% route), 9 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C6D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 4.449ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i5  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i4  (to RCLK_c +)
+
+   Delay:              11.385ns  (40.7% logic, 59.3% route), 9 logic levels.
+
+ Constraint Details:
+
+     11.385ns physical path delay SLICE_6 to SLICE_70 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.449ns
+
+ Physical Path Details:
+
+      Data path SLICE_6 to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C6D.CLK to       R6C6D.Q0 SLICE_6 (from RCLK_c)
+ROUTE        21     1.500       R6C6D.Q0 to       R3C7D.D0 FS_5
+CTOF_DEL    ---     0.495       R3C7D.D0 to       R3C7D.F0 SLICE_93
+ROUTE         3     0.453       R3C7D.F0 to       R3C7D.C1 n53_adj_9
+CTOF_DEL    ---     0.495       R3C7D.C1 to       R3C7D.F1 SLICE_93
+ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
+CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
+ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
+CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3A.D1 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3A.D1 to       R2C3A.F1 SLICE_70
+ROUTE         1     0.000       R2C3A.F1 to      R2C3A.DI1 wb_adr_7_N_60_4 (to RCLK_c)
+                  --------
+                   11.385   (40.7% logic, 59.3% route), 9 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C6D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3A.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 4.449ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i5  (from RCLK_c +)
+   Destination:    FF         Data in        wb_adr_i6  (to RCLK_c +)
+
+   Delay:              11.385ns  (40.7% logic, 59.3% route), 9 logic levels.
+
+ Constraint Details:
+
+     11.385ns physical path delay SLICE_6 to SLICE_72 meets
+     16.000ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.449ns
+
+ Physical Path Details:
+
+      Data path SLICE_6 to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C6D.CLK to       R6C6D.Q0 SLICE_6 (from RCLK_c)
+ROUTE        21     1.500       R6C6D.Q0 to       R3C7D.D0 FS_5
+CTOF_DEL    ---     0.495       R3C7D.D0 to       R3C7D.F0 SLICE_93
+ROUTE         3     0.453       R3C7D.F0 to       R3C7D.C1 n53_adj_9
+CTOF_DEL    ---     0.495       R3C7D.C1 to       R3C7D.F1 SLICE_93
+ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
+CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
+ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
+CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
+ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
+CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
+ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
+CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
+ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
+CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
+ROUTE         2     0.652       R2C5D.F0 to       R2C3D.D0 n14_adj_7
+CTOF_DEL    ---     0.495       R2C3D.D0 to       R2C3D.F0 SLICE_72
+ROUTE         1     0.000       R2C3D.F0 to      R2C3D.DI0 wb_adr_7_N_60_6 (to RCLK_c)
+                  --------
+                   11.385   (40.7% logic, 59.3% route), 9 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R6C6D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_72:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     2.019       63.PADDI to      R2C3D.CLK RCLK_c
+                  --------
+                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:   12.427ns is the minimum period for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.015ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_536  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     6.334ns  (71.9% logic, 28.1% route), 2 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_54 and
+      6.334ns delay SLICE_54 to RA[10] (totaling 9.485ns) meets
+     12.500ns offset RCLK to RA[10] by 3.015ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_54:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R4C11D.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_54 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R4C11D.CLK to      R4C11D.Q0 SLICE_54 (from RCLK_c)
+ROUTE         1     1.777      R4C11D.Q0 to       64.PADDO n1975
+DOPAD_DEL   ---     4.105       64.PADDO to         64.PAD RA[10]
+                  --------
+                    6.334   (71.9% logic, 28.1% route), 2 logic levels.
+
+Report:    9.485ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.495ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     7.854ns  (64.3% logic, 35.7% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      7.854ns delay SLICE_63 to RA[9] (totaling 11.005ns) meets
+     12.500ns offset RCLK to RA[9] by 1.495ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     1.016      R5C10A.Q0 to       R5C9B.A0 nRowColSel
+CTOF_DEL    ---     0.495       R5C9B.A0 to       R5C9B.F0 SLICE_151
+ROUTE         1     1.786       R5C9B.F0 to       62.PADDO RA_c_9
+DOPAD_DEL   ---     4.105       62.PADDO to         62.PAD RA[9]
+                  --------
+                    7.854   (64.3% logic, 35.7% route), 3 logic levels.
+
+Report:   11.005ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.386ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     7.963ns  (63.4% logic, 36.6% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      7.963ns delay SLICE_63 to RA[8] (totaling 11.114ns) meets
+     12.500ns offset RCLK to RA[8] by 1.386ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     1.053      R5C10A.Q0 to      R4C10D.B1 nRowColSel
+CTOF_DEL    ---     0.495      R4C10D.B1 to      R4C10D.F1 SLICE_163
+ROUTE         1     1.858      R4C10D.F1 to       65.PADDO RA_c_8
+DOPAD_DEL   ---     4.105       65.PADDO to         65.PAD RA[8]
+                  --------
+                    7.963   (63.4% logic, 36.6% route), 3 logic levels.
+
+Report:   11.114ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.552ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     7.797ns  (64.8% logic, 35.2% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      7.797ns delay SLICE_63 to RA[7] (totaling 10.948ns) meets
+     12.500ns offset RCLK to RA[7] by 1.552ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     1.017      R5C10A.Q0 to      R2C10D.D1 nRowColSel
+CTOF_DEL    ---     0.495      R2C10D.D1 to      R2C10D.F1 SLICE_155
+ROUTE         1     1.728      R2C10D.F1 to       75.PADDO RA_c_7
+DOPAD_DEL   ---     4.105       75.PADDO to         75.PAD RA[7]
+                  --------
+                    7.797   (64.8% logic, 35.2% route), 3 logic levels.
+
+Report:   10.948ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.401ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     7.948ns  (63.6% logic, 36.4% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      7.948ns delay SLICE_63 to RA[6] (totaling 11.099ns) meets
+     12.500ns offset RCLK to RA[6] by 1.401ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     1.053      R5C10A.Q0 to      R4C10D.B0 nRowColSel
+CTOF_DEL    ---     0.495      R4C10D.B0 to      R4C10D.F0 SLICE_163
+ROUTE         1     1.843      R4C10D.F0 to       68.PADDO RA_c_6
+DOPAD_DEL   ---     4.105       68.PADDO to         68.PAD RA[6]
+                  --------
+                    7.948   (63.6% logic, 36.4% route), 3 logic levels.
+
+Report:   11.099ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.135ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     8.214ns  (61.5% logic, 38.5% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      8.214ns delay SLICE_63 to RA[5] (totaling 11.365ns) meets
+     12.500ns offset RCLK to RA[5] by 1.135ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     1.310      R5C10A.Q0 to       R2C9A.C1 nRowColSel
+CTOF_DEL    ---     0.495       R2C9A.C1 to       R2C9A.F1 SLICE_157
+ROUTE         1     1.852       R2C9A.F1 to       70.PADDO RA_c_5
+DOPAD_DEL   ---     4.105       70.PADDO to         70.PAD RA[5]
+                  --------
+                    8.214   (61.5% logic, 38.5% route), 3 logic levels.
+
+Report:   11.365ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.135ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     8.214ns  (61.5% logic, 38.5% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      8.214ns delay SLICE_63 to RA[4] (totaling 11.365ns) meets
+     12.500ns offset RCLK to RA[4] by 1.135ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     1.310      R5C10A.Q0 to       R2C8B.C1 nRowColSel
+CTOF_DEL    ---     0.495       R2C8B.C1 to       R2C8B.F1 SLICE_158
+ROUTE         1     1.852       R2C8B.F1 to       74.PADDO RA_c_4
+DOPAD_DEL   ---     4.105       74.PADDO to         74.PAD RA[4]
+                  --------
+                    8.214   (61.5% logic, 38.5% route), 3 logic levels.
+
+Report:   11.365ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.322ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     8.027ns  (62.9% logic, 37.1% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      8.027ns delay SLICE_63 to RA[3] (totaling 11.178ns) meets
+     12.500ns offset RCLK to RA[3] by 1.322ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.990      R5C10A.Q0 to      R3C10C.D0 nRowColSel
+CTOF_DEL    ---     0.495      R3C10C.D0 to      R3C10C.F0 SLICE_162
+ROUTE         1     1.985      R3C10C.F0 to       71.PADDO RA_c_3
+DOPAD_DEL   ---     4.105       71.PADDO to         71.PAD RA[3]
+                  --------
+                    8.027   (62.9% logic, 37.1% route), 3 logic levels.
+
+Report:   11.178ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.577ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     7.772ns  (65.0% logic, 35.0% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      7.772ns delay SLICE_63 to RA[2] (totaling 10.923ns) meets
+     12.500ns offset RCLK to RA[2] by 1.577ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.796      R5C10A.Q0 to       R5C9C.C0 nRowColSel
+CTOF_DEL    ---     0.495       R5C9C.C0 to       R5C9C.F0 SLICE_161
+ROUTE         1     1.924       R5C9C.F0 to       69.PADDO RA_c_2
+DOPAD_DEL   ---     4.105       69.PADDO to         69.PAD RA[2]
+                  --------
+                    7.772   (65.0% logic, 35.0% route), 3 logic levels.
+
+Report:   10.923ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.579ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     7.770ns  (65.0% logic, 35.0% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      7.770ns delay SLICE_63 to RA[1] (totaling 10.921ns) meets
+     12.500ns offset RCLK to RA[1] by 1.579ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.990      R5C10A.Q0 to      R3C10C.D1 nRowColSel
+CTOF_DEL    ---     0.495      R3C10C.D1 to      R3C10C.F1 SLICE_162
+ROUTE         1     1.728      R3C10C.F1 to       67.PADDO RA_c_1
+DOPAD_DEL   ---     4.105       67.PADDO to         67.PAD RA[1]
+                  --------
+                    7.770   (65.0% logic, 35.0% route), 3 logic levels.
+
+Report:   10.921ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.855ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     7.494ns  (67.4% logic, 32.6% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      7.494ns delay SLICE_63 to RA[0] (totaling 10.645ns) meets
+     12.500ns offset RCLK to RA[0] by 1.855ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     1.017      R5C10A.Q0 to      R3C10D.D1 nRowColSel
+CTOF_DEL    ---     0.495      R3C10D.D1 to      R3C10D.F1 SLICE_159
+ROUTE         1     1.425      R3C10D.F1 to       66.PADDO RA_c_0
+DOPAD_DEL   ---     4.105       66.PADDO to         66.PAD RA[0]
+                  --------
+                    7.494   (67.4% logic, 32.6% route), 3 logic levels.
+
+Report:   10.645ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.826ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_532  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     6.523ns  (69.9% logic, 30.1% route), 2 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_59 and
+      6.523ns delay SLICE_59 to nRCS (totaling 9.674ns) meets
+     12.500ns offset RCLK to nRCS by 2.826ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_59:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R4C11B.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_59 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R4C11B.CLK to      R4C11B.Q0 SLICE_59 (from RCLK_c)
+ROUTE         1     1.966      R4C11B.Q0 to       57.PADDO nRCS_c
+DOPAD_DEL   ---     4.105       57.PADDO to         57.PAD nRCS
+                  --------
+                    6.523   (69.9% logic, 30.1% route), 2 logic levels.
+
+Report:    9.674ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.616ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_531  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     6.733ns  (67.7% logic, 32.3% route), 2 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_35 and
+      6.733ns delay SLICE_35 to RCKE (totaling 9.884ns) meets
+     12.500ns offset RCLK to RCKE by 2.616ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_35:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to      R4C7B.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_35 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R4C7B.CLK to       R4C7B.Q0 SLICE_35 (from RCLK_c)
+ROUTE         4     2.176       R4C7B.Q0 to       53.PADDO RCKE_c
+DOPAD_DEL   ---     4.105       53.PADDO to         53.PAD RCKE
+                  --------
+                    6.733   (67.7% logic, 32.3% route), 2 logic levels.
+
+Report:    9.884ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.225ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_535  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     6.124ns  (74.4% logic, 25.6% route), 2 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_62 and
+      6.124ns delay SLICE_62 to nRWE (totaling 9.275ns) meets
+     12.500ns offset RCLK to nRWE by 3.225ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_62:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C11A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_62 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C11A.CLK to      R5C11A.Q0 SLICE_62 (from RCLK_c)
+ROUTE         1     1.567      R5C11A.Q0 to       49.PADDO nRWE_c
+DOPAD_DEL   ---     4.105       49.PADDO to         49.PAD nRWE
+                  --------
+                    6.124   (74.4% logic, 25.6% route), 2 logic levels.
+
+Report:    9.275ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.703ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_533  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     6.646ns  (68.6% logic, 31.4% route), 2 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_60 and
+      6.646ns delay SLICE_60 to nRRAS (totaling 9.797ns) meets
+     12.500ns offset RCLK to nRRAS by 2.703ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R4C11A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_60 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R4C11A.CLK to      R4C11A.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1     2.089      R4C11A.Q0 to       54.PADDO nRRAS_c
+DOPAD_DEL   ---     4.105       54.PADDO to         54.PAD nRRAS
+                  --------
+                    6.646   (68.6% logic, 31.4% route), 2 logic levels.
+
+Report:    9.797ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 2.826ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_534  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     6.523ns  (69.9% logic, 30.1% route), 2 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_57 and
+      6.523ns delay SLICE_57 to nRCAS (totaling 9.674ns) meets
+     12.500ns offset RCLK to nRCAS by 2.826ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C11B.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_57 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C11B.CLK to      R5C11B.Q0 SLICE_57 (from RCLK_c)
+ROUTE         1     1.966      R5C11B.Q0 to       52.PADDO nRCAS_c
+DOPAD_DEL   ---     4.105       52.PADDO to         52.PAD nRCAS
+                  --------
+                    6.523   (69.9% logic, 30.1% route), 2 logic levels.
+
+Report:    9.674ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     7.790ns  (64.9% logic, 35.1% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      7.790ns delay SLICE_63 to RDQMH (totaling 10.941ns) meets
+     12.500ns offset RCLK to RDQMH by 1.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.648      R5C10A.Q0 to       R5C9B.D1 nRowColSel
+CTOF_DEL    ---     0.495       R5C9B.D1 to       R5C9B.F1 SLICE_151
+ROUTE         1     2.090       R5C9B.F1 to       51.PADDO RDQMH_c
+DOPAD_DEL   ---     4.105       51.PADDO to         51.PAD RDQMH
+                  --------
+                    7.790   (64.9% logic, 35.1% route), 3 logic levels.
+
+Report:   10.941ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 1.859ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     7.490ns  (67.4% logic, 32.6% route), 3 logic levels.
+
+   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
+
+ Constraint Details:
+      3.151ns delay RCLK to SLICE_63 and
+      7.490ns delay SLICE_63 to RDQML (totaling 10.641ns) meets
+     12.500ns offset RCLK to RDQML by 1.859ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
+ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
+
+      Data path SLICE_63 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.796      R5C10A.Q0 to       R5C9C.C1 nRowColSel
+CTOF_DEL    ---     0.495       R5C9C.C1 to       R5C9C.F1 SLICE_161
+ROUTE         1     1.642       R5C9C.F1 to       48.PADDO RDQML_c
+DOPAD_DEL   ---     4.105       48.PADDO to         48.PAD RDQML
+                  --------
+                    7.490   (67.4% logic, 32.6% route), 3 logic levels.
+
+Report:   10.641ns is the minimum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |   350.000 ns|    25.800 ns|   8  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |   350.000 ns|     2.500 ns|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |   350.000 ns|     2.500 ns|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |    16.000 ns|    12.427 ns|   9  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.485 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    11.005 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    11.114 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.948 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    11.099 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    11.365 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    11.365 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    11.178 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.923 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.921 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.645 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.674 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.884 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.275 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.797 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|     9.674 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.941 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |    12.500 ns|    10.641 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 5 clocks:
+
+Clock Domain: wb_clk   Source: SLICE_73.Q0   Loads: 1
+   No transfer within this clock domain is found
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 52
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: wb_clk   Source: SLICE_73.Q0
+      Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;   Transfers: 2
+
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 1548 paths, 9 nets, and 900 connections (79.58% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
+Tue Aug 17 06:21:01 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_640hc_impl1.ncd
+Preference file: ram2gs_lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,m
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • PERIOD NET "PHI2_c" 350.000000 ns  (0 errors)
    •             121 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCCAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "nCRAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • PERIOD NET "RCLK_c" 16.000000 ns  (0 errors)
    •             1409 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+
  • CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+VCCIO Voltage:
+                   3.135 V (Bank 0)
+                   3.135 V (Bank 1)
+                   3.135 V (Bank 2)
+                   3.135 V (Bank 3)
+                   2.375 V (Bank 4)
+                   2.375 V (Bank 5)
+                   2.375 V (Bank 6)
+                   2.375 V (Bank 7)
+
+
+
+================================================================================
+Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
+            121 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_542  (from PHI2_c -)
+   Destination:    FF         Data in        C1Submitted_542  (to PHI2_c -)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_15 to SLICE_15 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_15 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C9C.CLK to       R3C9C.Q0 SLICE_15 (from PHI2_c)
+ROUTE         2     0.132       R3C9C.Q0 to       R3C9C.A0 C1Submitted
+CTOF_DEL    ---     0.101       R3C9C.A0 to       R3C9C.F0 SLICE_15
+ROUTE         1     0.000       R3C9C.F0 to      R3C9C.DI0 n2549 (to PHI2_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9C.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9C.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.474ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_541  (from PHI2_c -)
+   Destination:    FF         Data in        CmdSubmitted_549  (to PHI2_c -)
+
+   Delay:               0.461ns  (50.8% logic, 49.2% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.461ns physical path delay SLICE_19 to SLICE_21 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.474ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_21:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C9A.CLK to       R3C9A.Q0 SLICE_19 (from PHI2_c)
+ROUTE         1     0.224       R3C9A.Q0 to       R4C9B.B0 CmdEnable
+CTOF_DEL    ---     0.101       R4C9B.B0 to       R4C9B.F0 SLICE_21
+ROUTE         4     0.003       R4C9B.F0 to      R4C9B.DI0 XOR8MEG_N_149 (to PHI2_c)
+                  --------
+                    0.461   (50.8% logic, 49.2% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_21:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R4C9B.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.538ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_543  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_541  (to PHI2_c -)
+
+   Delay:               0.510ns  (45.9% logic, 54.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.510ns physical path delay SLICE_10 to SLICE_19 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 0.538ns
+
+ Physical Path Details:
+
+      Data path SLICE_10 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C9B.CLK to       R3C9B.Q0 SLICE_10 (from PHI2_c)
+ROUTE         1     0.133       R3C9B.Q0 to       R3C9D.D0 ADSubmitted
+CTOF_DEL    ---     0.101       R3C9D.D0 to       R3C9D.F0 SLICE_130
+ROUTE         1     0.143       R3C9D.F0 to       R3C9A.CE PHI2_N_151_enable_1 (to PHI2_c)
+                  --------
+                    0.510   (45.9% logic, 54.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9B.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.860ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_542  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_541  (to PHI2_c -)
+
+   Delay:               0.832ns  (40.3% logic, 59.7% route), 3 logic levels.
+
+ Constraint Details:
+
+      0.832ns physical path delay SLICE_15 to SLICE_19 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 0.860ns
+
+ Physical Path Details:
+
+      Data path SLICE_15 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C9C.CLK to       R3C9C.Q0 SLICE_15 (from PHI2_c)
+ROUTE         2     0.224       R3C9C.Q0 to       R3C9C.B1 C1Submitted
+CTOF_DEL    ---     0.101       R3C9C.B1 to       R3C9C.F1 SLICE_15
+ROUTE         1     0.130       R3C9C.F1 to       R3C9D.A0 n7
+CTOF_DEL    ---     0.101       R3C9D.A0 to       R3C9D.F0 SLICE_130
+ROUTE         1     0.143       R3C9D.F0 to       R3C9A.CE PHI2_N_151_enable_1 (to PHI2_c)
+                  --------
+                    0.832   (40.3% logic, 59.7% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9C.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.873ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_541  (from PHI2_c -)
+   Destination:    FF         Data in        XOR8MEG_544  (to PHI2_c -)
+
+   Delay:               0.845ns  (39.6% logic, 60.4% route), 3 logic levels.
+
+ Constraint Details:
+
+      0.845ns physical path delay SLICE_19 to SLICE_145 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 0.873ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_145:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C9A.CLK to       R3C9A.Q0 SLICE_19 (from PHI2_c)
+ROUTE         1     0.224       R3C9A.Q0 to       R4C9B.B0 CmdEnable
+CTOF_DEL    ---     0.101       R4C9B.B0 to       R4C9B.F0 SLICE_21
+ROUTE         4     0.141       R4C9B.F0 to       R5C9A.D1 XOR8MEG_N_149
+CTOF_DEL    ---     0.101       R5C9A.D1 to       R5C9A.F1 SLICE_110
+ROUTE         1     0.145       R5C9A.F1 to       R5C8A.CE PHI2_N_151_enable_6 (to PHI2_c)
+                  --------
+                    0.845   (39.6% logic, 60.4% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_145:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C8A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.009ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_541  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMShift_547  (to PHI2_c -)
+                   FF                        CmdUFMData_548
+
+   Delay:               0.981ns  (34.1% logic, 65.9% route), 3 logic levels.
+
+ Constraint Details:
+
+      0.981ns physical path delay SLICE_19 to SLICE_161 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 1.009ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_161:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C9A.CLK to       R3C9A.Q0 SLICE_19 (from PHI2_c)
+ROUTE         1     0.224       R3C9A.Q0 to       R4C9B.B0 CmdEnable
+CTOF_DEL    ---     0.101       R4C9B.B0 to       R4C9B.F0 SLICE_21
+ROUTE         4     0.059       R4C9B.F0 to       R4C9B.C1 XOR8MEG_N_149
+CTOF_DEL    ---     0.101       R4C9B.C1 to       R4C9B.F1 SLICE_21
+ROUTE         1     0.363       R4C9B.F1 to       R5C9C.CE PHI2_N_151_enable_3 (to PHI2_c)
+                  --------
+                    0.981   (34.1% logic, 65.9% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_161:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C9C.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.341ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_541  (from PHI2_c -)
+   Destination:    FF         Data in        CmdLEDEN_545  (to PHI2_c -)
+
+   Delay:               1.313ns  (33.2% logic, 66.8% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.313ns physical path delay SLICE_19 to SLICE_20 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 1.341ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C9A.CLK to       R3C9A.Q0 SLICE_19 (from PHI2_c)
+ROUTE         1     0.224       R3C9A.Q0 to       R4C9B.B0 CmdEnable
+CTOF_DEL    ---     0.101       R4C9B.B0 to       R4C9B.F0 SLICE_21
+ROUTE         4     0.335       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.101       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.056       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.101       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     0.262       R5C8D.F1 to       R5C6A.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                    1.313   (33.2% logic, 66.8% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C6A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.341ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_541  (from PHI2_c -)
+   Destination:    FF         Data in        Cmdn8MEGEN_546  (to PHI2_c -)
+
+   Delay:               1.313ns  (33.2% logic, 66.8% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.313ns physical path delay SLICE_19 to SLICE_24 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 1.341ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C9A.CLK to       R3C9A.Q0 SLICE_19 (from PHI2_c)
+ROUTE         1     0.224       R3C9A.Q0 to       R4C9B.B0 CmdEnable
+CTOF_DEL    ---     0.101       R4C9B.B0 to       R4C9B.F0 SLICE_21
+ROUTE         4     0.335       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
+CTOF_DEL    ---     0.101       R5C8D.B0 to       R5C8D.F0 SLICE_112
+ROUTE         1     0.056       R5C8D.F0 to       R5C8D.C1 n4882
+CTOF_DEL    ---     0.101       R5C8D.C1 to       R5C8D.F1 SLICE_112
+ROUTE         2     0.262       R5C8D.F1 to       R5C6B.CE PHI2_N_151_enable_5 (to PHI2_c)
+                  --------
+                    1.313   (33.2% logic, 66.8% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C6B.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 175.457ns (weighted slack = 350.914ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              XOR8MEG_544  (from PHI2_c -)
+   Destination:    FF         Data in        RA11_521  (to PHI2_c +)
+
+   Delay:               0.444ns  (52.7% logic, 47.3% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.444ns physical path delay SLICE_145 to SLICE_32 meets
+     -0.013ns DIN_HLD and
+    -175.000ns delay constraint less
+      0.000ns skew requirement (totaling -175.013ns) by 175.457ns
+
+ Physical Path Details:
+
+      Data path SLICE_145 to SLICE_32:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R5C8A.CLK to       R5C8A.Q0 SLICE_145 (from PHI2_c)
+ROUTE         1     0.210       R5C8A.Q0 to       R5C8C.A0 XOR8MEG
+CTOF_DEL    ---     0.101       R5C8C.A0 to       R5C8C.F0 SLICE_32
+ROUTE         1     0.000       R5C8C.F0 to      R5C8C.DI0 RA11_N_217 (to PHI2_c)
+                  --------
+                    0.444   (52.7% logic, 47.3% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_145:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C8A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_32:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C8C.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 175.815ns (weighted slack = 351.630ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i2  (from PHI2_c +)
+   Destination:    FF         Data in        ADSubmitted_543  (to PHI2_c -)
+
+   Delay:               0.787ns  (42.6% logic, 57.4% route), 3 logic levels.
+
+ Constraint Details:
+
+      0.787ns physical path delay SLICE_143 to SLICE_10 meets
+     -0.028ns CE_HLD and
+    -175.000ns delay constraint less
+      0.000ns skew requirement (totaling -175.028ns) by 175.815ns
+
+ Physical Path Details:
+
+      Data path SLICE_143 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R2C8D.CLK to       R2C8D.Q0 SLICE_143 (from PHI2_c)
+ROUTE         2     0.139       R2C8D.Q0 to       R2C9C.C1 Bank_2
+CTOF_DEL    ---     0.101       R2C9C.C1 to       R2C9C.F1 SLICE_132
+ROUTE         1     0.056       R2C9C.F1 to       R2C9C.C0 n4782
+CTOF_DEL    ---     0.101       R2C9C.C0 to       R2C9C.F0 SLICE_132
+ROUTE         1     0.257       R2C9C.F0 to       R3C9B.CE PHI2_N_151_enable_7 (to PHI2_c)
+                  --------
+                    0.787   (42.6% logic, 57.4% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_143:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R2C8D.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C9B.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
+            1409 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i2  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i3  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_118 to SLICE_118 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_118 to SLICE_118:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R4C9C.CLK to       R4C9C.Q0 SLICE_118 (from RCLK_c)
+ROUTE         1     0.152       R4C9C.Q0 to       R4C9C.M1 n1197 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_118:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R4C9C.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_118:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R4C9C.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i4  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i5  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_127 to SLICE_127 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_127 to SLICE_127:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R4C10B.CLK to      R4C10B.Q0 SLICE_127 (from RCLK_c)
+ROUTE         1     0.152      R4C10B.Q0 to      R4C10B.M1 n1195 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_127:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to     R4C10B.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_127:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to     R4C10B.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CASr_518  (from RCLK_c +)
+   Destination:    FF         Data in        CASr2_519  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_16 to SLICE_16 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_16 to SLICE_16:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R6C10C.CLK to      R6C10C.Q0 SLICE_16 (from RCLK_c)
+ROUTE         1     0.152      R6C10C.Q0 to      R6C10C.M1 CASr (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_16:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to     R6C10C.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_16:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to     R6C10C.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i10  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i11  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_163 to SLICE_163 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_163 to SLICE_163:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R4C10D.CLK to      R4C10D.Q0 SLICE_163 (from RCLK_c)
+ROUTE         1     0.152      R4C10D.Q0 to      R4C10D.M1 n1189 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_163:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to     R4C10D.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_163:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to     R4C10D.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i14  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i15  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_91 to SLICE_91 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_91 to SLICE_91:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R4C8D.CLK to       R4C8D.Q0 SLICE_91 (from RCLK_c)
+ROUTE         1     0.152       R4C8D.Q0 to       R4C8D.M1 n1185 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_91:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R4C8D.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_91:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R4C8D.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i12  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i13  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_94 to SLICE_94 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_94 to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R4C7D.CLK to       R4C7D.Q0 SLICE_94 (from RCLK_c)
+ROUTE         1     0.152       R4C7D.Q0 to       R4C7D.M1 n1187 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R4C7D.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_94:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R4C7D.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              PHI2r_512  (from RCLK_c +)
+   Destination:    FF         Data in        PHI2r2_513  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_95 to SLICE_35 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_95 to SLICE_35:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R4C7A.CLK to       R4C7A.Q0 SLICE_95 (from RCLK_c)
+ROUTE         1     0.152       R4C7A.Q0 to       R4C7B.M1 PHI2r (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_95:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R4C7A.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_35:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R4C7B.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.306ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RASr_515  (from RCLK_c +)
+   Destination:    FF         Data in        RASr2_516  (to RCLK_c +)
+
+   Delay:               0.287ns  (46.3% logic, 53.7% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.287ns physical path delay SLICE_30 to SLICE_30 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.306ns
+
+ Physical Path Details:
+
+      Data path SLICE_30 to SLICE_30:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R5C7A.CLK to       R5C7A.Q0 SLICE_30 (from RCLK_c)
+ROUTE         2     0.154       R5C7A.Q0 to       R5C7A.M1 RASr (to RCLK_c)
+                  --------
+                    0.287   (46.3% logic, 53.7% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_30:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R5C7A.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_30:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R5C7A.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.307ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i0  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i1  (to RCLK_c +)
+
+   Delay:               0.288ns  (46.2% logic, 53.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.288ns physical path delay SLICE_162 to SLICE_162 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.307ns
+
+ Physical Path Details:
+
+      Data path SLICE_162 to SLICE_162:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R3C10C.CLK to      R3C10C.Q0 SLICE_162 (from RCLK_c)
+ROUTE         4     0.155      R3C10C.Q0 to      R3C10C.M1 nRCS_N_172 (to RCLK_c)
+                  --------
+                    0.288   (46.2% logic, 53.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_162:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to     R3C10C.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_162:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to     R3C10C.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_972__i2  (from RCLK_c +)
+   Destination:    FF         Data in        FS_972__i2  (to RCLK_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_0 to SLICE_0 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_0 to SLICE_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R6C6B.CLK to       R6C6B.Q1 SLICE_0 (from RCLK_c)
+ROUTE         3     0.132       R6C6B.Q1 to       R6C6B.A1 FS_2
+CTOF_DEL    ---     0.101       R6C6B.A1 to       R6C6B.F1 SLICE_0
+ROUTE         1     0.000       R6C6B.F1 to      R6C6B.DI1 n93 (to RCLK_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R6C6B.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        52     0.651       63.PADDI to      R6C6B.CLK RCLK_c
+                  --------
+                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.236ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA10_536  (from RCLK_c +)
+   Destination:    Port       Pad            RA[10]
+
+   Data Path Delay:     2.217ns  (81.5% logic, 18.5% route), 2 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_54 and
+      2.217ns delay SLICE_54 to RA[10] (totaling 3.236ns) meets
+      0.000ns hold offset RCLK to RA[10] by 3.236ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_54:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R4C11D.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_54 to RA[10]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R4C11D.CLK to      R4C11D.Q0 SLICE_54 (from RCLK_c)
+ROUTE         1     0.411      R4C11D.Q0 to       64.PADDO n1975
+DOPAD_DEL   ---     1.673       64.PADDO to         64.PAD RA[10]
+                  --------
+                    2.217   (81.5% logic, 18.5% route), 2 logic levels.
+
+Report:    3.236ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.561ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[9]
+
+   Data Path Delay:     2.542ns  (75.0% logic, 25.0% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.542ns delay SLICE_63 to RA[9] (totaling 3.561ns) meets
+      0.000ns hold offset RCLK to RA[9] by 3.561ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[9]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.219      R5C10A.Q0 to       R5C9B.A0 nRowColSel
+CTOF_DEL    ---     0.101       R5C9B.A0 to       R5C9B.F0 SLICE_151
+ROUTE         1     0.416       R5C9B.F0 to       62.PADDO RA_c_9
+DOPAD_DEL   ---     1.673       62.PADDO to         62.PAD RA[9]
+                  --------
+                    2.542   (75.0% logic, 25.0% route), 3 logic levels.
+
+Report:    3.561ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.608ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[8]
+
+   Data Path Delay:     2.589ns  (73.7% logic, 26.3% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.589ns delay SLICE_63 to RA[8] (totaling 3.608ns) meets
+      0.000ns hold offset RCLK to RA[8] by 3.608ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[8]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.231      R5C10A.Q0 to      R4C10D.B1 nRowColSel
+CTOF_DEL    ---     0.101      R4C10D.B1 to      R4C10D.F1 SLICE_163
+ROUTE         1     0.451      R4C10D.F1 to       65.PADDO RA_c_8
+DOPAD_DEL   ---     1.673       65.PADDO to         65.PAD RA[8]
+                  --------
+                    2.589   (73.7% logic, 26.3% route), 3 logic levels.
+
+Report:    3.608ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.552ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[7]
+
+   Data Path Delay:     2.533ns  (75.3% logic, 24.7% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.533ns delay SLICE_63 to RA[7] (totaling 3.552ns) meets
+      0.000ns hold offset RCLK to RA[7] by 3.552ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[7]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.229      R5C10A.Q0 to      R2C10D.D1 nRowColSel
+CTOF_DEL    ---     0.101      R2C10D.D1 to      R2C10D.F1 SLICE_155
+ROUTE         1     0.397      R2C10D.F1 to       75.PADDO RA_c_7
+DOPAD_DEL   ---     1.673       75.PADDO to         75.PAD RA[7]
+                  --------
+                    2.533   (75.3% logic, 24.7% route), 3 logic levels.
+
+Report:    3.552ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.573ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[6]
+
+   Data Path Delay:     2.554ns  (74.7% logic, 25.3% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.554ns delay SLICE_63 to RA[6] (totaling 3.573ns) meets
+      0.000ns hold offset RCLK to RA[6] by 3.573ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[6]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.231      R5C10A.Q0 to      R4C10D.B0 nRowColSel
+CTOF_DEL    ---     0.101      R4C10D.B0 to      R4C10D.F0 SLICE_163
+ROUTE         1     0.416      R4C10D.F0 to       68.PADDO RA_c_6
+DOPAD_DEL   ---     1.673       68.PADDO to         68.PAD RA[6]
+                  --------
+                    2.554   (74.7% logic, 25.3% route), 3 logic levels.
+
+Report:    3.573ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.630ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[5]
+
+   Data Path Delay:     2.611ns  (73.0% logic, 27.0% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.611ns delay SLICE_63 to RA[5] (totaling 3.630ns) meets
+      0.000ns hold offset RCLK to RA[5] by 3.630ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[5]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.283      R5C10A.Q0 to       R2C9A.C1 nRowColSel
+CTOF_DEL    ---     0.101       R2C9A.C1 to       R2C9A.F1 SLICE_157
+ROUTE         1     0.421       R2C9A.F1 to       70.PADDO RA_c_5
+DOPAD_DEL   ---     1.673       70.PADDO to         70.PAD RA[5]
+                  --------
+                    2.611   (73.0% logic, 27.0% route), 3 logic levels.
+
+Report:    3.630ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.630ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[4]
+
+   Data Path Delay:     2.611ns  (73.0% logic, 27.0% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.611ns delay SLICE_63 to RA[4] (totaling 3.630ns) meets
+      0.000ns hold offset RCLK to RA[4] by 3.630ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[4]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.283      R5C10A.Q0 to       R2C8B.C1 nRowColSel
+CTOF_DEL    ---     0.101       R2C8B.C1 to       R2C8B.F1 SLICE_158
+ROUTE         1     0.421       R2C8B.F1 to       74.PADDO RA_c_4
+DOPAD_DEL   ---     1.673       74.PADDO to         74.PAD RA[4]
+                  --------
+                    2.611   (73.0% logic, 27.0% route), 3 logic levels.
+
+Report:    3.630ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.615ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[3]
+
+   Data Path Delay:     2.596ns  (73.5% logic, 26.5% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.596ns delay SLICE_63 to RA[3] (totaling 3.615ns) meets
+      0.000ns hold offset RCLK to RA[3] by 3.615ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[3]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.226      R5C10A.Q0 to      R3C10C.D0 nRowColSel
+CTOF_DEL    ---     0.101      R3C10C.D0 to      R3C10C.F0 SLICE_162
+ROUTE         1     0.463      R3C10C.F0 to       71.PADDO RA_c_3
+DOPAD_DEL   ---     1.673       71.PADDO to         71.PAD RA[3]
+                  --------
+                    2.596   (73.5% logic, 26.5% route), 3 logic levels.
+
+Report:    3.615ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.527ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[2]
+
+   Data Path Delay:     2.508ns  (76.0% logic, 24.0% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.508ns delay SLICE_63 to RA[2] (totaling 3.527ns) meets
+      0.000ns hold offset RCLK to RA[2] by 3.527ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[2]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.145      R5C10A.Q0 to       R5C9C.C0 nRowColSel
+CTOF_DEL    ---     0.101       R5C9C.C0 to       R5C9C.F0 SLICE_161
+ROUTE         1     0.456       R5C9C.F0 to       69.PADDO RA_c_2
+DOPAD_DEL   ---     1.673       69.PADDO to         69.PAD RA[2]
+                  --------
+                    2.508   (76.0% logic, 24.0% route), 3 logic levels.
+
+Report:    3.527ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.549ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[1]
+
+   Data Path Delay:     2.530ns  (75.4% logic, 24.6% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.530ns delay SLICE_63 to RA[1] (totaling 3.549ns) meets
+      0.000ns hold offset RCLK to RA[1] by 3.549ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[1]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.226      R5C10A.Q0 to      R3C10C.D1 nRowColSel
+CTOF_DEL    ---     0.101      R3C10C.D1 to      R3C10C.F1 SLICE_162
+ROUTE         1     0.397      R3C10C.F1 to       67.PADDO RA_c_1
+DOPAD_DEL   ---     1.673       67.PADDO to         67.PAD RA[1]
+                  --------
+                    2.530   (75.4% logic, 24.6% route), 3 logic levels.
+
+Report:    3.549ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.471ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RA[0]
+
+   Data Path Delay:     2.452ns  (77.8% logic, 22.2% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.452ns delay SLICE_63 to RA[0] (totaling 3.471ns) meets
+      0.000ns hold offset RCLK to RA[0] by 3.471ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RA[0]:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.229      R5C10A.Q0 to      R3C10D.D1 nRowColSel
+CTOF_DEL    ---     0.101      R3C10D.D1 to      R3C10D.F1 SLICE_159
+ROUTE         1     0.316      R3C10D.F1 to       66.PADDO RA_c_0
+DOPAD_DEL   ---     1.673       66.PADDO to         66.PAD RA[0]
+                  --------
+                    2.452   (77.8% logic, 22.2% route), 3 logic levels.
+
+Report:    3.471ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.300ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCS_532  (from RCLK_c +)
+   Destination:    Port       Pad            nRCS
+
+   Data Path Delay:     2.281ns  (79.2% logic, 20.8% route), 2 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_59 and
+      2.281ns delay SLICE_59 to nRCS (totaling 3.300ns) meets
+      0.000ns hold offset RCLK to nRCS by 3.300ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_59:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R4C11B.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_59 to nRCS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R4C11B.CLK to      R4C11B.Q0 SLICE_59 (from RCLK_c)
+ROUTE         1     0.475      R4C11B.Q0 to       57.PADDO nRCS_c
+DOPAD_DEL   ---     1.673       57.PADDO to         57.PAD nRCS
+                  --------
+                    2.281   (79.2% logic, 20.8% route), 2 logic levels.
+
+Report:    3.300ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.362ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RCKE_531  (from RCLK_c +)
+   Destination:    Port       Pad            RCKE
+
+   Data Path Delay:     2.343ns  (77.1% logic, 22.9% route), 2 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_35 and
+      2.343ns delay SLICE_35 to RCKE (totaling 3.362ns) meets
+      0.000ns hold offset RCLK to RCKE by 3.362ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_35:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to      R4C7B.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_35 to RCKE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R4C7B.CLK to       R4C7B.Q0 SLICE_35 (from RCLK_c)
+ROUTE         4     0.537       R4C7B.Q0 to       53.PADDO RCKE_c
+DOPAD_DEL   ---     1.673       53.PADDO to         53.PAD RCKE
+                  --------
+                    2.343   (77.1% logic, 22.9% route), 2 logic levels.
+
+Report:    3.362ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.194ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRWE_535  (from RCLK_c +)
+   Destination:    Port       Pad            nRWE
+
+   Data Path Delay:     2.175ns  (83.0% logic, 17.0% route), 2 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_62 and
+      2.175ns delay SLICE_62 to nRWE (totaling 3.194ns) meets
+      0.000ns hold offset RCLK to nRWE by 3.194ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_62:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C11A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_62 to nRWE:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C11A.CLK to      R5C11A.Q0 SLICE_62 (from RCLK_c)
+ROUTE         1     0.369      R5C11A.Q0 to       49.PADDO nRWE_c
+DOPAD_DEL   ---     1.673       49.PADDO to         49.PAD nRWE
+                  --------
+                    2.175   (83.0% logic, 17.0% route), 2 logic levels.
+
+Report:    3.194ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.322ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRRAS_533  (from RCLK_c +)
+   Destination:    Port       Pad            nRRAS
+
+   Data Path Delay:     2.303ns  (78.4% logic, 21.6% route), 2 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_60 and
+      2.303ns delay SLICE_60 to nRRAS (totaling 3.322ns) meets
+      0.000ns hold offset RCLK to nRRAS by 3.322ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R4C11A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_60 to nRRAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R4C11A.CLK to      R4C11A.Q0 SLICE_60 (from RCLK_c)
+ROUTE         1     0.497      R4C11A.Q0 to       54.PADDO nRRAS_c
+DOPAD_DEL   ---     1.673       54.PADDO to         54.PAD nRRAS
+                  --------
+                    2.303   (78.4% logic, 21.6% route), 2 logic levels.
+
+Report:    3.322ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.300ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRCAS_534  (from RCLK_c +)
+   Destination:    Port       Pad            nRCAS
+
+   Data Path Delay:     2.281ns  (79.2% logic, 20.8% route), 2 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_57 and
+      2.281ns delay SLICE_57 to nRCAS (totaling 3.300ns) meets
+      0.000ns hold offset RCLK to nRCAS by 3.300ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C11B.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_57 to nRCAS:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C11B.CLK to      R5C11B.Q0 SLICE_57 (from RCLK_c)
+ROUTE         1     0.475      R5C11B.Q0 to       52.PADDO nRCAS_c
+DOPAD_DEL   ---     1.673       52.PADDO to         52.PAD nRCAS
+                  --------
+                    2.281   (79.2% logic, 20.8% route), 2 logic levels.
+
+Report:    3.300ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.559ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RDQMH
+
+   Data Path Delay:     2.540ns  (75.1% logic, 24.9% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.540ns delay SLICE_63 to RDQMH (totaling 3.559ns) meets
+      0.000ns hold offset RCLK to RDQMH by 3.559ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RDQMH:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.139      R5C10A.Q0 to       R5C9B.D1 nRowColSel
+CTOF_DEL    ---     0.101       R5C9B.D1 to       R5C9B.F1 SLICE_151
+ROUTE         1     0.494       R5C9B.F1 to       51.PADDO RDQMH_c
+DOPAD_DEL   ---     1.673       51.PADDO to         51.PAD RDQMH
+                  --------
+                    2.540   (75.1% logic, 24.9% route), 3 logic levels.
+
+Report:    3.559ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
+            1 item scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed:  The following path meets requirements by 3.470ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
+   Destination:    Port       Pad            RDQML
+
+   Data Path Delay:     2.451ns  (77.8% logic, 22.2% route), 3 logic levels.
+
+   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
+
+ Constraint Details:
+      1.019ns delay RCLK to SLICE_63 and
+      2.451ns delay SLICE_63 to RDQML (totaling 3.470ns) meets
+      0.000ns hold offset RCLK to RDQML by 3.470ns
+
+ Physical Path Details:
+
+      Clock path RCLK to SLICE_63:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
+ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
+                  --------
+                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
+
+      Data path SLICE_63 to RDQML:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
+ROUTE        12     0.145      R5C10A.Q0 to       R5C9C.C1 nRowColSel
+CTOF_DEL    ---     0.101       R5C9C.C1 to       R5C9C.F1 SLICE_161
+ROUTE         1     0.399       R5C9C.F1 to       48.PADDO RDQML_c
+DOPAD_DEL   ---     1.673       48.PADDO to         48.PAD RDQML
+                  --------
+                    2.451   (77.8% logic, 22.2% route), 3 logic levels.
+
+Report:    3.470ns is the maximum offset for this preference.
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+PERIOD NET "PHI2_c" 350.000000 ns  ;    |            -|            -|   2  
+                                        |             |             |
+PERIOD NET "nCCAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "nCRAS_c" 350.000000 ns  ;   |            -|            -|   0  
+                                        |             |             |
+PERIOD NET "RCLK_c" 16.000000 ns  ;     |            -|            -|   1  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
+ns CLKPORT "RCLK" ;                     |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.236 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.561 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.608 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.552 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.573 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.630 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.630 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.615 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.527 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.549 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.471 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.300 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.362 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.194 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.322 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.300 ns|   2  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.559 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |     0.000 ns|     3.470 ns|   3  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
+CLKPORT "RCLK" ;                        |            -|            -|   0  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 5 clocks:
+
+Clock Domain: wb_clk   Source: SLICE_73.Q0   Loads: 1
+   No transfer within this clock domain is found
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 52
+   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: wb_clk   Source: SLICE_73.Q0
+      Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;   Transfers: 2
+
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 1548 paths, 9 nets, and 900 connections (79.58% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 0 (setup), 0 (hold)
+Score: 0 (setup), 0 (hold)
+Cumulative negative slack: 0 (0+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
+
+
+
+
    
+
    
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diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_drc.log b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_drc.log
new file mode 100644
index 0000000..0265ac7
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_drc.log
@@ -0,0 +1,15 @@
+Results of NGD DRC are available in RAM2GS_drc.log.
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+
+
+Running DRC...
+
+DRC complete with no errors or warnings
+
+Design Results:
+    452 blocks expanded
+completed the first expansion
+All blocks are expanded and NGD expansion is successful.
+Writing NGD file RAM2GS_LCMXO2_640HC_impl1.ngd.
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_lse.twr b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_lse.twr
new file mode 100644
index 0000000..71c3f66
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_lse.twr
@@ -0,0 +1,335 @@
+--------------------------------------------------------------------------------
+Lattice Synthesis Timing Report, Version  
+Tue Aug 17 06:19:46 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Design:     RAM2GS
+Constraint file:  
+Report level:    verbose report, limited to 3 items per constraint
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk3 [get_nets PHI2_c]
+            130 items scored, 125 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error:  The following path violates requirements by 10.606ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i4  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdLEDEN_545  (to PHI2_c -)
+
+   Delay:                  12.821ns  (30.4% logic, 69.6% route), 8 logic levels.
+
+ Constraint Details:
+
+     12.821ns data_path Bank_i4 to CmdLEDEN_545 violates
+      2.500ns delay constraint less
+      0.285ns LCE_S requirement (totaling 2.215ns) by 10.606ns
+
+ Path Details: Bank_i4 to CmdLEDEN_545
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              Bank_i4 (from PHI2_c)
+Route         1   e 0.941                                  Bank[4]
+LUT4        ---     0.493              C to Z              i3734_4_lut
+Route         1   e 0.941                                  n4610
+LUT4        ---     0.493              B to Z              i3751_4_lut
+Route         2   e 1.141                                  n4628
+LUT4        ---     0.493              B to Z              i13_4_lut_adj_13
+Route         4   e 1.340                                  n2384
+LUT4        ---     0.493              B to Z              i3712_2_lut_rep_40
+Route         2   e 1.141                                  n4889
+LUT4        ---     0.493              D to Z              i3_4_lut_adj_23
+Route         4   e 1.340                                  XOR8MEG_N_149
+LUT4        ---     0.493              D to Z              i2_3_lut_rep_33_4_lut
+Route         1   e 0.941                                  n4882
+LUT4        ---     0.493              A to Z              i1_3_lut_adj_21
+Route         2   e 1.141                                  PHI2_N_151_enable_5
+                  --------
+                   12.821  (30.4% logic, 69.6% route), 8 logic levels.
+
+
+Error:  The following path violates requirements by 10.606ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i4  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             Cmdn8MEGEN_546  (to PHI2_c -)
+
+   Delay:                  12.821ns  (30.4% logic, 69.6% route), 8 logic levels.
+
+ Constraint Details:
+
+     12.821ns data_path Bank_i4 to Cmdn8MEGEN_546 violates
+      2.500ns delay constraint less
+      0.285ns LCE_S requirement (totaling 2.215ns) by 10.606ns
+
+ Path Details: Bank_i4 to Cmdn8MEGEN_546
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              Bank_i4 (from PHI2_c)
+Route         1   e 0.941                                  Bank[4]
+LUT4        ---     0.493              C to Z              i3734_4_lut
+Route         1   e 0.941                                  n4610
+LUT4        ---     0.493              B to Z              i3751_4_lut
+Route         2   e 1.141                                  n4628
+LUT4        ---     0.493              B to Z              i13_4_lut_adj_13
+Route         4   e 1.340                                  n2384
+LUT4        ---     0.493              B to Z              i3712_2_lut_rep_40
+Route         2   e 1.141                                  n4889
+LUT4        ---     0.493              D to Z              i3_4_lut_adj_23
+Route         4   e 1.340                                  XOR8MEG_N_149
+LUT4        ---     0.493              D to Z              i2_3_lut_rep_33_4_lut
+Route         1   e 0.941                                  n4882
+LUT4        ---     0.493              A to Z              i1_3_lut_adj_21
+Route         2   e 1.141                                  PHI2_N_151_enable_5
+                  --------
+                   12.821  (30.4% logic, 69.6% route), 8 logic levels.
+
+
+Error:  The following path violates requirements by 10.606ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i5  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdLEDEN_545  (to PHI2_c -)
+
+   Delay:                  12.821ns  (30.4% logic, 69.6% route), 8 logic levels.
+
+ Constraint Details:
+
+     12.821ns data_path Bank_i5 to CmdLEDEN_545 violates
+      2.500ns delay constraint less
+      0.285ns LCE_S requirement (totaling 2.215ns) by 10.606ns
+
+ Path Details: Bank_i5 to CmdLEDEN_545
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              Bank_i5 (from PHI2_c)
+Route         1   e 0.941                                  Bank[5]
+LUT4        ---     0.493              B to Z              i3734_4_lut
+Route         1   e 0.941                                  n4610
+LUT4        ---     0.493              B to Z              i3751_4_lut
+Route         2   e 1.141                                  n4628
+LUT4        ---     0.493              B to Z              i13_4_lut_adj_13
+Route         4   e 1.340                                  n2384
+LUT4        ---     0.493              B to Z              i3712_2_lut_rep_40
+Route         2   e 1.141                                  n4889
+LUT4        ---     0.493              D to Z              i3_4_lut_adj_23
+Route         4   e 1.340                                  XOR8MEG_N_149
+LUT4        ---     0.493              D to Z              i2_3_lut_rep_33_4_lut
+Route         1   e 0.941                                  n4882
+LUT4        ---     0.493              A to Z              i1_3_lut_adj_21
+Route         2   e 1.141                                  PHI2_N_151_enable_5
+                  --------
+                   12.821  (30.4% logic, 69.6% route), 8 logic levels.
+
+Warning: 13.106 ns is the maximum delay for this constraint.
+
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCCAS_c]
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk1 [get_nets nCRAS_c]
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c]
+            1392 items scored, 1147 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error:  The following path violates requirements by 10.222ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_972__i8  (from RCLK_c +)
+   Destination:    FD1S3AX    D              wb_adr_i4  (to RCLK_c +)
+
+   Delay:                  15.062ns  (30.7% logic, 69.3% route), 10 logic levels.
+
+ Constraint Details:
+
+     15.062ns data_path FS_972__i8 to wb_adr_i4 violates
+      5.000ns delay constraint less
+      0.160ns L_S requirement (totaling 4.840ns) by 10.222ns
+
+ Path Details: FS_972__i8 to wb_adr_i4
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              FS_972__i8 (from RCLK_c)
+Route        23   e 1.894                                  FS[8]
+LUT4        ---     0.493              B to Z              i1_2_lut_rep_75
+Route         4   e 1.340                                  n4924
+LUT4        ---     0.493              B to Z              i2387_3_lut_4_lut
+Route         1   e 0.941                                  n98
+LUT4        ---     0.493              D to Z              i1_3_lut_4_lut_adj_9
+Route         2   e 1.141                                  n2199
+LUT4        ---     0.493              B to Z              i92_4_lut
+Route         1   e 0.941                                  n53
+LUT4        ---     0.493              C to Z              i3106_3_lut_3_lut
+Route         1   e 0.020                                  n1_adj_6
+MUXL5       ---     0.233           ALUT to Z              i29
+Route         1   e 0.941                                  n14_adj_3
+LUT4        ---     0.493              C to Z              i1_2_lut_2_lut_3_lut
+Route         2   e 1.141                                  n12_adj_8
+LUT4        ---     0.493              C to Z              i1_3_lut_4_lut_adj_11
+Route         2   e 1.141                                  n14_adj_7
+LUT4        ---     0.493              A to Z              i28_3_lut
+Route         1   e 0.941                                  wb_adr_7__N_60[4]
+                  --------
+                   15.062  (30.7% logic, 69.3% route), 10 logic levels.
+
+
+Error:  The following path violates requirements by 10.222ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_972__i8  (from RCLK_c +)
+   Destination:    FD1S3AX    D              wb_adr_i6  (to RCLK_c +)
+
+   Delay:                  15.062ns  (30.7% logic, 69.3% route), 10 logic levels.
+
+ Constraint Details:
+
+     15.062ns data_path FS_972__i8 to wb_adr_i6 violates
+      5.000ns delay constraint less
+      0.160ns L_S requirement (totaling 4.840ns) by 10.222ns
+
+ Path Details: FS_972__i8 to wb_adr_i6
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              FS_972__i8 (from RCLK_c)
+Route        23   e 1.894                                  FS[8]
+LUT4        ---     0.493              B to Z              i1_2_lut_rep_75
+Route         4   e 1.340                                  n4924
+LUT4        ---     0.493              B to Z              i2387_3_lut_4_lut
+Route         1   e 0.941                                  n98
+LUT4        ---     0.493              D to Z              i1_3_lut_4_lut_adj_9
+Route         2   e 1.141                                  n2199
+LUT4        ---     0.493              B to Z              i92_4_lut
+Route         1   e 0.941                                  n53
+LUT4        ---     0.493              C to Z              i3106_3_lut_3_lut
+Route         1   e 0.020                                  n1_adj_6
+MUXL5       ---     0.233           ALUT to Z              i29
+Route         1   e 0.941                                  n14_adj_3
+LUT4        ---     0.493              C to Z              i1_2_lut_2_lut_3_lut
+Route         2   e 1.141                                  n12_adj_8
+LUT4        ---     0.493              C to Z              i1_3_lut_4_lut_adj_11
+Route         2   e 1.141                                  n14_adj_7
+LUT4        ---     0.493              A to Z              i29_3_lut
+Route         1   e 0.941                                  wb_adr_7__N_60[6]
+                  --------
+                   15.062  (30.7% logic, 69.3% route), 10 logic levels.
+
+
+Error:  The following path violates requirements by 10.216ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_972__i6  (from RCLK_c +)
+   Destination:    FD1S3AX    D              wb_adr_i4  (to RCLK_c +)
+
+   Delay:                  15.056ns  (30.7% logic, 69.3% route), 10 logic levels.
+
+ Constraint Details:
+
+     15.056ns data_path FS_972__i6 to wb_adr_i4 violates
+      5.000ns delay constraint less
+      0.160ns L_S requirement (totaling 4.840ns) by 10.216ns
+
+ Path Details: FS_972__i6 to wb_adr_i4
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              FS_972__i6 (from RCLK_c)
+Route        21   e 1.888                                  FS[6]
+LUT4        ---     0.493              A to Z              i1_2_lut_rep_75
+Route         4   e 1.340                                  n4924
+LUT4        ---     0.493              B to Z              i2387_3_lut_4_lut
+Route         1   e 0.941                                  n98
+LUT4        ---     0.493              D to Z              i1_3_lut_4_lut_adj_9
+Route         2   e 1.141                                  n2199
+LUT4        ---     0.493              B to Z              i92_4_lut
+Route         1   e 0.941                                  n53
+LUT4        ---     0.493              C to Z              i3106_3_lut_3_lut
+Route         1   e 0.020                                  n1_adj_6
+MUXL5       ---     0.233           ALUT to Z              i29
+Route         1   e 0.941                                  n14_adj_3
+LUT4        ---     0.493              C to Z              i1_2_lut_2_lut_3_lut
+Route         2   e 1.141                                  n12_adj_8
+LUT4        ---     0.493              C to Z              i1_3_lut_4_lut_adj_11
+Route         2   e 1.141                                  n14_adj_7
+LUT4        ---     0.493              A to Z              i28_3_lut
+Route         1   e 0.941                                  wb_adr_7__N_60[4]
+                  --------
+                   15.056  (30.7% logic, 69.3% route), 10 logic levels.
+
+Warning: 15.222 ns is the maximum delay for this constraint.
+
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk3 [get_nets PHI2_c]                  |     5.000 ns|    26.212 ns|     8 *
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk2 [get_nets nCCAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk1 [get_nets nCRAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets RCLK_c]                  |     5.000 ns|    15.222 ns|    10 *
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+2 constraints not met.
+
+--------------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+--------------------------------------------------------------------------------
+n14                                     |      16|     200|     15.72%
+                                        |        |        |
+n12_adj_8                               |       2|     198|     15.57%
+                                        |        |        |
+n14_adj_3                               |       1|     183|     14.39%
+                                        |        |        |
+n14_adj_7                               |       2|     176|     13.84%
+                                        |        |        |
+--------------------------------------------------------------------------------
+
+
+Timing summary:
+---------------
+
+Timing errors: 1272  Score: 5951146
+
+Constraints cover  1577 paths, 335 nets, and 954 connections (77.9% coverage)
+
+
+Peak memory: 59748352 bytes, TRCE: 3297280 bytes, DLYMAN: 0 bytes
+CPU_TIME_REPORT: 0 secs 
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_lse_lsetwr.html b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_lse_lsetwr.html
new file mode 100644
index 0000000..098f931
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_lse_lsetwr.html
@@ -0,0 +1,402 @@
+
+Lattice Synthesis Timing Report
+
+
+
    Lattice Synthesis Timing Report
+--------------------------------------------------------------------------------
+Lattice Synthesis Timing Report, Version  
+Tue Aug 17 05:43:37 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Design:     RAM2GS
+Constraint file:  
+Report level:    verbose report, limited to 3 items per constraint
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c]
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c]
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c]
+            120 items scored, 116 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error:  The following path violates requirements by 10.528ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i1  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdEnable_541  (to PHI2_c -)
+
+   Delay:                  12.743ns  (30.6% logic, 69.4% route), 8 logic levels.
+
+ Constraint Details:
+
+     12.743ns data_path Bank_i1 to CmdEnable_541 violates
+      2.500ns delay constraint less
+      0.285ns LCE_S requirement (totaling 2.215ns) by 10.528ns
+
+ Path Details: Bank_i1 to CmdEnable_541
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              Bank_i1 (from PHI2_c)
+Route         2   e 1.198                                  Bank[1]
+LUT4        ---     0.493              B to Z              i1819_2_lut
+Route         1   e 0.941                                  n2427
+LUT4        ---     0.493              C to Z              i1857_4_lut
+Route         1   e 0.941                                  n2465
+LUT4        ---     0.493              A to Z              i13_4_lut_adj_4
+Route         5   e 1.405                                  n1712
+LUT4        ---     0.493              A to Z              i1_2_lut_rep_12
+Route         2   e 1.141                                  n2551
+LUT4        ---     0.493              D to Z              i1827_4_lut
+Route         1   e 0.941                                  n2435
+LUT4        ---     0.493              B to Z              i3_4_lut_adj_1
+Route         4   e 1.340                                  C1Submitted_N_200
+LUT4        ---     0.493              C to Z              i34_4_lut
+Route         1   e 0.941                                  PHI2_N_119_enable_1
+                  --------
+                   12.743  (30.6% logic, 69.4% route), 8 logic levels.
+
+
+Error:  The following path violates requirements by 10.471ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i3  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdEnable_541  (to PHI2_c -)
+
+   Delay:                  12.686ns  (30.7% logic, 69.3% route), 8 logic levels.
+
+ Constraint Details:
+
+     12.686ns data_path Bank_i3 to CmdEnable_541 violates
+      2.500ns delay constraint less
+      0.285ns LCE_S requirement (totaling 2.215ns) by 10.471ns
+
+ Path Details: Bank_i3 to CmdEnable_541
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              Bank_i3 (from PHI2_c)
+Route         1   e 0.941                                  Bank[3]
+LUT4        ---     0.493              B to Z              i1799_2_lut
+Route         2   e 1.141                                  n2407
+LUT4        ---     0.493              A to Z              i1857_4_lut
+Route         1   e 0.941                                  n2465
+LUT4        ---     0.493              A to Z              i13_4_lut_adj_4
+Route         5   e 1.405                                  n1712
+LUT4        ---     0.493              A to Z              i1_2_lut_rep_12
+Route         2   e 1.141                                  n2551
+LUT4        ---     0.493              D to Z              i1827_4_lut
+Route         1   e 0.941                                  n2435
+LUT4        ---     0.493              B to Z              i3_4_lut_adj_1
+Route         4   e 1.340                                  C1Submitted_N_200
+LUT4        ---     0.493              C to Z              i34_4_lut
+Route         1   e 0.941                                  PHI2_N_119_enable_1
+                  --------
+                   12.686  (30.7% logic, 69.3% route), 8 logic levels.
+
+
+Error:  The following path violates requirements by 10.471ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i6  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdEnable_541  (to PHI2_c -)
+
+   Delay:                  12.686ns  (30.7% logic, 69.3% route), 8 logic levels.
+
+ Constraint Details:
+
+     12.686ns data_path Bank_i6 to CmdEnable_541 violates
+      2.500ns delay constraint less
+      0.285ns LCE_S requirement (totaling 2.215ns) by 10.471ns
+
+ Path Details: Bank_i6 to CmdEnable_541
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              Bank_i6 (from PHI2_c)
+Route         1   e 0.941                                  Bank[6]
+LUT4        ---     0.493              A to Z              i1799_2_lut
+Route         2   e 1.141                                  n2407
+LUT4        ---     0.493              A to Z              i1857_4_lut
+Route         1   e 0.941                                  n2465
+LUT4        ---     0.493              A to Z              i13_4_lut_adj_4
+Route         5   e 1.405                                  n1712
+LUT4        ---     0.493              A to Z              i1_2_lut_rep_12
+Route         2   e 1.141                                  n2551
+LUT4        ---     0.493              D to Z              i1827_4_lut
+Route         1   e 0.941                                  n2435
+LUT4        ---     0.493              B to Z              i3_4_lut_adj_1
+Route         4   e 1.340                                  C1Submitted_N_200
+LUT4        ---     0.493              C to Z              i34_4_lut
+Route         1   e 0.941                                  PHI2_N_119_enable_1
+                  --------
+                   12.686  (30.7% logic, 69.3% route), 8 logic levels.
+
+Warning: 13.028 ns is the maximum delay for this constraint.
+
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c]
+            466 items scored, 158 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error:  The following path violates requirements by 3.233ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_725__i9  (from RCLK_c +)
+   Destination:    FD1P3IX    SP             n8MEGEN_557  (to RCLK_c +)
+
+   Delay:                   7.948ns  (33.3% logic, 66.7% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.948ns data_path FS_725__i9 to n8MEGEN_557 violates
+      5.000ns delay constraint less
+      0.285ns LCE_S requirement (totaling 4.715ns) by 3.233ns
+
+ Path Details: FS_725__i9 to n8MEGEN_557
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              FS_725__i9 (from RCLK_c)
+Route         3   e 1.315                                  FS[9]
+LUT4        ---     0.493              A to Z              i1847_4_lut
+Route         1   e 0.941                                  n2455
+LUT4        ---     0.493              B to Z              i1855_4_lut
+Route         1   e 0.941                                  n2463
+LUT4        ---     0.493              B to Z              i14_4_lut
+Route         1   e 0.941                                  n2384
+LUT4        ---     0.493              D to Z              i3_4_lut_adj_13
+Route         1   e 0.020                                  n2385
+MUXL5       ---     0.233           BLUT to Z              i26
+Route         2   e 1.141                                  RCLK_c_enable_10
+                  --------
+                    7.948  (33.3% logic, 66.7% route), 6 logic levels.
+
+
+Error:  The following path violates requirements by 3.233ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_725__i9  (from RCLK_c +)
+   Destination:    FD1P3IX    SP             LEDEN_556  (to RCLK_c +)
+
+   Delay:                   7.948ns  (33.3% logic, 66.7% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.948ns data_path FS_725__i9 to LEDEN_556 violates
+      5.000ns delay constraint less
+      0.285ns LCE_S requirement (totaling 4.715ns) by 3.233ns
+
+ Path Details: FS_725__i9 to LEDEN_556
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              FS_725__i9 (from RCLK_c)
+Route         3   e 1.315                                  FS[9]
+LUT4        ---     0.493              A to Z              i1847_4_lut
+Route         1   e 0.941                                  n2455
+LUT4        ---     0.493              B to Z              i1855_4_lut
+Route         1   e 0.941                                  n2463
+LUT4        ---     0.493              B to Z              i14_4_lut
+Route         1   e 0.941                                  n2384
+LUT4        ---     0.493              D to Z              i3_4_lut_adj_13
+Route         1   e 0.020                                  n2385
+MUXL5       ---     0.233           BLUT to Z              i26
+Route         2   e 1.141                                  RCLK_c_enable_10
+                  --------
+                    7.948  (33.3% logic, 66.7% route), 6 logic levels.
+
+
+Error:  The following path violates requirements by 3.233ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_725__i8  (from RCLK_c +)
+   Destination:    FD1P3IX    SP             n8MEGEN_557  (to RCLK_c +)
+
+   Delay:                   7.948ns  (33.3% logic, 66.7% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.948ns data_path FS_725__i8 to n8MEGEN_557 violates
+      5.000ns delay constraint less
+      0.285ns LCE_S requirement (totaling 4.715ns) by 3.233ns
+
+ Path Details: FS_725__i8 to n8MEGEN_557
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              FS_725__i8 (from RCLK_c)
+Route         3   e 1.315                                  FS[8]
+LUT4        ---     0.493              B to Z              i1821_2_lut
+Route         1   e 0.941                                  n2429
+LUT4        ---     0.493              C to Z              i1855_4_lut
+Route         1   e 0.941                                  n2463
+LUT4        ---     0.493              B to Z              i14_4_lut
+Route         1   e 0.941                                  n2384
+LUT4        ---     0.493              D to Z              i3_4_lut_adj_13
+Route         1   e 0.020                                  n2385
+MUXL5       ---     0.233           BLUT to Z              i26
+Route         2   e 1.141                                  RCLK_c_enable_10
+                  --------
+                    7.948  (33.3% logic, 66.7% route), 6 logic levels.
+
+Warning: 8.233 ns is the maximum delay for this constraint.
+
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk1 [get_nets PHI2_c]                  |     5.000 ns|    26.056 ns|     8 *
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets RCLK_c]                  |     5.000 ns|     8.233 ns|     6 *
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+2 constraints not met.
+
+--------------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+--------------------------------------------------------------------------------
+n1712                                   |       5|     104|     37.96%
+                                        |        |        |
+n2465                                   |       1|      52|     18.98%
+                                        |        |        |
+n2251                                   |       1|      41|     14.96%
+                                        |        |        |
+n2551                                   |       2|      40|     14.60%
+                                        |        |        |
+n2250                                   |       1|      39|     14.23%
+                                        |        |        |
+n2252                                   |       1|      39|     14.23%
+                                        |        |        |
+XOR8MEG_N_117                           |       3|      34|     12.41%
+                                        |        |        |
+n2249                                   |       1|      33|     12.04%
+                                        |        |        |
+n2253                                   |       1|      33|     12.04%
+                                        |        |        |
+C1Submitted_N_200                       |       4|      32|     11.68%
+                                        |        |        |
+n2379                                   |       2|      32|     11.68%
+                                        |        |        |
+n2435                                   |       1|      32|     11.68%
+                                        |        |        |
+RCLK_c_enable_10                        |       2|      30|     10.95%
+                                        |        |        |
+n2384                                   |       1|      30|     10.95%
+                                        |        |        |
+n2385                                   |       1|      30|     10.95%
+                                        |        |        |
+n2407                                   |       2|      28|     10.22%
+                                        |        |        |
+n2453                                   |       2|      28|     10.22%
+                                        |        |        |
+--------------------------------------------------------------------------------
+
+
+Timing summary:
+---------------
+
+Timing errors: 274  Score: 1700966
+
+Constraints cover  587 paths, 177 nets, and 436 connections (66.4% coverage)
+
+
+Peak memory: 55074816 bytes, TRCE: 434176 bytes, DLYMAN: 0 bytes
+CPU_TIME_REPORT: 0 secs 
+
+
+
+
    
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+
    
+
    
+
    
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+
    
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+
    
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diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_prim.v b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_prim.v
new file mode 100644
index 0000000..e6fdb98
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_prim.v
@@ -0,0 +1,1243 @@
+// Verilog netlist produced by program LSE :  version Diamond (64-bit) 3.12.0.240.2
+// Netlist written on Tue Aug 17 06:19:46 2021
+//
+// Verilog Description of module RAM2GS
+//
+
+module RAM2GS (PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, 
+            LED, RBA, RA, RD, nRCS, RCLK, RCKE, nRWE, nRRAS, 
+            nRCAS, RDQMH, RDQML) /* synthesis syn_module_defined=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(1[8:14])
+    input PHI2;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(7[8:12])
+    input [9:0]MAin;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(34[14:18])
+    input [1:0]CROW;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(33[14:18])
+    input [7:0]Din;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(25[14:17])
+    output [7:0]Dout;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(26[15:19])
+    input nCCAS;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(15[8:13])
+    input nCRAS;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(15[15:20])
+    input nFWE;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(35[8:12])
+    output LED;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(11[9:12])
+    output [1:0]RBA;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(46[19:22])
+    output [11:0]RA;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(51[16:18])
+    inout [7:0]RD;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(59[14:16])
+    output nRCS;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(45[13:17])
+    input RCLK;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(40[8:12])
+    output RCKE;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(44[13:17])
+    output nRWE;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(45[45:49])
+    output nRRAS;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(45[23:28])
+    output nRCAS;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(45[34:39])
+    output RDQMH;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(55[16:21])
+    output RDQML;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(55[9:14])
+    
+    wire PHI2_c /* synthesis is_clock=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(7[8:12])
+    wire nCCAS_c /* synthesis is_clock=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(15[8:13])
+    wire nCRAS_c /* synthesis is_clock=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(15[15:20])
+    wire RCLK_c /* synthesis SET_AS_NETWORK=RCLK_c, is_clock=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(40[8:12])
+    wire wb_clk /* synthesis is_clock=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(317[6:12])
+    wire nCCAS_N_3 /* synthesis is_inv_clock=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(26[15:19])
+    wire nCRAS_N_9 /* synthesis is_inv_clock=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(46[19:22])
+    wire PHI2_N_151 /* synthesis is_inv_clock=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(37[6:13])
+    
+    wire GND_net, VCC_net, LEDEN, PHI2r, PHI2r2, PHI2r3, RASr, 
+        RASr2, RASr3, CASr, CASr2, CASr3, FWEr, CBR, Din_c_7, 
+        Din_c_6, Din_c_5, Din_c_4, Din_c_3, Din_c_2, Din_c_1, Din_c_0;
+    wire [7:0]Bank;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(30[12:16])
+    
+    wire CROW_c_1, CROW_c_0, MAin_c_9, MAin_c_8, MAin_c_7, MAin_c_6, 
+        MAin_c_5, MAin_c_4, MAin_c_3, MAin_c_2, MAin_c_1, MAin_c_0, 
+        nFWE_c, n8MEGEN, XOR8MEG, RCKEEN, RCKE_c, nRCS_c, nRRAS_c, 
+        nRCAS_c, nRWE_c, RBA_c_1, RBA_c_0, nRowColSel, RA_c, n1975;
+    wire [9:0]RowA;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(50[12:16])
+    
+    wire RA_c_9, RA_c_8, RA_c_7, RA_c_6, RA_c_5, RA_c_4, RA_c_3, 
+        RA_c_2, RA_c_1, RA_c_0, RDQML_c, RDQMH_c;
+    wire [7:0]WRD;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(58[12:15])
+    
+    wire C1Submitted, ADSubmitted, CmdEnable, CmdSubmitted, CmdLEDEN, 
+        Cmdn8MEGEN, CmdUFMData, CmdUFMShift, n4097, InitReady, Ready, 
+        n10;
+    wire [17:0]FS;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(78[13:15])
+    
+    wire wb_rst, wb_cyc_stb, wb_we;
+    wire [7:0]wb_adr;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(321[12:18])
+    wire [7:0]wb_dati;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(322[12:19])
+    wire [1:0]wb_dato;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(323[13:20])
+    
+    wire LED_N_134, RA11_N_217, n1197, n3, RCKE_N_165, nRowColSel_N_35, 
+        nRWE_N_215, nRowColSel_N_34, nRowColSel_N_33, nRowColSel_N_32, 
+        nRCS_N_179, n2557, nRCS_N_175, n2556, n4883, nRCS_N_174, 
+        nRCAS_N_199, nRWE_N_211, RCKEEN_N_153, nRCS_N_172, nRCAS_N_198, 
+        nRWE_N_210, nRWE_N_209, n1196, n1195, n1194, n1193, n3622, 
+        Ready_N_284, nRCS_N_170, Ready_N_280, nRCS_N_169, nRRAS_N_189, 
+        nRCAS_N_194, nRWE_N_204, RCKEEN_N_152, n3989, n1, CmdEnable_N_243, 
+        C1Submitted_N_232, XOR8MEG_N_149, CmdLEDEN_N_251, Cmdn8MEGEN_N_260, 
+        n4901, n2199, wb_adr_7__N_92, RCLK_c_enable_27, n4149, n17, 
+        wb_we_N_354, n2426, n5144, n4539, n93, n38, n4900, n87, 
+        wb_we_N_351, n638, n646, n4893, wb_cyc_stb_N_350, n4888, 
+        n5142, n4087, wb_cyc_stb_N_348, n89, n4880, n80, n4899, 
+        n2238, n746, n747, n748, n751, n752, n754, n755, n756, 
+        n757, n758, n759, n760, n761, n4094, n4093, n4882, n4628, 
+        n23, n4624, n4892, n4092, n4622, n3609, n4091, LEDEN_N_110, 
+        n8MEGEN_N_139, PHI2_N_151_enable_3, n4610, RCLK_c_enable_25, 
+        RCLK_c_enable_28, n4887, n4548, n84, wb_we_N_338, n2549, 
+        n83, n1969, n1971, wb_cyc_stb_N_307, n4517;
+    wire [7:0]wb_adr_7__N_60;
+    wire [7:0]wb_dati_7__N_68;
+    
+    wire n1192, n1191, n1189, n1188, n1187, n1186, n1185, n6, 
+        n3_adj_1, n4519, n2308, n14, n86, n39, PHI2_N_151_enable_1, 
+        n12, n2040, n2104, n1286, n4869, PHI2_N_151_enable_5, RCLK_c_enable_24, 
+        n4165, n1972, Dout_c, n1965, n1974, n10_adj_2, n78, n2262, 
+        n2252, n2258, n1973, n14_adj_3, n4884, n2244, n1885, n56, 
+        n4859, n4858, n1889, RCLK_c_enable_20, RCLK_c_enable_29, n4898, 
+        n45, n53, n85, n92, RCLK_c_enable_26, n4526, n4090, n1970, 
+        n4939, n4938, n95, n4937, n4089, n2384, n4850, n42, 
+        n3_adj_4, n4936, n1968, n91, n94, n90, n88, n79, n4935, 
+        n42_adj_5, n81, n82, n1_adj_6, n14_adj_7, n4574, n4504, 
+        n4088, n4086, n12_adj_8, n4934, PHI2_N_151_enable_6, n4933, 
+        n4585, n4932, n4733, n98, n4732, n3671, n4931, n4930, 
+        n4125, n4929, n4928, n4731, n4927, n4926, n4925, n4924, 
+        n4730, n4897, n4923, RCLK_c_enable_22, n4729, n53_adj_9, 
+        n175, n4921, n4920, n4919, n4164, n4918, n4917, n4916, 
+        n4915, n12_adj_10, n4914, n4913, n4896, n4807, n4806, 
+        n4582, n15, n4129, n3969, n4911, n3711, n4910, n4527, 
+        n4909, n4530, n4891, n6_adj_11, n4718, n4908, n6_adj_12, 
+        n4895, n4890, n4886, n4, n4907, n4_adj_13, PHI2_N_151_enable_7, 
+        n4782, n4889, n4894, n14_adj_14, n4885, n4777, n4776, 
+        n6_adj_15, n4906, n4905, n4941, n4632, n4513, n3_adj_16, 
+        n20, n4904, n4775, n4618, n4774, n4634, n22, n4903, 
+        n4902, n4940, n7;
+    
+    VHI i2 (.Z(VCC_net));
+    INV i4006 (.A(nCCAS_c), .Z(nCCAS_N_3));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(15[8:13])
+    FD1P3AX IS_FSM__i15 (.D(n1185), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
+            .Q(Ready_N_284));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15])
+    defparam IS_FSM__i15.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i14 (.D(n1186), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
+            .Q(n1185));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15])
+    defparam IS_FSM__i14.GSR = "ENABLED";
+    FD1S3AX PHI2r2_513 (.D(PHI2r), .CK(RCLK_c), .Q(PHI2r2));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(83[9] 87[5])
+    defparam PHI2r2_513.GSR = "ENABLED";
+    FD1S3AX PHI2r3_514 (.D(PHI2r2), .CK(RCLK_c), .Q(PHI2r3));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(83[9] 87[5])
+    defparam PHI2r3_514.GSR = "ENABLED";
+    FD1S3AX RASr_515 (.D(nCRAS_N_9), .CK(RCLK_c), .Q(RASr));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(83[9] 87[5])
+    defparam RASr_515.GSR = "ENABLED";
+    FD1S3AX RASr2_516 (.D(RASr), .CK(RCLK_c), .Q(RASr2));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(83[9] 87[5])
+    defparam RASr2_516.GSR = "ENABLED";
+    FD1S3AX RASr3_517 (.D(RASr2), .CK(RCLK_c), .Q(RASr3));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(83[9] 87[5])
+    defparam RASr3_517.GSR = "ENABLED";
+    FD1S3AX CASr_518 (.D(nCCAS_N_3), .CK(RCLK_c), .Q(CASr));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(83[9] 87[5])
+    defparam CASr_518.GSR = "ENABLED";
+    FD1S3AX CASr2_519 (.D(CASr), .CK(RCLK_c), .Q(CASr2));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(83[9] 87[5])
+    defparam CASr2_519.GSR = "ENABLED";
+    FD1S3AX CASr3_520 (.D(CASr2), .CK(RCLK_c), .Q(CASr3));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(83[9] 87[5])
+    defparam CASr3_520.GSR = "ENABLED";
+    FD1S3IX RowA_i0 (.D(MAin_c_0), .CK(nCRAS_N_9), .CD(n4935), .Q(RowA[0]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5])
+    defparam RowA_i0.GSR = "ENABLED";
+    FD1S3IX S_FSM_i2 (.D(n2556), .CK(RCLK_c), .CD(n4933), .Q(nRowColSel_N_34));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123[13:16])
+    defparam S_FSM_i2.GSR = "ENABLED";
+    FD1S3AX WRD_i0 (.D(Din_c_0), .CK(nCCAS_N_3), .Q(WRD[0]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(115[9] 117[5])
+    defparam WRD_i0.GSR = "ENABLED";
+    FD1S3AX FWEr_525 (.D(n4932), .CK(nCRAS_N_9), .Q(FWEr));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5])
+    defparam FWEr_525.GSR = "ENABLED";
+    FD1S3AX CBR_526 (.D(nCCAS_N_3), .CK(nCRAS_N_9), .Q(CBR));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5])
+    defparam CBR_526.GSR = "ENABLED";
+    FD1S3IX RBA__i1 (.D(CROW_c_0), .CK(nCRAS_N_9), .CD(n4935), .Q(RBA_c_0));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5])
+    defparam RBA__i1.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i13 (.D(n1187), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
+            .Q(n1186));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15])
+    defparam IS_FSM__i13.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i12 (.D(n1188), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
+            .Q(n1187));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15])
+    defparam IS_FSM__i12.GSR = "ENABLED";
+    EFB ufmefb (.WBCLKI(wb_clk), .WBRSTI(wb_rst), .WBCYCI(wb_cyc_stb), 
+        .WBSTBI(wb_cyc_stb), .WBWEI(wb_we), .WBADRI0(wb_adr[0]), .WBADRI1(wb_adr[1]), 
+        .WBADRI2(wb_adr[2]), .WBADRI3(wb_adr[3]), .WBADRI4(wb_adr[4]), 
+        .WBADRI5(wb_adr[5]), .WBADRI6(wb_adr[6]), .WBADRI7(wb_adr[7]), 
+        .WBDATI0(wb_dati[0]), .WBDATI1(wb_dati[1]), .WBDATI2(wb_dati[2]), 
+        .WBDATI3(wb_dati[3]), .WBDATI4(wb_dati[4]), .WBDATI5(wb_dati[5]), 
+        .WBDATI6(wb_dati[6]), .WBDATI7(wb_dati[7]), .I2C1SCLI(GND_net), 
+        .I2C1SDAI(GND_net), .I2C2SCLI(GND_net), .I2C2SDAI(GND_net), .SPISCKI(GND_net), 
+        .SPIMISOI(GND_net), .SPIMOSII(GND_net), .SPISCSN(GND_net), .TCCLKI(GND_net), 
+        .TCRSTN(GND_net), .TCIC(GND_net), .PLL0DATI0(GND_net), .PLL0DATI1(GND_net), 
+        .PLL0DATI2(GND_net), .PLL0DATI3(GND_net), .PLL0DATI4(GND_net), 
+        .PLL0DATI5(GND_net), .PLL0DATI6(GND_net), .PLL0DATI7(GND_net), 
+        .PLL0ACKI(GND_net), .PLL1DATI0(GND_net), .PLL1DATI1(GND_net), 
+        .PLL1DATI2(GND_net), .PLL1DATI3(GND_net), .PLL1DATI4(GND_net), 
+        .PLL1DATI5(GND_net), .PLL1DATI6(GND_net), .PLL1DATI7(GND_net), 
+        .PLL1ACKI(GND_net), .WBDATO0(wb_dato[0]), .WBDATO1(wb_dato[1])) /* synthesis syn_instantiated=1 */ ;
+    defparam ufmefb.EFB_I2C1 = "DISABLED";
+    defparam ufmefb.EFB_I2C2 = "DISABLED";
+    defparam ufmefb.EFB_SPI = "DISABLED";
+    defparam ufmefb.EFB_TC = "DISABLED";
+    defparam ufmefb.EFB_TC_PORTMODE = "NO_WB";
+    defparam ufmefb.EFB_UFM = "DISABLED";
+    defparam ufmefb.EFB_WB_CLK_FREQ = "50.0";
+    defparam ufmefb.DEV_DENSITY = "1200L";
+    defparam ufmefb.UFM_INIT_PAGES = 0;
+    defparam ufmefb.UFM_INIT_START_PAGE = 0;
+    defparam ufmefb.UFM_INIT_ALL_ZEROS = "ENABLED";
+    defparam ufmefb.UFM_INIT_FILE_NAME = "NONE";
+    defparam ufmefb.UFM_INIT_FILE_FORMAT = "HEX";
+    defparam ufmefb.I2C1_ADDRESSING = "7BIT";
+    defparam ufmefb.I2C2_ADDRESSING = "7BIT";
+    defparam ufmefb.I2C1_SLAVE_ADDR = "0b1000001";
+    defparam ufmefb.I2C2_SLAVE_ADDR = "0b1000010";
+    defparam ufmefb.I2C1_BUS_PERF = "100kHz";
+    defparam ufmefb.I2C2_BUS_PERF = "100kHz";
+    defparam ufmefb.I2C1_CLK_DIVIDER = 1;
+    defparam ufmefb.I2C2_CLK_DIVIDER = 1;
+    defparam ufmefb.I2C1_GEN_CALL = "DISABLED";
+    defparam ufmefb.I2C2_GEN_CALL = "DISABLED";
+    defparam ufmefb.I2C1_WAKEUP = "DISABLED";
+    defparam ufmefb.I2C2_WAKEUP = "DISABLED";
+    defparam ufmefb.SPI_MODE = "SLAVE";
+    defparam ufmefb.SPI_CLK_DIVIDER = 1;
+    defparam ufmefb.SPI_LSB_FIRST = "DISABLED";
+    defparam ufmefb.SPI_CLK_INV = "DISABLED";
+    defparam ufmefb.SPI_PHASE_ADJ = "DISABLED";
+    defparam ufmefb.SPI_SLAVE_HANDSHAKE = "DISABLED";
+    defparam ufmefb.SPI_INTR_TXRDY = "DISABLED";
+    defparam ufmefb.SPI_INTR_RXRDY = "DISABLED";
+    defparam ufmefb.SPI_INTR_TXOVR = "DISABLED";
+    defparam ufmefb.SPI_INTR_RXOVR = "DISABLED";
+    defparam ufmefb.SPI_WAKEUP = "DISABLED";
+    defparam ufmefb.TC_MODE = "CTCM";
+    defparam ufmefb.TC_SCLK_SEL = "PCLOCK";
+    defparam ufmefb.TC_CCLK_SEL = 1;
+    defparam ufmefb.GSR = "ENABLED";
+    defparam ufmefb.TC_TOP_SET = 65535;
+    defparam ufmefb.TC_OCR_SET = 32767;
+    defparam ufmefb.TC_OC_MODE = "TOGGLE";
+    defparam ufmefb.TC_RESETN = "ENABLED";
+    defparam ufmefb.TC_TOP_SEL = "ON";
+    defparam ufmefb.TC_OV_INT = "OFF";
+    defparam ufmefb.TC_OCR_INT = "OFF";
+    defparam ufmefb.TC_ICR_INT = "OFF";
+    defparam ufmefb.TC_OVERFLOW = "ENABLED";
+    defparam ufmefb.TC_ICAPTURE = "DISABLED";
+    FD1P3AX IS_FSM__i11 (.D(n1189), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
+            .Q(n1188));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15])
+    defparam IS_FSM__i11.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i10 (.D(nRWE_N_210), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
+            .Q(n1189));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15])
+    defparam IS_FSM__i10.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i9 (.D(n1191), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
+            .Q(nRWE_N_210));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15])
+    defparam IS_FSM__i9.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i8 (.D(n1192), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
+            .Q(n1191));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15])
+    defparam IS_FSM__i8.GSR = "ENABLED";
+    FD1S3AX RCKE_531 (.D(RCKE_N_165), .CK(RCLK_c), .Q(RCKE_c)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(133[9] 136[5])
+    defparam RCKE_531.GSR = "ENABLED";
+    FD1P3AY nRCS_532 (.D(nRCS_N_169), .SP(RCLK_c_enable_20), .CK(RCLK_c), 
+            .Q(nRCS_c)) /* synthesis lse_init_val=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(139[9] 277[5])
+    defparam nRCS_532.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i7 (.D(n1193), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
+            .Q(n1192));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15])
+    defparam IS_FSM__i7.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i6 (.D(n1194), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
+            .Q(n1193));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15])
+    defparam IS_FSM__i6.GSR = "ENABLED";
+    FD1S3IX S_FSM_i3 (.D(n2556), .CK(RCLK_c), .CD(n2557), .Q(nRowColSel_N_33));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123[13:16])
+    defparam S_FSM_i3.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i5 (.D(n1195), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
+            .Q(n1194));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15])
+    defparam IS_FSM__i5.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i4 (.D(n1196), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
+            .Q(n1195));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15])
+    defparam IS_FSM__i4.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i3 (.D(n1197), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
+            .Q(n1196));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15])
+    defparam IS_FSM__i3.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i2 (.D(nRCAS_N_198), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
+            .Q(n1197));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15])
+    defparam IS_FSM__i2.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i1 (.D(nRCS_N_172), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
+            .Q(nRCAS_N_198));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15])
+    defparam IS_FSM__i1.GSR = "ENABLED";
+    FD1P3AY nRRAS_533 (.D(nRRAS_N_189), .SP(RCLK_c_enable_20), .CK(RCLK_c), 
+            .Q(nRRAS_c)) /* synthesis lse_init_val=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(139[9] 277[5])
+    defparam nRRAS_533.GSR = "ENABLED";
+    LUT4 m1_lut (.Z(n5144)) /* synthesis lut_function=1, syn_instantiated=1 */ ;
+    defparam m1_lut.init = 16'hffff;
+    FD1P3AY nRCAS_534 (.D(nRCAS_N_194), .SP(RCLK_c_enable_20), .CK(RCLK_c), 
+            .Q(nRCAS_c)) /* synthesis lse_init_val=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(139[9] 277[5])
+    defparam nRCAS_534.GSR = "ENABLED";
+    FD1P3AY nRWE_535 (.D(nRWE_N_204), .SP(RCLK_c_enable_29), .CK(RCLK_c), 
+            .Q(nRWE_c)) /* synthesis lse_init_val=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(139[9] 277[5])
+    defparam nRWE_535.GSR = "ENABLED";
+    FD1S3JX RA10_536 (.D(n4129), .CK(RCLK_c), .PD(nRWE_N_209), .Q(n1975));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(139[9] 277[5])
+    defparam RA10_536.GSR = "ENABLED";
+    FD1P3AX RCKEEN_537 (.D(RCKEEN_N_152), .SP(RCLK_c_enable_20), .CK(RCLK_c), 
+            .Q(RCKEEN));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(139[9] 277[5])
+    defparam RCKEEN_537.GSR = "ENABLED";
+    FD1S3JX C1Submitted_542 (.D(n2549), .CK(PHI2_N_151), .PD(C1Submitted_N_232), 
+            .Q(C1Submitted)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(280[9] 315[5])
+    defparam C1Submitted_542.GSR = "ENABLED";
+    FD1P3IX wb_we_553 (.D(wb_we_N_338), .SP(RCLK_c_enable_25), .CD(wb_adr_7__N_92), 
+            .CK(RCLK_c), .Q(wb_we));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_we_553.GSR = "ENABLED";
+    LUT4 nRCS_I_34_3_lut_4_lut (.A(RCKE_c), .B(RASr2), .C(nRowColSel_N_35), 
+         .D(nRCS_N_175), .Z(nRCS_N_174)) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C+(D))))) */ ;
+    defparam nRCS_I_34_3_lut_4_lut.init = 16'h1f10;
+    FD1S3AX CmdSubmitted_549 (.D(XOR8MEG_N_149), .CK(PHI2_N_151), .Q(CmdSubmitted)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(280[9] 315[5])
+    defparam CmdSubmitted_549.GSR = "ENABLED";
+    FD1S3AX FS_972__i17 (.D(n78), .CK(RCLK_c), .Q(FS[17])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972__i17.GSR = "ENABLED";
+    PFUMX i12 (.BLUT(n3), .ALUT(n758), .C0(InitReady), .Z(wb_dati_7__N_68[3]));
+    FD1S3AX FS_972__i16 (.D(n79), .CK(RCLK_c), .Q(FS[16])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972__i16.GSR = "ENABLED";
+    FD1S3AX FS_972__i15 (.D(n80), .CK(RCLK_c), .Q(FS[15])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972__i15.GSR = "ENABLED";
+    FD1S3AX FS_972__i14 (.D(n81), .CK(RCLK_c), .Q(FS[14])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972__i14.GSR = "ENABLED";
+    FD1S3AX FS_972__i13 (.D(n82), .CK(RCLK_c), .Q(FS[13])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972__i13.GSR = "ENABLED";
+    FD1S3AX FS_972__i12 (.D(n83), .CK(RCLK_c), .Q(FS[12])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972__i12.GSR = "ENABLED";
+    FD1S3AX FS_972__i11 (.D(n84), .CK(RCLK_c), .Q(FS[11])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972__i11.GSR = "ENABLED";
+    FD1S3AX FS_972__i10 (.D(n85), .CK(RCLK_c), .Q(FS[10])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972__i10.GSR = "ENABLED";
+    FD1S3AX FS_972__i9 (.D(n86), .CK(RCLK_c), .Q(FS[9])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972__i9.GSR = "ENABLED";
+    FD1S3AX FS_972__i8 (.D(n87), .CK(RCLK_c), .Q(FS[8])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972__i8.GSR = "ENABLED";
+    FD1S3AX FS_972__i7 (.D(n88), .CK(RCLK_c), .Q(FS[7])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972__i7.GSR = "ENABLED";
+    FD1S3AX FS_972__i6 (.D(n89), .CK(RCLK_c), .Q(FS[6])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972__i6.GSR = "ENABLED";
+    FD1S3AX wb_adr_i0 (.D(wb_adr_7__N_60[0]), .CK(RCLK_c), .Q(wb_adr[0]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_adr_i0.GSR = "ENABLED";
+    FD1S3AX FS_972__i5 (.D(n90), .CK(RCLK_c), .Q(FS[5])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972__i5.GSR = "ENABLED";
+    FD1S3AX FS_972__i4 (.D(n91), .CK(RCLK_c), .Q(FS[4])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972__i4.GSR = "ENABLED";
+    FD1S3AX FS_972__i3 (.D(n92), .CK(RCLK_c), .Q(FS[3])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972__i3.GSR = "ENABLED";
+    FD1S3AX FS_972__i2 (.D(n93), .CK(RCLK_c), .Q(FS[2])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972__i2.GSR = "ENABLED";
+    FD1S3AX FS_972__i1 (.D(n94), .CK(RCLK_c), .Q(FS[1])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972__i1.GSR = "ENABLED";
+    FD1P3AX wb_rst_551 (.D(n3671), .SP(RCLK_c_enable_22), .CK(RCLK_c), 
+            .Q(wb_rst));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_rst_551.GSR = "ENABLED";
+    FD1S3AX wb_dati_i0 (.D(wb_dati_7__N_68[0]), .CK(RCLK_c), .Q(wb_dati[0]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_dati_i0.GSR = "ENABLED";
+    FD1S3AX S_FSM_i1 (.D(n4921), .CK(RCLK_c), .Q(nRowColSel_N_35));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123[13:16])
+    defparam S_FSM_i1.GSR = "ENABLED";
+    FD1P3AX LEDEN_556 (.D(LEDEN_N_110), .SP(RCLK_c_enable_24), .CK(RCLK_c), 
+            .Q(LEDEN)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam LEDEN_556.GSR = "ENABLED";
+    FD1P3AX n8MEGEN_557 (.D(n8MEGEN_N_139), .SP(RCLK_c_enable_24), .CK(RCLK_c), 
+            .Q(n8MEGEN)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam n8MEGEN_557.GSR = "ENABLED";
+    FD1S3AX PHI2r_512 (.D(PHI2_c), .CK(RCLK_c), .Q(PHI2r));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(83[9] 87[5])
+    defparam PHI2r_512.GSR = "ENABLED";
+    FD1S3IX S_FSM_i4 (.D(n1286), .CK(RCLK_c), .CD(n4921), .Q(nRowColSel_N_32));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123[13:16])
+    defparam S_FSM_i4.GSR = "ENABLED";
+    IB RCLK_pad (.I(RCLK), .O(RCLK_c));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(40[8:12])
+    IB nFWE_pad (.I(nFWE), .O(nFWE_c));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(35[8:12])
+    IB nCRAS_pad (.I(nCRAS), .O(nCRAS_c));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(15[15:20])
+    IB nCCAS_pad (.I(nCCAS), .O(nCCAS_c));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(15[8:13])
+    IB Din_pad_0 (.I(Din[0]), .O(Din_c_0));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(25[14:17])
+    IB Din_pad_1 (.I(Din[1]), .O(Din_c_1));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(25[14:17])
+    IB Din_pad_2 (.I(Din[2]), .O(Din_c_2));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(25[14:17])
+    IB Din_pad_3 (.I(Din[3]), .O(Din_c_3));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(25[14:17])
+    IB Din_pad_4 (.I(Din[4]), .O(Din_c_4));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(25[14:17])
+    IB Din_pad_5 (.I(Din[5]), .O(Din_c_5));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(25[14:17])
+    IB Din_pad_6 (.I(Din[6]), .O(Din_c_6));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(25[14:17])
+    IB Din_pad_7 (.I(Din[7]), .O(Din_c_7));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(25[14:17])
+    IB CROW_pad_0 (.I(CROW[0]), .O(CROW_c_0));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(33[14:18])
+    IB CROW_pad_1 (.I(CROW[1]), .O(CROW_c_1));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(33[14:18])
+    IB MAin_pad_0 (.I(MAin[0]), .O(MAin_c_0));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(34[14:18])
+    IB MAin_pad_1 (.I(MAin[1]), .O(MAin_c_1));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(34[14:18])
+    IB MAin_pad_2 (.I(MAin[2]), .O(MAin_c_2));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(34[14:18])
+    IB MAin_pad_3 (.I(MAin[3]), .O(MAin_c_3));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(34[14:18])
+    IB MAin_pad_4 (.I(MAin[4]), .O(MAin_c_4));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(34[14:18])
+    IB MAin_pad_5 (.I(MAin[5]), .O(MAin_c_5));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(34[14:18])
+    IB MAin_pad_6 (.I(MAin[6]), .O(MAin_c_6));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(34[14:18])
+    IB MAin_pad_7 (.I(MAin[7]), .O(MAin_c_7));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(34[14:18])
+    IB MAin_pad_8 (.I(MAin[8]), .O(MAin_c_8));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(34[14:18])
+    IB MAin_pad_9 (.I(MAin[9]), .O(MAin_c_9));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(34[14:18])
+    IB PHI2_pad (.I(PHI2), .O(PHI2_c));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(7[8:12])
+    OB RDQML_pad (.I(RDQML_c), .O(RDQML));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(55[9:14])
+    OB RDQMH_pad (.I(RDQMH_c), .O(RDQMH));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(55[16:21])
+    OB nRCAS_pad (.I(nRCAS_c), .O(nRCAS));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(45[34:39])
+    OB nRRAS_pad (.I(nRRAS_c), .O(nRRAS));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(45[23:28])
+    OB nRWE_pad (.I(nRWE_c), .O(nRWE));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(45[45:49])
+    OB RCKE_pad (.I(RCKE_c), .O(RCKE));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(44[13:17])
+    OB nRCS_pad (.I(nRCS_c), .O(nRCS));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(45[13:17])
+    OB RA_pad_0 (.I(RA_c_0), .O(RA[0]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(51[16:18])
+    OB RA_pad_1 (.I(RA_c_1), .O(RA[1]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(51[16:18])
+    OB RA_pad_2 (.I(RA_c_2), .O(RA[2]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(51[16:18])
+    OB RA_pad_3 (.I(RA_c_3), .O(RA[3]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(51[16:18])
+    OB RA_pad_4 (.I(RA_c_4), .O(RA[4]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(51[16:18])
+    OB RA_pad_5 (.I(RA_c_5), .O(RA[5]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(51[16:18])
+    OB RA_pad_6 (.I(RA_c_6), .O(RA[6]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(51[16:18])
+    OB RA_pad_7 (.I(RA_c_7), .O(RA[7]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(51[16:18])
+    OB RA_pad_8 (.I(RA_c_8), .O(RA[8]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(51[16:18])
+    OB RA_pad_9 (.I(RA_c_9), .O(RA[9]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(51[16:18])
+    OB RA_pad_10 (.I(n1975), .O(RA[10]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(51[16:18])
+    OB RA_pad_11 (.I(RA_c), .O(RA[11]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(51[16:18])
+    OB RBA_pad_0 (.I(RBA_c_0), .O(RBA[0]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(46[19:22])
+    OB RBA_pad_1 (.I(RBA_c_1), .O(RBA[1]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(46[19:22])
+    OB LED_pad (.I(LED_N_134), .O(LED));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(11[9:12])
+    OB Dout_pad_0 (.I(Dout_c), .O(Dout[0]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(26[15:19])
+    OB Dout_pad_1 (.I(n1974), .O(Dout[1]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(26[15:19])
+    OB Dout_pad_2 (.I(n1973), .O(Dout[2]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(26[15:19])
+    OB Dout_pad_3 (.I(n1972), .O(Dout[3]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(26[15:19])
+    OB Dout_pad_4 (.I(n1971), .O(Dout[4]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(26[15:19])
+    OB Dout_pad_5 (.I(n1970), .O(Dout[5]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(26[15:19])
+    OB Dout_pad_6 (.I(n1969), .O(Dout[6]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(26[15:19])
+    OB Dout_pad_7 (.I(n1968), .O(Dout[7]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(26[15:19])
+    BB Dout_pad_0__1130 (.I(WRD[0]), .T(n1965), .B(RD[0]), .O(Dout_c));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(59[14:16])
+    BB Dout_pad_1__1129 (.I(WRD[1]), .T(n1965), .B(RD[1]), .O(n1974));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(59[14:16])
+    BB Dout_pad_2__1128 (.I(WRD[2]), .T(n1965), .B(RD[2]), .O(n1973));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(59[14:16])
+    BB Dout_pad_3__1127 (.I(WRD[3]), .T(n1965), .B(RD[3]), .O(n1972));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(59[14:16])
+    BB Dout_pad_4__1126 (.I(WRD[4]), .T(n1965), .B(RD[4]), .O(n1971));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(59[14:16])
+    BB Dout_pad_5__1125 (.I(WRD[5]), .T(n1965), .B(RD[5]), .O(n1970));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(59[14:16])
+    BB Dout_pad_6__1124 (.I(WRD[6]), .T(n1965), .B(RD[6]), .O(n1969));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(59[14:16])
+    FD1S3AX wb_dati_i7 (.D(wb_dati_7__N_68[7]), .CK(RCLK_c), .Q(wb_dati[7]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_dati_i7.GSR = "ENABLED";
+    FD1S3AX wb_dati_i6 (.D(wb_dati_7__N_68[6]), .CK(RCLK_c), .Q(wb_dati[6]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_dati_i6.GSR = "ENABLED";
+    FD1S3AX wb_dati_i5 (.D(wb_dati_7__N_68[5]), .CK(RCLK_c), .Q(wb_dati[5]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_dati_i5.GSR = "ENABLED";
+    FD1S3AX wb_dati_i4 (.D(wb_dati_7__N_68[4]), .CK(RCLK_c), .Q(wb_dati[4]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_dati_i4.GSR = "ENABLED";
+    FD1S3AX wb_dati_i3 (.D(wb_dati_7__N_68[3]), .CK(RCLK_c), .Q(wb_dati[3]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_dati_i3.GSR = "ENABLED";
+    FD1S3AX wb_dati_i2 (.D(wb_dati_7__N_68[2]), .CK(RCLK_c), .Q(wb_dati[2]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_dati_i2.GSR = "ENABLED";
+    FD1S3AX wb_dati_i1 (.D(wb_dati_7__N_68[1]), .CK(RCLK_c), .Q(wb_dati[1]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_dati_i1.GSR = "ENABLED";
+    CCU2D FS_972_add_4_3 (.A0(FS[1]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
+          .A1(FS[2]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n4086), 
+          .COUT(n4087), .S0(n94), .S1(n93));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972_add_4_3.INIT0 = 16'hfaaa;
+    defparam FS_972_add_4_3.INIT1 = 16'hfaaa;
+    defparam FS_972_add_4_3.INJECT1_0 = "NO";
+    defparam FS_972_add_4_3.INJECT1_1 = "NO";
+    PFUMX i1369 (.BLUT(wb_we_N_351), .ALUT(n2104), .C0(n4886), .Z(n2238));
+    FD1P3IX wb_cyc_stb_552 (.D(wb_cyc_stb_N_307), .SP(RCLK_c_enable_25), 
+            .CD(wb_adr_7__N_92), .CK(RCLK_c), .Q(wb_cyc_stb));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_cyc_stb_552.GSR = "ENABLED";
+    FD1S3AX wb_adr_i7 (.D(wb_adr_7__N_60[7]), .CK(RCLK_c), .Q(wb_adr[7]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_adr_i7.GSR = "ENABLED";
+    FD1S3AX wb_adr_i6 (.D(wb_adr_7__N_60[6]), .CK(RCLK_c), .Q(wb_adr[6]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_adr_i6.GSR = "ENABLED";
+    FD1S3AX wb_adr_i5 (.D(wb_adr_7__N_60[5]), .CK(RCLK_c), .Q(wb_adr[5]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_adr_i5.GSR = "ENABLED";
+    FD1S3AX wb_adr_i4 (.D(wb_adr_7__N_60[4]), .CK(RCLK_c), .Q(wb_adr[4]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_adr_i4.GSR = "ENABLED";
+    FD1S3AX wb_adr_i3 (.D(wb_adr_7__N_60[3]), .CK(RCLK_c), .Q(wb_adr[3]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_adr_i3.GSR = "ENABLED";
+    FD1S3AX wb_adr_i2 (.D(wb_adr_7__N_60[2]), .CK(RCLK_c), .Q(wb_adr[2]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_adr_i2.GSR = "ENABLED";
+    FD1S3AX wb_adr_i1 (.D(wb_adr_7__N_60[1]), .CK(RCLK_c), .Q(wb_adr[1]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_adr_i1.GSR = "ENABLED";
+    FD1S3IX RBA__i2 (.D(CROW_c_1), .CK(nCRAS_N_9), .CD(n4935), .Q(RBA_c_1));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5])
+    defparam RBA__i2.GSR = "ENABLED";
+    CCU2D FS_972_add_4_17 (.A0(FS[15]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
+          .A1(FS[16]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n4093), 
+          .COUT(n4094), .S0(n80), .S1(n79));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972_add_4_17.INIT0 = 16'hfaaa;
+    defparam FS_972_add_4_17.INIT1 = 16'hfaaa;
+    defparam FS_972_add_4_17.INJECT1_0 = "NO";
+    defparam FS_972_add_4_17.INJECT1_1 = "NO";
+    CCU2D FS_972_add_4_15 (.A0(FS[13]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
+          .A1(FS[14]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n4092), 
+          .COUT(n4093), .S0(n82), .S1(n81));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972_add_4_15.INIT0 = 16'hfaaa;
+    defparam FS_972_add_4_15.INIT1 = 16'hfaaa;
+    defparam FS_972_add_4_15.INJECT1_0 = "NO";
+    defparam FS_972_add_4_15.INJECT1_1 = "NO";
+    FD1P3AX CmdEnable_541 (.D(CmdEnable_N_243), .SP(PHI2_N_151_enable_1), 
+            .CK(PHI2_N_151), .Q(CmdEnable)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(280[9] 315[5])
+    defparam CmdEnable_541.GSR = "ENABLED";
+    FD1P3AX InitReady_530 (.D(n5144), .SP(RCLK_c_enable_26), .CK(RCLK_c), 
+            .Q(InitReady)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(126[9] 130[5])
+    defparam InitReady_530.GSR = "ENABLED";
+    PFUMX i12_adj_1 (.BLUT(n3_adj_4), .ALUT(n755), .C0(InitReady), .Z(wb_dati_7__N_68[6]));
+    LUT4 i1_3_lut_4_lut_then_4_lut (.A(FS[5]), .B(FS[8]), .C(FS[6]), .D(FS[7]), 
+         .Z(n4941)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(78[13:15])
+    defparam i1_3_lut_4_lut_then_4_lut.init = 16'h8000;
+    LUT4 i1_3_lut_4_lut_else_4_lut (.A(FS[5]), .B(FS[8]), .C(FS[6]), .D(FS[7]), 
+         .Z(n4940)) /* synthesis lut_function=(!(A (B+(D))+!A (B+(C (D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(78[13:15])
+    defparam i1_3_lut_4_lut_else_4_lut.init = 16'h0133;
+    LUT4 i2692_2_lut (.A(RCKE_c), .B(RASr2), .Z(nRWE_N_215)) /* synthesis lut_function=((B)+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(160[14] 176[8])
+    defparam i2692_2_lut.init = 16'hdddd;
+    LUT4 i217_2_lut_rep_70 (.A(FS[9]), .B(FS[5]), .Z(n4919)) /* synthesis lut_function=(A+(B)) */ ;
+    defparam i217_2_lut_rep_70.init = 16'heeee;
+    LUT4 i1_2_lut (.A(n3989), .B(n3969), .Z(wb_dati_7__N_68[1])) /* synthesis lut_function=(A+(B)) */ ;
+    defparam i1_2_lut.init = 16'heeee;
+    LUT4 n4542_bdd_4_lut (.A(FS[10]), .B(FS[11]), .C(FS[7]), .D(n4924), 
+         .Z(n4806)) /* synthesis lut_function=(!((B ((D)+!C)+!B (C+(D)))+!A)) */ ;
+    defparam n4542_bdd_4_lut.init = 16'h0082;
+    LUT4 i1_2_lut_4_lut (.A(n4929), .B(XOR8MEG_N_149), .C(Din_c_4), .D(n4931), 
+         .Z(PHI2_N_151_enable_3)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ;
+    defparam i1_2_lut_4_lut.init = 16'h4000;
+    PFUMX i3861 (.BLUT(n4777), .ALUT(n761), .C0(InitReady), .Z(wb_dati_7__N_68[0]));
+    FD1S3AX Bank_i0 (.D(Din_c_0), .CK(PHI2_c), .Q(Bank[0]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(90[9] 94[5])
+    defparam Bank_i0.GSR = "ENABLED";
+    LUT4 i1_4_lut_4_lut (.A(CBR), .B(FWEr), .C(n4618), .D(nRowColSel_N_34), 
+         .Z(n20)) /* synthesis lut_function=(!(A+!(B (C+(D))+!B (D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(206[26:30])
+    defparam i1_4_lut_4_lut.init = 16'h5540;
+    LUT4 n10_bdd_4_lut_3959 (.A(n10_adj_2), .B(FS[10]), .C(FS[11]), .D(n14), 
+         .Z(n4517)) /* synthesis lut_function=(A+(B (D)+!B ((D)+!C))) */ ;
+    defparam n10_bdd_4_lut_3959.init = 16'hffab;
+    LUT4 i3141_4_lut_4_lut (.A(n4895), .B(n3609), .C(FS[10]), .D(FS[11]), 
+         .Z(n38)) /* synthesis lut_function=(!(A (B+(C+!(D)))+!A !(B (C)+!B (C+(D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam i3141_4_lut_4_lut.init = 16'h5350;
+    FD1S3AX WRD_i7 (.D(Din_c_7), .CK(nCCAS_N_3), .Q(WRD[7]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(115[9] 117[5])
+    defparam WRD_i7.GSR = "ENABLED";
+    FD1S3AX WRD_i6 (.D(Din_c_6), .CK(nCCAS_N_3), .Q(WRD[6]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(115[9] 117[5])
+    defparam WRD_i6.GSR = "ENABLED";
+    LUT4 i2_3_lut_rep_77 (.A(RASr2), .B(InitReady), .C(nRowColSel_N_35), 
+         .Z(n4926)) /* synthesis lut_function=(A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(225[8:20])
+    defparam i2_3_lut_rep_77.init = 16'h8080;
+    FD1S3AX WRD_i5 (.D(Din_c_5), .CK(nCCAS_N_3), .Q(WRD[5]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(115[9] 117[5])
+    defparam WRD_i5.GSR = "ENABLED";
+    CCU2D FS_972_add_4_13 (.A0(FS[11]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
+          .A1(FS[12]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n4091), 
+          .COUT(n4092), .S0(n84), .S1(n83));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972_add_4_13.INIT0 = 16'hfaaa;
+    defparam FS_972_add_4_13.INIT1 = 16'hfaaa;
+    defparam FS_972_add_4_13.INJECT1_0 = "NO";
+    defparam FS_972_add_4_13.INJECT1_1 = "NO";
+    FD1S3AX WRD_i4 (.D(Din_c_4), .CK(nCCAS_N_3), .Q(WRD[4]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(115[9] 117[5])
+    defparam WRD_i4.GSR = "ENABLED";
+    LUT4 i1_2_lut_rep_57_4_lut (.A(RASr2), .B(InitReady), .C(nRowColSel_N_35), 
+         .D(nRCS_N_172), .Z(n4906)) /* synthesis lut_function=((((D)+!C)+!B)+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(225[8:20])
+    defparam i1_2_lut_rep_57_4_lut.init = 16'hff7f;
+    FD1S3AX WRD_i3 (.D(Din_c_3), .CK(nCCAS_N_3), .Q(WRD[3]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(115[9] 117[5])
+    defparam WRD_i3.GSR = "ENABLED";
+    FD1S3AX WRD_i2 (.D(Din_c_2), .CK(nCCAS_N_3), .Q(WRD[2]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(115[9] 117[5])
+    defparam WRD_i2.GSR = "ENABLED";
+    FD1S3AX WRD_i1 (.D(Din_c_1), .CK(nCCAS_N_3), .Q(WRD[1]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(115[9] 117[5])
+    defparam WRD_i1.GSR = "ENABLED";
+    FD1S3JX RowA_i9 (.D(MAin_c_9), .CK(nCRAS_N_9), .PD(n4935), .Q(RowA[9]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5])
+    defparam RowA_i9.GSR = "ENABLED";
+    FD1S3IX RowA_i8 (.D(MAin_c_8), .CK(nCRAS_N_9), .CD(n4935), .Q(RowA[8]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5])
+    defparam RowA_i8.GSR = "ENABLED";
+    LUT4 n2426_bdd_4_lut (.A(n2426), .B(n4165), .C(FS[11]), .D(FS[10]), 
+         .Z(n5142)) /* synthesis lut_function=(A (B (D)+!B !(C+!(D)))+!A (B (C (D)))) */ ;
+    defparam n2426_bdd_4_lut.init = 16'hca00;
+    FD1S3IX RowA_i7 (.D(MAin_c_7), .CK(nCRAS_N_9), .CD(n4935), .Q(RowA[7]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5])
+    defparam RowA_i7.GSR = "ENABLED";
+    FD1S3IX RowA_i6 (.D(MAin_c_6), .CK(nCRAS_N_9), .CD(n4935), .Q(RowA[6]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5])
+    defparam RowA_i6.GSR = "ENABLED";
+    BB Dout_pad_7__1123 (.I(WRD[7]), .T(n1965), .B(RD[7]), .O(n1968));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(59[14:16])
+    FD1S3JX RowA_i5 (.D(MAin_c_5), .CK(nCRAS_N_9), .PD(n4935), .Q(RowA[5]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5])
+    defparam RowA_i5.GSR = "ENABLED";
+    FD1S3IX RowA_i4 (.D(MAin_c_4), .CK(nCRAS_N_9), .CD(n4935), .Q(RowA[4]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5])
+    defparam RowA_i4.GSR = "ENABLED";
+    FD1S3IX RowA_i3 (.D(MAin_c_3), .CK(nCRAS_N_9), .CD(n4935), .Q(RowA[3]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5])
+    defparam RowA_i3.GSR = "ENABLED";
+    FD1S3IX RowA_i2 (.D(MAin_c_2), .CK(nCRAS_N_9), .CD(n4935), .Q(RowA[2]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5])
+    defparam RowA_i2.GSR = "ENABLED";
+    LUT4 i3798_2_lut_4_lut (.A(RASr2), .B(InitReady), .C(nRowColSel_N_35), 
+         .D(Ready), .Z(RCLK_c_enable_27)) /* synthesis lut_function=(!((((D)+!C)+!B)+!A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(225[8:20])
+    defparam i3798_2_lut_4_lut.init = 16'h0080;
+    LUT4 i3_4_lut (.A(Din_c_6), .B(n4624), .C(Din_c_5), .D(n4548), .Z(C1Submitted_N_232)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ;
+    defparam i3_4_lut.init = 16'h0200;
+    FD1S3IX RowA_i1 (.D(MAin_c_1), .CK(nCRAS_N_9), .CD(n4935), .Q(RowA[1]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5])
+    defparam RowA_i1.GSR = "ENABLED";
+    GSR GSR_INST (.GSR(VCC_net));
+    FD1S3AX Bank_i7 (.D(Din_c_7), .CK(PHI2_c), .Q(Bank[7]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(90[9] 94[5])
+    defparam Bank_i7.GSR = "ENABLED";
+    LUT4 i1392_4_lut (.A(wb_we_N_354), .B(n2258), .C(n10_adj_2), .D(n4), 
+         .Z(n2262)) /* synthesis lut_function=(A (B+!(C+(D)))+!A (B (C+(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(525[4] 647[11])
+    defparam i1392_4_lut.init = 16'hccca;
+    LUT4 i1388_4_lut (.A(n4897), .B(n2238), .C(n10_adj_2), .D(n4891), 
+         .Z(n2258)) /* synthesis lut_function=(A (B+!(C+(D)))+!A (B (C+(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(525[4] 647[11])
+    defparam i1388_4_lut.init = 16'hccca;
+    CCU2D FS_972_add_4_11 (.A0(FS[9]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
+          .A1(FS[10]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n4090), 
+          .COUT(n4091), .S0(n86), .S1(n85));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972_add_4_11.INIT0 = 16'hfaaa;
+    defparam FS_972_add_4_11.INIT1 = 16'hfaaa;
+    defparam FS_972_add_4_11.INJECT1_0 = "NO";
+    defparam FS_972_add_4_11.INJECT1_1 = "NO";
+    LUT4 i1_2_lut_rep_35_3_lut_4_lut_4_lut (.A(n4920), .B(n4902), .C(n4899), 
+         .D(FS[10]), .Z(n4884)) /* synthesis lut_function=(A+(B (C)+!B !((D)+!C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(648[30:46])
+    defparam i1_2_lut_rep_35_3_lut_4_lut_4_lut.init = 16'heafa;
+    LUT4 i1_2_lut_rep_78 (.A(FS[7]), .B(FS[6]), .Z(n4927)) /* synthesis lut_function=(A+(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(78[13:15])
+    defparam i1_2_lut_rep_78.init = 16'heeee;
+    LUT4 i2_2_lut_rep_51_3_lut_4_lut (.A(FS[7]), .B(FS[6]), .C(FS[8]), 
+         .D(FS[9]), .Z(n4900)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(78[13:15])
+    defparam i2_2_lut_rep_51_3_lut_4_lut.init = 16'hfffe;
+    LUT4 i1_3_lut_4_lut (.A(FS[7]), .B(FS[6]), .C(FS[8]), .D(FS[5]), 
+         .Z(n53_adj_9)) /* synthesis lut_function=(A (C)+!A (B (C)+!B (C (D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(78[13:15])
+    defparam i1_3_lut_4_lut.init = 16'hf0e0;
+    LUT4 i1_2_lut_rep_79 (.A(FS[5]), .B(FS[9]), .Z(n4928)) /* synthesis lut_function=(!((B)+!A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam i1_2_lut_rep_79.init = 16'h2222;
+    LUT4 n34_bdd_2_lut_3877_3_lut (.A(FS[5]), .B(FS[9]), .C(n4806), .Z(n4807)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam n34_bdd_2_lut_3877_3_lut.init = 16'h2020;
+    LUT4 n61_bdd_4_lut_3912 (.A(n4923), .B(n12_adj_8), .C(n45), .D(FS[10]), 
+         .Z(n4850)) /* synthesis lut_function=(A (B+!((D)+!C))+!A (B)) */ ;
+    defparam n61_bdd_4_lut_3912.init = 16'hccec;
+    FD1S3AX Bank_i6 (.D(Din_c_6), .CK(PHI2_c), .Q(Bank[6]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(90[9] 94[5])
+    defparam Bank_i6.GSR = "ENABLED";
+    LUT4 i3122_3_lut_3_lut_4_lut (.A(n4927), .B(n4905), .C(n646), .D(FS[10]), 
+         .Z(n23)) /* synthesis lut_function=(!(A ((D)+!C)+!A (B ((D)+!C)+!B !(C+(D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam i3122_3_lut_3_lut_4_lut.init = 16'h11f0;
+    FD1S3AX Bank_i5 (.D(Din_c_5), .CK(PHI2_c), .Q(Bank[5]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(90[9] 94[5])
+    defparam Bank_i5.GSR = "ENABLED";
+    FD1S3AX Bank_i4 (.D(Din_c_4), .CK(PHI2_c), .Q(Bank[4]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(90[9] 94[5])
+    defparam Bank_i4.GSR = "ENABLED";
+    LUT4 i1_4_lut_4_lut_4_lut (.A(FS[10]), .B(n3_adj_16), .C(FS[11]), 
+         .D(n4895), .Z(n42_adj_5)) /* synthesis lut_function=(!(A+(B (C (D))+!B ((D)+!C)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i1_4_lut_4_lut_4_lut.init = 16'h0454;
+    LUT4 n1097_bdd_2_lut_3927 (.A(n4858), .B(FS[9]), .Z(n4859)) /* synthesis lut_function=(A+!(B)) */ ;
+    defparam n1097_bdd_2_lut_3927.init = 16'hbbbb;
+    FD1S3AX Bank_i3 (.D(Din_c_3), .CK(PHI2_c), .Q(Bank[3]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(90[9] 94[5])
+    defparam Bank_i3.GSR = "ENABLED";
+    FD1S3AX Bank_i2 (.D(Din_c_2), .CK(PHI2_c), .Q(Bank[2]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(90[9] 94[5])
+    defparam Bank_i2.GSR = "ENABLED";
+    FD1S3AX FS_972__i0 (.D(n95), .CK(RCLK_c), .Q(FS[0])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972__i0.GSR = "ENABLED";
+    LUT4 i7_4_lut_4_lut (.A(FS[4]), .B(n4517), .C(n10), .D(n14_adj_14), 
+         .Z(n4539)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(692[20:26])
+    defparam i7_4_lut_4_lut.init = 16'h4000;
+    LUT4 FS_5__bdd_4_lut_3949 (.A(FS[5]), .B(FS[8]), .C(FS[6]), .D(FS[7]), 
+         .Z(n4858)) /* synthesis lut_function=(A (B (C (D))+!B !(D))+!A !(B+(C (D)))) */ ;
+    defparam FS_5__bdd_4_lut_3949.init = 16'h8133;
+    FD1S3AX Bank_i1 (.D(Din_c_1), .CK(PHI2_c), .Q(Bank[1]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(90[9] 94[5])
+    defparam Bank_i1.GSR = "ENABLED";
+    LUT4 n9_bdd_2_lut_3908_4_lut (.A(n4910), .B(n4919), .C(FS[10]), .D(FS[12]), 
+         .Z(n4775)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam n9_bdd_2_lut_3908_4_lut.init = 16'h0200;
+    FD1P3AX CmdUFMData_548 (.D(Din_c_0), .SP(PHI2_N_151_enable_3), .CK(PHI2_N_151), 
+            .Q(CmdUFMData)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(280[9] 315[5])
+    defparam CmdUFMData_548.GSR = "ENABLED";
+    LUT4 i3106_3_lut_3_lut (.A(FS[12]), .B(FS[11]), .C(n53), .Z(n1_adj_6)) /* synthesis lut_function=(!(A (B+!(C))+!A !(C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(684[30:46])
+    defparam i3106_3_lut_3_lut.init = 16'h7070;
+    LUT4 nRCAS_I_0_594_3_lut_4_lut (.A(nRCAS_N_198), .B(n4906), .C(Ready), 
+         .D(nRCAS_N_199), .Z(nRCAS_N_194)) /* synthesis lut_function=(A ((D)+!C)+!A (B ((D)+!C)+!B (C (D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(267[12] 276[6])
+    defparam nRCAS_I_0_594_3_lut_4_lut.init = 16'hfe0e;
+    LUT4 i5_4_lut_4_lut (.A(FS[12]), .B(n4895), .C(n4519), .D(n2308), 
+         .Z(n12_adj_10)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(684[30:46])
+    defparam i5_4_lut_4_lut.init = 16'h4000;
+    LUT4 Din_7__I_0_i6_2_lut_rep_80 (.A(Din_c_6), .B(Din_c_7), .Z(n4929)) /* synthesis lut_function=(A+(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(304[17:31])
+    defparam Din_7__I_0_i6_2_lut_rep_80.init = 16'heeee;
+    LUT4 i1_4_lut_4_lut_adj_2 (.A(n4907), .B(FS[12]), .C(n42), .D(n4807), 
+         .Z(n3_adj_4)) /* synthesis lut_function=(!(A+!(B (C)+!B (D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i1_4_lut_4_lut_adj_2.init = 16'h5140;
+    LUT4 FS_7__bdd_4_lut_3948 (.A(FS[7]), .B(FS[9]), .C(FS[8]), .D(n4939), 
+         .Z(n638)) /* synthesis lut_function=(!(A (B (C+(D)))+!A (B (C)+!B !(C+(D))))) */ ;
+    defparam FS_7__bdd_4_lut_3948.init = 16'h373e;
+    PFUMX i29 (.BLUT(n56), .ALUT(n1_adj_6), .C0(n4632), .Z(n14_adj_3));
+    LUT4 i2_3_lut_rep_33_4_lut (.A(Din_c_6), .B(Din_c_7), .C(Din_c_4), 
+         .D(XOR8MEG_N_149), .Z(n4882)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(304[17:31])
+    defparam i2_3_lut_rep_33_4_lut.init = 16'h1000;
+    LUT4 i1_2_lut_rep_59_3_lut (.A(Din_c_6), .B(Din_c_7), .C(Din_c_5), 
+         .Z(n4908)) /* synthesis lut_function=(A+(B+(C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(304[17:31])
+    defparam i1_2_lut_rep_59_3_lut.init = 16'hfefe;
+    LUT4 i21_3_lut_4_lut_4_lut (.A(n4907), .B(n759), .C(InitReady), .D(n4880), 
+         .Z(wb_dati_7__N_68[2])) /* synthesis lut_function=(A (B (C))+!A (B (C+(D))+!B !(C+!(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i21_3_lut_4_lut_4_lut.init = 16'hc5c0;
+    PFUMX i13 (.BLUT(n4539), .ALUT(n4513), .C0(InitReady), .Z(RCLK_c_enable_24));
+    LUT4 i1_4_lut_4_lut_adj_3 (.A(n4907), .B(n4900), .C(n4890), .D(FS[5]), 
+         .Z(n45)) /* synthesis lut_function=(!(A+(B (C)+!B !((D)+!C)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i1_4_lut_4_lut_adj_3.init = 16'h1505;
+    LUT4 FS_6__bdd_4_lut_3962 (.A(FS[6]), .B(FS[5]), .C(FS[8]), .D(FS[7]), 
+         .Z(n4869)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(C+(D)))+!A !(B (C+(D))+!B (C)))) */ ;
+    defparam FS_6__bdd_4_lut_3962.init = 16'h7ef0;
+    LUT4 i3707_2_lut_rep_81 (.A(MAin_c_3), .B(MAin_c_6), .Z(n4930)) /* synthesis lut_function=(A (B)) */ ;
+    defparam i3707_2_lut_rep_81.init = 16'h8888;
+    LUT4 i1_2_lut_rep_82 (.A(Din_c_3), .B(Din_c_5), .Z(n4931)) /* synthesis lut_function=(A (B)) */ ;
+    defparam i1_2_lut_rep_82.init = 16'h8888;
+    PFUMX i3859 (.BLUT(n4775), .ALUT(n4774), .C0(FS[11]), .Z(n4776));
+    LUT4 i21_3_lut_4_lut_4_lut_adj_4 (.A(n4907), .B(n756), .C(InitReady), 
+         .D(n4880), .Z(wb_dati_7__N_68[5])) /* synthesis lut_function=(A (B (C))+!A (B (C+(D))+!B !(C+!(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i21_3_lut_4_lut_4_lut_adj_4.init = 16'hc5c0;
+    LUT4 i1_4_lut_4_lut_adj_5 (.A(n4907), .B(FS[12]), .C(n42), .D(n39), 
+         .Z(n3)) /* synthesis lut_function=(!(A+!(B (C)+!B (D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i1_4_lut_4_lut_adj_5.init = 16'h5140;
+    FD1P3AX CmdUFMShift_547 (.D(Din_c_1), .SP(PHI2_N_151_enable_3), .CK(PHI2_N_151), 
+            .Q(CmdUFMShift)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(280[9] 315[5])
+    defparam CmdUFMShift_547.GSR = "ENABLED";
+    FD1P3AX Cmdn8MEGEN_546 (.D(Cmdn8MEGEN_N_260), .SP(PHI2_N_151_enable_5), 
+            .CK(PHI2_N_151), .Q(Cmdn8MEGEN)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(280[9] 315[5])
+    defparam Cmdn8MEGEN_546.GSR = "ENABLED";
+    FD1P3AX CmdLEDEN_545 (.D(CmdLEDEN_N_251), .SP(PHI2_N_151_enable_5), 
+            .CK(PHI2_N_151), .Q(CmdLEDEN)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(280[9] 315[5])
+    defparam CmdLEDEN_545.GSR = "ENABLED";
+    LUT4 i1_2_lut_4_lut_4_lut (.A(n4907), .B(FS[12]), .C(n42_adj_5), .D(n38), 
+         .Z(n3_adj_1)) /* synthesis lut_function=(!(A+!(B (C)+!B (D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i1_2_lut_4_lut_4_lut.init = 16'h5140;
+    FD1P3AX Ready_540 (.D(n5144), .SP(Ready_N_280), .CK(RCLK_c), .Q(Ready)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(139[9] 277[5])
+    defparam Ready_540.GSR = "ENABLED";
+    FD1P3AX XOR8MEG_544 (.D(Din_c_0), .SP(PHI2_N_151_enable_6), .CK(PHI2_N_151), 
+            .Q(XOR8MEG)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(280[9] 315[5])
+    defparam XOR8MEG_544.GSR = "ENABLED";
+    LUT4 i3748_4_lut (.A(Din_c_3), .B(MAin_c_0), .C(Din_c_2), .D(n4888), 
+         .Z(n4624)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
+    defparam i3748_4_lut.init = 16'hfffe;
+    FD1S3IX RA11_521 (.D(RA11_N_217), .CK(PHI2_c), .CD(n4935), .Q(RA_c));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(90[9] 94[5])
+    defparam RA11_521.GSR = "ENABLED";
+    FD1P3AX IS_FSM__i0 (.D(Ready_N_284), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
+            .Q(nRCS_N_172));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15])
+    defparam IS_FSM__i0.GSR = "ENABLED";
+    FD1P3AX wb_clk_550 (.D(n1889), .SP(RCLK_c_enable_28), .CK(RCLK_c), 
+            .Q(wb_clk));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5])
+    defparam wb_clk_550.GSR = "ENABLED";
+    LUT4 i1_4_lut_4_lut_adj_6 (.A(n4907), .B(FS[11]), .C(n3711), .D(n175), 
+         .Z(n17)) /* synthesis lut_function=(!(A+(B (C)+!B !(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i1_4_lut_4_lut_adj_6.init = 16'h1504;
+    FD1P3AX nRowColSel_538 (.D(n1885), .SP(RCLK_c_enable_29), .CK(RCLK_c), 
+            .Q(nRowColSel));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(139[9] 277[5])
+    defparam nRowColSel_538.GSR = "ENABLED";
+    LUT4 i2_3_lut_rep_62_4_lut (.A(Din_c_3), .B(Din_c_5), .C(Din_c_2), 
+         .D(Din_c_6), .Z(n4911)) /* synthesis lut_function=(!((((D)+!C)+!B)+!A)) */ ;
+    defparam i2_3_lut_rep_62_4_lut.init = 16'h0080;
+    LUT4 i2_1_lut_rep_83 (.A(nFWE_c), .Z(n4932)) /* synthesis lut_function=(!(A)) */ ;
+    defparam i2_1_lut_rep_83.init = 16'h5555;
+    LUT4 i1_2_lut_2_lut (.A(nFWE_c), .B(n4504), .Z(n4548)) /* synthesis lut_function=(!(A+!(B))) */ ;
+    defparam i1_2_lut_2_lut.init = 16'h4444;
+    LUT4 i1684_1_lut_rep_84 (.A(nRowColSel_N_35), .Z(n4933)) /* synthesis lut_function=(!(A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123[13:16])
+    defparam i1684_1_lut_rep_84.init = 16'h5555;
+    LUT4 i2736_4_lut (.A(wb_adr[7]), .B(InitReady), .C(wb_adr[6]), .D(n4901), 
+         .Z(wb_adr_7__N_60[7])) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C (D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[12] 729[6])
+    defparam i2736_4_lut.init = 16'hc088;
+    LUT4 i29_3_lut (.A(n14_adj_7), .B(n746), .C(InitReady), .Z(wb_adr_7__N_60[6])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i29_3_lut.init = 16'hcaca;
+    LUT4 i3_4_lut_4_lut (.A(nRowColSel_N_35), .B(RASr2), .C(InitReady), 
+         .D(nRCS_N_172), .Z(nRCS_N_170)) /* synthesis lut_function=((((D)+!C)+!B)+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123[13:16])
+    defparam i3_4_lut_4_lut.init = 16'hff7f;
+    LUT4 i2787_2_lut_rep_85 (.A(FS[10]), .B(FS[11]), .Z(n4934)) /* synthesis lut_function=(A (B)) */ ;
+    defparam i2787_2_lut_rep_85.init = 16'h8888;
+    LUT4 i2791_2_lut_rep_42_3_lut_4_lut_4_lut_2_lut (.A(FS[11]), .B(n14), 
+         .Z(n4891)) /* synthesis lut_function=((B)+!A) */ ;
+    defparam i2791_2_lut_rep_42_3_lut_4_lut_4_lut_2_lut.init = 16'hdddd;
+    LUT4 i3_4_lut_4_lut_adj_7 (.A(n4907), .B(n4904), .C(InitReady), .D(n4895), 
+         .Z(n3969)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i3_4_lut_4_lut_adj_7.init = 16'h0004;
+    FD1P3IX ADSubmitted_543 (.D(n4883), .SP(PHI2_N_151_enable_7), .CD(C1Submitted_N_232), 
+            .CK(PHI2_N_151), .Q(ADSubmitted)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(280[9] 315[5])
+    defparam ADSubmitted_543.GSR = "ENABLED";
+    LUT4 CmdLEDEN_I_69_3_lut_4_lut (.A(Din_c_4), .B(n4908), .C(Din_c_1), 
+         .D(LEDEN), .Z(CmdLEDEN_N_251)) /* synthesis lut_function=(A (B (D)+!B !(C))+!A (D)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(304[17:31])
+    defparam CmdLEDEN_I_69_3_lut_4_lut.init = 16'hdf02;
+    LUT4 Cmdn8MEGEN_I_72_3_lut_4_lut (.A(Din_c_4), .B(n4908), .C(Din_c_0), 
+         .D(n8MEGEN), .Z(Cmdn8MEGEN_N_260)) /* synthesis lut_function=(A (B (D)+!B !(C))+!A (D)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(304[17:31])
+    defparam Cmdn8MEGEN_I_72_3_lut_4_lut.init = 16'hdf02;
+    CCU2D FS_972_add_4_9 (.A0(FS[7]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
+          .A1(FS[8]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n4089), 
+          .COUT(n4090), .S0(n88), .S1(n87));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972_add_4_9.INIT0 = 16'hfaaa;
+    defparam FS_972_add_4_9.INIT1 = 16'hfaaa;
+    defparam FS_972_add_4_9.INJECT1_0 = "NO";
+    defparam FS_972_add_4_9.INJECT1_1 = "NO";
+    LUT4 i3804_2_lut_4_lut (.A(FS[11]), .B(n4909), .C(n10_adj_2), .D(FS[9]), 
+         .Z(n3671)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(522[30:46])
+    defparam i3804_2_lut_4_lut.init = 16'h0001;
+    LUT4 i1_2_lut_rep_53 (.A(FS[11]), .B(n14), .Z(n4902)) /* synthesis lut_function=(A+(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(648[30:46])
+    defparam i1_2_lut_rep_53.init = 16'heeee;
+    LUT4 i3808_2_lut_4_lut (.A(FS[11]), .B(n4909), .C(n10_adj_2), .D(InitReady), 
+         .Z(wb_adr_7__N_92)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(522[30:46])
+    defparam i3808_2_lut_4_lut.init = 16'h0001;
+    LUT4 i1_2_lut_rep_64_3_lut (.A(FS[10]), .B(FS[11]), .C(n14), .Z(n4913)) /* synthesis lut_function=(((C)+!B)+!A) */ ;
+    defparam i1_2_lut_rep_64_3_lut.init = 16'hf7f7;
+    LUT4 mux_427_i5_3_lut_4_lut (.A(n4917), .B(CmdUFMShift), .C(wb_adr[3]), 
+         .D(wb_adr[4]), .Z(n748)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47])
+    defparam mux_427_i5_3_lut_4_lut.init = 16'hf780;
+    LUT4 i1044_1_lut_rep_86 (.A(Ready), .Z(n4935)) /* synthesis lut_function=(!(A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(139[9] 277[5])
+    defparam i1044_1_lut_rep_86.init = 16'h5555;
+    LUT4 n4729_bdd_2_lut_3976 (.A(n4729), .B(FS[11]), .Z(n4730)) /* synthesis lut_function=(!((B)+!A)) */ ;
+    defparam n4729_bdd_2_lut_3976.init = 16'h2222;
+    LUT4 i1_3_lut_rep_34_4_lut (.A(MAin_c_0), .B(n4888), .C(n4911), .D(n4548), 
+         .Z(n4883)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(72[15:31])
+    defparam i1_3_lut_rep_34_4_lut.init = 16'h2000;
+    LUT4 i1_2_lut_3_lut (.A(FS[11]), .B(n14), .C(FS[10]), .Z(n4)) /* synthesis lut_function=(A+(B+!(C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(648[30:46])
+    defparam i1_2_lut_3_lut.init = 16'hefef;
+    LUT4 n3572_bdd_4_lut_3847 (.A(n4890), .B(wb_cyc_stb_N_350), .C(n638), 
+         .D(FS[10]), .Z(n4729)) /* synthesis lut_function=(A (B (C+(D))+!B !((D)+!C))+!A !((D)+!C)) */ ;
+    defparam n3572_bdd_4_lut_3847.init = 16'h88f0;
+    LUT4 n4733_bdd_2_lut (.A(n4733), .B(n3969), .Z(wb_adr_7__N_60[0])) /* synthesis lut_function=(A+(B)) */ ;
+    defparam n4733_bdd_2_lut.init = 16'heeee;
+    LUT4 i28_3_lut (.A(n14_adj_7), .B(n748), .C(InitReady), .Z(wb_adr_7__N_60[4])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i28_3_lut.init = 16'hcaca;
+    LUT4 i1_2_lut_rep_44_3_lut_4_lut (.A(FS[11]), .B(n14), .C(FS[10]), 
+         .D(n4920), .Z(n4893)) /* synthesis lut_function=(A+(B+((D)+!C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(648[30:46])
+    defparam i1_2_lut_rep_44_3_lut_4_lut.init = 16'hffef;
+    LUT4 i1_2_lut_2_lut_adj_8 (.A(Ready), .B(nRowColSel_N_34), .Z(n6)) /* synthesis lut_function=((B)+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(139[9] 277[5])
+    defparam i1_2_lut_2_lut_adj_8.init = 16'hdddd;
+    LUT4 i1_2_lut_rep_37_3_lut_4_lut (.A(FS[11]), .B(n14), .C(FS[10]), 
+         .D(n4920), .Z(n4886)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(648[30:46])
+    defparam i1_2_lut_rep_37_3_lut_4_lut.init = 16'hfffe;
+    LUT4 i2_3_lut_4_lut_4_lut (.A(Ready), .B(n2040), .C(nRowColSel_N_32), 
+         .D(nRowColSel_N_35), .Z(RCLK_c_enable_29)) /* synthesis lut_function=((B+(C+(D)))+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(139[9] 277[5])
+    defparam i2_3_lut_4_lut_4_lut.init = 16'hfffd;
+    LUT4 i2742_4_lut (.A(wb_adr[3]), .B(InitReady), .C(wb_adr[2]), .D(n4901), 
+         .Z(wb_adr_7__N_60[3])) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C (D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[12] 729[6])
+    defparam i2742_4_lut.init = 16'hc088;
+    LUT4 i2_2_lut_4_lut (.A(FS[11]), .B(n4909), .C(n10_adj_2), .D(FS[9]), 
+         .Z(n10)) /* synthesis lut_function=(!(A (D)+!A (B (D)+!B ((D)+!C)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(522[30:46])
+    defparam i2_2_lut_4_lut.init = 16'h00fe;
+    LUT4 i2743_4_lut (.A(wb_adr[2]), .B(InitReady), .C(wb_adr[1]), .D(n4901), 
+         .Z(wb_adr_7__N_60[2])) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C (D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[12] 729[6])
+    defparam i2743_4_lut.init = 16'hc088;
+    CCU2D FS_972_add_4_7 (.A0(FS[5]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
+          .A1(FS[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n4088), 
+          .COUT(n4089), .S0(n90), .S1(n89));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972_add_4_7.INIT0 = 16'hfaaa;
+    defparam FS_972_add_4_7.INIT1 = 16'hfaaa;
+    defparam FS_972_add_4_7.INJECT1_0 = "NO";
+    defparam FS_972_add_4_7.INJECT1_1 = "NO";
+    LUT4 i2_3_lut_4_lut (.A(FS[7]), .B(n4919), .C(FS[8]), .D(FS[6]), 
+         .Z(n3_adj_16)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;
+    defparam i2_3_lut_4_lut.init = 16'h0100;
+    LUT4 nRCS_N_179_bdd_4_lut (.A(nRCS_N_179), .B(n2040), .C(nRWE_N_215), 
+         .D(nRowColSel_N_35), .Z(nRWE_N_211)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))+!A (C+!(D))) */ ;
+    defparam nRCS_N_179_bdd_4_lut.init = 16'hf0dd;
+    LUT4 i34_4_lut (.A(n7), .B(ADSubmitted), .C(C1Submitted_N_232), .D(n4889), 
+         .Z(PHI2_N_151_enable_1)) /* synthesis lut_function=(A (B (C))+!A (B (C+!(D))+!B !(C+(D)))) */ ;
+    defparam i34_4_lut.init = 16'hc0c5;
+    LUT4 FS_8__bdd_3_lut_4_lut (.A(FS[7]), .B(n4919), .C(FS[6]), .D(FS[8]), 
+         .Z(n4718)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;
+    defparam FS_8__bdd_3_lut_4_lut.init = 16'h0100;
+    LUT4 i13_4_lut (.A(MAin_c_0), .B(C1Submitted), .C(MAin_c_1), .D(n6_adj_11), 
+         .Z(n7)) /* synthesis lut_function=(!(A (B+!(C (D)))+!A (C))) */ ;
+    defparam i13_4_lut.init = 16'h2505;
+    LUT4 i2_2_lut_rep_54_2_lut (.A(Ready), .B(nRowColSel_N_35), .Z(n4903)) /* synthesis lut_function=((B)+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(139[9] 277[5])
+    defparam i2_2_lut_rep_54_2_lut.init = 16'hdddd;
+    LUT4 i1_2_lut_rep_87 (.A(FS[7]), .B(FS[5]), .Z(n4936)) /* synthesis lut_function=(A (B)) */ ;
+    defparam i1_2_lut_rep_87.init = 16'h8888;
+    LUT4 n34_bdd_2_lut_3867_3_lut_4_lut (.A(n4782), .B(n4930), .C(n4628), 
+         .D(n4582), .Z(PHI2_N_151_enable_7)) /* synthesis lut_function=(A (B (C (D)))) */ ;
+    defparam n34_bdd_2_lut_3867_3_lut_4_lut.init = 16'h8000;
+    LUT4 i1_3_lut_4_lut_adj_9 (.A(n4938), .B(n4914), .C(FS[9]), .D(n98), 
+         .Z(n2199)) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A (B+!(C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(78[13:15])
+    defparam i1_3_lut_4_lut_adj_9.init = 16'hc5cf;
+    LUT4 i3_4_lut_adj_10 (.A(FS[11]), .B(FS[12]), .C(n4907), .D(n23), 
+         .Z(n4125)) /* synthesis lut_function=(!(A+((C+!(D))+!B))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(78[13:15])
+    defparam i3_4_lut_adj_10.init = 16'h0400;
+    LUT4 i1_2_lut_rep_49_3_lut_4_lut (.A(FS[7]), .B(FS[5]), .C(FS[9]), 
+         .D(n4937), .Z(n4898)) /* synthesis lut_function=(A (B (C (D)))) */ ;
+    defparam i1_2_lut_rep_49_3_lut_4_lut.init = 16'h8000;
+    LUT4 i1_3_lut_4_lut_adj_11 (.A(FS[10]), .B(n4923), .C(n12_adj_8), 
+         .D(n45), .Z(n14_adj_7)) /* synthesis lut_function=(A (C)+!A (B (C+(D))+!B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i1_3_lut_4_lut_adj_11.init = 16'hf4f0;
+    LUT4 i1_2_lut_rep_88 (.A(FS[6]), .B(FS[8]), .Z(n4937)) /* synthesis lut_function=(A (B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam i1_2_lut_rep_88.init = 16'h8888;
+    LUT4 i1_2_lut_rep_65_3_lut_4_lut (.A(FS[6]), .B(FS[8]), .C(FS[5]), 
+         .D(FS[7]), .Z(n4914)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam i1_2_lut_rep_65_3_lut_4_lut.init = 16'h8000;
+    LUT4 i3_4_lut_adj_12 (.A(Din_c_1), .B(Din_c_0), .C(Din_c_7), .D(Din_c_4), 
+         .Z(n4504)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ;
+    defparam i3_4_lut_adj_12.init = 16'h0040;
+    LUT4 i1_2_lut_rep_89 (.A(FS[7]), .B(FS[8]), .Z(n4938)) /* synthesis lut_function=(A+(B)) */ ;
+    defparam i1_2_lut_rep_89.init = 16'heeee;
+    LUT4 i2_3_lut (.A(InitReady), .B(FS[12]), .C(n754), .Z(n4165)) /* synthesis lut_function=(A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[12] 729[6])
+    defparam i2_3_lut.init = 16'h8080;
+    LUT4 i1_2_lut_rep_45_3_lut_4_lut (.A(FS[7]), .B(FS[8]), .C(FS[9]), 
+         .D(n4939), .Z(n4894)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
+    defparam i1_2_lut_rep_45_3_lut_4_lut.init = 16'hfffe;
+    LUT4 n61_bdd_4_lut (.A(n4923), .B(n4895), .C(n4530), .D(FS[10]), 
+         .Z(n4880)) /* synthesis lut_function=(!(A ((D)+!C)+!A (B ((D)+!C)+!B !(C+(D))))) */ ;
+    defparam n61_bdd_4_lut.init = 16'h11f0;
+    LUT4 i1_2_lut_rep_90 (.A(FS[5]), .B(FS[6]), .Z(n4939)) /* synthesis lut_function=(A+(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(78[13:15])
+    defparam i1_2_lut_rep_90.init = 16'heeee;
+    LUT4 i2_2_lut_rep_66_3_lut_4_lut (.A(FS[5]), .B(FS[6]), .C(FS[8]), 
+         .D(FS[7]), .Z(n4915)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(78[13:15])
+    defparam i2_2_lut_rep_66_3_lut_4_lut.init = 16'hfffe;
+    LUT4 i13_4_lut_adj_13 (.A(n4582), .B(n4628), .C(n15), .D(n4930), 
+         .Z(n2384)) /* synthesis lut_function=(((C+!(D))+!B)+!A) */ ;
+    defparam i13_4_lut_adj_13.init = 16'hf7ff;
+    LUT4 i1_2_lut_adj_14 (.A(MAin_c_7), .B(Bank[2]), .Z(n15)) /* synthesis lut_function=((B)+!A) */ ;
+    defparam i1_2_lut_adj_14.init = 16'hdddd;
+    LUT4 i1_2_lut_rep_38_4_lut (.A(n53_adj_9), .B(n4914), .C(FS[9]), .D(FS[11]), 
+         .Z(n4887)) /* synthesis lut_function=(A (B (C (D)))+!A (B (D)+!B !(C+!(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(464[4] 521[11])
+    defparam i1_2_lut_rep_38_4_lut.init = 16'hc500;
+    LUT4 i2_2_lut_3_lut_4_lut (.A(nRCS_N_172), .B(n4926), .C(Ready), .D(nRCAS_N_198), 
+         .Z(n4129)) /* synthesis lut_function=(A+((C+(D))+!B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(267[12] 276[6])
+    defparam i2_2_lut_3_lut_4_lut.init = 16'hfffb;
+    LUT4 i1_3_lut_3_lut_4_lut (.A(FS[7]), .B(n4924), .C(n4914), .D(FS[9]), 
+         .Z(wb_cyc_stb_N_348)) /* synthesis lut_function=(A (C (D))+!A (B (C (D))+!B (C+!(D)))) */ ;
+    defparam i1_3_lut_3_lut_4_lut.init = 16'hf011;
+    LUT4 i1_2_lut_rep_58 (.A(n14), .B(FS[13]), .Z(n4907)) /* synthesis lut_function=(A+(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i1_2_lut_rep_58.init = 16'heeee;
+    LUT4 i1_2_lut_adj_15 (.A(RASr2), .B(nRowColSel_N_32), .Z(n2556)) /* synthesis lut_function=(!((B)+!A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(83[9] 87[5])
+    defparam i1_2_lut_adj_15.init = 16'h2222;
+    CCU2D FS_972_add_4_19 (.A0(FS[17]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
+          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n4094), 
+          .S0(n78));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972_add_4_19.INIT0 = 16'hfaaa;
+    defparam FS_972_add_4_19.INIT1 = 16'h0000;
+    defparam FS_972_add_4_19.INJECT1_0 = "NO";
+    defparam FS_972_add_4_19.INJECT1_1 = "NO";
+    LUT4 i3746_2_lut_3_lut (.A(n14), .B(FS[13]), .C(FS[10]), .Z(n4622)) /* synthesis lut_function=(A+(B+(C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i3746_2_lut_3_lut.init = 16'hfefe;
+    LUT4 i3709_2_lut (.A(Bank[3]), .B(MAin_c_5), .Z(n4582)) /* synthesis lut_function=(A (B)) */ ;
+    defparam i3709_2_lut.init = 16'h8888;
+    LUT4 i3711_4_lut (.A(n4890), .B(n4887), .C(n2199), .D(FS[10]), .Z(n4585)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i3711_4_lut.init = 16'ha088;
+    PFUMX i12_adj_16 (.BLUT(n4526), .ALUT(n751), .C0(InitReady), .Z(wb_adr_7__N_60[1]));
+    LUT4 i3751_4_lut (.A(Bank[1]), .B(n4610), .C(n4574), .D(Bank[0]), 
+         .Z(n4628)) /* synthesis lut_function=(A (B (C (D)))) */ ;
+    defparam i3751_4_lut.init = 16'h8000;
+    LUT4 i1_2_lut_2_lut_3_lut (.A(n14), .B(FS[13]), .C(n14_adj_3), .Z(n12_adj_8)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i1_2_lut_2_lut_3_lut.init = 16'h1010;
+    LUT4 i3734_4_lut (.A(MAin_c_4), .B(Bank[5]), .C(Bank[4]), .D(Bank[6]), 
+         .Z(n4610)) /* synthesis lut_function=(A (B (C (D)))) */ ;
+    defparam i3734_4_lut.init = 16'h8000;
+    PFUMX i1383 (.BLUT(n2244), .ALUT(n2252), .C0(n4634), .Z(wb_we_N_338));
+    LUT4 i2856_2_lut_3_lut_4_lut (.A(n14), .B(FS[13]), .C(n4915), .D(FS[9]), 
+         .Z(n2426)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i2856_2_lut_3_lut_4_lut.init = 16'h0001;
+    LUT4 i1669_3_lut_4_lut (.A(InitReady), .B(n4886), .C(wb_dato[0]), 
+         .D(Cmdn8MEGEN), .Z(n8MEGEN_N_139)) /* synthesis lut_function=(A (D)+!A (B (D)+!B (C))) */ ;
+    defparam i1669_3_lut_4_lut.init = 16'hfe10;
+    LUT4 i3701_2_lut (.A(Bank[7]), .B(MAin_c_2), .Z(n4574)) /* synthesis lut_function=(A (B)) */ ;
+    defparam i3701_2_lut.init = 16'h8888;
+    LUT4 n34_bdd_2_lut_3863_2_lut_3_lut (.A(n14), .B(FS[13]), .C(n4776), 
+         .Z(n4777)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam n34_bdd_2_lut_3863_2_lut_3_lut.init = 16'h1010;
+    LUT4 i1382_3_lut (.A(wb_we_N_354), .B(wb_cyc_stb), .C(InitReady), 
+         .Z(n2252)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(525[4] 647[11])
+    defparam i1382_3_lut.init = 16'hcaca;
+    PFUMX i12_adj_17 (.BLUT(n3_adj_1), .ALUT(n757), .C0(InitReady), .Z(wb_dati_7__N_68[4]));
+    LUT4 n34_bdd_2_lut_3841_2_lut_3_lut (.A(n14), .B(FS[13]), .C(n4731), 
+         .Z(n4732)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam n34_bdd_2_lut_3841_2_lut_3_lut.init = 16'h1010;
+    LUT4 i1375_4_lut (.A(n4897), .B(n2238), .C(n10_adj_2), .D(n4913), 
+         .Z(n2244)) /* synthesis lut_function=(A (B+!(C+(D)))+!A (B (C+(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(525[4] 647[11])
+    defparam i1375_4_lut.init = 16'hccca;
+    LUT4 i6_4_lut (.A(n4149), .B(n12_adj_10), .C(n4622), .D(n4164), 
+         .Z(n4526)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i6_4_lut.init = 16'h0800;
+    LUT4 mux_427_i1_3_lut_4_lut (.A(n4917), .B(CmdUFMShift), .C(wb_dati[7]), 
+         .D(wb_adr[0]), .Z(n752)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47])
+    defparam mux_427_i1_3_lut_4_lut.init = 16'hf780;
+    LUT4 i6_4_lut_adj_18 (.A(FS[13]), .B(n12), .C(FS[17]), .D(FS[14]), 
+         .Z(RCLK_c_enable_26)) /* synthesis lut_function=(A (B (C (D)))) */ ;
+    defparam i6_4_lut_adj_18.init = 16'h8000;
+    LUT4 i5_4_lut (.A(FS[12]), .B(FS[16]), .C(FS[15]), .D(n4934), .Z(n12)) /* synthesis lut_function=(A (B (C (D)))) */ ;
+    defparam i5_4_lut.init = 16'h8000;
+    LUT4 i2_3_lut_4_lut_adj_19 (.A(Din_c_5), .B(n4929), .C(XOR8MEG_N_149), 
+         .D(Din_c_4), .Z(PHI2_N_151_enable_6)) /* synthesis lut_function=(!(A+(B+((D)+!C)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(304[17:31])
+    defparam i2_3_lut_4_lut_adj_19.init = 16'h0010;
+    LUT4 i1_2_lut_rep_39 (.A(MAin_c_1), .B(n2384), .Z(n4888)) /* synthesis lut_function=((B)+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(72[15:31])
+    defparam i1_2_lut_rep_39.init = 16'hdddd;
+    PFUMX i3833 (.BLUT(n4732), .ALUT(n752), .C0(InitReady), .Z(n4733));
+    LUT4 i1683_1_lut (.A(nRowColSel_N_34), .Z(n2557)) /* synthesis lut_function=(!(A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123[13:16])
+    defparam i1683_1_lut.init = 16'h5555;
+    LUT4 i1_2_lut_rep_36_3_lut (.A(MAin_c_1), .B(n2384), .C(MAin_c_0), 
+         .Z(n4885)) /* synthesis lut_function=((B+!(C))+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(72[15:31])
+    defparam i1_2_lut_rep_36_3_lut.init = 16'hdfdf;
+    LUT4 i92_4_lut (.A(n4887), .B(n2199), .C(FS[10]), .D(n4890), .Z(n53)) /* synthesis lut_function=(A (B+!(C (D)))+!A (B (C)+!B !((D)+!C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i92_4_lut.init = 16'hcafa;
+    LUT4 i3812_2_lut (.A(FS[11]), .B(FS[12]), .Z(n4632)) /* synthesis lut_function=(A+!(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i3812_2_lut.init = 16'hbbbb;
+    LUT4 i6_4_lut_adj_20 (.A(FS[10]), .B(n4527), .C(n4924), .D(n4936), 
+         .Z(n14_adj_14)) /* synthesis lut_function=(!(A+((C+!(D))+!B))) */ ;
+    defparam i6_4_lut_adj_20.init = 16'h0400;
+    LUT4 i4_4_lut (.A(FS[1]), .B(n4902), .C(n4920), .D(n6_adj_12), .Z(n4527)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;
+    defparam i4_4_lut.init = 16'h0100;
+    PFUMX i3123 (.BLUT(n4125), .ALUT(n760), .C0(InitReady), .Z(n3989));
+    LUT4 i1_3_lut (.A(FS[0]), .B(FS[2]), .C(FS[3]), .Z(n6_adj_12)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;
+    defparam i1_3_lut.init = 16'h4040;
+    LUT4 i1_2_lut_rep_60 (.A(FS[10]), .B(n14), .Z(n4909)) /* synthesis lut_function=(A+(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(684[30:46])
+    defparam i1_2_lut_rep_60.init = 16'heeee;
+    LUT4 nRCS_N_170_I_0_4_lut (.A(nRCS_N_170), .B(n4918), .C(Ready), .D(nRowColSel_N_35), 
+         .Z(nRRAS_N_189)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B ((D)+!C)+!B !(C)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(224[12] 276[6])
+    defparam nRCS_N_170_I_0_4_lut.init = 16'h3afa;
+    LUT4 i1_3_lut_adj_21 (.A(n4882), .B(Din_c_5), .C(Din_c_3), .Z(PHI2_N_151_enable_5)) /* synthesis lut_function=(A ((C)+!B)) */ ;
+    defparam i1_3_lut_adj_21.init = 16'ha2a2;
+    LUT4 FS_17__I_0_579_i10_2_lut (.A(FS[12]), .B(FS[13]), .Z(n10_adj_2)) /* synthesis lut_function=(A+(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(461[30:46])
+    defparam FS_17__I_0_579_i10_2_lut.init = 16'heeee;
+    LUT4 i3_4_lut_adj_22 (.A(FS[15]), .B(FS[17]), .C(FS[16]), .D(FS[14]), 
+         .Z(n14)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
+    defparam i3_4_lut_adj_22.init = 16'hfffe;
+    LUT4 i1_2_lut_rep_50_3_lut (.A(FS[10]), .B(n14), .C(FS[11]), .Z(n4899)) /* synthesis lut_function=(A+(B+!(C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(684[30:46])
+    defparam i1_2_lut_rep_50_3_lut.init = 16'hefef;
+    LUT4 i1_2_lut_rep_43_3_lut_4_lut (.A(FS[10]), .B(n14), .C(n4920), 
+         .D(FS[11]), .Z(n4892)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(684[30:46])
+    defparam i1_2_lut_rep_43_3_lut_4_lut.init = 16'hfeff;
+    LUT4 i3_4_lut_adj_23 (.A(MAin_c_1), .B(MAin_c_0), .C(CmdEnable), .D(n4889), 
+         .Z(XOR8MEG_N_149)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ;
+    defparam i3_4_lut_adj_23.init = 16'h0040;
+    LUT4 i3712_2_lut_rep_40 (.A(nFWE_c), .B(n2384), .Z(n4889)) /* synthesis lut_function=(A+(B)) */ ;
+    defparam i3712_2_lut_rep_40.init = 16'heeee;
+    LUT4 nRCAS_I_46_4_lut (.A(nRCS_N_175), .B(CBR), .C(nRowColSel_N_35), 
+         .D(RASr2), .Z(nRCAS_N_199)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B ((D)+!C)+!B !(C)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(178[13] 223[7])
+    defparam nRCAS_I_46_4_lut.init = 16'h3afa;
+    LUT4 i66_4_lut (.A(FS[10]), .B(n3609), .C(FS[11]), .D(n2308), .Z(n39)) /* synthesis lut_function=(!(A (C+(D))+!A (B+!(C)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i66_4_lut.init = 16'h101a;
+    LUT4 i2_2_lut (.A(InitReady), .B(Ready_N_284), .Z(n6_adj_15)) /* synthesis lut_function=(A (B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(83[9] 87[5])
+    defparam i2_2_lut.init = 16'h8888;
+    LUT4 i2_2_lut_4_lut_adj_24 (.A(n4931), .B(Din_c_6), .C(Din_c_2), .D(n4504), 
+         .Z(n6_adj_11)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ;
+    defparam i2_2_lut_4_lut_adj_24.init = 16'h2000;
+    LUT4 FS_17__I_0_572_i10_2_lut_rep_71 (.A(FS[12]), .B(FS[13]), .Z(n4920)) /* synthesis lut_function=((B)+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(684[30:46])
+    defparam FS_17__I_0_572_i10_2_lut_rep_71.init = 16'hdddd;
+    LUT4 i1676_3_lut_4_lut (.A(nFWE_c), .B(n2384), .C(MAin_c_1), .D(C1Submitted), 
+         .Z(n2549)) /* synthesis lut_function=(A (D)+!A (B (D)+!B !(C+!(D)))) */ ;
+    defparam i1676_3_lut_4_lut.init = 16'hef00;
+    LUT4 RA11_I_57_3_lut (.A(Din_c_6), .B(XOR8MEG), .C(n8MEGEN), .Z(RA11_N_217)) /* synthesis lut_function=(A (B (C)+!B !(C))+!A (B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(91[22:51])
+    defparam RA11_I_57_3_lut.init = 16'hc6c6;
+    LUT4 i2387_3_lut_4_lut (.A(FS[5]), .B(n4924), .C(FS[11]), .D(n53_adj_9), 
+         .Z(n98)) /* synthesis lut_function=(A ((D)+!C)+!A (B ((D)+!C)+!B (C (D)))) */ ;
+    defparam i2387_3_lut_4_lut.init = 16'hfe0e;
+    LUT4 i1_4_lut (.A(FS[2]), .B(n4884), .C(n4886), .D(n4517), .Z(n1)) /* synthesis lut_function=(!((B (C (D)))+!A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam i1_4_lut.init = 16'h2aaa;
+    LUT4 i2506_4_lut (.A(RASr), .B(RCKEEN), .C(RASr2), .D(RASr3), .Z(RCKE_N_165)) /* synthesis lut_function=(A (B+!(C+!(D)))+!A (B (C+(D))+!B !(C+!(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(19[12:17])
+    defparam i2506_4_lut.init = 16'hcfc8;
+    LUT4 i2801_4_lut (.A(FWEr), .B(n4903), .C(n2040), .D(n4_adj_13), 
+         .Z(n1885)) /* synthesis lut_function=(!(A (B+!(C+!(D)))+!A (B+!(C)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(139[9] 277[5])
+    defparam i2801_4_lut.init = 16'h3032;
+    LUT4 i1_2_lut_adj_25 (.A(CASr3), .B(CBR), .Z(n4_adj_13)) /* synthesis lut_function=(A+(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(222[16:37])
+    defparam i1_2_lut_adj_25.init = 16'heeee;
+    LUT4 i2_2_lut_3_lut_4_lut_adj_26 (.A(n4898), .B(n4894), .C(n4897), 
+         .D(FS[11]), .Z(n4519)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ;
+    defparam i2_2_lut_3_lut_4_lut_adj_26.init = 16'h4000;
+    LUT4 n9_bdd_4_lut_3892 (.A(n4895), .B(n4718), .C(FS[10]), .D(FS[12]), 
+         .Z(n4774)) /* synthesis lut_function=(!(A (((D)+!C)+!B)+!A (B (C (D)+!C !(D))+!B (C+!(D))))) */ ;
+    defparam n9_bdd_4_lut_3892.init = 16'h05c0;
+    LUT4 i1_4_lut_adj_27 (.A(FS[10]), .B(n646), .C(n4895), .D(FS[11]), 
+         .Z(n42)) /* synthesis lut_function=(!(A+(B (C (D))+!B (C+!(D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i1_4_lut_adj_27.init = 16'h0544;
+    LUT4 MAin_9__I_0_565_i3_3_lut (.A(RowA[2]), .B(MAin_c_2), .C(nRowColSel), 
+         .Z(RA_c_2)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(54[19:54])
+    defparam MAin_9__I_0_565_i3_3_lut.init = 16'hcaca;
+    LUT4 MAin_9__I_0_565_i4_3_lut (.A(RowA[3]), .B(MAin_c_3), .C(nRowColSel), 
+         .Z(RA_c_3)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(54[19:54])
+    defparam MAin_9__I_0_565_i4_3_lut.init = 16'hcaca;
+    LUT4 MAin_9__I_0_565_i5_3_lut (.A(RowA[4]), .B(MAin_c_4), .C(nRowColSel), 
+         .Z(RA_c_4)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(54[19:54])
+    defparam MAin_9__I_0_565_i5_3_lut.init = 16'hcaca;
+    LUT4 i2319_3_lut_rep_47_4_lut (.A(n4937), .B(n4936), .C(FS[9]), .D(n4938), 
+         .Z(n4896)) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A !(C+(D))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam i2319_3_lut_rep_47_4_lut.init = 16'h808f;
+    LUT4 i24_3_lut_rep_48_4_lut (.A(n4937), .B(n4936), .C(FS[9]), .D(n53_adj_9), 
+         .Z(n4897)) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A !(C+(D))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam i24_3_lut_rep_48_4_lut.init = 16'h808f;
+    LUT4 i1_3_lut_4_lut_adj_28 (.A(n4927), .B(n4925), .C(FS[10]), .D(FS[12]), 
+         .Z(n175)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;
+    defparam i1_3_lut_4_lut_adj_28.init = 16'h0100;
+    LUT4 i1_3_lut_3_lut_4_lut_adj_29 (.A(n4937), .B(n4936), .C(n4938), 
+         .D(FS[9]), .Z(wb_cyc_stb_N_350)) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C+(D)))+!A !(C+(D))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam i1_3_lut_3_lut_4_lut_adj_29.init = 16'h880f;
+    LUT4 i2708_2_lut_rep_41_3_lut_3_lut_4_lut (.A(n4937), .B(n4936), .C(n4915), 
+         .D(FS[9]), .Z(n4890)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B !(C+(D)))+!A !(C+(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam i2708_2_lut_rep_41_3_lut_3_lut_4_lut.init = 16'h77f0;
+    LUT4 MAin_9__I_0_565_i6_3_lut (.A(RowA[5]), .B(MAin_c_5), .C(nRowColSel), 
+         .Z(RA_c_5)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(54[19:54])
+    defparam MAin_9__I_0_565_i6_3_lut.init = 16'hcaca;
+    LUT4 MAin_9__I_0_565_i7_3_lut (.A(RowA[6]), .B(MAin_c_6), .C(nRowColSel), 
+         .Z(RA_c_6)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(54[19:54])
+    defparam MAin_9__I_0_565_i7_3_lut.init = 16'hcaca;
+    PFUMX i3831 (.BLUT(n4585), .ALUT(n4730), .C0(FS[12]), .Z(n4731));
+    LUT4 MAin_9__I_0_565_i8_3_lut (.A(RowA[7]), .B(MAin_c_7), .C(nRowColSel), 
+         .Z(RA_c_7)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(54[19:54])
+    defparam MAin_9__I_0_565_i8_3_lut.init = 16'hcaca;
+    CCU2D FS_972_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
+          .A1(FS[0]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .COUT(n4086), 
+          .S1(n95));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972_add_4_1.INIT0 = 16'hF000;
+    defparam FS_972_add_4_1.INIT1 = 16'h0555;
+    defparam FS_972_add_4_1.INJECT1_0 = "NO";
+    defparam FS_972_add_4_1.INJECT1_1 = "NO";
+    LUT4 MAin_9__I_0_565_i9_3_lut (.A(RowA[8]), .B(MAin_c_8), .C(nRowColSel), 
+         .Z(RA_c_8)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(54[19:54])
+    defparam MAin_9__I_0_565_i9_3_lut.init = 16'hcaca;
+    LUT4 MAin_9__I_0_565_i10_3_lut (.A(RowA[9]), .B(MAin_c_9), .C(nRowColSel), 
+         .Z(RA_c_9)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(54[19:54])
+    defparam MAin_9__I_0_565_i10_3_lut.init = 16'hcaca;
+    LUT4 i2_4_lut_4_lut (.A(FS[6]), .B(n4097), .C(FS[11]), .D(n4905), 
+         .Z(n4530)) /* synthesis lut_function=(!(A+(B+((D)+!C)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam i2_4_lut_4_lut.init = 16'h0010;
+    CCU2D FS_972_add_4_5 (.A0(FS[3]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
+          .A1(FS[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n4087), 
+          .COUT(n4088), .S0(n92), .S1(n91));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam FS_972_add_4_5.INIT0 = 16'hfaaa;
+    defparam FS_972_add_4_5.INIT1 = 16'hfaaa;
+    defparam FS_972_add_4_5.INJECT1_0 = "NO";
+    defparam FS_972_add_4_5.INJECT1_1 = "NO";
+    LUT4 i1248_4_lut (.A(wb_cyc_stb_N_350), .B(wb_cyc_stb_N_348), .C(n4893), 
+         .D(n4892), .Z(n2104)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(684[12] 729[6])
+    defparam i1248_4_lut.init = 16'h0aca;
+    LUT4 i2812_2_lut_rep_69 (.A(RCKE_c), .B(RASr2), .Z(n4918)) /* synthesis lut_function=(A+(B)) */ ;
+    defparam i2812_2_lut_rep_69.init = 16'heeee;
+    LUT4 i1_2_lut_rep_52_4_lut (.A(CmdSubmitted), .B(PHI2r3), .C(PHI2r2), 
+         .D(CmdUFMShift), .Z(n4901)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47])
+    defparam i1_2_lut_rep_52_4_lut.init = 16'h0800;
+    LUT4 i3810_4_lut (.A(InitReady), .B(n10_adj_2), .C(n4899), .D(n4), 
+         .Z(n4634)) /* synthesis lut_function=(A+!(B+(C (D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(525[4] 647[11])
+    defparam i3810_4_lut.init = 16'habbb;
+    LUT4 i3792_2_lut (.A(nCRAS_c), .B(LEDEN), .Z(LED_N_134)) /* synthesis lut_function=(A+!(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(12[15:34])
+    defparam i3792_2_lut.init = 16'hbbbb;
+    LUT4 i2694_2_lut_rep_67 (.A(FWEr), .B(CBR), .Z(n4916)) /* synthesis lut_function=(A+(B)) */ ;
+    defparam i2694_2_lut_rep_67.init = 16'heeee;
+    LUT4 RASr2_I_0_1_lut_rep_72 (.A(RASr2), .Z(n4921)) /* synthesis lut_function=(!(A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(135[40:46])
+    defparam RASr2_I_0_1_lut_rep_72.init = 16'h5555;
+    LUT4 i2_3_lut_rep_68 (.A(CmdSubmitted), .B(PHI2r3), .C(PHI2r2), .Z(n4917)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47])
+    defparam i2_3_lut_rep_68.init = 16'h0808;
+    LUT4 i3742_2_lut (.A(nRowColSel_N_33), .B(CASr2), .Z(n4618)) /* synthesis lut_function=(A+!(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(178[13] 223[7])
+    defparam i3742_2_lut.init = 16'hbbbb;
+    LUT4 nRWE_I_0_596_4_lut (.A(n3622), .B(nRWE_N_211), .C(Ready), .D(n4906), 
+         .Z(nRWE_N_204)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B+!(C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(224[12] 276[6])
+    defparam nRWE_I_0_596_4_lut.init = 16'hcfc5;
+    LUT4 i1174_2_lut (.A(FS[9]), .B(n4869), .Z(wb_we_N_351)) /* synthesis lut_function=(!(A (B))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(525[4] 647[11])
+    defparam i1174_2_lut.init = 16'h7777;
+    LUT4 i3224_2_lut (.A(FS[12]), .B(FS[7]), .Z(n4097)) /* synthesis lut_function=(A (B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(78[13:15])
+    defparam i3224_2_lut.init = 16'h8888;
+    LUT4 i1662_2_lut_4_lut (.A(n4548), .B(n4885), .C(n4911), .D(C1Submitted_N_232), 
+         .Z(CmdEnable_N_243)) /* synthesis lut_function=(A (B (D)+!B (C+(D)))+!A (D)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(301[7:24])
+    defparam i1662_2_lut_4_lut.init = 16'hff20;
+    LUT4 i3754_2_lut_3_lut (.A(FWEr), .B(CBR), .C(RASr2), .Z(n22)) /* synthesis lut_function=(!(A (C)+!A (B (C)))) */ ;
+    defparam i3754_2_lut_3_lut.init = 16'h1f1f;
+    LUT4 i4_4_lut_adj_30 (.A(nRowColSel_N_35), .B(nRowColSel_N_33), .C(nRowColSel_N_32), 
+         .D(n6), .Z(RCLK_c_enable_20)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
+    defparam i4_4_lut_adj_30.init = 16'hfffe;
+    LUT4 mux_427_i6_3_lut_4_lut (.A(n4917), .B(CmdUFMShift), .C(wb_adr[4]), 
+         .D(wb_adr[5]), .Z(n747)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47])
+    defparam mux_427_i6_3_lut_4_lut.init = 16'hf780;
+    LUT4 i1_4_lut_4_lut_adj_31 (.A(RASr2), .B(n6_adj_15), .C(nRowColSel_N_32), 
+         .D(Ready), .Z(Ready_N_280)) /* synthesis lut_function=(A (D)+!A (B (C+(D))+!B (D))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(135[40:46])
+    defparam i1_4_lut_4_lut_adj_31.init = 16'hff40;
+    LUT4 InitReady_I_0_586_1_lut_rep_73 (.A(InitReady), .Z(RCLK_c_enable_22)) /* synthesis lut_function=(!(A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(710[16:26])
+    defparam InitReady_I_0_586_1_lut_rep_73.init = 16'h5555;
+    LUT4 nRCS_I_0_590_3_lut (.A(nRCS_N_170), .B(nRCS_N_174), .C(Ready), 
+         .Z(nRCS_N_169)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(224[12] 276[6])
+    defparam nRCS_I_0_590_3_lut.init = 16'hcaca;
+    LUT4 i1390_4_lut_4_lut (.A(InitReady), .B(n2262), .C(FS[4]), .D(CmdUFMData), 
+         .Z(wb_cyc_stb_N_307)) /* synthesis lut_function=(A (D)+!A !((C)+!B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(710[16:26])
+    defparam i1390_4_lut_4_lut.init = 16'hae04;
+    LUT4 i2758_2_lut (.A(nRWE_N_210), .B(nRCAS_N_198), .Z(n3622)) /* synthesis lut_function=(A+(B)) */ ;
+    defparam i2758_2_lut.init = 16'heeee;
+    LUT4 i1_2_lut_4_lut_4_lut_adj_32 (.A(InitReady), .B(PHI2r2), .C(PHI2r3), 
+         .D(CmdSubmitted), .Z(RCLK_c_enable_28)) /* synthesis lut_function=(!(A (B+!(C (D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(710[16:26])
+    defparam i1_2_lut_4_lut_4_lut_adj_32.init = 16'h7555;
+    LUT4 i1_2_lut_3_lut_adj_33 (.A(n4917), .B(CmdUFMShift), .C(InitReady), 
+         .Z(RCLK_c_enable_25)) /* synthesis lut_function=(A (B+!(C))+!A !(C)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47])
+    defparam i1_2_lut_3_lut_adj_33.init = 16'h8f8f;
+    LUT4 mux_427_i7_3_lut_4_lut (.A(n4917), .B(CmdUFMShift), .C(wb_adr[5]), 
+         .D(wb_adr[6]), .Z(n746)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47])
+    defparam mux_427_i7_3_lut_4_lut.init = 16'hf780;
+    LUT4 i1_4_lut_4_lut_adj_34 (.A(InitReady), .B(n1), .C(CmdUFMShift), 
+         .D(wb_adr_7__N_92), .Z(n1889)) /* synthesis lut_function=(!(A (C+(D))+!A ((D)+!B))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(710[16:26])
+    defparam i1_4_lut_4_lut_adj_34.init = 16'h004e;
+    PFUMX i36 (.BLUT(n20), .ALUT(n22), .C0(nRowColSel_N_35), .Z(RCKEEN_N_153));
+    LUT4 mux_428_i8_3_lut_4_lut (.A(n4917), .B(CmdUFMShift), .C(wb_dati[6]), 
+         .D(wb_dati[7]), .Z(n754)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47])
+    defparam mux_428_i8_3_lut_4_lut.init = 16'hf780;
+    LUT4 MAin_9__I_0_565_i2_3_lut (.A(RowA[1]), .B(MAin_c_1), .C(nRowColSel), 
+         .Z(RA_c_1)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(54[19:54])
+    defparam MAin_9__I_0_565_i2_3_lut.init = 16'hcaca;
+    LUT4 i1_2_lut_rep_74 (.A(FS[11]), .B(FS[12]), .Z(n4923)) /* synthesis lut_function=(A (B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam i1_2_lut_rep_74.init = 16'h8888;
+    LUT4 i1185_2_lut (.A(nRowColSel_N_33), .B(nRowColSel_N_34), .Z(n2040)) /* synthesis lut_function=(A+(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(187[13] 223[7])
+    defparam i1185_2_lut.init = 16'heeee;
+    PFUMX i3897 (.BLUT(n4850), .ALUT(n747), .C0(InitReady), .Z(wb_adr_7__N_60[5]));
+    LUT4 i2685_2_lut (.A(nCCAS_c), .B(nFWE_c), .Z(n1965)) /* synthesis lut_function=(A+(B)) */ ;
+    defparam i2685_2_lut.init = 16'heeee;
+    LUT4 i1_2_lut_rep_55_3_lut (.A(FS[11]), .B(FS[12]), .C(FS[10]), .Z(n4904)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam i1_2_lut_rep_55_3_lut.init = 16'h0808;
+    LUT4 nRWE_I_53_1_lut (.A(nRWE_N_210), .Z(nRWE_N_209)) /* synthesis lut_function=(!(A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(247[14] 254[8])
+    defparam nRWE_I_53_1_lut.init = 16'h5555;
+    LUT4 i1_2_lut_3_lut_4_lut (.A(FS[7]), .B(FS[6]), .C(n4925), .D(FS[5]), 
+         .Z(n4164)) /* synthesis lut_function=(A+((C+!(D))+!B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam i1_2_lut_3_lut_4_lut.init = 16'hfbff;
+    LUT4 i1_2_lut_rep_46_3_lut_4_lut (.A(FS[9]), .B(FS[8]), .C(n4927), 
+         .D(FS[5]), .Z(n4895)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ;
+    defparam i1_2_lut_rep_46_3_lut_4_lut.init = 16'hfeff;
+    LUT4 i3789_3_lut_4_lut_4_lut (.A(n4890), .B(n4859), .C(FS[10]), .D(n4896), 
+         .Z(n56)) /* synthesis lut_function=(A (B ((D)+!C)+!B (C (D)))+!A (B+(C))) */ ;
+    defparam i3789_3_lut_4_lut_4_lut.init = 16'hfc5c;
+    LUT4 n4580_bdd_4_lut (.A(nFWE_c), .B(MAin_c_1), .C(MAin_c_7), .D(Bank[2]), 
+         .Z(n4782)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ;
+    defparam n4580_bdd_4_lut.init = 16'h0040;
+    LUT4 i2832_2_lut_3_lut_4_lut (.A(FS[9]), .B(FS[8]), .C(FS[6]), .D(FS[5]), 
+         .Z(n3609)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ;
+    defparam i2832_2_lut_3_lut_4_lut.init = 16'hfeff;
+    LUT4 i2_3_lut_4_lut_adj_35 (.A(FS[7]), .B(FS[6]), .C(n4925), .D(FS[5]), 
+         .Z(n2308)) /* synthesis lut_function=(A+((C+(D))+!B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13])
+    defparam i2_3_lut_4_lut_adj_35.init = 16'hfffb;
+    LUT4 i1_2_lut_rep_75 (.A(FS[6]), .B(FS[8]), .Z(n4924)) /* synthesis lut_function=(A+(B)) */ ;
+    defparam i1_2_lut_rep_75.init = 16'heeee;
+    LUT4 i3_4_lut_adj_36 (.A(CASr2), .B(FWEr), .C(CBR), .D(CASr3), .Z(nRCS_N_179)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ;
+    defparam i3_4_lut_adj_36.init = 16'h0008;
+    LUT4 i1_2_lut_3_lut_4_lut_adj_37 (.A(FS[6]), .B(FS[8]), .C(n4928), 
+         .D(FS[7]), .Z(n646)) /* synthesis lut_function=(!(A+(B+((D)+!C)))) */ ;
+    defparam i1_2_lut_3_lut_4_lut_adj_37.init = 16'h0010;
+    PUR PUR_INST (.PUR(VCC_net));
+    defparam PUR_INST.RST_PULSE = 1;
+    LUT4 i1_2_lut_rep_61_3_lut (.A(FS[6]), .B(FS[8]), .C(FS[7]), .Z(n4910)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ;
+    defparam i1_2_lut_rep_61_3_lut.init = 16'h1010;
+    LUT4 mux_428_i6_3_lut_4_lut (.A(n4917), .B(CmdUFMShift), .C(wb_dati[4]), 
+         .D(wb_dati[5]), .Z(n756)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47])
+    defparam mux_428_i6_3_lut_4_lut.init = 16'hf780;
+    TSALL TSALL_INST (.TSALL(GND_net));
+    LUT4 i1667_3_lut_4_lut (.A(InitReady), .B(n4886), .C(wb_dato[1]), 
+         .D(CmdLEDEN), .Z(LEDEN_N_110)) /* synthesis lut_function=(A (D)+!A (B (D)+!B (C))) */ ;
+    defparam i1667_3_lut_4_lut.init = 16'hfe10;
+    LUT4 mux_428_i3_3_lut_4_lut (.A(n4917), .B(CmdUFMShift), .C(wb_dati[1]), 
+         .D(wb_dati[2]), .Z(n759)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47])
+    defparam mux_428_i3_3_lut_4_lut.init = 16'hf780;
+    LUT4 i1_2_lut_rep_76 (.A(FS[9]), .B(FS[8]), .Z(n4925)) /* synthesis lut_function=(A+(B)) */ ;
+    defparam i1_2_lut_rep_76.init = 16'heeee;
+    LUT4 i1_3_lut_4_lut_adj_38 (.A(n4893), .B(n4892), .C(InitReady), .D(n4917), 
+         .Z(n4513)) /* synthesis lut_function=(A (B (D)+!B (C (D)))+!A (C (D))) */ ;
+    defparam i1_3_lut_4_lut_adj_38.init = 16'hf800;
+    LUT4 i1_2_lut_rep_56_3_lut (.A(FS[9]), .B(FS[8]), .C(FS[5]), .Z(n4905)) /* synthesis lut_function=(A+(B+!(C))) */ ;
+    defparam i1_2_lut_rep_56_3_lut.init = 16'hefef;
+    LUT4 i36_4_lut (.A(n5142), .B(n754), .C(InitReady), .D(n17), .Z(wb_dati_7__N_68[7])) /* synthesis lut_function=(A (B+!(C))+!A (B (C+(D))+!B !(C+!(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6])
+    defparam i36_4_lut.init = 16'hcfca;
+    LUT4 mux_428_i4_3_lut_4_lut (.A(n4917), .B(CmdUFMShift), .C(wb_dati[2]), 
+         .D(wb_dati[3]), .Z(n758)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47])
+    defparam mux_428_i4_3_lut_4_lut.init = 16'hf780;
+    LUT4 i2696_4_lut (.A(nRCS_N_179), .B(nRowColSel_N_34), .C(n4916), 
+         .D(nRowColSel_N_33), .Z(nRCS_N_175)) /* synthesis lut_function=(A (B+(C (D)))+!A (B+(C+!(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(187[13] 223[7])
+    defparam i2696_4_lut.init = 16'hfcdd;
+    LUT4 InitReady_I_0_3_lut (.A(InitReady), .B(RCKEEN_N_153), .C(Ready), 
+         .Z(RCKEEN_N_152)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(224[12] 276[6])
+    defparam InitReady_I_0_3_lut.init = 16'hcaca;
+    LUT4 i2726_2_lut (.A(nRowColSel_N_33), .B(nRowColSel_N_32), .Z(n1286)) /* synthesis lut_function=(A+(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123[13:16])
+    defparam i2726_2_lut.init = 16'heeee;
+    LUT4 i3795_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQML_c)) /* synthesis lut_function=(!(A (B))) */ ;
+    defparam i3795_2_lut.init = 16'h7777;
+    LUT4 i95_4_lut (.A(n4894), .B(FS[10]), .C(FS[12]), .D(n4900), .Z(n3711)) /* synthesis lut_function=(A (B (C+(D))+!B ((D)+!C))+!A (B (C+(D))+!B (C (D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(78[13:15])
+    defparam i95_4_lut.init = 16'hfec2;
+    LUT4 i2684_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQMH_c)) /* synthesis lut_function=(A+!(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(57[17:46])
+    defparam i2684_2_lut.init = 16'hbbbb;
+    LUT4 mux_428_i2_3_lut_4_lut (.A(n4917), .B(CmdUFMShift), .C(wb_dati[0]), 
+         .D(wb_dati[1]), .Z(n760)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47])
+    defparam mux_428_i2_3_lut_4_lut.init = 16'hf780;
+    LUT4 i2_3_lut_4_lut_adj_39 (.A(FS[9]), .B(FS[8]), .C(FS[7]), .D(n4939), 
+         .Z(n4149)) /* synthesis lut_function=(A+(B+((D)+!C))) */ ;
+    defparam i2_3_lut_4_lut_adj_39.init = 16'hffef;
+    LUT4 mux_428_i7_3_lut_4_lut (.A(n4917), .B(CmdUFMShift), .C(wb_dati[5]), 
+         .D(wb_dati[6]), .Z(n755)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47])
+    defparam mux_428_i7_3_lut_4_lut.init = 16'hf780;
+    LUT4 mux_428_i5_3_lut_4_lut (.A(n4917), .B(CmdUFMShift), .C(wb_dati[3]), 
+         .D(wb_dati[4]), .Z(n757)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47])
+    defparam mux_428_i5_3_lut_4_lut.init = 16'hf780;
+    LUT4 mux_427_i2_3_lut_4_lut (.A(n4917), .B(CmdUFMShift), .C(wb_adr[0]), 
+         .D(wb_adr[1]), .Z(n751)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47])
+    defparam mux_427_i2_3_lut_4_lut.init = 16'hf780;
+    LUT4 MAin_9__I_0_565_i1_3_lut (.A(RowA[0]), .B(MAin_c_0), .C(nRowColSel), 
+         .Z(RA_c_0)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(54[19:54])
+    defparam MAin_9__I_0_565_i1_3_lut.init = 16'hcaca;
+    LUT4 mux_428_i1_3_lut_4_lut (.A(n4917), .B(CmdUFMShift), .C(wb_we), 
+         .D(wb_dati[0]), .Z(n761)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47])
+    defparam mux_428_i1_3_lut_4_lut.init = 16'hf780;
+    INV i4008 (.A(PHI2_c), .Z(PHI2_N_151));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(7[8:12])
+    INV i4007 (.A(nCRAS_c), .Z(nCRAS_N_9));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(15[15:20])
+    PFUMX i3913 (.BLUT(n4940), .ALUT(n4941), .C0(FS[9]), .Z(wb_we_N_354));
+    VLO i1 (.Z(GND_net));
+    
+endmodule
+//
+// Verilog Description of module PUR
+// module not written out since it is a black-box. 
+//
+
+//
+// Verilog Description of module TSALL
+// module not written out since it is a black-box. 
+//
+
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/automake.log b/CPLD/LCMXO2/LCMXO2-640HC/impl1/automake.log
new file mode 100644
index 0000000..aef4f04
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/automake.log
@@ -0,0 +1,1344 @@
+
+map -a "MachXO2" -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial   "RAM2GS_LCMXO2_640HC_impl1.ngd" -o "RAM2GS_LCMXO2_640HC_impl1_map.ncd" -pr "RAM2GS_LCMXO2_640HC_impl1.prf" -mp "RAM2GS_LCMXO2_640HC_impl1.mrp" -lpf "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lpf" -lpf "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf"  -c 0           
+map:  version Diamond (64-bit) 3.12.0.240.2
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+   Process the file: RAM2GS_LCMXO2_640HC_impl1.ngd
+   Picdevice="LCMXO2-640HC"
+
+   Pictype="TQFP100"
+
+   Picspeed=4
+
+   Remove unused logic
+
+   Do not produce over sized NCDs.
+
+Part used: LCMXO2-640HCTQFP100, Performance used: 4.
+
+Loading device for application baspr from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+
+Running general design DRC...
+
+Removing unused logic...
+
+Optimizing...
+
+
+
+
+Design Summary:
+   Number of registers:    119 out of   877 (14%)
+      PFU registers:          119 out of   640 (19%)
+      PIO registers:            0 out of   237 (0%)
+   Number of SLICEs:       131 out of   320 (41%)
+      SLICEs as Logic/ROM:    131 out of   320 (41%)
+      SLICEs as RAM:            0 out of   240 (0%)
+      SLICEs as Carry:         10 out of   320 (3%)
+   Number of LUT4s:        255 out of   640 (40%)
+      Number used as logic LUTs:        235
+      Number used as distributed RAM:     0
+      Number used as ripple logic:       20
+      Number used as shift registers:     0
+   Number of PIO sites used: 63 + 4(JTAG) out of 79 (85%)
+   Number of block RAMs:  0 out of 2 (0%)
+   Number of GSRs:        0 out of 1 (0%)
+   EFB used :        Yes
+   JTAG used :       No
+   Readback used :   No
+   Oscillator used : No
+   Startup used :    No
+   POR :             On
+   Bandgap :         On
+   Number of Power Controller:  0 out of 1 (0%)
+   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
+   Number of DCCA:  0 out of 8 (0%)
+   Number of DCMA:  0 out of 2 (0%)
+   Notes:-
+      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic)
+      2. Number of logic LUT4s does not include count of distributed RAM and ripple logic.
+   Number of clocks:  5
+     Net RCLK_c: 52 loads, 52 rising, 0 falling (Driver: PIO RCLK )
+     Net wb_clk: 1 loads, 1 rising, 0 falling (Driver: wb_clk_550 )
+     Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 )
+     Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS )
+     Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
+   Number of Clock Enables:  14
+     Net RCLK_c_enable_27: 8 loads, 8 LSLICEs
+     Net RCLK_c_enable_20: 4 loads, 4 LSLICEs
+     Net RCLK_c_enable_29: 2 loads, 2 LSLICEs
+     Net RCLK_c_enable_25: 2 loads, 2 LSLICEs
+     Net InitReady: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_24: 2 loads, 2 LSLICEs
+     Net PHI2_N_151_enable_1: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_26: 1 loads, 1 LSLICEs
+     Net PHI2_N_151_enable_3: 1 loads, 1 LSLICEs
+     Net PHI2_N_151_enable_5: 2 loads, 2 LSLICEs
+     Net Ready_N_280: 1 loads, 1 LSLICEs
+     Net PHI2_N_151_enable_6: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_28: 1 loads, 1 LSLICEs
+     Net PHI2_N_151_enable_7: 1 loads, 1 LSLICEs
+   Number of LSRs:  8
+     Net RASr2: 1 loads, 1 LSLICEs
+     Net nRowColSel_N_34: 1 loads, 1 LSLICEs
+     Net wb_rst: 1 loads, 0 LSLICEs
+     Net nRWE_N_210: 1 loads, 1 LSLICEs
+     Net C1Submitted_N_232: 2 loads, 2 LSLICEs
+     Net wb_adr_7__N_92: 2 loads, 2 LSLICEs
+     Net nRowColSel_N_35: 1 loads, 1 LSLICEs
+     Net Ready: 7 loads, 7 LSLICEs
+   Number of nets driven by tri-state buffers:  0
+   Top 10 highest fanout non-clock nets:
+     Net InitReady: 36 loads
+     Net FS_10: 32 loads
+     Net FS_11: 32 loads
+     Net FS_9: 26 loads
+     Net FS_7: 25 loads
+     Net FS_8: 23 loads
+     Net FS_5: 21 loads
+     Net FS_6: 21 loads
+     Net FS_12: 20 loads
+     Net Ready: 18 loads
+ 
+
+   Number of warnings:  0
+   Number of errors:    0
+
+
+
+Total CPU Time: 0 secs  
+Total REAL Time: 0 secs  
+Peak Memory Usage: 36 MB
+
+Dumping design to file RAM2GS_LCMXO2_640HC_impl1_map.ncd.
+
+ncd2vdb "RAM2GS_LCMXO2_640HC_impl1_map.ncd" ".vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb"
+
+Loading device for application ncd2vdb from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+
+trce -f "RAM2GS_LCMXO2_640HC_impl1.mt" -o "RAM2GS_LCMXO2_640HC_impl1.tw1" "RAM2GS_LCMXO2_640HC_impl1_map.ncd" "RAM2GS_LCMXO2_640HC_impl1.prf"
+trce:  version Diamond (64-bit) 3.12.0.240.2
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
+Tue Aug 17 06:20:51 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_640hc_impl1_map.ncd
+Preference file: ram2gs_lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,4
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+VCCIO Voltage:
+                   3.135 V (Bank 0)
+                   3.135 V (Bank 1)
+                   3.135 V (Bank 2)
+                   3.135 V (Bank 3)
+                   2.375 V (Bank 4)
+                   2.375 V (Bank 5)
+                   2.375 V (Bank 6)
+                   2.375 V (Bank 7)
+
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 1548 paths, 9 nets, and 889 connections (78.60% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
+Tue Aug 17 06:20:51 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_640hc_impl1_map.ncd
+Preference file: ram2gs_lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,M
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+VCCIO Voltage:
+                   3.135 V (Bank 0)
+                   3.135 V (Bank 1)
+                   3.135 V (Bank 2)
+                   3.135 V (Bank 3)
+                   2.375 V (Bank 4)
+                   2.375 V (Bank 5)
+                   2.375 V (Bank 6)
+                   2.375 V (Bank 7)
+
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 1548 paths, 9 nets, and 889 connections (78.60% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 0 (setup), 0 (hold)
+Score: 0 (setup), 0 (hold)
+Cumulative negative slack: 0 (0+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
+Total CPU Time: 0 secs 
+Total REAL Time: 0 secs 
+Peak Memory Usage: 40 MB
+
+
+mpartrce -p "RAM2GS_LCMXO2_640HC_impl1.p2t" -f "RAM2GS_LCMXO2_640HC_impl1.p3t" -tf "RAM2GS_LCMXO2_640HC_impl1.pt" "RAM2GS_LCMXO2_640HC_impl1_map.ncd" "RAM2GS_LCMXO2_640HC_impl1.ncd"
+
+---- MParTrce Tool ----
+Removing old design directory at request of -rem command line option to this program.
+Running par. Please wait . . .
+
+Lattice Place and Route Report for Design "RAM2GS_LCMXO2_640HC_impl1_map.ncd"
+Tue Aug 17 06:20:51 2021
+
+PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
+Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file RAM2GS_LCMXO2_640HC_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+Device utilization summary:
+
+   PIO (prelim)   63+4(JTAG)/80      84% used
+                  63+4(JTAG)/79      85% bonded
+
+   SLICE            131/320          40% used
+
+   EFB                1/1           100% used
+
+
+Number of Signals: 401
+Number of Connections: 1131
+
+Pin Constraint Summary:
+   63 out of 63 pins locked (100% locked).
+
+The following 4 signals are selected to use the primary clock routing resources:
+    RCLK_c (driver: RCLK, clk load #: 52)
+    PHI2_c (driver: PHI2, clk load #: 13)
+    nCRAS_c (driver: nCRAS, clk load #: 7)
+    nCCAS_c (driver: nCCAS, clk load #: 4)
+
+    
+    
+    
+
+No signal is selected as secondary clock.
+
+No signal is selected as Global Set/Reset.
+Starting Placer Phase 0.
+............
+Finished Placer Phase 0.  REAL time: 0 secs 
+
+Starting Placer Phase 1.
+....................
+Placer score = 65362.
+Finished Placer Phase 1.  REAL time: 6 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  65089
+Finished Placer Phase 2.  REAL time: 6 secs 
+
+
+------------------ Clock Report ------------------
+
+Global Clock Resources:
+  CLK_PIN    : 1 out of 8 (12%)
+  General PIO: 3 out of 80 (3%)
+  DCM        : 0 out of 2 (0%)
+  DCC        : 0 out of 8 (0%)
+
+Global Clocks:
+  PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "63 (PR5C)", clk load = 52
+  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 13
+  PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 7
+  PRIMARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 4
+
+  PRIMARY  : 4 out of 8 (50%)
+  SECONDARY: 0 out of 8 (0%)
+
+--------------- End of Clock Report ---------------
+
+
+I/O Usage Summary (final):
+   63 + 4(JTAG) out of 80 (83.8%) PIO sites used.
+   63 + 4(JTAG) out of 79 (84.8%) bonded PIO sites used.
+   Number of PIO comps: 63; differential: 0.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+----------------+------------+-----------+
+| I/O Bank | Usage          | Bank Vccio | Bank Vref |
++----------+----------------+------------+-----------+
+| 0        | 13 / 19 ( 68%) | 3.3V       | -         |
+| 1        | 20 / 20 (100%) | 3.3V       | -         |
+| 2        | 12 / 20 ( 60%) | 3.3V       | -         |
+| 3        | 18 / 20 ( 90%) | 3.3V       | -         |
++----------+----------------+------------+-----------+
+
+Total placer CPU time: 5 secs 
+
+Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
+
+0 connections routed; 1131 unrouted.
+Starting router resource preassignment
+    
+    
+    
+
+    
+
+Completed router resource preassignment. Real time: 8 secs 
+
+Start NBR router at 06:20:59 08/17/21
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at 06:20:59 08/17/21
+
+Start NBR section for initial routing at 06:20:59 08/17/21
+Level 1, iteration 1
+0(0.00%) conflict; 980(86.65%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.167ns/0.000ns; real time: 8 secs 
+Level 2, iteration 1
+1(0.00%) conflict; 970(85.76%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.141ns/0.000ns; real time: 9 secs 
+Level 3, iteration 1
+1(0.00%) conflict; 904(79.93%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+Level 4, iteration 1
+26(0.06%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 06:21:00 08/17/21
+Level 1, iteration 1
+1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+Level 2, iteration 1
+1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+Level 3, iteration 1
+1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+Level 4, iteration 1
+12(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+Level 4, iteration 2
+5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+Level 4, iteration 3
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+
+Start NBR section for setup/hold timing optimization with effort level 3 at 06:21:00 08/17/21
+
+Start NBR section for re-routing at 06:21:00 08/17/21
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 9 secs 
+
+Start NBR section for post-routing at 06:21:00 08/17/21
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 0 (0.00%)
+  Estimated worst slack : 1.135ns
+  Timing score : 0
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+    
+
+Total CPU time 9 secs 
+Total REAL time: 10 secs 
+Completely routed.
+End of route.  1131 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 0 
+
+Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
+
+
+PAR_SUMMARY::Run status = Completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack> = 1.135
+PAR_SUMMARY::Timing score> = 0.000
+PAR_SUMMARY::Worst  slack> = 0.304
+PAR_SUMMARY::Timing score> = 0.000
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 9 secs 
+Total REAL time to completion: 10 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Exiting par with exit code 0
+Exiting mpartrce with exit code 0
+
+trce -f "RAM2GS_LCMXO2_640HC_impl1.pt" -o "RAM2GS_LCMXO2_640HC_impl1.twr" "RAM2GS_LCMXO2_640HC_impl1.ncd" "RAM2GS_LCMXO2_640HC_impl1.prf"
+trce:  version Diamond (64-bit) 3.12.0.240.2
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
+Tue Aug 17 06:21:01 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_640hc_impl1.ncd
+Preference file: ram2gs_lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,4
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+VCCIO Voltage:
+                   3.135 V (Bank 0)
+                   3.135 V (Bank 1)
+                   3.135 V (Bank 2)
+                   3.135 V (Bank 3)
+                   2.375 V (Bank 4)
+                   2.375 V (Bank 5)
+                   2.375 V (Bank 6)
+                   2.375 V (Bank 7)
+
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 1548 paths, 9 nets, and 900 connections (79.58% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
+Tue Aug 17 06:21:01 2021
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_640hc_impl1.ncd
+Preference file: ram2gs_lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,m
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+Derating parameters
+-------------------
+Voltage:    3.300 V
+
+VCCIO Voltage:
+                   3.135 V (Bank 0)
+                   3.135 V (Bank 1)
+                   3.135 V (Bank 2)
+                   3.135 V (Bank 3)
+                   2.375 V (Bank 4)
+                   2.375 V (Bank 5)
+                   2.375 V (Bank 6)
+                   2.375 V (Bank 7)
+
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 1548 paths, 9 nets, and 900 connections (79.58% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 0 (setup), 0 (hold)
+Score: 0 (setup), 0 (hold)
+Cumulative negative slack: 0 (0+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
+Total CPU Time: 0 secs 
+Total REAL Time: 0 secs 
+Peak Memory Usage: 40 MB
+
+
+iotiming  "RAM2GS_LCMXO2_640HC_impl1.ncd" "RAM2GS_LCMXO2_640HC_impl1.prf"
+I/O Timing Report:
+:  version Diamond (64-bit) 3.12.0.240.2
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application iotiming from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Running Performance Grade: 4
+Computing Setup Time ...
+Computing Max Clock to Output Delay ...
+Computing Hold Time ...
+Computing Min Clock to Output Delay ...
+
+Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 5
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Running Performance Grade: 5
+Computing Setup Time ...
+Computing Max Clock to Output Delay ...
+Computing Hold Time ...
+Computing Min Clock to Output Delay ...
+
+Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 6
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Running Performance Grade: 6
+Computing Setup Time ...
+Computing Max Clock to Output Delay ...
+Computing Hold Time ...
+Computing Min Clock to Output Delay ...
+
+Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: M
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Running Performance Grade: M
+Computing Setup Time ...
+Computing Max Clock to Output Delay ...
+Computing Hold Time ...
+Computing Min Clock to Output Delay ...
+Done.
+
+ibisgen "RAM2GS_LCMXO2_640HC_impl1.pad" "C:/lscc/diamond/3.12/cae_library/ibis/machxo2.ibs"   
+IBIS Models Generator: Lattice Diamond (64-bit) 3.12.0.240.2
+
+Tue Aug 17 06:21:03 2021
+
+Comp: CROW[0]
+ Site: 10
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: CROW[1]
+ Site: 16
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: Din[0]
+ Site: 3
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: Din[1]
+ Site: 96
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: Din[2]
+ Site: 88
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: Din[3]
+ Site: 97
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: Din[4]
+ Site: 99
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: Din[5]
+ Site: 98
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: Din[6]
+ Site: 2
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: Din[7]
+ Site: 1
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: Dout[0]
+ Site: 76
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[1]
+ Site: 86
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[2]
+ Site: 87
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[3]
+ Site: 85
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[4]
+ Site: 83
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[5]
+ Site: 84
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[6]
+ Site: 78
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: Dout[7]
+ Site: 82
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: LED
+ Site: 34
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=16mA 
+ SLEW=SLOW 
+-----------------------
+Comp: MAin[0]
+ Site: 14
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: MAin[1]
+ Site: 12
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: MAin[2]
+ Site: 13
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: MAin[3]
+ Site: 21
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: MAin[4]
+ Site: 20
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: MAin[5]
+ Site: 19
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: MAin[6]
+ Site: 24
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: MAin[7]
+ Site: 18
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: MAin[8]
+ Site: 25
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: MAin[9]
+ Site: 32
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: PHI2
+ Site: 8
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: RA[0]
+ Site: 66
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[10]
+ Site: 64
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[11]
+ Site: 59
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[1]
+ Site: 67
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[2]
+ Site: 69
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[3]
+ Site: 71
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[4]
+ Site: 74
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[5]
+ Site: 70
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[6]
+ Site: 68
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[7]
+ Site: 75
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[8]
+ Site: 65
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RA[9]
+ Site: 62
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RBA[0]
+ Site: 58
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RBA[1]
+ Site: 60
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RCKE
+ Site: 53
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RCLK
+ Site: 63
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: RDQMH
+ Site: 51
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RDQML
+ Site: 48
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: RD[0]
+ Site: 36
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ PULL=KEEPER 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+ SLEW=SLOW 
+-----------------------
+Comp: RD[1]
+ Site: 37
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ PULL=KEEPER 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+ SLEW=SLOW 
+-----------------------
+Comp: RD[2]
+ Site: 38
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ PULL=KEEPER 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+ SLEW=SLOW 
+-----------------------
+Comp: RD[3]
+ Site: 39
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ PULL=KEEPER 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+ SLEW=SLOW 
+-----------------------
+Comp: RD[4]
+ Site: 40
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ PULL=KEEPER 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+ SLEW=SLOW 
+-----------------------
+Comp: RD[5]
+ Site: 41
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ PULL=KEEPER 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+ SLEW=SLOW 
+-----------------------
+Comp: RD[6]
+ Site: 42
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ PULL=KEEPER 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+ SLEW=SLOW 
+-----------------------
+Comp: RD[7]
+ Site: 43
+ Type: BIDI
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ PULL=KEEPER 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+ SLEW=SLOW 
+-----------------------
+Comp: nCCAS
+ Site: 9
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: nCRAS
+ Site: 17
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: nFWE
+ Site: 15
+ Type: IN
+ IO_TYPE=LVTTL33 
+ CLAMP=ON 
+ HYSTERESIS=SMALL 
+-----------------------
+Comp: nRCAS
+ Site: 52
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: nRCS
+ Site: 57
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: nRRAS
+ Site: 54
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Comp: nRWE
+ Site: 49
+ Type: OUT
+ IO_TYPE=LVTTL33 
+ DRIVE=4mA 
+ SLEW=SLOW 
+-----------------------
+Created design models.
+
+
+Generating: C:\Users\Dog\Documents\GitHub\RAM2GS\CPLD\LCMXO2\LCMXO2-640HC\impl1\IBIS\RAM2GS_LCMXO2_640HC~.ibs
+
+
+    
+
+tmcheck -par "RAM2GS_LCMXO2_640HC_impl1.par" 
+
+bitgen -f "RAM2GS_LCMXO2_640HC_impl1.t2b" -w "RAM2GS_LCMXO2_640HC_impl1.ncd"  "RAM2GS_LCMXO2_640HC_impl1.prf"
+
+
+BITGEN: Bitstream Generator Diamond (64-bit) 3.12.0.240.2
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+
+Loading design for application Bitgen from file RAM2GS_LCMXO2_640HC_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+
+Running DRC.
+DRC detected 0 errors and 0 warnings.
+Reading Preference File from RAM2GS_LCMXO2_640HC_impl1.prf.
+
+Preference Summary:
++---------------------------------+---------------------------------+
+|  Preference                     |  Current Setting                |
++---------------------------------+---------------------------------+
+|                         RamCfg  |                        Reset**  |
++---------------------------------+---------------------------------+
+|                     MCCLK_FREQ  |                         2.08**  |
++---------------------------------+---------------------------------+
+|                  CONFIG_SECURE  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                          INBUF  |                           ON**  |
++---------------------------------+---------------------------------+
+|                      JTAG_PORT  |                       ENABLE**  |
++---------------------------------+---------------------------------+
+|                       SDM_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                 SLAVE_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                MASTER_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                       I2C_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|        MUX_CONFIGURATION_PORTS  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  CONFIGURATION  |                          CFG**  |
++---------------------------------+---------------------------------+
+|                COMPRESS_CONFIG  |                           ON**  |
++---------------------------------+---------------------------------+
+|                        MY_ASSP  |                          OFF**  |
++---------------------------------+---------------------------------+
+|               ONE_TIME_PROGRAM  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                 ENABLE_TRANSFR  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  SHAREDEBRINIT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|            BACKGROUND_RECONFIG  |                          OFF**  |
++---------------------------------+---------------------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+
+Creating bit map...
+ 
+Bitstream Status: Final           Version 1.95.
+ 
+Saving bit stream in "RAM2GS_LCMXO2_640HC_impl1.bit".
+Total CPU Time: 1 secs 
+Total REAL Time: 2 secs 
+Peak Memory Usage: 245 MB
+
+tmcheck -par "RAM2GS_LCMXO2_640HC_impl1.par" 
+
+bitgen -f "RAM2GS_LCMXO2_640HC_impl1.t2b" -w "RAM2GS_LCMXO2_640HC_impl1.ncd"  -jedec "RAM2GS_LCMXO2_640HC_impl1.prf"
+
+
+BITGEN: Bitstream Generator Diamond (64-bit) 3.12.0.240.2
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+
+Loading design for application Bitgen from file RAM2GS_LCMXO2_640HC_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+
+Running DRC.
+DRC detected 0 errors and 0 warnings.
+Reading Preference File from RAM2GS_LCMXO2_640HC_impl1.prf.
+
+Preference Summary:
++---------------------------------+---------------------------------+
+|  Preference                     |  Current Setting                |
++---------------------------------+---------------------------------+
+|                         RamCfg  |                        Reset**  |
++---------------------------------+---------------------------------+
+|                     MCCLK_FREQ  |                         2.08**  |
++---------------------------------+---------------------------------+
+|                  CONFIG_SECURE  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                          INBUF  |                           ON**  |
++---------------------------------+---------------------------------+
+|                      JTAG_PORT  |                       ENABLE**  |
++---------------------------------+---------------------------------+
+|                       SDM_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                 SLAVE_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                MASTER_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                       I2C_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|        MUX_CONFIGURATION_PORTS  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  CONFIGURATION  |                          CFG**  |
++---------------------------------+---------------------------------+
+|                COMPRESS_CONFIG  |                           ON**  |
++---------------------------------+---------------------------------+
+|                        MY_ASSP  |                          OFF**  |
++---------------------------------+---------------------------------+
+|               ONE_TIME_PROGRAM  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                 ENABLE_TRANSFR  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  SHAREDEBRINIT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|            BACKGROUND_RECONFIG  |                          OFF**  |
++---------------------------------+---------------------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+
+Creating bit map...
+ 
+Bitstream Status: Final           Version 1.95.
+ 
+Saving bit stream in "RAM2GS_LCMXO2_640HC_impl1.jed".
+ 
+===========
+UFM Summary.
+===========
+UFM Size:        191 Pages (128*191 Bits).
+UFM Utilization: General Purpose Flash Memory.
+ 
+Available General Purpose Flash Memory:  191 Pages (Page 0 to Page 190).
+Initialized UFM Pages:                     0 Page.
+ 
+Total CPU Time: 1 secs 
+Total REAL Time: 2 secs 
+Peak Memory Usage: 245 MB
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html b/CPLD/LCMXO2/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html
new file mode 100644
index 0000000..ad12f66
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html
@@ -0,0 +1,12 @@
+         	                                   	                                                	                                                 	                                                  	
    Setting log file to 'C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html'.
+Starting: parse design source files
+(VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v'
+(VERI-1482) Analyzing Verilog file 'C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v'
+INFO - C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v(1,8-1,14) (VERI-1018) compiling module 'RAM2GS'
+INFO - C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v(1,1-731,10) (VERI-9000) elaborating module 'RAM2GS'
+INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1800,1-1872,10) (VERI-9000) elaborating module 'EFB_uniq_1'
+WARNING - C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v(325,2-348,25) (VERI-2435) port 'PLL0DATI7' is not connected on this instance
+WARNING - C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v(325,2-348,25) (VERI-1927) port 'WBDATO7' remains unconnected for this instance
+Done: design load finished with (0) errors, and (2) warnings
+
+
    
\ No newline at end of file
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1.ior b/CPLD/LCMXO2/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1.ior
new file mode 100644
index 0000000..6529f93
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1.ior
@@ -0,0 +1,133 @@
+Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 5
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 6
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: M
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+// Design: RAM2GS
+// Package: TQFP100
+// ncd File: ram2gs_lcmxo2_640hc_impl1.ncd
+// Version: Diamond (64-bit) 3.12.0.240.2
+// Written on Tue Aug 17 06:21:03 2021
+// M: Minimum Performance Grade
+// iotiming RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml
+
+I/O Timing Report (All units are in ns)
+
+Worst Case Results across Performance Grades (M, 6, 5, 4):
+
+// Input Setup and Hold Times
+
+Port    Clock Edge  Setup Performance_Grade  Hold Performance_Grade
+----------------------------------------------------------------------
+CROW[0] nCRAS F    -0.195      M       1.729     4
+CROW[1] nCRAS F    -0.218      M       1.801     4
+Din[0]  PHI2  F     6.339      4       1.186     4
+Din[0]  nCCAS F     1.641      4       0.107     M
+Din[1]  PHI2  F     6.084      4       1.570     4
+Din[1]  nCCAS F     0.198      4       1.314     4
+Din[2]  PHI2  F     3.778      4       1.771     4
+Din[2]  nCCAS F     0.075      4       1.431     4
+Din[3]  PHI2  F     4.331      4       1.705     4
+Din[3]  nCCAS F    -0.116      M       1.722     4
+Din[4]  PHI2  F     6.176      4       1.711     4
+Din[4]  nCCAS F     1.065      4       0.575     4
+Din[5]  PHI2  F     4.684      4       1.261     4
+Din[5]  nCCAS F    -0.081      M       1.625     4
+Din[6]  PHI2  F     5.243      4       0.356     4
+Din[6]  nCCAS F     1.414      4       0.309     4
+Din[7]  PHI2  F     6.602      4       1.175     4
+Din[7]  nCCAS F    -0.286      M       2.137     4
+MAin[0] PHI2  F     5.034      4       0.629     4
+MAin[0] nCRAS F     1.094      4       0.380     4
+MAin[1] PHI2  F     6.081      4       1.157     4
+MAin[1] nCRAS F     0.544      4       0.877     4
+MAin[2] PHI2  F     9.979      4      -0.319     M
+MAin[2] nCRAS F    -0.050      M       1.401     4
+MAin[3] PHI2  F     9.162      4      -0.219     M
+MAin[3] nCRAS F     1.032      4       0.440     4
+MAin[4] PHI2  F    11.678      4      -0.770     M
+MAin[4] nCRAS F    -0.150      M       1.620     4
+MAin[5] PHI2  F     8.668      4      -0.081     M
+MAin[5] nCRAS F    -0.050      M       1.401     4
+MAin[6] PHI2  F     8.516      4      -0.025     M
+MAin[6] nCRAS F     1.003      4       0.478     4
+MAin[7] PHI2  F     9.320      4      -0.061     M
+MAin[7] nCRAS F     1.001      4       0.478     4
+MAin[8] nCRAS F    -0.146      M       1.657     4
+MAin[9] nCRAS F    -0.360      M       2.140     4
+PHI2    RCLK  R     3.079      4      -0.602     M
+nCCAS   RCLK  R     3.574      4      -0.705     M
+nCCAS   nCRAS F     3.232      4      -0.351     M
+nCRAS   RCLK  R     2.757      4      -0.470     M
+nFWE    PHI2  F     5.913      4       0.723     4
+nFWE    nCRAS F     0.547      4       0.890     4
+
+
+// Clock to Output Delay
+
+Port   Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
+------------------------------------------------------------------------
+LED    RCLK  R    10.062         4        3.164          M
+RA[0]  RCLK  R    10.645         4        3.471          M
+RA[0]  nCRAS F    11.744         4        3.770          M
+RA[10] RCLK  R     9.485         4        3.236          M
+RA[11] PHI2  R    11.513         4        3.824          M
+RA[1]  RCLK  R    10.921         4        3.549          M
+RA[1]  nCRAS F    12.664         4        4.036          M
+RA[2]  RCLK  R    10.923         4        3.527          M
+RA[2]  nCRAS F    12.463         4        3.984          M
+RA[3]  RCLK  R    11.178         4        3.615          M
+RA[3]  nCRAS F    12.304         4        3.917          M
+RA[4]  RCLK  R    11.365         4        3.630          M
+RA[4]  nCRAS F    13.243         4        4.179          M
+RA[5]  RCLK  R    11.365         4        3.630          M
+RA[5]  nCRAS F    12.940         4        4.098          M
+RA[6]  RCLK  R    11.099         4        3.573          M
+RA[6]  nCRAS F    12.162         4        3.870          M
+RA[7]  RCLK  R    10.948         4        3.552          M
+RA[7]  nCRAS F    12.282         4        3.936          M
+RA[8]  RCLK  R    11.114         4        3.608          M
+RA[8]  nCRAS F    12.909         4        4.116          M
+RA[9]  RCLK  R    11.005         4        3.561          M
+RA[9]  nCRAS F    12.959         4        4.081          M
+RBA[0] nCRAS F    11.842         4        3.911          M
+RBA[1] nCRAS F    11.343         4        3.771          M
+RCKE   RCLK  R     9.884         4        3.362          M
+RDQMH  RCLK  R    10.941         4        3.559          M
+RDQML  RCLK  R    10.641         4        3.470          M
+RD[0]  nCCAS F    12.628         4        4.413          M
+RD[1]  nCCAS F    12.231         4        4.302          M
+RD[2]  nCCAS F    12.231         4        4.302          M
+RD[3]  nCCAS F    11.928         4        4.221          M
+RD[4]  nCCAS F    12.427         4        4.361          M
+RD[5]  nCCAS F    12.697         4        4.400          M
+RD[6]  nCCAS F    12.427         4        4.361          M
+RD[7]  nCCAS F    12.427         4        4.361          M
+nRCAS  RCLK  R     9.674         4        3.300          M
+nRCS   RCLK  R     9.674         4        3.300          M
+nRRAS  RCLK  R     9.797         4        3.322          M
+nRWE   RCLK  R     9.275         4        3.194          M
+WARNING: you must also run trce with hold speed: 4
+WARNING: you must also run trce with setup speed: M
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1_trce.asd b/CPLD/LCMXO2/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1_trce.asd
new file mode 100644
index 0000000..0409f06
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1_trce.asd
@@ -0,0 +1,91 @@
+[ActiveSupport TRCE]
+; Setup Analysis
+Period_0 = 25.800 ns (350.000 ns);
+Period_1 = 2.500 ns (350.000 ns);
+Period_2 = 2.500 ns (350.000 ns);
+Period_3 = 12.427 ns (16.000 ns);
+Tco_4 = - (-);
+Tco_5 = - (-);
+Tco_6 = - (-);
+Tco_7 = - (-);
+Tco_8 = - (-);
+Tco_9 = - (-);
+Tco_10 = - (-);
+Tco_11 = - (-);
+Tco_12 = - (-);
+Tco_13 = - (-);
+Tco_14 = - (-);
+Tco_15 = - (-);
+Tco_16 = 9.485 ns (12.500 ns);
+Tco_17 = 11.005 ns (12.500 ns);
+Tco_18 = 11.114 ns (12.500 ns);
+Tco_19 = 10.948 ns (12.500 ns);
+Tco_20 = 11.099 ns (12.500 ns);
+Tco_21 = 11.365 ns (12.500 ns);
+Tco_22 = 11.365 ns (12.500 ns);
+Tco_23 = 11.178 ns (12.500 ns);
+Tco_24 = 10.923 ns (12.500 ns);
+Tco_25 = 10.921 ns (12.500 ns);
+Tco_26 = 10.645 ns (12.500 ns);
+Tco_27 = 9.674 ns (12.500 ns);
+Tco_28 = 9.884 ns (12.500 ns);
+Tco_29 = 9.275 ns (12.500 ns);
+Tco_30 = 9.797 ns (12.500 ns);
+Tco_31 = 9.674 ns (12.500 ns);
+Tco_32 = 10.941 ns (12.500 ns);
+Tco_33 = 10.641 ns (12.500 ns);
+Tco_34 = - (-);
+Tco_35 = - (-);
+Tco_36 = - (-);
+Tco_37 = - (-);
+Tco_38 = - (-);
+Tco_39 = - (-);
+Tco_40 = - (-);
+Failed = 0 (Total 41);
+Clock_ports = 4;
+Clock_nets = 5;
+; Hold Analysis
+Period_0 = - (-);
+Period_1 = - (-);
+Period_2 = - (-);
+Period_3 = - (-);
+Tco_4 = - (-);
+Tco_5 = - (-);
+Tco_6 = - (-);
+Tco_7 = - (-);
+Tco_8 = - (-);
+Tco_9 = - (-);
+Tco_10 = - (-);
+Tco_11 = - (-);
+Tco_12 = - (-);
+Tco_13 = - (-);
+Tco_14 = - (-);
+Tco_15 = - (-);
+Tco_16 = 3.236 ns (0.000 ns);
+Tco_17 = 3.561 ns (0.000 ns);
+Tco_18 = 3.608 ns (0.000 ns);
+Tco_19 = 3.552 ns (0.000 ns);
+Tco_20 = 3.573 ns (0.000 ns);
+Tco_21 = 3.630 ns (0.000 ns);
+Tco_22 = 3.630 ns (0.000 ns);
+Tco_23 = 3.615 ns (0.000 ns);
+Tco_24 = 3.527 ns (0.000 ns);
+Tco_25 = 3.549 ns (0.000 ns);
+Tco_26 = 3.471 ns (0.000 ns);
+Tco_27 = 3.300 ns (0.000 ns);
+Tco_28 = 3.362 ns (0.000 ns);
+Tco_29 = 3.194 ns (0.000 ns);
+Tco_30 = 3.322 ns (0.000 ns);
+Tco_31 = 3.300 ns (0.000 ns);
+Tco_32 = 3.559 ns (0.000 ns);
+Tco_33 = 3.470 ns (0.000 ns);
+Tco_34 = - (-);
+Tco_35 = - (-);
+Tco_36 = - (-);
+Tco_37 = - (-);
+Tco_38 = - (-);
+Tco_39 = - (-);
+Tco_40 = - (-);
+Failed = 0 (Total 41);
+Clock_ports = 4;
+Clock_nets = 5;
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/synthesis.log b/CPLD/LCMXO2/LCMXO2-640HC/impl1/synthesis.log
new file mode 100644
index 0000000..7c23447
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/synthesis.log
@@ -0,0 +1,271 @@
+synthesis:  version Diamond (64-bit) 3.12.0.240.2
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 17 06:19:45 2021
+
+
+Command Line:  synthesis -f RAM2GS_LCMXO2_640HC_impl1_lattice.synproj -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml 
+
+Synthesis options:
+The -a option is MachXO2.
+The -s option is 4.
+The -t option is TQFP100.
+The -d option is LCMXO2-640HC.
+Using package TQFP100.
+Using performance grade 4.
+                                                          
+
+##########################################################
+
+### Lattice Family : MachXO2
+
+### Device  : LCMXO2-640HC
+
+### Package : TQFP100
+
+### Speed   : 4
+
+##########################################################
+
+                                                          
+
+INFO - synthesis: User-Selected Strategy Settings
+Optimization goal = Balanced
+Top-level module name = RAM2GS.
+Target frequency = 200.000000 MHz.
+Maximum fanout = 1000.
+Timing path count = 3
+BRAM utilization = 100.000000 %
+DSP usage = true
+DSP utilization = 100.000000 %
+fsm_encoding_style = auto
+resolve_mixed_drivers = 0
+fix_gated_clocks = 1
+
+Mux style = Auto
+Use Carry Chain = true
+carry_chain_length = 0
+Loop Limit = 1950.
+Use IO Insertion = TRUE
+Use IO Reg = AUTO
+
+Resource Sharing = TRUE
+Propagate Constants = TRUE
+Remove Duplicate Registers = TRUE
+force_gsr = auto
+ROM style = auto
+RAM style = auto
+The -comp option is FALSE.
+The -syn option is FALSE.
+-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added)
+-p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added)
+-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1 (searchpath added)
+-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added)
+Verilog design file = C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v
+NGD file = RAM2GS_LCMXO2_640HC_impl1.ngd
+-sdc option: SDC file input not used.
+-lpf option: Output file option is ON.
+Hardtimer checking is enabled (default). The -dt option is not used.
+The -r option is OFF. [ Remove LOC Properties is OFF. ]
+Technology check ok...
+
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
+Compile design.
+Compile Design Begin
+Analyzing Verilog file c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v. VERI-1482
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
+Top module name (Verilog): RAM2GS
+INFO - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(1): compiling module RAM2GS. VERI-1018
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123): expression size 32 truncated to fit in target size 2. VERI-1209
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128): expression size 32 truncated to fit in target size 18. VERI-1209
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255): expression size 32 truncated to fit in target size 4. VERI-1209
+INFO - synthesis: C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1800): compiling module EFB. VERI-1018
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(348): input port PLL0DATI7 is not connected on this instance. VDB-1013
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+Loading device for application map from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Top-level module name = RAM2GS.
+######## Missing driver on net n1128. Patching with GND.
+######## Missing driver on net n1132. Patching with GND.
+######## Missing driver on net n1133. Patching with GND.
+######## Missing driver on net n1134. Patching with GND.
+######## Missing driver on net n1135. Patching with GND.
+######## Missing driver on net n1131. Patching with GND.
+######## Missing driver on net n1130. Patching with GND.
+######## Missing driver on net n1136. Patching with GND.
+######## Missing driver on net n1137. Patching with GND.
+######## Missing driver on net n1138. Patching with GND.
+######## Missing driver on net n1139. Patching with GND.
+######## Missing driver on net n1140. Patching with GND.
+######## Missing driver on net n1141. Patching with GND.
+######## Missing driver on net n1142. Patching with GND.
+######## Missing driver on net n1143. Patching with GND.
+######## Missing driver on net n1144. Patching with GND.
+######## Missing driver on net n1145. Patching with GND.
+######## Missing driver on net n1146. Patching with GND.
+######## Missing driver on net n1147. Patching with GND.
+######## Missing driver on net n1148. Patching with GND.
+######## Missing driver on net n1129. Patching with GND.
+######## Missing driver on net n1149. Patching with GND.
+######## Missing driver on net n1150. Patching with GND.
+######## Missing driver on net n1151. Patching with GND.
+######## Missing driver on net n1152. Patching with GND.
+######## Missing driver on net n1153. Patching with GND.
+######## Missing driver on net n1154. Patching with GND.
+######## Missing driver on net n1155. Patching with GND.
+######## Missing driver on net n1156. Patching with GND.
+######## Missing driver on net n1157. Patching with GND.
+INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 0000 -> 0000000000000001
+
+ 0001 -> 0000000000000010
+
+ 0010 -> 0000000000000100
+
+ 0011 -> 0000000000001000
+
+ 0100 -> 0000000000010000
+
+ 0101 -> 0000000000100000
+
+ 0110 -> 0000000001000000
+
+ 0111 -> 0000000010000000
+
+ 1000 -> 0000000100000000
+
+ 1001 -> 0000001000000000
+
+ 1010 -> 0000010000000000
+
+ 1011 -> 0000100000000000
+
+ 1100 -> 0001000000000000
+
+ 1101 -> 0010000000000000
+
+ 1110 -> 0100000000000000
+
+ 1111 -> 1000000000000000
+
+INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 00 -> 0001
+
+ 01 -> 0010
+
+ 10 -> 0100
+
+ 11 -> 1000
+
+
+
+
+GSR will not be inferred because no asynchronous signal was found in the netlist.
+WARNING - synthesis: Initial value found on instance C1Submitted_542 will be ignored.
+Applying 200.000000 MHz constraint to all clocks
+
+WARNING - synthesis: No user .sdc file.
+Results of NGD DRC are available in RAM2GS_drc.log.
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+All blocks are expanded and NGD expansion is successful.
+Writing NGD file RAM2GS_LCMXO2_640HC_impl1.ngd.
+
+################### Begin Area Report (RAM2GS)######################
+Number of register bits => 119 of 877 (13 % )
+BB => 8
+CCU2D => 10
+EFB => 1
+FD1P3AX => 30
+FD1P3AY => 4
+FD1P3IX => 3
+FD1S3AX => 64
+FD1S3IX => 14
+FD1S3JX => 4
+GSR => 1
+IB => 25
+INV => 3
+LUT4 => 236
+OB => 30
+PFUMX => 16
+################### End Area Report ##################
+
+################### Begin BlackBox Report ######################
+TSALL => 1
+################### End BlackBox Report ##################
+
+################### Begin Clock Report ######################
+Clock Nets
+Number of Clocks: 5
+  Net : RCLK_c, loads : 79
+  Net : PHI2_c, loads : 11
+  Net : nCRAS_c, loads : 2
+  Net : nCCAS_c, loads : 2
+  Net : wb_clk, loads : 1
+Clock Enable Nets
+Number of Clock Enables: 14
+Top 10 highest fanout Clock Enables:
+  Net : RCLK_c_enable_27, loads : 16
+  Net : RCLK_c_enable_20, loads : 4
+  Net : RCLK_c_enable_25, loads : 2
+  Net : RCLK_c_enable_24, loads : 2
+  Net : RCLK_c_enable_29, loads : 2
+  Net : PHI2_N_151_enable_5, loads : 2
+  Net : PHI2_N_151_enable_3, loads : 2
+  Net : PHI2_N_151_enable_1, loads : 1
+  Net : Ready_N_280, loads : 1
+  Net : PHI2_N_151_enable_6, loads : 1
+Highest fanout non-clock nets
+Top 10 highest fanout non-clock nets:
+  Net : InitReady, loads : 36
+  Net : FS_11, loads : 32
+  Net : FS_10, loads : 32
+  Net : FS_9, loads : 26
+  Net : FS_7, loads : 25
+  Net : FS_8, loads : 23
+  Net : FS_6, loads : 21
+  Net : FS_5, loads : 21
+  Net : FS_12, loads : 20
+  Net : CmdUFMShift, loads : 16
+################### End Clock Report ##################
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk3 [get_nets PHI2_c]                  |  200.000 MHz|   38.150 MHz|     8 *
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk2 [get_nets nCCAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk1 [get_nets nCRAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets RCLK_c]                  |  200.000 MHz|   65.694 MHz|    10 *
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+2 constraints not met.
+
+
+Peak Memory Usage: 57.273  MB
+
+--------------------------------------------------------------
+Elapsed CPU time for LSE flow : 0.952  secs
+--------------------------------------------------------------
diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/synthesis_lse.html b/CPLD/LCMXO2/LCMXO2-640HC/impl1/synthesis_lse.html
new file mode 100644
index 0000000..14e4497
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/synthesis_lse.html
@@ -0,0 +1,336 @@
+
+Synthesis and Ngdbuild Report
+
+
+
    Synthesis and Ngdbuild  Report
+synthesis:  version Diamond (64-bit) 3.12.0.240.2
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 17 06:19:45 2021
+
+
+Command Line:  synthesis -f RAM2GS_LCMXO2_640HC_impl1_lattice.synproj -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml 
+
+Synthesis options:
+The -a option is MachXO2.
+The -s option is 4.
+The -t option is TQFP100.
+The -d option is LCMXO2-640HC.
+Using package TQFP100.
+Using performance grade 4.
+                                                          
+
+##########################################################
+
+### Lattice Family : MachXO2
+
+### Device  : LCMXO2-640HC
+
+### Package : TQFP100
+
+### Speed   : 4
+
+##########################################################
+
+                                                          
+
+INFO - synthesis: User-Selected Strategy Settings
+Optimization goal = Balanced
+Top-level module name = RAM2GS.
+Target frequency = 200.000000 MHz.
+Maximum fanout = 1000.
+Timing path count = 3
+BRAM utilization = 100.000000 %
+DSP usage = true
+DSP utilization = 100.000000 %
+fsm_encoding_style = auto
+resolve_mixed_drivers = 0
+fix_gated_clocks = 1
+
+Mux style = Auto
+Use Carry Chain = true
+carry_chain_length = 0
+Loop Limit = 1950.
+Use IO Insertion = TRUE
+Use IO Reg = AUTO
+
+Resource Sharing = TRUE
+Propagate Constants = TRUE
+Remove Duplicate Registers = TRUE
+force_gsr = auto
+ROM style = auto
+RAM style = auto
+The -comp option is FALSE.
+The -syn option is FALSE.
+-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added)
+-p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added)
+-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1 (searchpath added)
+-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added)
+Verilog design file = C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v
+NGD file = RAM2GS_LCMXO2_640HC_impl1.ngd
+-sdc option: SDC file input not used.
+-lpf option: Output file option is ON.
+Hardtimer checking is enabled (default). The -dt option is not used.
+The -r option is OFF. [ Remove LOC Properties is OFF. ]
+Technology check ok...
+
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
+Compile design.
+Compile Design Begin
+Analyzing Verilog file c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v. VERI-1482
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
+Top module name (Verilog): RAM2GS
+INFO - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(1): compiling module RAM2GS. VERI-1018
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123): expression size 32 truncated to fit in target size 2. VERI-1209
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128): expression size 32 truncated to fit in target size 18. VERI-1209
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255): expression size 32 truncated to fit in target size 4. VERI-1209
+INFO - synthesis: C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1800): compiling module EFB. VERI-1018
+WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(348): input port PLL0DATI7 is not connected on this instance. VDB-1013
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+Loading device for application map from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Top-level module name = RAM2GS.
+######## Missing driver on net n1128. Patching with GND.
+######## Missing driver on net n1132. Patching with GND.
+######## Missing driver on net n1133. Patching with GND.
+######## Missing driver on net n1134. Patching with GND.
+######## Missing driver on net n1135. Patching with GND.
+######## Missing driver on net n1131. Patching with GND.
+######## Missing driver on net n1130. Patching with GND.
+######## Missing driver on net n1136. Patching with GND.
+######## Missing driver on net n1137. Patching with GND.
+######## Missing driver on net n1138. Patching with GND.
+######## Missing driver on net n1139. Patching with GND.
+######## Missing driver on net n1140. Patching with GND.
+######## Missing driver on net n1141. Patching with GND.
+######## Missing driver on net n1142. Patching with GND.
+######## Missing driver on net n1143. Patching with GND.
+######## Missing driver on net n1144. Patching with GND.
+######## Missing driver on net n1145. Patching with GND.
+######## Missing driver on net n1146. Patching with GND.
+######## Missing driver on net n1147. Patching with GND.
+######## Missing driver on net n1148. Patching with GND.
+######## Missing driver on net n1129. Patching with GND.
+######## Missing driver on net n1149. Patching with GND.
+######## Missing driver on net n1150. Patching with GND.
+######## Missing driver on net n1151. Patching with GND.
+######## Missing driver on net n1152. Patching with GND.
+######## Missing driver on net n1153. Patching with GND.
+######## Missing driver on net n1154. Patching with GND.
+######## Missing driver on net n1155. Patching with GND.
+######## Missing driver on net n1156. Patching with GND.
+######## Missing driver on net n1157. Patching with GND.
+INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 0000 -> 0000000000000001
+
+ 0001 -> 0000000000000010
+
+ 0010 -> 0000000000000100
+
+ 0011 -> 0000000000001000
+
+ 0100 -> 0000000000010000
+
+ 0101 -> 0000000000100000
+
+ 0110 -> 0000000001000000
+
+ 0111 -> 0000000010000000
+
+ 1000 -> 0000000100000000
+
+ 1001 -> 0000001000000000
+
+ 1010 -> 0000010000000000
+
+ 1011 -> 0000100000000000
+
+ 1100 -> 0001000000000000
+
+ 1101 -> 0010000000000000
+
+ 1110 -> 0100000000000000
+
+ 1111 -> 1000000000000000
+
+INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 00 -> 0001
+
+ 01 -> 0010
+
+ 10 -> 0100
+
+ 11 -> 1000
+
+
+
+
+GSR will not be inferred because no asynchronous signal was found in the netlist.
+WARNING - synthesis: Initial value found on instance C1Submitted_542 will be ignored.
+Applying 200.000000 MHz constraint to all clocks
+
+WARNING - synthesis: No user .sdc file.
+Results of NGD DRC are available in RAM2GS_drc.log.
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+All blocks are expanded and NGD expansion is successful.
+Writing NGD file RAM2GS_LCMXO2_640HC_impl1.ngd.
+
+################### Begin Area Report (RAM2GS)######################
+Number of register bits => 119 of 877 (13 % )
+BB => 8
+CCU2D => 10
+EFB => 1
+FD1P3AX => 30
+FD1P3AY => 4
+FD1P3IX => 3
+FD1S3AX => 64
+FD1S3IX => 14
+FD1S3JX => 4
+GSR => 1
+IB => 25
+INV => 3
+LUT4 => 236
+OB => 30
+PFUMX => 16
+################### End Area Report ##################
+
+################### Begin BlackBox Report ######################
+TSALL => 1
+################### End BlackBox Report ##################
+
+################### Begin Clock Report ######################
+Clock Nets
+Number of Clocks: 5
+  Net : RCLK_c, loads : 79
+  Net : PHI2_c, loads : 11
+  Net : nCRAS_c, loads : 2
+  Net : nCCAS_c, loads : 2
+  Net : wb_clk, loads : 1
+Clock Enable Nets
+Number of Clock Enables: 14
+Top 10 highest fanout Clock Enables:
+  Net : RCLK_c_enable_27, loads : 16
+  Net : RCLK_c_enable_20, loads : 4
+  Net : RCLK_c_enable_25, loads : 2
+  Net : RCLK_c_enable_24, loads : 2
+  Net : RCLK_c_enable_29, loads : 2
+  Net : PHI2_N_151_enable_5, loads : 2
+  Net : PHI2_N_151_enable_3, loads : 2
+  Net : PHI2_N_151_enable_1, loads : 1
+  Net : Ready_N_280, loads : 1
+  Net : PHI2_N_151_enable_6, loads : 1
+Highest fanout non-clock nets
+Top 10 highest fanout non-clock nets:
+  Net : InitReady, loads : 36
+  Net : FS_11, loads : 32
+  Net : FS_10, loads : 32
+  Net : FS_9, loads : 26
+  Net : FS_7, loads : 25
+  Net : FS_8, loads : 23
+  Net : FS_6, loads : 21
+  Net : FS_5, loads : 21
+  Net : FS_12, loads : 20
+  Net : CmdUFMShift, loads : 16
+################### End Clock Report ##################
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk3 [get_nets PHI2_c]                  |  200.000 MHz|   38.150 MHz|     8 *
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk2 [get_nets nCCAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk1 [get_nets nCRAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets RCLK_c]                  |  200.000 MHz|   65.694 MHz|    10 *
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+2 constraints not met.
+
+
+Peak Memory Usage: 57.273  MB
+
+--------------------------------------------------------------
+Elapsed CPU time for LSE flow : 0.952  secs
+--------------------------------------------------------------
+
+
+
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diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/xxx_lse_cp_file_list b/CPLD/LCMXO2/LCMXO2-640HC/impl1/xxx_lse_cp_file_list
new file mode 100644
index 0000000..b0c79e4
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/impl1/xxx_lse_cp_file_list
@@ -0,0 +1,350 @@
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diff --git a/CPLD/LCMXO2/LCMXO2-640HC/impl1/xxx_lse_sign_file b/CPLD/LCMXO2/LCMXO2-640HC/impl1/xxx_lse_sign_file
new file mode 100644
index 0000000..ca7af8d
--- /dev/null
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diff --git a/CPLD/LCMXO2/LCMXO2-640HC/msg_file.log b/CPLD/LCMXO2/LCMXO2-640HC/msg_file.log
new file mode 100644
index 0000000..e93ec92
--- /dev/null
+++ b/CPLD/LCMXO2/LCMXO2-640HC/msg_file.log
@@ -0,0 +1,29 @@
+SCUBA, Version Diamond (64-bit) 3.12.0.240.2
+Tue Aug 17 05:48:29 2021
+  
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+  
+BEGIN SCUBA Module Synthesis
+  
+    Issued command   : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n EFB -lang verilog -synth lse -bus_exp 7 -bb -type efb -arch xo2c00 -freq 16 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640 
+    Circuit name     : EFB
+    Module type      : efb
+    Module Version   : 1.2
+    Ports            : 
+    Inputs       : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0]
+    Outputs      : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq
+    I/O buffer       : not inserted
+    EDIF output      : EFB.edn
+    Verilog output   : EFB.v
+    Verilog template : EFB_tmpl.v
+    Verilog purpose  : for synthesis and simulation
+    Bus notation     : big endian
+    Report output    : EFB.srp
+    Estimated Resource Usage:
+  
+END   SCUBA Module Synthesis
+
diff --git a/CPLD/LCMXO2/RAM2GS-LCMXO2.v b/CPLD/LCMXO2/RAM2GS-LCMXO2.v
new file mode 100644
index 0000000..48ace8c
--- /dev/null
+++ b/CPLD/LCMXO2/RAM2GS-LCMXO2.v
@@ -0,0 +1,731 @@
+module RAM2GS(PHI2, MAin, CROW, Din, Dout,
+			  nCCAS, nCRAS, nFWE, LED,
+			  RBA, RA, RD, nRCS, RCLK, RCKE,
+			  nRWE, nRRAS, nRCAS, RDQMH, RDQML);
+
+	/* 65816 Phase 2 Clock */
+	input PHI2;
+
+	/* Activity LED */
+	reg LEDEN = 0;
+	output LED;
+	assign LED = ~(~nCRAS &&  LEDEN);
+
+	/* Async. DRAM Control Inputs */
+	input nCCAS, nCRAS;
+
+	/* Synchronized PHI2 and DRAM signals */
+	reg PHI2r, PHI2r2, PHI2r3;
+	reg RASr, RASr2, RASr3;
+	reg CASr, CASr2, CASr3;
+	reg FWEr;
+	reg CBR;
+
+	/* 65816 Data */
+	input [7:0] Din;
+	output [7:0] Dout;
+	assign Dout[7:0] = RD[7:0];
+
+	/* Latched 65816 Bank Address */
+	reg [7:0] Bank;
+
+	/* Async. DRAM Address Bus */
+	input [1:0] CROW;
+	input [9:0] MAin;
+	input nFWE;
+	reg n8MEGEN = 0;
+	reg XOR8MEG = 0;
+	
+	/* SDRAM Clock */
+	input RCLK;
+	
+	/* SDRAM */
+	reg RCKEEN;
+	output reg RCKE = 0;
+	output reg nRCS = 1, nRRAS = 1, nRCAS = 1, nRWE = 1;
+	output reg [1:0] RBA;
+	reg nRowColSel;
+	reg RA11;
+	reg RA10;
+	reg [9:0] RowA;
+	output [11:0] RA;
+	assign RA[11] = RA11;
+	assign RA[10] = RA10;
+	assign RA[9:0] = ~nRowColSel ? RowA[9:0] : MAin[9:0];
+	output RDQML, RDQMH;
+	assign RDQML = ~nRowColSel ? 1'b1 : ~MAin[9];
+	assign RDQMH = ~nRowColSel ? 1'b1 :  MAin[9];
+	reg [7:0] WRD;
+	inout [7:0] RD = (~nCCAS & ~nFWE) ? WRD[7:0] : 8'bZ;
+
+	/* UFM Command Interface */
+	reg C1Submitted = 0;
+	reg ADSubmitted = 0;
+	reg CmdEnable = 0;
+	reg CmdSubmitted = 0;
+	reg CmdLEDEN = 0;
+	reg Cmdn8MEGEN = 0;
+	reg CmdUFMData = 0;
+	reg CmdUFMShift = 0;
+	wire ADWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFF & ~nFWE;
+	wire C1WR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFE & ~nFWE;
+	wire CMDWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFD & ~nFWE;
+	
+	/* State Counters */
+	reg InitReady = 0; // 1 if ready for init sequence
+	reg Ready = 0; // 1 if done with init sequence
+	reg [1:0] S = 0; // post-RAS State counter
+	reg [17:0] FS = 0; // Fast init state counter
+	reg [3:0] IS = 0; // Init state counter
+	reg WriteDone;
+	
+	/* Synchronize PHI2, RAS, CAS */
+	always @(posedge RCLK) begin
+		PHI2r <= PHI2; PHI2r2 <= PHI2r; PHI2r3 <= PHI2r2;
+		RASr <= ~nCRAS; RASr2 <= RASr; RASr3 <= RASr2;
+		CASr <= ~nCCAS; CASr2 <= CASr; CASr3 <= CASr2;
+	end
+	
+	/* Latch 65816 bank when PHI2 rises */
+	always @(posedge PHI2) begin
+		if (Ready) RA11 <= (Din[6] & ~n8MEGEN) ^ XOR8MEG; // Set RA11
+		else RA11 <= 1'b0; // Reserved in mode register
+		Bank[7:0] <= Din[7:0]; // Latch bank
+	end
+	
+	/* Latch bank address, row address, WE, and CAS when RAS falls */
+	always @(negedge nCRAS) begin
+		if (Ready) begin
+			RBA[1:0] <= CROW[1:0];
+			RowA[9:0] <= MAin[9:0];
+		end else begin
+			RBA[1:0] <= 2'b00;		// Reserved in mode register
+			RowA[9] <= 1'b1;		// "1" for single write mode
+			RowA[8] <= 1'b0;		// Reserved
+			RowA[7] <= 1'b0;		// "0" for not test mode
+			RowA[6:4] <= 3'b010;	// "2" for CAS latency 2
+			RowA[3] <= 1'b0;		// "0" for sequential burst (not used)
+			RowA[2:0] <= 3'b000;	// "0" for burst length 1 (no burst)
+		end
+		FWEr <= ~nFWE;
+		CBR <= ~nCCAS;
+	end
+
+	/* Latch write data when CAS falls */
+	always @(negedge nCCAS) begin
+		WRD[7:0] <= Din[7:0];
+	end
+
+	/* State counter from RAS */
+	always @(posedge RCLK) begin
+		if (~RASr2) S <= 0;
+		else if (S==2'h3) S <= 2'h3;
+		else S <= S+1;
+	end
+	/* Init state counter */
+	always @(posedge RCLK) begin
+		// Wait ~4.178ms (at 62.5 MHz) before starting init sequence
+		FS <= FS+1;
+		if (FS[17:10] == 8'hFF) InitReady <= 1'b1;
+	end
+
+	/* SDRAM CKE */
+	always @(posedge RCLK) begin
+		// Only 1 LUT4 allowed for this function!
+		RCKE <= ((RASr | RASr2) & RCKEEN) | (~RASr2 & RASr3);
+	end
+
+	/* SDRAM command */
+	always @(posedge RCLK) begin
+		if (Ready) begin
+			if (S==0) begin
+				if (RASr2) begin
+					if (CBR) begin
+						// AREF
+						nRCS <= 1'b0;
+						nRRAS <= 1'b0;
+						nRCAS <= 1'b0;
+						nRWE <= 1'b1;
+						RA10 <= 1'b1; // RA10 is don't care
+					end else begin
+						// ACT
+						nRCS <= 1'b0;
+						nRRAS <= 1'b0;
+						nRCAS <= 1'b1;
+						nRWE <= 1'b1;
+						RA10 <= 1'b1; // Bank RA10 consistently "1"
+					end
+					// Enable clock only for reads
+					RCKEEN <= ~CBR & ~FWEr;
+				end else if (RCKE) begin
+					// PCall
+					nRCS <= 1'b0;
+					nRRAS <= 1'b0;
+					nRCAS <= 1'b1;
+					nRWE <= 1'b0;
+					RA10 <= 1'b1; // "all"
+					RCKEEN <= 1'b1;
+				end else begin
+					// NOP
+					nRCS <= 1'b1;
+					nRRAS <= 1'b1;
+					nRCAS <= 1'b1;
+					nRWE <= 1'b1;
+					RA10 <= 1'b1; // RA10 is don't care
+					RCKEEN <= 1'b1;
+				end
+				nRowColSel <= 1'b0; // Select registered row addres
+			end else if (S==1) begin
+				// NOP
+				nRCS <= 1'b1;
+				nRRAS <= 1'b1;
+				nRCAS <= 1'b1;
+				nRWE <= 1'b1;
+				RA10 <= 1'b1; // RA10 is don't care
+				nRowColSel <= 1'b1; // Select asynchronous column address
+				RCKEEN <= ~CBR; // Disable clock if refresh cycle
+			end else if (S==2) begin
+				if (~FWEr & ~CBR) begin
+					// RD
+					nRCS <= 1'b0;
+					nRRAS <= 1'b1;
+					nRCAS <= 1'b0;
+					nRWE <= 1'b1;
+					RA10 <= 1'b1; // Auto-precharge
+				end else begin
+					// NOP
+					nRCS <= 1'b1;
+					nRRAS <= 1'b1;
+					nRCAS <= 1'b1;
+					nRWE <= 1'b1;
+					RA10 <= 1'b1; // RA10 is don't care
+				end
+				nRowColSel <= 1'b1; // Select asynchronous column address
+				RCKEEN <= ~CBR & FWEr; // Enable clock only for writes
+			end else if (S==3) begin
+				if (CASr2 & ~CASr3 & ~CBR & FWEr) begin
+					// WR
+					nRCS <= 1'b0;
+					nRRAS <= 1'b1;
+					nRCAS <= 1'b0;
+					nRWE <= 1'b0;
+					RA10 <= 1'b1; // Auto-precharge
+				end else begin
+					// NOP
+					nRCS <= 1'b1;
+					nRRAS <= 1'b1;
+					nRCAS <= 1'b1;
+					nRWE <= 1'b1;
+					RA10 <= 1'b1; // RA10 is don't care
+				end
+				nRowColSel <= ~(~FWEr | CASr3 | CBR);
+				RCKEEN <= ~(~FWEr | CASr2 | CBR);
+			end
+		end else if (InitReady) begin
+			if (S==0 & RASr2) begin
+				if (IS==0) begin
+					// NOP
+					nRCS <= 1'b1;
+					nRRAS <= 1'b1;
+					nRCAS <= 1'b1;
+					nRWE <= 1'b1;
+					RA10 <= 1'b1; // RA10 is don't care
+				end else if (IS==1) begin
+					// PC all
+					nRCS <= 1'b0;
+					nRRAS <= 1'b0;
+					nRCAS <= 1'b1;
+					nRWE <= 1'b0;
+					RA10 <= 1'b1; // "all"
+				end else if (IS==9) begin
+					// Load mode register
+					nRCS <= 1'b0;
+					nRRAS <= 1'b0;
+					nRCAS <= 1'b0;
+					nRWE <= 1'b0;
+					RA10 <= 1'b0; // Reserved in mode register
+				end else begin
+					// AREF
+					nRCS <= 1'b0;
+					nRRAS <= 1'b0;
+					nRCAS <= 1'b0;
+					nRWE <= 1'b1;
+					RA10 <= 1'b1; // RA10 is don't care
+				end
+				IS <= IS+1;
+			end else begin
+				// NOP
+				nRCS <= 1'b1;
+				nRRAS <= 1'b1;
+				nRCAS <= 1'b1;
+				nRWE <= 1'b1;
+				RA10 <= 1'b1; // RA10 is don't care
+			end
+			if (S==3 & ~RASr2 & IS==15) Ready <= 1'b1;
+			nRowColSel <= 1'b0; // Select registered row address
+			RCKEEN <= 1'b1;
+		end else begin
+			// NOP
+			nRCS <= 1'b1;
+			nRRAS <= 1'b1;
+			nRCAS <= 1'b1;
+			nRWE <= 1'b1;
+			RA10 <= 1'b1; // RA10 is don't care
+			nRowColSel <= 1'b0; // Select registered row address
+			RCKEEN <= 1'b0;
+		end
+	end
+	
+	/* Submit command when PHI2 falls */
+	always @(negedge PHI2) begin
+		// Magic number check
+		if (C1WR & Din[7:0]==8'hC1) begin // "C1" magic number
+			if (ADSubmitted) begin
+				CmdEnable <= 1'b1;
+			end
+			C1Submitted <= 1'b1;
+			ADSubmitted <= 1'b0;
+		end else if (ADWR & Din[7:0]==8'hAD) begin // "AD" magic number
+			if (C1Submitted) begin
+				CmdEnable <= 1'b1;
+			end
+			ADSubmitted <= 1'b1;
+			C1Submitted <= 1'b0;
+		end else if (C1WR | ADWR) begin // wrong magic number submitted
+			CmdEnable <= 1'b0;
+			C1Submitted <= 1'b0;
+			ADSubmitted <= 1'b0;
+		end else if (CMDWR) CmdEnable <= 1'b0;
+
+		// Submit command
+		if (CMDWR & CmdEnable) begin
+			if (Din[7:4]==4'h0) begin
+				XOR8MEG <= Din[0];
+			end else if (Din[7:4]==4'h1) begin
+				CmdLEDEN <= ~Din[1];
+				Cmdn8MEGEN <= ~Din[0];
+			end else if (Din[7:4]==4'h3 && Din[3]) begin
+				CmdLEDEN <= LEDEN;
+				Cmdn8MEGEN <= n8MEGEN;
+				CmdUFMShift <= Din[1];
+				CmdUFMData <= Din[0];
+			end
+			CmdSubmitted <= 1;
+		end else CmdSubmitted <= 0;
+	end
+	
+	reg wb_clk;
+	reg wb_rst;
+	reg wb_cyc_stb;
+	reg wb_we;
+	reg [7:0] wb_adr;
+	reg [7:0] wb_dati;
+	wire [1:0] wb_dato;
+	
+	EFB ufmefb (
+		.WBCLKI(wb_clk),
+		.WBRSTI(wb_rst),
+		.WBCYCI(wb_cyc_stb),
+		.WBSTBI(wb_cyc_stb), 
+		.WBWEI(wb_we),
+		.WBADRI7(wb_adr[7]),
+		.WBADRI6(wb_adr[6]),
+		.WBADRI5(wb_adr[5]),
+		.WBADRI4(wb_adr[4]),
+		.WBADRI3(wb_adr[3]),
+		.WBADRI2(wb_adr[2]),
+		.WBADRI1(wb_adr[1]),
+		.WBADRI0(wb_adr[0]),
+		.WBDATI7(wb_dati[7]),
+		.WBDATI6(wb_dati[6]),
+		.WBDATI5(wb_dati[5]),
+		.WBDATI4(wb_dati[4]),
+		.WBDATI3(wb_dati[3]),
+		.WBDATI2(wb_dati[2]),
+		.WBDATI1(wb_dati[1]),
+		.WBDATI0(wb_dati[0]),
+		.WBDATO1(wb_dato[1]),
+		.WBDATO0(wb_dato[0]));
+
+	/* UFM Control */
+	always @(posedge RCLK) begin
+		if (~InitReady && FS[17:10]==8'h00) begin
+			wb_clk <= 1'b0;
+			wb_rst <= ~FS[9];
+			wb_cyc_stb <= 1'b0;
+			wb_we <= 1'b0;
+			wb_adr[7:0] <= 8'h00;
+			wb_dati[7:0] <= 8'h00;
+		end else if (~InitReady && FS[17:10]==8'h01) begin
+			wb_clk <= FS[2];
+			wb_rst <= 1'b0;
+			case (FS[9:5])
+				5'h00: begin // Open frame
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h70;
+					wb_dati[7:0] <= 8'h80;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h01: begin // Enable configuration interface - command
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h74;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h02: begin // Enable configuration interface - operand 1/3
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h08;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h03: begin // Enable configuration interface - operand 2/3
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h04: begin // Enable configuration interface - operand 3/3
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h1F: begin // Close frame
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h70;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end default: begin
+					wb_we <= 1'b0;
+					wb_adr[7:0] <= 8'h00;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= 1'b0;
+				end
+			endcase
+		end else if (~InitReady && FS[17:10]==8'h02) begin
+			wb_clk <= FS[2];
+			wb_rst <= 1'b0;
+			case (FS[9:5])
+				5'h00: begin // Open frame
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h70;
+					wb_dati[7:0] <= 8'h80;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h01: begin // Poll status register - command
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h3C;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h02: begin // Poll status register - operand 1/3
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h03: begin // Poll status register - operand 2/3
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h04: begin // Poll status register - operand 3/3
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h05: begin // Read status register 1/4
+					wb_we <= 1'b0;
+					wb_adr[7:0] <= 8'h73;
+					wb_dati[7:0] <= 8'h3C;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h06: begin // Read status register 2/4
+					wb_we <= 1'b0;
+					wb_adr[7:0] <= 8'h73;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h07: begin // Read status register 3/4
+					wb_we <= 1'b0;
+					wb_adr[7:0] <= 8'h73;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h08: begin // Read status register 4/4
+					wb_we <= 1'b0;
+					wb_adr[7:0] <= 8'h73;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h1F: begin // Close frame
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h70;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end default: begin
+					wb_we <= 1'b0;
+					wb_adr[7:0] <= 8'h00;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= 1'b0;
+				end
+			endcase
+		end else if (~InitReady && FS[17:10]==8'h03) begin
+			wb_clk <= FS[2];
+			wb_rst <= 1'b0;
+			case (FS[9:5])
+				5'h00: begin // Open frame
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h70;
+					wb_dati[7:0] <= 8'h80;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h01: begin // Set UFM address - command
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'hB4;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h02: begin // Set UFM address - operand 1/3
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h03: begin // Set UFM address - operand 2/3
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h04: begin // Set UFM address - operand 3/3
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h05: begin // Set UFM address - data 1/4
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h40;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h06: begin // Set UFM address - data 2/4
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h07: begin // Set UFM address - data 3/4
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h08: begin // Set UFM address - data 4/4
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h01;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h1F: begin // Close frame
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h70;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end default: begin
+					wb_we <= 1'b0;
+					wb_adr[7:0] <= 8'h00;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= 1'b0;
+				end
+			endcase
+		end else if (~InitReady && FS[17:10]==8'h04) begin
+			wb_clk <= FS[2];
+			wb_rst <= 1'b0;
+			case (FS[9:5])
+				5'h00: begin // Open frame
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h70;
+					wb_dati[7:0] <= 8'h80;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h01: begin // Read UFM page - command
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'hCA;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h02: begin // Read UFM page - operand 1/3
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h10;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h03: begin // Read UFM page - operand 2/3
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h04: begin // Read UFM page - operand 3/3
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h01;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h05: begin // Read UFM page - data 1/16
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+					
+					if (FS[4:0]==5'h0C) begin
+						LEDEN <= wb_dato[1];
+						n8MEGEN <= wb_dato[0];
+					end
+				end 5'h06: begin // Read UFM page - data 2/16
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h07: begin // Read UFM page - data 3/16
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h08: begin // Read UFM page - data 4/16
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h09: begin // Read UFM page - data 5/16
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h0A: begin // Read UFM page - data 6/16
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h0B: begin // Read UFM page - data 7/16
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h0C: begin // Read UFM page - data 8/16
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h0D: begin // Read UFM page - data 9/16
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h0E: begin // Read UFM page - data 10/16
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h0F: begin // Read UFM page - data 11/16
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h10: begin // Read UFM page - data 12/16
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h11: begin // Read UFM page - data 13/16
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h12: begin // Read UFM page - data 14/16
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h13: begin // Read UFM page - data 15/16
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h14: begin // Read UFM page - data 16/16
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h1F: begin // Close frame
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h70;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end default: begin
+					wb_we <= 1'b0;
+					wb_adr[7:0] <= 8'h00;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= 1'b0;
+				end
+			endcase
+		end else if (~InitReady && FS[17:10]==8'h05) begin
+			wb_clk <= FS[2];
+			wb_rst <= 1'b0;
+			case (FS[9:5])
+				5'h00: begin // Open frame
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h70;
+					wb_dati[7:0] <= 8'h80;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h01: begin // Disable configuration interface - command
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h26;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h02: begin // Disable configuration interface - operand 1/2
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h03: begin // Disable configuration interface - operand 2/2
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h1F: begin // Close frame
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h70;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end default: begin
+					wb_we <= 1'b0;
+					wb_adr[7:0] <= 8'h00;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= 1'b0;
+				end
+			endcase
+		end else if (~InitReady && FS[17:10]==8'h06) begin
+			wb_clk <= FS[2];
+			wb_rst <= 1'b0;
+			case (FS[9:5])
+				5'h00: begin // Open frame
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h70;
+					wb_dati[7:0] <= 8'h80;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h01: begin // Disable configuration interface - command
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h71;
+					wb_dati[7:0] <= 8'hFF;
+					wb_cyc_stb <= ~FS[4];
+				end 5'h1F: begin // Close frame
+					wb_we <= 1'b1;
+					wb_adr[7:0] <= 8'h70;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= ~FS[4];
+				end default: begin
+					wb_we <= 1'b0;
+					wb_adr[7:0] <= 8'h00;
+					wb_dati[7:0] <= 8'h00;
+					wb_cyc_stb <= 1'b0;
+				end
+			endcase
+		end else if (~InitReady) begin
+			wb_clk <= 1'b0;
+			wb_rst <= 1'b0;
+			wb_cyc_stb <= 1'b0;
+			wb_we <= 1'b0;
+			wb_adr[7:0] <= 8'h00;
+			wb_dati[7:0] <= 8'h00;
+		end else if (~PHI2r2 & PHI2r3 & CmdSubmitted) begin
+			// Set user command signals after PHI2 falls
+			// CmdnLEDEN, Cmdn8MEGEN, CmdUFMShift, CmdUFMData
+			LEDEN <= CmdLEDEN;
+			n8MEGEN <= Cmdn8MEGEN;
+			if (CmdUFMShift) begin
+				wb_adr[7:0] <= { wb_adr[6:0], wb_dati[7] };
+				wb_dati[7:0] <= { wb_dati[6:0], wb_we };
+				wb_we <= wb_cyc_stb;
+				wb_cyc_stb <= CmdUFMData;
+				wb_clk <= 1'b0;
+			end else wb_clk <= 1'b1;
+		end
+	end
+endmodule
diff --git a/CPLD/MAX/MAXII/RAM2GS.qws b/CPLD/MAX/MAXII/RAM2GS.qws
index b0761a5349eac02c3f91222206380c2ce3b47e72..4620ebd54aa138f6cfdb41c02b9004f436262c7c 100644
GIT binary patch
literal 818
zcmc(dyG{a85QcwH5=tv83kqY12^Wdtr4sR0U}8WMJG1PrN)VU8q9(={@YQT=eFq;w
z#cxiQh8PoVJSTJJ_Me@9=InM}leM60c^WF#x$YEcpe|mYn6D5}3W-(MmP$G$6M`6G
z?}EKdw6BqRWNtuO?m!)^L!xcGrfND;g=h<}u46U0T_RS~*;KxeM2osjYB%(t4XvuG
zb#$Oj&H~!UuVSsR1C_Bn&cJ2MSQW(61>4gaJOcPV{#P$H#MBeV7}19vQl>@l4P!Qu
zEIRw1I4Gr&C8ib9MXa25m}tz7m~>7j=!n;A)8W9N8na9%Yfk%I4QbsVzPjIm95pWF
zd8ZC9di9q|_FobRmX0M>O2=i-MiX*5Vrq^f6>TIcQr%E;>(O90%pM8?<*El
YuP@K;LsrABOp`7$6Ay-;Cg!L01?`7}%m4rY

delta 246
zcmdnQ_LOCUc0B_SFaog;Lp4JRgDHav5QFFxhBO9U24f)Kh#?ioG6cdDAl79_WH4Z`
z0J98$EF&OJ1gcE~k|scC2$ZY+4+LO?R{}{e>o3$A5T(Gt!1Ut}6NvfS9!M%Nga9=s
zG2{R(Qeemj8l}MC45afIN`N9DvKZt-AYl3dBw`rArnBgS_>;RCPjZ7~Re*-%GZaj|
Z$YeBm4^zDOcaVAz04n|m!XP#i0|3TcGROb`

diff --git a/CPLD/MAX/MAXII/db/RAM2GS.db_info b/CPLD/MAX/MAXII/db/RAM2GS.db_info
index c0baa44..5d4d051 100644
--- a/CPLD/MAX/MAXII/db/RAM2GS.db_info
+++ b/CPLD/MAX/MAXII/db/RAM2GS.db_info
@@ -1,3 +1,3 @@
 Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
 Version_Index = 302049280
-Creation_Time = Mon Aug 16 18:36:28 2021
+Creation_Time = Tue Sep 28 21:30:08 2021
diff --git a/CPLD/MAX/MAXII/db/RAM2GS.ipinfo b/CPLD/MAX/MAXII/db/RAM2GS.ipinfo
index fa2304dd52e67aba538ff1d8d0aba1434af3953a..b9c26971f85c34a6e2ceded3667f29df5e2c05c5 100644
GIT binary patch
delta 184
zcmdnU*vvE`xW1eL0uDmyP$j^BG`e$?)G#QN?4+UJ!@Bx|j|9=Hz
zQc^zY
Q`1?mJLhMq<4?v6n00~k+{{R30

delta 101
zcmZo>+Q>K|IF5q>0-B(-E|lH~r7IYJ{r~^Jo=pM7|Np;&F)1Y>B_JUo!C=4a23Ze7
g4yKLi4eJ-j?@4#qvwZ&S`aRvk9&;KwI~c*r0hz@e+5i9m

diff --git a/CPLD/MAX/MAXII/db/RAM2GS.tmw_info b/CPLD/MAX/MAXII/db/RAM2GS.tmw_info
index 162d740..16f5f5b 100644
--- a/CPLD/MAX/MAXII/db/RAM2GS.tmw_info
+++ b/CPLD/MAX/MAXII/db/RAM2GS.tmw_info
@@ -1,6 +1,6 @@
-start_full_compilation:s:00:00:09
-start_analysis_synthesis:s:00:00:02-start_full_compilation
+start_full_compilation:s
+start_analysis_synthesis:s-start_full_compilation
 start_analysis_elaboration:s-start_full_compilation
-start_fitter:s:00:00:04-start_full_compilation
-start_assembler:s:00:00:01-start_full_compilation
-start_timing_analyzer:s:00:00:02-start_full_compilation
+start_fitter:s-start_full_compilation
+start_assembler:s-start_full_compilation
+start_timing_analyzer:s-start_full_compilation
diff --git a/CPLD/MAX/RAM2GS-MAX.v b/CPLD/MAX/RAM2GS-MAX.v
index 8be9f35..b18d542 100644
--- a/CPLD/MAX/RAM2GS-MAX.v
+++ b/CPLD/MAX/RAM2GS-MAX.v
@@ -8,7 +8,8 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
 
 	/* Activity LED */
 	reg LEDEN = 0;
-	output LED = ~(~nCRAS &&  LEDEN);
+	output LED;
+	assign LED = ~(~nCRAS &&  LEDEN);
 
 	/* Async. DRAM Control Inputs */
 	input nCCAS, nCRAS;
@@ -22,7 +23,8 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
 
 	/* 65816 Data */
 	input [7:0] Din;
-	output [7:0] Dout = RD[7:0];
+	output [7:0] Dout;
+	assign Dout[7:0] = RD[7:0];
 
 	/* Latched 65816 Bank Address */
 	reg [7:0] Bank;
@@ -50,8 +52,9 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
 	assign RA[11] = RA11;
 	assign RA[10] = RA10;
 	assign RA[9:0] = ~nRowColSel ? RowA[9:0] : MAin[9:0];
-	output RDQML = ~nRowColSel ? 1'b1 : ~MAin[9];
-	output RDQMH = ~nRowColSel ? 1'b1 : MAin[9];
+	output RDQML, RDQMH;
+	assign RDQML = ~nRowColSel ? 1'b1 : ~MAin[9];
+	assign RDQMH = ~nRowColSel ? 1'b1 :  MAin[9];
 	reg [7:0] WRD;
 	inout [7:0] RD = (~nCCAS & ~nFWE) ? WRD[7:0] : 8'bZ;
 
@@ -97,6 +100,7 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
 	reg ADSubmitted = 0;
 	reg CmdEnable = 0;
 	reg CmdSubmitted = 0;
+	reg CmdLEDEN = 0;
 	reg Cmdn8MEGEN = 0;
 	reg CmdDRCLK = 0;
 	reg CmdDRDIn = 0;
@@ -339,9 +343,11 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
 			if (Din[7:4]==4'h0) begin
 				XOR8MEG <= Din[0];
 			end else if (Din[7:4]==4'h1) begin
+				CmdLEDEN <= ~Din[1];
 				Cmdn8MEGEN <= ~Din[0];
 				CmdSubmitted <= 1'b1;
-			end else if (Din[7:4]==4'h2) begin
+			end else if (Din[7:4]==4'h2 && Din[3]==1'b0) begin
+				CmdLEDEN <= LEDEN;
 				Cmdn8MEGEN <= n8MEGEN;
 				CmdUFMErase <= Din[3];
 				CmdUFMPrgm <= Din[2];

    BITGEN: Bitstream Generator Diamond (64-bit) 3.12.0.240.2
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 17 06:21:07 2021
+
+
+Command: bitgen -g RamCfg:Reset -path C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC -w -jedec -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+
+Loading design for application Bitgen from file RAM2GS_LCMXO2_640HC_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+
+Running DRC.
+DRC detected 0 errors and 0 warnings.
+Reading Preference File from RAM2GS_LCMXO2_640HC_impl1.prf.
+
+
+Preference Summary:
+
++---------------------------------+---------------------------------+
+|  Preference                     |  Current Setting                |
++---------------------------------+---------------------------------+
+|                         RamCfg  |                        Reset**  |
++---------------------------------+---------------------------------+
+|                     MCCLK_FREQ  |                         2.08**  |
++---------------------------------+---------------------------------+
+|                  CONFIG_SECURE  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                          INBUF  |                           ON**  |
++---------------------------------+---------------------------------+
+|                      JTAG_PORT  |                       ENABLE**  |
++---------------------------------+---------------------------------+
+|                       SDM_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                 SLAVE_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                MASTER_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                       I2C_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|        MUX_CONFIGURATION_PORTS  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  CONFIGURATION  |                          CFG**  |
++---------------------------------+---------------------------------+
+|                COMPRESS_CONFIG  |                           ON**  |
++---------------------------------+---------------------------------+
+|                        MY_ASSP  |                          OFF**  |
++---------------------------------+---------------------------------+
+|               ONE_TIME_PROGRAM  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                 ENABLE_TRANSFR  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  SHAREDEBRINIT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|            BACKGROUND_RECONFIG  |                          OFF**  |
++---------------------------------+---------------------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+
+Creating bit map...
+ 
+Bitstream Status: Final           Version 1.95.
+ 
+Saving bit stream in "RAM2GS_LCMXO2_640HC_impl1.jed".
+ 
+===========
+UFM Summary.
+===========
+UFM Size:        191 Pages (128*191 Bits).
+UFM Utilization: General Purpose Flash Memory.
+ 
+Available General Purpose Flash Memory:  191 Pages (Page 0 to Page 190).
+Initialized UFM Pages:                     0 Page.
+ 
+Total CPU Time: 1 secs 
+Total REAL Time: 2 secs 
+Peak Memory Usage: 245 MB
+
+
+
+
    
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+
    BITGEN: Bitstream Generator Diamond (64-bit) 3.12.0.240.2
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Mon Aug 16 21:36:33 2021
+
+
+Command: bitgen -w -g ES:No -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf 
+
+Loading design for application Bitgen from file RAM2GS_LCMXO640C_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 3
+Loading device for application Bitgen from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+
+Running DRC.
+DRC detected 0 errors and 0 warnings.
+Reading Preference File from RAM2GS_LCMXO640C_impl1.prf.
+
+
+Preference Summary:
+
++---------------------------------+---------------------------------+
+|  Preference                     |  Current Setting                |
++---------------------------------+---------------------------------+
+|                  CONFIG_SECURE  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                          INBUF  |                           ON**  |
++---------------------------------+---------------------------------+
+|                             ES  |                           No**  |
++---------------------------------+---------------------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+
+Creating bit map...
+Saving bit stream in "RAM2GS_LCMXO640C_impl1.bit".
+Total CPU Time: 0 secs 
+Total REAL Time: 0 secs 
+Peak Memory Usage: 46 MB
+
+
+
+
    
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+
    BITGEN: Bitstream Generator Diamond (64-bit) 3.12.0.240.2
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Mon Aug 16 21:36:25 2021
+
+
+Command: bitgen -w -g ES:No -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf 
+
+Loading design for application Bitgen from file RAM2GS_LCMXO256C_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: 3
+Loading device for application Bitgen from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+
+Running DRC.
+DRC detected 0 errors and 0 warnings.
+Reading Preference File from RAM2GS_LCMXO256C_impl1.prf.
+
+
+Preference Summary:
+
++---------------------------------+---------------------------------+
+|  Preference                     |  Current Setting                |
++---------------------------------+---------------------------------+
+|                  CONFIG_SECURE  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                          INBUF  |                           ON**  |
++---------------------------------+---------------------------------+
+|                             ES  |                           No**  |
++---------------------------------+---------------------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+
+Creating bit map...
+Saving bit stream in "RAM2GS_LCMXO256C_impl1.bit".
+Total CPU Time: 0 secs 
+Total REAL Time: 0 secs 
+Peak Memory Usage: 44 MB
+
+
+
+
    
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