diff --git a/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC_tcl.html b/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC_tcl.html new file mode 100644 index 0000000..f71517e --- /dev/null +++ b/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC_tcl.html @@ -0,0 +1,88 @@ + +Lattice TCL Log + + +
pn231117190458
+#Start recording tcl command: 11/17/2023 18:14:50
+#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC; Project name: RAM2GS_LCMXO2_1200HC
+prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.ldf"
+#Stop recording: 11/17/2023 19:04:58
+
+
+
+pn231118021829
+#Start recording tcl command: 11/17/2023 20:00:00
+#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC; Project name: RAM2GS_LCMXO2_1200HC
+prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.ldf"
+prj_run Export -impl impl1
+prj_run Export -impl impl1 -forceAll
+#Stop recording: 11/18/2023 02:18:29
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+
+
+pn231118021905
+#Start recording tcl command: 11/18/2023 02:18:52
+#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC; Project name: RAM2GS_LCMXO2_1200HC
+prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.ldf"
+prj_project close
+#Stop recording: 11/18/2023 02:19:05
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+ + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.alt b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.alt index 8d2aef6..e3dda9a 100644 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.alt +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.alt @@ -1,6 +1,6 @@ NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation * NOTE All Rights Reserved * -NOTE DATE CREATED: Thu Oct 19 23:51:27 2023 * +NOTE DATE CREATED: Sat Nov 18 02:06:32 2023 * NOTE DESIGN NAME: RAM2GS * NOTE DEVICE NAME: LCMXO2-1200HC-4TQFP100 * NOTE PIN ASSIGNMENTS * @@ -13,7 +13,7 @@ NOTE PINS nRCAS : 52 : out * NOTE PINS nRRAS : 54 : out * NOTE PINS nRWE : 49 : out * NOTE PINS RCKE : 53 : out * -NOTE PINS RCLKout : 62 : out * +NOTE PINS RCLKout : 60 : out * NOTE PINS RCLK : 63 : in * NOTE PINS nRCS : 57 : out * NOTE PINS RD[7] : 43 : inout * @@ -25,7 +25,7 @@ NOTE PINS RD[2] : 38 : inout * NOTE PINS RD[1] : 37 : inout * NOTE PINS RA[11] : 59 : out * NOTE PINS RA[10] : 64 : out * -NOTE PINS RA[9] : 47 : out * +NOTE PINS RA[9] : 62 : out * NOTE PINS RA[8] : 65 : out * NOTE PINS RA[7] : 75 : out * NOTE PINS RA[6] : 68 : out * @@ -35,7 +35,7 @@ NOTE PINS RA[3] : 71 : out * NOTE PINS RA[2] : 69 : out * NOTE PINS RA[1] : 67 : out * NOTE PINS RA[0] : 66 : out * -NOTE PINS RBA[1] : 60 : out * +NOTE PINS RBA[1] : 47 : out * NOTE PINS RBA[0] : 58 : out * NOTE PINS LED : 34 : out * NOTE PINS nFWE : 15 : in * diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.areasrr b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.areasrr index b08bcc1..fe69f63 100644 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.areasrr +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.areasrr @@ -1,7 +1,7 @@ ---------------------------------------------------------------------- Report for cell RAM2GS.verilog -Register bits: 110 of 1280 (9%) +Register bits: 109 of 1280 (9%) PIC Latch: 0 I/O cells: 64 Cell usage: @@ -11,7 +11,7 @@ I/O cells: 64 EFB 1 100.0 FD1P3AX 25 100.0 FD1P3IX 2 100.0 - FD1S3AX 54 100.0 + FD1S3AX 53 100.0 FD1S3IX 4 100.0 GSR 1 100.0 IB 25 100.0 @@ -22,22 +22,23 @@ I/O cells: 64 OFS1P3BX 4 100.0 OFS1P3DX 11 100.0 OFS1P3JX 1 100.0 - ORCALUT4 203 100.0 + ORCALUT4 212 100.0 + PFUMX 2 100.0 PUR 1 100.0 VHI 2 100.0 VLO 2 100.0 SUB MODULES REFB 1 100.0 - TOTAL 403 + TOTAL 413 ---------------------------------------------------------------------- Report for cell REFB.netlist Instance path: ufmefb Cell usage: cell count Res Usage(%) EFB 1 100.0 - ORCALUT4 1 0.5 + ORCALUT4 2 0.9 VHI 1 50.0 VLO 1 50.0 - TOTAL 4 + TOTAL 5 diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.bgn b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.bgn index 5381cd7..2362085 100644 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.bgn +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.bgn @@ -4,7 +4,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Thu Oct 19 23:51:23 2023 +Sat Nov 18 02:06:29 2023 Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC -w -jedec -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf @@ -82,5 +82,5 @@ Available General Purpose Flash Memory: 511 Pages (Page 0 to Page 510). Initialized UFM Pages: 321 Pages (Page 190 to Page 510). Total CPU Time: 3 secs -Total REAL Time: 4 secs -Peak Memory Usage: 275 MB +Total REAL Time: 3 secs +Peak Memory Usage: 274 MB diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.bit b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.bit index a212c27..733e4d6 100644 Binary files a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.bit and b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.bit differ diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.edi b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.edi index 61d257a..7056502 100644 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.edi +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.edi @@ -4,7 +4,7 @@ (keywordMap (keywordLevel 0)) (status (written - (timeStamp 2023 10 19 23 50 53) + (timeStamp 2023 11 18 2 5 49) (author "Synopsys, Inc.") (program "Synplify Pro" (version "R-2021.03L-SP1, mapper map202103lat, Build 070R")) ) @@ -155,6 +155,16 @@ ) ) ) + (cell PFUMX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port ALUT (direction INPUT)) + (port BLUT (direction INPUT)) + (port C0 (direction INPUT)) + (port Z (direction OUTPUT)) + ) + ) + ) (cell GSR (cellType GENERIC) (view PRIM (viewType NETLIST) (interface @@ -360,17 +370,22 @@ (port (array (rename wb_dato "wb_dato[1:0]") 2) (direction OUTPUT)) (port (array (rename wb_dati "wb_dati[7:0]") 8) (direction INPUT)) (port (array (rename wb_adr "wb_adr[7:0]") 8) (direction INPUT)) - (port (array (rename fs "FS[14:13]") 2) (direction INPUT)) + (port (array (rename fs "FS[14:12]") 3) (direction INPUT)) + (port FS_RNIF2MA_0 (direction INPUT)) + (port FS_RNIHVJI_0 (direction INPUT)) (port wb_we (direction INPUT)) (port wb_cyc_stb (direction INPUT)) (port wb_rst (direction INPUT)) (port RCLK_c (direction INPUT)) - (port g0_0_a3_1 (direction OUTPUT)) (port wb_ack (direction OUTPUT)) + (port N_4 (direction OUTPUT)) ) (contents - (instance EFBInst_0_RNI8K48 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C (!B A))")) + (instance EFBInst_0_RNISI191 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (!B !A))")) + ) + (instance EFBInst_0_RNISGNB (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B A)))")) ) (instance EFBInst_0 (viewRef verilog (cellRef EFB)) (property UFM_INIT_FILE_FORMAT (string "HEX")) @@ -426,18 +441,17 @@ ) (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT))) ) (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) - (net (rename FS_13 "FS[13]") (joined - (portRef (member fs 1)) - (portRef A (instanceRef EFBInst_0_RNI8K48)) + (net (rename FS_RNIHVJI_0 "FS_RNIHVJI[15]") (joined + (portRef FS_RNIHVJI_0) + (portRef A (instanceRef EFBInst_0_RNISI191)) )) - (net (rename FS_14 "FS[14]") (joined - (portRef (member fs 0)) - (portRef B (instanceRef EFBInst_0_RNI8K48)) + (net (rename FS_RNIF2MA_0 "FS_RNIF2MA[9]") (joined + (portRef FS_RNIF2MA_0) + (portRef B (instanceRef EFBInst_0_RNISI191)) )) - (net wb_ack (joined - (portRef WBACKO (instanceRef EFBInst_0)) - (portRef C (instanceRef EFBInst_0_RNI8K48)) - (portRef wb_ack) + (net g0_0_a3_2 (joined + (portRef Z (instanceRef EFBInst_0_RNISGNB)) + (portRef C (instanceRef EFBInst_0_RNISI191)) )) (net GND (joined (portRef Z (instanceRef GND)) @@ -471,9 +485,26 @@ (portRef PLL0DATI6 (instanceRef EFBInst_0)) (portRef PLL0DATI7 (instanceRef EFBInst_0)) )) - (net g0_0_a3_1 (joined - (portRef Z (instanceRef EFBInst_0_RNI8K48)) - (portRef g0_0_a3_1) + (net N_4 (joined + (portRef Z (instanceRef EFBInst_0_RNISI191)) + (portRef N_4) + )) + (net (rename FS_12 "FS[12]") (joined + (portRef (member fs 2)) + (portRef A (instanceRef EFBInst_0_RNISGNB)) + )) + (net (rename FS_13 "FS[13]") (joined + (portRef (member fs 1)) + (portRef B (instanceRef EFBInst_0_RNISGNB)) + )) + (net (rename FS_14 "FS[14]") (joined + (portRef (member fs 0)) + (portRef C (instanceRef EFBInst_0_RNISGNB)) + )) + (net wb_ack (joined + (portRef WBACKO (instanceRef EFBInst_0)) + (portRef D (instanceRef EFBInst_0_RNISGNB)) + (portRef wb_ack) )) (net RCLK_c (joined (portRef RCLK_c) @@ -785,37 +816,75 @@ (instance RA10_0io_RNO (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) (instance nCCAS_pad_RNISUR8 (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) (instance RASr_RNO (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) - (instance nFWE_pad_RNI420B (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) - (instance (rename S_RNICVV51_0 "S_RNICVV51[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B A))")) + (instance FWEr_RNO (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) + (instance (rename wb_dati_5_1_iv_0_a2_0_RNO_7 "wb_dati_5_1_iv_0_a2_0_RNO[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B A))")) ) (instance C1Submitted_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (B+A)+D (!C A+C (B+A)))")) ) - (instance (rename wb_dati_5_1_iv_0_1_RNO_7 "wb_dati_5_1_iv_0_1_RNO[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B+A)+C (!B !A+B A))")) + (instance (rename FS_RNIJO0F_12 "FS_RNIJO0F[12]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B !A))")) ) - (instance (rename wb_dati_5_1_iv_0_0_RNO_7 "wb_dati_5_1_iv_0_0_RNO[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C (!B A))")) + (instance (rename S_RNICVV51_1 "S_RNICVV51[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B A))")) ) - (instance (rename FS_RNIHVJI_15 "FS_RNIHVJI[15]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance nRCAS_0io_RNO_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B !A)+C !A)")) + ) + (instance (rename wb_adr_5_i_0_2_RNO_0_0 "wb_adr_5_i_0_2_RNO_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B A)))")) + ) + (instance (rename FS_RNIOVGI_9 "FS_RNIOVGI[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B !A)))")) + ) + (instance (rename FS_RNIHVJI_0_15 "FS_RNIHVJI_0[15]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (!C (!B !A)))")) ) + (instance (rename wb_adr_5_i_0_2_RNO_0 "wb_adr_5_i_0_2_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D B+D (!C (B+A)+C B))")) + ) + (instance (rename wb_adr_RNO_0_1 "wb_adr_RNO_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D A+D (!C (B A)))")) + ) (instance RCKEEN_8_u_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (!C (!B A)+C (!B+!A))+D (C !A))")) ) - (instance wb_we_0_0_0_a2_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!B+A)+D (!C (!B+A)+C (!B A)))")) - ) - (instance (rename wb_dati_5_1_iv_0_a2_RNO_4 "wb_dati_5_1_iv_0_a2_RNO[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (B A)+D (!C (B A)+C (!B A+B !A)))")) - ) (instance (rename IS_RNO_3 "IS_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D A+D (!C A+C (!B A+B !A)))")) ) + (instance wb_reqe_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D !A+D (!C !A+C (!B !A)))")) + ) + (instance (rename wb_dati_5_1_iv_0_o2_0_RNIMDJC1_4 "wb_dati_5_1_iv_0_o2_0_RNIMDJC1[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B A)))")) + ) + (instance (rename wb_dati_5_1_iv_0_1_RNO_7 "wb_dati_5_1_iv_0_1_RNO[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B A)))")) + ) + (instance (rename wb_dati_5_1_iv_0_RNO_7 "wb_dati_5_1_iv_0_RNO[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!B A)+D (C (!B A)))")) + ) + (instance un1_CmdEnable20_0_0_a2_3_RNIJ3N91 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B A)))")) + ) (instance Ready_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D A+D (!C (B+A)+C A))")) ) + (instance (rename wb_adr_5_i_0_1_0 "wb_adr_5_i_0_1[0]") (viewRef PRIM (cellRef PFUMX (libraryRef LUCENT))) ) + (instance (rename wb_adr_5_i_0_1_bm_0 "wb_adr_5_i_0_1_bm[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B A))")) + ) + (instance (rename wb_adr_5_i_0_1_am_0 "wb_adr_5_i_0_1_am[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (!B A+B !A)))")) + ) + (instance (rename wb_dati_5_1_iv_0_0_o2_5 "wb_dati_5_1_iv_0_0_o2[5]") (viewRef PRIM (cellRef PFUMX (libraryRef LUCENT))) ) + (instance (rename wb_dati_5_1_iv_0_0_o2_bm_5 "wb_dati_5_1_iv_0_0_o2_bm[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C A+C (!B+A))+D A)")) + ) + (instance (rename wb_dati_5_1_iv_0_0_o2_am_5 "wb_dati_5_1_iv_0_0_o2_am[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D A+D (!C A+C (!B+A)))")) + ) (instance Ready_fast_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(B+A)")) ) @@ -991,8 +1060,6 @@ ) (instance (rename IS_3 "IS[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) ) - (instance FWEr_fast (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) (instance FWEr (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) ) (instance (rename FS_0 "FS[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) @@ -1134,50 +1201,50 @@ (instance (rename MAin_pad_0 "MAin_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) (instance PHI2_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance CmdEnable_s_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C !B)+D (!C (!B A)))")) - ) (instance CmdEnable_s (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D+(!C A+C B))")) ) - (instance ADSubmitted_r_0_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B A)")) + (instance CmdEnable_0_sqmuxa_0_a2_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) ) - (instance CmdEnable17_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (!B A)))")) + (instance nRWE_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C+(!B+A))+D A)")) + ) + (instance (rename wb_dati_5_1_iv_0_0_5 "wb_dati_5_1_iv_0_0[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C (B+A))")) + ) + (instance (rename wb_dati_5_1_iv_0_0_2 "wb_dati_5_1_iv_0_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C (B+A))")) + ) + (instance CmdEnable_s_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C !B)+D (!C (!B A)))")) ) (instance CmdUFMData_1_sqmuxa_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (!B A)))")) + (property lut_function (string "(B A)")) ) - (instance (rename wb_adr_5_i_i_0 "wb_adr_5_i_i[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(!C B+C (B+A)))")) + (instance wb_we_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C+(B A)))")) ) - (instance (rename wb_dati_5_1_iv_0_2 "wb_dati_5_1_iv_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(!C B+C (B+A)))")) + (instance (rename wb_adr_RNO_0 "wb_adr_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B+!A)))")) ) - (instance (rename wb_dati_5_1_iv_0_5 "wb_dati_5_1_iv_0[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(!C B+C (B+A)))")) + (instance nRCS_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B+!A)+C !A))")) ) - (instance XOR8MEG18_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance un1_ADWR_i_i_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!B A)")) ) - (instance (rename wb_dati_5_1_iv_0_4 "wb_dati_5_1_iv_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C+(B+A))")) + (instance CmdUFMData_1_sqmuxa_0_a2_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B A)))")) ) - (instance CmdEnable_0_sqmuxa_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (!B A)))")) + (instance (rename wb_dati_5_1_iv_0_0_6 "wb_dati_5_1_iv_0_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C (!B !A)))")) ) - (instance (rename wb_adr_5_i_i_1 "wb_adr_5_i_i[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C+(B !A))")) - ) - (instance (rename wb_dati_5_1_iv_0_6 "wb_dati_5_1_iv_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance (rename wb_dati_5_1_iv_0_7 "wb_dati_5_1_iv_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D+(!C A+C (B+A)))")) ) - (instance (rename wb_dati_5_1_iv_0_3 "wb_dati_5_1_iv_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(!C B+C (B+A)))")) - ) - (instance (rename wb_adr_5_i_i_5_0 "wb_adr_5_i_i_5[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C+(B+A)))")) + (instance (rename wb_dati_5_1_iv_0_0_3 "wb_dati_5_1_iv_0_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+B)+D (C+(B+A)))")) ) (instance Cmdn8MEGEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C (!B !A)+C !A)")) @@ -1185,212 +1252,206 @@ (instance CmdLEDEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C !A+C (B !A))")) ) - (instance (rename wb_dati_5_0_iv_0_0 "wb_dati_5_0_iv_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C B)+D (!C A+C (B+A)))")) + (instance (rename wb_adr_RNO_1 "wb_adr_RNO[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B A)))")) ) (instance RA10_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D+(!C+(B+A)))")) ) - (instance un1_ADWR_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance un1_CmdEnable20_0_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D+(C+(!B+!A)))")) ) - (instance (rename wb_dati_5_1_iv_0_0_1 "wb_dati_5_1_iv_0_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C+(B+A)))")) + (instance (rename wb_dati_5_1_iv_0_1 "wb_dati_5_1_iv_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C (!B !A)))")) ) - (instance wb_we_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C+(B A)))")) + (instance nRWE_s_i_tz_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C (B !A)))")) ) - (instance un1_CmdEnable20_0_a2_1_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (!B A)))")) + (instance (rename wb_dati_5_1_iv_0_0_1_6 "wb_dati_5_1_iv_0_0_1[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+B)+D (C+(B+A)))")) ) - (instance (rename wb_dati_5_1_iv_0_1_3 "wb_dati_5_1_iv_0_1[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D C+D (C+(B !A)))")) + (instance (rename wb_dati_5_1_iv_0_1_7 "wb_dati_5_1_iv_0_1[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+B)+D (C+(B+A)))")) ) - (instance (rename wb_dati_5_1_iv_0_2_4 "wb_dati_5_1_iv_0_2[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C A)+D (!C B+C (B+A)))")) + (instance (rename wb_dati_5_1_iv_0_0_1_4 "wb_dati_5_1_iv_0_0_1[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+B)+D (C+(B+A)))")) ) - (instance (rename wb_adr_5_i_i_0_1 "wb_adr_5_i_i_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C !B)+D (!C A+C (!B+A)))")) + (instance (rename wb_dati_5_0_iv_0_0 "wb_dati_5_0_iv_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C B)+D (!C A+C (B+A)))")) ) - (instance wb_cyc_stb_4_iv_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance wb_cyc_stb_4_iv_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D C+D (C+(B A)))")) ) - (instance CmdUFMWrite_3_u_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance CmdUFMWrite_3_u_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D C+D (C+(B !A)))")) ) - (instance (rename wb_dati_5_1_iv_0_a2_0_1 "wb_dati_5_1_iv_0_a2_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (!C (B !A)))")) + (instance nRWE_s_i_a2_1_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B A)))")) ) (instance nRCS_9_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D+(!C (!B A)+C !B))")) ) - (instance (rename wb_adr_5_i_i_a2_5_0 "wb_adr_5_i_i_a2_5[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C (B !A))")) + (instance (rename wb_dati_5_1_iv_0_0_a2_6 "wb_dati_5_1_iv_0_0_a2[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B !A+B A)))")) ) - (instance (rename wb_dati_5_1_iv_0_a2_0_7 "wb_dati_5_1_iv_0_a2_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (!B !A+B A)))")) + (instance (rename wb_dati_5_1_iv_0_1_1 "wb_dati_5_1_iv_0_1[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C (B A)))")) ) - (instance (rename wb_dati_5_1_iv_0_o2_0_5 "wb_dati_5_1_iv_0_o2_0[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D C+D (C+(B !A)))")) + (instance (rename wb_dati_5_1_iv_0_0_0_3 "wb_dati_5_1_iv_0_0_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C (B+A))")) ) - (instance (rename wb_dati_5_1_iv_0_0_6 "wb_dati_5_1_iv_0_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C A)+D (!C B+C (B+A)))")) - ) - (instance (rename wb_dati_5_1_iv_0_0_4 "wb_dati_5_1_iv_0_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C B)+D (!C A+C (B+A)))")) - ) - (instance (rename wb_adr_5_i_i_1_0 "wb_adr_5_i_i_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C+B)+D (C+(B+A)))")) + (instance (rename wb_dati_5_1_iv_0_0_1_3 "wb_dati_5_1_iv_0_0_1[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D C+D (C+(B A)))")) ) (instance un1_nRCAS_6_sqmuxa_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (C+(!B+A))+D (!C (!B+A)))")) ) - (instance (rename wb_dati_5_1_iv_0_a2_1_3 "wb_dati_5_1_iv_0_a2_1[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (!C (B !A)))")) - ) - (instance CmdUFMShift_3_u_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C A)+D (!C !B+C (!B+A)))")) - ) - (instance XOR8MEG_3_u_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D C+D (C+(!B+!A)))")) - ) - (instance (rename wb_adr_5_i_i_1_0_0 "wb_adr_5_i_i_1_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B !A))+D !B)")) - ) - (instance wb_cyc_stb_4_iv_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (!B A)))")) - ) - (instance wb_cyc_stb_2_sqmuxa_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(!C A+C (B+A)))")) - ) - (instance wb_we_0_0_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C (!B !A))")) - ) - (instance (rename wb_adr_5_i_i_a2_7_0 "wb_adr_5_i_i_a2_7[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (!C (B !A)))")) - ) - (instance Cmdn8MEGEN_4_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C A)+D (!C !B+C (!B+A)))")) - ) - (instance CmdLEDEN_4_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C B)+D (!C (B+!A)+C !A))")) - ) - (instance wb_we_0_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C (!B !A)))")) - ) - (instance un1_ADWR_i_o2_10 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C+(B+!A)))")) - ) - (instance un1_CmdEnable20_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!B !A)+D (C+(!B !A)))")) - ) - (instance (rename wb_dati_5_1_iv_0_0_7 "wb_dati_5_1_iv_0_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C A)+D (!C !B+C (!B+A)))")) - ) - (instance (rename wb_adr_5_i_i_0_RNO_1 "wb_adr_5_i_i_0_RNO[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance (rename wb_dati_5_1_iv_0_o2_7 "wb_dati_5_1_iv_0_o2[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(C+(B !A))")) ) - (instance wb_reqe_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C+(!B+!A)))")) + (instance XOR8MEG_3_u_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D C+D (C+(!B+!A)))")) ) - (instance CmdValid_RNIS5A51 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D !B+D (!C (!B+A)+C !B))")) + (instance CmdUFMShift_3_u_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C A)+D (!C !B+C (!B+A)))")) ) - (instance (rename wb_dati_5_1_iv_0_o2_3 "wb_dati_5_1_iv_0_o2[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (B !A)+C (B A))+D (C (!B+!A)))")) + (instance (rename wb_dati_5_1_iv_0_a2_5_3 "wb_dati_5_1_iv_0_a2_5[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) ) - (instance (rename wb_adr_5_i_m2_0_6 "wb_adr_5_i_m2_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C !B+C (!B+A))")) + (instance (rename wb_dati_5_1_iv_0_a2_7_3 "wb_dati_5_1_iv_0_a2_7[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B !A)))")) ) - (instance (rename wb_adr_5_i_m2_0_5 "wb_adr_5_i_m2_0[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C !B+C (!B+A))")) + (instance (rename wb_dati_5_1_iv_0_a2_2_4 "wb_dati_5_1_iv_0_a2_2[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) ) - (instance (rename wb_adr_5_i_m2_0_4 "wb_adr_5_i_m2_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C !B+C (!B+A))")) - ) - (instance CmdEnable_0_sqmuxa_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B A)")) - ) - (instance (rename wb_dati_5_1_iv_0_a2_7_1 "wb_dati_5_1_iv_0_a2_7[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B !A)")) - ) - (instance CmdUFMWrite_3_u_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B A)")) - ) - (instance IS_0_sqmuxa_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B+A)")) - ) - (instance nRCAS_0_sqmuxa_1_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (!B A)))")) - ) - (instance CmdValid_r (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B !A)")) - ) - (instance Ready_0_sqmuxa_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (!C (!B A)))")) - ) - (instance (rename wb_dati_5_1_iv_0_a2_2_1 "wb_dati_5_1_iv_0_a2_2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance wb_cyc_stb_4_iv_0_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D (!C (B A)))")) ) - (instance (rename wb_adr_5_i_i_a2_0 "wb_adr_5_i_i_a2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B !A)+C (!B A)))")) + (instance wb_cyc_stb_2_sqmuxa_i_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+B)+D (C+(B+A)))")) ) - (instance wb_we_0_0_0_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B !A)))")) + (instance Cmdn8MEGEN_4_u_i_m2_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C A)+D (!C !B+C (!B+A)))")) + ) + (instance CmdLEDEN_4_u_i_m2_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C B)+D (!C (B+!A)+C !A))")) + ) + (instance un1_CmdEnable20_0_0_a2_1_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B A))")) + ) + (instance un1_CmdEnable20_0_0_o2_10 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(!B+!A)))")) + ) + (instance nRCAS_0io_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C !A+C (!B !A)))")) + ) + (instance un1_CmdEnable20_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!B !A)+D (C+(!B !A)))")) + ) + (instance (rename wb_adr_5_i_0_2_0 "wb_adr_5_i_0_2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+(B+A))+D (C+(B !A)))")) + ) + (instance (rename wb_adr_5_i_0_3_0 "wb_adr_5_i_0_3[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C (B !A)))")) + ) + (instance (rename wb_dati_5_1_iv_0_0_1 "wb_dati_5_1_iv_0_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C A)+D (!C !B+C (!B+A)))")) + ) + (instance IS_0_sqmuxa_0_o3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance (rename wb_adr_5_i_3_0_a2_1 "wb_adr_5_i_3_0_a2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C !B+C A))")) + ) + (instance (rename wb_dati_5_1_iv_0_a2_12_3 "wb_dati_5_1_iv_0_a2_12[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B !A)")) + ) + (instance CmdUFMWrite_3_u_0_0_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance CmdValid_r (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B A)")) + ) + (instance LED_pad_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(!C+(!B+A)))")) + ) + (instance (rename wb_adr_5_i_3_0_a2_0_1 "wb_adr_5_i_3_0_a2_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B A))+D (!C A))")) + ) + (instance (rename wb_dati_5_1_iv_0_a2_0_7 "wb_dati_5_1_iv_0_a2_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B A+B !A)))")) + ) + (instance Ready_0_sqmuxa_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B A)))")) ) (instance nRCS_9_u_i_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D (!C (B !A)+C !A))")) ) - (instance (rename wb_adr_5_i_i_a2_0_1_1 "wb_adr_5_i_i_a2_0_1[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (B !A))+D (!C (B A)))")) + (instance (rename wb_adr_5_i_3_0_m2_1 "wb_adr_5_i_3_0_m2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B !A)+C (!B+A))")) + ) + (instance (rename wb_adr_5_i_m2_4 "wb_adr_5_i_m2[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B !A)+C (!B+A))")) + ) + (instance (rename wb_adr_5_i_m2_5 "wb_adr_5_i_m2[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B !A)+C (!B+A))")) + ) + (instance (rename wb_adr_5_i_m2_6 "wb_adr_5_i_m2[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B !A)+C (!B+A))")) ) (instance (rename IS_RNO_2 "IS_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C (B A)+C (!B+!A))")) ) - (instance CmdValid_2_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(!C !B+C (!B+!A)))")) + (instance nRowColSel_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C B+C (B+!A)))")) ) - (instance (rename wb_dati_5_1_iv_0_0_o2_1 "wb_dati_5_1_iv_0_0_o2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance (rename wb_dati_5_1_iv_0_0_o2_4 "wb_dati_5_1_iv_0_0_o2[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B !A+B A)+C (!B !A))")) + ) + (instance (rename wb_dati_5_1_iv_0_0_o2_3 "wb_dati_5_1_iv_0_0_o2[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (C (!B !A))+D (!C (B A)))")) ) - (instance CmdUFMData_1_sqmuxa_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C (B A)))")) - ) - (instance XOR8MEG_3_u_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance XOR8MEG_3_u_0_0_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D (C+(B+A)))")) ) - (instance nRowColSel_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C B+C (B+A))+D (!C B+C (B+!A)))")) + (instance CmdValid_2_i_o2_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(!C !B+C (!B+!A)))")) ) - (instance ADSubmitted_r_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance un1_InitReady_4_i_0_a2_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D !B+D (!C (!B+A)+C !B))")) + ) + (instance ADSubmitted_r_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (C+(!B A)))")) ) - (instance LED_pad_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C+(!B+A))")) - ) - (instance CmdEnable_0_sqmuxa_0_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance un1_CmdEnable20_0_0_a2_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D (!C (B !A)))")) ) - (instance InitReady3_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C (B A)))")) - ) - (instance wb_cyc_stb_2_sqmuxa_i_a2_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (!B !A)))")) - ) - (instance nRWE_s_i_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance un1_CmdEnable20_0_0_a2_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D (C (!B A)))")) ) - (instance XOR8MEG_3_u_0_a2_0_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (!B A)))")) + (instance wb_we_0_0_i_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B !A)+C !B))")) ) - (instance (rename wb_adr_5_i_i_1_0_tz_0_0 "wb_adr_5_i_i_1_0_tz_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(!C (!B A)))")) - ) - (instance (rename wb_dati_5_1_iv_0_a2_1_1_7 "wb_dati_5_1_iv_0_a2_1_1[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance wb_rst_3_0_a2_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D (!C (!B !A)))")) ) - (instance (rename wb_dati_5_1_iv_0_a2_1_0_6 "wb_dati_5_1_iv_0_a2_1_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B !A)+C (!B A)))")) + (instance wb_cyc_stb_2_sqmuxa_i_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B !A)))")) + ) + (instance nRWE_s_i_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B A)))")) + ) + (instance XOR8MEG_3_u_0_0_a2_0_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B A)))")) + ) + (instance wb_cyc_stb_2_sqmuxa_i_0_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B !A)+C B)")) + ) + (instance (rename wb_dati_5_1_iv_0_a2_0_2_1 "wb_dati_5_1_iv_0_a2_0_2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B !A)))")) + ) + (instance (rename wb_dati_5_0_iv_0_a2_1_0 "wb_dati_5_0_iv_0_a2_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B A)+C (!B A)))")) ) (instance RCKE_2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (C !B)+D (C+(B+A)))")) @@ -1398,14 +1459,20 @@ (instance (rename S_RNO_0 "S_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(B+!A)")) ) - (instance Ready_0_sqmuxa_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C+(!B+!A))")) - ) (instance un1_nRCAS_6_sqmuxa_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(C+(B+A))")) ) - (instance (rename wb_adr_5_i_i_a2_3_0_0 "wb_adr_5_i_i_a2_3_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B A))")) + (instance Ready_0_sqmuxa_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C+(!B+!A))")) + ) + (instance (rename wb_dati_5_1_iv_0_a2_5_7 "wb_dati_5_1_iv_0_a2_5[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (!B !A))")) + ) + (instance (rename wb_adr_5_i_0_o2_0 "wb_adr_5_i_0_o2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B !A)+C (!B+A))")) + ) + (instance un1_wb_rst14_2_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(B+A))")) ) (instance RDQMH_pad_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!B+A)")) @@ -1413,69 +1480,57 @@ (instance nCCAS_pad_RNI01SJ (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(B+A)")) ) - (instance (rename wb_adr_5_i_i_a2_6_0_0 "wb_adr_5_i_i_a2_6_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C (!B !A))")) + (instance wb_cyc_stb_2_sqmuxa_i_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B !A))")) ) - (instance (rename FS_RNIQV0F_16 "FS_RNIQV0F[16]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C+(B+A))")) - ) - (instance nRowColSel_0_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (!B !A)))")) - ) - (instance RCKEEN_8_u_0_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance RCKEEN_8_u_0_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(C (B !A))")) ) - (instance wb_cyc_stb_2_sqmuxa_i_a2_3_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B !A)))")) - ) - (instance InitReady3_0_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (B A)))")) - ) - (instance Ready_0_sqmuxa_0_a3_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance Ready_0_sqmuxa_0_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D (!C (B A)))")) ) - (instance un1_ADWR_i_o2_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C+(!B+!A))")) + (instance un1_CmdEnable20_0_0_o2_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C+(!B+!A))")) ) - (instance un1_ADWR_i_o2_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D+(!C+(!B+!A)))")) + (instance un1_CmdEnable20_0_0_o2_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(!C+(!B+!A)))")) ) - (instance un1_ADWR_i_o2_11 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D+(!C+(!B+!A)))")) + (instance un1_CmdEnable20_0_0_o2_11 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D+(!C+(!B+A)))")) ) - (instance (rename wb_dati_5_0_iv_0_a2_0_0_0 "wb_dati_5_0_iv_0_a2_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C (B A))+D (C (!B A)))")) - ) - (instance (rename un9_RA_i_m2_9 "un9_RA_i_m2[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C B+C A)")) - ) - (instance (rename un9_RA_i_m2_7 "un9_RA_i_m2[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C B+C A)")) - ) - (instance (rename un9_RA_i_m2_6 "un9_RA_i_m2[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C B+C A)")) - ) - (instance (rename un9_RA_i_m2_5 "un9_RA_i_m2[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C B+C A)")) - ) - (instance (rename un9_RA_i_m2_4 "un9_RA_i_m2[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C B+C A)")) - ) - (instance (rename un9_RA_i_m2_3 "un9_RA_i_m2[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C B+C A)")) - ) - (instance (rename un9_RA_i_m2_2 "un9_RA_i_m2[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C B+C A)")) - ) - (instance (rename un9_RA_i_m2_1 "un9_RA_i_m2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C B+C A)")) - ) - (instance (rename un9_RA_i_m2_0 "un9_RA_i_m2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C B+C A)")) + (instance (rename wb_dati_5_1_iv_0_0_a2_1_3 "wb_dati_5_1_iv_0_0_a2_1[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B !A)+C (B A)))")) ) (instance LEDEN_6_i_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C (B A)+C (!B+A))")) ) + (instance (rename un9_RA_i_m2_i_m2_0 "un9_RA_i_m2_i_m2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_i_m2_i_m2_1 "un9_RA_i_m2_i_m2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_i_m2_i_m2_4 "un9_RA_i_m2_i_m2[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_i_m2_i_m2_5 "un9_RA_i_m2_i_m2[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_i_m2_i_m2_6 "un9_RA_i_m2_i_m2[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_i_m2_i_m2_7 "un9_RA_i_m2_i_m2[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_i_m2_i_m2_9 "un9_RA_i_m2_i_m2[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_i_m2_i_m2_3 "un9_RA_i_m2_i_m2[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_i_m2_i_m2_2 "un9_RA_i_m2_i_m2[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) (instance (rename un9_RA_8 "un9_RA[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C B+C A)")) ) @@ -1488,95 +1543,95 @@ (instance (rename wb_adr_5_7 "wb_adr_5[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(B A)")) ) - (instance (rename wb_dati_5_1_iv_0_a2_2_6 "wb_dati_5_1_iv_0_a2_2[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B A)")) - ) - (instance (rename wb_dati_5_1_iv_0_o2_7 "wb_dati_5_1_iv_0_o2[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B+A)")) - ) - (instance (rename wb_dati_5_1_iv_0_o2_0_6 "wb_dati_5_1_iv_0_o2_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B+!A)")) - ) - (instance wb_cyc_stb_2_sqmuxa_i_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B+!A)")) - ) - (instance XOR8MEG_3_u_0_o2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B+A)")) - ) - (instance RDQML_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B+!A)")) - ) - (instance XOR8MEG_3_u_0_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance nRCS_9_u_i_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!B !A)")) ) - (instance XOR8MEG_3_u_0_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B A)")) + (instance nRowColSel_0_0_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B !A)")) ) - (instance (rename wb_dati_5_1_iv_0_a2_1_1 "wb_dati_5_1_iv_0_a2_1[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B A)")) + (instance (rename S_0_i_o3_1 "S_0_i_o3[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance RCKEEN_8_u_0_o3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B+!A)")) ) (instance IS_n1_0_x2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!B A+B !A)")) ) - (instance (rename S_0_i_o2_1 "S_0_i_o2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B+A)")) + (instance nRowColSel_0_0_x2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B A+B !A)")) ) - (instance wb_cyc_stb_2_sqmuxa_i_a2_3_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance (rename wb_adr_5_i_0_a2_6_0 "wb_adr_5_i_0_a2_6[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B A)")) + ) + (instance (rename wb_dati_5_1_iv_0_a2_6_4 "wb_dati_5_1_iv_0_a2_6[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename wb_adr_5_i_3_0_a2_3_1 "wb_adr_5_i_3_0_a2_3[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!B !A)")) ) - (instance (rename wb_dati_5_1_iv_0_1_7 "wb_dati_5_1_iv_0_1[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C+(!B+A)))")) + (instance (rename wb_dati_5_1_iv_0_a2_11_3 "wb_dati_5_1_iv_0_a2_11[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B A)")) ) - (instance (rename wb_dati_5_1_iv_0_7 "wb_dati_5_1_iv_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C+A)+D (!C+(B+A)))")) + (instance (rename wb_dati_5_1_iv_0_a2_7_4 "wb_dati_5_1_iv_0_a2_7[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B !A)")) ) - (instance RCKEEN_8_u_1_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance (rename wb_dati_5_1_iv_0_o2_0_7 "wb_dati_5_1_iv_0_o2_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+!A)")) + ) + (instance Cmdn8MEGEN_4_u_i_m2_i_a2_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance XOR8MEG_3_u_0_0_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B A)")) + ) + (instance XOR8MEG_3_u_0_0_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B !A)")) + ) + (instance XOR8MEG_3_u_0_0_o2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance RDQML_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B+!A)")) + ) + (instance wb_cyc_stb_2_sqmuxa_i_a2_2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B !A)")) + ) + (instance wb_cyc_stb_4_iv_0_0_a2_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance InitReady3_0_a2_1_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D+(!C+(!B+!A)))")) + ) + (instance InitReady3_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B A)))")) + ) + (instance wb_we_0_0_i_1_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D !C+D (!C (!B+A)))")) + ) + (instance wb_we_0_0_i_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D+(!C (B A)+C A))")) + ) + (instance (rename wb_dati_5_1_iv_0_1_0_4 "wb_dati_5_1_iv_0_1_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!B+A)+D (!C (!B+A)+C (!B !A)))")) + ) + (instance (rename wb_dati_5_1_iv_0_0_4 "wb_dati_5_1_iv_0_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+A)+D (C+(B !A)))")) + ) + (instance RCKEEN_8_u_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (!C+B)+D (C (!B+!A)))")) ) (instance RCKEEN_8_u (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D B+D (!C B+C (B+!A)))")) ) (instance LEDENe (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B A)+C (B+A))")) + (property lut_function (string "(!C A+C B)")) ) (instance wb_rste (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C !B)+D (!C (B !A)+C (!B+!A)))")) + (property lut_function (string "(!C (B !A)+C (B+A))")) ) (instance wb_reqe (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B A)+C (!B+A))")) - ) - (instance n8MEGEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B+A)+C (B !A))")) - ) - (instance CmdValid_RNITBH02 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D C+D (C+(B A)))")) - ) - (instance wb_cyc_stb_2_sqmuxa_i_o2_RNI167R (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (!C (!B !A)))")) - ) - (instance (rename FS_RNITL2J_14 "FS_RNITL2J[14]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B A)))")) - ) - (instance wb_cyc_stb_4_iv_0_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C (!B A))")) - ) - (instance (rename FS_RNI1FVB_14 "FS_RNI1FVB[14]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B A))")) - ) - (instance n8MEGEN_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B+!A)+C (B !A))")) - ) - (instance (rename FS_RNI7O57_11 "FS_RNI7O57[11]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B+!A)")) - ) - (instance (rename FS_RNIS637_9 "FS_RNIS637[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B+!A)")) - ) - (instance (rename FS_RNICHC8_14 "FS_RNICHC8[14]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B !A)")) - ) - (instance PHI2r3_RNIFT0I (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B !A)")) + (property lut_function (string "(!C (B A)+C (B+!A))")) ) (instance CmdValid_fast_RNI3K0H1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D+(C (B A)))")) @@ -1584,125 +1639,125 @@ (instance PHI2r3_RNIFT0I_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(B !A)")) ) - (instance CmdValid_r_fast (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance n8MEGEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C A+C !B)")) + ) + (instance CmdValid_RNIOOBE2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D C+D (C+(B A)))")) + ) + (instance (rename FS_RNI7U6M_14 "FS_RNI7U6M[14]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!B !A)")) ) - (instance nRCAS_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!B A)+D (!C !B+C (!B A)))")) + (instance (rename FS_RNIGOCT_12 "FS_RNIGOCT[12]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B A)))")) ) - (instance nRCAS_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B !A))+D (!C (!B !A)+C (B !A)))")) + (instance wb_cyc_stb_4_iv_0_0_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (!B A))")) ) - (instance nRCAS_0io_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B A)")) + (instance (rename FS_RNI82PA_15 "FS_RNI82PA[15]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(B+!A))")) ) - (instance nRCS_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B+!A)+C !A))")) + (instance (rename FS_RNIHVJI_15 "FS_RNIHVJI[15]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(B+!A)))")) ) - (instance nRCS_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B !A)")) + (instance (rename FS_RNIF2MA_9 "FS_RNIF2MA[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C+(!B+!A))")) ) - (instance nRWE_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C (!B+!A)))")) + (instance n8MEGEN_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B+!A)+C (B !A))")) ) - (instance nRWE_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C+!A)+D (!C (!B !A)+C !B))")) + (instance (rename FS_RNIS637_9 "FS_RNIS637[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B+!A)")) ) - (instance nRWE_0io_RNO_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance (rename FS_RNI9Q57_12 "FS_RNI9Q57[12]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance PHI2r3_RNIFT0I (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(B !A)")) ) - (instance nRWE_0io_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B A))")) + (instance CBR_fast_RNIQ31K1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B A)))")) + ) + (instance RASr2_RNI6PUF (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B A)")) + ) + (instance CmdValid_r_fast (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B A)")) + ) + (instance nRCAS_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B+!A)+C B)")) + ) + (instance nRCAS_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D !C+D (!C (!B !A)))")) ) (instance RA11d (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (!C (B A)+C (B !A))+D (C B))")) ) - (instance wb_cyc_stb_2_sqmuxa_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C+(B+!A)))")) - ) - (instance (rename wb_dati_5_1_iv_0_a2_3_2_7 "wb_dati_5_1_iv_0_a2_3_2[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (!C (B A)))")) - ) - (instance (rename wb_dati_5_1_iv_0_a2_9_1 "wb_dati_5_1_iv_0_a2_9[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (!C (!B !A)))")) - ) - (instance CmdLEDEN_4_u_i_a2_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (B !A)))")) - ) - (instance un1_CmdEnable20_0_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (!C (!B A)))")) - ) - (instance IS_0_sqmuxa_0_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C+(!B+!A)))")) - ) - (instance (rename RowAd_7 "RowAd[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B A)")) - ) (instance (rename RowAd_8 "RowAd[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(B A)")) ) - (instance (rename RowAd_5 "RowAd[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B+A)")) - ) - (instance (rename RBAd_1 "RBAd[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B A)")) - ) - (instance (rename RowAd_3 "RowAd[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B A)")) - ) (instance (rename RowAd_0 "RowAd[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(B A)")) ) - (instance (rename RowAd_6 "RowAd[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance (rename RowAd_2 "RowAd[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(B A)")) ) - (instance (rename RowAd_2 "RowAd[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance (rename RowAd_3 "RowAd[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(B A)")) ) (instance (rename RowAd_4 "RowAd[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(B A)")) ) - (instance (rename RowAd_1 "RowAd[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance (rename RowAd_6 "RowAd[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(B A)")) ) (instance (rename RBAd_0 "RBAd[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(B A)")) ) + (instance (rename RowAd_7 "RowAd[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename RowAd_5 "RowAd[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B+A)")) + ) + (instance (rename RowAd_1 "RowAd[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename RBAd_1 "RBAd[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) (instance (rename RowAd_9 "RowAd[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!B+A)")) ) + (instance IS_0_sqmuxa_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(!B+!A)))")) + ) + (instance Cmdn8MEGEN_4_u_i_m2_i_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B !A)))")) + ) + (instance un1_CmdEnable20_0_0_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B A)))")) + ) + (instance CmdLEDEN_4_u_i_m2_i_a2_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B !A)))")) + ) + (instance (rename wb_dati_5_1_iv_0_o2_0_4 "wb_dati_5_1_iv_0_o2_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C A+C (!B A+B !A))")) + ) + (instance (rename wb_dati_5_1_iv_0_a2_13_3 "wb_dati_5_1_iv_0_a2_13[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B !A))")) + ) (instance nRRAS_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (!C (!B !A)+C !A)+D (C !A))")) ) - (instance CmdEnable16_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (!B A)))")) - ) - (instance un1_CmdEnable20_0_a2_3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (B A)))")) - ) - (instance (rename wb_dati_5_1_iv_0_0_a2_1 "wb_dati_5_1_iv_0_0_a2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (B A)))")) - ) - (instance (rename wb_adr_5_i_i_a2_11_0 "wb_adr_5_i_i_a2_11[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B A))")) - ) - (instance IS_0_sqmuxa_0_o2_0_RNIS63D (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance IS_0_sqmuxa_0_o2_RNIDJQJ (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!B !A)")) ) (instance (rename IS_RNO_0 "IS_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C (!B !A+B A)+C A)")) ) - (instance (rename wb_adr_5_i_i_a2_6_0 "wb_adr_5_i_i_a2_6[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B A))")) - ) - (instance (rename wb_dati_5_1_iv_0_a2_4 "wb_dati_5_1_iv_0_a2[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B A)))")) - ) - (instance XOR8MEG18_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (!C (B !A)))")) - ) - (instance CmdEnable_RNI7PMB1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(!C+(B+!A)))")) + (instance CmdEnable16_0_a2_1_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B A)))")) ) (instance (rename FS_s_0_17 "FS_s_0[17]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) (property INIT0 (string "0x5002")) @@ -1764,13 +1819,13 @@ (property INJECT1_0 (string "NO")) (property INIT1 (string "0x300A")) ) - (instance rck (viewRef verilog (cellRef ODDRXE)) ) + (instance rclk_oddr (viewRef verilog (cellRef ODDRXE)) ) (instance ufmefb (viewRef netlist (cellRef REFB)) ) (net wb_rst (joined (portRef Q (instanceRef wb_rst)) (portRef wb_rst (instanceRef ufmefb)) - (portRef C (instanceRef wb_rste)) + (portRef B (instanceRef wb_rste)) )) (net wb_cyc_stb (joined (portRef Q (instanceRef wb_cyc_stb)) @@ -1784,7 +1839,7 @@ (net (rename wb_adr_0 "wb_adr[0]") (joined (portRef Q (instanceRef wb_adr_0)) (portRef (member wb_adr 7) (instanceRef ufmefb)) - (portRef D (instanceRef wb_adr_5_i_i_0_1)) + (portRef C (instanceRef wb_adr_5_i_3_0_m2_1)) )) (net (rename wb_adr_1 "wb_adr[1]") (joined (portRef Q (instanceRef wb_adr_1)) @@ -1799,17 +1854,17 @@ (net (rename wb_adr_3 "wb_adr[3]") (joined (portRef Q (instanceRef wb_adr_3)) (portRef (member wb_adr 4) (instanceRef ufmefb)) - (portRef C (instanceRef wb_adr_5_i_m2_0_4)) + (portRef C (instanceRef wb_adr_5_i_m2_4)) )) (net (rename wb_adr_4 "wb_adr[4]") (joined (portRef Q (instanceRef wb_adr_4)) (portRef (member wb_adr 3) (instanceRef ufmefb)) - (portRef C (instanceRef wb_adr_5_i_m2_0_5)) + (portRef C (instanceRef wb_adr_5_i_m2_5)) )) (net (rename wb_adr_5 "wb_adr[5]") (joined (portRef Q (instanceRef wb_adr_5)) (portRef (member wb_adr 2) (instanceRef ufmefb)) - (portRef C (instanceRef wb_adr_5_i_m2_0_6)) + (portRef C (instanceRef wb_adr_5_i_m2_6)) )) (net (rename wb_adr_6 "wb_adr[6]") (joined (portRef Q (instanceRef wb_adr_6)) @@ -1823,42 +1878,42 @@ (net (rename wb_dati_0 "wb_dati[0]") (joined (portRef Q (instanceRef wb_dati_0)) (portRef (member wb_dati 7) (instanceRef ufmefb)) - (portRef B (instanceRef wb_dati_5_1_iv_0_a2_1_1)) + (portRef C (instanceRef wb_dati_5_1_iv_0_0_1)) )) (net (rename wb_dati_1 "wb_dati[1]") (joined (portRef Q (instanceRef wb_dati_1)) (portRef (member wb_dati 6) (instanceRef ufmefb)) - (portRef C (instanceRef wb_dati_5_1_iv_0_2)) + (portRef C (instanceRef wb_dati_5_1_iv_0_0_2)) )) (net (rename wb_dati_2 "wb_dati[2]") (joined (portRef Q (instanceRef wb_dati_2)) (portRef (member wb_dati 5) (instanceRef ufmefb)) - (portRef C (instanceRef wb_dati_5_1_iv_0_3)) + (portRef C (instanceRef wb_dati_5_1_iv_0_0_0_3)) )) (net (rename wb_dati_3 "wb_dati[3]") (joined (portRef Q (instanceRef wb_dati_3)) (portRef (member wb_dati 4) (instanceRef ufmefb)) - (portRef D (instanceRef wb_dati_5_1_iv_0_0_4)) + (portRef D (instanceRef wb_dati_5_1_iv_0_0_1_4)) )) (net (rename wb_dati_4 "wb_dati[4]") (joined (portRef Q (instanceRef wb_dati_4)) (portRef (member wb_dati 3) (instanceRef ufmefb)) - (portRef C (instanceRef wb_dati_5_1_iv_0_5)) + (portRef C (instanceRef wb_dati_5_1_iv_0_0_5)) )) (net (rename wb_dati_5 "wb_dati[5]") (joined (portRef Q (instanceRef wb_dati_5)) (portRef (member wb_dati 2) (instanceRef ufmefb)) - (portRef C (instanceRef wb_dati_5_1_iv_0_0_6)) + (portRef D (instanceRef wb_dati_5_1_iv_0_0_1_6)) )) (net (rename wb_dati_6 "wb_dati[6]") (joined (portRef Q (instanceRef wb_dati_6)) (portRef (member wb_dati 1) (instanceRef ufmefb)) - (portRef C (instanceRef wb_dati_5_1_iv_0_0_7)) + (portRef D (instanceRef wb_dati_5_1_iv_0_1_7)) )) (net (rename wb_dati_7 "wb_dati[7]") (joined (portRef Q (instanceRef wb_dati_7)) (portRef (member wb_dati 0) (instanceRef ufmefb)) - (portRef D (instanceRef wb_adr_5_i_i_1_0)) + (portRef D (instanceRef wb_adr_5_i_0_2_0)) )) (net (rename wb_dato_0 "wb_dato[0]") (joined (portRef (member wb_dato 1) (instanceRef ufmefb)) @@ -1870,48 +1925,58 @@ )) (net wb_ack (joined (portRef wb_ack (instanceRef ufmefb)) - (portRef D (instanceRef wb_cyc_stb_2_sqmuxa_i_0)) + (portRef C (instanceRef wb_cyc_stb_2_sqmuxa_i_0_0)) )) (net CBR (joined (portRef Q (instanceRef CBR)) - (portRef A (instanceRef nRCAS_0io_RNO_0)) (portRef A (instanceRef RCKEEN_8_u)) - (portRef B (instanceRef nRowColSel_0_0_a3_0)) + (portRef A (instanceRef RCKEEN_8_u_0_a2_2)) + (portRef A (instanceRef nRowColSel_0_0)) (portRef A (instanceRef LED_pad_RNO)) + (portRef A (instanceRef nRCAS_0io_RNO_1)) )) (net InitReady (joined (portRef Q (instanceRef InitReady)) - (portRef B (instanceRef IS_0_sqmuxa_0_o2_0)) - (portRef B (instanceRef wb_cyc_stb_2_sqmuxa_i_o2)) - (portRef D (instanceRef CmdValid_fast_RNI3K0H1)) + (portRef B (instanceRef IS_0_sqmuxa_0_o2)) (portRef B (instanceRef n8MEGEN_RNO_0)) - (portRef B (instanceRef CmdValid_RNITBH02)) - (portRef A (instanceRef wb_dati_5_1_iv_0_a2_1_1)) + (portRef D (instanceRef FS_RNIHVJI_15)) + (portRef B (instanceRef CmdValid_RNIOOBE2)) + (portRef D (instanceRef CmdValid_fast_RNI3K0H1)) + (portRef A (instanceRef wb_we_0_0_i_1_1)) + (portRef B (instanceRef wb_adr_5_i_3_0_a2_3_1)) + (portRef B (instanceRef wb_adr_5_i_0_a2_6_0)) (portRef A (instanceRef wb_adr_5_7)) (portRef A (instanceRef wb_adr_5_3)) (portRef A (instanceRef wb_adr_5_2)) (portRef B (instanceRef LEDEN_6_i_m2)) - (portRef C (instanceRef FS_RNIQV0F_16)) - (portRef A (instanceRef Ready_0_sqmuxa_0_a3)) - (portRef A (instanceRef wb_adr_5_i_m2_0_4)) - (portRef A (instanceRef wb_adr_5_i_m2_0_5)) - (portRef A (instanceRef wb_adr_5_i_m2_0_6)) - (portRef B (instanceRef CmdValid_RNIS5A51)) - (portRef A (instanceRef wb_dati_5_1_iv_0_0_7)) - (portRef A (instanceRef wb_adr_5_i_i_1_0)) - (portRef A (instanceRef wb_dati_5_1_iv_0_0_4)) - (portRef A (instanceRef wb_dati_5_1_iv_0_0_6)) - (portRef B (instanceRef wb_cyc_stb_4_iv_0)) - (portRef A (instanceRef wb_adr_5_i_i_0_1)) - (portRef B (instanceRef wb_we_0_0_0)) + (portRef C (instanceRef un1_wb_rst14_2_0_o2)) + (portRef B (instanceRef un1_InitReady_4_i_0_a2_i)) + (portRef A (instanceRef wb_adr_5_i_m2_6)) + (portRef A (instanceRef wb_adr_5_i_m2_5)) + (portRef A (instanceRef wb_adr_5_i_m2_4)) + (portRef A (instanceRef wb_adr_5_i_3_0_m2_1)) + (portRef A (instanceRef Ready_0_sqmuxa_0_a2)) + (portRef C (instanceRef wb_adr_5_i_3_0_a2_0_1)) + (portRef A (instanceRef wb_dati_5_1_iv_0_0_1)) + (portRef A (instanceRef wb_adr_5_i_0_2_0)) + (portRef A (instanceRef wb_dati_5_1_iv_0_0_0_3)) + (portRef B (instanceRef wb_cyc_stb_4_iv_0_0)) (portRef A (instanceRef wb_dati_5_0_iv_0_0)) - (portRef A (instanceRef wb_dati_5_1_iv_0_3)) - (portRef A (instanceRef wb_dati_5_1_iv_0_5)) - (portRef A (instanceRef wb_dati_5_1_iv_0_2)) + (portRef A (instanceRef wb_dati_5_1_iv_0_0_1_4)) + (portRef A (instanceRef wb_dati_5_1_iv_0_1_7)) + (portRef A (instanceRef wb_dati_5_1_iv_0_0_1_6)) + (portRef B (instanceRef wb_we_RNO)) + (portRef A (instanceRef wb_dati_5_1_iv_0_0_2)) + (portRef A (instanceRef wb_dati_5_1_iv_0_0_5)) (portRef B (instanceRef InitReady_RNO)) + (portRef D (instanceRef wb_adr_5_i_0_1_am_0)) (portRef D (instanceRef Ready_RNO)) (portRef C (instanceRef RCKEEN_8_u_RNO)) - (portRef B (instanceRef FS_RNIHVJI_15)) + (portRef C (instanceRef wb_adr_5_i_0_2_RNO_0)) + (portRef B (instanceRef FS_RNIHVJI_0_15)) + (portRef A (instanceRef FS_RNIOVGI_9)) + (portRef C (instanceRef wb_adr_5_i_0_2_RNO_0_0)) + (portRef B (instanceRef FS_RNIJO0F_12)) )) (net C1Submitted (joined (portRef Q (instanceRef C1Submitted)) @@ -1921,69 +1986,72 @@ (net CmdUFMShift (joined (portRef Q (instanceRef CmdUFMShift)) (portRef A (instanceRef CmdValid_fast_RNI3K0H1)) - (portRef A (instanceRef CmdUFMShift_3_u_0_0)) + (portRef A (instanceRef CmdUFMShift_3_u_0_0_0)) )) (net (rename Bank_2 "Bank[2]") (joined (portRef Q (instanceRef Bank_0io_2)) - (portRef B (instanceRef un1_ADWR_i_o2_10)) + (portRef A (instanceRef un1_CmdEnable20_0_0_o2_11)) )) (net Ready (joined (portRef Q (instanceRef Ready)) (portRef B (instanceRef IS_RNO_0)) - (portRef A (instanceRef IS_0_sqmuxa_0_o2_0_RNIS63D)) + (portRef A (instanceRef IS_0_sqmuxa_0_o2_RNIDJQJ)) + (portRef C (instanceRef CBR_fast_RNIQ31K1)) (portRef D (instanceRef RCKEEN_8_u)) - (portRef B (instanceRef RCKEEN_8_u_0_a2_1)) - (portRef D (instanceRef nRowColSel_0_0_a3_0)) - (portRef C (instanceRef nRowColSel_0_0)) + (portRef B (instanceRef RCKEEN_8_u_0_a2_2)) + (portRef D (instanceRef nRowColSel_0_0)) (portRef D (instanceRef nRCS_9_u_i_0_0)) - (portRef C (instanceRef Ready_0_sqmuxa_0_a3)) - (portRef D (instanceRef nRCAS_0_sqmuxa_1_0_a3)) - (portRef B (instanceRef IS_0_sqmuxa_0_o2)) + (portRef C (instanceRef Ready_0_sqmuxa_0_a2)) + (portRef C (instanceRef LED_pad_RNO)) + (portRef B (instanceRef IS_0_sqmuxa_0_o3)) (portRef C (instanceRef un1_nRCAS_6_sqmuxa_i_0)) (portRef A (instanceRef Ready_RNO)) (portRef A (instanceRef RCKEEN_8_u_RNO)) - (portRef A (instanceRef S_RNICVV51_0)) + (portRef A (instanceRef S_RNICVV51_1)) )) (net n8MEGEN (joined (portRef Q (instanceRef n8MEGEN)) (portRef D (instanceRef RA11d)) - (portRef B (instanceRef n8MEGEN_RNO)) + (portRef A (instanceRef n8MEGEN_RNO)) (portRef C (instanceRef Cmdn8MEGEN_RNO)) )) (net CO0 (joined (portRef Q (instanceRef S_0)) - (portRef D (instanceRef IS_0_sqmuxa_0_o2_0)) - (portRef A (instanceRef nRCS_0io_RNO_0)) - (portRef B (instanceRef nRCAS_0io_RNO_0)) - (portRef B (instanceRef RCKEEN_8_u_1_0)) - (portRef A (instanceRef S_0_i_o2_1)) - (portRef A (instanceRef Ready_0_sqmuxa_0_a3_2)) + (portRef D (instanceRef IS_0_sqmuxa_0_o2)) + (portRef B (instanceRef CBR_fast_RNIQ31K1)) + (portRef B (instanceRef RCKEEN_8_u_1)) + (portRef A (instanceRef nRowColSel_0_0_x2)) + (portRef B (instanceRef RCKEEN_8_u_0_o3)) + (portRef A (instanceRef S_0_i_o3_1)) + (portRef A (instanceRef nRCS_9_u_i_a2_0)) + (portRef A (instanceRef Ready_0_sqmuxa_0_a2_2)) (portRef A (instanceRef S_RNO_0)) - (portRef C (instanceRef nRWE_s_i_a2_0)) - (portRef A (instanceRef nRowColSel_0_0)) - (portRef C (instanceRef S_RNICVV51_0)) + (portRef C (instanceRef nRWE_s_i_a2_2)) + (portRef B (instanceRef nRCAS_0io_RNO_2)) + (portRef C (instanceRef S_RNICVV51_1)) )) (net (rename S_1 "S[1]") (joined (portRef Q (instanceRef S_1)) - (portRef C (instanceRef IS_0_sqmuxa_0_o2_0)) - (portRef D (instanceRef nRCAS_0io_RNO)) - (portRef D (instanceRef RCKEEN_8_u_1_0)) - (portRef B (instanceRef S_0_i_o2_1)) - (portRef D (instanceRef Ready_0_sqmuxa_0_a3_2)) - (portRef C (instanceRef RCKEEN_8_u_0_a2_1)) + (portRef C (instanceRef IS_0_sqmuxa_0_o2)) + (portRef C (instanceRef nRCAS_0io_RNO_0)) + (portRef B (instanceRef RASr2_RNI6PUF)) + (portRef D (instanceRef RCKEEN_8_u_1)) + (portRef B (instanceRef nRowColSel_0_0_x2)) + (portRef B (instanceRef S_0_i_o3_1)) + (portRef D (instanceRef Ready_0_sqmuxa_0_a2_2)) + (portRef C (instanceRef RCKEEN_8_u_0_a2_2)) (portRef B (instanceRef S_RNO_0)) - (portRef D (instanceRef nRowColSel_0_0)) (portRef D (instanceRef un1_nRCAS_6_sqmuxa_i_0)) - (portRef B (instanceRef S_RNICVV51_0)) + (portRef B (instanceRef S_RNICVV51_1)) )) (net RASr2 (joined (portRef Q (instanceRef RASr2)) - (portRef A (instanceRef IS_0_sqmuxa_0_o2_0)) - (portRef A (instanceRef nRWE_0io_RNO_2)) - (portRef C (instanceRef Ready_0_sqmuxa_0_a3_2)) + (portRef A (instanceRef IS_0_sqmuxa_0_o2)) + (portRef A (instanceRef RASr2_RNI6PUF)) + (portRef C (instanceRef Ready_0_sqmuxa_0_a2_2)) (portRef B (instanceRef RCKE_2_0)) (portRef B (instanceRef nRCS_9_u_i_0_0)) - (portRef C (instanceRef nRCAS_0_sqmuxa_1_0_a3)) + (portRef A (instanceRef nRWE_s_i_tz_0)) (portRef D (instanceRef RASr3)) (portRef B (instanceRef RCKEEN_8_u_RNO)) (portRef A (instanceRef RASr2_RNIAFR1)) @@ -1992,265 +2060,275 @@ (portRef Q (instanceRef FS_14)) (portRef (member fs 0) (instanceRef ufmefb)) (portRef A1 (instanceRef FS_cry_0_13)) - (portRef D (instanceRef wb_dati_5_1_iv_0_a2_4)) - (portRef C (instanceRef wb_adr_5_i_i_a2_6_0)) - (portRef A (instanceRef wb_dati_5_1_iv_0_a2_3_2_7)) - (portRef A (instanceRef FS_RNICHC8_14)) - (portRef B (instanceRef FS_RNI1FVB_14)) - (portRef B (instanceRef FS_RNITL2J_14)) - (portRef A (instanceRef wb_rste)) - (portRef B (instanceRef wb_dati_5_1_iv_0_o2_7)) - (portRef D (instanceRef wb_dati_5_0_iv_0_a2_0_0_0)) + (portRef C (instanceRef wb_dati_5_1_iv_0_a2_13_3)) + (portRef C (instanceRef FS_RNIGOCT_12)) + (portRef A (instanceRef FS_RNI7U6M_14)) (portRef B (instanceRef InitReady3_0_a2)) - (portRef D (instanceRef wb_dati_5_1_iv_0_0_o2_1)) - (portRef B (instanceRef wb_dati_5_1_iv_0_a2_2_1)) - (portRef C (instanceRef wb_reqe_RNO)) - (portRef A (instanceRef wb_we_0_0_0_a2)) - (portRef B (instanceRef wb_dati_5_1_iv_0_a2_0_7)) + (portRef B (instanceRef wb_dati_5_1_iv_0_a2_7_4)) + (portRef A (instanceRef wb_adr_5_i_3_0_a2_3_1)) + (portRef A (instanceRef wb_adr_5_i_0_a2_6_0)) + (portRef C (instanceRef wb_dati_5_0_iv_0_a2_1_0)) + (portRef D (instanceRef wb_dati_5_1_iv_0_0_o2_3)) + (portRef B (instanceRef wb_adr_5_i_3_0_a2_0_1)) + (portRef C (instanceRef wb_adr_5_i_3_0_a2_1)) + (portRef A (instanceRef wb_dati_5_1_iv_0_o2_7)) + (portRef B (instanceRef wb_reqe_RNO)) + (portRef D (instanceRef wb_adr_5_i_0_2_RNO_0)) + (portRef D (instanceRef wb_adr_5_i_0_2_RNO_0_0)) + (portRef C (instanceRef FS_RNIJO0F_12)) + (portRef B (instanceRef wb_dati_5_1_iv_0_a2_0_RNO_7)) )) (net FWEr (joined (portRef Q (instanceRef FWEr)) - (portRef B (instanceRef nRCS_0io_RNO_0)) - (portRef C (instanceRef nRCAS_0io_RNO_0)) - (portRef C (instanceRef RCKEEN_8_u_1_0)) - (portRef C (instanceRef nRowColSel_0_0_a3_0)) + (portRef C (instanceRef RCKEEN_8_u_1)) + (portRef B (instanceRef nRowColSel_0_0_a2_1)) + (portRef B (instanceRef nRCS_9_u_i_a2_0)) + (portRef D (instanceRef nRWE_s_i_a2_2)) + (portRef B (instanceRef nRCAS_0io_RNO_1)) )) (net CASr3 (joined (portRef Q (instanceRef CASr3)) - (portRef B (instanceRef nRCAS_0io_RNO_1)) - (portRef A (instanceRef nRowColSel_0_0_a3_0)) - (portRef B (instanceRef nRWE_s_i_a2_0)) + (portRef A (instanceRef nRowColSel_0_0_a2_1)) + (portRef B (instanceRef nRWE_s_i_a2_2)) )) (net (rename IS_0 "IS[0]") (joined (portRef Q (instanceRef IS_0)) (portRef A (instanceRef IS_RNO_0)) (portRef D (instanceRef nRRAS_0io_RNO)) - (portRef A (instanceRef nRWE_0io_RNO_1)) (portRef A (instanceRef IS_n1_0_x2)) (portRef A (instanceRef Ready_0_sqmuxa_0_o2)) (portRef A (instanceRef IS_RNO_2)) (portRef A (instanceRef nRCS_9_u_i_0)) + (portRef A (instanceRef nRWE_s_i_a2_1_0)) (portRef D (instanceRef IS_RNO_3)) (portRef A (instanceRef RA10_0io_RNO)) )) (net (rename IS_3 "IS[3]") (joined (portRef Q (instanceRef IS_3)) - (portRef B (instanceRef Ready_0_sqmuxa_0_a3_2)) + (portRef B (instanceRef Ready_0_sqmuxa_0_a2_2)) (portRef C (instanceRef un1_nRCAS_6_sqmuxa_i_o2)) (portRef C (instanceRef RA10_0io_RNO_0)) (portRef A (instanceRef IS_RNO_3)) )) (net (rename IS_1 "IS[1]") (joined (portRef Q (instanceRef IS_1)) - (portRef B (instanceRef nRWE_0io_RNO_1)) (portRef B (instanceRef IS_n1_0_x2)) - (portRef A (instanceRef un1_nRCAS_6_sqmuxa_i_o2)) (portRef B (instanceRef Ready_0_sqmuxa_0_o2)) + (portRef A (instanceRef un1_nRCAS_6_sqmuxa_i_o2)) (portRef B (instanceRef IS_RNO_2)) + (portRef B (instanceRef nRWE_s_i_a2_1_0)) (portRef A (instanceRef RA10_0io_RNO_0)) (portRef C (instanceRef IS_RNO_3)) )) (net (rename IS_2 "IS[2]") (joined (portRef Q (instanceRef IS_2)) - (portRef C (instanceRef nRWE_0io_RNO_1)) - (portRef B (instanceRef un1_nRCAS_6_sqmuxa_i_o2)) (portRef C (instanceRef Ready_0_sqmuxa_0_o2)) + (portRef B (instanceRef un1_nRCAS_6_sqmuxa_i_o2)) (portRef C (instanceRef IS_RNO_2)) + (portRef C (instanceRef nRWE_s_i_a2_1_0)) (portRef B (instanceRef RA10_0io_RNO_0)) (portRef B (instanceRef IS_RNO_3)) )) (net (rename FS_15 "FS[15]") (joined (portRef Q (instanceRef FS_15)) (portRef A0 (instanceRef FS_cry_0_15)) - (portRef A (instanceRef wb_cyc_stb_2_sqmuxa_i_o2)) - (portRef B (instanceRef InitReady3_0_a2_2)) (portRef A (instanceRef FS_RNIHVJI_15)) + (portRef A (instanceRef FS_RNI82PA_15)) + (portRef B (instanceRef InitReady3_0_a2_1_0)) + (portRef A (instanceRef wb_rst_3_0_a2_0_a2)) + (portRef A (instanceRef FS_RNIHVJI_0_15)) )) (net (rename FS_16 "FS[16]") (joined (portRef Q (instanceRef FS_16)) (portRef A1 (instanceRef FS_cry_0_15)) - (portRef D (instanceRef wb_cyc_stb_2_sqmuxa_i_o2)) - (portRef C (instanceRef InitReady3_0_a2_2)) - (portRef A (instanceRef FS_RNIQV0F_16)) - (portRef D (instanceRef FS_RNIHVJI_15)) + (portRef B (instanceRef FS_RNIHVJI_15)) + (portRef B (instanceRef FS_RNI82PA_15)) + (portRef C (instanceRef InitReady3_0_a2_1_0)) + (portRef A (instanceRef un1_wb_rst14_2_0_o2)) + (portRef B (instanceRef wb_rst_3_0_a2_0_a2)) + (portRef D (instanceRef FS_RNIHVJI_0_15)) )) (net (rename FS_17 "FS[17]") (joined (portRef Q (instanceRef FS_17)) (portRef A0 (instanceRef FS_s_0_17)) - (portRef C (instanceRef wb_cyc_stb_2_sqmuxa_i_o2)) - (portRef D (instanceRef InitReady3_0_a2_2)) - (portRef B (instanceRef FS_RNIQV0F_16)) (portRef C (instanceRef FS_RNIHVJI_15)) + (portRef C (instanceRef FS_RNI82PA_15)) + (portRef D (instanceRef InitReady3_0_a2_1_0)) + (portRef B (instanceRef un1_wb_rst14_2_0_o2)) + (portRef C (instanceRef wb_rst_3_0_a2_0_a2)) + (portRef C (instanceRef FS_RNIHVJI_0_15)) )) (net (rename FS_0 "FS[0]") (joined (portRef Q (instanceRef FS_0)) (portRef A1 (instanceRef FS_cry_0_0)) - (portRef A (instanceRef wb_cyc_stb_2_sqmuxa_i_o2_0)) - (portRef A (instanceRef wb_cyc_stb_4_iv_0_a2_0)) + (portRef A (instanceRef wb_cyc_stb_4_iv_0_0_a2_0_0)) + (portRef A (instanceRef wb_cyc_stb_2_sqmuxa_i_0_0_a2_0)) )) (net (rename FS_7 "FS[7]") (joined (portRef Q (instanceRef FS_7)) (portRef A0 (instanceRef FS_cry_0_7)) - (portRef B (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_3_3)) + (portRef B (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_2_0)) )) (net (rename FS_8 "FS[8]") (joined (portRef Q (instanceRef FS_8)) (portRef A1 (instanceRef FS_cry_0_7)) - (portRef B (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_3)) + (portRef C (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_1)) )) (net (rename FS_6 "FS[6]") (joined (portRef Q (instanceRef FS_6)) (portRef A1 (instanceRef FS_cry_0_5)) - (portRef A (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_3_3)) + (portRef B (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_1)) )) (net (rename FS_2 "FS[2]") (joined (portRef Q (instanceRef FS_2)) (portRef A1 (instanceRef FS_cry_0_1)) - (portRef B (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_3_4)) + (portRef A (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_2)) )) (net (rename FS_1 "FS[1]") (joined (portRef Q (instanceRef FS_1)) (portRef A0 (instanceRef FS_cry_0_1)) - (portRef A (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_3_4)) + (portRef A (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_2_0)) )) (net (rename FS_4 "FS[4]") (joined (portRef Q (instanceRef FS_4)) (portRef A1 (instanceRef FS_cry_0_3)) - (portRef C (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_3_4)) + (portRef B (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_2)) )) (net (rename FS_5 "FS[5]") (joined (portRef Q (instanceRef FS_5)) (portRef A0 (instanceRef FS_cry_0_5)) - (portRef D (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_3_4)) + (portRef C (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_2)) )) (net (rename FS_3 "FS[3]") (joined (portRef Q (instanceRef FS_3)) (portRef A0 (instanceRef FS_cry_0_3)) - (portRef A (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_3)) + (portRef A (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_1)) )) (net PHI2r2 (joined (portRef Q (instanceRef PHI2r2)) - (portRef A (instanceRef PHI2r3_RNIFT0I_0)) (portRef A (instanceRef PHI2r3_RNIFT0I)) - (portRef B (instanceRef wb_cyc_stb_4_iv_0_RNO)) - (portRef C (instanceRef CmdValid_RNIS5A51)) + (portRef B (instanceRef wb_cyc_stb_4_iv_0_0_RNO)) + (portRef A (instanceRef PHI2r3_RNIFT0I_0)) + (portRef C (instanceRef un1_InitReady_4_i_0_a2_i)) (portRef D (instanceRef PHI2r3)) )) (net (rename FS_9 "FS[9]") (joined (portRef Q (instanceRef FS_9)) (portRef A0 (instanceRef FS_cry_0_9)) - (portRef C (instanceRef wb_adr_5_i_i_a2_11_0)) - (portRef D (instanceRef wb_dati_5_1_iv_0_0_a2_1)) - (portRef D (instanceRef wb_dati_5_1_iv_0_a2_9_1)) + (portRef C (instanceRef wb_dati_5_1_iv_0_o2_0_4)) (portRef A (instanceRef FS_RNIS637_9)) - (portRef A (instanceRef wb_dati_5_1_iv_0_o2_0_6)) - (portRef A (instanceRef wb_adr_5_i_i_a2_6_0_0)) - (portRef A (instanceRef wb_adr_5_i_i_a2_3_0_0)) - (portRef A (instanceRef wb_dati_5_1_iv_0_a2_7_1)) - (portRef A (instanceRef wb_dati_5_1_iv_0_o2_3)) - (portRef D (instanceRef wb_dati_5_1_iv_0_a2_RNO_4)) - (portRef D (instanceRef wb_we_0_0_0_a2_RNO)) - (portRef C (instanceRef wb_dati_5_1_iv_0_0_RNO_7)) - (portRef C (instanceRef wb_dati_5_1_iv_0_1_RNO_7)) + (portRef A (instanceRef FS_RNIF2MA_9)) + (portRef A (instanceRef wb_dati_5_1_iv_0_0_4)) + (portRef A (instanceRef wb_dati_5_1_iv_0_1_0_4)) + (portRef A (instanceRef wb_dati_5_1_iv_0_o2_0_7)) + (portRef A (instanceRef wb_dati_5_1_iv_0_0_a2_1_3)) + (portRef A (instanceRef wb_adr_5_i_0_o2_0)) + (portRef A (instanceRef wb_dati_5_1_iv_0_a2_0_7)) + (portRef A (instanceRef wb_dati_5_1_iv_0_a2_12_3)) + (portRef A (instanceRef wb_adr_5_i_0_3_0)) + (portRef C0 (instanceRef wb_dati_5_1_iv_0_0_o2_5)) + (portRef B (instanceRef wb_adr_5_i_0_1_am_0)) + (portRef D (instanceRef wb_dati_5_1_iv_0_RNO_7)) + (portRef D (instanceRef wb_dati_5_1_iv_0_1_RNO_7)) + (portRef D (instanceRef FS_RNIOVGI_9)) )) (net (rename FS_10 "FS[10]") (joined (portRef Q (instanceRef FS_10)) (portRef A1 (instanceRef FS_cry_0_9)) - (portRef A (instanceRef wb_adr_5_i_i_a2_11_0)) - (portRef C (instanceRef wb_dati_5_1_iv_0_a2_9_1)) + (portRef B (instanceRef wb_dati_5_1_iv_0_o2_0_4)) (portRef B (instanceRef FS_RNIS637_9)) - (portRef B (instanceRef wb_dati_5_1_iv_0_o2_0_6)) - (portRef A (instanceRef InitReady3_0_a2_2)) - (portRef B (instanceRef wb_adr_5_i_i_a2_6_0_0)) - (portRef A (instanceRef wb_dati_5_1_iv_0_a2_1_1_7)) - (portRef A (instanceRef wb_adr_5_i_i_1_0_tz_0_0)) - (portRef A (instanceRef wb_dati_5_1_iv_0_0_o2_1)) - (portRef B (instanceRef wb_dati_5_1_iv_0_o2_3)) - (portRef A (instanceRef wb_adr_5_i_i_a2_7_0)) - (portRef C (instanceRef wb_dati_5_1_iv_0_a2_RNO_4)) - (portRef C (instanceRef wb_we_0_0_0_a2_RNO)) - (portRef B (instanceRef wb_dati_5_1_iv_0_0_RNO_7)) - (portRef B (instanceRef wb_dati_5_1_iv_0_1_RNO_7)) + (portRef B (instanceRef FS_RNIF2MA_9)) + (portRef B (instanceRef wb_dati_5_1_iv_0_1_0_4)) + (portRef A (instanceRef InitReady3_0_a2_1_0)) + (portRef B (instanceRef wb_dati_5_1_iv_0_o2_0_7)) + (portRef B (instanceRef wb_dati_5_1_iv_0_0_a2_1_3)) + (portRef B (instanceRef wb_adr_5_i_0_o2_0)) + (portRef A (instanceRef wb_dati_5_1_iv_0_a2_5_7)) + (portRef A (instanceRef wb_dati_5_0_iv_0_a2_1_0)) + (portRef A (instanceRef wb_dati_5_1_iv_0_0_o2_3)) + (portRef A (instanceRef wb_dati_5_1_iv_0_0_o2_4)) + (portRef B (instanceRef wb_dati_5_1_iv_0_a2_0_7)) + (portRef A (instanceRef wb_dati_5_1_iv_0_a2_2_4)) + (portRef A (instanceRef wb_adr_5_i_0_1_am_0)) + (portRef C (instanceRef wb_dati_5_1_iv_0_RNO_7)) + (portRef C (instanceRef FS_RNIOVGI_9)) )) (net (rename FS_11 "FS[11]") (joined (portRef Q (instanceRef FS_11)) (portRef A0 (instanceRef FS_cry_0_11)) - (portRef B (instanceRef wb_dati_5_1_iv_0_a2_9_1)) - (portRef D (instanceRef wb_dati_5_1_iv_0_a2_3_2_7)) - (portRef A (instanceRef FS_RNI7O57_11)) - (portRef A (instanceRef wb_dati_5_1_iv_0_1_7)) - (portRef A (instanceRef wb_dati_5_1_iv_0_a2_2_6)) - (portRef A (instanceRef wb_dati_5_0_iv_0_a2_0_0_0)) - (portRef B (instanceRef wb_adr_5_i_i_a2_3_0_0)) - (portRef A (instanceRef wb_dati_5_1_iv_0_a2_1_0_6)) - (portRef B (instanceRef wb_dati_5_1_iv_0_a2_1_1_7)) - (portRef B (instanceRef wb_adr_5_i_i_1_0_tz_0_0)) - (portRef B (instanceRef wb_dati_5_1_iv_0_0_o2_1)) - (portRef A (instanceRef wb_adr_5_i_i_a2_0_1_1)) - (portRef C (instanceRef wb_dati_5_1_iv_0_o2_3)) - (portRef B (instanceRef wb_adr_5_i_i_a2_7_0)) - (portRef A (instanceRef wb_dati_5_1_iv_0_a2_1_3)) - (portRef A (instanceRef wb_dati_5_1_iv_0_a2_0_1)) - (portRef A (instanceRef wb_adr_5_i_i_0)) - (portRef B (instanceRef wb_dati_5_1_iv_0_a2_RNO_4)) - (portRef B (instanceRef wb_we_0_0_0_a2_RNO)) + (portRef A (instanceRef wb_dati_5_1_iv_0_o2_0_4)) + (portRef C (instanceRef FS_RNIF2MA_9)) + (portRef A (instanceRef InitReady3_0_a2)) + (portRef A (instanceRef wb_dati_5_1_iv_0_a2_6_4)) + (portRef C (instanceRef wb_dati_5_1_iv_0_0_a2_1_3)) + (portRef C (instanceRef wb_adr_5_i_0_o2_0)) + (portRef B (instanceRef wb_dati_5_1_iv_0_a2_5_7)) + (portRef A (instanceRef wb_dati_5_1_iv_0_a2_0_2_1)) + (portRef B (instanceRef wb_dati_5_1_iv_0_0_o2_3)) + (portRef B (instanceRef wb_dati_5_1_iv_0_0_o2_4)) + (portRef A (instanceRef wb_dati_5_1_iv_0_a2_7_3)) + (portRef A (instanceRef wb_dati_5_1_iv_0_a2_5_3)) + (portRef A (instanceRef wb_dati_5_1_iv_0_0_a2_6)) + (portRef A (instanceRef wb_dati_5_1_iv_0_1)) + (portRef A (instanceRef wb_dati_5_1_iv_0_0_6)) + (portRef C0 (instanceRef wb_adr_5_i_0_1_0)) + (portRef B (instanceRef wb_dati_5_1_iv_0_RNO_7)) + (portRef C (instanceRef wb_adr_RNO_0_1)) + (portRef B (instanceRef FS_RNIOVGI_9)) )) (net (rename FS_12 "FS[12]") (joined (portRef Q (instanceRef FS_12)) + (portRef (member fs 2) (instanceRef ufmefb)) (portRef A1 (instanceRef FS_cry_0_11)) - (portRef A (instanceRef wb_dati_5_1_iv_0_a2_9_1)) - (portRef C (instanceRef wb_dati_5_1_iv_0_a2_3_2_7)) - (portRef B (instanceRef FS_RNI7O57_11)) - (portRef B (instanceRef wb_dati_5_1_iv_0_a2_2_6)) - (portRef B (instanceRef wb_dati_5_0_iv_0_a2_0_0_0)) - (portRef C (instanceRef wb_adr_5_i_i_a2_6_0_0)) - (portRef C (instanceRef wb_adr_5_i_i_a2_3_0_0)) - (portRef B (instanceRef wb_dati_5_1_iv_0_a2_1_0_6)) - (portRef C (instanceRef wb_dati_5_1_iv_0_a2_1_1_7)) - (portRef C (instanceRef wb_dati_5_1_iv_0_0_o2_1)) - (portRef B (instanceRef wb_adr_5_i_i_a2_0_1_1)) - (portRef A (instanceRef wb_adr_5_i_i_a2_0)) - (portRef D (instanceRef wb_dati_5_1_iv_0_o2_3)) - (portRef A (instanceRef wb_reqe_RNO)) - (portRef A (instanceRef wb_we_0_0_0_0)) - (portRef A (instanceRef wb_adr_5_i_i_1_0_0)) - (portRef B (instanceRef wb_dati_5_1_iv_0_a2_1_3)) - (portRef A (instanceRef wb_adr_5_i_i_a2_5_0)) - (portRef B (instanceRef wb_dati_5_1_iv_0_a2_0_1)) - (portRef A (instanceRef wb_dati_5_1_iv_0_a2_RNO_4)) - (portRef A (instanceRef wb_dati_5_1_iv_0_1_RNO_7)) + (portRef A (instanceRef wb_dati_5_1_iv_0_a2_13_3)) + (portRef A (instanceRef FS_RNI9Q57_12)) + (portRef A (instanceRef FS_RNIGOCT_12)) + (portRef A (instanceRef wb_dati_5_1_iv_0_a2_7_4)) + (portRef A (instanceRef wb_dati_5_1_iv_0_a2_11_3)) + (portRef B (instanceRef wb_dati_5_0_iv_0_a2_1_0)) + (portRef A (instanceRef wb_we_0_0_i_a2_0)) + (portRef C (instanceRef wb_dati_5_1_iv_0_0_o2_3)) + (portRef A (instanceRef wb_adr_5_i_3_0_a2_1)) + (portRef B (instanceRef wb_dati_5_1_iv_0_a2_7_3)) + (portRef D (instanceRef wb_dati_5_1_iv_0_0_o2_bm_5)) + (portRef B (instanceRef wb_dati_5_1_iv_0_1_RNO_7)) + (portRef D (instanceRef wb_dati_5_1_iv_0_o2_0_RNIMDJC1_4)) + (portRef D (instanceRef wb_reqe_RNO)) + (portRef D (instanceRef wb_adr_RNO_0_1)) + (portRef A (instanceRef FS_RNIJO0F_12)) + (portRef C (instanceRef wb_dati_5_1_iv_0_a2_0_RNO_7)) )) (net (rename FS_13 "FS[13]") (joined (portRef Q (instanceRef FS_13)) (portRef (member fs 1) (instanceRef ufmefb)) (portRef A0 (instanceRef FS_cry_0_13)) - (portRef B (instanceRef wb_dati_5_1_iv_0_a2_4)) - (portRef B (instanceRef wb_dati_5_1_iv_0_0_a2_1)) - (portRef B (instanceRef wb_dati_5_1_iv_0_a2_3_2_7)) - (portRef A (instanceRef FS_RNI1FVB_14)) - (portRef A (instanceRef FS_RNITL2J_14)) - (portRef A (instanceRef wb_dati_5_1_iv_0_o2_7)) - (portRef C (instanceRef wb_dati_5_0_iv_0_a2_0_0_0)) - (portRef C (instanceRef wb_dati_5_1_iv_0_a2_1_0_6)) - (portRef C (instanceRef wb_adr_5_i_i_1_0_tz_0_0)) - (portRef A (instanceRef InitReady3_0_a2)) - (portRef C (instanceRef wb_adr_5_i_i_a2_0_1_1)) - (portRef A (instanceRef wb_we_0_0_0_a2_2)) - (portRef B (instanceRef wb_adr_5_i_i_a2_0)) - (portRef A (instanceRef wb_dati_5_1_iv_0_a2_2_1)) - (portRef B (instanceRef wb_reqe_RNO)) - (portRef C (instanceRef wb_adr_5_i_i_a2_7_0)) - (portRef A (instanceRef wb_dati_5_1_iv_0_a2_0_7)) - (portRef B (instanceRef wb_adr_5_i_i_a2_5_0)) - (portRef A (instanceRef wb_dati_5_1_iv_0_1_3)) - (portRef A (instanceRef wb_we_0_0_0_a2_RNO)) + (portRef B (instanceRef FS_RNI9Q57_12)) + (portRef B (instanceRef FS_RNIGOCT_12)) + (portRef B (instanceRef wb_dati_5_1_iv_0_a2_11_3)) + (portRef B (instanceRef wb_dati_5_1_iv_0_a2_6_4)) + (portRef D (instanceRef wb_dati_5_1_iv_0_0_a2_1_3)) + (portRef C (instanceRef wb_dati_5_1_iv_0_a2_5_7)) + (portRef B (instanceRef wb_dati_5_1_iv_0_a2_0_2_1)) + (portRef B (instanceRef wb_we_0_0_i_a2_0)) + (portRef C (instanceRef wb_dati_5_1_iv_0_0_o2_4)) + (portRef A (instanceRef wb_adr_5_i_3_0_a2_0_1)) + (portRef B (instanceRef wb_adr_5_i_3_0_a2_1)) + (portRef A (instanceRef wb_dati_5_1_iv_0_0_1_3)) + (portRef A (instanceRef wb_dati_5_1_iv_0_1_1)) + (portRef B (instanceRef wb_dati_5_1_iv_0_0_a2_6)) + (portRef D (instanceRef wb_dati_5_1_iv_0_0_o2_am_5)) + (portRef C (instanceRef wb_adr_5_i_0_1_bm_0)) + (portRef C (instanceRef wb_dati_5_1_iv_0_o2_0_RNIMDJC1_4)) + (portRef C (instanceRef wb_reqe_RNO)) + (portRef B (instanceRef wb_adr_5_i_0_2_RNO_0_0)) )) (net CASr2 (joined (portRef Q (instanceRef CASr2)) - (portRef A (instanceRef nRCAS_0io_RNO_1)) - (portRef A (instanceRef RCKEEN_8_u_1_0)) - (portRef A (instanceRef nRWE_s_i_a2_0)) + (portRef A (instanceRef RCKEEN_8_u_1)) + (portRef A (instanceRef RCKEEN_8_u_0_o3)) + (portRef A (instanceRef nRWE_s_i_a2_2)) (portRef D (instanceRef CASr3)) + (portRef C (instanceRef nRCAS_0io_RNO_2)) )) (net CASr (joined (portRef Q (instanceRef CASr)) @@ -2267,63 +2345,63 @@ )) (net (rename Bank_0 "Bank[0]") (joined (portRef Q (instanceRef Bank_0io_0)) - (portRef A (instanceRef un1_ADWR_i_o2_10)) + (portRef A (instanceRef un1_CmdEnable20_0_0_o2)) )) (net (rename Bank_1 "Bank[1]") (joined (portRef Q (instanceRef Bank_0io_1)) - (portRef A (instanceRef un1_ADWR_i_o2)) + (portRef A (instanceRef un1_CmdEnable20_0_0_o2_10)) )) (net (rename Bank_3 "Bank[3]") (joined (portRef Q (instanceRef Bank_0io_3)) - (portRef B (instanceRef un1_ADWR_i_o2)) + (portRef B (instanceRef un1_CmdEnable20_0_0_o2_11)) )) (net (rename Bank_4 "Bank[4]") (joined (portRef Q (instanceRef Bank_0io_4)) - (portRef A (instanceRef un1_ADWR_i_o2_11)) + (portRef B (instanceRef un1_CmdEnable20_0_0_o2)) )) (net (rename Bank_5 "Bank[5]") (joined (portRef Q (instanceRef Bank_0io_5)) - (portRef B (instanceRef un1_ADWR_i_o2_11)) + (portRef C (instanceRef un1_CmdEnable20_0_0_o2_11)) )) (net (rename Bank_6 "Bank[6]") (joined (portRef Q (instanceRef Bank_0io_6)) - (portRef C (instanceRef un1_ADWR_i_o2_11)) + (portRef D (instanceRef un1_CmdEnable20_0_0_o2_11)) )) (net (rename Bank_7 "Bank[7]") (joined (portRef Q (instanceRef Bank_0io_7)) - (portRef D (instanceRef un1_ADWR_i_o2_11)) + (portRef B (instanceRef un1_CmdEnable20_0_0_o2_10)) )) (net (rename RowA_0 "RowA[0]") (joined (portRef Q (instanceRef RowA_0)) - (portRef B (instanceRef un9_RA_i_m2_0)) + (portRef B (instanceRef un9_RA_i_m2_i_m2_0)) )) (net (rename RowA_1 "RowA[1]") (joined (portRef Q (instanceRef RowA_1)) - (portRef B (instanceRef un9_RA_i_m2_1)) + (portRef B (instanceRef un9_RA_i_m2_i_m2_1)) )) (net (rename RowA_2 "RowA[2]") (joined (portRef Q (instanceRef RowA_2)) - (portRef B (instanceRef un9_RA_i_m2_2)) + (portRef B (instanceRef un9_RA_i_m2_i_m2_2)) )) (net (rename RowA_3 "RowA[3]") (joined (portRef Q (instanceRef RowA_3)) - (portRef B (instanceRef un9_RA_i_m2_3)) + (portRef B (instanceRef un9_RA_i_m2_i_m2_3)) )) (net (rename RowA_4 "RowA[4]") (joined (portRef Q (instanceRef RowA_4)) - (portRef B (instanceRef un9_RA_i_m2_4)) + (portRef B (instanceRef un9_RA_i_m2_i_m2_4)) )) (net (rename RowA_5 "RowA[5]") (joined (portRef Q (instanceRef RowA_5)) - (portRef B (instanceRef un9_RA_i_m2_5)) + (portRef B (instanceRef un9_RA_i_m2_i_m2_5)) )) (net (rename RowA_6 "RowA[6]") (joined (portRef Q (instanceRef RowA_6)) - (portRef B (instanceRef un9_RA_i_m2_6)) + (portRef B (instanceRef un9_RA_i_m2_i_m2_6)) )) (net (rename RowA_7 "RowA[7]") (joined (portRef Q (instanceRef RowA_7)) - (portRef B (instanceRef un9_RA_i_m2_7)) + (portRef B (instanceRef un9_RA_i_m2_i_m2_7)) )) (net (rename RowA_8 "RowA[8]") (joined (portRef Q (instanceRef RowA_8)) @@ -2331,7 +2409,7 @@ )) (net (rename RowA_9 "RowA[9]") (joined (portRef Q (instanceRef RowA_9)) - (portRef B (instanceRef un9_RA_i_m2_9)) + (portRef B (instanceRef un9_RA_i_m2_i_m2_9)) )) (net (rename WRD_0 "WRD[0]") (joined (portRef Q (instanceRef WRD_0io_0)) @@ -2367,17 +2445,17 @@ )) (net nRowColSel (joined (portRef Q (instanceRef nRowColSel)) - (portRef B (instanceRef RDQML_0)) + (portRef B (instanceRef RDQML_0_0)) (portRef C (instanceRef un9_RA_8)) - (portRef C (instanceRef un9_RA_i_m2_0)) - (portRef C (instanceRef un9_RA_i_m2_1)) - (portRef C (instanceRef un9_RA_i_m2_2)) - (portRef C (instanceRef un9_RA_i_m2_3)) - (portRef C (instanceRef un9_RA_i_m2_4)) - (portRef C (instanceRef un9_RA_i_m2_5)) - (portRef C (instanceRef un9_RA_i_m2_6)) - (portRef C (instanceRef un9_RA_i_m2_7)) - (portRef C (instanceRef un9_RA_i_m2_9)) + (portRef C (instanceRef un9_RA_i_m2_i_m2_2)) + (portRef C (instanceRef un9_RA_i_m2_i_m2_3)) + (portRef C (instanceRef un9_RA_i_m2_i_m2_9)) + (portRef C (instanceRef un9_RA_i_m2_i_m2_7)) + (portRef C (instanceRef un9_RA_i_m2_i_m2_6)) + (portRef C (instanceRef un9_RA_i_m2_i_m2_5)) + (portRef C (instanceRef un9_RA_i_m2_i_m2_4)) + (portRef C (instanceRef un9_RA_i_m2_i_m2_1)) + (portRef C (instanceRef un9_RA_i_m2_i_m2_0)) (portRef B (instanceRef RDQMH_pad_RNO)) )) (net RASr3 (joined @@ -2388,39 +2466,38 @@ (portRef Q (instanceRef LEDEN)) (portRef A (instanceRef LEDENe)) (portRef B (instanceRef LED_pad_RNO)) - (portRef B (instanceRef XOR8MEG_3_u_0_0)) + (portRef B (instanceRef XOR8MEG_3_u_0_0_0)) (portRef B (instanceRef CmdLEDEN_RNO)) )) (net CmdLEDEN (joined (portRef Q (instanceRef CmdLEDEN)) (portRef A (instanceRef LEDEN_6_i_m2)) - (portRef A (instanceRef CmdLEDEN_4_u_i_0)) + (portRef A (instanceRef CmdLEDEN_4_u_i_m2_i_0)) )) (net Cmdn8MEGEN (joined (portRef Q (instanceRef Cmdn8MEGEN)) (portRef A (instanceRef n8MEGEN_RNO_0)) - (portRef B (instanceRef Cmdn8MEGEN_4_u_i_0)) + (portRef B (instanceRef Cmdn8MEGEN_4_u_i_m2_i_0)) )) (net PHI2r3 (joined (portRef Q (instanceRef PHI2r3)) - (portRef B (instanceRef PHI2r3_RNIFT0I_0)) (portRef B (instanceRef PHI2r3_RNIFT0I)) - (portRef C (instanceRef wb_cyc_stb_4_iv_0_RNO)) - (portRef D (instanceRef CmdValid_RNIS5A51)) + (portRef C (instanceRef wb_cyc_stb_4_iv_0_0_RNO)) + (portRef B (instanceRef PHI2r3_RNIFT0I_0)) + (portRef D (instanceRef un1_InitReady_4_i_0_a2_i)) )) (net CmdValid (joined (portRef Q (instanceRef CmdValid)) - (portRef A (instanceRef wb_cyc_stb_4_iv_0_RNO)) - (portRef A (instanceRef CmdValid_RNITBH02)) - (portRef A (instanceRef CmdValid_RNIS5A51)) + (portRef A (instanceRef wb_cyc_stb_4_iv_0_0_RNO)) + (portRef A (instanceRef CmdValid_RNIOOBE2)) + (portRef A (instanceRef un1_InitReady_4_i_0_a2_i)) )) (net CmdUFMData (joined (portRef Q (instanceRef CmdUFMData)) - (portRef A (instanceRef wb_we_0_0_0)) + (portRef A (instanceRef wb_we_RNO)) )) (net wb_rst10 (joined - (portRef Z (instanceRef FS_RNIHVJI_15)) - (portRef D (instanceRef wb_rste)) + (portRef Z (instanceRef FS_RNIHVJI_0_15)) (portRef CD (instanceRef wb_cyc_stb)) (portRef CD (instanceRef wb_req)) (portRef CD (instanceRef wb_we)) @@ -2436,34 +2513,41 @@ (net XOR8MEG (joined (portRef Q (instanceRef XOR8MEG)) (portRef C (instanceRef RA11d)) - (portRef D (instanceRef XOR8MEG_3_u_0_a2)) + (portRef D (instanceRef XOR8MEG_3_u_0_0_0_a2)) )) (net nRRAS_0_sqmuxa (joined - (portRef Z (instanceRef S_RNICVV51_0)) - (portRef D (instanceRef nRWE_0io_RNO_0)) + (portRef Z (instanceRef S_RNICVV51_1)) + (portRef C (instanceRef nRWE_s_i_tz_0)) (portRef CD (instanceRef nRowColSel)) )) (net wb_req (joined (portRef Q (instanceRef wb_req)) (portRef C (instanceRef wb_reqe)) - (portRef B (instanceRef wb_cyc_stb_2_sqmuxa_i_o2_0)) - (portRef D (instanceRef wb_cyc_stb_4_iv_0_a2_0)) + (portRef B (instanceRef wb_cyc_stb_4_iv_0_0_a2_0_0)) + (portRef C (instanceRef wb_cyc_stb_2_sqmuxa_i_0_0_a2_0)) )) (net Ready_0_sqmuxa (joined - (portRef Z (instanceRef Ready_0_sqmuxa_0_a3)) + (portRef Z (instanceRef Ready_0_sqmuxa_0_a2)) (portRef A (instanceRef Ready_fast_RNO)) )) + (net wb_rst_3 (joined + (portRef Z (instanceRef wb_rst_3_0_a2_0_a2)) + (portRef C (instanceRef wb_rste)) + )) (net RCKE_2 (joined (portRef Z (instanceRef RCKE_2_0)) (portRef D (instanceRef RCKE)) )) (net nRCAS_0_sqmuxa_1 (joined - (portRef Z (instanceRef nRCAS_0_sqmuxa_1_0_a3)) - (portRef D (instanceRef nRWE_0io_RNO)) - (portRef B (instanceRef nRCAS_0io_RNO)) + (portRef Z (instanceRef CBR_fast_RNIQ31K1)) + (portRef B (instanceRef nRCAS_0io_RNO_0)) + (portRef A (instanceRef nRWE_0io_RNO)) )) (net XOR8MEG18 (joined - (portRef Z (instanceRef XOR8MEG18_0_a2)) + (portRef Z (instanceRef CmdUFMData_1_sqmuxa_0_a2_3)) + (portRef A (instanceRef CmdValid_r_fast)) + (portRef A (instanceRef CmdValid_r)) + (portRef B (instanceRef CmdUFMData_1_sqmuxa_0_a2)) (portRef SP (instanceRef CmdLEDEN)) (portRef SP (instanceRef CmdUFMShift)) (portRef SP (instanceRef CmdUFMWrite)) @@ -2472,24 +2556,23 @@ )) (net CmdEnable (joined (portRef Q (instanceRef CmdEnable)) - (portRef C (instanceRef CmdEnable_RNI7PMB1)) - (portRef B (instanceRef XOR8MEG18_0_a2)) - (portRef A (instanceRef CmdUFMData_1_sqmuxa_0_a2)) + (portRef A (instanceRef CmdUFMData_1_sqmuxa_0_a2_3)) (portRef A (instanceRef CmdEnable_s)) )) (net CmdUFMWrite (joined (portRef Q (instanceRef CmdUFMWrite)) - (portRef A (instanceRef CmdUFMWrite_3_u_0_a2)) - (portRef A (instanceRef wb_cyc_stb_4_iv_0)) + (portRef A (instanceRef CmdUFMWrite_3_u_0_0_0_a2)) + (portRef A (instanceRef wb_cyc_stb_4_iv_0_0)) )) (net CmdEnable16 (joined - (portRef Z (instanceRef CmdEnable16_0_a2)) - (portRef D (instanceRef ADSubmitted_r_0)) + (portRef Z (instanceRef CmdEnable16_0_a2_1_a2)) + (portRef D (instanceRef ADSubmitted_r_0_0)) + (portRef B (instanceRef CmdEnable_0_sqmuxa_0_a2_0_a2)) (portRef A (instanceRef C1Submitted_RNO)) )) (net CmdEnable17 (joined - (portRef Z (instanceRef CmdEnable17_0_a2)) - (portRef C (instanceRef ADSubmitted_r_0)) + (portRef Z (instanceRef un1_CmdEnable20_0_0_a2_3_RNIJ3N91)) + (portRef C (instanceRef ADSubmitted_r_0_0)) (portRef B (instanceRef CmdEnable_s)) )) (net CmdUFMData_1_sqmuxa (joined @@ -2498,15 +2581,15 @@ )) (net ADSubmitted (joined (portRef Q (instanceRef ADSubmitted)) - (portRef A (instanceRef ADSubmitted_r_0)) - (portRef A (instanceRef CmdEnable_0_sqmuxa_0_a2)) + (portRef A (instanceRef ADSubmitted_r_0_0)) + (portRef A (instanceRef CmdEnable_0_sqmuxa_0_a2_0_a2)) )) (net CmdEnable_0_sqmuxa (joined - (portRef Z (instanceRef CmdEnable_0_sqmuxa_0_a2)) + (portRef Z (instanceRef CmdEnable_0_sqmuxa_0_a2_0_a2)) (portRef D (instanceRef CmdEnable_s)) )) (net wb_cyc_stb_4 (joined - (portRef Z (instanceRef wb_cyc_stb_4_iv_0)) + (portRef Z (instanceRef wb_cyc_stb_4_iv_0_0)) (portRef D (instanceRef wb_cyc_stb)) )) (net (rename wb_dati_5_0 "wb_dati_5[0]") (joined @@ -2514,21 +2597,33 @@ (portRef D (instanceRef wb_dati_0)) )) (net (rename wb_dati_5_1 "wb_dati_5[1]") (joined - (portRef Z (instanceRef wb_dati_5_1_iv_0_0_1)) + (portRef Z (instanceRef wb_dati_5_1_iv_0_1)) (portRef D (instanceRef wb_dati_1)) )) (net (rename wb_dati_5_2 "wb_dati_5[2]") (joined - (portRef Z (instanceRef wb_dati_5_1_iv_0_2)) + (portRef Z (instanceRef wb_dati_5_1_iv_0_0_2)) (portRef D (instanceRef wb_dati_2)) )) + (net (rename wb_dati_5_3 "wb_dati_5[3]") (joined + (portRef Z (instanceRef wb_dati_5_1_iv_0_0_3)) + (portRef D (instanceRef wb_dati_3)) + )) (net (rename wb_dati_5_4 "wb_dati_5[4]") (joined - (portRef Z (instanceRef wb_dati_5_1_iv_0_4)) + (portRef Z (instanceRef wb_dati_5_1_iv_0_0_4)) (portRef D (instanceRef wb_dati_4)) )) (net (rename wb_dati_5_5 "wb_dati_5[5]") (joined - (portRef Z (instanceRef wb_dati_5_1_iv_0_5)) + (portRef Z (instanceRef wb_dati_5_1_iv_0_0_5)) (portRef D (instanceRef wb_dati_5)) )) + (net (rename wb_dati_5_6 "wb_dati_5[6]") (joined + (portRef Z (instanceRef wb_dati_5_1_iv_0_0_6)) + (portRef D (instanceRef wb_dati_6)) + )) + (net (rename wb_dati_5_7 "wb_dati_5[7]") (joined + (portRef Z (instanceRef wb_dati_5_1_iv_0_7)) + (portRef D (instanceRef wb_dati_7)) + )) (net CmdValid_r (joined (portRef Z (instanceRef CmdValid_r)) (portRef D (instanceRef CmdValid)) @@ -2537,80 +2632,117 @@ (portRef Z (instanceRef C1Submitted_RNO)) (portRef D (instanceRef C1Submitted)) )) - (net ADSubmitted_r_0 (joined - (portRef Z (instanceRef ADSubmitted_r_0)) + (net ADSubmitted_r_0_0 (joined + (portRef Z (instanceRef ADSubmitted_r_0_0)) (portRef D (instanceRef ADSubmitted)) )) (net CmdEnable_s (joined (portRef Z (instanceRef CmdEnable_s)) (portRef D (instanceRef CmdEnable)) )) - (net wb_we_0_0_0 (joined - (portRef Z (instanceRef wb_we_0_0_0)) - (portRef D (instanceRef wb_we)) - )) (net nRowColSel_0_0 (joined (portRef Z (instanceRef nRowColSel_0_0)) (portRef D (instanceRef nRowColSel)) )) - (net XOR8MEG_3 (joined - (portRef Z (instanceRef XOR8MEG_3_u_0_0)) - (portRef D (instanceRef XOR8MEG)) + (net (rename wb_adr_5_2 "wb_adr_5[2]") (joined + (portRef Z (instanceRef wb_adr_5_2)) + (portRef D (instanceRef wb_adr_2)) )) - (net CmdUFMShift_3 (joined - (portRef Z (instanceRef CmdUFMShift_3_u_0_0)) - (portRef D (instanceRef CmdUFMShift)) + (net (rename wb_adr_5_3 "wb_adr_5[3]") (joined + (portRef Z (instanceRef wb_adr_5_3)) + (portRef D (instanceRef wb_adr_3)) )) - (net CmdUFMWrite_3 (joined - (portRef Z (instanceRef CmdUFMWrite_3_u_0_0)) - (portRef D (instanceRef CmdUFMWrite)) + (net (rename wb_adr_5_7 "wb_adr_5[7]") (joined + (portRef Z (instanceRef wb_adr_5_7)) + (portRef D (instanceRef wb_adr_7)) )) (net RCKEEN_8 (joined (portRef Z (instanceRef RCKEEN_8_u)) (portRef D (instanceRef RCKEEN)) )) - (net (rename wb_adr_5_i_m2_0_6 "wb_adr_5_i_m2_0[6]") (joined - (portRef Z (instanceRef wb_adr_5_i_m2_0_6)) - (portRef D (instanceRef wb_adr_6)) + (net wb_cyc_stb_2_sqmuxa_i_0_0 (joined + (portRef Z (instanceRef wb_cyc_stb_2_sqmuxa_i_0_0)) + (portRef SP (instanceRef wb_cyc_stb)) )) - (net N_80 (joined - (portRef Z (instanceRef wb_adr_5_i_m2_0_5)) - (portRef D (instanceRef wb_adr_5)) - )) - (net N_81 (joined - (portRef Z (instanceRef wb_adr_5_i_m2_0_4)) - (portRef D (instanceRef wb_adr_4)) - )) - (net N_39 (joined + (net N_48 (joined (portRef Z (instanceRef un1_nRCAS_6_sqmuxa_i_0)) - (portRef A (instanceRef nRCAS_0io_RNO)) + (portRef A (instanceRef nRCAS_0io_RNO_0)) + (portRef A (instanceRef nRCAS_0io_RNO_2)) )) - (net N_41 (joined - (portRef Z (instanceRef S_0_i_o2_1)) + (net (rename S_0_i_o3_1 "S_0_i_o3[1]") (joined + (portRef Z (instanceRef S_0_i_o3_1)) (portRef A (instanceRef nRCS_9_u_i_0_0)) - (portRef B (instanceRef nRCAS_0_sqmuxa_1_0_a3)) (portRef D (instanceRef S_1)) (portRef D (instanceRef RCKEEN_8_u_RNO)) )) (net IS_0_sqmuxa_0_o2 (joined (portRef Z (instanceRef IS_0_sqmuxa_0_o2)) - (portRef C (instanceRef nRWE_0io_RNO_0)) + (portRef C (instanceRef IS_RNO_0)) + (portRef B (instanceRef IS_0_sqmuxa_0_o2_RNIDJQJ)) + (portRef C (instanceRef nRRAS_0io_RNO)) + (portRef A (instanceRef IS_0_sqmuxa_0_o3)) + (portRef A (instanceRef un1_nRCAS_6_sqmuxa_i_0)) + (portRef B (instanceRef nRCS_9_u_i_0)) + )) + (net IS_0_sqmuxa_0_o3 (joined + (portRef Z (instanceRef IS_0_sqmuxa_0_o3)) + (portRef D (instanceRef nRWE_s_i_a2_1_0)) (portRef D (instanceRef RA10_0io_RNO_0)) )) - (net N_53_i (joined + (net RCKEEN_8_u_0_o3 (joined + (portRef Z (instanceRef RCKEEN_8_u_0_o3)) + (portRef C (instanceRef nRCAS_0io_RNO_1)) + )) + (net un1_nRCAS_6_sqmuxa_i_o2 (joined + (portRef Z (instanceRef un1_nRCAS_6_sqmuxa_i_o2)) + (portRef B (instanceRef nRRAS_0io_RNO)) + (portRef B (instanceRef un1_nRCAS_6_sqmuxa_i_0)) + (portRef C (instanceRef nRCS_9_u_i_0)) + )) + (net Ready_0_sqmuxa_0_o2 (joined + (portRef Z (instanceRef Ready_0_sqmuxa_0_o2)) + (portRef B (instanceRef Ready_0_sqmuxa_0_a2)) + (portRef C (instanceRef Ready_RNO)) + )) + (net N_251_i_1 (joined + (portRef Z (instanceRef nRCS_9_u_i_a2_0)) + (portRef A (instanceRef nRCAS_0io_RNO)) + (portRef C (instanceRef nRCS_0io_RNO)) + )) + (net N_251_i_1_0 (joined + (portRef Z (instanceRef nRowColSel_0_0_a2_1)) + (portRef B (instanceRef nRCAS_0io_RNO)) + (portRef C (instanceRef nRowColSel_0_0)) + )) + (net N_141 (joined + (portRef Z (instanceRef RCKEEN_8_u_0_a2_2)) + (portRef A (instanceRef nRCS_0io_RNO)) + (portRef B (instanceRef nRWE_0io_RNO)) + )) + (net N_142 (joined + (portRef Z (instanceRef nRWE_s_i_a2_2)) + (portRef B (instanceRef nRCS_0io_RNO)) + (portRef C (instanceRef nRWE_0io_RNO)) + )) + (net N_69_i (joined (portRef Z (instanceRef IS_n1_0_x2)) (portRef D (instanceRef IS_1)) )) - (net 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(instanceRef nRRAS_0io_RNO)) - (portRef B (instanceRef un1_nRCAS_6_sqmuxa_i_0)) - (portRef C (instanceRef nRCS_9_u_i_0)) - )) - (net N_255 (joined - (portRef Z (instanceRef nRowColSel_0_0_a3_0)) - (portRef B (instanceRef nRowColSel_0_0)) - )) - (net (rename wb_adr_5_i_i_a2_0_1 "wb_adr_5_i_i_a2_0[1]") (joined - (portRef Z (instanceRef wb_adr_5_i_i_a2_0_1_1)) - (portRef C (instanceRef wb_adr_5_i_i_0_RNO_1)) - )) - (net N_428_tz (joined - (portRef Z (instanceRef wb_adr_5_i_i_0_RNO_1)) - (portRef C (instanceRef wb_adr_5_i_i_0_1)) - )) - (net (rename wb_adr_5_i_i_a2_3_0_0 "wb_adr_5_i_i_a2_3_0[0]") (joined - (portRef Z (instanceRef wb_adr_5_i_i_a2_3_0_0)) - (portRef D (instanceRef wb_adr_5_i_i_1_0_tz_0_0)) + (net nRWE_s_i_a2_1_0 (joined + (portRef Z (instanceRef nRWE_s_i_a2_1_0)) + (portRef D (instanceRef nRWE_s_i_tz_0)) )) (net RCKEEN_8_u_0_0 (joined (portRef Z (instanceRef RCKEEN_8_u_RNO)) (portRef B (instanceRef RCKEEN_8_u)) )) - (net (rename wb_adr_5_i_i_1_0_0 "wb_adr_5_i_i_1_0[0]") (joined - (portRef Z (instanceRef wb_adr_5_i_i_1_0_0)) - (portRef C (instanceRef wb_adr_5_i_i_1_0)) - )) (net nRCS_9_u_i_0 (joined (portRef Z (instanceRef nRCS_9_u_i_0)) (portRef D (instanceRef nRCS_0io_RNO)) )) - (net (rename wb_adr_5_i_i_a2_6_0_0 "wb_adr_5_i_i_a2_6_0[0]") (joined - (portRef Z (instanceRef wb_adr_5_i_i_a2_6_0_0)) - (portRef A (instanceRef wb_adr_5_i_i_a2_6_0)) - (portRef D (instanceRef wb_dati_5_1_iv_0_2_4)) - )) (net nCRAS_c_i (joined (portRef Z (instanceRef nCRAS_pad_RNIBPVB)) (portRef CK (instanceRef CBR)) (portRef CK (instanceRef CBR_fast)) (portRef CK (instanceRef FWEr)) - (portRef CK (instanceRef FWEr_fast)) (portRef CK (instanceRef RowA_9)) (portRef CK (instanceRef RowA_8)) (portRef CK (instanceRef RowA_7)) @@ -3024,12 +3124,6 @@ (portRef SCLK (instanceRef RBA_0io_1)) (portRef SCLK (instanceRef RBA_0io_0)) )) - (net N_244_i (joined - (portRef Z (instanceRef IS_0_sqmuxa_0_o2_0_RNIS63D)) - (portRef SP (instanceRef IS_3)) - (portRef SP (instanceRef IS_2)) - (portRef SP (instanceRef IS_1)) - )) (net RD_1_i (joined (portRef Z (instanceRef nCCAS_pad_RNI01SJ)) (portRef T (instanceRef RD_pad_0)) @@ -3041,68 +3135,72 @@ (portRef T (instanceRef RD_pad_6)) (portRef T (instanceRef RD_pad_7)) )) - (net N_242_i (joined + (net N_261_i (joined + (portRef Z (instanceRef IS_0_sqmuxa_0_o2_RNIDJQJ)) + (portRef SP (instanceRef IS_3)) + (portRef SP (instanceRef IS_2)) + (portRef SP (instanceRef IS_1)) + )) + (net N_251_i (joined (portRef Z (instanceRef nRCAS_0io_RNO)) (portRef D (instanceRef nRCAS_0io)) )) - (net N_25_i (joined + (net N_32_i (joined (portRef Z (instanceRef nRRAS_0io_RNO)) (portRef D (instanceRef nRRAS_0io)) )) - (net N_28_i (joined + (net N_37_i (joined (portRef Z (instanceRef nRCS_0io_RNO)) (portRef D (instanceRef nRCS_0io)) )) - (net N_37_i (joined + (net N_252_i (joined (portRef Z (instanceRef nRWE_0io_RNO)) (portRef D (instanceRef nRWE_0io)) )) - (net N_60_i_i (joined + (net N_76_i_i (joined (portRef Z (instanceRef IS_RNO_0)) (portRef D (instanceRef IS_0)) )) - (net N_58_i_i (joined + (net N_74_i_i (joined (portRef Z (instanceRef IS_RNO_3)) (portRef D (instanceRef IS_3)) )) - (net N_57_i_i (joined + (net N_73_i_i (joined (portRef Z (instanceRef IS_RNO_2)) (portRef D (instanceRef IS_2)) )) - (net N_253_i (joined + (net N_279_i (joined (portRef Z (instanceRef S_RNO_0)) (portRef D (instanceRef S_0)) )) - (net N_94_i (joined - (portRef Z (instanceRef CmdValid_RNIS5A51)) - (portRef B (instanceRef wb_reqe)) - (portRef B (instanceRef wb_rste)) + (net N_45_i (joined + (portRef Z (instanceRef wb_adr_RNO_1)) + (portRef D (instanceRef wb_adr_1)) )) - (net N_284_i (joined + (net N_47_i (joined + (portRef Z (instanceRef wb_adr_RNO_0)) + (portRef D (instanceRef wb_adr_0)) + )) + (net N_17_i (joined (portRef Z (instanceRef CmdLEDEN_RNO)) (portRef D (instanceRef CmdLEDEN)) )) - (net N_285_i (joined + (net N_15_i (joined (portRef Z (instanceRef Cmdn8MEGEN_RNO)) (portRef D (instanceRef Cmdn8MEGEN)) )) - (net N_34_i (joined + (net N_346_i (joined + (portRef Z (instanceRef wb_we_RNO)) + (portRef D (instanceRef wb_we)) + )) + (net un1_wb_rst14_2_i (joined (portRef Z (instanceRef wb_reqe_RNO)) - (portRef A (instanceRef wb_reqe)) + (portRef B (instanceRef wb_reqe)) )) (net un1_CmdEnable20_i (joined (portRef Z (instanceRef CmdEnable_s_RNO)) (portRef C (instanceRef CmdEnable_s)) )) - (net N_22_i (joined - (portRef Z (instanceRef ADSubmitted_r_0_RNO)) - (portRef B (instanceRef ADSubmitted_r_0)) - )) - (net XOR8MEG18_i (joined - (portRef Z (instanceRef CmdEnable_RNI7PMB1)) - (portRef A (instanceRef CmdValid_r_fast)) - (portRef A (instanceRef CmdValid_r)) - )) (net (rename FS_cry_0 "FS_cry[0]") (joined (portRef COUT (instanceRef FS_cry_0_0)) (portRef CIN (instanceRef FS_cry_0_1)) @@ -3215,134 +3313,148 @@ (portRef Z (instanceRef RA10_0io_RNO_0)) (portRef PD (instanceRef RA10_0io)) )) - (net un1_CmdEnable20_0_a2_3_0 (joined - (portRef Z (instanceRef un1_CmdEnable20_0_a2_3_0)) - (portRef D (instanceRef un1_CmdEnable20_0_a2_1_0)) - (portRef D (instanceRef CmdEnable17_0_a2)) + (net CmdLEDEN_4_u_i_m2_i_a2_0_0 (joined + (portRef Z (instanceRef CmdLEDEN_4_u_i_m2_i_a2_0_0)) + (portRef B (instanceRef CmdLEDEN_4_u_i_m2_i_0)) + (portRef A (instanceRef Cmdn8MEGEN_4_u_i_m2_i_0)) )) - (net CmdLEDEN_4_u_i_a2_0_0 (joined - (portRef Z (instanceRef CmdLEDEN_4_u_i_a2_0_0)) - (portRef B (instanceRef CmdLEDEN_4_u_i_0)) - (portRef A (instanceRef Cmdn8MEGEN_4_u_i_0)) - )) - (net un1_CmdEnable20_0_a2_1_0 (joined - (portRef Z (instanceRef un1_CmdEnable20_0_a2_1_0)) - (portRef D (instanceRef CmdEnable_s_RNO)) - )) - (net Cmdn8MEGEN_4_u_i_0 (joined - (portRef Z (instanceRef Cmdn8MEGEN_4_u_i_0)) + (net Cmdn8MEGEN_4_u_i_m2_i_0 (joined + (portRef Z (instanceRef Cmdn8MEGEN_4_u_i_m2_i_0)) (portRef A (instanceRef Cmdn8MEGEN_RNO)) )) - (net CmdLEDEN_4_u_i_0 (joined - (portRef Z (instanceRef CmdLEDEN_4_u_i_0)) + (net CmdLEDEN_4_u_i_m2_i_0 (joined + (portRef Z (instanceRef CmdLEDEN_4_u_i_m2_i_0)) (portRef A (instanceRef CmdLEDEN_RNO)) )) - (net wb_we_0_0_0_0 (joined - (portRef Z (instanceRef wb_we_0_0_0_0)) - (portRef D (instanceRef wb_we_0_0_0)) + (net un1_CmdEnable20_0_0_a2_1_1 (joined + (portRef Z (instanceRef un1_CmdEnable20_0_0_a2_1_1)) + (portRef D (instanceRef CmdEnable_s_RNO)) )) - (net wb_cyc_stb_2_sqmuxa_i_a2_3_3 (joined - (portRef Z (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_3_3)) - (portRef C (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_3)) + (net wb_cyc_stb_2_sqmuxa_i_a2_2_0 (joined + (portRef Z (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_2_0)) + (portRef D (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_2)) )) - (net wb_cyc_stb_2_sqmuxa_i_a2_3_4 (joined - (portRef Z (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_3_4)) - (portRef D (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_3)) + (net XOR8MEG_3_u_0_0_a2_0_2 (joined + (portRef Z (instanceRef XOR8MEG_3_u_0_0_a2_0_2)) + (portRef D (instanceRef XOR8MEG_3_u_0_0_0)) )) - (net InitReady3_0_a2_2 (joined - (portRef Z (instanceRef InitReady3_0_a2_2)) - (portRef C (instanceRef InitReady3_0_a2)) + (net wb_we_0_0_i_1 (joined + (portRef Z (instanceRef wb_we_0_0_i_1)) + (portRef D (instanceRef wb_we_RNO)) )) - (net XOR8MEG_3_u_0_a2_0_2 (joined - (portRef Z (instanceRef XOR8MEG_3_u_0_a2_0_2)) - (portRef D (instanceRef XOR8MEG_3_u_0_0)) - )) - (net (rename wb_adr_5_i_i_1_0_tz_0_0 "wb_adr_5_i_i_1_0_tz_0[0]") (joined - (portRef Z (instanceRef wb_adr_5_i_i_1_0_tz_0_0)) - (portRef D (instanceRef wb_adr_5_i_i_1_0_0)) - )) - (net Ready_0_sqmuxa_0_a3_2 (joined - (portRef Z (instanceRef Ready_0_sqmuxa_0_a3_2)) - (portRef D (instanceRef Ready_0_sqmuxa_0_a3)) + (net Ready_0_sqmuxa_0_a2_2 (joined + (portRef Z (instanceRef Ready_0_sqmuxa_0_a2_2)) + (portRef D (instanceRef Ready_0_sqmuxa_0_a2)) (portRef B (instanceRef Ready_RNO)) )) - (net (rename wb_dati_5_1_iv_0_a2_3_0_7 "wb_dati_5_1_iv_0_a2_3_0[7]") (joined - (portRef Z (instanceRef wb_dati_5_1_iv_0_0_RNO_7)) - (portRef D (instanceRef wb_dati_5_1_iv_0_0_7)) + (net wb_cyc_stb_2_sqmuxa_i_0_0_a2_0 (joined + (portRef Z (instanceRef wb_cyc_stb_2_sqmuxa_i_0_0_a2_0)) + (portRef D (instanceRef wb_cyc_stb_2_sqmuxa_i_0_0)) )) - (net un1_ADWR_i_o2_3 (joined - (portRef Z (instanceRef un1_ADWR_i_o2_3)) - (portRef C (instanceRef un1_ADWR_i_o2_10)) + (net nRWE_s_i_tz_0 (joined + (portRef Z (instanceRef nRWE_s_i_tz_0)) + (portRef D (instanceRef nRWE_0io_RNO)) )) - (net un1_ADWR_i_o2_4 (joined - (portRef Z (instanceRef un1_ADWR_i_o2_4)) - (portRef D (instanceRef un1_ADWR_i_o2_10)) + (net (rename wb_dati_5_1_iv_0_a2_0_0_7 "wb_dati_5_1_iv_0_a2_0_0[7]") (joined + (portRef Z (instanceRef wb_dati_5_1_iv_0_a2_0_RNO_7)) + (portRef D (instanceRef wb_dati_5_1_iv_0_a2_0_7)) )) - (net un1_ADWR_i_o2_10 (joined - (portRef Z (instanceRef un1_ADWR_i_o2_10)) - (portRef C (instanceRef un1_ADWR_i_o2)) + (net un1_CmdEnable20_0_0_o2_3 (joined + (portRef Z (instanceRef un1_CmdEnable20_0_0_o2_3)) + (portRef C (instanceRef un1_CmdEnable20_0_0_o2_10)) )) - (net un1_ADWR_i_o2_11 (joined - (portRef Z (instanceRef un1_ADWR_i_o2_11)) - (portRef D (instanceRef un1_ADWR_i_o2)) + (net un1_CmdEnable20_0_0_o2_4 (joined + (portRef Z (instanceRef un1_CmdEnable20_0_0_o2_4)) + (portRef D (instanceRef un1_CmdEnable20_0_0_o2_10)) )) - (net (rename wb_dati_5_1_iv_0_a2_1_1_7 "wb_dati_5_1_iv_0_a2_1_1[7]") (joined - (portRef Z (instanceRef wb_dati_5_1_iv_0_a2_1_1_7)) - (portRef D (instanceRef wb_dati_5_1_iv_0_7)) + (net un1_CmdEnable20_0_0_o2_10 (joined + (portRef Z (instanceRef un1_CmdEnable20_0_0_o2_10)) + (portRef C (instanceRef un1_CmdEnable20_0_0_o2)) )) - (net (rename wb_dati_5_1_iv_0_a2_1_6 "wb_dati_5_1_iv_0_a2_1[6]") (joined - (portRef Z (instanceRef wb_dati_5_1_iv_0_a2_1_0_6)) - (portRef D (instanceRef wb_dati_5_1_iv_0_0_6)) + (net un1_CmdEnable20_0_0_o2_11 (joined + (portRef Z (instanceRef un1_CmdEnable20_0_0_o2_11)) + (portRef D (instanceRef un1_CmdEnable20_0_0_o2)) + )) + (net nRCS_9_u_i_o3_0_0 (joined + (portRef Z (instanceRef nRCAS_0io_RNO_2)) + (portRef D (instanceRef nRCAS_0io_RNO_1)) + )) + (net nRCS_9_u_i_o3_0_2 (joined + (portRef Z (instanceRef nRCAS_0io_RNO_1)) + (portRef D (instanceRef nRCAS_0io_RNO)) + )) + (net (rename wb_dati_5_1_iv_0_a2_0_2_1 "wb_dati_5_1_iv_0_a2_0_2[1]") (joined + (portRef Z (instanceRef wb_dati_5_1_iv_0_a2_0_2_1)) + (portRef D (instanceRef wb_dati_5_1_iv_0_0_1)) + )) + (net wb_cyc_stb_4_iv_0_0_a2_0_0 (joined + (portRef Z (instanceRef wb_cyc_stb_4_iv_0_0_a2_0_0)) + (portRef D (instanceRef wb_cyc_stb_4_iv_0_0_a2_0)) + )) + (net (rename wb_dati_5_0_iv_0_a2_1_0 "wb_dati_5_0_iv_0_a2_1[0]") (joined + (portRef Z (instanceRef wb_dati_5_0_iv_0_a2_1_0)) + (portRef C (instanceRef wb_dati_5_0_iv_0_0)) )) (net nRCS_9_u_i_0_0 (joined (portRef Z (instanceRef nRCS_9_u_i_0_0)) (portRef A (instanceRef nRRAS_0io_RNO)) (portRef D (instanceRef nRCS_9_u_i_0)) )) - (net un1_CmdEnable20_0_0 (joined - (portRef Z (instanceRef un1_CmdEnable20_0_0)) + (net un1_CmdEnable20_0_0_0 (joined + (portRef Z (instanceRef un1_CmdEnable20_0_0_0)) (portRef C (instanceRef CmdEnable_s_RNO)) )) - (net (rename wb_dati_5_0_iv_0_a2_0_0 "wb_dati_5_0_iv_0_a2_0[0]") (joined - (portRef Z (instanceRef wb_dati_5_0_iv_0_a2_0_0_0)) - (portRef C (instanceRef wb_dati_5_0_iv_0_0)) + (net (rename wb_adr_5_i_3_0_0_1 "wb_adr_5_i_3_0_0[1]") (joined + (portRef Z (instanceRef wb_adr_RNO_0_1)) + (portRef D (instanceRef wb_adr_RNO_1)) )) - (net (rename wb_dati_5_1_iv_0_1_3 "wb_dati_5_1_iv_0_1[3]") (joined - (portRef Z (instanceRef wb_dati_5_1_iv_0_1_3)) - (portRef D (instanceRef wb_dati_5_1_iv_0_3)) + (net (rename wb_dati_5_1_iv_0_0_a2_1_3 "wb_dati_5_1_iv_0_0_a2_1[3]") (joined + (portRef Z (instanceRef wb_dati_5_1_iv_0_0_a2_1_3)) + (portRef D (instanceRef wb_dati_5_1_iv_0_0_3)) )) - (net (rename wb_dati_5_1_iv_0_o2_0_5 "wb_dati_5_1_iv_0_o2_0[5]") (joined - (portRef Z (instanceRef wb_dati_5_1_iv_0_o2_0_5)) - (portRef D (instanceRef wb_dati_5_1_iv_0_5)) - (portRef D (instanceRef wb_dati_5_1_iv_0_2)) + (net (rename wb_adr_5_i_0_0_0 "wb_adr_5_i_0_0[0]") (joined + (portRef Z (instanceRef wb_adr_5_i_0_2_RNO_0)) + (portRef C (instanceRef wb_adr_5_i_0_2_0)) )) - (net (rename wb_dati_5_1_iv_0_0_6 "wb_dati_5_1_iv_0_0[6]") (joined - (portRef Z (instanceRef wb_dati_5_1_iv_0_0_6)) - (portRef D (instanceRef wb_dati_5_1_iv_0_6)) + (net (rename wb_adr_5_i_0_1_0 "wb_adr_5_i_0_1[0]") (joined + (portRef Z (instanceRef wb_adr_5_i_0_1_0)) + (portRef D (instanceRef wb_adr_5_i_0_3_0)) )) - (net (rename wb_dati_5_1_iv_0_0_4 "wb_dati_5_1_iv_0_0[4]") (joined - (portRef Z (instanceRef wb_dati_5_1_iv_0_0_4)) - (portRef B (instanceRef wb_dati_5_1_iv_0_4)) + (net (rename wb_adr_5_i_0_2_0 "wb_adr_5_i_0_2[0]") (joined + (portRef Z (instanceRef wb_adr_5_i_0_2_0)) + (portRef C (instanceRef wb_adr_RNO_0)) )) - (net (rename wb_dati_5_1_iv_0_2_4 "wb_dati_5_1_iv_0_2[4]") (joined - (portRef Z (instanceRef wb_dati_5_1_iv_0_2_4)) - (portRef C (instanceRef wb_dati_5_1_iv_0_4)) + (net (rename wb_adr_5_i_0_3_0 "wb_adr_5_i_0_3[0]") (joined + (portRef Z (instanceRef wb_adr_5_i_0_3_0)) + (portRef D (instanceRef wb_adr_RNO_0)) )) - (net (rename wb_adr_5_i_i_0_1 "wb_adr_5_i_i_0[1]") (joined - (portRef Z (instanceRef wb_adr_5_i_i_0_1)) - (portRef C (instanceRef wb_adr_5_i_i_1)) + (net (rename wb_dati_5_1_iv_0_0_1 "wb_dati_5_1_iv_0_0[1]") (joined + (portRef Z (instanceRef wb_dati_5_1_iv_0_0_1)) + (portRef D (instanceRef wb_dati_5_1_iv_0_1_1)) )) - (net (rename wb_dati_5_1_iv_0_0_7 "wb_dati_5_1_iv_0_0[7]") (joined - (portRef Z (instanceRef wb_dati_5_1_iv_0_0_7)) - (portRef D (instanceRef wb_dati_5_1_iv_0_1_7)) + (net (rename wb_dati_5_1_iv_0_1_1 "wb_dati_5_1_iv_0_1[1]") (joined + (portRef Z (instanceRef wb_dati_5_1_iv_0_1_1)) + (portRef D (instanceRef wb_dati_5_1_iv_0_1)) )) - (net (rename wb_adr_5_i_i_1_0 "wb_adr_5_i_i_1[0]") (joined - (portRef Z (instanceRef wb_adr_5_i_i_1_0)) - (portRef D (instanceRef wb_adr_5_i_i_5_0)) + (net (rename wb_dati_5_1_iv_0_0_1_6 "wb_dati_5_1_iv_0_0_1[6]") (joined + (portRef Z (instanceRef wb_dati_5_1_iv_0_0_1_6)) + (portRef D (instanceRef wb_dati_5_1_iv_0_0_6)) )) - (net (rename wb_adr_5_i_i_5_0 "wb_adr_5_i_i_5[0]") (joined - (portRef Z (instanceRef wb_adr_5_i_i_5_0)) - (portRef D (instanceRef wb_adr_5_i_i_0)) + (net (rename wb_dati_5_1_iv_0_0_0_3 "wb_dati_5_1_iv_0_0_0[3]") (joined + (portRef Z (instanceRef wb_dati_5_1_iv_0_0_0_3)) + (portRef B (instanceRef wb_dati_5_1_iv_0_0_3)) + )) + (net (rename wb_dati_5_1_iv_0_0_1_3 "wb_dati_5_1_iv_0_0_1[3]") (joined + (portRef Z (instanceRef wb_dati_5_1_iv_0_0_1_3)) + (portRef C (instanceRef wb_dati_5_1_iv_0_0_3)) + )) + (net (rename wb_dati_5_1_iv_0_1_7 "wb_dati_5_1_iv_0_1[7]") (joined + (portRef Z (instanceRef wb_dati_5_1_iv_0_1_7)) + (portRef D (instanceRef wb_dati_5_1_iv_0_7)) + )) + (net (rename wb_dati_5_1_iv_0_0_1_4 "wb_dati_5_1_iv_0_0_1[4]") (joined + (portRef Z (instanceRef wb_dati_5_1_iv_0_0_1_4)) + (portRef C (instanceRef wb_dati_5_1_iv_0_0_4)) )) (net (rename FS_cry_0_S0_0 "FS_cry_0_S0[0]") (joined (portRef S0 (instanceRef FS_cry_0_0)) @@ -3353,12 +3465,20 @@ (net (rename FS_s_0_COUT_17 "FS_s_0_COUT[17]") (joined (portRef COUT (instanceRef FS_s_0_17)) )) - (net (rename wb_dati_5_1_iv_0_1_7 "wb_dati_5_1_iv_0_1[7]") (joined - (portRef Z (instanceRef wb_dati_5_1_iv_0_1_7)) - (portRef C (instanceRef wb_dati_5_1_iv_0_7)) + (net InitReady3_0_a2_1_0 (joined + (portRef Z (instanceRef InitReady3_0_a2_1_0)) + (portRef C (instanceRef InitReady3_0_a2)) + )) + (net wb_we_0_0_i_1_1 (joined + (portRef Z (instanceRef wb_we_0_0_i_1_1)) + (portRef D (instanceRef wb_we_0_0_i_1)) + )) + (net (rename wb_dati_5_1_iv_0_1_0_4 "wb_dati_5_1_iv_0_1_0[4]") (joined + (portRef Z (instanceRef wb_dati_5_1_iv_0_1_0_4)) + (portRef D (instanceRef wb_dati_5_1_iv_0_0_4)) )) (net RCKEEN_8_u_1 (joined - (portRef Z (instanceRef RCKEEN_8_u_1_0)) + (portRef Z (instanceRef RCKEEN_8_u_1)) (portRef C (instanceRef RCKEEN_8_u)) )) (net LEDENe_0 (joined @@ -3369,50 +3489,50 @@ (portRef Z (instanceRef n8MEGEN_RNO)) (portRef D (instanceRef n8MEGEN)) )) - (net (rename RowAd_0_7 "RowAd_0[7]") (joined - (portRef Z (instanceRef RowAd_7)) - (portRef D (instanceRef RowA_7)) - )) (net (rename RowAd_0_8 "RowAd_0[8]") (joined (portRef Z (instanceRef RowAd_8)) (portRef D (instanceRef RowA_8)) )) - (net (rename RowAd_0_5 "RowAd_0[5]") (joined - (portRef Z (instanceRef RowAd_5)) - (portRef D (instanceRef RowA_5)) - )) - (net (rename RBAd_0_1 "RBAd_0[1]") (joined - (portRef Z (instanceRef RBAd_1)) - (portRef D (instanceRef RBA_0io_1)) - )) - (net (rename RowAd_0_3 "RowAd_0[3]") (joined - (portRef Z (instanceRef RowAd_3)) - (portRef D (instanceRef RowA_3)) - )) (net (rename RowAd_0_0 "RowAd_0[0]") (joined (portRef Z (instanceRef RowAd_0)) (portRef D (instanceRef RowA_0)) )) - (net (rename RowAd_0_6 "RowAd_0[6]") (joined - (portRef Z (instanceRef RowAd_6)) - (portRef D (instanceRef RowA_6)) - )) (net (rename RowAd_0_2 "RowAd_0[2]") (joined (portRef Z (instanceRef RowAd_2)) (portRef D (instanceRef RowA_2)) )) + (net (rename RowAd_0_3 "RowAd_0[3]") (joined + (portRef Z (instanceRef RowAd_3)) + (portRef D (instanceRef RowA_3)) + )) (net (rename RowAd_0_4 "RowAd_0[4]") (joined (portRef Z (instanceRef RowAd_4)) (portRef D (instanceRef RowA_4)) )) - (net (rename RowAd_0_1 "RowAd_0[1]") (joined - (portRef Z (instanceRef RowAd_1)) - (portRef D (instanceRef RowA_1)) + (net (rename RowAd_0_6 "RowAd_0[6]") (joined + (portRef Z (instanceRef RowAd_6)) + (portRef D (instanceRef RowA_6)) )) (net (rename RBAd_0_0 "RBAd_0[0]") (joined (portRef Z (instanceRef RBAd_0)) (portRef D (instanceRef RBA_0io_0)) )) + (net (rename RowAd_0_7 "RowAd_0[7]") (joined + (portRef Z (instanceRef RowAd_7)) + (portRef D (instanceRef RowA_7)) + )) + (net (rename RowAd_0_5 "RowAd_0[5]") (joined + (portRef Z (instanceRef RowAd_5)) + (portRef D (instanceRef RowA_5)) + )) + (net (rename RowAd_0_1 "RowAd_0[1]") (joined + (portRef Z (instanceRef RowAd_1)) + (portRef D (instanceRef RowA_1)) + )) + (net (rename RBAd_0_1 "RBAd_0[1]") (joined + (portRef Z (instanceRef RBAd_1)) + (portRef D (instanceRef RBA_0io_1)) + )) (net (rename RowAd_0_9 "RowAd_0[9]") (joined (portRef Z (instanceRef RowAd_9)) (portRef D (instanceRef RowA_9)) @@ -3429,84 +3549,59 @@ (portRef Z (instanceRef RA11d)) (portRef D (instanceRef RA11_0io)) )) - (net N_4 (joined - (portRef Z (instanceRef wb_cyc_stb_2_sqmuxa_i_o2_RNI167R)) - (portRef C (instanceRef CmdValid_RNITBH02)) + (net G_4_0_a3_0 (joined + (portRef Z (instanceRef PHI2r3_RNIFT0I_0)) + (portRef C (instanceRef CmdValid_fast_RNI3K0H1)) )) (net n8MEGENe_1_0 (joined (portRef Z (instanceRef n8MEGEN_RNO_0)) - (portRef C (instanceRef n8MEGEN_RNO)) + (portRef B (instanceRef n8MEGEN_RNO)) + )) + (net N_4 (joined + (portRef N_4 (instanceRef ufmefb)) + (portRef C (instanceRef CmdValid_RNIOOBE2)) )) (net g1_0 (joined (portRef Z (instanceRef PHI2r3_RNIFT0I)) - (portRef D (instanceRef CmdValid_RNITBH02)) + (portRef D (instanceRef CmdValid_RNIOOBE2)) )) - (net g0_0_a3_1 (joined - (portRef g0_0_a3_1 (instanceRef ufmefb)) - (portRef D (instanceRef wb_cyc_stb_2_sqmuxa_i_o2_RNI167R)) + (net m3_0_a2_0 (joined + (portRef Z (instanceRef RASr2_RNI6PUF)) + (portRef D (instanceRef CBR_fast_RNIQ31K1)) )) - (net G_8_0_a3_0_0 (joined - (portRef Z (instanceRef PHI2r3_RNIFT0I_0)) - (portRef C (instanceRef CmdValid_fast_RNI3K0H1)) + (net CBR_fast (joined + (portRef Q (instanceRef CBR_fast)) + (portRef A (instanceRef CBR_fast_RNIQ31K1)) )) (net CmdValid_fast (joined (portRef Q (instanceRef CmdValid_fast)) (portRef B (instanceRef CmdValid_fast_RNI3K0H1)) )) - (net N_36_fast (joined + (net N_34_fast (joined (portRef Z (instanceRef CmdValid_r_fast)) (portRef D (instanceRef CmdValid_fast)) )) (net Ready_fast (joined (portRef Q (instanceRef Ready_fast)) (portRef B (instanceRef RowAd_9)) - (portRef B (instanceRef RBAd_0)) - (portRef B (instanceRef RowAd_1)) - (portRef B (instanceRef RowAd_4)) - (portRef B (instanceRef RowAd_2)) - (portRef B (instanceRef RowAd_6)) - (portRef B (instanceRef RowAd_0)) - (portRef B (instanceRef RowAd_3)) (portRef B (instanceRef RBAd_1)) + (portRef B (instanceRef RowAd_1)) (portRef B (instanceRef RowAd_5)) - (portRef B (instanceRef RowAd_8)) (portRef B (instanceRef RowAd_7)) + (portRef B (instanceRef RBAd_0)) + (portRef B (instanceRef RowAd_6)) + (portRef B (instanceRef RowAd_4)) + (portRef B (instanceRef RowAd_3)) + (portRef B (instanceRef RowAd_2)) + (portRef B (instanceRef RowAd_0)) + (portRef B (instanceRef RowAd_8)) (portRef B (instanceRef RA11d)) (portRef B (instanceRef Ready_fast_RNO)) )) - (net CBR_fast (joined - (portRef Q (instanceRef CBR_fast)) - (portRef A (instanceRef RCKEEN_8_u_0_a2_1)) - (portRef A (instanceRef nRCAS_0_sqmuxa_1_0_a3)) - )) - (net FWEr_fast (joined - (portRef Q (instanceRef FWEr_fast)) - (portRef D (instanceRef nRWE_s_i_a2_0)) - )) - (net nRCAS_0io_RNO_1 (joined - (portRef Z (instanceRef nRCAS_0io_RNO_1)) - (portRef D (instanceRef nRCAS_0io_RNO_0)) - )) - (net N_242_i_1 (joined + (net N_251_i_sx (joined (portRef Z (instanceRef nRCAS_0io_RNO_0)) (portRef C (instanceRef nRCAS_0io_RNO)) )) - (net nRCS_0io_RNO_0 (joined - (portRef Z (instanceRef nRCS_0io_RNO_0)) - (portRef B (instanceRef nRCS_0io_RNO)) - )) - (net nRWE_0io_RNO_1 (joined - (portRef Z (instanceRef nRWE_0io_RNO_1)) - (portRef A (instanceRef nRWE_0io_RNO_0)) - )) - (net nRWE_0io_RNO_2 (joined - (portRef Z (instanceRef nRWE_0io_RNO_2)) - (portRef B (instanceRef nRWE_0io_RNO_0)) - )) - (net nRWE_0io_RNO_0 (joined - (portRef Z (instanceRef nRWE_0io_RNO_0)) - (portRef C (instanceRef nRWE_0io_RNO)) - )) (net (rename XOR8MEG_CN "XOR8MEG.CN") (joined (portRef Z (instanceRef XOR8MEG_CN)) (portRef CK (instanceRef ADSubmitted)) @@ -3523,7 +3618,7 @@ )) (net VCC (joined (portRef Z (instanceRef VCC)) - (portRef D1 (instanceRef rck)) + (portRef D1 (instanceRef rclk_oddr)) (portRef B0 (instanceRef FS_cry_0_0)) (portRef SP (instanceRef RA10_0io)) (portRef SP (instanceRef RA11_0io)) @@ -3554,8 +3649,8 @@ )) (net GND (joined (portRef Z (instanceRef GND)) - (portRef RST (instanceRef rck)) - (portRef D0 (instanceRef rck)) + (portRef RST (instanceRef rclk_oddr)) + (portRef D0 (instanceRef rclk_oddr)) (portRef D1 (instanceRef FS_cry_0_0)) (portRef C1 (instanceRef FS_cry_0_0)) (portRef B1 (instanceRef FS_cry_0_0)) @@ -3662,14 +3757,12 @@ )) (net (rename MAin_c_0 "MAin_c[0]") (joined (portRef O (instanceRef MAin_pad_0)) - (portRef A (instanceRef CmdEnable_RNI7PMB1)) - (portRef D (instanceRef XOR8MEG18_0_a2)) (portRef A (instanceRef RowAd_0)) - (portRef A (instanceRef un9_RA_i_m2_0)) - (portRef C (instanceRef CmdEnable_0_sqmuxa_0_a2_1)) - (portRef A (instanceRef un1_CmdEnable20_0_0)) - (portRef C (instanceRef un1_CmdEnable20_0_a2_1_0)) - (portRef A (instanceRef XOR8MEG18_0_a2_0)) + (portRef A (instanceRef un9_RA_i_m2_i_m2_0)) + (portRef C (instanceRef un1_CmdEnable20_0_0_a2_3)) + (portRef C (instanceRef un1_CmdEnable20_0_0_a2_4)) + (portRef A (instanceRef un1_CmdEnable20_0_0_0)) + (portRef B (instanceRef CmdUFMData_1_sqmuxa_0_a2_3)) )) (net (rename MAin_0 "MAin[0]") (joined (portRef (member main 9)) @@ -3677,16 +3770,14 @@ )) (net (rename MAin_c_1 "MAin_c[1]") (joined (portRef O (instanceRef MAin_pad_1)) - (portRef D (instanceRef CmdEnable_RNI7PMB1)) - (portRef A (instanceRef XOR8MEG18_0_a2)) - (portRef D (instanceRef un1_CmdEnable20_0_a2_3_0)) - (portRef D (instanceRef CmdEnable16_0_a2)) + (portRef D (instanceRef CmdEnable16_0_a2_1_a2)) (portRef A (instanceRef RowAd_1)) - (portRef A (instanceRef un9_RA_i_m2_1)) - (portRef A (instanceRef CmdEnable_0_sqmuxa_0_a2_0)) - (portRef B (instanceRef un1_CmdEnable20_0_0)) - (portRef B (instanceRef CmdUFMData_1_sqmuxa_0_a2)) - (portRef A (instanceRef ADSubmitted_r_0_RNO)) + (portRef A (instanceRef un9_RA_i_m2_i_m2_1)) + (portRef B (instanceRef un1_CmdEnable20_0_0_0)) + (portRef A (instanceRef un1_CmdEnable20_0_0_a2_1_1)) + (portRef C (instanceRef CmdUFMData_1_sqmuxa_0_a2_3)) + (portRef A (instanceRef un1_ADWR_i_i_a2)) + (portRef D (instanceRef un1_CmdEnable20_0_0_a2_3_RNIJ3N91)) (portRef D (instanceRef C1Submitted_RNO)) )) (net (rename MAin_1 "MAin[1]") (joined @@ -3696,8 +3787,8 @@ (net (rename MAin_c_2 "MAin_c[2]") (joined (portRef O (instanceRef MAin_pad_2)) (portRef A (instanceRef RowAd_2)) - (portRef A (instanceRef un9_RA_i_m2_2)) - (portRef A (instanceRef un1_ADWR_i_o2_4)) + (portRef A (instanceRef un9_RA_i_m2_i_m2_2)) + (portRef A (instanceRef un1_CmdEnable20_0_0_o2_3)) )) (net (rename MAin_2 "MAin[2]") (joined (portRef (member main 7)) @@ -3706,8 +3797,8 @@ (net (rename MAin_c_3 "MAin_c[3]") (joined (portRef O (instanceRef MAin_pad_3)) (portRef A (instanceRef RowAd_3)) - (portRef A (instanceRef un9_RA_i_m2_3)) - (portRef A (instanceRef un1_ADWR_i_o2_3)) + (portRef A (instanceRef un9_RA_i_m2_i_m2_3)) + (portRef B (instanceRef un1_CmdEnable20_0_0_o2_3)) )) (net (rename MAin_3 "MAin[3]") (joined (portRef (member main 6)) @@ -3716,8 +3807,8 @@ (net (rename MAin_c_4 "MAin_c[4]") (joined (portRef O (instanceRef MAin_pad_4)) (portRef A (instanceRef RowAd_4)) - (portRef A (instanceRef un9_RA_i_m2_4)) - (portRef B (instanceRef un1_ADWR_i_o2_4)) + (portRef A (instanceRef un9_RA_i_m2_i_m2_4)) + (portRef A (instanceRef un1_CmdEnable20_0_0_o2_4)) )) (net (rename MAin_4 "MAin[4]") (joined (portRef (member main 5)) @@ -3726,8 +3817,8 @@ (net (rename MAin_c_5 "MAin_c[5]") (joined (portRef O (instanceRef MAin_pad_5)) (portRef A (instanceRef RowAd_5)) - (portRef A (instanceRef un9_RA_i_m2_5)) - (portRef C (instanceRef un1_ADWR_i_o2_4)) + (portRef A (instanceRef un9_RA_i_m2_i_m2_5)) + (portRef C (instanceRef un1_CmdEnable20_0_0_o2_3)) )) (net (rename MAin_5 "MAin[5]") (joined (portRef (member main 4)) @@ -3736,8 +3827,8 @@ (net (rename MAin_c_6 "MAin_c[6]") (joined (portRef O (instanceRef MAin_pad_6)) (portRef A (instanceRef RowAd_6)) - (portRef A (instanceRef un9_RA_i_m2_6)) - (portRef B (instanceRef un1_ADWR_i_o2_3)) + (portRef A (instanceRef un9_RA_i_m2_i_m2_6)) + (portRef B (instanceRef un1_CmdEnable20_0_0_o2_4)) )) (net (rename MAin_6 "MAin[6]") (joined (portRef (member main 3)) @@ -3746,8 +3837,8 @@ (net (rename MAin_c_7 "MAin_c[7]") (joined (portRef O (instanceRef MAin_pad_7)) (portRef A (instanceRef RowAd_7)) - (portRef A (instanceRef un9_RA_i_m2_7)) - (portRef D (instanceRef un1_ADWR_i_o2_4)) + (portRef A (instanceRef un9_RA_i_m2_i_m2_7)) + (portRef C (instanceRef un1_CmdEnable20_0_0_o2_4)) )) (net (rename MAin_7 "MAin[7]") (joined (portRef (member main 2)) @@ -3765,8 +3856,8 @@ (net (rename MAin_c_9 "MAin_c[9]") (joined (portRef O (instanceRef MAin_pad_9)) (portRef A (instanceRef RowAd_9)) - (portRef A (instanceRef RDQML_0)) - (portRef A (instanceRef un9_RA_i_m2_9)) + (portRef A (instanceRef RDQML_0_0)) + (portRef A (instanceRef un9_RA_i_m2_i_m2_9)) (portRef A (instanceRef RDQMH_pad_RNO)) )) (net (rename MAin_9 "MAin[9]") (joined @@ -3791,10 +3882,10 @@ )) (net (rename Din_c_0 "Din_c[0]") (joined (portRef O (instanceRef Din_pad_0)) - (portRef D (instanceRef un1_CmdEnable20_0_a2_2)) - (portRef A (instanceRef XOR8MEG_3_u_0_a2_1)) - (portRef C (instanceRef Cmdn8MEGEN_4_u_i_0)) - (portRef A (instanceRef CmdUFMWrite_3_u_0_0)) + (portRef D (instanceRef un1_CmdEnable20_0_0_a2_2)) + (portRef A (instanceRef XOR8MEG_3_u_0_0_a2_1)) + (portRef C (instanceRef Cmdn8MEGEN_4_u_i_m2_i_0)) + (portRef A (instanceRef CmdUFMWrite_3_u_0_0_0)) (portRef D (instanceRef CmdUFMData)) (portRef D (instanceRef Bank_0io_0)) (portRef D (instanceRef WRD_0io_0)) @@ -3805,11 +3896,11 @@ )) (net (rename Din_c_1 "Din_c[1]") (joined (portRef O (instanceRef Din_pad_1)) - (portRef B (instanceRef un1_CmdEnable20_0_a2_2)) - (portRef C (instanceRef CmdLEDEN_4_u_i_0)) - (portRef A (instanceRef XOR8MEG_3_u_0_0)) - (portRef B (instanceRef CmdUFMShift_3_u_0_0)) - (portRef B (instanceRef CmdUFMWrite_3_u_0_0)) + (portRef B (instanceRef un1_CmdEnable20_0_0_a2_2)) + (portRef C (instanceRef CmdLEDEN_4_u_i_m2_i_0)) + (portRef B (instanceRef CmdUFMShift_3_u_0_0_0)) + (portRef A (instanceRef XOR8MEG_3_u_0_0_0)) + (portRef B (instanceRef CmdUFMWrite_3_u_0_0_0)) (portRef D (instanceRef Bank_0io_1)) (portRef D (instanceRef WRD_0io_1)) )) @@ -3819,9 +3910,8 @@ )) (net (rename Din_c_2 "Din_c[2]") (joined (portRef O (instanceRef Din_pad_2)) - (portRef A (instanceRef XOR8MEG_3_u_0_a2_2)) - (portRef A (instanceRef un1_CmdEnable20_0_a2_1_0)) - (portRef A (instanceRef CmdEnable17_0_a2)) + (portRef A (instanceRef XOR8MEG_3_u_0_0_a2_2)) + (portRef A (instanceRef un1_CmdEnable20_0_0_a2_3)) (portRef D (instanceRef Bank_0io_2)) (portRef D (instanceRef WRD_0io_2)) )) @@ -3831,11 +3921,11 @@ )) (net (rename Din_c_3 "Din_c[3]") (joined (portRef O (instanceRef Din_pad_3)) - (portRef B (instanceRef un1_CmdEnable20_0_a2_3_0)) - (portRef A (instanceRef XOR8MEG_3_u_0_a2_0_2)) - (portRef A (instanceRef CmdEnable_0_sqmuxa_0_a2_1)) - (portRef A (instanceRef CmdUFMData_1_sqmuxa_0_a2_0)) - (portRef A (instanceRef CmdValid_2_i_o2)) + (portRef D (instanceRef Cmdn8MEGEN_4_u_i_m2_i_a2_2)) + (portRef A (instanceRef Cmdn8MEGEN_4_u_i_m2_i_a2_3)) + (portRef A (instanceRef XOR8MEG_3_u_0_0_a2_0_2)) + (portRef A (instanceRef un1_CmdEnable20_0_0_a2_4)) + (portRef A (instanceRef CmdValid_2_i_o2_0_o2)) (portRef D (instanceRef Bank_0io_3)) (portRef D (instanceRef WRD_0io_3)) )) @@ -3845,12 +3935,12 @@ )) (net (rename Din_c_4 "Din_c[4]") (joined (portRef O (instanceRef Din_pad_4)) - (portRef C (instanceRef un1_CmdEnable20_0_a2_2)) - (portRef B (instanceRef CmdLEDEN_4_u_i_a2_0_0)) - (portRef B (instanceRef XOR8MEG_3_u_0_a2_1)) - (portRef A (instanceRef XOR8MEG_3_u_0_a2)) - (portRef B (instanceRef CmdUFMData_1_sqmuxa_0_a2_0)) - (portRef B (instanceRef CmdValid_2_i_o2)) + (portRef B (instanceRef CmdLEDEN_4_u_i_m2_i_a2_0_0)) + (portRef C (instanceRef un1_CmdEnable20_0_0_a2_2)) + (portRef B (instanceRef Cmdn8MEGEN_4_u_i_m2_i_a2_2)) + (portRef B (instanceRef XOR8MEG_3_u_0_0_a2_1)) + (portRef B (instanceRef CmdValid_2_i_o2_0_o2)) + (portRef A (instanceRef XOR8MEG_3_u_0_0_0_a2)) (portRef D (instanceRef Bank_0io_4)) (portRef D (instanceRef WRD_0io_4)) )) @@ -3860,12 +3950,12 @@ )) (net (rename Din_c_5 "Din_c[5]") (joined (portRef O (instanceRef Din_pad_5)) - (portRef A (instanceRef un1_CmdEnable20_0_a2_3_0)) - (portRef A (instanceRef CmdLEDEN_4_u_i_a2_0_0)) - (portRef B (instanceRef XOR8MEG_3_u_0_a2_2)) - (portRef B (instanceRef XOR8MEG_3_u_0_a2)) - (portRef C (instanceRef CmdUFMData_1_sqmuxa_0_a2_0)) - (portRef C (instanceRef CmdValid_2_i_o2)) + (portRef A (instanceRef CmdLEDEN_4_u_i_m2_i_a2_0_0)) + (portRef C (instanceRef Cmdn8MEGEN_4_u_i_m2_i_a2_2)) + (portRef B (instanceRef XOR8MEG_3_u_0_0_a2_2)) + (portRef B (instanceRef Cmdn8MEGEN_4_u_i_m2_i_a2_3)) + (portRef C (instanceRef CmdValid_2_i_o2_0_o2)) + (portRef B (instanceRef XOR8MEG_3_u_0_0_0_a2)) (portRef D (instanceRef Bank_0io_5)) (portRef D (instanceRef WRD_0io_5)) )) @@ -3875,12 +3965,11 @@ )) (net (rename Din_c_6 "Din_c[6]") (joined (portRef O (instanceRef Din_pad_6)) - (portRef D (instanceRef CmdLEDEN_4_u_i_a2_0_0)) + (portRef D (instanceRef CmdLEDEN_4_u_i_m2_i_a2_0_0)) (portRef A (instanceRef RA11d)) - (portRef A (instanceRef XOR8MEG_3_u_0_o2_1)) - (portRef B (instanceRef CmdEnable_0_sqmuxa_0_a2_1)) - (portRef B (instanceRef un1_CmdEnable20_0_a2_1_0)) - (portRef B (instanceRef CmdEnable17_0_a2)) + (portRef A (instanceRef XOR8MEG_3_u_0_0_o2_1)) + (portRef B (instanceRef un1_CmdEnable20_0_0_a2_3)) + (portRef B (instanceRef un1_CmdEnable20_0_0_a2_4)) (portRef D (instanceRef Bank_0io_6)) (portRef D (instanceRef WRD_0io_6)) )) @@ -3890,9 +3979,9 @@ )) (net (rename Din_c_7 "Din_c[7]") (joined (portRef O (instanceRef Din_pad_7)) - (portRef A (instanceRef un1_CmdEnable20_0_a2_2)) - (portRef C (instanceRef CmdLEDEN_4_u_i_a2_0_0)) - (portRef B (instanceRef XOR8MEG_3_u_0_o2_1)) + (portRef C (instanceRef CmdLEDEN_4_u_i_m2_i_a2_0_0)) + (portRef A (instanceRef un1_CmdEnable20_0_0_a2_2)) + (portRef B (instanceRef XOR8MEG_3_u_0_0_o2_1)) (portRef D (instanceRef Bank_0io_7)) (portRef D (instanceRef WRD_0io_7)) )) @@ -3943,7 +4032,7 @@ )) (net nCRAS_c (joined (portRef O (instanceRef nCRAS_pad)) - (portRef C (instanceRef LED_pad_RNO)) + (portRef D (instanceRef LED_pad_RNO)) (portRef A (instanceRef nCRAS_pad_RNIBPVB)) (portRef A (instanceRef RASr_RNO)) )) @@ -3953,9 +4042,9 @@ )) (net nFWE_c (joined (portRef O (instanceRef nFWE_pad)) - (portRef C (instanceRef un1_ADWR_i_o2_3)) + (portRef D (instanceRef un1_CmdEnable20_0_0_o2_4)) (portRef B (instanceRef nCCAS_pad_RNI01SJ)) - (portRef A (instanceRef nFWE_pad_RNI420B)) + (portRef A (instanceRef FWEr_RNO)) )) (net nFWE (joined (portRef nFWE) @@ -3986,7 +4075,7 @@ (portRef (member rba 0)) )) (net (rename RA_c_0 "RA_c[0]") (joined - (portRef Z (instanceRef un9_RA_i_m2_0)) + (portRef Z (instanceRef un9_RA_i_m2_i_m2_0)) (portRef I (instanceRef RA_pad_0)) )) (net (rename RA_0 "RA[0]") (joined @@ -3994,7 +4083,7 @@ (portRef (member ra 11)) )) (net (rename RA_c_1 "RA_c[1]") (joined - (portRef Z (instanceRef un9_RA_i_m2_1)) + (portRef Z (instanceRef un9_RA_i_m2_i_m2_1)) (portRef I (instanceRef RA_pad_1)) )) (net (rename RA_1 "RA[1]") (joined @@ -4002,7 +4091,7 @@ (portRef (member ra 10)) )) (net (rename RA_c_2 "RA_c[2]") (joined - (portRef Z (instanceRef un9_RA_i_m2_2)) + (portRef Z (instanceRef un9_RA_i_m2_i_m2_2)) (portRef I (instanceRef RA_pad_2)) )) (net (rename RA_2 "RA[2]") (joined @@ -4010,7 +4099,7 @@ (portRef (member ra 9)) )) (net (rename RA_c_3 "RA_c[3]") (joined - (portRef Z (instanceRef un9_RA_i_m2_3)) + (portRef Z (instanceRef un9_RA_i_m2_i_m2_3)) (portRef I (instanceRef RA_pad_3)) )) (net (rename RA_3 "RA[3]") (joined @@ -4018,7 +4107,7 @@ (portRef (member ra 8)) )) (net (rename RA_c_4 "RA_c[4]") (joined - (portRef Z (instanceRef un9_RA_i_m2_4)) + (portRef Z (instanceRef un9_RA_i_m2_i_m2_4)) (portRef I (instanceRef RA_pad_4)) )) (net (rename RA_4 "RA[4]") (joined @@ -4026,7 +4115,7 @@ (portRef (member ra 7)) )) (net (rename RA_c_5 "RA_c[5]") (joined - (portRef Z (instanceRef un9_RA_i_m2_5)) + (portRef Z (instanceRef un9_RA_i_m2_i_m2_5)) (portRef I (instanceRef RA_pad_5)) )) (net (rename RA_5 "RA[5]") (joined @@ -4034,7 +4123,7 @@ (portRef (member ra 6)) )) (net (rename RA_c_6 "RA_c[6]") (joined - (portRef Z (instanceRef un9_RA_i_m2_6)) + (portRef Z (instanceRef un9_RA_i_m2_i_m2_6)) (portRef I (instanceRef RA_pad_6)) )) (net (rename RA_6 "RA[6]") (joined @@ -4042,7 +4131,7 @@ (portRef (member ra 5)) )) (net (rename RA_c_7 "RA_c[7]") (joined - (portRef Z (instanceRef un9_RA_i_m2_7)) + (portRef Z (instanceRef un9_RA_i_m2_i_m2_7)) (portRef I (instanceRef RA_pad_7)) )) (net (rename RA_7 "RA[7]") (joined @@ -4058,7 +4147,7 @@ (portRef (member ra 3)) )) (net (rename RA_c_9 "RA_c[9]") (joined - (portRef Z (instanceRef un9_RA_i_m2_9)) + (portRef Z (instanceRef un9_RA_i_m2_i_m2_9)) (portRef I (instanceRef RA_pad_9)) )) (net (rename RA_9 "RA[9]") (joined @@ -4156,7 +4245,7 @@ (net RCLK_c (joined (portRef O (instanceRef RCLK_pad)) (portRef RCLK_c (instanceRef ufmefb)) - (portRef SCLK (instanceRef rck)) + (portRef SCLK (instanceRef rclk_oddr)) (portRef CK (instanceRef CASr)) (portRef CK (instanceRef CASr2)) (portRef CK (instanceRef CASr3)) @@ -4229,7 +4318,7 @@ (portRef I (instanceRef RCLK_pad)) )) (net RCLKout_c (joined - (portRef Q (instanceRef rck)) + (portRef Q (instanceRef rclk_oddr)) (portRef I (instanceRef RCLKout_pad)) )) (net RCLKout (joined @@ -4238,8 +4327,8 @@ )) (net RCKE_c (joined (portRef Q (instanceRef RCKE)) - (portRef B (instanceRef nRWE_0io_RNO_2)) (portRef C (instanceRef nRCS_9_u_i_0_0)) + (portRef B (instanceRef nRWE_s_i_tz_0)) (portRef I (instanceRef RCKE_pad)) )) (net RCKE (joined @@ -4279,29 +4368,28 @@ (portRef RDQMH) )) (net RDQML_c (joined - (portRef Z (instanceRef RDQML_0)) + (portRef Z (instanceRef RDQML_0_0)) (portRef I (instanceRef RDQML_pad)) )) (net RDQML (joined (portRef O (instanceRef RDQML_pad)) (portRef RDQML) )) - (net N_586_0 (joined + (net N_705_0 (joined (portRef Z (instanceRef InitReady_RNO)) (portRef D (instanceRef InitReady)) )) - (net N_587_0 (joined + (net N_706_0 (joined (portRef Z (instanceRef Ready_RNO)) (portRef D (instanceRef Ready)) )) - (net N_588_0 (joined + (net N_707_0 (joined (portRef Z (instanceRef Ready_fast_RNO)) (portRef D (instanceRef Ready_fast)) )) (net nFWE_c_i (joined - (portRef Z (instanceRef nFWE_pad_RNI420B)) + (portRef Z (instanceRef FWEr_RNO)) (portRef D (instanceRef FWEr)) - (portRef D (instanceRef FWEr_fast)) )) (net nCRAS_c_i_0 (joined (portRef Z (instanceRef RASr_RNO)) @@ -4330,6 +4418,22 @@ (portRef CD (instanceRef S_1)) (portRef CD (instanceRef S_0)) )) + (net (rename wb_dati_5_1_iv_0_0_o2_am_5 "wb_dati_5_1_iv_0_0_o2_am[5]") (joined + (portRef Z (instanceRef wb_dati_5_1_iv_0_0_o2_am_5)) + (portRef BLUT (instanceRef wb_dati_5_1_iv_0_0_o2_5)) + )) + (net (rename wb_dati_5_1_iv_0_0_o2_bm_5 "wb_dati_5_1_iv_0_0_o2_bm[5]") (joined + (portRef Z (instanceRef wb_dati_5_1_iv_0_0_o2_bm_5)) + (portRef ALUT (instanceRef wb_dati_5_1_iv_0_0_o2_5)) + )) + (net (rename wb_adr_5_i_0_1_am_0 "wb_adr_5_i_0_1_am[0]") (joined + (portRef Z (instanceRef wb_adr_5_i_0_1_am_0)) + (portRef BLUT (instanceRef wb_adr_5_i_0_1_0)) + )) + (net (rename wb_adr_5_i_0_1_bm_0 "wb_adr_5_i_0_1_bm[0]") (joined + (portRef Z (instanceRef wb_adr_5_i_0_1_bm_0)) + (portRef ALUT (instanceRef wb_adr_5_i_0_1_0)) + )) (net N_1 (joined (portRef CIN (instanceRef FS_cry_0_0)) )) diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.jed b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.jed index 9a2c0f9..7285bf2 100644 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.jed +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.jed @@ -2,7 +2,7 @@ NOTE Diamond (64-bit) 3.12.1.454 JEDEC Compatible Fuse File.* NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation.* NOTE All Rights Reserved.* -NOTE DATE CREATED: Thu Oct 19 23:51:24 2023* +NOTE DATE CREATED: Sat Nov 18 02:06:29 2023* NOTE DESIGN NAME: RAM2GS_LCMXO2_1200HC_impl1.ncd* NOTE DEVICE NAME: LCMXO2-1200HC-4TQFP100* NOTE JEDEC FILE STATUS: Final Version 1.95* @@ -16,7 +16,7 @@ NOTE PINS nRCAS : 52 : out* NOTE PINS nRRAS : 54 : out* NOTE PINS nRWE : 49 : out* NOTE PINS RCKE : 53 : out* -NOTE PINS RCLKout : 62 : out* +NOTE PINS RCLKout : 60 : out* NOTE PINS RCLK : 63 : in* NOTE PINS nRCS : 57 : out* NOTE PINS RD[7] : 43 : inout* @@ -28,7 +28,7 @@ NOTE PINS RD[2] : 38 : inout* NOTE PINS RD[1] : 37 : inout* NOTE PINS RA[11] : 59 : out* NOTE PINS RA[10] : 64 : out* -NOTE PINS RA[9] : 47 : out* +NOTE PINS RA[9] : 62 : out* NOTE PINS RA[8] : 65 : out* NOTE PINS RA[7] : 75 : out* NOTE PINS RA[6] : 68 : out* @@ -38,7 +38,7 @@ NOTE PINS RA[3] : 71 : out* NOTE PINS RA[2] : 69 : out* NOTE PINS RA[1] : 67 : out* NOTE PINS RA[0] : 66 : out* -NOTE PINS RBA[1] : 60 : out* +NOTE PINS RBA[1] : 47 : out* NOTE PINS RBA[0] : 58 : out* NOTE PINS LED : 34 : out* NOTE PINS nFWE : 15 : in* @@ -76,529 +76,536 @@ QF343936* G0* F0* L000000 -11111111111111111011110110110011111111111111111100111011000000000000000000000000000000100000000000000000000000001100000000001001 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00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 @@ -2770,10 +2770,10 @@ L302720 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 * -C3886* +C6298* NOTE FEATURE_ROW* E0000000000000000000000000000000000000000000000000000000000000000 0000010001100000* NOTE User Electronic Signature Data* UH00000000* -8207 +83C1 diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.mrp b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.mrp index fea8aaf..4ecf228 100644 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.mrp +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.mrp @@ -15,20 +15,20 @@ Target Vendor: LATTICE Target Device: LCMXO2-1200HCTQFP100 Target Performance: 4 Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454 -Mapped on: 10/19/23 23:50:56 +Mapped on: 11/18/23 02:05:52 Design Summary -------------- - Number of registers: 110 out of 1520 (7%) - PFU registers: 85 out of 1280 (7%) + Number of registers: 109 out of 1520 (7%) + PFU registers: 84 out of 1280 (7%) PIO registers: 25 out of 240 (10%) - Number of SLICEs: 115 out of 640 (18%) - SLICEs as Logic/ROM: 115 out of 640 (18%) + Number of SLICEs: 120 out of 640 (19%) + SLICEs as Logic/ROM: 120 out of 640 (19%) SLICEs as RAM: 0 out of 480 (0%) SLICEs as Carry: 10 out of 640 (2%) - Number of LUT4s: 229 out of 1280 (18%) - Number used as logic LUTs: 209 + Number of LUT4s: 238 out of 1280 (19%) + Number used as logic LUTs: 218 Number used as distributed RAM: 0 Number used as ripple logic: 20 Number used as shift registers: 0 @@ -66,7 +66,7 @@ Design Summary -Design: RAM2GS Date: 10/19/23 23:50:56 +Design: RAM2GS Date: 11/18/23 02:05:52 Design Summary (cont) --------------------- @@ -82,13 +82,13 @@ Design Summary (cont) Number of clocks: 4 Net PHI2_c: 20 loads, 9 rising, 11 falling (Driver: PIO PHI2 ) Net RCLK_c: 48 loads, 48 rising, 0 falling (Driver: PIO RCLK ) - Net nCRAS_c: 10 loads, 0 rising, 10 falling (Driver: PIO nCRAS ) + Net nCRAS_c: 9 loads, 0 rising, 9 falling (Driver: PIO nCRAS ) Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS ) Number of Clock Enables: 5 - Net N_103: 1 loads, 1 LSLICEs + Net wb_cyc_stb_2_sqmuxa_i_0_0: 1 loads, 1 LSLICEs Net XOR8MEG18: 5 loads, 5 LSLICEs - Net N_122: 9 loads, 9 LSLICEs - Net N_244_i: 2 loads, 2 LSLICEs + Net N_126_i: 9 loads, 9 LSLICEs + Net N_261_i: 2 loads, 2 LSLICEs Net CmdUFMData_1_sqmuxa: 1 loads, 1 LSLICEs Number of LSRs: 5 Net RA10s_i: 1 loads, 0 LSLICEs @@ -98,16 +98,16 @@ Design Summary (cont) Net RASr2: 2 loads, 2 LSLICEs Number of nets driven by tri-state buffers: 0 Top 10 highest fanout non-clock nets: - Net InitReady: 31 loads - Net FS[12]: 23 loads - Net FS[13]: 23 loads + Net InitReady: 40 loads + Net FS[13]: 22 loads Net FS[11]: 21 loads - Net N_132: 20 loads - Net FS[14]: 18 loads - Net FS[10]: 16 loads - Net FS[9]: 14 loads + Net FS[12]: 19 loads + Net FS[14]: 19 loads + Net FS[10]: 18 loads + Net FS[9]: 17 loads Net Ready: 14 loads Net Ready_fast: 14 loads + Net CO0: 12 loads @@ -132,7 +132,7 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will -Design: RAM2GS Date: 10/19/23 23:50:56 +Design: RAM2GS Date: 11/18/23 02:05:52 IO (PIO) Attributes ------------------- @@ -198,7 +198,7 @@ IO (PIO) Attributes -Design: RAM2GS Date: 10/19/23 23:50:56 +Design: RAM2GS Date: 11/18/23 02:05:52 IO (PIO) Attributes (cont) -------------------------- @@ -264,7 +264,7 @@ IO (PIO) Attributes (cont) -Design: RAM2GS Date: 10/19/23 23:50:56 +Design: RAM2GS Date: 11/18/23 02:05:52 IO (PIO) Attributes (cont) -------------------------- @@ -330,7 +330,7 @@ Signal ufmefb/I2C1IRQO undriven or does not drive anything - clipped. -Design: RAM2GS Date: 10/19/23 23:50:56 +Design: RAM2GS Date: 11/18/23 02:05:52 Removed logic (cont) -------------------- @@ -396,7 +396,7 @@ Embedded Functional Block Connection Summary -Design: RAM2GS Date: 10/19/23 23:50:56 +Design: RAM2GS Date: 11/18/23 02:05:52 Embedded Functional Block Connection Summary (cont) --------------------------------------------------- @@ -435,7 +435,7 @@ Run Time and Memory Usage Total CPU Time: 0 secs Total REAL Time: 0 secs - Peak Memory Usage: 63 MB + Peak Memory Usage: 64 MB diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.pad b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.pad index 3c05c43..9a7deec 100644 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.pad +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.pad @@ -6,7 +6,7 @@ Performance Grade: 4 PACKAGE: TQFP100 Package Status: Final Version 1.44 -Thu Oct 19 23:51:05 2023 +Sat Nov 18 02:06:05 2023 Pinout by Port Name: +-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ @@ -53,12 +53,12 @@ Pinout by Port Name: | RA[6] | 68/1 | LVCMOS33_OUT | PR4B | | | DRIVE:4mA SLEW:SLOW | | RA[7] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW | | RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW | -| RA[9] | 47/2 | LVCMOS33_OUT | PB18D | | | DRIVE:4mA SLEW:SLOW | +| RA[9] | 62/1 | LVCMOS33_OUT | PR5D | | | DRIVE:4mA SLEW:SLOW | | RBA[0] | 58/1 | LVCMOS33_OUT | PR9A | | | DRIVE:4mA SLEW:SLOW | -| RBA[1] | 60/1 | LVCMOS33_OUT | PR8C | | | DRIVE:4mA SLEW:SLOW | +| RBA[1] | 47/2 | LVCMOS33_OUT | PB18D | | | DRIVE:4mA SLEW:SLOW | | RCKE | 53/1 | LVCMOS33_OUT | PR9D | | | DRIVE:4mA SLEW:SLOW | | RCLK | 63/1 | LVCMOS33_IN | PR5C | | | CLAMP:ON HYSTERESIS:SMALL | -| RCLKout | 62/1 | LVCMOS33_OUT | PR5D | | | DRIVE:4mA SLEW:FAST | +| RCLKout | 60/1 | LVCMOS33_OUT | PR8C | | | DRIVE:24mA SLEW:FAST | | RDQMH | 51/1 | LVCMOS33_OUT | PR10D | | | DRIVE:4mA SLEW:SLOW | | RDQML | 48/2 | LVCMOS33_OUT | PB20C | | | DRIVE:4mA SLEW:SLOW | | RD[0] | 36/2 | LVCMOS33_BIDI | PB11C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | @@ -135,7 +135,7 @@ Pinout by Pin Number: | 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB18A | | | | | 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB18B | | | | | 45/2 | unused, PULL:DOWN | | | PB18C | | | | -| 47/2 | RA[9] | LOCATED | LVCMOS33_OUT | PB18D | | | | +| 47/2 | RBA[1] | LOCATED | LVCMOS33_OUT | PB18D | | | | | 48/2 | RDQML | LOCATED | LVCMOS33_OUT | PB20C | SN | | | | 49/2 | nRWE | LOCATED | LVCMOS33_OUT | PB20D | SI/SISPI | | | | 51/1 | RDQMH | LOCATED | LVCMOS33_OUT | PR10D | DQ1 | | | @@ -145,9 +145,9 @@ Pinout by Pin Number: | 57/1 | nRCS | LOCATED | LVCMOS33_OUT | PR9B | DQ1 | | | | 58/1 | RBA[0] | LOCATED | LVCMOS33_OUT | PR9A | DQ1 | | | | 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR8D | DQ1 | | | -| 60/1 | RBA[1] | LOCATED | LVCMOS33_OUT | PR8C | DQ1 | | | +| 60/1 | RCLKout | LOCATED | LVCMOS33_OUT | PR8C | DQ1 | | | | 61/1 | unused, PULL:DOWN | | | PR8A | DQS1 | | | -| 62/1 | RCLKout | LOCATED | LVCMOS33_OUT | PR5D | PCLKC1_0/DQ0 | | | +| 62/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5D | PCLKC1_0/DQ0 | | | | 63/1 | RCLK | LOCATED | LVCMOS33_IN | PR5C | PCLKT1_0/DQ0 | | | | 64/1 | RA[10] | LOCATED | LVCMOS33_OUT | PR5B | DQS0N | | | | 65/1 | RA[8] | LOCATED | LVCMOS33_OUT | PR5A | DQS0 | | | @@ -265,12 +265,12 @@ LOCATE COMP "RA[5]" SITE "70"; LOCATE COMP "RA[6]" SITE "68"; LOCATE COMP "RA[7]" SITE "75"; LOCATE COMP "RA[8]" SITE "65"; -LOCATE COMP "RA[9]" SITE "47"; +LOCATE COMP "RA[9]" SITE "62"; LOCATE COMP "RBA[0]" SITE "58"; -LOCATE COMP "RBA[1]" SITE "60"; +LOCATE COMP "RBA[1]" SITE "47"; LOCATE COMP "RCKE" SITE "53"; LOCATE COMP "RCLK" SITE "63"; -LOCATE COMP "RCLKout" SITE "62"; +LOCATE COMP "RCLKout" SITE "60"; LOCATE COMP "RDQMH" SITE "51"; LOCATE COMP "RDQML" SITE "48"; LOCATE COMP "RD[0]" SITE "36"; @@ -299,5 +299,5 @@ Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Thu Oct 19 23:51:08 2023 +Sat Nov 18 02:06:09 2023 diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.prf b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.prf index a31ef81..cc2a9db 100644 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.prf +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.prf @@ -1,5 +1,5 @@ SCHEMATIC START ; -# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Thu Oct 19 23:50:57 2023 +# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Sat Nov 18 02:05:53 2023 SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ; LOCATE COMP "RD[0]" SITE "36" ; @@ -11,7 +11,7 @@ LOCATE COMP "nRCAS" SITE "52" ; LOCATE COMP "nRRAS" SITE "54" ; LOCATE COMP "nRWE" SITE "49" ; LOCATE COMP "RCKE" SITE "53" ; -LOCATE COMP "RCLKout" SITE "62" ; +LOCATE COMP "RCLKout" SITE "60" ; LOCATE COMP "RCLK" SITE "63" ; LOCATE COMP "nRCS" SITE "57" ; LOCATE COMP "RD[7]" SITE "43" ; @@ -23,7 +23,7 @@ LOCATE COMP "RD[2]" SITE "38" ; LOCATE COMP "RD[1]" SITE "37" ; LOCATE COMP "RA[11]" SITE "59" ; LOCATE COMP "RA[10]" SITE "64" ; -LOCATE COMP "RA[9]" SITE "47" ; +LOCATE COMP "RA[9]" SITE "62" ; LOCATE COMP "RA[8]" SITE "65" ; LOCATE COMP "RA[7]" SITE "75" ; LOCATE COMP "RA[6]" SITE "68" ; @@ -33,7 +33,7 @@ LOCATE COMP "RA[3]" SITE "71" ; LOCATE COMP "RA[2]" SITE "69" ; LOCATE COMP "RA[1]" SITE "67" ; LOCATE COMP "RA[0]" SITE "66" ; -LOCATE COMP "RBA[1]" SITE "60" ; +LOCATE COMP "RBA[1]" SITE "47" ; LOCATE COMP "RBA[0]" SITE "58" ; LOCATE COMP "LED" SITE "34" ; LOCATE COMP "nFWE" SITE "15" ; diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.srr b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.srr index 21fb607..e3ab859 100644 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.srr +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.srr @@ -3,7 +3,7 @@ #OS: Windows 8 6.2 #Hostname: ZANEMACWIN11 -# Thu Oct 19 23:50:47 2023 +# Sat Nov 18 02:05:40 2023 #Implementation: impl1 @@ -51,19 +51,17 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202 @I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v" (library work) @I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC\REFB.v" (library work) Verilog syntax check successful! - -Compiler output is up to date. No re-compile necessary - +File \\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v changed - recompiling Selecting top level module RAM2GS @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1601:7:1601:12|Synthesizing module ODDRXE in library work. Running optimization stage 1 on ODDRXE ....... -Finished optimization stage 1 on ODDRXE (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB) +Finished optimization stage 1 on ODDRXE (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB) @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work. Running optimization stage 1 on VHI ....... -Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB) +Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB) @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work. Running optimization stage 1 on VLO ....... -Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB) +Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB) @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work. Running optimization stage 1 on EFB ....... Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB) @@ -71,9 +69,6 @@ Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: Running optimization stage 1 on REFB ....... Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB) @N: CG364 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v":1:7:1:12|Synthesizing module RAM2GS in library work. -@W: CS263 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v":46:6:46:6|Port-width mismatch for port D0. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port. -@W: CS263 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v":46:14:46:14|Port-width mismatch for port D1. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port. -@W: CS263 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v":47:7:47:7|Port-width mismatch for port RST. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port. Running optimization stage 1 on RAM2GS ....... Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB) Running optimization stage 2 on RAM2GS ....... @@ -89,12 +84,12 @@ Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: Running optimization stage 2 on ODDRXE ....... Finished optimization stage 2 on ODDRXE (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) -At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 96MB peak: 97MB) +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Oct 19 23:50:47 2023 +# Sat Nov 18 02:05:41 2023 ###########################################################] ###########################################################[ @@ -121,7 +116,7 @@ At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Oct 19 23:50:48 2023 +# Sat Nov 18 02:05:41 2023 ###########################################################] @@ -136,7 +131,7 @@ At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Oct 19 23:50:48 2023 +# Sat Nov 18 02:05:41 2023 ###########################################################] ###########################################################[ @@ -164,10 +159,10 @@ At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Oct 19 23:50:49 2023 +# Sat Nov 18 02:05:43 2023 ###########################################################] -# Thu Oct 19 23:50:49 2023 +# Sat Nov 18 02:05:43 2023 Copyright (C) 1994-2021 Synopsys, Inc. @@ -186,7 +181,7 @@ Implementation : impl1 Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @ -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB) +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB) Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 140MB) @@ -213,7 +208,6 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h @W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. @N: FX493 |Applying initial value "0" on instance Ready. @N: FX493 |Applying initial value "0" on instance RCKE. -@N: FX493 |Applying initial value "0" on instance LEDEN. @N: FX493 |Applying initial value "0" on instance n8MEGEN. @N: FX493 |Applying initial value "1" on instance nRCAS. @N: FX493 |Applying initial value "0" on instance CmdLEDEN. @@ -239,11 +233,11 @@ Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapse Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB) -Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) +Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB) @N: FX1184 |Applying syn_allowed_resources blockrams=7 on top level netlist RAM2GS -Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB) @@ -324,13 +318,13 @@ Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:0 Pre-mapping successful! -At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 103MB peak: 185MB) +At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 185MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu Oct 19 23:50:50 2023 +# Sat Nov 18 02:05:44 2023 ###########################################################] -# Thu Oct 19 23:50:50 2023 +# Sat Nov 18 02:05:44 2023 Copyright (C) 1994-2021 Synopsys, Inc. @@ -349,42 +343,42 @@ Implementation : impl1 Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @ -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB) +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB) @N: MF916 |Option synthesis_strategy=base is enabled. @N: MF248 |Running in 64-bit mode. @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 139MB) +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB) -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 139MB) +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB) -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB) +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB) -Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 178MB peak: 178MB) +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 179MB peak: 179MB) -Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) +Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB) -@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":169:4:169:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] -@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":156:4:156:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] +@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":166:4:166:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] +@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":153:4:153:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] @N: FX493 |Applying initial value "0" on instance IS[0]. @W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. @N: FX493 |Applying initial value "0" on instance IS[1]. @N: FX493 |Applying initial value "0" on instance IS[2]. @N: FX493 |Applying initial value "0" on instance IS[3]. -Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 185MB peak: 185MB) +Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 185MB peak: 185MB) -Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB) +Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB) Available hyper_sources - for debug and ip models @@ -406,63 +400,51 @@ Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CP Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB) -Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 195MB peak: 195MB) +Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 197MB peak: 197MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ - 1 0h:00m:01s -2.76ns 193 / 106 - 2 0h:00m:01s -2.76ns 209 / 106 - 3 0h:00m:01s -2.76ns 208 / 106 - 4 0h:00m:01s -2.76ns 206 / 106 - 5 0h:00m:01s -2.76ns 206 / 106 - 6 0h:00m:01s -2.76ns 205 / 106 - 7 0h:00m:01s -2.76ns 205 / 106 -@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":310:4:310:9|Replicating instance CmdValid (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing. -@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":169:4:169:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing. -@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":127:4:127:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing. -@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":127:4:127:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing. + 1 0h:00m:02s -2.98ns 202 / 106 + 2 0h:00m:02s -2.98ns 215 / 106 + 3 0h:00m:02s -2.76ns 215 / 106 +@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":124:4:124:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing. +@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":307:4:307:9|Replicating instance CmdValid (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing. +@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":166:4:166:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing. Timing driven replication report -Added 4 Registers via timing driven replication -Added 2 LUTs via timing driven replication +Added 3 Registers via timing driven replication +Added 1 LUTs via timing driven replication - 8 0h:00m:01s -1.83ns 209 / 110 - 9 0h:00m:01s -1.83ns 209 / 110 - 10 0h:00m:01s -1.83ns 209 / 110 - 11 0h:00m:01s -1.83ns 209 / 110 - 12 0h:00m:01s -1.83ns 209 / 110 + 4 0h:00m:02s -1.97ns 220 / 109 - 13 0h:00m:01s -1.83ns 208 / 110 - 14 0h:00m:01s -1.83ns 209 / 110 - 15 0h:00m:01s -1.83ns 209 / 110 - 16 0h:00m:01s -1.83ns 209 / 110 + 5 0h:00m:02s -1.97ns 220 / 109 -Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 196MB peak: 196MB) +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 197MB peak: 197MB) @N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. -Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 196MB peak: 196MB) +Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 198MB peak: 198MB) -Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 160MB peak: 196MB) +Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 160MB peak: 198MB) Writing Analyst data base \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2GS_LCMXO2_1200HC_impl1_m.srm -Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 197MB peak: 197MB) +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 198MB peak: 198MB) Writing EDIF Netlist and constraint files @N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC\impl1\RAM2GS_LCMXO2_1200HC_impl1.edi @N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF -Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 201MB peak: 201MB) +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 203MB peak: 203MB) -Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 201MB peak: 202MB) +Finished Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 203MB peak: 203MB) -Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 200MB peak: 202MB) +Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 201MB peak: 203MB) -@W: MT246 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":43:8:43:10|Blackbox ODDRXE is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) +@W: MT246 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":43:11:43:19|Blackbox ODDRXE is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W: MT246 :"\\mac\icloud\repos\ram2gs\cpld\lcmxo2-1200hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @N: MT615 |Found clock RCLK with period 16.00ns @N: MT615 |Found clock PHI2 with period 350.00ns @@ -471,7 +453,7 @@ Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:0 ##### START OF TIMING REPORT #####[ -# Timing report written on Thu Oct 19 23:50:54 2023 +# Timing report written on Sat Nov 18 02:05:49 2023 # @@ -491,15 +473,15 @@ Performance Summary ******************* -Worst slack in design: -1.828 +Worst slack in design: -2.605 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------- PHI2 2.9 MHz 1.0 MHz 350.000 989.870 -1.828 declared default_clkgroup -RCLK 62.5 MHz 22.1 MHz 16.000 45.251 -0.784 declared default_clkgroup +RCLK 62.5 MHz 17.3 MHz 16.000 57.686 -0.784 declared default_clkgroup nCCAS 2.9 MHz NA 350.000 NA NA declared default_clkgroup -nCRAS 2.9 MHz 1.1 MHz 350.000 942.410 -1.693 declared default_clkgroup +nCRAS 2.9 MHz 0.8 MHz 350.000 1261.890 -2.605 declared default_clkgroup System 100.0 MHz NA 10.000 NA 12.918 system system_clkgroup =================================================================================================================== Estimated period and frequency reported as NA means no slack depends directly on the clock waveform @@ -522,12 +504,12 @@ Starting Ending | constraint slack | constraint slack | constraint --------------------------------------------------------------------------------------------------------------- System RCLK | 16.000 12.918 | No paths - | No paths - | No paths - RCLK System | 16.000 14.956 | No paths - | No paths - | No paths - -RCLK RCLK | 16.000 9.100 | No paths - | No paths - | No paths - +RCLK RCLK | 16.000 9.237 | No paths - | No paths - | No paths - RCLK PHI2 | 2.000 0.216 | No paths - | 1.000 -0.676 | No paths - RCLK nCRAS | No paths - | No paths - | 1.000 -0.784 | No paths - PHI2 RCLK | No paths - | No paths - | No paths - | 1.000 -1.828 -PHI2 PHI2 | No paths - | 350.000 347.156 | 175.000 169.041 | 175.000 173.428 -nCRAS RCLK | No paths - | No paths - | No paths - | 1.000 -1.693 +PHI2 PHI2 | No paths - | 350.000 346.603 | 175.000 169.081 | 175.000 173.428 +nCRAS RCLK | No paths - | No paths - | No paths - | 1.000 -2.605 =============================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. @@ -561,30 +543,30 @@ CmdLEDEN PHI2 FD1P3AX Q CmdLEDEN 1.044 Cmdn8MEGEN PHI2 FD1P3AX Q Cmdn8MEGEN 1.044 -1.589 CmdUFMWrite PHI2 FD1P3AX Q CmdUFMWrite 1.044 -0.572 CmdUFMData PHI2 FD1P3AX Q CmdUFMData 0.972 -0.500 -Bank_0io[0] PHI2 IFS1P3DX Q Bank[0] 0.972 169.041 -Bank_0io[2] PHI2 IFS1P3DX Q Bank[2] 0.972 169.041 -Bank_0io[4] PHI2 IFS1P3DX Q Bank[4] 0.972 169.041 +Bank_0io[1] PHI2 IFS1P3DX Q Bank[1] 0.972 169.081 +Bank_0io[2] PHI2 IFS1P3DX Q Bank[2] 0.972 169.081 +Bank_0io[3] PHI2 IFS1P3DX Q Bank[3] 0.972 169.081 ========================================================================================== Ending Points with Worst Slack ****************************** - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------- -wb_adr[0] PHI2 FD1P3AX SP N_122 0.528 -1.828 -wb_adr[1] PHI2 FD1P3AX SP N_122 0.528 -1.828 -wb_adr[2] PHI2 FD1P3AX SP N_122 0.528 -1.828 -wb_adr[3] PHI2 FD1P3AX SP N_122 0.528 -1.828 -wb_adr[4] PHI2 FD1P3AX SP N_122 0.528 -1.828 -wb_adr[5] PHI2 FD1P3AX SP N_122 0.528 -1.828 -wb_adr[6] PHI2 FD1P3AX SP N_122 0.528 -1.828 -wb_adr[7] PHI2 FD1P3AX SP N_122 0.528 -1.828 -wb_dati[0] PHI2 FD1P3AX SP N_122 0.528 -1.828 -wb_dati[1] PHI2 FD1P3AX SP N_122 0.528 -1.828 -============================================================================== + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------- +wb_adr[0] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +wb_adr[1] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +wb_adr[2] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +wb_adr[3] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +wb_adr[4] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +wb_adr[5] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +wb_adr[6] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +wb_adr[7] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +wb_dati[0] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +wb_dati[1] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +================================================================================ @@ -600,7 +582,7 @@ Path information for path number 1: - Propagation time: 2.357 - Clock delay at starting point: 0.000 (ideal) - = Slack (critical) : -1.828 + = Slack (non-critical) : -1.828 Number of logic level(s): 1 Starting point: CmdUFMShift / Q @@ -615,7 +597,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r - CmdUFMShift Net - - - - 2 CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r - CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r - -N_122 Net - - - - 17 +N_126_i Net - - - - 17 wb_adr[0] FD1P3AX SP In 0.000 2.357 r - ========================================================================================= @@ -628,7 +610,7 @@ Path information for path number 2: - Propagation time: 2.357 - Clock delay at starting point: 0.000 (ideal) - = Slack (critical) : -1.828 + = Slack (non-critical) : -1.828 Number of logic level(s): 1 Starting point: CmdUFMShift / Q @@ -643,7 +625,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r - CmdUFMShift Net - - - - 2 CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r - CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r - -N_122 Net - - - - 17 +N_126_i Net - - - - 17 wb_adr[7] FD1P3AX SP In 0.000 2.357 r - ========================================================================================= @@ -656,7 +638,7 @@ Path information for path number 3: - Propagation time: 2.357 - Clock delay at starting point: 0.000 (ideal) - = Slack (critical) : -1.828 + = Slack (non-critical) : -1.828 Number of logic level(s): 1 Starting point: CmdUFMShift / Q @@ -671,7 +653,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r - CmdUFMShift Net - - - - 2 CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r - CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r - -N_122 Net - - - - 17 +N_126_i Net - - - - 17 wb_adr[6] FD1P3AX SP In 0.000 2.357 r - ========================================================================================= @@ -684,7 +666,7 @@ Path information for path number 4: - Propagation time: 2.357 - Clock delay at starting point: 0.000 (ideal) - = Slack (critical) : -1.828 + = Slack (non-critical) : -1.828 Number of logic level(s): 1 Starting point: CmdUFMShift / Q @@ -699,7 +681,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r - CmdUFMShift Net - - - - 2 CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r - CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r - -N_122 Net - - - - 17 +N_126_i Net - - - - 17 wb_adr[5] FD1P3AX SP In 0.000 2.357 r - ========================================================================================= @@ -712,7 +694,7 @@ Path information for path number 5: - Propagation time: 2.357 - Clock delay at starting point: 0.000 (ideal) - = Slack (critical) : -1.828 + = Slack (non-critical) : -1.828 Number of logic level(s): 1 Starting point: CmdUFMShift / Q @@ -727,7 +709,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r - CmdUFMShift Net - - - - 2 CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r - CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r - -N_122 Net - - - - 17 +N_126_i Net - - - - 17 wb_adr[4] FD1P3AX SP In 0.000 2.357 r - ========================================================================================= @@ -750,13 +732,13 @@ Instance Reference Type Pin Net Time Slac Ready_fast RCLK FD1S3AX Q Ready_fast 1.256 -0.784 LEDEN RCLK FD1S3AX Q LEDEN 1.148 -0.676 n8MEGEN RCLK FD1S3AX Q n8MEGEN 1.108 -0.636 -FS[12] RCLK FD1S3AX Q FS[12] 1.288 9.100 -FS[11] RCLK FD1S3AX Q FS[11] 1.280 9.108 -FS[9] RCLK FD1S3AX Q FS[9] 1.256 9.132 -InitReady RCLK FD1S3AX Q InitReady 1.317 9.708 -FS[16] RCLK FD1S3AX Q FS[16] 1.180 9.845 -FS[17] RCLK FD1S3AX Q FS[17] 1.180 9.845 -FS[15] RCLK FD1S3AX Q FS[15] 1.148 9.877 +InitReady RCLK FD1S3AX Q InitReady 1.337 9.237 +FS[16] RCLK FD1S3AX Q FS[16] 1.204 9.371 +FS[17] RCLK FD1S3AX Q FS[17] 1.204 9.371 +FS[15] RCLK FD1S3AX Q FS[15] 1.188 9.387 +S[0] RCLK FD1S3IX Q CO0 1.244 9.873 +S[1] RCLK FD1S3IX Q S[1] 1.236 9.881 +RASr2 RCLK FD1S3AX Q RASr2 1.228 9.889 ================================================================================== @@ -851,6 +833,34 @@ Path information for path number 3: - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.784 + Number of logic level(s): 1 + Starting point: Ready_fast / Q + Ending point: RBA_0io[1] / D + The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK + The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin SCLK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------- +Ready_fast FD1S3AX Q Out 1.256 1.256 r - +Ready_fast Net - - - - 14 +RBAd[1] ORCALUT4 B In 0.000 1.256 r - +RBAd[1] ORCALUT4 Z Out 0.617 1.873 r - +RBAd_0[1] Net - - - - 1 +RBA_0io[1] OFS1P3DX D In 0.000 1.873 r - +================================================================================= + + +Path information for path number 4: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 1.873 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -0.784 + Number of logic level(s): 1 Starting point: Ready_fast / Q Ending point: RowA[1] / D @@ -869,34 +879,6 @@ RowA[1] FD1S3AX D In 0.000 1.873 r - ================================================================================= -Path information for path number 4: - Requested Period: 1.000 - - Setup time: -0.089 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 1.089 - - - Propagation time: 1.873 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : -0.784 - - Number of logic level(s): 1 - Starting point: Ready_fast / Q - Ending point: RowA[4] / D - The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK - The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------- -Ready_fast FD1S3AX Q Out 1.256 1.256 r - -Ready_fast Net - - - - 14 -RowAd[4] ORCALUT4 B In 0.000 1.256 r - -RowAd[4] ORCALUT4 Z Out 0.617 1.873 r - -RowAd_0[4] Net - - - - 1 -RowA[4] FD1S3AX D In 0.000 1.873 r - -================================================================================= - - Path information for path number 5: Requested Period: 1.000 - Setup time: -0.089 @@ -909,7 +891,7 @@ Path information for path number 5: Number of logic level(s): 1 Starting point: Ready_fast / Q - Ending point: RowA[2] / D + Ending point: RowA[5] / D The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK @@ -918,10 +900,10 @@ Name Type Name Dir Delay Time Fan Out(s --------------------------------------------------------------------------------- Ready_fast FD1S3AX Q Out 1.256 1.256 r - Ready_fast Net - - - - 14 -RowAd[2] ORCALUT4 B In 0.000 1.256 r - -RowAd[2] ORCALUT4 Z Out 0.617 1.873 r - -RowAd_0[2] Net - - - - 1 -RowA[2] FD1S3AX D In 0.000 1.873 r - +RowAd[5] ORCALUT4 B In 0.000 1.256 r - +RowAd[5] ORCALUT4 Z Out 0.617 1.873 f - +RowAd_0[5] Net - - - - 1 +RowA[5] FD1S3AX D In 0.000 1.873 f - ================================================================================= @@ -936,15 +918,14 @@ Detailed Report for Clock: nCRAS Starting Points with Worst Slack ******************************** - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock --------------------------------------------------------------------------------- -CBR nCRAS FD1S3AX Q CBR 1.148 -1.693 -FWEr nCRAS FD1S3AX Q FWEr 1.148 -1.693 -CBR_fast nCRAS FD1S3AX Q CBR_fast 1.044 -1.661 -FWEr_fast nCRAS FD1S3AX Q FWEr_fast 0.972 -1.589 -================================================================================ + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------ +CBR_fast nCRAS FD1S3AX Q CBR_fast 0.972 -2.605 +CBR nCRAS FD1S3AX Q CBR 1.180 -1.797 +FWEr nCRAS FD1S3AX Q FWEr 1.180 -1.797 +============================================================================== Ending Points with Worst Slack @@ -954,11 +935,11 @@ Ending Points with Worst Slack Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------- -RCKEEN nCRAS FD1S3AX D RCKEEN_8 1.089 -1.693 -nRCAS_0io nCRAS OFS1P3BX D N_242_i 1.089 -1.693 -nRCS_0io nCRAS OFS1P3BX D N_28_i 1.089 -1.693 -nRowColSel nCRAS FD1S3IX D nRowColSel_0_0 1.089 -1.693 -nRWE_0io nCRAS OFS1P3BX D N_37_i 1.089 -1.661 +nRCAS_0io nCRAS OFS1P3BX D N_251_i 1.089 -2.605 +nRCS_0io nCRAS OFS1P3BX D N_37_i 1.089 -1.797 +nRWE_0io nCRAS OFS1P3BX D N_252_i 1.089 -1.797 +nRowColSel nCRAS FD1S3IX D nRowColSel_0_0 1.089 -1.797 +RCKEEN nCRAS FD1S3AX D RCKEEN_8 1.089 -1.725 ======================================================================================== @@ -973,29 +954,32 @@ Path information for path number 1: + Clock delay at ending point: 0.000 (ideal) = Required time: 1.089 - - Propagation time: 2.781 + - Propagation time: 3.694 - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : -1.693 + = Slack (critical) : -2.605 - Number of logic level(s): 2 - Starting point: CBR / Q + Number of logic level(s): 3 + Starting point: CBR_fast / Q Ending point: nRCAS_0io / D The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------- -CBR FD1S3AX Q Out 1.148 1.148 r - -CBR Net - - - - 4 -nRCAS_0io_RNO_0 ORCALUT4 A In 0.000 1.148 r - -nRCAS_0io_RNO_0 ORCALUT4 Z Out 1.017 2.165 f - -N_242_i_1 Net - - - - 1 -nRCAS_0io_RNO ORCALUT4 C In 0.000 2.165 f - -nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.781 r - -N_242_i Net - - - - 1 -nRCAS_0io OFS1P3BX D In 0.000 2.781 r - -================================================================================== +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +------------------------------------------------------------------------------------ +CBR_fast FD1S3AX Q Out 0.972 0.972 r - +CBR_fast Net - - - - 1 +CBR_fast_RNIQ31K1 ORCALUT4 A In 0.000 0.972 r - +CBR_fast_RNIQ31K1 ORCALUT4 Z Out 1.089 2.061 r - +nRCAS_0_sqmuxa_1 Net - - - - 2 +nRCAS_0io_RNO_0 ORCALUT4 B In 0.000 2.061 r - +nRCAS_0io_RNO_0 ORCALUT4 Z Out 1.017 3.077 r - +N_251_i_sx Net - - - - 1 +nRCAS_0io_RNO ORCALUT4 C In 0.000 3.077 r - +nRCAS_0io_RNO ORCALUT4 Z Out 0.617 3.694 f - +N_251_i Net - - - - 1 +nRCAS_0io OFS1P3BX D In 0.000 3.694 f - +==================================================================================== Path information for path number 2: @@ -1004,29 +988,29 @@ Path information for path number 2: + Clock delay at ending point: 0.000 (ideal) = Required time: 1.089 - - Propagation time: 2.781 + - Propagation time: 2.885 - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : -1.693 + = Slack (non-critical) : -1.797 Number of logic level(s): 2 - Starting point: FWEr / Q - Ending point: RCKEEN / D + Starting point: CBR / Q + Ending point: nRCS_0io / D The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK - The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK + The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------- -FWEr FD1S3AX Q Out 1.148 1.148 r - -FWEr Net - - - - 4 -RCKEEN_8_u_1_0 ORCALUT4 C In 0.000 1.148 r - -RCKEEN_8_u_1_0 ORCALUT4 Z Out 1.017 2.165 r - -RCKEEN_8_u_1 Net - - - - 1 -RCKEEN_8_u ORCALUT4 C In 0.000 2.165 r - -RCKEEN_8_u ORCALUT4 Z Out 0.617 2.781 r - -RCKEEN_8 Net - - - - 1 -RCKEEN FD1S3AX D In 0.000 2.781 r - -================================================================================= +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +------------------------------------------------------------------------------------ +CBR FD1S3AX Q Out 1.180 1.180 r - +CBR Net - - - - 5 +RCKEEN_8_u_0_a2_2 ORCALUT4 A In 0.000 1.180 r - +RCKEEN_8_u_0_a2_2 ORCALUT4 Z Out 1.089 2.269 f - +N_141 Net - - - - 2 +nRCS_0io_RNO ORCALUT4 A In 0.000 2.269 f - +nRCS_0io_RNO ORCALUT4 Z Out 0.617 2.885 r - +N_37_i Net - - - - 1 +nRCS_0io OFS1P3BX D In 0.000 2.885 r - +==================================================================================== Path information for path number 3: @@ -1035,71 +1019,9 @@ Path information for path number 3: + Clock delay at ending point: 0.000 (ideal) = Required time: 1.089 - - Propagation time: 2.781 + - Propagation time: 2.885 - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : -1.693 - - Number of logic level(s): 2 - Starting point: CBR / Q - Ending point: nRowColSel / D - The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK - The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------- -CBR FD1S3AX Q Out 1.148 1.148 r - -CBR Net - - - - 4 -nRowColSel_0_0_a3_0 ORCALUT4 B In 0.000 1.148 r - -nRowColSel_0_0_a3_0 ORCALUT4 Z Out 1.017 2.165 f - -N_255 Net - - - - 1 -nRowColSel_0_0 ORCALUT4 B In 0.000 2.165 f - -nRowColSel_0_0 ORCALUT4 Z Out 0.617 2.781 f - -nRowColSel_0_0 Net - - - - 1 -nRowColSel FD1S3IX D In 0.000 2.781 f - -====================================================================================== - - -Path information for path number 4: - Requested Period: 1.000 - - Setup time: -0.089 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 1.089 - - - Propagation time: 2.781 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : -1.693 - - Number of logic level(s): 2 - Starting point: FWEr / Q - Ending point: nRCS_0io / D - The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK - The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------- -FWEr FD1S3AX Q Out 1.148 1.148 r - -FWEr Net - - - - 4 -nRCS_0io_RNO_0 ORCALUT4 B In 0.000 1.148 r - -nRCS_0io_RNO_0 ORCALUT4 Z Out 1.017 2.165 f - -nRCS_0io_RNO_0 Net - - - - 1 -nRCS_0io_RNO ORCALUT4 B In 0.000 2.165 f - -nRCS_0io_RNO ORCALUT4 Z Out 0.617 2.781 r - -N_28_i Net - - - - 1 -nRCS_0io OFS1P3BX D In 0.000 2.781 r - -================================================================================= - - -Path information for path number 5: - Requested Period: 1.000 - - Setup time: -0.089 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 1.089 - - - Propagation time: 2.781 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : -1.693 + = Slack (non-critical) : -1.797 Number of logic level(s): 2 Starting point: FWEr / Q @@ -1110,18 +1032,80 @@ Path information for path number 5: Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------- -FWEr FD1S3AX Q Out 1.148 1.148 r - -FWEr Net - - - - 4 -nRCAS_0io_RNO_0 ORCALUT4 C In 0.000 1.148 r - -nRCAS_0io_RNO_0 ORCALUT4 Z Out 1.017 2.165 r - -N_242_i_1 Net - - - - 1 -nRCAS_0io_RNO ORCALUT4 C In 0.000 2.165 r - -nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.781 f - -N_242_i Net - - - - 1 -nRCAS_0io OFS1P3BX D In 0.000 2.781 f - +FWEr FD1S3AX Q Out 1.180 1.180 r - +FWEr Net - - - - 5 +nRCS_9_u_i_a2_0 ORCALUT4 B In 0.000 1.180 r - +nRCS_9_u_i_a2_0 ORCALUT4 Z Out 1.089 2.269 f - +N_251_i_1 Net - - - - 2 +nRCAS_0io_RNO ORCALUT4 A In 0.000 2.269 f - +nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.885 r - +N_251_i Net - - - - 1 +nRCAS_0io OFS1P3BX D In 0.000 2.885 r - ================================================================================== +Path information for path number 4: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 2.885 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -1.797 + + Number of logic level(s): 2 + Starting point: CBR / Q + Ending point: nRWE_0io / D + The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +------------------------------------------------------------------------------------ +CBR FD1S3AX Q Out 1.180 1.180 r - +CBR Net - - - - 5 +RCKEEN_8_u_0_a2_2 ORCALUT4 A In 0.000 1.180 r - +RCKEEN_8_u_0_a2_2 ORCALUT4 Z Out 1.089 2.269 f - +N_141 Net - - - - 2 +nRWE_0io_RNO ORCALUT4 B In 0.000 2.269 f - +nRWE_0io_RNO ORCALUT4 Z Out 0.617 2.885 r - +N_252_i Net - - - - 1 +nRWE_0io OFS1P3BX D In 0.000 2.885 r - +==================================================================================== + + +Path information for path number 5: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 2.885 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -1.797 + + Number of logic level(s): 2 + Starting point: FWEr / Q + Ending point: nRCAS_0io / D + The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------- +FWEr FD1S3AX Q Out 1.180 1.180 r - +FWEr Net - - - - 5 +nRowColSel_0_0_a2_1 ORCALUT4 B In 0.000 1.180 r - +nRowColSel_0_0_a2_1 ORCALUT4 Z Out 1.089 2.269 r - +N_251_i_1_0 Net - - - - 2 +nRCAS_0io_RNO ORCALUT4 B In 0.000 2.269 r - +nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.885 f - +N_251_i Net - - - - 1 +nRCAS_0io OFS1P3BX D In 0.000 2.885 f - +====================================================================================== + + ==================================== @@ -1146,14 +1130,14 @@ ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 Ending Points with Worst Slack ****************************** - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------ -LEDEN System FD1S3AX D LEDENe_0 16.089 12.918 -n8MEGEN System FD1S3AX D n8MEGENe_0 16.089 12.918 -wb_cyc_stb System FD1P3IX SP N_103 15.528 14.912 -=================================================================================== + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------------------------- +LEDEN System FD1S3AX D LEDENe_0 16.089 12.918 +n8MEGEN System FD1S3AX D n8MEGENe_0 16.089 12.918 +wb_cyc_stb System FD1P3IX SP wb_cyc_stb_2_sqmuxa_i_0_0 15.528 14.912 +================================================================================================== @@ -1178,25 +1162,25 @@ Path information for path number 1: The start point is clocked by System [rising] The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------ -ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 r - -wb_ack Net - - - - 2 -ufmefb.EFBInst_0_RNI8K48 ORCALUT4 C In 0.000 0.000 r - -ufmefb.EFBInst_0_RNI8K48 ORCALUT4 Z Out 0.449 0.449 r - -g0_0_a3_1 Net - - - - 1 -wb_cyc_stb_2_sqmuxa_i_o2_RNI167R ORCALUT4 D In 0.000 0.449 r - -wb_cyc_stb_2_sqmuxa_i_o2_RNI167R ORCALUT4 Z Out 1.017 1.466 r - -N_4 Net - - - - 1 -CmdValid_RNITBH02 ORCALUT4 C In 0.000 1.466 r - -CmdValid_RNITBH02 ORCALUT4 Z Out 1.089 2.554 r - -CmdValid_RNITBH02 Net - - - - 2 -LEDENe ORCALUT4 B In 0.000 2.554 r - -LEDENe ORCALUT4 Z Out 0.617 3.171 r - -LEDENe_0 Net - - - - 1 -LEDEN FD1S3AX D In 0.000 3.171 r - -===================================================================================================== +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +---------------------------------------------------------------------------------------------- +ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 r - +wb_ack Net - - - - 2 +ufmefb.EFBInst_0_RNISGNB ORCALUT4 D In 0.000 0.000 r - +ufmefb.EFBInst_0_RNISGNB ORCALUT4 Z Out 1.017 1.017 r - +g0_0_a3_2 Net - - - - 1 +ufmefb.EFBInst_0_RNISI191 ORCALUT4 C In 0.000 1.017 r - +ufmefb.EFBInst_0_RNISI191 ORCALUT4 Z Out 0.449 1.466 r - +N_4 Net - - - - 1 +CmdValid_RNIOOBE2 ORCALUT4 C In 0.000 1.466 r - +CmdValid_RNIOOBE2 ORCALUT4 Z Out 1.089 2.554 r - +un1_FS_38_i Net - - - - 2 +LEDENe ORCALUT4 C In 0.000 2.554 r - +LEDENe ORCALUT4 Z Out 0.617 3.171 r - +LEDENe_0 Net - - - - 1 +LEDEN FD1S3AX D In 0.000 3.171 r - +============================================================================================== @@ -1204,16 +1188,16 @@ LEDEN FD1S3AX D In 0.000 3 Timing exceptions that could not be applied -Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 201MB peak: 202MB) +Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 202MB peak: 203MB) -Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 201MB peak: 202MB) +Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 202MB peak: 203MB) --------------------------------------- Resource Usage Report Part: lcmxo2_1200hc-4 -Register bits: 110 of 1280 (9%) +Register bits: 109 of 1280 (9%) PIC Latch: 0 I/O cells: 64 @@ -1224,7 +1208,7 @@ CCU2D: 10 EFB: 1 FD1P3AX: 25 FD1P3IX: 2 -FD1S3AX: 54 +FD1S3AX: 53 FD1S3IX: 4 GSR: 1 IB: 25 @@ -1235,15 +1219,16 @@ ODDRXE: 1 OFS1P3BX: 4 OFS1P3DX: 11 OFS1P3JX: 1 -ORCALUT4: 203 +ORCALUT4: 212 +PFUMX: 2 PUR: 1 VHI: 2 VLO: 2 Mapper successful! -At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 78MB peak: 202MB) +At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 78MB peak: 203MB) -Process took 0h:00m:03s realtime, 0h:00m:03s cputime -# Thu Oct 19 23:50:54 2023 +Process took 0h:00m:04s realtime, 0h:00m:04s cputime +# Sat Nov 18 02:05:49 2023 ###########################################################] diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.tw1 b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.tw1 index f7135e6..4f98bf9 100644 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.tw1 +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.tw1 @@ -13,7 +13,7 @@ Setup and Hold Report -------------------------------------------------------------------------------- Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 -Thu Oct 19 23:50:57 2023 +Sat Nov 18 02:05:54 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -42,42 +42,42 @@ Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ; -------------------------------------------------------------------------------- -Passed: The following path meets requirements by 163.779ns (weighted slack = 327.558ns) +Passed: The following path meets requirements by 163.025ns (weighted slack = 326.050ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_0io[0] (from PHI2_c +) - Destination: FF Data in ADSubmitted (to PHI2_c -) + Source: FF Q Bank_0io[1] (from PHI2_c +) + Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 8.469ns (36.0% logic, 64.0% route), 6 logic levels. + Delay: 9.223ns (33.1% logic, 66.9% route), 6 logic levels. Constraint Details: - 8.469ns physical path delay Din[0]_MGIOL to SLICE_10 meets + 9.223ns physical path delay Din[1]_MGIOL to SLICE_17 meets 172.414ns delay constraint less - 0.166ns DIN_SET requirement (totaling 172.248ns) by 163.779ns + 0.166ns DIN_SET requirement (totaling 172.248ns) by 163.025ns Physical Path Details: - Data path Din[0]_MGIOL to SLICE_10: + Data path Din[1]_MGIOL to SLICE_17: Name Fanout Delay (ns) Site Resource -C2INP_DEL --- 0.577 *[0]_MGIOL.CLK to *n[0]_MGIOL.IN Din[0]_MGIOL (from PHI2_c) -ROUTE 1 e 1.234 *n[0]_MGIOL.IN to SLICE_89.A0 Bank[0] -CTOF_DEL --- 0.495 SLICE_89.A0 to SLICE_89.F0 SLICE_89 -ROUTE 1 e 1.234 SLICE_89.F0 to SLICE_75.C1 un1_ADWR_i_o2_10 -CTOF_DEL --- 0.495 SLICE_75.C1 to SLICE_75.F1 SLICE_75 -ROUTE 8 e 0.480 SLICE_75.F1 to SLICE_75.B0 N_294 -CTOF_DEL --- 0.495 SLICE_75.B0 to SLICE_75.F0 SLICE_75 -ROUTE 2 e 1.234 SLICE_75.F0 to SLICE_73.C0 N_382 -CTOF_DEL --- 0.495 SLICE_73.C0 to SLICE_73.F0 SLICE_73 -ROUTE 2 e 1.234 SLICE_73.F0 to SLICE_10.C0 CmdEnable17 -CTOF_DEL --- 0.495 SLICE_10.C0 to SLICE_10.F0 SLICE_10 -ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r_0 (to PHI2_c) +C2INP_DEL --- 0.577 *[1]_MGIOL.CLK to *n[1]_MGIOL.IN Din[1]_MGIOL (from PHI2_c) +ROUTE 1 e 1.234 *n[1]_MGIOL.IN to SLICE_90.A0 Bank[1] +CTOF_DEL --- 0.495 SLICE_90.A0 to SLICE_90.F0 SLICE_90 +ROUTE 1 e 1.234 SLICE_90.F0 to SLICE_80.C0 un1_CmdEnable20_0_0_o2_10 +CTOF_DEL --- 0.495 SLICE_80.C0 to SLICE_80.F0 SLICE_80 +ROUTE 6 e 1.234 SLICE_80.F0 to SLICE_11.C1 N_367 +CTOF_DEL --- 0.495 SLICE_11.C1 to SLICE_11.F1 SLICE_11 +ROUTE 3 e 1.234 SLICE_11.F1 to SLICE_33.B0 CmdEnable16 +CTOF_DEL --- 0.495 SLICE_33.B0 to SLICE_33.F0 SLICE_33 +ROUTE 1 e 1.234 SLICE_33.F0 to SLICE_17.D0 CmdEnable_0_sqmuxa +CTOF_DEL --- 0.495 SLICE_17.D0 to SLICE_17.F0 SLICE_17 +ROUTE 1 e 0.001 SLICE_17.F0 to SLICE_17.DI0 CmdEnable_s (to PHI2_c) -------- - 8.469 (36.0% logic, 64.0% route), 6 logic levels. + 9.223 (33.1% logic, 66.9% route), 6 logic levels. -Report: 57.904MHz is the maximum frequency for this preference. +Report: 53.254MHz is the maximum frequency for this preference. ================================================================================ @@ -118,48 +118,46 @@ Report: 150.150MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; - 868 items scored, 0 timing errors detected. + 891 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- -Passed: The following path meets requirements by 5.761ns +Passed: The following path meets requirements by 5.516ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS[11] (from RCLK_c +) - Destination: FF Data in wb_adr[0] (to RCLK_c +) + Source: FF Q S[0] (from RCLK_c +) + Destination: FF Data in nRWE_0io (to RCLK_c +) - Delay: 10.073ns (34.0% logic, 66.0% route), 7 logic levels. + Delay: 10.331ns (28.3% logic, 71.7% route), 6 logic levels. Constraint Details: - 10.073ns physical path delay SLICE_4 to SLICE_48 meets + 10.331ns physical path delay SLICE_16 to nRWE_MGIOL meets 16.000ns delay constraint less - 0.166ns DIN_SET requirement (totaling 15.834ns) by 5.761ns + 0.153ns DO_SET requirement (totaling 15.847ns) by 5.516ns Physical Path Details: - Data path SLICE_4 to SLICE_48: + Data path SLICE_16 to nRWE_MGIOL: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 SLICE_4.CLK to SLICE_4.Q0 SLICE_4 (from RCLK_c) -ROUTE 21 e 1.234 SLICE_4.Q0 to SLICE_66.B1 FS[11] -CTOF_DEL --- 0.495 SLICE_66.B1 to SLICE_66.F1 SLICE_66 -ROUTE 1 e 0.480 SLICE_66.F1 to SLICE_66.D0 wb_adr_5_i_i_a2_3_0[0] -CTOF_DEL --- 0.495 SLICE_66.D0 to SLICE_66.F0 SLICE_66 -ROUTE 1 e 1.234 SLICE_66.F0 to SLICE_86.D0 wb_adr_5_i_i_1_0_tz_0[0] -CTOF_DEL --- 0.495 SLICE_86.D0 to SLICE_86.F0 SLICE_86 -ROUTE 1 e 1.234 SLICE_86.F0 to SLICE_85.C0 wb_adr_5_i_i_1_0[0] -CTOF_DEL --- 0.495 SLICE_85.C0 to SLICE_85.F0 SLICE_85 -ROUTE 1 e 1.234 SLICE_85.F0 to SLICE_77.D0 wb_adr_5_i_i_1[0] -CTOF_DEL --- 0.495 SLICE_77.D0 to SLICE_77.F0 SLICE_77 -ROUTE 1 e 1.234 SLICE_77.F0 to SLICE_48.D0 wb_adr_5_i_i_5[0] -CTOF_DEL --- 0.495 SLICE_48.D0 to SLICE_48.F0 SLICE_48 -ROUTE 1 e 0.001 SLICE_48.F0 to SLICE_48.DI0 N_283 (to RCLK_c) +REG_DEL --- 0.452 SLICE_16.CLK to SLICE_16.Q0 SLICE_16 (from RCLK_c) +ROUTE 12 e 1.234 SLICE_16.Q0 to SLICE_62.D1 CO0 +CTOF_DEL --- 0.495 SLICE_62.D1 to SLICE_62.F1 SLICE_62 +ROUTE 6 e 1.234 SLICE_62.F1 to SLICE_79.A1 IS_0_sqmuxa_0_o2 +CTOF_DEL --- 0.495 SLICE_79.A1 to SLICE_79.F1 SLICE_79 +ROUTE 2 e 1.234 SLICE_79.F1 to SLICE_28.D1 IS_0_sqmuxa_0_o3 +CTOF_DEL --- 0.495 SLICE_28.D1 to SLICE_28.F1 SLICE_28 +ROUTE 1 e 1.234 SLICE_28.F1 to SLICE_68.D1 nRWE_s_i_a2_1_0 +CTOF_DEL --- 0.495 SLICE_68.D1 to SLICE_68.F1 SLICE_68 +ROUTE 1 e 1.234 SLICE_68.F1 to SLICE_75.D0 nRWE_s_i_tz_0 +CTOF_DEL --- 0.495 SLICE_75.D0 to SLICE_75.F0 SLICE_75 +ROUTE 1 e 1.234 SLICE_75.F0 to *WE_MGIOL.OPOS N_252_i (to RCLK_c) -------- - 10.073 (34.0% logic, 66.0% route), 7 logic levels. + 10.331 (28.3% logic, 71.7% route), 6 logic levels. -Report: 97.666MHz is the maximum frequency for this preference. +Report: 95.383MHz is the maximum frequency for this preference. Report Summary -------------- @@ -167,13 +165,13 @@ Report Summary Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | -FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 57.904 MHz| 6 +FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 53.254 MHz| 6 | | | FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0 | | | FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0 | | | -FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 97.666 MHz| 7 +FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 95.383 MHz| 6 | | | ---------------------------------------------------------------------------- @@ -186,7 +184,7 @@ Clock Domains Analysis Found 4 clocks: -Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12 +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11 No transfer within this clock domain is found Data transfers from: @@ -228,11 +226,11 @@ Timing summary (Setup): Timing errors: 0 Score: 0 Cumulative negative slack: 0 -Constraints cover 1015 paths, 4 nets, and 706 connections (71.10% coverage) +Constraints cover 1038 paths, 4 nets, and 732 connections (72.40% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 -Thu Oct 19 23:50:58 2023 +Sat Nov 18 02:05:54 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -284,7 +282,7 @@ Passed: The following path meets requirements by 0.447ns REG_DEL --- 0.133 SLICE_10.CLK to SLICE_10.Q0 SLICE_10 (from PHI2_c) ROUTE 2 e 0.199 SLICE_10.Q0 to SLICE_10.A0 ADSubmitted CTOF_DEL --- 0.101 SLICE_10.A0 to SLICE_10.F0 SLICE_10 -ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r_0 (to PHI2_c) +ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r_0_0 (to PHI2_c) -------- 0.434 (53.9% logic, 46.1% route), 2 logic levels. @@ -303,7 +301,7 @@ Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ; ================================================================================ Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; - 868 items scored, 0 timing errors detected. + 891 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- @@ -357,7 +355,7 @@ Clock Domains Analysis Found 4 clocks: -Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12 +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11 No transfer within this clock domain is found Data transfers from: @@ -399,7 +397,7 @@ Timing summary (Hold): Timing errors: 0 Score: 0 Cumulative negative slack: 0 -Constraints cover 1015 paths, 4 nets, and 706 connections (71.10% coverage) +Constraints cover 1038 paths, 4 nets, and 732 connections (72.40% coverage) diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.twr b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.twr index 2912982..a02e2d1 100644 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.twr +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.twr @@ -13,7 +13,7 @@ Setup and Hold Report -------------------------------------------------------------------------------- Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 -Thu Oct 19 23:51:11 2023 +Sat Nov 18 02:06:13 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -42,127 +42,174 @@ Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ; -------------------------------------------------------------------------------- -Passed: The following path meets requirements by 162.455ns (weighted slack = 324.910ns) +Passed: The following path meets requirements by 162.097ns (weighted slack = 324.194ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_0io[0] (from PHI2_c +) - Destination: FF Data in CmdEnable (to PHI2_c -) + Source: FF Q Bank_0io[7] (from PHI2_c +) + Destination: FF Data in CmdUFMData (to PHI2_c -) - Delay: 9.620ns (31.7% logic, 68.3% route), 6 logic levels. + Delay: 9.837ns (26.0% logic, 74.0% route), 5 logic levels. Constraint Details: - 9.620ns physical path delay Din[0]_MGIOL to SLICE_17 meets + 9.837ns physical path delay Din[7]_MGIOL to SLICE_19 meets 172.414ns delay constraint less 0.173ns skew and - 0.166ns DIN_SET requirement (totaling 172.075ns) by 162.455ns + 0.307ns CE_SET requirement (totaling 171.934ns) by 162.097ns Physical Path Details: - Data path Din[0]_MGIOL to SLICE_17: + Data path Din[7]_MGIOL to SLICE_19: Name Fanout Delay (ns) Site Resource -C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c) -ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0] -CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_89 -ROUTE 1 1.001 R4C11A.F0 to R4C10A.B1 un1_ADWR_i_o2_10 -CTOF_DEL --- 0.495 R4C10A.B1 to R4C10A.F1 SLICE_75 -ROUTE 8 0.710 R4C10A.F1 to R4C10A.B0 N_294 -CTOF_DEL --- 0.495 R4C10A.B0 to R4C10A.F0 SLICE_75 -ROUTE 2 1.093 R4C10A.F0 to R5C11A.C0 N_382 -CTOF_DEL --- 0.495 R5C11A.C0 to R5C11A.F0 SLICE_73 -ROUTE 2 1.013 R5C11A.F0 to R5C11D.B0 CmdEnable17 -CTOF_DEL --- 0.495 R5C11D.B0 to R5C11D.F0 SLICE_17 -ROUTE 1 0.000 R5C11D.F0 to R5C11D.DI0 CmdEnable_s (to PHI2_c) +C2INP_DEL --- 0.577 IOL_L2C.CLK to IOL_L2C.IN Din[7]_MGIOL (from PHI2_c) +ROUTE 1 2.215 IOL_L2C.IN to R4C10D.A0 Bank[7] +CTOF_DEL --- 0.495 R4C10D.A0 to R4C10D.F0 SLICE_90 +ROUTE 1 0.958 R4C10D.F0 to R2C9D.D0 un1_CmdEnable20_0_0_o2_10 +CTOF_DEL --- 0.495 R2C9D.D0 to R2C9D.F0 SLICE_80 +ROUTE 6 1.104 R2C9D.F0 to R5C9A.D1 N_367 +CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_23 +ROUTE 8 1.295 R5C9A.F1 to R7C10B.C0 XOR8MEG18 +CTOF_DEL --- 0.495 R7C10B.C0 to R7C10B.F0 SLICE_77 +ROUTE 1 1.708 R7C10B.F0 to R7C11B.CE CmdUFMData_1_sqmuxa (to PHI2_c) -------- - 9.620 (31.7% logic, 68.3% route), 6 logic levels. + 9.837 (26.0% logic, 74.0% route), 5 logic levels. Clock Skew Details: - Source Clock Path PHI2 to Din[0]_MGIOL: + Source Clock Path PHI2 to Din[7]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c +ROUTE 21 4.369 8.PADDI to IOL_L2C.CLK PHI2_c -------- 4.369 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_17: + Destination Clock Path PHI2 to SLICE_19: Name Fanout Delay (ns) Site Resource -ROUTE 21 4.196 8.PADDI to R5C11D.CLK PHI2_c +ROUTE 21 4.196 8.PADDI to R7C11B.CLK PHI2_c -------- 4.196 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 162.715ns (weighted slack = 325.430ns) +Passed: The following path meets requirements by 162.937ns (weighted slack = 325.874ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_0io[0] (from PHI2_c +) - Destination: FF Data in ADSubmitted (to PHI2_c -) + Source: FF Q Bank_0io[1] (from PHI2_c +) + Destination: FF Data in CmdUFMData (to PHI2_c -) - Delay: 9.360ns (32.6% logic, 67.4% route), 6 logic levels. + Delay: 8.997ns (28.4% logic, 71.6% route), 5 logic levels. Constraint Details: - 9.360ns physical path delay Din[0]_MGIOL to SLICE_10 meets + 8.997ns physical path delay Din[1]_MGIOL to SLICE_19 meets 172.414ns delay constraint less 0.173ns skew and - 0.166ns DIN_SET requirement (totaling 172.075ns) by 162.715ns + 0.307ns CE_SET requirement (totaling 171.934ns) by 162.937ns Physical Path Details: - Data path Din[0]_MGIOL to SLICE_10: + Data path Din[1]_MGIOL to SLICE_19: Name Fanout Delay (ns) Site Resource -C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c) -ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0] -CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_89 -ROUTE 1 1.001 R4C11A.F0 to R4C10A.B1 un1_ADWR_i_o2_10 -CTOF_DEL --- 0.495 R4C10A.B1 to R4C10A.F1 SLICE_75 -ROUTE 8 0.710 R4C10A.F1 to R4C10A.B0 N_294 -CTOF_DEL --- 0.495 R4C10A.B0 to R4C10A.F0 SLICE_75 -ROUTE 2 1.093 R4C10A.F0 to R5C11A.C0 N_382 -CTOF_DEL --- 0.495 R5C11A.C0 to R5C11A.F0 SLICE_73 -ROUTE 2 0.753 R5C11A.F0 to R5C12C.C0 CmdEnable17 -CTOF_DEL --- 0.495 R5C12C.C0 to R5C12C.F0 SLICE_10 -ROUTE 1 0.000 R5C12C.F0 to R5C12C.DI0 ADSubmitted_r_0 (to PHI2_c) +C2INP_DEL --- 0.577 IOL_T10B.CLK to IOL_T10B.IN Din[1]_MGIOL (from PHI2_c) +ROUTE 1 1.375 IOL_T10B.IN to R4C10D.D0 Bank[1] +CTOF_DEL --- 0.495 R4C10D.D0 to R4C10D.F0 SLICE_90 +ROUTE 1 0.958 R4C10D.F0 to R2C9D.D0 un1_CmdEnable20_0_0_o2_10 +CTOF_DEL --- 0.495 R2C9D.D0 to R2C9D.F0 SLICE_80 +ROUTE 6 1.104 R2C9D.F0 to R5C9A.D1 N_367 +CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_23 +ROUTE 8 1.295 R5C9A.F1 to R7C10B.C0 XOR8MEG18 +CTOF_DEL --- 0.495 R7C10B.C0 to R7C10B.F0 SLICE_77 +ROUTE 1 1.708 R7C10B.F0 to R7C11B.CE CmdUFMData_1_sqmuxa (to PHI2_c) -------- - 9.360 (32.6% logic, 67.4% route), 6 logic levels. + 8.997 (28.4% logic, 71.6% route), 5 logic levels. Clock Skew Details: - Source Clock Path PHI2 to Din[0]_MGIOL: + Source Clock Path PHI2 to Din[1]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c +ROUTE 21 4.369 8.PADDI to IOL_T10B.CLK PHI2_c -------- 4.369 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_10: + Destination Clock Path PHI2 to SLICE_19: Name Fanout Delay (ns) Site Resource -ROUTE 21 4.196 8.PADDI to R5C12C.CLK PHI2_c +ROUTE 21 4.196 8.PADDI to R7C11B.CLK PHI2_c -------- 4.196 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 162.913ns (weighted slack = 325.826ns) +Passed: The following path meets requirements by 163.032ns (weighted slack = 326.064ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_0io[6] (from PHI2_c +) + Destination: FF Data in CmdUFMData (to PHI2_c -) + + Delay: 8.902ns (28.7% logic, 71.3% route), 5 logic levels. + + Constraint Details: + + 8.902ns physical path delay Din[6]_MGIOL to SLICE_19 meets + 172.414ns delay constraint less + 0.173ns skew and + 0.307ns CE_SET requirement (totaling 171.934ns) by 163.032ns + + Physical Path Details: + + Data path Din[6]_MGIOL to SLICE_19: + + Name Fanout Delay (ns) Site Resource +C2INP_DEL --- 0.577 IOL_L2D.CLK to IOL_L2D.IN Din[6]_MGIOL (from PHI2_c) +ROUTE 1 1.802 IOL_L2D.IN to R2C9D.D1 Bank[6] +CTOF_DEL --- 0.495 R2C9D.D1 to R2C9D.F1 SLICE_80 +ROUTE 1 0.436 R2C9D.F1 to R2C9D.C0 un1_CmdEnable20_0_0_o2_11 +CTOF_DEL --- 0.495 R2C9D.C0 to R2C9D.F0 SLICE_80 +ROUTE 6 1.104 R2C9D.F0 to R5C9A.D1 N_367 +CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_23 +ROUTE 8 1.295 R5C9A.F1 to R7C10B.C0 XOR8MEG18 +CTOF_DEL --- 0.495 R7C10B.C0 to R7C10B.F0 SLICE_77 +ROUTE 1 1.708 R7C10B.F0 to R7C11B.CE CmdUFMData_1_sqmuxa (to PHI2_c) + -------- + 8.902 (28.7% logic, 71.3% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to Din[6]_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 4.369 8.PADDI to IOL_L2D.CLK PHI2_c + -------- + 4.369 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 4.196 8.PADDI to R7C11B.CLK PHI2_c + -------- + 4.196 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 163.085ns (weighted slack = 326.170ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Bank_0io[7] (from PHI2_c +) Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 9.162ns (33.3% logic, 66.7% route), 6 logic levels. + Delay: 8.990ns (33.9% logic, 66.1% route), 6 logic levels. Constraint Details: - 9.162ns physical path delay Din[7]_MGIOL to SLICE_17 meets + 8.990ns physical path delay Din[7]_MGIOL to SLICE_17 meets 172.414ns delay constraint less 0.173ns skew and - 0.166ns DIN_SET requirement (totaling 172.075ns) by 162.913ns + 0.166ns DIN_SET requirement (totaling 172.075ns) by 163.085ns Physical Path Details: @@ -170,19 +217,19 @@ Passed: The following path meets requirements by 162.913ns (weighted slack = 325 Name Fanout Delay (ns) Site Resource C2INP_DEL --- 0.577 IOL_L2C.CLK to IOL_L2C.IN Din[7]_MGIOL (from PHI2_c) -ROUTE 1 2.215 IOL_L2C.IN to R3C9D.A0 Bank[7] -CTOF_DEL --- 0.495 R3C9D.A0 to R3C9D.F0 SLICE_32 -ROUTE 1 1.079 R3C9D.F0 to R4C10A.C1 un1_ADWR_i_o2_11 -CTOF_DEL --- 0.495 R4C10A.C1 to R4C10A.F1 SLICE_75 -ROUTE 8 0.710 R4C10A.F1 to R4C10A.B0 N_294 -CTOF_DEL --- 0.495 R4C10A.B0 to R4C10A.F0 SLICE_75 -ROUTE 2 1.093 R4C10A.F0 to R5C11A.C0 N_382 -CTOF_DEL --- 0.495 R5C11A.C0 to R5C11A.F0 SLICE_73 -ROUTE 2 1.013 R5C11A.F0 to R5C11D.B0 CmdEnable17 -CTOF_DEL --- 0.495 R5C11D.B0 to R5C11D.F0 SLICE_17 -ROUTE 1 0.000 R5C11D.F0 to R5C11D.DI0 CmdEnable_s (to PHI2_c) +ROUTE 1 2.215 IOL_L2C.IN to R4C10D.A0 Bank[7] +CTOF_DEL --- 0.495 R4C10D.A0 to R4C10D.F0 SLICE_90 +ROUTE 1 0.958 R4C10D.F0 to R2C9D.D0 un1_CmdEnable20_0_0_o2_10 +CTOF_DEL --- 0.495 R2C9D.D0 to R2C9D.F0 SLICE_80 +ROUTE 6 1.048 R2C9D.F0 to R4C9A.B1 N_367 +CTOF_DEL --- 0.495 R4C9A.B1 to R4C9A.F1 SLICE_11 +ROUTE 3 0.753 R4C9A.F1 to R4C8A.C0 CmdEnable16 +CTOF_DEL --- 0.495 R4C8A.C0 to R4C8A.F0 SLICE_33 +ROUTE 1 0.964 R4C8A.F0 to R4C9B.A0 CmdEnable_0_sqmuxa +CTOF_DEL --- 0.495 R4C9B.A0 to R4C9B.F0 SLICE_17 +ROUTE 1 0.000 R4C9B.F0 to R4C9B.DI0 CmdEnable_s (to PHI2_c) -------- - 9.162 (33.3% logic, 66.7% route), 6 logic levels. + 8.990 (33.9% logic, 66.1% route), 6 logic levels. Clock Skew Details: @@ -196,95 +243,195 @@ ROUTE 21 4.369 8.PADDI to IOL_L2C.CLK PHI2_c Destination Clock Path PHI2 to SLICE_17: Name Fanout Delay (ns) Site Resource -ROUTE 21 4.196 8.PADDI to R5C11D.CLK PHI2_c +ROUTE 21 4.196 8.PADDI to R4C9B.CLK PHI2_c -------- 4.196 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 163.173ns (weighted slack = 326.346ns) +Passed: The following path meets requirements by 163.118ns (weighted slack = 326.236ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_0io[7] (from PHI2_c +) - Destination: FF Data in ADSubmitted (to PHI2_c -) + Source: FF Q Bank_0io[2] (from PHI2_c +) + Destination: FF Data in CmdUFMData (to PHI2_c -) - Delay: 8.902ns (34.3% logic, 65.7% route), 6 logic levels. + Delay: 8.816ns (29.0% logic, 71.0% route), 5 logic levels. Constraint Details: - 8.902ns physical path delay Din[7]_MGIOL to SLICE_10 meets + 8.816ns physical path delay Din[2]_MGIOL to SLICE_19 meets 172.414ns delay constraint less 0.173ns skew and - 0.166ns DIN_SET requirement (totaling 172.075ns) by 163.173ns + 0.307ns CE_SET requirement (totaling 171.934ns) by 163.118ns Physical Path Details: - Data path Din[7]_MGIOL to SLICE_10: + Data path Din[2]_MGIOL to SLICE_19: Name Fanout Delay (ns) Site Resource -C2INP_DEL --- 0.577 IOL_L2C.CLK to IOL_L2C.IN Din[7]_MGIOL (from PHI2_c) -ROUTE 1 2.215 IOL_L2C.IN to R3C9D.A0 Bank[7] -CTOF_DEL --- 0.495 R3C9D.A0 to R3C9D.F0 SLICE_32 -ROUTE 1 1.079 R3C9D.F0 to R4C10A.C1 un1_ADWR_i_o2_11 -CTOF_DEL --- 0.495 R4C10A.C1 to R4C10A.F1 SLICE_75 -ROUTE 8 0.710 R4C10A.F1 to R4C10A.B0 N_294 -CTOF_DEL --- 0.495 R4C10A.B0 to R4C10A.F0 SLICE_75 -ROUTE 2 1.093 R4C10A.F0 to R5C11A.C0 N_382 -CTOF_DEL --- 0.495 R5C11A.C0 to R5C11A.F0 SLICE_73 -ROUTE 2 0.753 R5C11A.F0 to R5C12C.C0 CmdEnable17 -CTOF_DEL --- 0.495 R5C12C.C0 to R5C12C.F0 SLICE_10 -ROUTE 1 0.000 R5C12C.F0 to R5C12C.DI0 ADSubmitted_r_0 (to PHI2_c) +C2INP_DEL --- 0.577 IOL_T12A.CLK to IOL_T12A.IN Din[2]_MGIOL (from PHI2_c) +ROUTE 1 1.716 IOL_T12A.IN to R2C9D.A1 Bank[2] +CTOF_DEL --- 0.495 R2C9D.A1 to R2C9D.F1 SLICE_80 +ROUTE 1 0.436 R2C9D.F1 to R2C9D.C0 un1_CmdEnable20_0_0_o2_11 +CTOF_DEL --- 0.495 R2C9D.C0 to R2C9D.F0 SLICE_80 +ROUTE 6 1.104 R2C9D.F0 to R5C9A.D1 N_367 +CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_23 +ROUTE 8 1.295 R5C9A.F1 to R7C10B.C0 XOR8MEG18 +CTOF_DEL --- 0.495 R7C10B.C0 to R7C10B.F0 SLICE_77 +ROUTE 1 1.708 R7C10B.F0 to R7C11B.CE CmdUFMData_1_sqmuxa (to PHI2_c) -------- - 8.902 (34.3% logic, 65.7% route), 6 logic levels. + 8.816 (29.0% logic, 71.0% route), 5 logic levels. Clock Skew Details: - Source Clock Path PHI2 to Din[7]_MGIOL: + Source Clock Path PHI2 to Din[2]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 21 4.369 8.PADDI to IOL_L2C.CLK PHI2_c +ROUTE 21 4.369 8.PADDI to IOL_T12A.CLK PHI2_c -------- 4.369 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_10: + Destination Clock Path PHI2 to SLICE_19: Name Fanout Delay (ns) Site Resource -ROUTE 21 4.196 8.PADDI to R5C12C.CLK PHI2_c +ROUTE 21 4.196 8.PADDI to R7C11B.CLK PHI2_c -------- 4.196 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 163.263ns (weighted slack = 326.526ns) +Passed: The following path meets requirements by 163.196ns (weighted slack = 326.392ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_0io[5] (from PHI2_c +) + Destination: FF Data in CmdUFMData (to PHI2_c -) + + Delay: 8.738ns (29.3% logic, 70.7% route), 5 logic levels. + + Constraint Details: + + 8.738ns physical path delay Din[5]_MGIOL to SLICE_19 meets + 172.414ns delay constraint less + 0.173ns skew and + 0.307ns CE_SET requirement (totaling 171.934ns) by 163.196ns + + Physical Path Details: + + Data path Din[5]_MGIOL to SLICE_19: + + Name Fanout Delay (ns) Site Resource +C2INP_DEL --- 0.577 IOL_T9B.CLK to IOL_T9B.IN Din[5]_MGIOL (from PHI2_c) +ROUTE 1 1.638 IOL_T9B.IN to R2C9D.B1 Bank[5] +CTOF_DEL --- 0.495 R2C9D.B1 to R2C9D.F1 SLICE_80 +ROUTE 1 0.436 R2C9D.F1 to R2C9D.C0 un1_CmdEnable20_0_0_o2_11 +CTOF_DEL --- 0.495 R2C9D.C0 to R2C9D.F0 SLICE_80 +ROUTE 6 1.104 R2C9D.F0 to R5C9A.D1 N_367 +CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_23 +ROUTE 8 1.295 R5C9A.F1 to R7C10B.C0 XOR8MEG18 +CTOF_DEL --- 0.495 R7C10B.C0 to R7C10B.F0 SLICE_77 +ROUTE 1 1.708 R7C10B.F0 to R7C11B.CE CmdUFMData_1_sqmuxa (to PHI2_c) + -------- + 8.738 (29.3% logic, 70.7% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to Din[5]_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 4.369 8.PADDI to IOL_T9B.CLK PHI2_c + -------- + 4.369 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 4.196 8.PADDI to R7C11B.CLK PHI2_c + -------- + 4.196 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 163.537ns (weighted slack = 327.074ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_0io[3] (from PHI2_c +) + Destination: FF Data in CmdUFMData (to PHI2_c -) + + Delay: 8.397ns (30.5% logic, 69.5% route), 5 logic levels. + + Constraint Details: + + 8.397ns physical path delay Din[3]_MGIOL to SLICE_19 meets + 172.414ns delay constraint less + 0.173ns skew and + 0.307ns CE_SET requirement (totaling 171.934ns) by 163.537ns + + Physical Path Details: + + Data path Din[3]_MGIOL to SLICE_19: + + Name Fanout Delay (ns) Site Resource +C2INP_DEL --- 0.577 IOL_T10A.CLK to IOL_T10A.IN Din[3]_MGIOL (from PHI2_c) +ROUTE 1 1.297 IOL_T10A.IN to R2C9D.C1 Bank[3] +CTOF_DEL --- 0.495 R2C9D.C1 to R2C9D.F1 SLICE_80 +ROUTE 1 0.436 R2C9D.F1 to R2C9D.C0 un1_CmdEnable20_0_0_o2_11 +CTOF_DEL --- 0.495 R2C9D.C0 to R2C9D.F0 SLICE_80 +ROUTE 6 1.104 R2C9D.F0 to R5C9A.D1 N_367 +CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_23 +ROUTE 8 1.295 R5C9A.F1 to R7C10B.C0 XOR8MEG18 +CTOF_DEL --- 0.495 R7C10B.C0 to R7C10B.F0 SLICE_77 +ROUTE 1 1.708 R7C10B.F0 to R7C11B.CE CmdUFMData_1_sqmuxa (to PHI2_c) + -------- + 8.397 (30.5% logic, 69.5% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to Din[3]_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 4.369 8.PADDI to IOL_T10A.CLK PHI2_c + -------- + 4.369 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 4.196 8.PADDI to R7C11B.CLK PHI2_c + -------- + 4.196 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 163.622ns (weighted slack = 327.244ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Bank_0io[0] (from PHI2_c +) - Destination: FF Data in CmdLEDEN (to PHI2_c -) + Destination: FF Data in CmdUFMData (to PHI2_c -) - Delay: 8.671ns (23.8% logic, 76.2% route), 4 logic levels. + Delay: 8.312ns (24.8% logic, 75.2% route), 4 logic levels. Constraint Details: - 8.671ns physical path delay Din[0]_MGIOL to SLICE_18 meets + 8.312ns physical path delay Din[0]_MGIOL to SLICE_19 meets 172.414ns delay constraint less 0.173ns skew and - 0.307ns CE_SET requirement (totaling 171.934ns) by 163.263ns + 0.307ns CE_SET requirement (totaling 171.934ns) by 163.622ns Physical Path Details: - Data path Din[0]_MGIOL to SLICE_18: + Data path Din[0]_MGIOL to SLICE_19: Name Fanout Delay (ns) Site Resource C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c) -ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0] -CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_89 -ROUTE 1 1.001 R4C11A.F0 to R4C10A.B1 un1_ADWR_i_o2_10 -CTOF_DEL --- 0.495 R4C10A.B1 to R4C10A.F1 SLICE_75 -ROUTE 8 1.444 R4C10A.F1 to R5C11C.A1 N_294 -CTOF_DEL --- 0.495 R5C11C.A1 to R5C11C.F1 SLICE_106 -ROUTE 5 1.413 R5C11C.F1 to R3C10B.CE XOR8MEG18 (to PHI2_c) +ROUTE 1 2.143 IOL_L3A.IN to R2C9D.A0 Bank[0] +CTOF_DEL --- 0.495 R2C9D.A0 to R2C9D.F0 SLICE_80 +ROUTE 6 1.104 R2C9D.F0 to R5C9A.D1 N_367 +CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_23 +ROUTE 8 1.295 R5C9A.F1 to R7C10B.C0 XOR8MEG18 +CTOF_DEL --- 0.495 R7C10B.C0 to R7C10B.F0 SLICE_77 +ROUTE 1 1.708 R7C10B.F0 to R7C11B.CE CmdUFMData_1_sqmuxa (to PHI2_c) -------- - 8.671 (23.8% logic, 76.2% route), 4 logic levels. + 8.312 (24.8% logic, 75.2% route), 4 logic levels. Clock Skew Details: @@ -295,176 +442,82 @@ ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c -------- 4.369 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_18: + Destination Clock Path PHI2 to SLICE_19: Name Fanout Delay (ns) Site Resource -ROUTE 21 4.196 8.PADDI to R3C10B.CLK PHI2_c +ROUTE 21 4.196 8.PADDI to R7C11B.CLK PHI2_c -------- 4.196 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 163.263ns (weighted slack = 326.526ns) +Passed: The following path meets requirements by 163.925ns (weighted slack = 327.850ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_0io[0] (from PHI2_c +) - Destination: FF Data in CmdUFMShift (to PHI2_c -) + Source: FF Q Bank_0io[1] (from PHI2_c +) + Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 8.671ns (23.8% logic, 76.2% route), 4 logic levels. + Delay: 8.150ns (37.4% logic, 62.6% route), 6 logic levels. Constraint Details: - 8.671ns physical path delay Din[0]_MGIOL to SLICE_20 meets + 8.150ns physical path delay Din[1]_MGIOL to SLICE_17 meets 172.414ns delay constraint less 0.173ns skew and - 0.307ns CE_SET requirement (totaling 171.934ns) by 163.263ns + 0.166ns DIN_SET requirement (totaling 172.075ns) by 163.925ns Physical Path Details: - Data path Din[0]_MGIOL to SLICE_20: + Data path Din[1]_MGIOL to SLICE_17: Name Fanout Delay (ns) Site Resource -C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c) -ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0] -CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_89 -ROUTE 1 1.001 R4C11A.F0 to R4C10A.B1 un1_ADWR_i_o2_10 -CTOF_DEL --- 0.495 R4C10A.B1 to R4C10A.F1 SLICE_75 -ROUTE 8 1.444 R4C10A.F1 to R5C11C.A1 N_294 -CTOF_DEL --- 0.495 R5C11C.A1 to R5C11C.F1 SLICE_106 -ROUTE 5 1.413 R5C11C.F1 to R4C10B.CE XOR8MEG18 (to PHI2_c) +C2INP_DEL --- 0.577 IOL_T10B.CLK to IOL_T10B.IN Din[1]_MGIOL (from PHI2_c) +ROUTE 1 1.375 IOL_T10B.IN to R4C10D.D0 Bank[1] +CTOF_DEL --- 0.495 R4C10D.D0 to R4C10D.F0 SLICE_90 +ROUTE 1 0.958 R4C10D.F0 to R2C9D.D0 un1_CmdEnable20_0_0_o2_10 +CTOF_DEL --- 0.495 R2C9D.D0 to R2C9D.F0 SLICE_80 +ROUTE 6 1.048 R2C9D.F0 to R4C9A.B1 N_367 +CTOF_DEL --- 0.495 R4C9A.B1 to R4C9A.F1 SLICE_11 +ROUTE 3 0.753 R4C9A.F1 to R4C8A.C0 CmdEnable16 +CTOF_DEL --- 0.495 R4C8A.C0 to R4C8A.F0 SLICE_33 +ROUTE 1 0.964 R4C8A.F0 to R4C9B.A0 CmdEnable_0_sqmuxa +CTOF_DEL --- 0.495 R4C9B.A0 to R4C9B.F0 SLICE_17 +ROUTE 1 0.000 R4C9B.F0 to R4C9B.DI0 CmdEnable_s (to PHI2_c) -------- - 8.671 (23.8% logic, 76.2% route), 4 logic levels. + 8.150 (37.4% logic, 62.6% route), 6 logic levels. Clock Skew Details: - Source Clock Path PHI2 to Din[0]_MGIOL: + Source Clock Path PHI2 to Din[1]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c +ROUTE 21 4.369 8.PADDI to IOL_T10B.CLK PHI2_c -------- 4.369 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_20: + Destination Clock Path PHI2 to SLICE_17: Name Fanout Delay (ns) Site Resource -ROUTE 21 4.196 8.PADDI to R4C10B.CLK PHI2_c +ROUTE 21 4.196 8.PADDI to R4C9B.CLK PHI2_c -------- 4.196 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 163.263ns (weighted slack = 326.526ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_0io[0] (from PHI2_c +) - Destination: FF Data in CmdUFMWrite (to PHI2_c -) - - Delay: 8.671ns (23.8% logic, 76.2% route), 4 logic levels. - - Constraint Details: - - 8.671ns physical path delay Din[0]_MGIOL to SLICE_21 meets - 172.414ns delay constraint less - 0.173ns skew and - 0.307ns CE_SET requirement (totaling 171.934ns) by 163.263ns - - Physical Path Details: - - Data path Din[0]_MGIOL to SLICE_21: - - Name Fanout Delay (ns) Site Resource -C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c) -ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0] -CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_89 -ROUTE 1 1.001 R4C11A.F0 to R4C10A.B1 un1_ADWR_i_o2_10 -CTOF_DEL --- 0.495 R4C10A.B1 to R4C10A.F1 SLICE_75 -ROUTE 8 1.444 R4C10A.F1 to R5C11C.A1 N_294 -CTOF_DEL --- 0.495 R5C11C.A1 to R5C11C.F1 SLICE_106 -ROUTE 5 1.413 R5C11C.F1 to R4C10D.CE XOR8MEG18 (to PHI2_c) - -------- - 8.671 (23.8% logic, 76.2% route), 4 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to Din[0]_MGIOL: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c - -------- - 4.369 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_21: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 4.196 8.PADDI to R4C10D.CLK PHI2_c - -------- - 4.196 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 163.263ns (weighted slack = 326.526ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_0io[0] (from PHI2_c +) - Destination: FF Data in Cmdn8MEGEN (to PHI2_c -) - - Delay: 8.671ns (23.8% logic, 76.2% route), 4 logic levels. - - Constraint Details: - - 8.671ns physical path delay Din[0]_MGIOL to SLICE_24 meets - 172.414ns delay constraint less - 0.173ns skew and - 0.307ns CE_SET requirement (totaling 171.934ns) by 163.263ns - - Physical Path Details: - - Data path Din[0]_MGIOL to SLICE_24: - - Name Fanout Delay (ns) Site Resource -C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c) -ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0] -CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_89 -ROUTE 1 1.001 R4C11A.F0 to R4C10A.B1 un1_ADWR_i_o2_10 -CTOF_DEL --- 0.495 R4C10A.B1 to R4C10A.F1 SLICE_75 -ROUTE 8 1.444 R4C10A.F1 to R5C11C.A1 N_294 -CTOF_DEL --- 0.495 R5C11C.A1 to R5C11C.F1 SLICE_106 -ROUTE 5 1.413 R5C11C.F1 to R3C10C.CE XOR8MEG18 (to PHI2_c) - -------- - 8.671 (23.8% logic, 76.2% route), 4 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to Din[0]_MGIOL: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c - -------- - 4.369 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_24: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 4.196 8.PADDI to R3C10C.CLK PHI2_c - -------- - 4.196 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 163.326ns (weighted slack = 326.652ns) +Passed: The following path meets requirements by 164.020ns (weighted slack = 328.040ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Bank_0io[6] (from PHI2_c +) Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 8.749ns (34.9% logic, 65.1% route), 6 logic levels. + Delay: 8.055ns (37.9% logic, 62.1% route), 6 logic levels. Constraint Details: - 8.749ns physical path delay Din[6]_MGIOL to SLICE_17 meets + 8.055ns physical path delay Din[6]_MGIOL to SLICE_17 meets 172.414ns delay constraint less 0.173ns skew and - 0.166ns DIN_SET requirement (totaling 172.075ns) by 163.326ns + 0.166ns DIN_SET requirement (totaling 172.075ns) by 164.020ns Physical Path Details: @@ -472,19 +525,19 @@ Passed: The following path meets requirements by 163.326ns (weighted slack = 326 Name Fanout Delay (ns) Site Resource C2INP_DEL --- 0.577 IOL_L2D.CLK to IOL_L2D.IN Din[6]_MGIOL (from PHI2_c) -ROUTE 1 1.802 IOL_L2D.IN to R3C9D.D0 Bank[6] -CTOF_DEL --- 0.495 R3C9D.D0 to R3C9D.F0 SLICE_32 -ROUTE 1 1.079 R3C9D.F0 to R4C10A.C1 un1_ADWR_i_o2_11 -CTOF_DEL --- 0.495 R4C10A.C1 to R4C10A.F1 SLICE_75 -ROUTE 8 0.710 R4C10A.F1 to R4C10A.B0 N_294 -CTOF_DEL --- 0.495 R4C10A.B0 to R4C10A.F0 SLICE_75 -ROUTE 2 1.093 R4C10A.F0 to R5C11A.C0 N_382 -CTOF_DEL --- 0.495 R5C11A.C0 to R5C11A.F0 SLICE_73 -ROUTE 2 1.013 R5C11A.F0 to R5C11D.B0 CmdEnable17 -CTOF_DEL --- 0.495 R5C11D.B0 to R5C11D.F0 SLICE_17 -ROUTE 1 0.000 R5C11D.F0 to R5C11D.DI0 CmdEnable_s (to PHI2_c) +ROUTE 1 1.802 IOL_L2D.IN to R2C9D.D1 Bank[6] +CTOF_DEL --- 0.495 R2C9D.D1 to R2C9D.F1 SLICE_80 +ROUTE 1 0.436 R2C9D.F1 to R2C9D.C0 un1_CmdEnable20_0_0_o2_11 +CTOF_DEL --- 0.495 R2C9D.C0 to R2C9D.F0 SLICE_80 +ROUTE 6 1.048 R2C9D.F0 to R4C9A.B1 N_367 +CTOF_DEL --- 0.495 R4C9A.B1 to R4C9A.F1 SLICE_11 +ROUTE 3 0.753 R4C9A.F1 to R4C8A.C0 CmdEnable16 +CTOF_DEL --- 0.495 R4C8A.C0 to R4C8A.F0 SLICE_33 +ROUTE 1 0.964 R4C8A.F0 to R4C9B.A0 CmdEnable_0_sqmuxa +CTOF_DEL --- 0.495 R4C9B.A0 to R4C9B.F0 SLICE_17 +ROUTE 1 0.000 R4C9B.F0 to R4C9B.DI0 CmdEnable_s (to PHI2_c) -------- - 8.749 (34.9% logic, 65.1% route), 6 logic levels. + 8.055 (37.9% logic, 62.1% route), 6 logic levels. Clock Skew Details: @@ -498,62 +551,11 @@ ROUTE 21 4.369 8.PADDI to IOL_L2D.CLK PHI2_c Destination Clock Path PHI2 to SLICE_17: Name Fanout Delay (ns) Site Resource -ROUTE 21 4.196 8.PADDI to R5C11D.CLK PHI2_c +ROUTE 21 4.196 8.PADDI to R4C9B.CLK PHI2_c -------- 4.196 (0.0% logic, 100.0% route), 0 logic levels. - -Passed: The following path meets requirements by 163.343ns (weighted slack = 326.686ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_0io[0] (from PHI2_c +) - Destination: FF Data in ADSubmitted (to PHI2_c -) - - Delay: 8.732ns (29.3% logic, 70.7% route), 5 logic levels. - - Constraint Details: - - 8.732ns physical path delay Din[0]_MGIOL to SLICE_10 meets - 172.414ns delay constraint less - 0.173ns skew and - 0.166ns DIN_SET requirement (totaling 172.075ns) by 163.343ns - - Physical Path Details: - - Data path Din[0]_MGIOL to SLICE_10: - - Name Fanout Delay (ns) Site Resource -C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c) -ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0] -CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_89 -ROUTE 1 1.001 R4C11A.F0 to R4C10A.B1 un1_ADWR_i_o2_10 -CTOF_DEL --- 0.495 R4C10A.B1 to R4C10A.F1 SLICE_75 -ROUTE 8 1.456 R4C10A.F1 to R5C12C.A1 N_294 -CTOF_DEL --- 0.495 R5C12C.A1 to R5C12C.F1 SLICE_10 -ROUTE 1 0.967 R5C12C.F1 to R5C12C.A0 N_22_i -CTOF_DEL --- 0.495 R5C12C.A0 to R5C12C.F0 SLICE_10 -ROUTE 1 0.000 R5C12C.F0 to R5C12C.DI0 ADSubmitted_r_0 (to PHI2_c) - -------- - 8.732 (29.3% logic, 70.7% route), 5 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to Din[0]_MGIOL: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c - -------- - 4.369 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_10: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 4.196 8.PADDI to R5C12C.CLK PHI2_c - -------- - 4.196 (0.0% logic, 100.0% route), 0 logic levels. - -Report: 50.206MHz is the maximum frequency for this preference. +Report: 48.464MHz is the maximum frequency for this preference. ================================================================================ @@ -594,90 +596,92 @@ Report: 150.150MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; - 868 items scored, 0 timing errors detected. + 891 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- -Passed: The following path meets requirements by 5.798ns +Passed: The following path meets requirements by 6.215ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS[12] (from RCLK_c +) - Destination: FF Data in wb_adr[1] (to RCLK_c +) + Source: FF Q RASr2 (from RCLK_c +) + Destination: FF Data in nRWE_0io (to RCLK_c +) - Delay: 10.036ns (24.2% logic, 75.8% route), 5 logic levels. + Delay: 9.805ns (29.9% logic, 70.1% route), 6 logic levels. Constraint Details: - 10.036ns physical path delay SLICE_4 to SLICE_48 meets + 9.805ns physical path delay SLICE_32 to nRWE_MGIOL meets 16.000ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 15.834ns) by 5.798ns + -0.173ns skew and + 0.153ns DO_SET requirement (totaling 16.020ns) by 6.215ns Physical Path Details: - Data path SLICE_4 to SLICE_48: + Data path SLICE_32 to nRWE_MGIOL: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C5C.CLK to R5C5C.Q1 SLICE_4 (from RCLK_c) -ROUTE 23 2.663 R5C5C.Q1 to R2C7A.A1 FS[12] -CTOF_DEL --- 0.495 R2C7A.A1 to R2C7A.F1 SLICE_101 -ROUTE 4 2.173 R2C7A.F1 to R4C7C.B1 N_142 -CTOF_DEL --- 0.495 R4C7C.B1 to R4C7C.F1 SLICE_65 -ROUTE 1 0.967 R4C7C.F1 to R4C7A.A0 N_428_tz -CTOF_DEL --- 0.495 R4C7A.A0 to R4C7A.F0 SLICE_61 -ROUTE 1 1.801 R4C7A.F0 to R4C6C.A1 wb_adr_5_i_i_0[1] -CTOF_DEL --- 0.495 R4C6C.A1 to R4C6C.F1 SLICE_48 -ROUTE 1 0.000 R4C6C.F1 to R4C6C.DI1 N_282 (to RCLK_c) +REG_DEL --- 0.452 R4C12C.CLK to R4C12C.Q1 SLICE_32 (from RCLK_c) +ROUTE 10 1.963 R4C12C.Q1 to R8C11B.A1 RASr2 +CTOF_DEL --- 0.495 R8C11B.A1 to R8C11B.F1 SLICE_62 +ROUTE 6 1.078 R8C11B.F1 to R7C12C.D1 IS_0_sqmuxa_0_o2 +CTOF_DEL --- 0.495 R7C12C.D1 to R7C12C.F1 SLICE_79 +ROUTE 2 0.635 R7C12C.F1 to R7C12A.D1 IS_0_sqmuxa_0_o3 +CTOF_DEL --- 0.495 R7C12A.D1 to R7C12A.F1 SLICE_28 +ROUTE 1 0.744 R7C12A.F1 to R8C12B.C1 nRWE_s_i_a2_1_0 +CTOF_DEL --- 0.495 R8C12B.C1 to R8C12B.F1 SLICE_68 +ROUTE 1 0.744 R8C12B.F1 to R9C12D.C0 nRWE_s_i_tz_0 +CTOF_DEL --- 0.495 R9C12D.C0 to R9C12D.F0 SLICE_75 +ROUTE 1 1.714 R9C12D.F0 to IOL_B20D.OPOS N_252_i (to RCLK_c) -------- - 10.036 (24.2% logic, 75.8% route), 5 logic levels. + 9.805 (29.9% logic, 70.1% route), 6 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_4: + Source Clock Path RCLK to SLICE_32: Name Fanout Delay (ns) Site Resource -ROUTE 48 2.264 63.PADDI to R5C5C.CLK RCLK_c +ROUTE 48 2.264 63.PADDI to R4C12C.CLK RCLK_c -------- 2.264 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_48: + Destination Clock Path RCLK to nRWE_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 48 2.264 63.PADDI to R4C6C.CLK RCLK_c +ROUTE 48 2.437 63.PADDI to IOL_B20D.CLK RCLK_c -------- - 2.264 (0.0% logic, 100.0% route), 0 logic levels. + 2.437 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 6.138ns +Passed: The following path meets requirements by 6.236ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: EFB Port ufmefb/EFBInst_0(ASIC) (from RCLK_c +) Destination: FF Data in n8MEGEN (to RCLK_c +) - Delay: 9.523ns (76.3% logic, 23.7% route), 3 logic levels. + Delay: 9.425ns (77.1% logic, 22.9% route), 3 logic levels. Constraint Details: - 9.523ns physical path delay ufmefb/EFBInst_0 to SLICE_46 meets + 9.425ns physical path delay ufmefb/EFBInst_0 to SLICE_45 meets 16.000ns delay constraint less 0.173ns skew and - 0.166ns DIN_SET requirement (totaling 15.661ns) by 6.138ns + 0.166ns DIN_SET requirement (totaling 15.661ns) by 6.236ns Physical Path Details: - Data path ufmefb/EFBInst_0 to SLICE_46: + Data path ufmefb/EFBInst_0 to SLICE_45: Name Fanout Delay (ns) Site Resource WCLKI2WBDA --- 6.278 EFB.WBCLKI to EFB.WBDATO0 ufmefb/EFBInst_0 (from RCLK_c) -ROUTE 1 1.297 EFB.WBDATO0 to R3C5B.C1 wb_dato[0] -CTOF_DEL --- 0.495 R3C5B.C1 to R3C5B.F1 SLICE_108 -ROUTE 1 0.958 R3C5B.F1 to R3C8B.D0 n8MEGENe_1_0 -CTOF_DEL --- 0.495 R3C8B.D0 to R3C8B.F0 SLICE_46 -ROUTE 1 0.000 R3C8B.F0 to R3C8B.DI0 n8MEGENe_0 (to RCLK_c) +ROUTE 1 1.512 EFB.WBDATO0 to R4C5C.C1 wb_dato[0] +CTOF_DEL --- 0.495 R4C5C.C1 to R4C5C.F1 SLICE_111 +ROUTE 1 0.645 R4C5C.F1 to R5C5B.D0 n8MEGENe_1_0 +CTOF_DEL --- 0.495 R5C5B.D0 to R5C5B.F0 SLICE_45 +ROUTE 1 0.000 R5C5B.F0 to R5C5B.DI0 n8MEGENe_0 (to RCLK_c) -------- - 9.523 (76.3% logic, 23.7% route), 3 logic levels. + 9.425 (77.1% logic, 22.9% route), 3 logic levels. Clock Skew Details: @@ -688,420 +692,100 @@ ROUTE 48 2.437 63.PADDI to EFB.WBCLKI RCLK_c -------- 2.437 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_46: - - Name Fanout Delay (ns) Site Resource -ROUTE 48 2.264 63.PADDI to R3C8B.CLK RCLK_c - -------- - 2.264 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 6.414ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[12] (from RCLK_c +) - Destination: FF Data in wb_adr[0] (to RCLK_c +) - - Delay: 9.420ns (36.3% logic, 63.7% route), 7 logic levels. - - Constraint Details: - - 9.420ns physical path delay SLICE_4 to SLICE_48 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 15.834ns) by 6.414ns - - Physical Path Details: - - Data path SLICE_4 to SLICE_48: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C5C.CLK to R5C5C.Q1 SLICE_4 (from RCLK_c) -ROUTE 23 2.237 R5C5C.Q1 to R2C7D.A1 FS[12] -CTOF_DEL --- 0.495 R2C7D.A1 to R2C7D.F1 SLICE_66 -ROUTE 1 0.436 R2C7D.F1 to R2C7D.C0 wb_adr_5_i_i_a2_3_0[0] -CTOF_DEL --- 0.495 R2C7D.C0 to R2C7D.F0 SLICE_66 -ROUTE 1 0.967 R2C7D.F0 to R2C7B.A0 wb_adr_5_i_i_1_0_tz_0[0] -CTOF_DEL --- 0.495 R2C7B.A0 to R2C7B.F0 SLICE_86 -ROUTE 1 1.001 R2C7B.F0 to R2C6A.B0 wb_adr_5_i_i_1_0[0] -CTOF_DEL --- 0.495 R2C6A.B0 to R2C6A.F0 SLICE_85 -ROUTE 1 1.042 R2C6A.F0 to R4C6D.D0 wb_adr_5_i_i_1[0] -CTOF_DEL --- 0.495 R4C6D.D0 to R4C6D.F0 SLICE_77 -ROUTE 1 0.315 R4C6D.F0 to R4C6C.D0 wb_adr_5_i_i_5[0] -CTOF_DEL --- 0.495 R4C6C.D0 to R4C6C.F0 SLICE_48 -ROUTE 1 0.000 R4C6C.F0 to R4C6C.DI0 N_283 (to RCLK_c) - -------- - 9.420 (36.3% logic, 63.7% route), 7 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_4: - - Name Fanout Delay (ns) Site Resource -ROUTE 48 2.264 63.PADDI to R5C5C.CLK RCLK_c - -------- - 2.264 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_48: - - Name Fanout Delay (ns) Site Resource -ROUTE 48 2.264 63.PADDI to R4C6C.CLK RCLK_c - -------- - 2.264 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 6.769ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[9] (from RCLK_c +) - Destination: FF Data in wb_adr[1] (to RCLK_c +) - - Delay: 9.065ns (32.3% logic, 67.7% route), 6 logic levels. - - Constraint Details: - - 9.065ns physical path delay SLICE_5 to SLICE_48 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 15.834ns) by 6.769ns - - Physical Path Details: - - Data path SLICE_5 to SLICE_48: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C5B.CLK to R5C5B.Q0 SLICE_5 (from RCLK_c) -ROUTE 14 1.803 R5C5B.Q0 to R3C6D.B1 FS[9] -CTOF_DEL --- 0.495 R3C6D.B1 to R3C6D.F1 SLICE_80 -ROUTE 7 1.131 R3C6D.F1 to R4C7C.C0 N_125 -CTOF_DEL --- 0.495 R4C7C.C0 to R4C7C.F0 SLICE_65 -ROUTE 1 0.436 R4C7C.F0 to R4C7C.C1 wb_adr_5_i_i_a2_0[1] -CTOF_DEL --- 0.495 R4C7C.C1 to R4C7C.F1 SLICE_65 -ROUTE 1 0.967 R4C7C.F1 to R4C7A.A0 N_428_tz -CTOF_DEL --- 0.495 R4C7A.A0 to R4C7A.F0 SLICE_61 -ROUTE 1 1.801 R4C7A.F0 to R4C6C.A1 wb_adr_5_i_i_0[1] -CTOF_DEL --- 0.495 R4C6C.A1 to R4C6C.F1 SLICE_48 -ROUTE 1 0.000 R4C6C.F1 to R4C6C.DI1 N_282 (to RCLK_c) - -------- - 9.065 (32.3% logic, 67.7% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_5: + Destination Clock Path RCLK to SLICE_45: Name Fanout Delay (ns) Site Resource ROUTE 48 2.264 63.PADDI to R5C5B.CLK RCLK_c -------- 2.264 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_48: - Name Fanout Delay (ns) Site Resource -ROUTE 48 2.264 63.PADDI to R4C6C.CLK RCLK_c - -------- - 2.264 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 7.019ns +Passed: The following path meets requirements by 6.365ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS[13] (from RCLK_c +) - Destination: FF Data in wb_dati[7] (to RCLK_c +) + Source: EFB Port ufmefb/EFBInst_0(ASIC) (from RCLK_c +) + Destination: FF Data in LEDEN (to RCLK_c +) - Delay: 8.815ns (33.2% logic, 66.8% route), 6 logic levels. + Delay: 9.296ns (69.4% logic, 30.6% route), 3 logic levels. Constraint Details: - 8.815ns physical path delay SLICE_3 to SLICE_56 meets + 9.296ns physical path delay ufmefb/EFBInst_0 to SLICE_30 meets 16.000ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.019ns + 0.173ns skew and + 0.166ns DIN_SET requirement (totaling 15.661ns) by 6.365ns Physical Path Details: - Data path SLICE_3 to SLICE_56: + Data path ufmefb/EFBInst_0 to SLICE_30: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C5D.CLK to R5C5D.Q0 SLICE_3 (from RCLK_c) -ROUTE 23 1.929 R5C5D.Q0 to R3C5D.A1 FS[13] -CTOF_DEL --- 0.495 R3C5D.A1 to R3C5D.F1 SLICE_70 -ROUTE 3 1.021 R3C5D.F1 to R3C5D.B0 N_348_2 -CTOF_DEL --- 0.495 R3C5D.B0 to R3C5D.F0 SLICE_70 -ROUTE 1 0.967 R3C5D.F0 to R3C5B.A0 wb_dati_5_1_iv_0_a2_3_0[7] -CTOF_DEL --- 0.495 R3C5B.A0 to R3C5B.F0 SLICE_108 -ROUTE 1 0.967 R3C5B.F0 to R3C5A.A1 wb_dati_5_1_iv_0_0[7] -CTOF_DEL --- 0.495 R3C5A.A1 to R3C5A.F1 SLICE_69 -ROUTE 1 1.004 R3C5A.F1 to R3C5C.B1 wb_dati_5_1_iv_0_1[7] -CTOF_DEL --- 0.495 R3C5C.B1 to R3C5C.F1 SLICE_56 -ROUTE 1 0.000 R3C5C.F1 to R3C5C.DI1 wb_dati_5[7] (to RCLK_c) +WCLKI2WBDA --- 5.461 EFB.WBCLKI to EFB.WBDATO1 ufmefb/EFBInst_0 (from RCLK_c) +ROUTE 1 2.152 EFB.WBDATO1 to R7C5A.A1 wb_dato[1] +CTOF_DEL --- 0.495 R7C5A.A1 to R7C5A.F1 SLICE_30 +ROUTE 1 0.693 R7C5A.F1 to R7C5A.B0 LEDEN_6 +CTOF_DEL --- 0.495 R7C5A.B0 to R7C5A.F0 SLICE_30 +ROUTE 1 0.000 R7C5A.F0 to R7C5A.DI0 LEDENe_0 (to RCLK_c) -------- - 8.815 (33.2% logic, 66.8% route), 6 logic levels. + 9.296 (69.4% logic, 30.6% route), 3 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_3: + Source Clock Path RCLK to ufmefb/EFBInst_0: Name Fanout Delay (ns) Site Resource -ROUTE 48 2.264 63.PADDI to R5C5D.CLK RCLK_c +ROUTE 48 2.437 63.PADDI to EFB.WBCLKI RCLK_c -------- - 2.264 (0.0% logic, 100.0% route), 0 logic levels. + 2.437 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_56: + Destination Clock Path RCLK to SLICE_30: Name Fanout Delay (ns) Site Resource -ROUTE 48 2.264 63.PADDI to R3C5C.CLK RCLK_c +ROUTE 48 2.264 63.PADDI to R7C5A.CLK RCLK_c -------- 2.264 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 7.040ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[13] (from RCLK_c +) - Destination: FF Data in wb_adr[1] (to RCLK_c +) - - Delay: 8.794ns (27.7% logic, 72.3% route), 5 logic levels. - - Constraint Details: - - 8.794ns physical path delay SLICE_3 to SLICE_48 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.040ns - - Physical Path Details: - - Data path SLICE_3 to SLICE_48: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C5D.CLK to R5C5D.Q0 SLICE_3 (from RCLK_c) -ROUTE 23 3.158 R5C5D.Q0 to R4C7C.A0 FS[13] -CTOF_DEL --- 0.495 R4C7C.A0 to R4C7C.F0 SLICE_65 -ROUTE 1 0.436 R4C7C.F0 to R4C7C.C1 wb_adr_5_i_i_a2_0[1] -CTOF_DEL --- 0.495 R4C7C.C1 to R4C7C.F1 SLICE_65 -ROUTE 1 0.967 R4C7C.F1 to R4C7A.A0 N_428_tz -CTOF_DEL --- 0.495 R4C7A.A0 to R4C7A.F0 SLICE_61 -ROUTE 1 1.801 R4C7A.F0 to R4C6C.A1 wb_adr_5_i_i_0[1] -CTOF_DEL --- 0.495 R4C6C.A1 to R4C6C.F1 SLICE_48 -ROUTE 1 0.000 R4C6C.F1 to R4C6C.DI1 N_282 (to RCLK_c) - -------- - 8.794 (27.7% logic, 72.3% route), 5 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_3: - - Name Fanout Delay (ns) Site Resource -ROUTE 48 2.264 63.PADDI to R5C5D.CLK RCLK_c - -------- - 2.264 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_48: - - Name Fanout Delay (ns) Site Resource -ROUTE 48 2.264 63.PADDI to R4C6C.CLK RCLK_c - -------- - 2.264 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 7.108ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[12] (from RCLK_c +) - Destination: FF Data in wb_dati[7] (to RCLK_c +) - - Delay: 8.726ns (33.5% logic, 66.5% route), 6 logic levels. - - Constraint Details: - - 8.726ns physical path delay SLICE_4 to SLICE_56 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.108ns - - Physical Path Details: - - Data path SLICE_4 to SLICE_56: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C5C.CLK to R5C5C.Q1 SLICE_4 (from RCLK_c) -ROUTE 23 1.840 R5C5C.Q1 to R3C5D.B1 FS[12] -CTOF_DEL --- 0.495 R3C5D.B1 to R3C5D.F1 SLICE_70 -ROUTE 3 1.021 R3C5D.F1 to R3C5D.B0 N_348_2 -CTOF_DEL --- 0.495 R3C5D.B0 to R3C5D.F0 SLICE_70 -ROUTE 1 0.967 R3C5D.F0 to R3C5B.A0 wb_dati_5_1_iv_0_a2_3_0[7] -CTOF_DEL --- 0.495 R3C5B.A0 to R3C5B.F0 SLICE_108 -ROUTE 1 0.967 R3C5B.F0 to R3C5A.A1 wb_dati_5_1_iv_0_0[7] -CTOF_DEL --- 0.495 R3C5A.A1 to R3C5A.F1 SLICE_69 -ROUTE 1 1.004 R3C5A.F1 to R3C5C.B1 wb_dati_5_1_iv_0_1[7] -CTOF_DEL --- 0.495 R3C5C.B1 to R3C5C.F1 SLICE_56 -ROUTE 1 0.000 R3C5C.F1 to R3C5C.DI1 wb_dati_5[7] (to RCLK_c) - -------- - 8.726 (33.5% logic, 66.5% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_4: - - Name Fanout Delay (ns) Site Resource -ROUTE 48 2.264 63.PADDI to R5C5C.CLK RCLK_c - -------- - 2.264 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_56: - - Name Fanout Delay (ns) Site Resource -ROUTE 48 2.264 63.PADDI to R3C5C.CLK RCLK_c - -------- - 2.264 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 7.132ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[10] (from RCLK_c +) - Destination: FF Data in wb_adr[1] (to RCLK_c +) - - Delay: 8.702ns (33.6% logic, 66.4% route), 6 logic levels. - - Constraint Details: - - 8.702ns physical path delay SLICE_5 to SLICE_48 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.132ns - - Physical Path Details: - - Data path SLICE_5 to SLICE_48: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C5B.CLK to R5C5B.Q1 SLICE_5 (from RCLK_c) -ROUTE 16 1.440 R5C5B.Q1 to R3C6D.A1 FS[10] -CTOF_DEL --- 0.495 R3C6D.A1 to R3C6D.F1 SLICE_80 -ROUTE 7 1.131 R3C6D.F1 to R4C7C.C0 N_125 -CTOF_DEL --- 0.495 R4C7C.C0 to R4C7C.F0 SLICE_65 -ROUTE 1 0.436 R4C7C.F0 to R4C7C.C1 wb_adr_5_i_i_a2_0[1] -CTOF_DEL --- 0.495 R4C7C.C1 to R4C7C.F1 SLICE_65 -ROUTE 1 0.967 R4C7C.F1 to R4C7A.A0 N_428_tz -CTOF_DEL --- 0.495 R4C7A.A0 to R4C7A.F0 SLICE_61 -ROUTE 1 1.801 R4C7A.F0 to R4C6C.A1 wb_adr_5_i_i_0[1] -CTOF_DEL --- 0.495 R4C6C.A1 to R4C6C.F1 SLICE_48 -ROUTE 1 0.000 R4C6C.F1 to R4C6C.DI1 N_282 (to RCLK_c) - -------- - 8.702 (33.6% logic, 66.4% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_5: - - Name Fanout Delay (ns) Site Resource -ROUTE 48 2.264 63.PADDI to R5C5B.CLK RCLK_c - -------- - 2.264 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_48: - - Name Fanout Delay (ns) Site Resource -ROUTE 48 2.264 63.PADDI to R4C6C.CLK RCLK_c - -------- - 2.264 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 7.246ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[11] (from RCLK_c +) - Destination: FF Data in wb_adr[1] (to RCLK_c +) - - Delay: 8.588ns (28.3% logic, 71.7% route), 5 logic levels. - - Constraint Details: - - 8.588ns physical path delay SLICE_4 to SLICE_48 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.246ns - - Physical Path Details: - - Data path SLICE_4 to SLICE_48: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C5C.CLK to R5C5C.Q0 SLICE_4 (from RCLK_c) -ROUTE 21 1.215 R5C5C.Q0 to R2C7A.D1 FS[11] -CTOF_DEL --- 0.495 R2C7A.D1 to R2C7A.F1 SLICE_101 -ROUTE 4 2.173 R2C7A.F1 to R4C7C.B1 N_142 -CTOF_DEL --- 0.495 R4C7C.B1 to R4C7C.F1 SLICE_65 -ROUTE 1 0.967 R4C7C.F1 to R4C7A.A0 N_428_tz -CTOF_DEL --- 0.495 R4C7A.A0 to R4C7A.F0 SLICE_61 -ROUTE 1 1.801 R4C7A.F0 to R4C6C.A1 wb_adr_5_i_i_0[1] -CTOF_DEL --- 0.495 R4C6C.A1 to R4C6C.F1 SLICE_48 -ROUTE 1 0.000 R4C6C.F1 to R4C6C.DI1 N_282 (to RCLK_c) - -------- - 8.588 (28.3% logic, 71.7% route), 5 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_4: - - Name Fanout Delay (ns) Site Resource -ROUTE 48 2.264 63.PADDI to R5C5C.CLK RCLK_c - -------- - 2.264 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_48: - - Name Fanout Delay (ns) Site Resource -ROUTE 48 2.264 63.PADDI to R4C6C.CLK RCLK_c - -------- - 2.264 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 7.249ns +Passed: The following path meets requirements by 6.454ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q InitReady (from RCLK_c +) Destination: FF Data in nRWE_0io (to RCLK_c +) - Delay: 8.771ns (27.7% logic, 72.3% route), 5 logic levels. + Delay: 9.566ns (30.6% logic, 69.4% route), 6 logic levels. Constraint Details: - 8.771ns physical path delay SLICE_30 to nRWE_MGIOL meets + 9.566ns physical path delay SLICE_29 to nRWE_MGIOL meets 16.000ns delay constraint less -0.173ns skew and - 0.153ns DO_SET requirement (totaling 16.020ns) by 7.249ns + 0.153ns DO_SET requirement (totaling 16.020ns) by 6.454ns Physical Path Details: - Data path SLICE_30 to nRWE_MGIOL: + Data path SLICE_29 to nRWE_MGIOL: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R4C8D.CLK to R4C8D.Q0 SLICE_30 (from RCLK_c) -ROUTE 31 1.714 R4C8D.Q0 to R7C15A.D1 InitReady -CTOF_DEL --- 0.495 R7C15A.D1 to R7C15A.F1 SLICE_62 -ROUTE 6 1.032 R7C15A.F1 to R7C16A.B1 N_43 -CTOF_DEL --- 0.495 R7C16A.B1 to R7C16A.F1 SLICE_78 -ROUTE 2 0.775 R7C16A.F1 to R7C14B.C1 IS_0_sqmuxa_0_o2 -CTOF_DEL --- 0.495 R7C14B.C1 to R7C14B.F1 SLICE_68 -ROUTE 1 1.023 R7C14B.F1 to R8C14C.B1 nRWE_0io_RNO_0 -CTOF_DEL --- 0.495 R8C14C.B1 to R8C14C.F1 SLICE_92 -ROUTE 1 1.795 R8C14C.F1 to IOL_B20D.OPOS N_37_i (to RCLK_c) +REG_DEL --- 0.452 R4C8D.CLK to R4C8D.Q0 SLICE_29 (from RCLK_c) +ROUTE 40 1.724 R4C8D.Q0 to R8C11B.D1 InitReady +CTOF_DEL --- 0.495 R8C11B.D1 to R8C11B.F1 SLICE_62 +ROUTE 6 1.078 R8C11B.F1 to R7C12C.D1 IS_0_sqmuxa_0_o2 +CTOF_DEL --- 0.495 R7C12C.D1 to R7C12C.F1 SLICE_79 +ROUTE 2 0.635 R7C12C.F1 to R7C12A.D1 IS_0_sqmuxa_0_o3 +CTOF_DEL --- 0.495 R7C12A.D1 to R7C12A.F1 SLICE_28 +ROUTE 1 0.744 R7C12A.F1 to R8C12B.C1 nRWE_s_i_a2_1_0 +CTOF_DEL --- 0.495 R8C12B.C1 to R8C12B.F1 SLICE_68 +ROUTE 1 0.744 R8C12B.F1 to R9C12D.C0 nRWE_s_i_tz_0 +CTOF_DEL --- 0.495 R9C12D.C0 to R9C12D.F0 SLICE_75 +ROUTE 1 1.714 R9C12D.F0 to IOL_B20D.OPOS N_252_i (to RCLK_c) -------- - 8.771 (27.7% logic, 72.3% route), 5 logic levels. + 9.566 (30.6% logic, 69.4% route), 6 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_30: + Source Clock Path RCLK to SLICE_29: Name Fanout Delay (ns) Site Resource ROUTE 48 2.264 63.PADDI to R4C8D.CLK RCLK_c @@ -1115,7 +799,321 @@ ROUTE 48 2.437 63.PADDI to IOL_B20D.CLK RCLK_c -------- 2.437 (0.0% logic, 100.0% route), 0 logic levels. -Report: 98.020MHz is the maximum frequency for this preference. + +Passed: The following path meets requirements by 6.646ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS[1] (from RCLK_c +) + Destination: FF Data in nRCAS_0io (to RCLK_c +) + + Delay: 9.373ns (31.2% logic, 68.8% route), 6 logic levels. + + Constraint Details: + + 9.373ns physical path delay SLICE_27 to nRCAS_MGIOL meets + 16.000ns delay constraint less + -0.172ns skew and + 0.153ns DO_SET requirement (totaling 16.019ns) by 6.646ns + + Physical Path Details: + + Data path SLICE_27 to nRCAS_MGIOL: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R7C11C.CLK to R7C11C.Q0 SLICE_27 (from RCLK_c) +ROUTE 7 1.445 R7C11C.Q0 to R8C12A.A1 IS[1] +CTOF_DEL --- 0.495 R8C12A.A1 to R8C12A.F1 SLICE_83 +ROUTE 3 0.973 R8C12A.F1 to R8C11B.A0 un1_nRCAS_6_sqmuxa_i_o2 +CTOF_DEL --- 0.495 R8C11B.A0 to R8C11B.F0 SLICE_62 +ROUTE 2 0.632 R8C11B.F0 to R9C11A.D0 N_48 +CTOF_DEL --- 0.495 R9C11A.D0 to R9C11A.F0 SLICE_69 +ROUTE 1 0.626 R9C11A.F0 to R9C11A.D1 nRCS_9_u_i_o3_0_0 +CTOF_DEL --- 0.495 R9C11A.D1 to R9C11A.F1 SLICE_69 +ROUTE 1 0.744 R9C11A.F1 to R9C12C.C1 nRCS_9_u_i_o3_0_2 +CTOF_DEL --- 0.495 R9C12C.C1 to R9C12C.F1 SLICE_101 +ROUTE 1 2.026 R9C12C.F1 to IOL_R10C.OPOS N_251_i (to RCLK_c) + -------- + 9.373 (31.2% logic, 68.8% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_27: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.264 63.PADDI to R7C11C.CLK RCLK_c + -------- + 2.264 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to nRCAS_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.436 63.PADDI to IOL_R10C.CLK RCLK_c + -------- + 2.436 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 6.656ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RASr2 (from RCLK_c +) + Destination: FF Data in nRCAS_0io (to RCLK_c +) + + Delay: 9.363ns (31.3% logic, 68.7% route), 6 logic levels. + + Constraint Details: + + 9.363ns physical path delay SLICE_32 to nRCAS_MGIOL meets + 16.000ns delay constraint less + -0.172ns skew and + 0.153ns DO_SET requirement (totaling 16.019ns) by 6.656ns + + Physical Path Details: + + Data path SLICE_32 to nRCAS_MGIOL: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R4C12C.CLK to R4C12C.Q1 SLICE_32 (from RCLK_c) +ROUTE 10 1.963 R4C12C.Q1 to R8C11B.A1 RASr2 +CTOF_DEL --- 0.495 R8C11B.A1 to R8C11B.F1 SLICE_62 +ROUTE 6 0.445 R8C11B.F1 to R8C11B.C0 IS_0_sqmuxa_0_o2 +CTOF_DEL --- 0.495 R8C11B.C0 to R8C11B.F0 SLICE_62 +ROUTE 2 0.632 R8C11B.F0 to R9C11A.D0 N_48 +CTOF_DEL --- 0.495 R9C11A.D0 to R9C11A.F0 SLICE_69 +ROUTE 1 0.626 R9C11A.F0 to R9C11A.D1 nRCS_9_u_i_o3_0_0 +CTOF_DEL --- 0.495 R9C11A.D1 to R9C11A.F1 SLICE_69 +ROUTE 1 0.744 R9C11A.F1 to R9C12C.C1 nRCS_9_u_i_o3_0_2 +CTOF_DEL --- 0.495 R9C12C.C1 to R9C12C.F1 SLICE_101 +ROUTE 1 2.026 R9C12C.F1 to IOL_R10C.OPOS N_251_i (to RCLK_c) + -------- + 9.363 (31.3% logic, 68.7% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_32: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.264 63.PADDI to R4C12C.CLK RCLK_c + -------- + 2.264 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to nRCAS_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.436 63.PADDI to IOL_R10C.CLK RCLK_c + -------- + 2.436 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 6.868ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS[1] (from RCLK_c +) + Destination: FF Data in nRCAS_0io (to RCLK_c +) + + Delay: 9.151ns (26.6% logic, 73.4% route), 5 logic levels. + + Constraint Details: + + 9.151ns physical path delay SLICE_27 to nRCAS_MGIOL meets + 16.000ns delay constraint less + -0.172ns skew and + 0.153ns DO_SET requirement (totaling 16.019ns) by 6.868ns + + Physical Path Details: + + Data path SLICE_27 to nRCAS_MGIOL: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R7C11C.CLK to R7C11C.Q0 SLICE_27 (from RCLK_c) +ROUTE 7 1.445 R7C11C.Q0 to R8C12A.A1 IS[1] +CTOF_DEL --- 0.495 R8C12A.A1 to R8C12A.F1 SLICE_83 +ROUTE 3 0.973 R8C12A.F1 to R8C11B.A0 un1_nRCAS_6_sqmuxa_i_o2 +CTOF_DEL --- 0.495 R8C11B.A0 to R8C11B.F0 SLICE_62 +ROUTE 2 1.308 R8C11B.F0 to R9C12C.A0 N_48 +CTOF_DEL --- 0.495 R9C12C.A0 to R9C12C.F0 SLICE_101 +ROUTE 1 0.967 R9C12C.F0 to R9C12C.A1 N_251_i_sx +CTOF_DEL --- 0.495 R9C12C.A1 to R9C12C.F1 SLICE_101 +ROUTE 1 2.026 R9C12C.F1 to IOL_R10C.OPOS N_251_i (to RCLK_c) + -------- + 9.151 (26.6% logic, 73.4% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_27: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.264 63.PADDI to R7C11C.CLK RCLK_c + -------- + 2.264 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to nRCAS_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.436 63.PADDI to IOL_R10C.CLK RCLK_c + -------- + 2.436 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 6.878ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RASr2 (from RCLK_c +) + Destination: FF Data in nRCAS_0io (to RCLK_c +) + + Delay: 9.141ns (26.6% logic, 73.4% route), 5 logic levels. + + Constraint Details: + + 9.141ns physical path delay SLICE_32 to nRCAS_MGIOL meets + 16.000ns delay constraint less + -0.172ns skew and + 0.153ns DO_SET requirement (totaling 16.019ns) by 6.878ns + + Physical Path Details: + + Data path SLICE_32 to nRCAS_MGIOL: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R4C12C.CLK to R4C12C.Q1 SLICE_32 (from RCLK_c) +ROUTE 10 1.963 R4C12C.Q1 to R8C11B.A1 RASr2 +CTOF_DEL --- 0.495 R8C11B.A1 to R8C11B.F1 SLICE_62 +ROUTE 6 0.445 R8C11B.F1 to R8C11B.C0 IS_0_sqmuxa_0_o2 +CTOF_DEL --- 0.495 R8C11B.C0 to R8C11B.F0 SLICE_62 +ROUTE 2 1.308 R8C11B.F0 to R9C12C.A0 N_48 +CTOF_DEL --- 0.495 R9C12C.A0 to R9C12C.F0 SLICE_101 +ROUTE 1 0.967 R9C12C.F0 to R9C12C.A1 N_251_i_sx +CTOF_DEL --- 0.495 R9C12C.A1 to R9C12C.F1 SLICE_101 +ROUTE 1 2.026 R9C12C.F1 to IOL_R10C.OPOS N_251_i (to RCLK_c) + -------- + 9.141 (26.6% logic, 73.4% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_32: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.264 63.PADDI to R4C12C.CLK RCLK_c + -------- + 2.264 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to nRCAS_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.436 63.PADDI to IOL_R10C.CLK RCLK_c + -------- + 2.436 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 6.895ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q InitReady (from RCLK_c +) + Destination: FF Data in nRCAS_0io (to RCLK_c +) + + Delay: 9.124ns (32.1% logic, 67.9% route), 6 logic levels. + + Constraint Details: + + 9.124ns physical path delay SLICE_29 to nRCAS_MGIOL meets + 16.000ns delay constraint less + -0.172ns skew and + 0.153ns DO_SET requirement (totaling 16.019ns) by 6.895ns + + Physical Path Details: + + Data path SLICE_29 to nRCAS_MGIOL: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R4C8D.CLK to R4C8D.Q0 SLICE_29 (from RCLK_c) +ROUTE 40 1.724 R4C8D.Q0 to R8C11B.D1 InitReady +CTOF_DEL --- 0.495 R8C11B.D1 to R8C11B.F1 SLICE_62 +ROUTE 6 0.445 R8C11B.F1 to R8C11B.C0 IS_0_sqmuxa_0_o2 +CTOF_DEL --- 0.495 R8C11B.C0 to R8C11B.F0 SLICE_62 +ROUTE 2 0.632 R8C11B.F0 to R9C11A.D0 N_48 +CTOF_DEL --- 0.495 R9C11A.D0 to R9C11A.F0 SLICE_69 +ROUTE 1 0.626 R9C11A.F0 to R9C11A.D1 nRCS_9_u_i_o3_0_0 +CTOF_DEL --- 0.495 R9C11A.D1 to R9C11A.F1 SLICE_69 +ROUTE 1 0.744 R9C11A.F1 to R9C12C.C1 nRCS_9_u_i_o3_0_2 +CTOF_DEL --- 0.495 R9C12C.C1 to R9C12C.F1 SLICE_101 +ROUTE 1 2.026 R9C12C.F1 to IOL_R10C.OPOS N_251_i (to RCLK_c) + -------- + 9.124 (32.1% logic, 67.9% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_29: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.264 63.PADDI to R4C8D.CLK RCLK_c + -------- + 2.264 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to nRCAS_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.436 63.PADDI to IOL_R10C.CLK RCLK_c + -------- + 2.436 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 6.966ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS[2] (from RCLK_c +) + Destination: FF Data in nRCAS_0io (to RCLK_c +) + + Delay: 9.053ns (32.3% logic, 67.7% route), 6 logic levels. + + Constraint Details: + + 9.053ns physical path delay SLICE_27 to nRCAS_MGIOL meets + 16.000ns delay constraint less + -0.172ns skew and + 0.153ns DO_SET requirement (totaling 16.019ns) by 6.966ns + + Physical Path Details: + + Data path SLICE_27 to nRCAS_MGIOL: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R7C11C.CLK to R7C11C.Q1 SLICE_27 (from RCLK_c) +ROUTE 6 1.125 R7C11C.Q1 to R8C12A.C1 IS[2] +CTOF_DEL --- 0.495 R8C12A.C1 to R8C12A.F1 SLICE_83 +ROUTE 3 0.973 R8C12A.F1 to R8C11B.A0 un1_nRCAS_6_sqmuxa_i_o2 +CTOF_DEL --- 0.495 R8C11B.A0 to R8C11B.F0 SLICE_62 +ROUTE 2 0.632 R8C11B.F0 to R9C11A.D0 N_48 +CTOF_DEL --- 0.495 R9C11A.D0 to R9C11A.F0 SLICE_69 +ROUTE 1 0.626 R9C11A.F0 to R9C11A.D1 nRCS_9_u_i_o3_0_0 +CTOF_DEL --- 0.495 R9C11A.D1 to R9C11A.F1 SLICE_69 +ROUTE 1 0.744 R9C11A.F1 to R9C12C.C1 nRCS_9_u_i_o3_0_2 +CTOF_DEL --- 0.495 R9C12C.C1 to R9C12C.F1 SLICE_101 +ROUTE 1 2.026 R9C12C.F1 to IOL_R10C.OPOS N_251_i (to RCLK_c) + -------- + 9.053 (32.3% logic, 67.7% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_27: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.264 63.PADDI to R7C11C.CLK RCLK_c + -------- + 2.264 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to nRCAS_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.436 63.PADDI to IOL_R10C.CLK RCLK_c + -------- + 2.436 (0.0% logic, 100.0% route), 0 logic levels. + +Report: 102.197MHz is the maximum frequency for this preference. Report Summary -------------- @@ -1123,13 +1121,13 @@ Report Summary Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | -FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 50.206 MHz| 6 +FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 48.464 MHz| 5 | | | FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0 | | | FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0 | | | -FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 98.020 MHz| 5 +FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 102.197 MHz| 6 | | | ---------------------------------------------------------------------------- @@ -1142,7 +1140,7 @@ Clock Domains Analysis Found 4 clocks: -Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12 +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11 No transfer within this clock domain is found Data transfers from: @@ -1184,11 +1182,11 @@ Timing summary (Setup): Timing errors: 0 Score: 0 Cumulative negative slack: 0 -Constraints cover 1015 paths, 4 nets, and 725 connections (73.01% coverage) +Constraints cover 1038 paths, 4 nets, and 750 connections (74.18% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 -Thu Oct 19 23:51:11 2023 +Sat Nov 18 02:06:13 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -1221,43 +1219,43 @@ Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q C1Submitted (from PHI2_c -) - Destination: FF Data in C1Submitted (to PHI2_c -) + Source: FF Q ADSubmitted (from PHI2_c -) + Destination: FF Data in ADSubmitted (to PHI2_c -) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: - 0.366ns physical path delay SLICE_11 to SLICE_11 meets + 0.366ns physical path delay SLICE_10 to SLICE_10 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: - Data path SLICE_11 to SLICE_11: + Data path SLICE_10 to SLICE_10: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C12A.CLK to R5C12A.Q0 SLICE_11 (from PHI2_c) -ROUTE 2 0.132 R5C12A.Q0 to R5C12A.A0 C1Submitted -CTOF_DEL --- 0.101 R5C12A.A0 to R5C12A.F0 SLICE_11 -ROUTE 1 0.000 R5C12A.F0 to R5C12A.DI0 C1Submitted_RNO (to PHI2_c) +REG_DEL --- 0.133 R4C9D.CLK to R4C9D.Q0 SLICE_10 (from PHI2_c) +ROUTE 2 0.132 R4C9D.Q0 to R4C9D.A0 ADSubmitted +CTOF_DEL --- 0.101 R4C9D.A0 to R4C9D.F0 SLICE_10 +ROUTE 1 0.000 R4C9D.F0 to R4C9D.DI0 ADSubmitted_r_0_0 (to PHI2_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_11: + Source Clock Path PHI2 to SLICE_10: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R5C12A.CLK PHI2_c +ROUTE 21 1.423 8.PADDI to R4C9D.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_11: + Destination Clock Path PHI2 to SLICE_10: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R5C12A.CLK PHI2_c +ROUTE 21 1.423 8.PADDI to R4C9D.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. @@ -1283,10 +1281,10 @@ Passed: The following path meets requirements by 0.379ns Data path SLICE_20 to SLICE_20: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R4C10B.CLK to R4C10B.Q0 SLICE_20 (from PHI2_c) -ROUTE 2 0.132 R4C10B.Q0 to R4C10B.A0 CmdUFMShift -CTOF_DEL --- 0.101 R4C10B.A0 to R4C10B.F0 SLICE_20 -ROUTE 1 0.000 R4C10B.F0 to R4C10B.DI0 CmdUFMShift_3 (to PHI2_c) +REG_DEL --- 0.133 R7C9A.CLK to R7C9A.Q0 SLICE_20 (from PHI2_c) +ROUTE 2 0.132 R7C9A.Q0 to R7C9A.A0 CmdUFMShift +CTOF_DEL --- 0.101 R7C9A.A0 to R7C9A.F0 SLICE_20 +ROUTE 1 0.000 R7C9A.F0 to R7C9A.DI0 CmdUFMShift_3 (to PHI2_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. @@ -1295,384 +1293,384 @@ ROUTE 1 0.000 R4C10B.F0 to R4C10B.DI0 CmdUFMShift_3 (to PHI Source Clock Path PHI2 to SLICE_20: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R4C10B.CLK PHI2_c +ROUTE 21 1.423 8.PADDI to R7C9A.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_20: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R4C10B.CLK PHI2_c +ROUTE 21 1.423 8.PADDI to R7C9A.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 0.382ns +Passed: The following path meets requirements by 0.385ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q ADSubmitted (from PHI2_c -) - Destination: FF Data in ADSubmitted (to PHI2_c -) + Source: FF Q C1Submitted (from PHI2_c -) + Destination: FF Data in C1Submitted (to PHI2_c -) - Delay: 0.369ns (63.4% logic, 36.6% route), 2 logic levels. + Delay: 0.372ns (62.9% logic, 37.1% route), 2 logic levels. Constraint Details: - 0.369ns physical path delay SLICE_10 to SLICE_10 meets + 0.372ns physical path delay SLICE_11 to SLICE_11 meets -0.013ns DIN_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.382ns + 0.000ns skew requirement (totaling -0.013ns) by 0.385ns Physical Path Details: - Data path SLICE_10 to SLICE_10: + Data path SLICE_11 to SLICE_11: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C12C.CLK to R5C12C.Q0 SLICE_10 (from PHI2_c) -ROUTE 2 0.135 R5C12C.Q0 to R5C12C.D0 ADSubmitted -CTOF_DEL --- 0.101 R5C12C.D0 to R5C12C.F0 SLICE_10 -ROUTE 1 0.000 R5C12C.F0 to R5C12C.DI0 ADSubmitted_r_0 (to PHI2_c) +REG_DEL --- 0.133 R4C9A.CLK to R4C9A.Q0 SLICE_11 (from PHI2_c) +ROUTE 2 0.138 R4C9A.Q0 to R4C9A.C0 C1Submitted +CTOF_DEL --- 0.101 R4C9A.C0 to R4C9A.F0 SLICE_11 +ROUTE 1 0.000 R4C9A.F0 to R4C9A.DI0 C1Submitted_RNO (to PHI2_c) -------- - 0.369 (63.4% logic, 36.6% route), 2 logic levels. + 0.372 (62.9% logic, 37.1% route), 2 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_10: + Source Clock Path PHI2 to SLICE_11: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R5C12C.CLK PHI2_c +ROUTE 21 1.423 8.PADDI to R4C9A.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_10: + Destination Clock Path PHI2 to SLICE_11: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R5C12C.CLK PHI2_c +ROUTE 21 1.423 8.PADDI to R4C9A.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 0.387ns +Passed: The following path meets requirements by 0.471ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CmdEnable (from PHI2_c -) Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 0.374ns (62.6% logic, 37.4% route), 2 logic levels. + Delay: 0.458ns (51.1% logic, 48.9% route), 2 logic levels. Constraint Details: - 0.374ns physical path delay SLICE_17 to SLICE_17 meets + 0.458ns physical path delay SLICE_17 to SLICE_17 meets -0.013ns DIN_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.387ns + 0.000ns skew requirement (totaling -0.013ns) by 0.471ns Physical Path Details: Data path SLICE_17 to SLICE_17: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C11D.CLK to R5C11D.Q0 SLICE_17 (from PHI2_c) -ROUTE 4 0.140 R5C11D.Q0 to R5C11D.D0 CmdEnable -CTOF_DEL --- 0.101 R5C11D.D0 to R5C11D.F0 SLICE_17 -ROUTE 1 0.000 R5C11D.F0 to R5C11D.DI0 CmdEnable_s (to PHI2_c) +REG_DEL --- 0.133 R4C9B.CLK to R4C9B.Q0 SLICE_17 (from PHI2_c) +ROUTE 2 0.224 R4C9B.Q0 to R4C9B.B0 CmdEnable +CTOF_DEL --- 0.101 R4C9B.B0 to R4C9B.F0 SLICE_17 +ROUTE 1 0.000 R4C9B.F0 to R4C9B.DI0 CmdEnable_s (to PHI2_c) -------- - 0.374 (62.6% logic, 37.4% route), 2 logic levels. + 0.458 (51.1% logic, 48.9% route), 2 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_17: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R5C11D.CLK PHI2_c +ROUTE 21 1.423 8.PADDI to R4C9B.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_17: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R5C11D.CLK PHI2_c +ROUTE 21 1.423 8.PADDI to R4C9B.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.616ns - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CmdUFMWrite (from PHI2_c -) - Destination: FF Data in CmdUFMWrite (to PHI2_c -) - - Delay: 0.603ns (55.6% logic, 44.4% route), 3 logic levels. - - Constraint Details: - - 0.603ns physical path delay SLICE_21 to SLICE_21 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.616ns - - Physical Path Details: - - Data path SLICE_21 to SLICE_21: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R4C10D.CLK to R4C10D.Q0 SLICE_21 (from PHI2_c) -ROUTE 2 0.212 R4C10D.Q0 to R4C10D.A1 CmdUFMWrite -CTOF_DEL --- 0.101 R4C10D.A1 to R4C10D.F1 SLICE_21 -ROUTE 1 0.056 R4C10D.F1 to R4C10D.C0 N_279 -CTOF_DEL --- 0.101 R4C10D.C0 to R4C10D.F0 SLICE_21 -ROUTE 1 0.000 R4C10D.F0 to R4C10D.DI0 CmdUFMWrite_3 (to PHI2_c) - -------- - 0.603 (55.6% logic, 44.4% route), 3 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_21: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R4C10D.CLK PHI2_c - -------- - 1.423 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_21: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R4C10D.CLK PHI2_c - -------- - 1.423 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.616ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Cmdn8MEGEN (from PHI2_c -) - Destination: FF Data in Cmdn8MEGEN (to PHI2_c -) - - Delay: 0.603ns (55.6% logic, 44.4% route), 3 logic levels. - - Constraint Details: - - 0.603ns physical path delay SLICE_24 to SLICE_24 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.616ns - - Physical Path Details: - - Data path SLICE_24 to SLICE_24: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C10C.CLK to R3C10C.Q0 SLICE_24 (from PHI2_c) -ROUTE 2 0.212 R3C10C.Q0 to R3C10C.A1 Cmdn8MEGEN -CTOF_DEL --- 0.101 R3C10C.A1 to R3C10C.F1 SLICE_24 -ROUTE 1 0.056 R3C10C.F1 to R3C10C.C0 Cmdn8MEGEN_4_u_i_0 -CTOF_DEL --- 0.101 R3C10C.C0 to R3C10C.F0 SLICE_24 -ROUTE 1 0.000 R3C10C.F0 to R3C10C.DI0 N_285_i (to PHI2_c) - -------- - 0.603 (55.6% logic, 44.4% route), 3 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_24: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R3C10C.CLK PHI2_c - -------- - 1.423 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_24: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R3C10C.CLK PHI2_c - -------- - 1.423 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.616ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q XOR8MEG (from PHI2_c -) - Destination: FF Data in XOR8MEG (to PHI2_c -) - - Delay: 0.603ns (55.6% logic, 44.4% route), 3 logic levels. - - Constraint Details: - - 0.603ns physical path delay SLICE_45 to SLICE_45 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.616ns - - Physical Path Details: - - Data path SLICE_45 to SLICE_45: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C10D.CLK to R5C10D.Q0 SLICE_45 (from PHI2_c) -ROUTE 2 0.212 R5C10D.Q0 to R5C10D.A1 XOR8MEG -CTOF_DEL --- 0.101 R5C10D.A1 to R5C10D.F1 SLICE_45 -ROUTE 1 0.056 R5C10D.F1 to R5C10D.C0 N_274 -CTOF_DEL --- 0.101 R5C10D.C0 to R5C10D.F0 SLICE_45 -ROUTE 1 0.000 R5C10D.F0 to R5C10D.DI0 XOR8MEG_3 (to PHI2_c) - -------- - 0.603 (55.6% logic, 44.4% route), 3 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_45: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R5C10D.CLK PHI2_c - -------- - 1.423 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_45: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R5C10D.CLK PHI2_c - -------- - 1.423 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.628ns - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CmdLEDEN (from PHI2_c -) Destination: FF Data in CmdLEDEN (to PHI2_c -) - Delay: 0.615ns (54.5% logic, 45.5% route), 3 logic levels. + Delay: 0.603ns (55.6% logic, 44.4% route), 3 logic levels. Constraint Details: - 0.615ns physical path delay SLICE_18 to SLICE_18 meets + 0.603ns physical path delay SLICE_18 to SLICE_18 meets -0.013ns DIN_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.628ns + 0.000ns skew requirement (totaling -0.013ns) by 0.616ns Physical Path Details: Data path SLICE_18 to SLICE_18: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C10B.CLK to R3C10B.Q0 SLICE_18 (from PHI2_c) -ROUTE 2 0.224 R3C10B.Q0 to R3C10B.B1 CmdLEDEN -CTOF_DEL --- 0.101 R3C10B.B1 to R3C10B.F1 SLICE_18 -ROUTE 1 0.056 R3C10B.F1 to R3C10B.C0 CmdLEDEN_4_u_i_0 -CTOF_DEL --- 0.101 R3C10B.C0 to R3C10B.F0 SLICE_18 -ROUTE 1 0.000 R3C10B.F0 to R3C10B.DI0 N_284_i (to PHI2_c) +REG_DEL --- 0.133 R7C8C.CLK to R7C8C.Q0 SLICE_18 (from PHI2_c) +ROUTE 2 0.212 R7C8C.Q0 to R7C8C.A1 CmdLEDEN +CTOF_DEL --- 0.101 R7C8C.A1 to R7C8C.F1 SLICE_18 +ROUTE 1 0.056 R7C8C.F1 to R7C8C.C0 CmdLEDEN_4_u_i_m2_i_0 +CTOF_DEL --- 0.101 R7C8C.C0 to R7C8C.F0 SLICE_18 +ROUTE 1 0.000 R7C8C.F0 to R7C8C.DI0 N_17_i (to PHI2_c) -------- - 0.615 (54.5% logic, 45.5% route), 3 logic levels. + 0.603 (55.6% logic, 44.4% route), 3 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_18: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R3C10B.CLK PHI2_c +ROUTE 21 1.423 8.PADDI to R7C8C.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_18: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R3C10B.CLK PHI2_c +ROUTE 21 1.423 8.PADDI to R7C8C.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 0.632ns +Passed: The following path meets requirements by 0.622ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q C1Submitted (from PHI2_c -) + Destination: FF Data in CmdEnable (to PHI2_c -) + + Delay: 0.609ns (55.0% logic, 45.0% route), 3 logic levels. + + Constraint Details: + + 0.609ns physical path delay SLICE_11 to SLICE_17 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.622ns + + Physical Path Details: + + Data path SLICE_11 to SLICE_17: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R4C9A.CLK to R4C9A.Q0 SLICE_11 (from PHI2_c) +ROUTE 2 0.137 R4C9A.Q0 to R5C9D.D0 C1Submitted +CTOF_DEL --- 0.101 R5C9D.D0 to R5C9D.F0 SLICE_76 +ROUTE 1 0.137 R5C9D.F0 to R4C9B.C0 un1_CmdEnable20_i +CTOF_DEL --- 0.101 R4C9B.C0 to R4C9B.F0 SLICE_17 +ROUTE 1 0.000 R4C9B.F0 to R4C9B.DI0 CmdEnable_s (to PHI2_c) + -------- + 0.609 (55.0% logic, 45.0% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_11: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 1.423 8.PADDI to R4C9A.CLK PHI2_c + -------- + 1.423 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_17: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 1.423 8.PADDI to R4C9B.CLK PHI2_c + -------- + 1.423 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.705ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Cmdn8MEGEN (from PHI2_c -) + Destination: FF Data in Cmdn8MEGEN (to PHI2_c -) + + Delay: 0.692ns (48.4% logic, 51.6% route), 3 logic levels. + + Constraint Details: + + 0.692ns physical path delay SLICE_24 to SLICE_24 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.705ns + + Physical Path Details: + + Data path SLICE_24 to SLICE_24: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R7C8B.CLK to R7C8B.Q0 SLICE_24 (from PHI2_c) +ROUTE 2 0.135 R7C8B.Q0 to R7C8B.D1 Cmdn8MEGEN +CTOF_DEL --- 0.101 R7C8B.D1 to R7C8B.F1 SLICE_24 +ROUTE 1 0.222 R7C8B.F1 to R7C8B.B0 Cmdn8MEGEN_4_u_i_m2_i_0 +CTOF_DEL --- 0.101 R7C8B.B0 to R7C8B.F0 SLICE_24 +ROUTE 1 0.000 R7C8B.F0 to R7C8B.DI0 N_15_i (to PHI2_c) + -------- + 0.692 (48.4% logic, 51.6% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_24: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 1.423 8.PADDI to R7C8B.CLK PHI2_c + -------- + 1.423 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_24: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 1.423 8.PADDI to R7C8B.CLK PHI2_c + -------- + 1.423 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.728ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable (from PHI2_c -) + Destination: FF Data in CmdUFMShift (to PHI2_c -) + + Delay: 0.700ns (33.4% logic, 66.6% route), 2 logic levels. + + Constraint Details: + + 0.700ns physical path delay SLICE_17 to SLICE_20 meets + -0.028ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.028ns) by 0.728ns + + Physical Path Details: + + Data path SLICE_17 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R4C9B.CLK to R4C9B.Q0 SLICE_17 (from PHI2_c) +ROUTE 2 0.277 R4C9B.Q0 to R5C9A.C1 CmdEnable +CTOF_DEL --- 0.101 R5C9A.C1 to R5C9A.F1 SLICE_23 +ROUTE 8 0.189 R5C9A.F1 to R7C9A.CE XOR8MEG18 (to PHI2_c) + -------- + 0.700 (33.4% logic, 66.6% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_17: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 1.423 8.PADDI to R4C9B.CLK PHI2_c + -------- + 1.423 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 1.423 8.PADDI to R7C9A.CLK PHI2_c + -------- + 1.423 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.770ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CmdEnable (from PHI2_c -) Destination: FF Data in CmdValid_fast (to PHI2_c -) - Delay: 0.619ns (54.1% logic, 45.9% route), 3 logic levels. + Delay: 0.757ns (44.3% logic, 55.7% route), 3 logic levels. Constraint Details: - 0.619ns physical path delay SLICE_17 to SLICE_23 meets + 0.757ns physical path delay SLICE_17 to SLICE_23 meets -0.013ns DIN_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.632ns + 0.000ns skew requirement (totaling -0.013ns) by 0.770ns Physical Path Details: Data path SLICE_17 to SLICE_23: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C11D.CLK to R5C11D.Q0 SLICE_17 (from PHI2_c) -ROUTE 4 0.226 R5C11D.Q0 to R4C10C.C1 CmdEnable -CTOF_DEL --- 0.101 R4C10C.C1 to R4C10C.F1 SLICE_23 -ROUTE 2 0.058 R4C10C.F1 to R4C10C.C0 XOR8MEG18_i -CTOF_DEL --- 0.101 R4C10C.C0 to R4C10C.F0 SLICE_23 -ROUTE 1 0.000 R4C10C.F0 to R4C10C.DI0 N_36_fast (to PHI2_c) +REG_DEL --- 0.133 R4C9B.CLK to R4C9B.Q0 SLICE_17 (from PHI2_c) +ROUTE 2 0.277 R4C9B.Q0 to R5C9A.C1 CmdEnable +CTOF_DEL --- 0.101 R5C9A.C1 to R5C9A.F1 SLICE_23 +ROUTE 8 0.145 R5C9A.F1 to R5C9A.B0 XOR8MEG18 +CTOF_DEL --- 0.101 R5C9A.B0 to R5C9A.F0 SLICE_23 +ROUTE 1 0.000 R5C9A.F0 to R5C9A.DI0 N_34_fast (to PHI2_c) -------- - 0.619 (54.1% logic, 45.9% route), 3 logic levels. + 0.757 (44.3% logic, 55.7% route), 3 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_17: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R5C11D.CLK PHI2_c +ROUTE 21 1.423 8.PADDI to R4C9B.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_23: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R4C10C.CLK PHI2_c +ROUTE 21 1.423 8.PADDI to R5C9A.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 0.661ns +Passed: The following path meets requirements by 0.782ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q CmdEnable (from PHI2_c -) - Destination: FF Data in XOR8MEG (to PHI2_c -) + Source: FF Q CmdUFMWrite (from PHI2_c -) + Destination: FF Data in CmdUFMWrite (to PHI2_c -) - Delay: 0.633ns (37.0% logic, 63.0% route), 2 logic levels. + Delay: 0.769ns (43.6% logic, 56.4% route), 3 logic levels. Constraint Details: - 0.633ns physical path delay SLICE_17 to SLICE_45 meets - -0.028ns CE_HLD and + 0.769ns physical path delay SLICE_21 to SLICE_21 meets + -0.013ns DIN_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.028ns) by 0.661ns + 0.000ns skew requirement (totaling -0.013ns) by 0.782ns Physical Path Details: - Data path SLICE_17 to SLICE_45: + Data path SLICE_21 to SLICE_21: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C11D.CLK to R5C11D.Q0 SLICE_17 (from PHI2_c) -ROUTE 4 0.140 R5C11D.Q0 to R5C11C.D1 CmdEnable -CTOF_DEL --- 0.101 R5C11C.D1 to R5C11C.F1 SLICE_106 -ROUTE 5 0.259 R5C11C.F1 to R5C10D.CE XOR8MEG18 (to PHI2_c) +REG_DEL --- 0.133 R7C8D.CLK to R7C8D.Q0 SLICE_21 (from PHI2_c) +ROUTE 2 0.224 R7C8D.Q0 to R7C8D.B1 CmdUFMWrite +CTOF_DEL --- 0.101 R7C8D.B1 to R7C8D.F1 SLICE_21 +ROUTE 1 0.210 R7C8D.F1 to R7C8D.A0 N_415 +CTOF_DEL --- 0.101 R7C8D.A0 to R7C8D.F0 SLICE_21 +ROUTE 1 0.000 R7C8D.F0 to R7C8D.DI0 CmdUFMWrite_3 (to PHI2_c) -------- - 0.633 (37.0% logic, 63.0% route), 2 logic levels. + 0.769 (43.6% logic, 56.4% route), 3 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_17: + Source Clock Path PHI2 to SLICE_21: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R5C11D.CLK PHI2_c +ROUTE 21 1.423 8.PADDI to R7C8D.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_45: + Destination Clock Path PHI2 to SLICE_21: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R5C10D.CLK PHI2_c +ROUTE 21 1.423 8.PADDI to R7C8D.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. @@ -1691,7 +1689,7 @@ Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ; ================================================================================ Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; - 868 items scored, 0 timing errors detected. + 891 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- @@ -1716,8 +1714,8 @@ Passed: The following path meets requirements by 0.304ns Data path SLICE_12 to SLICE_12: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C12B.CLK to R5C12B.Q0 SLICE_12 (from RCLK_c) -ROUTE 1 0.152 R5C12B.Q0 to R5C12B.M1 CASr (to RCLK_c) +REG_DEL --- 0.133 R5C10B.CLK to R5C10B.Q0 SLICE_12 (from RCLK_c) +ROUTE 1 0.152 R5C10B.Q0 to R5C10B.M1 CASr (to RCLK_c) -------- 0.285 (46.7% logic, 53.3% route), 1 logic levels. @@ -1726,57 +1724,14 @@ ROUTE 1 0.152 R5C12B.Q0 to R5C12B.M1 CASr (to RCLK_c) Source Clock Path RCLK to SLICE_12: Name Fanout Delay (ns) Site Resource -ROUTE 48 0.788 63.PADDI to R5C12B.CLK RCLK_c +ROUTE 48 0.788 63.PADDI to R5C10B.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_12: Name Fanout Delay (ns) Site Resource -ROUTE 48 0.788 63.PADDI to R5C12B.CLK RCLK_c - -------- - 0.788 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.306ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CASr2 (from RCLK_c +) - Destination: FF Data in CASr3 (to RCLK_c +) - - Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. - - Constraint Details: - - 0.287ns physical path delay SLICE_12 to SLICE_76 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.306ns - - Physical Path Details: - - Data path SLICE_12 to SLICE_76: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C12B.CLK to R5C12B.Q1 SLICE_12 (from RCLK_c) -ROUTE 4 0.154 R5C12B.Q1 to R5C12D.M0 CASr2 (to RCLK_c) - -------- - 0.287 (46.3% logic, 53.7% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_12: - - Name Fanout Delay (ns) Site Resource -ROUTE 48 0.788 63.PADDI to R5C12B.CLK RCLK_c - -------- - 0.788 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_76: - - Name Fanout Delay (ns) Site Resource -ROUTE 48 0.788 63.PADDI to R5C12D.CLK RCLK_c +ROUTE 48 0.788 63.PADDI to R5C10B.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. @@ -1792,113 +1747,113 @@ Passed: The following path meets requirements by 0.306ns Constraint Details: - 0.287ns physical path delay SLICE_33 to SLICE_33 meets + 0.287ns physical path delay SLICE_32 to SLICE_32 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns - Physical Path Details: - - Data path SLICE_33 to SLICE_33: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R7C10D.CLK to R7C10D.Q0 SLICE_33 (from RCLK_c) -ROUTE 2 0.154 R7C10D.Q0 to R7C10D.M1 RASr (to RCLK_c) - -------- - 0.287 (46.3% logic, 53.7% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_33: - - Name Fanout Delay (ns) Site Resource -ROUTE 48 0.788 63.PADDI to R7C10D.CLK RCLK_c - -------- - 0.788 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_33: - - Name Fanout Delay (ns) Site Resource -ROUTE 48 0.788 63.PADDI to R7C10D.CLK RCLK_c - -------- - 0.788 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.311ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q PHI2r2 (from RCLK_c +) - Destination: FF Data in PHI2r3 (to RCLK_c +) - - Delay: 0.292ns (45.5% logic, 54.5% route), 1 logic levels. - - Constraint Details: - - 0.292ns physical path delay SLICE_32 to SLICE_32 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.311ns - Physical Path Details: Data path SLICE_32 to SLICE_32: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C9D.CLK to R3C9D.Q0 SLICE_32 (from RCLK_c) -ROUTE 5 0.159 R3C9D.Q0 to R3C9D.M1 PHI2r2 (to RCLK_c) +REG_DEL --- 0.133 R4C12C.CLK to R4C12C.Q0 SLICE_32 (from RCLK_c) +ROUTE 2 0.154 R4C12C.Q0 to R4C12C.M1 RASr (to RCLK_c) -------- - 0.292 (45.5% logic, 54.5% route), 1 logic levels. + 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_32: Name Fanout Delay (ns) Site Resource -ROUTE 48 0.788 63.PADDI to R3C9D.CLK RCLK_c +ROUTE 48 0.788 63.PADDI to R4C12C.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_32: Name Fanout Delay (ns) Site Resource -ROUTE 48 0.788 63.PADDI to R3C9D.CLK RCLK_c +ROUTE 48 0.788 63.PADDI to R4C12C.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 0.347ns +Passed: The following path meets requirements by 0.322ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q wb_dati[3] (from RCLK_c +) - Destination: EFB Port ufmefb/EFBInst_0(ASIC) (to RCLK_c +) + Source: FF Q PHI2r2 (from RCLK_c +) + Destination: FF Data in PHI2r3 (to RCLK_c +) - Delay: 0.306ns (43.5% logic, 56.5% route), 1 logic levels. + Delay: 0.303ns (43.9% logic, 56.1% route), 1 logic levels. Constraint Details: - 0.306ns physical path delay SLICE_54 to ufmefb/EFBInst_0 meets - -0.095ns WBDATI_HLD and + 0.303ns physical path delay SLICE_31 to SLICE_31 meets + -0.019ns M_HLD and 0.000ns delay constraint less - -0.054ns skew requirement (totaling -0.041ns) by 0.347ns + 0.000ns skew requirement (totaling -0.019ns) by 0.322ns Physical Path Details: - Data path SLICE_54 to ufmefb/EFBInst_0: + Data path SLICE_31 to SLICE_31: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R2C6D.CLK to R2C6D.Q1 SLICE_54 (from RCLK_c) -ROUTE 2 0.173 R2C6D.Q1 to EFB.WBDATI3 wb_dati[3] (to RCLK_c) +REG_DEL --- 0.133 R5C8B.CLK to R5C8B.Q0 SLICE_31 (from RCLK_c) +ROUTE 5 0.170 R5C8B.Q0 to R5C8B.M1 PHI2r2 (to RCLK_c) -------- - 0.306 (43.5% logic, 56.5% route), 1 logic levels. + 0.303 (43.9% logic, 56.1% route), 1 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_54: + Source Clock Path RCLK to SLICE_31: Name Fanout Delay (ns) Site Resource -ROUTE 48 0.788 63.PADDI to R2C6D.CLK RCLK_c +ROUTE 48 0.788 63.PADDI to R5C8B.CLK RCLK_c + -------- + 0.788 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_31: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 0.788 63.PADDI to R5C8B.CLK RCLK_c + -------- + 0.788 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.326ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q wb_dati[7] (from RCLK_c +) + Destination: EFB Port ufmefb/EFBInst_0(ASIC) (to RCLK_c +) + + Delay: 0.307ns (43.3% logic, 56.7% route), 1 logic levels. + + Constraint Details: + + 0.307ns physical path delay SLICE_55 to ufmefb/EFBInst_0 meets + -0.073ns WBDATI_HLD and + 0.000ns delay constraint less + -0.054ns skew requirement (totaling -0.019ns) by 0.326ns + + Physical Path Details: + + Data path SLICE_55 to ufmefb/EFBInst_0: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R3C6C.CLK to R3C6C.Q1 SLICE_55 (from RCLK_c) +ROUTE 2 0.174 R3C6C.Q1 to EFB.WBDATI7 wb_dati[7] (to RCLK_c) + -------- + 0.307 (43.3% logic, 56.7% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_55: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 0.788 63.PADDI to R3C6C.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. @@ -1931,10 +1886,10 @@ Passed: The following path meets requirements by 0.379ns Data path SLICE_0 to SLICE_0: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C4A.CLK to R5C4A.Q1 SLICE_0 (from RCLK_c) -ROUTE 3 0.132 R5C4A.Q1 to R5C4A.A1 FS[0] -CTOF_DEL --- 0.101 R5C4A.A1 to R5C4A.F1 SLICE_0 -ROUTE 1 0.000 R5C4A.F1 to R5C4A.DI1 FS_s[0] (to RCLK_c) +REG_DEL --- 0.133 R2C7A.CLK to R2C7A.Q1 SLICE_0 (from RCLK_c) +ROUTE 3 0.132 R2C7A.Q1 to R2C7A.A1 FS[0] +CTOF_DEL --- 0.101 R2C7A.A1 to R2C7A.F1 SLICE_0 +ROUTE 1 0.000 R2C7A.F1 to R2C7A.DI1 FS_s[0] (to RCLK_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. @@ -1943,14 +1898,14 @@ ROUTE 1 0.000 R5C4A.F1 to R5C4A.DI1 FS_s[0] (to RCLK_c) Source Clock Path RCLK to SLICE_0: Name Fanout Delay (ns) Site Resource -ROUTE 48 0.788 63.PADDI to R5C4A.CLK RCLK_c +ROUTE 48 0.788 63.PADDI to R2C7A.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_0: Name Fanout Delay (ns) Site Resource -ROUTE 48 0.788 63.PADDI to R5C4A.CLK RCLK_c +ROUTE 48 0.788 63.PADDI to R2C7A.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. @@ -1976,10 +1931,10 @@ Passed: The following path meets requirements by 0.379ns Data path SLICE_1 to SLICE_1: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C6B.CLK to R5C6B.Q0 SLICE_1 (from RCLK_c) -ROUTE 5 0.132 R5C6B.Q0 to R5C6B.A0 FS[17] -CTOF_DEL --- 0.101 R5C6B.A0 to R5C6B.F0 SLICE_1 -ROUTE 1 0.000 R5C6B.F0 to R5C6B.DI0 FS_s[17] (to RCLK_c) +REG_DEL --- 0.133 R2C9B.CLK to R2C9B.Q0 SLICE_1 (from RCLK_c) +ROUTE 7 0.132 R2C9B.Q0 to R2C9B.A0 FS[17] +CTOF_DEL --- 0.101 R2C9B.A0 to R2C9B.F0 SLICE_1 +ROUTE 1 0.000 R2C9B.F0 to R2C9B.DI0 FS_s[17] (to RCLK_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. @@ -1988,14 +1943,14 @@ ROUTE 1 0.000 R5C6B.F0 to R5C6B.DI0 FS_s[17] (to RCLK_c) Source Clock Path RCLK to SLICE_1: Name Fanout Delay (ns) Site Resource -ROUTE 48 0.788 63.PADDI to R5C6B.CLK RCLK_c +ROUTE 48 0.788 63.PADDI to R2C9B.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_1: Name Fanout Delay (ns) Site Resource -ROUTE 48 0.788 63.PADDI to R5C6B.CLK RCLK_c +ROUTE 48 0.788 63.PADDI to R2C9B.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. @@ -2021,10 +1976,10 @@ Passed: The following path meets requirements by 0.379ns Data path SLICE_2 to SLICE_2: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C6A.CLK to R5C6A.Q0 SLICE_2 (from RCLK_c) -ROUTE 4 0.132 R5C6A.Q0 to R5C6A.A0 FS[15] -CTOF_DEL --- 0.101 R5C6A.A0 to R5C6A.F0 SLICE_2 -ROUTE 1 0.000 R5C6A.F0 to R5C6A.DI0 FS_s[15] (to RCLK_c) +REG_DEL --- 0.133 R2C9A.CLK to R2C9A.Q0 SLICE_2 (from RCLK_c) +ROUTE 6 0.132 R2C9A.Q0 to R2C9A.A0 FS[15] +CTOF_DEL --- 0.101 R2C9A.A0 to R2C9A.F0 SLICE_2 +ROUTE 1 0.000 R2C9A.F0 to R2C9A.DI0 FS_s[15] (to RCLK_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. @@ -2033,14 +1988,14 @@ ROUTE 1 0.000 R5C6A.F0 to R5C6A.DI0 FS_s[15] (to RCLK_c) Source Clock Path RCLK to SLICE_2: Name Fanout Delay (ns) Site Resource -ROUTE 48 0.788 63.PADDI to R5C6A.CLK RCLK_c +ROUTE 48 0.788 63.PADDI to R2C9A.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_2: Name Fanout Delay (ns) Site Resource -ROUTE 48 0.788 63.PADDI to R5C6A.CLK RCLK_c +ROUTE 48 0.788 63.PADDI to R2C9A.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. @@ -2049,43 +2004,43 @@ Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS[16] (from RCLK_c +) - Destination: FF Data in FS[16] (to RCLK_c +) + Source: FF Q FS[14] (from RCLK_c +) + Destination: FF Data in FS[14] (to RCLK_c +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: - 0.366ns physical path delay SLICE_2 to SLICE_2 meets + 0.366ns physical path delay SLICE_3 to SLICE_3 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: - Data path SLICE_2 to SLICE_2: + Data path SLICE_3 to SLICE_3: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C6A.CLK to R5C6A.Q1 SLICE_2 (from RCLK_c) -ROUTE 5 0.132 R5C6A.Q1 to R5C6A.A1 FS[16] -CTOF_DEL --- 0.101 R5C6A.A1 to R5C6A.F1 SLICE_2 -ROUTE 1 0.000 R5C6A.F1 to R5C6A.DI1 FS_s[16] (to RCLK_c) +REG_DEL --- 0.133 R2C8D.CLK to R2C8D.Q1 SLICE_3 (from RCLK_c) +ROUTE 19 0.132 R2C8D.Q1 to R2C8D.A1 FS[14] +CTOF_DEL --- 0.101 R2C8D.A1 to R2C8D.F1 SLICE_3 +ROUTE 1 0.000 R2C8D.F1 to R2C8D.DI1 FS_s[14] (to RCLK_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_2: + Source Clock Path RCLK to SLICE_3: Name Fanout Delay (ns) Site Resource -ROUTE 48 0.788 63.PADDI to R5C6A.CLK RCLK_c +ROUTE 48 0.788 63.PADDI to R2C8D.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_2: + Destination Clock Path RCLK to SLICE_3: Name Fanout Delay (ns) Site Resource -ROUTE 48 0.788 63.PADDI to R5C6A.CLK RCLK_c +ROUTE 48 0.788 63.PADDI to R2C8D.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. @@ -2094,43 +2049,88 @@ Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS[12] (from RCLK_c +) - Destination: FF Data in FS[12] (to RCLK_c +) + Source: FF Q LEDEN (from RCLK_c +) + Destination: FF Data in LEDEN (to RCLK_c +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: - 0.366ns physical path delay SLICE_4 to SLICE_4 meets + 0.366ns physical path delay SLICE_30 to SLICE_30 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: - Data path SLICE_4 to SLICE_4: + Data path SLICE_30 to SLICE_30: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C5C.CLK to R5C5C.Q1 SLICE_4 (from RCLK_c) -ROUTE 23 0.132 R5C5C.Q1 to R5C5C.A1 FS[12] -CTOF_DEL --- 0.101 R5C5C.A1 to R5C5C.F1 SLICE_4 -ROUTE 1 0.000 R5C5C.F1 to R5C5C.DI1 FS_s[12] (to RCLK_c) +REG_DEL --- 0.133 R7C5A.CLK to R7C5A.Q0 SLICE_30 (from RCLK_c) +ROUTE 4 0.132 R7C5A.Q0 to R7C5A.A0 LEDEN +CTOF_DEL --- 0.101 R7C5A.A0 to R7C5A.F0 SLICE_30 +ROUTE 1 0.000 R7C5A.F0 to R7C5A.DI0 LEDENe_0 (to RCLK_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_4: + Source Clock Path RCLK to SLICE_30: Name Fanout Delay (ns) Site Resource -ROUTE 48 0.788 63.PADDI to R5C5C.CLK RCLK_c +ROUTE 48 0.788 63.PADDI to R7C5A.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_4: + Destination Clock Path RCLK to SLICE_30: Name Fanout Delay (ns) Site Resource -ROUTE 48 0.788 63.PADDI to R5C5C.CLK RCLK_c +ROUTE 48 0.788 63.PADDI to R7C5A.CLK RCLK_c + -------- + 0.788 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.379ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q n8MEGEN (from RCLK_c +) + Destination: FF Data in n8MEGEN (to RCLK_c +) + + Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. + + Constraint Details: + + 0.366ns physical path delay SLICE_45 to SLICE_45 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.379ns + + Physical Path Details: + + Data path SLICE_45 to SLICE_45: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C5B.CLK to R5C5B.Q0 SLICE_45 (from RCLK_c) +ROUTE 3 0.132 R5C5B.Q0 to R5C5B.A0 n8MEGEN +CTOF_DEL --- 0.101 R5C5B.A0 to R5C5B.F0 SLICE_45 +ROUTE 1 0.000 R5C5B.F0 to R5C5B.DI0 n8MEGENe_0 (to RCLK_c) + -------- + 0.366 (63.9% logic, 36.1% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_45: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 0.788 63.PADDI to R5C5B.CLK RCLK_c + -------- + 0.788 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_45: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 0.788 63.PADDI to R5C5B.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. @@ -2159,7 +2159,7 @@ Clock Domains Analysis Found 4 clocks: -Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12 +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11 No transfer within this clock domain is found Data transfers from: @@ -2201,7 +2201,7 @@ Timing summary (Hold): Timing errors: 0 Score: 0 Cumulative negative slack: 0 -Constraints cover 1015 paths, 4 nets, and 725 connections (73.01% coverage) +Constraints cover 1038 paths, 4 nets, and 750 connections (74.18% coverage) diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_bgn.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_bgn.html index 965acf4..27c952f 100644 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_bgn.html +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_bgn.html @@ -12,7 +12,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Thu Oct 19 23:51:23 2023 +Sat Nov 18 02:06:29 2023 Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC -w -jedec -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf @@ -92,8 +92,8 @@ Available General Purpose Flash Memory: 511 Pages (Page 0 to Page 510). Initialized UFM Pages: 321 Pages (Page 190 to Page 510). Total CPU Time: 3 secs -Total REAL Time: 4 secs -Peak Memory Usage: 275 MB +Total REAL Time: 3 secs +Peak Memory Usage: 274 MB diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_cck.rpt b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_cck.rpt index 31621ea..3c03689 100644 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_cck.rpt +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_cck.rpt @@ -13,7 +13,7 @@ Hostname: ZANEMACWIN11 Implementation : impl1 -# Written on Thu Oct 19 23:50:50 2023 +# Written on Sat Nov 18 02:05:44 2023 ##### DESIGN INFO ####################################################### diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_iotiming.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_iotiming.html index 6488645..f5c383f 100644 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_iotiming.html +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_iotiming.html @@ -38,7 +38,7 @@ Performance Hardware Data Status: Final Version 34.4. // Package: TQFP100 // ncd File: ram2gs_lcmxo2_1200hc_impl1.ncd // Version: Diamond (64-bit) 3.12.1.454 -// Written on Thu Oct 19 23:51:14 2023 +// Written on Sat Nov 18 02:06:17 2023 // M: Minimum Performance Grade // iotiming RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml @@ -50,99 +50,97 @@ Worst Case Results across Performance Grades (M, 6, 5, 4): Port Clock Edge Setup Performance_Grade Hold Performance_Grade ---------------------------------------------------------------------- -CROW[0] nCRAS F 1.569 4 0.268 6 -CROW[1] nCRAS F 1.013 4 0.820 4 -Din[0] PHI2 F 5.478 4 4.293 4 -Din[0] nCCAS F 2.010 4 -0.119 M -Din[1] PHI2 F 4.088 4 4.173 4 -Din[1] nCCAS F 0.601 4 0.796 4 -Din[2] PHI2 F 4.967 4 4.173 4 -Din[2] nCCAS F 0.811 4 0.583 4 -Din[3] PHI2 F 3.810 4 4.173 4 -Din[3] nCCAS F 1.136 4 0.322 4 -Din[4] PHI2 F 4.400 4 4.173 4 -Din[4] nCCAS F 0.762 4 0.590 4 -Din[5] PHI2 F 5.595 4 4.173 4 -Din[5] nCCAS F 0.779 4 0.576 4 -Din[6] PHI2 F 5.120 4 4.293 4 -Din[6] nCCAS F 2.036 4 -0.117 M -Din[7] PHI2 F 5.630 4 4.293 4 -Din[7] nCCAS F 2.301 4 -0.192 M -MAin[0] PHI2 F 4.196 4 1.086 4 -MAin[0] nCRAS F 0.152 6 1.567 4 -MAin[1] PHI2 F 3.875 4 1.164 4 -MAin[1] nCRAS F -0.177 M 2.102 4 -MAin[2] PHI2 F 8.381 4 -0.693 M -MAin[2] nCRAS F -0.315 M 2.358 4 -MAin[3] PHI2 F 7.199 4 -0.405 M -MAin[3] nCRAS F -0.173 M 1.962 4 -MAin[4] PHI2 F 8.710 4 -0.769 M -MAin[4] nCRAS F 0.292 4 1.419 4 -MAin[5] PHI2 F 8.562 4 -0.730 M -MAin[5] nCRAS F -0.055 M 1.752 4 -MAin[6] PHI2 F 7.862 4 -0.604 M -MAin[6] nCRAS F -0.126 M 1.965 4 -MAin[7] PHI2 F 8.829 4 -0.836 M -MAin[7] nCRAS F -0.122 M 1.960 4 -MAin[8] nCRAS F -0.288 M 2.424 4 -MAin[9] nCRAS F -0.212 M 2.196 4 +CROW[0] nCRAS F 3.288 4 -0.390 M +CROW[1] nCRAS F 2.823 4 -0.285 M +Din[0] PHI2 F 6.398 4 4.293 4 +Din[0] nCCAS F 1.411 4 -0.004 M +Din[1] PHI2 F 3.916 4 4.173 4 +Din[1] nCCAS F 1.877 4 -0.123 M +Din[2] PHI2 F 6.180 4 4.173 4 +Din[2] nCCAS F 1.548 4 -0.062 M +Din[3] PHI2 F 5.536 4 4.173 4 +Din[3] nCCAS F 0.467 4 0.734 4 +Din[4] PHI2 F 3.611 4 4.173 4 +Din[4] nCCAS F 1.533 4 -0.043 M +Din[5] PHI2 F 5.673 4 4.173 4 +Din[5] nCCAS F 1.663 4 -0.072 M +Din[6] PHI2 F 5.355 4 4.293 4 +Din[6] nCCAS F 2.807 4 -0.352 M +Din[7] PHI2 F 5.296 4 4.293 4 +Din[7] nCCAS F 1.914 4 -0.136 M +MAin[0] PHI2 F 4.091 4 1.414 4 +MAin[0] nCRAS F 1.207 4 0.347 4 +MAin[1] PHI2 F 3.273 4 1.759 4 +MAin[1] nCRAS F 1.077 4 0.460 4 +MAin[2] PHI2 F 8.126 4 -0.351 M +MAin[2] nCRAS F 0.671 4 0.850 4 +MAin[3] PHI2 F 8.831 4 -0.579 M +MAin[3] nCRAS F 1.100 4 0.463 4 +MAin[4] PHI2 F 8.415 4 -0.447 M +MAin[4] nCRAS F 1.390 4 0.207 4 +MAin[5] PHI2 F 9.742 4 -0.803 M +MAin[5] nCRAS F 1.269 4 0.218 4 +MAin[6] PHI2 F 7.970 4 -0.325 M +MAin[6] nCRAS F 1.165 4 0.337 4 +MAin[7] PHI2 F 8.481 4 -0.438 M +MAin[7] nCRAS F 0.761 4 0.673 4 +MAin[8] nCRAS F 1.261 4 0.223 4 +MAin[9] nCRAS F 0.756 4 0.667 4 PHI2 RCLK R -0.133 M 2.360 4 -nCCAS RCLK R 3.627 4 -0.577 M -nCCAS nCRAS F 3.154 4 -0.145 M -nCRAS RCLK R 1.461 4 -0.017 M -nFWE PHI2 F 6.933 4 -0.318 M -nFWE nCRAS F 0.403 4 1.860 4 +nCCAS RCLK R 4.128 4 -0.675 M +nCCAS nCRAS F 4.568 4 -0.666 M +nCRAS RCLK R 3.070 4 -0.412 M +nFWE PHI2 F 8.979 4 -0.603 M +nFWE nCRAS F 1.467 4 0.144 4 // Clock to Output Delay Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade ------------------------------------------------------------------------ -LED RCLK R 10.948 4 3.270 M -LED nCRAS F 12.507 4 3.690 M -RA[0] RCLK R 13.208 4 4.000 M -RA[0] nCRAS F 13.040 4 3.935 M +LED RCLK R 11.034 4 3.119 M +LED nCRAS F 11.531 4 3.339 M +RA[0] RCLK R 11.682 4 3.586 M +RA[0] nCRAS F 11.704 4 3.483 M RA[10] RCLK R 7.888 4 2.711 M RA[11] PHI2 R 9.755 4 3.200 M -RA[1] RCLK R 13.332 4 4.024 M -RA[1] nCRAS F 12.944 4 3.885 M -RA[2] RCLK R 13.624 4 4.099 M -RA[2] nCRAS F 13.220 4 3.993 M -RA[3] RCLK R 13.506 4 4.055 M -RA[3] nCRAS F 13.322 4 4.022 M -RA[4] RCLK R 12.512 4 3.834 M -RA[4] nCRAS F 14.534 4 4.331 M -RA[5] RCLK R 13.530 4 4.069 M -RA[5] nCRAS F 13.126 4 3.963 M -RA[6] RCLK R 14.238 4 4.245 M -RA[6] nCRAS F 13.589 4 4.077 M -RA[7] RCLK R 13.759 4 4.129 M -RA[7] nCRAS F 13.371 4 3.990 M -RA[8] RCLK R 11.858 4 3.632 M -RA[8] nCRAS F 13.338 4 4.026 M -RA[9] RCLK R 11.007 4 3.423 M -RA[9] nCRAS F 12.651 4 3.856 M -RBA[0] nCRAS F 10.201 4 3.325 M -RBA[1] nCRAS F 10.201 4 3.325 M -RCKE RCLK R 9.754 4 3.167 M -RCLKout RCLK R 7.971 4 2.504 M -RDQMH RCLK R 11.153 4 3.458 M -RDQML RCLK R 11.133 4 3.466 M -RD[0] nCCAS F 9.354 4 3.132 M -RD[1] nCCAS F 9.354 4 3.132 M -RD[2] nCCAS F 9.354 4 3.132 M -RD[3] nCCAS F 9.354 4 3.132 M -RD[4] nCCAS F 9.354 4 3.132 M -RD[5] nCCAS F 9.354 4 3.132 M -RD[6] nCCAS F 9.354 4 3.132 M -RD[7] nCCAS F 9.354 4 3.132 M +RA[1] RCLK R 11.454 4 3.535 M +RA[1] nCRAS F 11.216 4 3.347 M +RA[2] RCLK R 12.084 4 3.693 M +RA[2] nCRAS F 11.742 4 3.501 M +RA[3] RCLK R 12.131 4 3.715 M +RA[3] nCRAS F 11.857 4 3.533 M +RA[4] RCLK R 11.966 4 3.684 M +RA[4] nCRAS F 12.319 4 3.650 M +RA[5] RCLK R 11.928 4 3.670 M +RA[5] nCRAS F 11.637 4 3.446 M +RA[6] RCLK R 11.419 4 3.523 M +RA[6] nCRAS F 11.718 4 3.486 M +RA[7] RCLK R 11.988 4 3.651 M +RA[7] nCRAS F 12.274 4 3.636 M +RA[8] RCLK R 11.660 4 3.582 M +RA[8] nCRAS F 11.098 4 3.343 M +RA[9] RCLK R 11.454 4 3.547 M +RA[9] nCRAS F 11.134 4 3.314 M +RBA[0] nCRAS F 8.903 4 2.891 M +RBA[1] nCRAS F 8.883 4 2.898 M +RCKE RCLK R 9.774 4 3.159 M +RCLKout RCLK R 7.101 4 2.108 M +RDQMH RCLK R 10.733 4 3.351 M +RDQML RCLK R 10.683 4 3.364 M +RD[0] nCCAS F 8.977 4 3.012 M +RD[1] nCCAS F 8.977 4 3.012 M +RD[2] nCCAS F 8.977 4 3.012 M +RD[3] nCCAS F 8.977 4 3.012 M +RD[4] nCCAS F 8.977 4 3.012 M +RD[5] nCCAS F 8.977 4 3.012 M +RD[6] nCCAS F 8.977 4 3.012 M +RD[7] nCCAS F 8.977 4 3.012 M nRCAS RCLK R 7.822 4 2.706 M nRCS RCLK R 7.822 4 2.706 M nRRAS RCLK R 7.822 4 2.706 M nRWE RCLK R 7.803 4 2.713 M WARNING: you must also run trce with hold speed: 4 -WARNING: you must also run trce with setup speed: 6 -WARNING: you must also run trce with hold speed: 6 WARNING: you must also run trce with setup speed: M diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.sdf b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.sdf index 45d3fd0..c7d445b 100644 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.sdf +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.sdf @@ -1,7 +1,7 @@ (DELAYFILE (SDFVERSION "3.0") (DESIGN "RAM2GS") - (DATE "Thu Oct 19 23:50:59 2023") + (DATE "Sat Nov 18 02:05:56 2023") (VENDOR "Lattice") (PROGRAM "ldbanno") (VERSION "Diamond (64-bit) 3.12.1.454") @@ -397,6 +397,7 @@ (INSTANCE SLICE_19) (DELAY (ABSOLUTE + (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) ) ) @@ -414,10 +415,6 @@ (INSTANCE SLICE_20) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) @@ -549,26 +546,8 @@ (INSTANCE SLICE_26) (DELAY (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) - ) - ) - (CELL - (CELLTYPE "SLICE_27") - (INSTANCE SLICE_27) - (DELAY - (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) @@ -586,8 +565,8 @@ ) ) (CELL - (CELLTYPE "SLICE_28") - (INSTANCE SLICE_28) + (CELLTYPE "SLICE_27") + (INSTANCE SLICE_27) (DELAY (ABSOLUTE (IOPATH C1 F1 (367:431:495)(367:431:495)) @@ -610,10 +589,11 @@ ) ) (CELL - (CELLTYPE "SLICE_29") - (INSTANCE SLICE_29) + (CELLTYPE "SLICE_28") + (INSTANCE SLICE_28) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) @@ -634,8 +614,8 @@ ) ) (CELL - (CELLTYPE "SLICE_30") - (INSTANCE SLICE_30) + (CELLTYPE "SLICE_29") + (INSTANCE SLICE_29) (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) @@ -656,8 +636,8 @@ ) ) (CELL - (CELLTYPE "SLICE_31") - (INSTANCE SLICE_31) + (CELLTYPE "SLICE_30") + (INSTANCE SLICE_30) (DELAY (ABSOLUTE (IOPATH C1 F1 (367:431:495)(367:431:495)) @@ -678,15 +658,10 @@ ) ) (CELL - (CELLTYPE "SLICE_32") - (INSTANCE SLICE_32) + (CELLTYPE "SLICE_31") + (INSTANCE SLICE_31) (DELAY (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) @@ -703,8 +678,8 @@ ) ) (CELL - (CELLTYPE "SLICE_33") - (INSTANCE SLICE_33) + (CELLTYPE "SLICE_32") + (INSTANCE SLICE_32) (DELAY (ABSOLUTE (IOPATH C1 F1 (367:431:495)(367:431:495)) @@ -724,6 +699,27 @@ (WIDTH (negedge CLK) (1250:1250:1250)) ) ) + (CELL + (CELLTYPE "SLICE_33") + (INSTANCE SLICE_33) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) (CELL (CELLTYPE "SLICE_34") (INSTANCE SLICE_34) @@ -741,7 +737,7 @@ ) ) (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) ) (TIMINGCHECK (WIDTH (posedge CLK) (1250:1250:1250)) @@ -753,8 +749,6 @@ (INSTANCE SLICE_35) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) @@ -777,6 +771,7 @@ (INSTANCE SLICE_36) (DELAY (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) @@ -799,11 +794,10 @@ (INSTANCE SLICE_37) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) @@ -822,22 +816,22 @@ (INSTANCE SLICE_38) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) ) ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - ) (TIMINGCHECK (WIDTH (posedge CLK) (1250:1250:1250)) (WIDTH (negedge CLK) (1250:1250:1250)) ) + (TIMINGCHECK + (SETUPHOLD DI1 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + ) ) (CELL (CELLTYPE "SLICE_39") @@ -930,28 +924,6 @@ (CELL (CELLTYPE "SLICE_43") (INSTANCE SLICE_43) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (negedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) - ) - ) - (CELL - (CELLTYPE "SLICE_44") - (INSTANCE SLICE_44) (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) @@ -975,8 +947,8 @@ ) ) (CELL - (CELLTYPE "SLICE_45") - (INSTANCE SLICE_45) + (CELLTYPE "SLICE_44") + (INSTANCE SLICE_44) (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) @@ -1000,8 +972,8 @@ ) ) (CELL - (CELLTYPE "SLICE_46") - (INSTANCE SLICE_46) + (CELLTYPE "SLICE_45") + (INSTANCE SLICE_45) (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) @@ -1023,12 +995,10 @@ ) ) (CELL - (CELLTYPE "SLICE_47") - (INSTANCE SLICE_47) + (CELLTYPE "SLICE_46") + (INSTANCE SLICE_46) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) @@ -1050,8 +1020,8 @@ ) ) (CELL - (CELLTYPE "SLICE_48") - (INSTANCE SLICE_48) + (CELLTYPE "SLICE_47") + (INSTANCE SLICE_47) (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) @@ -1077,8 +1047,8 @@ ) ) (CELL - (CELLTYPE "SLICE_49") - (INSTANCE SLICE_49) + (CELLTYPE "SLICE_48") + (INSTANCE SLICE_48) (DELAY (ABSOLUTE (IOPATH B1 F1 (367:431:495)(367:431:495)) @@ -1099,12 +1069,36 @@ (WIDTH (negedge CLK) (1250:1250:1250)) ) ) + (CELL + (CELLTYPE "SLICE_49") + (INSTANCE SLICE_49) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) (CELL (CELLTYPE "SLICE_50") (INSTANCE SLICE_50) (DELAY (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) @@ -1127,30 +1121,6 @@ (CELL (CELLTYPE "SLICE_51") (INSTANCE SLICE_51) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "SLICE_52") - (INSTANCE SLICE_52) (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) @@ -1177,8 +1147,8 @@ ) ) (CELL - (CELLTYPE "SLICE_53") - (INSTANCE SLICE_53) + (CELLTYPE "SLICE_52") + (INSTANCE SLICE_52) (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) @@ -1203,12 +1173,37 @@ (WIDTH (negedge CLK) (1250:1250:1250)) ) ) + (CELL + (CELLTYPE "SLICE_53") + (INSTANCE SLICE_53) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) (CELL (CELLTYPE "SLICE_54") (INSTANCE SLICE_54) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) @@ -1239,6 +1234,7 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -1265,20 +1261,19 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) ) ) (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) ) (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) (WIDTH (posedge CLK) (1250:1250:1250)) (WIDTH (negedge CLK) (1250:1250:1250)) ) @@ -1300,11 +1295,8 @@ ) (TIMINGCHECK (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) ) (TIMINGCHECK - (WIDTH (posedge LSR) (4000:4000:4000)) - (WIDTH (negedge LSR) (4000:4000:4000)) (WIDTH (posedge CLK) (1250:1250:1250)) (WIDTH (negedge CLK) (1250:1250:1250)) ) @@ -1314,31 +1306,6 @@ (INSTANCE SLICE_58) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "SLICE_59") - (INSTANCE SLICE_59) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) @@ -1362,18 +1329,35 @@ ) ) (CELL - (CELLTYPE "SLICE_60") - (INSTANCE SLICE_60) + (CELLTYPE "wb_dati_5_1_iv_0_0_o2_5__SLICE_59") + (INSTANCE wb_dati_5_1_iv_0_0_o2\[5\]\/SLICE_59) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH D1 OFX0 (457:589:721)(457:589:721)) + (IOPATH C1 OFX0 (457:589:721)(457:589:721)) + (IOPATH B1 OFX0 (457:589:721)(457:589:721)) + (IOPATH A1 OFX0 (457:589:721)(457:589:721)) + (IOPATH D0 OFX0 (457:589:721)(457:589:721)) + (IOPATH C0 OFX0 (457:589:721)(457:589:721)) + (IOPATH B0 OFX0 (457:589:721)(457:589:721)) + (IOPATH A0 OFX0 (457:589:721)(457:589:721)) + (IOPATH M0 OFX0 (322:349:376)(322:349:376)) + ) + ) + ) + (CELL + (CELLTYPE "wb_adr_5_i_0_1_0__SLICE_60") + (INSTANCE wb_adr_5_i_0_1\[0\]\/SLICE_60) + (DELAY + (ABSOLUTE + (IOPATH C1 OFX0 (457:589:721)(457:589:721)) + (IOPATH B1 OFX0 (457:589:721)(457:589:721)) + (IOPATH A1 OFX0 (457:589:721)(457:589:721)) + (IOPATH D0 OFX0 (457:589:721)(457:589:721)) + (IOPATH C0 OFX0 (457:589:721)(457:589:721)) + (IOPATH B0 OFX0 (457:589:721)(457:589:721)) + (IOPATH A0 OFX0 (457:589:721)(457:589:721)) + (IOPATH M0 OFX0 (322:349:376)(322:349:376)) ) ) ) @@ -1450,7 +1434,6 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -1465,7 +1448,6 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -1526,6 +1508,7 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -1537,7 +1520,6 @@ (INSTANCE SLICE_71) (DELAY (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) @@ -1552,7 +1534,6 @@ (INSTANCE SLICE_72) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) @@ -1568,7 +1549,6 @@ (INSTANCE SLICE_73) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) @@ -1576,18 +1556,8 @@ (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) ) ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) - (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) - ) ) (CELL (CELLTYPE "SLICE_74") @@ -1614,6 +1584,8 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) ) @@ -1624,6 +1596,7 @@ (INSTANCE SLICE_76) (DELAY (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) @@ -1631,6 +1604,30 @@ (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + ) + ) + (CELL + (CELLTYPE "SLICE_77") + (INSTANCE SLICE_77) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) ) ) (TIMINGCHECK @@ -1641,21 +1638,6 @@ (WIDTH (negedge CLK) (1250:1250:1250)) ) ) - (CELL - (CELLTYPE "SLICE_77") - (INSTANCE SLICE_77) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) (CELL (CELLTYPE "SLICE_78") (INSTANCE SLICE_78) @@ -1675,7 +1657,6 @@ (INSTANCE SLICE_79) (DELAY (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) @@ -1690,6 +1671,8 @@ (INSTANCE SLICE_80) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) @@ -1720,6 +1703,8 @@ (INSTANCE SLICE_82) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) @@ -1734,7 +1719,6 @@ (INSTANCE SLICE_83) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) @@ -1750,6 +1734,7 @@ (INSTANCE SLICE_84) (DELAY (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) @@ -1780,9 +1765,10 @@ (INSTANCE SLICE_86) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -1822,7 +1808,6 @@ (INSTANCE SLICE_89) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) @@ -1854,6 +1839,7 @@ (INSTANCE SLICE_91) (DELAY (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) @@ -1868,8 +1854,6 @@ (INSTANCE SLICE_92) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) @@ -1884,6 +1868,8 @@ (INSTANCE SLICE_93) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) @@ -1926,8 +1912,6 @@ (INSTANCE SLICE_96) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) @@ -1942,7 +1926,6 @@ (INSTANCE SLICE_97) (DELAY (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) @@ -1957,7 +1940,6 @@ (INSTANCE SLICE_98) (DELAY (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) @@ -1972,6 +1954,7 @@ (INSTANCE SLICE_99) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) @@ -1987,8 +1970,6 @@ (INSTANCE SLICE_100) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) @@ -2003,9 +1984,10 @@ (INSTANCE SLICE_101) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -2017,8 +1999,12 @@ (INSTANCE SLICE_102) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) ) @@ -2033,6 +2019,7 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -2048,6 +2035,7 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) ) @@ -2072,7 +2060,6 @@ (INSTANCE SLICE_106) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) @@ -2088,10 +2075,9 @@ (INSTANCE SLICE_107) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -2103,11 +2089,8 @@ (INSTANCE SLICE_108) (DELAY (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) ) @@ -2118,10 +2101,10 @@ (INSTANCE SLICE_109) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) ) @@ -2132,7 +2115,6 @@ (INSTANCE SLICE_110) (DELAY (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) @@ -2149,6 +2131,7 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -2188,6 +2171,8 @@ (INSTANCE SLICE_114) (DELAY (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) @@ -2200,9 +2185,9 @@ (INSTANCE SLICE_115) (DELAY (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -2214,8 +2199,10 @@ (INSTANCE SLICE_116) (DELAY (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) ) @@ -2224,6 +2211,71 @@ (CELL (CELLTYPE "SLICE_117") (INSTANCE SLICE_117) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_118") + (INSTANCE SLICE_118) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_119") + (INSTANCE SLICE_119) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_120") + (INSTANCE SLICE_120) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_121") + (INSTANCE SLICE_121) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_122") + (INSTANCE SLICE_122) (DELAY (ABSOLUTE (IOPATH C1 F1 (367:431:495)(367:431:495)) @@ -2411,7 +2463,7 @@ (INSTANCE RCLKout_I) (DELAY (ABSOLUTE - (IOPATH IOLDO RCLKout (2293:2420:2548)(2293:2420:2548)) + (IOPATH IOLDO RCLKout (1847:1987:2127)(1847:1987:2127)) ) ) ) @@ -3427,8 +3479,8 @@ (DELAY (ABSOLUTE (INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_0/Q1 SLICE_52/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_0/Q1 SLICE_87/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_89/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_121/A1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_0/F1 SLICE_0/DI1 (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_0/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_1/CLK (0:0:0)(0:0:0)) @@ -3442,6 +3494,7 @@ (INTERCONNECT RCLK_I/PADDI SLICE_9/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_12/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_16/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_26/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_27/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_28/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_29/CLK (0:0:0)(0:0:0)) @@ -3453,8 +3506,8 @@ (INTERCONNECT RCLK_I/PADDI SLICE_35/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_36/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_37/CLK (0:0:0)(0:0:0)) - (INTERCONNECT RCLK_I/PADDI SLICE_38/CLK (0:0:0)(0:0:0)) - (INTERCONNECT RCLK_I/PADDI SLICE_44/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_43/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_45/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_46/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_47/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_48/CLK (0:0:0)(0:0:0)) @@ -3468,8 +3521,7 @@ (INTERCONNECT RCLK_I/PADDI SLICE_56/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_57/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_58/CLK (0:0:0)(0:0:0)) - (INTERCONNECT RCLK_I/PADDI SLICE_59/CLK (0:0:0)(0:0:0)) - (INTERCONNECT RCLK_I/PADDI SLICE_76/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_77/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI PHI2_MGIOL/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI nRCAS_MGIOL/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI nRRAS_MGIOL/CLK (0:0:0)(0:0:0)) @@ -3481,201 +3533,205 @@ ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBCLKIin (0:0:0)(0:0:0)) (INTERCONNECT SLICE_0/FCO SLICE_9/FCI (0:0:0)(0:0:0)) (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q0 SLICE_58/C1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q0 SLICE_61/C1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q0 SLICE_103/D1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q0 SLICE_103/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_29/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_58/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_64/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_91/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_94/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_99/D0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_1/F0 SLICE_1/DI0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_2/FCO SLICE_1/FCI (0:0:0)(0:0:0)) (INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q1 SLICE_58/D1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q1 SLICE_61/D1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q1 SLICE_103/C1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q1 SLICE_103/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_29/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_58/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_64/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_91/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_94/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_99/C0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q0 SLICE_58/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q0 SLICE_61/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q0 SLICE_103/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_29/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_64/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_91/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_94/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_99/B0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_2/F1 SLICE_2/DI1 (0:0:0)(0:0:0)) (INTERCONNECT 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(0:0:0)(0:0:0)) + (INTERCONNECT SLICE_17/F1 SLICE_10/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_17/F1 SLICE_17/B0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_10/F1 SLICE_10/B0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_10/Q0 SLICE_10/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_10/Q0 SLICE_76/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_10/Q0 SLICE_33/A0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_10/F0 SLICE_10/DI0 (0:0:0)(0:0:0)) (INTERCONNECT PHI2_I/PADDI SLICE_10/CLK (0:0:0)(0:0:0)) (INTERCONNECT PHI2_I/PADDI SLICE_11/CLK (0:0:0)(0:0:0)) @@ -3687,7 +3743,7 @@ (INTERCONNECT PHI2_I/PADDI SLICE_22/CLK (0:0:0)(0:0:0)) (INTERCONNECT PHI2_I/PADDI SLICE_23/CLK (0:0:0)(0:0:0)) (INTERCONNECT PHI2_I/PADDI SLICE_24/CLK (0:0:0)(0:0:0)) - (INTERCONNECT PHI2_I/PADDI SLICE_45/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_44/CLK (0:0:0)(0:0:0)) (INTERCONNECT PHI2_I/PADDI PHI2_MGIOL/DI (0:0:0)(0:0:0)) (INTERCONNECT PHI2_I/PADDI RA\[11\]_MGIOL/CLK (0:0:0)(0:0:0)) (INTERCONNECT PHI2_I/PADDI Din\[7\]_MGIOL/CLK (0:0:0)(0:0:0)) @@ -3698,15 +3754,14 @@ (INTERCONNECT PHI2_I/PADDI Din\[2\]_MGIOL/CLK (0:0:0)(0:0:0)) (INTERCONNECT PHI2_I/PADDI Din\[1\]_MGIOL/CLK (0:0:0)(0:0:0)) (INTERCONNECT PHI2_I/PADDI Din\[0\]_MGIOL/CLK (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_20/F1 SLICE_11/C1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_20/F1 SLICE_64/C0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_20/F1 SLICE_73/C1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_20/F1 SLICE_76/B1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_64/F1 SLICE_11/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_64/F1 SLICE_64/D0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_64/F1 SLICE_76/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_109/F1 SLICE_11/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_109/F1 SLICE_17/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_109/F1 SLICE_63/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_109/F1 SLICE_76/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63/F1 SLICE_11/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63/F1 SLICE_63/D0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_11/Q0 SLICE_11/B0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_11/Q0 SLICE_17/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_11/Q0 SLICE_76/A0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_11/F0 SLICE_11/DI0 (0:0:0)(0:0:0)) (INTERCONNECT nCCAS_I/PADDI SLICE_12/A0 (0:0:0)(0:0:0)) (INTERCONNECT nCCAS_I/PADDI SLICE_25/A1 (0:0:0)(0:0:0)) @@ -3719,58 +3774,60 @@ (INTERCONNECT nCCAS_I/PADDI RD\[2\]_MGIOL/CLK (0:0:0)(0:0:0)) (INTERCONNECT nCCAS_I/PADDI RD\[1\]_MGIOL/CLK (0:0:0)(0:0:0)) (INTERCONNECT SLICE_12/F0 SLICE_12/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_12/F0 SLICE_73/M0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_12/F0 SLICE_73/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_12/F0 SLICE_76/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_12/F0 SLICE_76/M1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_12/Q0 SLICE_12/M1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_12/Q1 SLICE_76/M0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_12/Q1 SLICE_92/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_12/Q1 SLICE_105/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_12/Q1 SLICE_69/C0 (0:0:0)(0:0:0)) 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(INTERCONNECT SLICE_96/F0 nRCAS_MGIOL/OPOS (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_102/F0 RDQMH_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_102/F1 RDQML_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT ufmefb\/EFBInst_0/WBDATO0 SLICE_108/C1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_109/F1 RA\[3\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_110/F0 RA\[9\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_110/F1 RA\[8\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_111/F0 RA\[7\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_111/F1 RA\[0\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_112/F0 RA\[6\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_112/F1 RA\[1\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_113/F0 RA\[5\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_113/F1 RA\[2\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_114/F1 RA\[10\]_MGIOL/OPOS (0:0:0)(0:0:0)) - (INTERCONNECT CROW\[0\]_I/PADDI SLICE_115/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_115/F0 RA\[11\]_MGIOL/OPOS (0:0:0)(0:0:0)) - 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SLICE_81/F1 SLICE_81/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/F1 SLICE_111/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102/F1 SLICE_82/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/F1 SLICE_82/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/F1 SLICE_86/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/F0 SLICE_87/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/F1 SLICE_89/D0 (0:0:0)(0:0:0)) + (INTERCONNECT ufmefb\/EFBInst_0/WBACKO SLICE_89/C0 (0:0:0)(0:0:0)) + (INTERCONNECT ufmefb\/EFBInst_0/WBACKO SLICE_102/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/F1 SLICE_90/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_112/F0 SLICE_90/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_MGIOL/IN SLICE_90/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_MGIOL/IN SLICE_90/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F1 SLICE_92/D0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_92/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_119/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI RD\[2\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI Din\[2\]_MGIOL/DI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93/F0 SLICE_93/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95/F1 SLICE_95/D0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_96/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_109/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_119/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI RD\[7\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI Din\[7\]_MGIOL/DI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_109/F0 SLICE_96/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99/F0 SLICE_99/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F1 SLICE_100/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/F0 SLICE_101/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/F1 nRCAS_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_106/F0 LED_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_108/F0 RDQMH_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_108/F1 RDQML_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT ufmefb\/EFBInst_0/WBDATO0 SLICE_111/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_112/F1 RA\[2\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_113/F0 RA\[0\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_113/F1 RA\[8\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_114/F0 RA\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_114/F1 RA\[3\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_115/F0 RA\[4\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_115/F1 RA\[9\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_116/F0 RA\[5\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_116/F1 RA\[7\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT CROW\[1\]_I/PADDI SLICE_120/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_120/F0 RA\[11\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_120/F1 RBA\[1\]_MGIOL/OPOS (0:0:0)(0:0:0)) (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_I/PADDO (0:0:0)(0:0:0)) (INTERCONNECT RD\[0\]_MGIOL/IOLDO RD\[0\]_I/IOLDO (0:0:0)(0:0:0)) (INTERCONNECT nRCAS_MGIOL/IOLDO nRCAS_I/IOLDO (0:0:0)(0:0:0)) diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.vo b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.vo index 0e72972..4b94b32 100644 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.vo +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.vo @@ -2,8 +2,8 @@ // Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454 // ldbanno -n Verilog -o RAM2GS_LCMXO2_1200HC_impl1_mapvo.vo -w -neg -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd -// Netlist created on Thu Oct 19 23:50:56 2023 -// Netlist written on Thu Oct 19 23:50:59 2023 +// Netlist created on Sat Nov 18 02:05:52 2023 +// Netlist written on Sat Nov 18 02:05:56 2023 // Design is for device LCMXO2-1200HC // Design is for package TQFP100 // Design is for performance grade 4 @@ -31,66 +31,81 @@ module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, \FS_cry[10] , \FS[10] , \FS[9] , \FS_s[10] , \FS_s[9] , \FS_cry[8] , \FS[8] , \FS[7] , \FS_s[8] , \FS_s[7] , \FS_cry[6] , \FS[6] , \FS[5] , \FS_s[6] , \FS_s[5] , \FS_cry[4] , \FS[4] , \FS[3] , \FS_s[4] , - \FS_s[3] , \FS_cry[2] , \FS[2] , \FS[1] , \FS_s[2] , \FS_s[1] , N_294, - \MAin_c[1] , CmdEnable16, CmdEnable17, N_22_i, ADSubmitted, - ADSubmitted_r_0, PHI2_c, N_374, N_393, C1Submitted, C1Submitted_RNO, - nCCAS_c, nCCAS_c_i, CASr, CASr2, \S[1] , RASr2, \IS[3] , CO0, N_253_i, - Ready_0_sqmuxa_0_a3_2, un1_CmdEnable20_0_a2_1_0, un1_CmdEnable20_0_0, - CmdEnable_0_sqmuxa, un1_CmdEnable20_i, CmdEnable, CmdEnable_s, N_140, - \Din_c[1] , CmdLEDEN_4_u_i_a2_0_0, CmdLEDEN, N_380, LEDEN, - CmdLEDEN_4_u_i_0, N_284_i, XOR8MEG18, \Din_c[0] , CmdUFMData_1_sqmuxa, - VCC, CmdUFMData, GND, \Din_c[4] , \Din_c[7] , CmdUFMShift, - CmdUFMShift_3, CmdUFMWrite, N_279, CmdUFMWrite_3, N_134, \Din_c[5] , - \Din_c[3] , XOR8MEG18_i, CmdValid_r, CmdValid, \MAin_c[0] , N_36_fast, - CmdValid_fast, Cmdn8MEGEN, n8MEGEN, Cmdn8MEGEN_4_u_i_0, N_285_i, - nFWE_c, nFWE_c_i, nCRAS_c, FWEr, RD_1_i, Ready_fast, \CROW_c[1] , - \Din_c[2] , N_381, FWEr_fast, \RBAd_0[1] , N_43, Ready, \IS[0] , - N_60_i_i, N_244_i, \IS[2] , \IS[1] , N_57_i_i, N_53_i, N_58_i_i, N_49, - N_142, InitReady3_0_a2_2, InitReady, InitReady3, N_586_0, - \wb_dato[1] , LEDEN_6_i_m2, CmdValid_RNITBH02, LEDENe_0, nRowColSel, - \RowA[4] , \MAin_c[4] , \Bank[7] , \Bank[6] , \Bank[5] , \Bank[4] , - PHI2r2, PHI2r, un1_ADWR_i_o2_11, \RA_c[4] , PHI2r3, CBR, nCRAS_c_i_0, - RASr, LED_c, N_133, \wb_dati_5_1_iv_0_a2_1_1[7] , RASr3, - wb_cyc_stb_2_sqmuxa_i_a2_3_4, N_41, RCKEEN_8_u_1, RCKEEN_8_u_0_0, - RCKEEN_8, RCKEEN, RCKE_c, RCKE_2, nRWE_0io_RNO_2, N_248, N_587_0, - Ready_0_sqmuxa, N_588_0, \RowAd_0[1] , \RowAd_0[0] , \RowA[0] , - \RowA[1] , \MAin_c[3] , \MAin_c[2] , \RowAd_0[3] , \RowAd_0[2] , - \RowA[2] , \RowA[3] , \MAin_c[5] , \RowAd_0[5] , \RowAd_0[4] , - \RowA[5] , \MAin_c[7] , \MAin_c[6] , \RowAd_0[7] , \RowAd_0[6] , - \RowA[6] , \RowA[7] , \MAin_c[9] , \MAin_c[8] , \RowAd_0[9] , - \RowAd_0[8] , \RowA[8] , \RowA[9] , CBR_fast, nRCAS_0_sqmuxa_1, - XOR8MEG, XOR8MEG_3_u_0_a2_0_2, N_274, XOR8MEG_3, g1_0, N_4, - n8MEGENe_1_0, n8MEGENe_0, CASr3, N_255, nRowColSel_0_0, - nRRAS_0_sqmuxa, \wb_adr_5_i_i_0[1] , N_384, \wb_adr_5_i_i_5[0] , - N_367, N_313, N_282, N_283, N_122, \wb_adr[0] , \wb_adr[1] , - \wb_adr[2] , \wb_adr_5[3] , \wb_adr_5[2] , \wb_adr[3] , \wb_adr[4] , - N_132, N_80, N_81, \wb_adr[5] , \wb_adr[6] , \wb_adr_5[7] , - \wb_adr_5_i_m2_0[6] , \wb_adr[7] , wb_req, N_330_4, un1_PHI2r3, N_330, - wb_cyc_stb_4, N_103, wb_rst10, wb_cyc_stb, N_303, N_302, N_233, N_226, - wb_we, \wb_dati_5_0_iv_0_a2_0[0] , N_383, \wb_dati_5[1] , - \wb_dati_5[0] , \wb_dati[0] , \wb_dati[1] , \wb_dati_5_1_iv_0_1[3] , - \wb_dati[2] , N_341, \wb_dati_5_1_iv_0_o2_0[5] , N_335, - \wb_dati_5[3] , \wb_dati_5[2] , \wb_dati[3] , \wb_dati[4] , - \wb_dati_5_1_iv_0_2[4] , \wb_dati_5_1_iv_0_0[4] , \wb_dati_5[5] , - \wb_dati_5[4] , \wb_dati[5] , \wb_dati_5_1_iv_0_1[7] , N_375, N_345, - \wb_dati_5_1_iv_0_0[6] , N_348_2, \wb_dati_5[7] , \wb_dati_5[6] , - \wb_dati[6] , \wb_dati[7] , N_131, N_94_i, N_34_i, wb_reqe_0, wb_rst, - wb_rste_0, N_394, N_362, wb_we_0_0_0_0, N_353, wb_we_0_0_0, N_129, - N_223, N_428_tz, N_39, N_125, N_356, \Din_c[6] , - \wb_adr_5_i_i_a2_0[1] , \wb_adr_5_i_i_a2_3_0[0] , - \wb_adr_5_i_i_1_0_tz_0[0] , g0_0_a3_1, wb_ack, IS_0_sqmuxa_0_o2, - nRWE_0io_RNO_1, nRWE_0io_RNO_0, \wb_dati_5_1_iv_0_0[7] , N_220, - \wb_dati_5_1_iv_0_a2_3_0[7] , N_143, N_137, un1_CmdEnable20_0_a2_3_0, - N_382, un1_ADWR_i_o2_10, \Bank[3] , \Bank[1] , N_378, - \wb_adr_5_i_i_a2_6_0[0] , \wb_adr_5_i_i_1[0] , N_315, N_314, RA10s_i, - nRCS_9_u_i_0, N_37_i_1, nRCS_0io_RNO_0, N_28_i_1, nRCS_9_u_i_0_0, - N_28_i, N_376, \wb_dati_5_1_iv_0_a2_1[6] , \wb_adr_5_i_i_1_0[0] , - N_307, N_295, un1_ADWR_i_o2_4, un1_ADWR_i_o2_3, \Bank[2] , \Bank[0] , - N_25_i, wb_cyc_stb_2_sqmuxa_i_a2_3_3, N_37_i, N_371, N_141, - G_8_0_a3_0_0, nRCAS_0io_RNO_1, N_242_i_1, N_242_i, RDQMH_c, RDQML_c, - \wb_dato[0] , \RA_c[3] , \RA_c[9] , \RA_c[8] , \RA_c[7] , \RA_c[0] , - \RA_c[6] , \RA_c[1] , \RA_c[5] , \RA_c[2] , \IS_i[0] , \CROW_c[0] , - RA11d_0, \RBAd_0[0] , \RD_in[0] , \WRD[0] , nRCAS_c, nRRAS_c, nRWE_c, + \FS_s[3] , \FS_cry[2] , \FS[2] , \FS[1] , \FS_s[2] , \FS_s[1] , N_367, + \MAin_c[1] , CmdEnable16, CmdEnable17, N_293_i, ADSubmitted, + ADSubmitted_r_0_0, PHI2_c, N_457, N_483, C1Submitted, C1Submitted_RNO, + nCCAS_c, nCCAS_c_i, CASr, CASr2, \S[1] , RASr2, \IS[3] , CO0, N_279_i, + Ready_0_sqmuxa_0_a2_2, N_482, CmdEnable_0_sqmuxa, un1_CmdEnable20_i, + CmdEnable, CmdEnable_s, N_260, \Din_c[1] , CmdLEDEN_4_u_i_m2_i_a2_0_0, + CmdLEDEN, N_461, LEDEN, CmdLEDEN_4_u_i_m2_i_0, N_17_i, XOR8MEG18, + \IS[0] , \Din_c[0] , CmdUFMData_1_sqmuxa, \IS_i[0] , CmdUFMData, + CmdUFMShift, CmdUFMShift_3, GND, CmdUFMWrite, N_415, CmdUFMWrite_3, + N_353, \Din_c[5] , \Din_c[4] , \Din_c[3] , CmdValid_r, CmdValid, + \MAin_c[0] , N_34_fast, CmdValid_fast, Cmdn8MEGEN, n8MEGEN, + Cmdn8MEGEN_4_u_i_m2_i_0, N_15_i, nFWE_c, nFWE_c_i, nCRAS_c, FWEr, + RD_1_i, IS_0_sqmuxa_0_o2, un1_nRCAS_6_sqmuxa_i_o2, nRCS_9_u_i_0_0, + Ready, N_76_i_i, N_32_i, \IS[2] , \IS[1] , N_73_i_i, N_69_i, N_261_i, + IS_0_sqmuxa_0_o3, N_74_i_i, nRWE_s_i_a2_1_0, InitReady, InitReady3, + N_705_0, wb_rst10, \wb_dato[1] , un1_FS_38_i, LEDEN_6, LEDENe_0, + Ready_fast, \CROW_c[0] , PHI2r2, PHI2r, \RBAd_0[0] , VCC, PHI2r3, + nRowColSel, \RowA[6] , \MAin_c[6] , nCRAS_c_i_0, RASr, \RA_c[6] , + RASr3, \wb_adr_5_i_0_o2[0] , \S_0_i_o3[1] , RCKEEN_8_u_1, + RCKEEN_8_u_0_0, CBR, RCKEEN_8, RCKEEN, RCKE_2, RCKE_c, m3_0_a2_0, + Ready_0_sqmuxa_0_o2, N_706_0, Ready_0_sqmuxa, N_707_0, \RowAd_0[1] , + \RowAd_0[0] , \RowA[0] , \RowA[1] , \MAin_c[3] , \MAin_c[2] , + \RowAd_0[3] , \RowAd_0[2] , \RowA[2] , \RowA[3] , \MAin_c[5] , + \MAin_c[4] , \RowAd_0[5] , \RowAd_0[4] , \RowA[4] , \RowA[5] , + \MAin_c[7] , \RowAd_0[7] , \RowAd_0[6] , \RowA[7] , \MAin_c[9] , + \MAin_c[8] , \RowAd_0[9] , \RowAd_0[8] , \RowA[8] , \RowA[9] , + XOR8MEG, XOR8MEG_3_u_0_0_a2_0_2, N_411, XOR8MEG_3, g1_0, N_4, + n8MEGENe_1_0, n8MEGENe_0, CASr3, N_251_i_1_0, N_70_i, nRowColSel_0_0, + nRRAS_0_sqmuxa, \wb_adr_5_i_3_0_0[1] , \wb_adr_5_i_3_0_a2_0[1] , + \wb_adr_5_i_3_0_a2[1] , N_216, \wb_adr_5_i_0_3[0] , + \wb_adr_5_i_0_2[0] , \FS_RNIOVGI[9] , \wb_dati_5_1_iv_0_a2_11[3] , + N_45_i, N_47_i, N_126_i, \wb_adr[0] , \wb_adr[1] , \wb_adr[2] , + \wb_adr_5[3] , \wb_adr_5[2] , \wb_adr[3] , \wb_adr[4] , + \FS_RNI82PA[15] , \wb_adr_5[5] , \wb_adr_5[4] , \wb_adr[5] , + \wb_adr[6] , \wb_adr_5[7] , \wb_adr_5[6] , \wb_adr[7] , + wb_cyc_stb_4_iv_0_0_a2_0_0, \FS_RNIHVJI[15] , N_99_2, N_99_1, + un1_PHI2r3_i_li, wb_cyc_stb_4_iv_0_0_a2_0, wb_cyc_stb_4, + wb_cyc_stb_2_sqmuxa_i_0_0, wb_cyc_stb, \wb_dati_5_1_iv_0_1[1] , + \FS_RNIGOCT[12] , \FS_RNIS637[9] , wb_we, \wb_dati_5_0_iv_0_a2_1[0] , + \wb_dati_5_1_iv_0_a2_12[3] , \wb_dati_5[1] , \wb_dati_5[0] , + \wb_dati[0] , \wb_dati[1] , \wb_dati_5_1_iv_0_0_a2_1[3] , + \wb_dati_5_1_iv_0_0_1[3] , \wb_dati_5_1_iv_0_0_0[3] , + \wb_dati_5_1_iv_0_a2_13[3] , \wb_dati_5_1_iv_0_0_o2[5] , + \wb_dati_5[3] , \wb_dati_5[2] , \wb_dati[2] , \wb_dati[3] , + \wb_dati[4] , \wb_dati_5_1_iv_0_1_0[4] , \wb_dati_5_1_iv_0_0_1[4] , + \wb_dati_5[5] , \wb_dati_5[4] , \wb_dati[5] , \wb_dati_5_1_iv_0_1[7] , + \wb_dati_5_1_iv_0_a2_5[7] , \wb_dati_5_1_iv_0_RNO[7] , + \wb_dati_5_1_iv_0_0_1[6] , \wb_dati_5[7] , \wb_dati_5[6] , + \wb_dati[6] , \wb_dati[7] , un1_wb_rst14_2_0_o2, wb_req, + un1_wb_rst14_2_i, N_122_i, wb_reqe_0, wb_rst_3, wb_rst, wb_rste_0, + wb_we_0_0_i_1, N_346_i, \wb_dati_5_1_iv_0_o2[7] , + \wb_dati_5_1_iv_0_o2_0_RNIMDJC1[4] , \wb_dati_5_1_iv_0_0_o2[3] , + \wb_dati_5_1_iv_0_o2_0[7] , \FS_RNIJO0F[12] , \FS_RNI9Q57[12] , + \wb_adr_5_i_0_1[0] , N_313, \wb_adr_5_i_0_0[0] , N_48, N_466, + \Din_c[6] , un1_CmdEnable20_0_0_0, \wb_dati_5_1_iv_0_a2_0_2[1] , + \wb_dati_5_1_iv_0_0[1] , \wb_dati_5_1_iv_0_0_o2[4] , + \ufmefb/g0_0_a3_2 , \FS_RNIF2MA[9] , nRWE_s_i_tz_0, nRCS_9_u_i_o3_0_0, + RCKEEN_8_u_0_o3, nRCS_9_u_i_o3_0_2, wb_we_0_0_i_1_1, + \wb_adr_5_i_0_a2_6[0] , \wb_adr_5_i_3_0_a2_3[1] , + \wb_dati_5_1_iv_0_o2_0[4] , \FS_RNI7U6M[14] , + \wb_dati_5_1_iv_0_1_RNO[7] , CBR_fast, N_142, N_141, nRCAS_0_sqmuxa_1, + N_252_i, un1_CmdEnable20_0_0_a2_1_1, nRCS_9_u_i_0, N_251_i_1, N_37_i, + RA10s_i, \Bank[6] , \Bank[5] , \Bank[3] , \Bank[2] , + un1_CmdEnable20_0_0_o2_11, un1_CmdEnable20_0_0_o2_10, \Bank[4] , + \Bank[0] , \wb_dati_5_1_iv_0_a2_7[4] , \wb_dati_5_1_iv_0_a2_6[4] , + \wb_dati_5_1_iv_0_0_a2[6] , \wb_dati_5_1_iv_0_a2_2[4] , + \wb_dati_5_1_iv_0_a2_0_0[7] , \wb_dati_5_1_iv_0_a2_0[7] , + \wb_dati_5_1_iv_0_a2_7[3] , \wb_dati_5_1_iv_0_a2_5[3] , + wb_cyc_stb_2_sqmuxa_i_0_0_a2_0, wb_ack, un1_CmdEnable20_0_0_o2_4, + un1_CmdEnable20_0_0_o2_3, \Bank[7] , \Bank[1] , N_442, \Din_c[2] , + wb_we_0_0_i_a2_0, wb_cyc_stb_2_sqmuxa_i_a2_2_0, \Din_c[7] , N_452, + InitReady3_0_a2_1_0, G_4_0_a3_0, N_251_i_sx, N_251_i, LED_c, RDQMH_c, + RDQML_c, \wb_dato[0] , \RA_c[2] , \RA_c[0] , \RA_c[8] , \RA_c[1] , + \RA_c[3] , \RA_c[4] , \RA_c[9] , \RA_c[5] , \RA_c[7] , \CROW_c[1] , + RA11d_0, \RBAd_0[1] , \RD_in[0] , \WRD[0] , nRCAS_c, nRRAS_c, nRWE_c, RCLKout_c, nRCS_c, \RD_in[7] , \WRD[7] , \RD_in[6] , \WRD[6] , \RD_in[5] , \WRD[5] , \RD_in[4] , \WRD[4] , \RD_in[3] , \WRD[3] , \RD_in[2] , \WRD[2] , \RD_in[1] , \WRD[1] , \RA_c[11] , \RA_c[10] , @@ -124,332 +139,384 @@ module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, SLICE_9 SLICE_9( .A1(\FS[2] ), .A0(\FS[1] ), .DI1(\FS_s[2] ), .DI0(\FS_s[1] ), .CLK(RCLK_c), .FCI(\FS_cry[0] ), .F0(\FS_s[1] ), .Q0(\FS[1] ), .F1(\FS_s[2] ), .Q1(\FS[2] ), .FCO(\FS_cry[2] )); - SLICE_10 SLICE_10( .B1(N_294), .A1(\MAin_c[1] ), .D0(CmdEnable16), - .C0(CmdEnable17), .B0(N_22_i), .A0(ADSubmitted), .DI0(ADSubmitted_r_0), - .CLK(PHI2_c), .F0(ADSubmitted_r_0), .Q0(ADSubmitted), .F1(N_22_i)); - SLICE_11 SLICE_11( .D1(\MAin_c[1] ), .C1(N_374), .B1(N_294), .A1(N_393), - .D0(\MAin_c[1] ), .C0(N_294), .B0(C1Submitted), .A0(CmdEnable16), + SLICE_10 SLICE_10( .B1(N_367), .A1(\MAin_c[1] ), .D0(CmdEnable16), + .C0(CmdEnable17), .B0(N_293_i), .A0(ADSubmitted), .DI0(ADSubmitted_r_0_0), + .CLK(PHI2_c), .F0(ADSubmitted_r_0_0), .Q0(ADSubmitted), .F1(N_293_i)); + SLICE_11 SLICE_11( .D1(\MAin_c[1] ), .C1(N_367), .B1(N_457), .A1(N_483), + .D0(\MAin_c[1] ), .C0(N_367), .B0(C1Submitted), .A0(CmdEnable16), .DI0(C1Submitted_RNO), .CLK(PHI2_c), .F0(C1Submitted_RNO), .Q0(C1Submitted), .F1(CmdEnable16)); SLICE_12 SLICE_12( .A0(nCCAS_c), .DI0(nCCAS_c_i), .M1(CASr), .CLK(RCLK_c), .F0(nCCAS_c_i), .Q0(CASr), .Q1(CASr2)); SLICE_16 SLICE_16( .D1(\S[1] ), .C1(RASr2), .B1(\IS[3] ), .A1(CO0), - .B0(\S[1] ), .A0(CO0), .DI0(N_253_i), .LSR(RASr2), .CLK(RCLK_c), - .F0(N_253_i), .Q0(CO0), .F1(Ready_0_sqmuxa_0_a3_2)); - SLICE_17 SLICE_17( .D1(un1_CmdEnable20_0_a2_1_0), .C1(un1_CmdEnable20_0_0), - .B1(N_294), .A1(C1Submitted), .D0(CmdEnable_0_sqmuxa), - .C0(un1_CmdEnable20_i), .B0(CmdEnable17), .A0(CmdEnable), - .DI0(CmdEnable_s), .CLK(PHI2_c), .F0(CmdEnable_s), .Q0(CmdEnable), - .F1(un1_CmdEnable20_i)); - SLICE_18 SLICE_18( .D1(N_140), .C1(\Din_c[1] ), .B1(CmdLEDEN_4_u_i_a2_0_0), - .A1(CmdLEDEN), .C0(N_380), .B0(LEDEN), .A0(CmdLEDEN_4_u_i_0), - .DI0(N_284_i), .CE(XOR8MEG18), .CLK(PHI2_c), .F0(N_284_i), .Q0(CmdLEDEN), - .F1(CmdLEDEN_4_u_i_0)); - SLICE_19 SLICE_19( .M0(\Din_c[0] ), .CE(CmdUFMData_1_sqmuxa), .CLK(PHI2_c), - .F0(VCC), .Q0(CmdUFMData), .F1(GND)); - SLICE_20 SLICE_20( .D1(\Din_c[0] ), .C1(\Din_c[4] ), .B1(\Din_c[1] ), - .A1(\Din_c[7] ), .D0(N_380), .C0(N_140), .B0(\Din_c[1] ), .A0(CmdUFMShift), + .B0(\S[1] ), .A0(CO0), .DI0(N_279_i), .LSR(RASr2), .CLK(RCLK_c), + .F0(N_279_i), .Q0(CO0), .F1(Ready_0_sqmuxa_0_a2_2)); + SLICE_17 SLICE_17( .D1(\MAin_c[1] ), .C1(N_367), .B1(N_457), .A1(N_482), + .D0(CmdEnable_0_sqmuxa), .C0(un1_CmdEnable20_i), .B0(CmdEnable17), + .A0(CmdEnable), .DI0(CmdEnable_s), .CLK(PHI2_c), .F0(CmdEnable_s), + .Q0(CmdEnable), .F1(CmdEnable17)); + SLICE_18 SLICE_18( .D1(N_260), .C1(\Din_c[1] ), + .B1(CmdLEDEN_4_u_i_m2_i_a2_0_0), .A1(CmdLEDEN), .C0(N_461), .B0(LEDEN), + .A0(CmdLEDEN_4_u_i_m2_i_0), .DI0(N_17_i), .CE(XOR8MEG18), .CLK(PHI2_c), + .F0(N_17_i), .Q0(CmdLEDEN), .F1(CmdLEDEN_4_u_i_m2_i_0)); + SLICE_19 SLICE_19( .A0(\IS[0] ), .M0(\Din_c[0] ), .CE(CmdUFMData_1_sqmuxa), + .CLK(PHI2_c), .F0(\IS_i[0] ), .Q0(CmdUFMData)); + SLICE_20 SLICE_20( .D0(N_461), .C0(N_260), .B0(\Din_c[1] ), .A0(CmdUFMShift), .DI0(CmdUFMShift_3), .CE(XOR8MEG18), .CLK(PHI2_c), .F0(CmdUFMShift_3), - .Q0(CmdUFMShift), .F1(N_374)); - SLICE_21 SLICE_21( .B1(N_140), .A1(CmdUFMWrite), .D0(N_380), .C0(N_279), + .Q0(CmdUFMShift), .F1(GND)); + SLICE_21 SLICE_21( .B1(N_260), .A1(CmdUFMWrite), .D0(N_461), .C0(N_415), .B0(\Din_c[1] ), .A0(\Din_c[0] ), .DI0(CmdUFMWrite_3), .CE(XOR8MEG18), - .CLK(PHI2_c), .F0(CmdUFMWrite_3), .Q0(CmdUFMWrite), .F1(N_279)); - SLICE_22 SLICE_22( .D1(N_134), .C1(\Din_c[5] ), .B1(\Din_c[4] ), - .A1(\Din_c[3] ), .B0(N_140), .A0(XOR8MEG18_i), .DI0(CmdValid_r), - .CLK(PHI2_c), .F0(CmdValid_r), .Q0(CmdValid), .F1(N_140)); - SLICE_23 SLICE_23( .D1(\MAin_c[1] ), .C1(CmdEnable), .B1(N_294), - .A1(\MAin_c[0] ), .B0(N_140), .A0(XOR8MEG18_i), .DI0(N_36_fast), - .CLK(PHI2_c), .F0(N_36_fast), .Q0(CmdValid_fast), .F1(XOR8MEG18_i)); - SLICE_24 SLICE_24( .D1(N_140), .C1(\Din_c[0] ), .B1(Cmdn8MEGEN), - .A1(CmdLEDEN_4_u_i_a2_0_0), .C0(n8MEGEN), .B0(N_380), - .A0(Cmdn8MEGEN_4_u_i_0), .DI0(N_285_i), .CE(XOR8MEG18), .CLK(PHI2_c), - .F0(N_285_i), .Q0(Cmdn8MEGEN), .F1(Cmdn8MEGEN_4_u_i_0)); + .CLK(PHI2_c), .F0(CmdUFMWrite_3), .Q0(CmdUFMWrite), .F1(N_415)); + SLICE_22 SLICE_22( .D1(N_353), .C1(\Din_c[5] ), .B1(\Din_c[4] ), + .A1(\Din_c[3] ), .B0(N_260), .A0(XOR8MEG18), .DI0(CmdValid_r), + .CLK(PHI2_c), .F0(CmdValid_r), .Q0(CmdValid), .F1(N_260)); + SLICE_23 SLICE_23( .D1(N_367), .C1(\MAin_c[1] ), .B1(\MAin_c[0] ), + .A1(CmdEnable), .B0(N_260), .A0(XOR8MEG18), .DI0(N_34_fast), .CLK(PHI2_c), + .F0(N_34_fast), .Q0(CmdValid_fast), .F1(XOR8MEG18)); + SLICE_24 SLICE_24( .D1(N_260), .C1(\Din_c[0] ), .B1(Cmdn8MEGEN), + .A1(CmdLEDEN_4_u_i_m2_i_a2_0_0), .C0(n8MEGEN), .B0(N_461), + .A0(Cmdn8MEGEN_4_u_i_m2_i_0), .DI0(N_15_i), .CE(XOR8MEG18), .CLK(PHI2_c), + .F0(N_15_i), .Q0(Cmdn8MEGEN), .F1(Cmdn8MEGEN_4_u_i_m2_i_0)); SLICE_25 SLICE_25( .B1(nFWE_c), .A1(nCCAS_c), .A0(nFWE_c), .DI0(nFWE_c_i), .CLK(nCRAS_c), .F0(nFWE_c_i), .Q0(FWEr), .F1(RD_1_i)); - SLICE_26 SLICE_26( .B1(Ready_fast), .A1(\CROW_c[1] ), .B0(\Din_c[5] ), - .A0(\Din_c[2] ), .M0(nFWE_c_i), .CLK(nCRAS_c), .F0(N_381), .Q0(FWEr_fast), - .F1(\RBAd_0[1] )); - SLICE_27 SLICE_27( .B1(N_43), .A1(Ready), .C0(N_43), .B0(Ready), - .A0(\IS[0] ), .DI0(N_60_i_i), .CLK(RCLK_c), .F0(N_60_i_i), .Q0(\IS[0] ), - .F1(N_244_i)); - SLICE_28 SLICE_28( .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), .B0(\IS[1] ), - .A0(\IS[0] ), .DI1(N_57_i_i), .DI0(N_53_i), .CE(N_244_i), .CLK(RCLK_c), - .F0(N_53_i), .Q0(\IS[1] ), .F1(N_57_i_i), .Q1(\IS[2] )); - SLICE_29 SLICE_29( .C1(\IS[3] ), .B1(\IS[2] ), .A1(\IS[1] ), .D0(\IS[0] ), - .C0(\IS[1] ), .B0(\IS[2] ), .A0(\IS[3] ), .DI0(N_58_i_i), .CE(N_244_i), - .CLK(RCLK_c), .F0(N_58_i_i), .Q0(\IS[3] ), .F1(N_49)); - SLICE_30 SLICE_30( .D1(N_142), .C1(InitReady3_0_a2_2), .B1(\FS[14] ), - .A1(\FS[13] ), .B0(InitReady), .A0(InitReady3), .DI0(N_586_0), - .CLK(RCLK_c), .F0(N_586_0), .Q0(InitReady), .F1(InitReady3)); - SLICE_31 SLICE_31( .C1(\wb_dato[1] ), .B1(InitReady), .A1(CmdLEDEN), - .C0(LEDEN_6_i_m2), .B0(CmdValid_RNITBH02), .A0(LEDEN), .DI0(LEDENe_0), - .CLK(RCLK_c), .F0(LEDENe_0), .Q0(LEDEN), .F1(LEDEN_6_i_m2)); - SLICE_32 SLICE_32( .C1(nRowColSel), .B1(\RowA[4] ), .A1(\MAin_c[4] ), - .D0(\Bank[7] ), .C0(\Bank[6] ), .B0(\Bank[5] ), .A0(\Bank[4] ), - .M1(PHI2r2), .M0(PHI2r), .CLK(RCLK_c), .F0(un1_ADWR_i_o2_11), .Q0(PHI2r2), - .F1(\RA_c[4] ), .Q1(PHI2r3)); - SLICE_33 SLICE_33( .C1(nCRAS_c), .B1(LEDEN), .A1(CBR), .A0(nCRAS_c), - .DI0(nCRAS_c_i_0), .M1(RASr), .CLK(RCLK_c), .F0(nCRAS_c_i_0), .Q0(RASr), - .F1(LED_c), .Q1(RASr2)); - SLICE_34 SLICE_34( .D1(\FS[5] ), .C1(\FS[4] ), .B1(\FS[2] ), .A1(\FS[1] ), - .D0(N_133), .C0(\FS[12] ), .B0(\FS[11] ), .A0(\FS[10] ), .M0(RASr2), - .CLK(RCLK_c), .F0(\wb_dati_5_1_iv_0_a2_1_1[7] ), .Q0(RASr3), - .F1(wb_cyc_stb_2_sqmuxa_i_a2_3_4)); - SLICE_35 SLICE_35( .D1(N_41), .C1(InitReady), .B1(RASr2), .A1(Ready), - .D0(Ready), .C0(RCKEEN_8_u_1), .B0(RCKEEN_8_u_0_0), .A0(CBR), + SLICE_26 SLICE_26( .D1(\IS[0] ), .C1(IS_0_sqmuxa_0_o2), + .B1(un1_nRCAS_6_sqmuxa_i_o2), .A1(nRCS_9_u_i_0_0), .C0(IS_0_sqmuxa_0_o2), + .B0(Ready), .A0(\IS[0] ), .DI0(N_76_i_i), .CLK(RCLK_c), .F0(N_76_i_i), + .Q0(\IS[0] ), .F1(N_32_i)); + SLICE_27 SLICE_27( .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), .B0(\IS[1] ), + .A0(\IS[0] ), .DI1(N_73_i_i), .DI0(N_69_i), .CE(N_261_i), .CLK(RCLK_c), + .F0(N_69_i), .Q0(\IS[1] ), .F1(N_73_i_i), .Q1(\IS[2] )); + SLICE_28 SLICE_28( .D1(IS_0_sqmuxa_0_o3), .C1(\IS[2] ), .B1(\IS[1] ), + .A1(\IS[0] ), .D0(\IS[0] ), .C0(\IS[1] ), .B0(\IS[2] ), .A0(\IS[3] ), + .DI0(N_74_i_i), .CE(N_261_i), .CLK(RCLK_c), .F0(N_74_i_i), .Q0(\IS[3] ), + .F1(nRWE_s_i_a2_1_0)); + SLICE_29 SLICE_29( .D1(\FS[16] ), .C1(\FS[17] ), .B1(InitReady), + .A1(\FS[15] ), .B0(InitReady), .A0(InitReady3), .DI0(N_705_0), + .CLK(RCLK_c), .F0(N_705_0), .Q0(InitReady), .F1(wb_rst10)); + SLICE_30 SLICE_30( .C1(\wb_dato[1] ), .B1(InitReady), .A1(CmdLEDEN), + .C0(un1_FS_38_i), .B0(LEDEN_6), .A0(LEDEN), .DI0(LEDENe_0), .CLK(RCLK_c), + .F0(LEDENe_0), .Q0(LEDEN), .F1(LEDEN_6)); + SLICE_31 SLICE_31( .B0(Ready_fast), .A0(\CROW_c[0] ), .M1(PHI2r2), + .M0(PHI2r), .CLK(RCLK_c), .F0(\RBAd_0[0] ), .Q0(PHI2r2), .F1(VCC), + .Q1(PHI2r3)); + SLICE_32 SLICE_32( .C1(nRowColSel), .B1(\RowA[6] ), .A1(\MAin_c[6] ), + .A0(nCRAS_c), .DI0(nCRAS_c_i_0), .M1(RASr), .CLK(RCLK_c), .F0(nCRAS_c_i_0), + .Q0(RASr), .F1(\RA_c[6] ), .Q1(RASr2)); + SLICE_33 SLICE_33( .C1(\FS[11] ), .B1(\FS[10] ), .A1(\FS[9] ), + .B0(CmdEnable16), .A0(ADSubmitted), .M0(RASr2), .CLK(RCLK_c), + .F0(CmdEnable_0_sqmuxa), .Q0(RASr3), .F1(\wb_adr_5_i_0_o2[0] )); + SLICE_34 SLICE_34( .D1(\S_0_i_o3[1] ), .C1(InitReady), .B1(RASr2), + .A1(Ready), .D0(Ready), .C0(RCKEEN_8_u_1), .B0(RCKEEN_8_u_0_0), .A0(CBR), .DI0(RCKEEN_8), .CLK(RCLK_c), .F0(RCKEEN_8), .Q0(RCKEEN), .F1(RCKEEN_8_u_0_0)); - SLICE_36 SLICE_36( .B1(RCKE_c), .A1(RASr2), .D0(RCKEEN), .C0(RASr3), + SLICE_35 SLICE_35( .B1(\S[1] ), .A1(RASr2), .D0(RCKEEN), .C0(RASr3), .B0(RASr2), .A0(RASr), .DI0(RCKE_2), .CLK(RCLK_c), .F0(RCKE_2), - .Q0(RCKE_c), .F1(nRWE_0io_RNO_2)); - SLICE_37 SLICE_37( .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), .D0(InitReady), - .C0(N_248), .B0(Ready_0_sqmuxa_0_a3_2), .A0(Ready), .DI0(N_587_0), - .CLK(RCLK_c), .F0(N_587_0), .Q0(Ready), .F1(N_248)); - SLICE_38 SLICE_38( .D1(Ready_0_sqmuxa_0_a3_2), .C1(Ready), .B1(N_248), - .A1(InitReady), .B0(Ready_fast), .A0(Ready_0_sqmuxa), .DI0(N_588_0), - .CLK(RCLK_c), .F0(N_588_0), .Q0(Ready_fast), .F1(Ready_0_sqmuxa)); - SLICE_39 SLICE_39( .B1(Ready_fast), .A1(\MAin_c[1] ), .B0(Ready_fast), + .Q0(RCKE_c), .F1(m3_0_a2_0)); + SLICE_36 SLICE_36( .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), .D0(InitReady), + .C0(Ready_0_sqmuxa_0_o2), .B0(Ready_0_sqmuxa_0_a2_2), .A0(Ready), + .DI0(N_706_0), .CLK(RCLK_c), .F0(N_706_0), .Q0(Ready), + .F1(Ready_0_sqmuxa_0_o2)); + SLICE_37 SLICE_37( .D1(Ready_0_sqmuxa_0_a2_2), .C1(Ready), + .B1(Ready_0_sqmuxa_0_o2), .A1(InitReady), .B0(Ready_fast), + .A0(Ready_0_sqmuxa), .DI0(N_707_0), .CLK(RCLK_c), .F0(N_707_0), + .Q0(Ready_fast), .F1(Ready_0_sqmuxa)); + SLICE_38 SLICE_38( .B1(Ready_fast), .A1(\MAin_c[1] ), .B0(Ready_fast), .A0(\MAin_c[0] ), .DI1(\RowAd_0[1] ), .DI0(\RowAd_0[0] ), .CLK(nCRAS_c), .F0(\RowAd_0[0] ), .Q0(\RowA[0] ), .F1(\RowAd_0[1] ), .Q1(\RowA[1] )); - SLICE_40 SLICE_40( .B1(Ready_fast), .A1(\MAin_c[3] ), .B0(Ready_fast), + SLICE_39 SLICE_39( .B1(Ready_fast), .A1(\MAin_c[3] ), .B0(Ready_fast), .A0(\MAin_c[2] ), .DI1(\RowAd_0[3] ), .DI0(\RowAd_0[2] ), .CLK(nCRAS_c), .F0(\RowAd_0[2] ), .Q0(\RowA[2] ), .F1(\RowAd_0[3] ), .Q1(\RowA[3] )); - SLICE_41 SLICE_41( .B1(Ready_fast), .A1(\MAin_c[5] ), .B0(Ready_fast), + SLICE_40 SLICE_40( .B1(Ready_fast), .A1(\MAin_c[5] ), .B0(Ready_fast), .A0(\MAin_c[4] ), .DI1(\RowAd_0[5] ), .DI0(\RowAd_0[4] ), .CLK(nCRAS_c), .F0(\RowAd_0[4] ), .Q0(\RowA[4] ), .F1(\RowAd_0[5] ), .Q1(\RowA[5] )); - SLICE_42 SLICE_42( .B1(Ready_fast), .A1(\MAin_c[7] ), .B0(Ready_fast), + SLICE_41 SLICE_41( .B1(Ready_fast), .A1(\MAin_c[7] ), .B0(Ready_fast), .A0(\MAin_c[6] ), .DI1(\RowAd_0[7] ), .DI0(\RowAd_0[6] ), .CLK(nCRAS_c), .F0(\RowAd_0[6] ), .Q0(\RowA[6] ), .F1(\RowAd_0[7] ), .Q1(\RowA[7] )); - SLICE_43 SLICE_43( .B1(Ready_fast), .A1(\MAin_c[9] ), .B0(Ready_fast), + SLICE_42 SLICE_42( .B1(Ready_fast), .A1(\MAin_c[9] ), .B0(Ready_fast), .A0(\MAin_c[8] ), .DI1(\RowAd_0[9] ), .DI0(\RowAd_0[8] ), .CLK(nCRAS_c), .F0(\RowAd_0[8] ), .Q0(\RowA[8] ), .F1(\RowAd_0[9] ), .Q1(\RowA[9] )); - SLICE_44 SLICE_44( .D1(Ready), .C1(RASr2), .B1(N_41), .A1(CBR_fast), - .B0(\S[1] ), .A0(CO0), .DI0(N_41), .LSR(RASr2), .CLK(RCLK_c), .F0(N_41), - .Q0(\S[1] ), .F1(nRCAS_0_sqmuxa_1)); - SLICE_45 SLICE_45( .D1(XOR8MEG), .C1(N_134), .B1(\Din_c[5] ), - .A1(\Din_c[4] ), .D0(XOR8MEG_3_u_0_a2_0_2), .C0(N_274), .B0(LEDEN), + SLICE_43 SLICE_43( .D1(Ready), .C1(RCKE_c), .B1(RASr2), .A1(\S_0_i_o3[1] ), + .B0(\S[1] ), .A0(CO0), .DI0(\S_0_i_o3[1] ), .LSR(RASr2), .CLK(RCLK_c), + .F0(\S_0_i_o3[1] ), .Q0(\S[1] ), .F1(nRCS_9_u_i_0_0)); + SLICE_44 SLICE_44( .D1(XOR8MEG), .C1(N_353), .B1(\Din_c[5] ), + .A1(\Din_c[4] ), .D0(XOR8MEG_3_u_0_0_a2_0_2), .C0(N_411), .B0(LEDEN), .A0(\Din_c[1] ), .DI0(XOR8MEG_3), .CE(XOR8MEG18), .CLK(PHI2_c), - .F0(XOR8MEG_3), .Q0(XOR8MEG), .F1(N_274)); - SLICE_46 SLICE_46( .D1(g1_0), .C1(N_4), .B1(InitReady), .A1(CmdValid), - .C0(n8MEGENe_1_0), .B0(n8MEGEN), .A0(CmdValid_RNITBH02), .DI0(n8MEGENe_0), - .CLK(RCLK_c), .F0(n8MEGENe_0), .Q0(n8MEGEN), .F1(CmdValid_RNITBH02)); - SLICE_47 SLICE_47( .D1(Ready), .C1(FWEr), .B1(CBR), .A1(CASr3), .D0(\S[1] ), - .C0(Ready), .B0(N_255), .A0(CO0), .DI0(nRowColSel_0_0), - .LSR(nRRAS_0_sqmuxa), .CLK(RCLK_c), .F0(nRowColSel_0_0), .Q0(nRowColSel), - .F1(N_255)); - SLICE_48 SLICE_48( .D1(\wb_adr_5_i_i_0[1] ), .C1(N_384), .B1(\FS[12] ), - .A1(\FS[11] ), .D0(\wb_adr_5_i_i_5[0] ), .C0(N_367), .B0(N_313), - .A0(\FS[11] ), .DI1(N_282), .DI0(N_283), .CE(N_122), .CLK(RCLK_c), - .F0(N_283), .Q0(\wb_adr[0] ), .F1(N_282), .Q1(\wb_adr[1] )); - SLICE_49 SLICE_49( .B1(\wb_adr[2] ), .A1(InitReady), .B0(\wb_adr[1] ), - .A0(InitReady), .DI1(\wb_adr_5[3] ), .DI0(\wb_adr_5[2] ), .CE(N_122), + .F0(XOR8MEG_3), .Q0(XOR8MEG), .F1(N_411)); + SLICE_45 SLICE_45( .D1(g1_0), .C1(N_4), .B1(InitReady), .A1(CmdValid), + .C0(un1_FS_38_i), .B0(n8MEGENe_1_0), .A0(n8MEGEN), .DI0(n8MEGENe_0), + .CLK(RCLK_c), .F0(n8MEGENe_0), .Q0(n8MEGEN), .F1(un1_FS_38_i)); + SLICE_46 SLICE_46( .B1(FWEr), .A1(CASr3), .D0(Ready), .C0(N_251_i_1_0), + .B0(N_70_i), .A0(CBR), .DI0(nRowColSel_0_0), .LSR(nRRAS_0_sqmuxa), + .CLK(RCLK_c), .F0(nRowColSel_0_0), .Q0(nRowColSel), .F1(N_251_i_1_0)); + SLICE_47 SLICE_47( .D1(\wb_adr_5_i_3_0_0[1] ), .C1(\wb_adr_5_i_3_0_a2_0[1] ), + .B1(\wb_adr_5_i_3_0_a2[1] ), .A1(N_216), .D0(\wb_adr_5_i_0_3[0] ), + .C0(\wb_adr_5_i_0_2[0] ), .B0(\FS_RNIOVGI[9] ), + .A0(\wb_dati_5_1_iv_0_a2_11[3] ), .DI1(N_45_i), .DI0(N_47_i), .CE(N_126_i), + .CLK(RCLK_c), .F0(N_47_i), .Q0(\wb_adr[0] ), .F1(N_45_i), .Q1(\wb_adr[1] )); + SLICE_48 SLICE_48( .B1(\wb_adr[2] ), .A1(InitReady), .B0(\wb_adr[1] ), + .A0(InitReady), .DI1(\wb_adr_5[3] ), .DI0(\wb_adr_5[2] ), .CE(N_126_i), .CLK(RCLK_c), .F0(\wb_adr_5[2] ), .Q0(\wb_adr[2] ), .F1(\wb_adr_5[3] ), .Q1(\wb_adr[3] )); - SLICE_50 SLICE_50( .C1(\wb_adr[4] ), .B1(N_132), .A1(InitReady), - .C0(\wb_adr[3] ), .B0(N_132), .A0(InitReady), .DI1(N_80), .DI0(N_81), - .CE(N_122), .CLK(RCLK_c), .F0(N_81), .Q0(\wb_adr[4] ), .F1(N_80), - .Q1(\wb_adr[5] )); - SLICE_51 SLICE_51( .B1(\wb_adr[6] ), .A1(InitReady), .C0(\wb_adr[5] ), - .B0(N_132), .A0(InitReady), .DI1(\wb_adr_5[7] ), - .DI0(\wb_adr_5_i_m2_0[6] ), .CE(N_122), .CLK(RCLK_c), - .F0(\wb_adr_5_i_m2_0[6] ), .Q0(\wb_adr[6] ), .F1(\wb_adr_5[7] ), - .Q1(\wb_adr[7] )); - SLICE_52 SLICE_52( .D1(wb_req), .C1(N_330_4), .B1(N_132), .A1(\FS[0] ), - .D0(un1_PHI2r3), .C0(N_330), .B0(InitReady), .A0(CmdUFMWrite), - .DI0(wb_cyc_stb_4), .CE(N_103), .LSR(wb_rst10), .CLK(RCLK_c), - .F0(wb_cyc_stb_4), .Q0(wb_cyc_stb), .F1(N_330)); - SLICE_53 SLICE_53( .D1(N_303), .C1(N_302), .B1(N_233), .A1(N_226), - .D0(wb_we), .C0(\wb_dati_5_0_iv_0_a2_0[0] ), .B0(N_383), .A0(InitReady), - .DI1(\wb_dati_5[1] ), .DI0(\wb_dati_5[0] ), .CE(N_122), .CLK(RCLK_c), - .F0(\wb_dati_5[0] ), .Q0(\wb_dati[0] ), .F1(\wb_dati_5[1] ), + SLICE_49 SLICE_49( .C1(\wb_adr[4] ), .B1(\FS_RNI82PA[15] ), .A1(InitReady), + .C0(\wb_adr[3] ), .B0(\FS_RNI82PA[15] ), .A0(InitReady), + .DI1(\wb_adr_5[5] ), .DI0(\wb_adr_5[4] ), .CE(N_126_i), .CLK(RCLK_c), + .F0(\wb_adr_5[4] ), .Q0(\wb_adr[4] ), .F1(\wb_adr_5[5] ), .Q1(\wb_adr[5] )); + SLICE_50 SLICE_50( .B1(\wb_adr[6] ), .A1(InitReady), .C0(\wb_adr[5] ), + .B0(\FS_RNI82PA[15] ), .A0(InitReady), .DI1(\wb_adr_5[7] ), + .DI0(\wb_adr_5[6] ), .CE(N_126_i), .CLK(RCLK_c), .F0(\wb_adr_5[6] ), + .Q0(\wb_adr[6] ), .F1(\wb_adr_5[7] ), .Q1(\wb_adr[7] )); + SLICE_51 SLICE_51( .D1(wb_cyc_stb_4_iv_0_0_a2_0_0), .C1(\FS_RNIHVJI[15] ), + .B1(N_99_2), .A1(N_99_1), .D0(un1_PHI2r3_i_li), + .C0(wb_cyc_stb_4_iv_0_0_a2_0), .B0(InitReady), .A0(CmdUFMWrite), + .DI0(wb_cyc_stb_4), .CE(wb_cyc_stb_2_sqmuxa_i_0_0), .LSR(wb_rst10), + .CLK(RCLK_c), .F0(wb_cyc_stb_4), .Q0(wb_cyc_stb), + .F1(wb_cyc_stb_4_iv_0_0_a2_0)); + SLICE_52 SLICE_52( .D1(\wb_dati_5_1_iv_0_1[1] ), .C1(\FS_RNIGOCT[12] ), + .B1(\FS_RNIS637[9] ), .A1(\FS[11] ), .D0(wb_we), + .C0(\wb_dati_5_0_iv_0_a2_1[0] ), .B0(\wb_dati_5_1_iv_0_a2_12[3] ), + .A0(InitReady), .DI1(\wb_dati_5[1] ), .DI0(\wb_dati_5[0] ), .CE(N_126_i), + .CLK(RCLK_c), .F0(\wb_dati_5[0] ), .Q0(\wb_dati[0] ), .F1(\wb_dati_5[1] ), .Q1(\wb_dati[1] )); - SLICE_54 SLICE_54( .D1(\wb_dati_5_1_iv_0_1[3] ), .C1(\wb_dati[2] ), - .B1(N_341), .A1(InitReady), .D0(\wb_dati_5_1_iv_0_o2_0[5] ), - .C0(\wb_dati[1] ), .B0(N_335), .A0(InitReady), .DI1(\wb_dati_5[3] ), - .DI0(\wb_dati_5[2] ), .CE(N_122), .CLK(RCLK_c), .F0(\wb_dati_5[2] ), + SLICE_53 SLICE_53( .D1(\wb_dati_5_1_iv_0_0_a2_1[3] ), + .C1(\wb_dati_5_1_iv_0_0_1[3] ), .B1(\wb_dati_5_1_iv_0_0_0[3] ), + .A1(\wb_dati_5_1_iv_0_a2_13[3] ), .C0(\wb_dati[1] ), + .B0(\wb_dati_5_1_iv_0_0_o2[5] ), .A0(InitReady), .DI1(\wb_dati_5[3] ), + .DI0(\wb_dati_5[2] ), .CE(N_126_i), .CLK(RCLK_c), .F0(\wb_dati_5[2] ), .Q0(\wb_dati[2] ), .F1(\wb_dati_5[3] ), .Q1(\wb_dati[3] )); - SLICE_55 SLICE_55( .D1(\wb_dati_5_1_iv_0_o2_0[5] ), .C1(\wb_dati[4] ), - .B1(N_335), .A1(InitReady), .C0(\wb_dati_5_1_iv_0_2[4] ), - .B0(\wb_dati_5_1_iv_0_0[4] ), .A0(N_335), .DI1(\wb_dati_5[5] ), - .DI0(\wb_dati_5[4] ), .CE(N_122), .CLK(RCLK_c), .F0(\wb_dati_5[4] ), - .Q0(\wb_dati[4] ), .F1(\wb_dati_5[5] ), .Q1(\wb_dati[5] )); - SLICE_56 SLICE_56( .D1(\wb_dati_5_1_iv_0_a2_1_1[7] ), - .C1(\wb_dati_5_1_iv_0_1[7] ), .B1(N_375), .A1(N_345), - .D0(\wb_dati_5_1_iv_0_0[6] ), .C0(N_383), .B0(N_348_2), .A0(N_233), - .DI1(\wb_dati_5[7] ), .DI0(\wb_dati_5[6] ), .CE(N_122), .CLK(RCLK_c), + SLICE_54 SLICE_54( .C1(\wb_dati[4] ), .B1(\wb_dati_5_1_iv_0_0_o2[5] ), + .A1(InitReady), .D0(\wb_dati_5_1_iv_0_1_0[4] ), + .C0(\wb_dati_5_1_iv_0_0_1[4] ), .B0(\FS_RNIGOCT[12] ), .A0(\FS[9] ), + .DI1(\wb_dati_5[5] ), .DI0(\wb_dati_5[4] ), .CE(N_126_i), .CLK(RCLK_c), + .F0(\wb_dati_5[4] ), .Q0(\wb_dati[4] ), .F1(\wb_dati_5[5] ), + .Q1(\wb_dati[5] )); + SLICE_55 SLICE_55( .D1(\wb_dati_5_1_iv_0_1[7] ), + .C1(\wb_dati_5_1_iv_0_a2_5[7] ), .B1(\wb_dati_5_1_iv_0_a2_13[3] ), + .A1(\wb_dati_5_1_iv_0_RNO[7] ), .D0(\wb_dati_5_1_iv_0_0_1[6] ), + .C0(\FS_RNIGOCT[12] ), .B0(\FS_RNIS637[9] ), .A0(\FS[11] ), + .DI1(\wb_dati_5[7] ), .DI0(\wb_dati_5[6] ), .CE(N_126_i), .CLK(RCLK_c), .F0(\wb_dati_5[6] ), .Q0(\wb_dati[6] ), .F1(\wb_dati_5[7] ), .Q1(\wb_dati[7] )); - SLICE_57 SLICE_57( .D1(N_131), .C1(\FS[14] ), .B1(\FS[13] ), .A1(\FS[12] ), - .C0(wb_req), .B0(N_94_i), .A0(N_34_i), .DI0(wb_reqe_0), .LSR(wb_rst10), - .CLK(RCLK_c), .F0(wb_reqe_0), .Q0(wb_req), .F1(N_34_i)); - SLICE_58 SLICE_58( .D1(\FS[16] ), .C1(\FS[17] ), .B1(InitReady), - .A1(\FS[15] ), .D0(wb_rst10), .C0(wb_rst), .B0(N_94_i), .A0(\FS[14] ), - .DI0(wb_rste_0), .CLK(RCLK_c), .F0(wb_rste_0), .Q0(wb_rst), .F1(wb_rst10)); - SLICE_59 SLICE_59( .D1(\wb_dati[3] ), .C1(N_394), .B1(N_362), .A1(InitReady), - .D0(wb_we_0_0_0_0), .C0(N_353), .B0(InitReady), .A0(CmdUFMData), - .DI0(wb_we_0_0_0), .CE(N_122), .LSR(wb_rst10), .CLK(RCLK_c), - .F0(wb_we_0_0_0), .Q0(wb_we), .F1(\wb_dati_5_1_iv_0_0[4] )); - SLICE_60 SLICE_60( .D1(\FS[9] ), .C1(N_132), .B1(\FS[13] ), .A1(N_129), - .D0(N_362), .C0(N_226), .B0(N_223), .A0(\FS[13] ), - .F0(\wb_dati_5_1_iv_0_1[3] ), .F1(N_226)); - SLICE_61 SLICE_61( .D1(\FS[16] ), .C1(\FS[17] ), .B1(InitReady), - .A1(\FS[15] ), .D0(\wb_adr[0] ), .C0(N_428_tz), .B0(N_132), .A0(InitReady), - .F0(\wb_adr_5_i_i_0[1] ), .F1(N_132)); + SLICE_56 SLICE_56( .D1(\FS[12] ), .C1(\FS[13] ), .B1(\FS[14] ), + .A1(un1_wb_rst14_2_0_o2), .C0(wb_req), .B0(un1_wb_rst14_2_i), .A0(N_122_i), + .DI0(wb_reqe_0), .LSR(wb_rst10), .CLK(RCLK_c), .F0(wb_reqe_0), .Q0(wb_req), + .F1(un1_wb_rst14_2_i)); + SLICE_57 SLICE_57( .D1(PHI2r3), .C1(PHI2r2), .B1(InitReady), .A1(CmdValid), + .C0(wb_rst_3), .B0(wb_rst), .A0(N_122_i), .DI0(wb_rste_0), .CLK(RCLK_c), + .F0(wb_rste_0), .Q0(wb_rst), .F1(N_122_i)); + SLICE_58 SLICE_58( .C1(InitReady), .B1(\FS[17] ), .A1(\FS[16] ), + .D0(wb_we_0_0_i_1), .C0(un1_wb_rst14_2_0_o2), .B0(InitReady), + .A0(CmdUFMData), .DI0(N_346_i), .CE(N_126_i), .LSR(wb_rst10), .CLK(RCLK_c), + .F0(N_346_i), .Q0(wb_we), .F1(un1_wb_rst14_2_0_o2)); + wb_dati_5_1_iv_0_0_o2_5__SLICE_59 \wb_dati_5_1_iv_0_0_o2[5]/SLICE_59 ( + .D1(\FS[12] ), .C1(\wb_dati_5_1_iv_0_o2[7] ), .B1(\FS_RNIHVJI[15] ), + .A1(\wb_dati_5_1_iv_0_o2_0_RNIMDJC1[4] ), .D0(\FS[13] ), + .C0(\wb_dati_5_1_iv_0_0_o2[3] ), .B0(\FS_RNIHVJI[15] ), + .A0(\wb_dati_5_1_iv_0_o2_0_RNIMDJC1[4] ), .M0(\FS[9] ), + .OFX0(\wb_dati_5_1_iv_0_0_o2[5] )); + wb_adr_5_i_0_1_0__SLICE_60 \wb_adr_5_i_0_1[0]/SLICE_60 ( .C1(\FS[13] ), + .B1(\wb_dati_5_1_iv_0_o2_0[7] ), .A1(\FS_RNIJO0F[12] ), .D0(InitReady), + .C0(\FS_RNI9Q57[12] ), .B0(\FS[9] ), .A0(\FS[10] ), .M0(\FS[11] ), + .OFX0(\wb_adr_5_i_0_1[0] )); + SLICE_61 SLICE_61( .D1(\FS[14] ), .C1(InitReady), .B1(N_313), + .A1(\FS_RNI9Q57[12] ), .D0(\FS[14] ), .C0(InitReady), .B0(\FS[13] ), + .A0(\wb_adr_5_i_0_o2[0] ), .F0(N_313), .F1(\wb_adr_5_i_0_0[0] )); SLICE_62 SLICE_62( .D1(CO0), .C1(\S[1] ), .B1(InitReady), .A1(RASr2), - .D0(\S[1] ), .C0(Ready), .B0(N_49), .A0(N_43), .F0(N_39), .F1(N_43)); - SLICE_63 SLICE_63( .D1(N_142), .C1(N_131), .B1(N_125), .A1(\FS[13] ), - .D0(N_356), .C0(N_133), .B0(N_131), .A0(\FS[12] ), .F0(wb_we_0_0_0_0), - .F1(N_356)); - SLICE_64 SLICE_64( .D1(N_381), .C1(\MAin_c[0] ), .B1(\Din_c[6] ), - .A1(\Din_c[3] ), .D0(N_393), .C0(N_374), .B0(\MAin_c[1] ), - .A0(\MAin_c[0] ), .F0(un1_CmdEnable20_0_0), .F1(N_393)); - SLICE_65 SLICE_65( .D1(\wb_adr_5_i_i_a2_0[1] ), .C1(N_142), .B1(\FS[14] ), - .A1(\FS[13] ), .D0(N_125), .C0(\FS[13] ), .B0(\FS[12] ), .A0(\FS[11] ), - .F0(\wb_adr_5_i_i_a2_0[1] ), .F1(N_428_tz)); - SLICE_66 SLICE_66( .C1(\FS[12] ), .B1(\FS[11] ), .A1(\FS[9] ), - .D0(\wb_adr_5_i_i_a2_3_0[0] ), .C0(\FS[13] ), .B0(\FS[11] ), .A0(\FS[10] ), - .F0(\wb_adr_5_i_i_1_0_tz_0[0] ), .F1(\wb_adr_5_i_i_a2_3_0[0] )); - SLICE_67 SLICE_67( .D1(g0_0_a3_1), .C1(N_142), .B1(N_132), .A1(N_125), - .C0(wb_ack), .B0(\FS[14] ), .A0(\FS[13] ), .F0(g0_0_a3_1), .F1(N_4)); - SLICE_68 SLICE_68( .D1(nRRAS_0_sqmuxa), .C1(IS_0_sqmuxa_0_o2), - .B1(nRWE_0io_RNO_2), .A1(nRWE_0io_RNO_1), .C0(CO0), .B0(\S[1] ), - .A0(Ready), .F0(nRRAS_0_sqmuxa), .F1(nRWE_0io_RNO_0)); - SLICE_69 SLICE_69( .D1(\wb_dati_5_1_iv_0_0[7] ), .C1(N_367), .B1(N_220), - .A1(\FS[11] ), .C0(\FS[9] ), .B0(\FS[10] ), .A0(\FS[12] ), .F0(N_220), - .F1(\wb_dati_5_1_iv_0_1[7] )); - SLICE_70 SLICE_70( .D1(\FS[11] ), .C1(\FS[12] ), .B1(\FS[13] ), - .A1(\FS[14] ), .C0(\FS[9] ), .B0(\FS[10] ), .A0(N_348_2), - .F0(\wb_dati_5_1_iv_0_a2_3_0[7] ), .F1(N_348_2)); - SLICE_71 SLICE_71( .C1(N_143), .B1(N_131), .A1(\FS[14] ), .D0(\FS[9] ), - .C0(\FS[10] ), .B0(\FS[11] ), .A0(\FS[13] ), .F0(N_143), .F1(N_353)); - SLICE_72 SLICE_72( .D1(\FS[14] ), .C1(N_132), .B1(\FS[13] ), .A1(N_137), - .D0(\FS[9] ), .C0(\FS[10] ), .B0(\FS[11] ), .A0(\FS[12] ), .F0(N_137), - .F1(N_335)); - SLICE_73 SLICE_73( .D1(\MAin_c[1] ), .C1(N_374), .B1(\Din_c[3] ), - .A1(\Din_c[5] ), .D0(un1_CmdEnable20_0_a2_3_0), .C0(N_382), - .B0(\Din_c[6] ), .A0(\Din_c[2] ), .M1(nCCAS_c_i), .M0(nCCAS_c_i), - .CLK(nCRAS_c), .F0(CmdEnable17), .Q0(CBR), .F1(un1_CmdEnable20_0_a2_3_0), + .D0(\S[1] ), .C0(Ready), .B0(un1_nRCAS_6_sqmuxa_i_o2), + .A0(IS_0_sqmuxa_0_o2), .F0(N_48), .F1(IS_0_sqmuxa_0_o2)); + SLICE_63 SLICE_63( .D1(N_466), .C1(\MAin_c[0] ), .B1(\Din_c[6] ), + .A1(\Din_c[3] ), .D0(N_483), .C0(N_457), .B0(\MAin_c[1] ), + .A0(\MAin_c[0] ), .F0(un1_CmdEnable20_0_0_0), .F1(N_483)); + SLICE_64 SLICE_64( .D1(InitReady), .C1(\FS[17] ), .B1(\FS[16] ), + .A1(\FS[15] ), .D0(\wb_dati_5_1_iv_0_a2_0_2[1] ), .C0(\wb_dati[0] ), + .B0(\FS_RNIHVJI[15] ), .A0(InitReady), .F0(\wb_dati_5_1_iv_0_0[1] ), + .F1(\FS_RNIHVJI[15] )); + SLICE_65 SLICE_65( .D1(\wb_dati_5_1_iv_0_a2_13[3] ), + .C1(\wb_dati_5_1_iv_0_0_o2[4] ), .B1(\FS[10] ), .A1(\FS[9] ), + .C0(\FS[13] ), .B0(\FS[11] ), .A0(\FS[10] ), + .F0(\wb_dati_5_1_iv_0_0_o2[4] ), .F1(\wb_dati_5_1_iv_0_1_0[4] )); + SLICE_66 SLICE_66( .C1(\FS[11] ), .B1(\FS[10] ), .A1(\FS[9] ), + .C0(\ufmefb/g0_0_a3_2 ), .B0(\FS_RNIF2MA[9] ), .A0(\FS_RNIHVJI[15] ), + .F0(N_4), .F1(\FS_RNIF2MA[9] )); + SLICE_67 SLICE_67( .D1(\wb_adr_5_i_0_1[0] ), .C1(\FS_RNIJO0F[12] ), + .B1(\wb_dati_5_1_iv_0_0_o2[4] ), .A1(\FS[9] ), .C0(\FS[14] ), + .B0(InitReady), .A0(\FS[12] ), .F0(\FS_RNIJO0F[12] ), + .F1(\wb_adr_5_i_0_3[0] )); + SLICE_68 SLICE_68( .D1(nRWE_s_i_a2_1_0), .C1(nRRAS_0_sqmuxa), .B1(RCKE_c), + .A1(RASr2), .C0(CO0), .B0(\S[1] ), .A0(Ready), .F0(nRRAS_0_sqmuxa), + .F1(nRWE_s_i_tz_0)); + SLICE_69 SLICE_69( .D1(nRCS_9_u_i_o3_0_0), .C1(RCKEEN_8_u_0_o3), .B1(FWEr), + .A1(CBR), .C0(CASr2), .B0(CO0), .A0(N_48), .F0(nRCS_9_u_i_o3_0_0), + .F1(nRCS_9_u_i_o3_0_2)); + SLICE_70 SLICE_70( .D1(wb_we_0_0_i_1_1), .C1(\FS_RNIOVGI[9] ), + .B1(\wb_adr_5_i_0_a2_6[0] ), .A1(\FS_RNI9Q57[12] ), .D0(\FS[9] ), + .C0(\FS[10] ), .B0(\FS[11] ), .A0(InitReady), .F0(\FS_RNIOVGI[9] ), + .F1(wb_we_0_0_i_1)); + SLICE_71 SLICE_71( .B1(\FS[10] ), .A1(\FS[9] ), .D0(\FS[12] ), .C0(\FS[11] ), + .B0(\FS_RNIS637[9] ), .A0(\wb_adr_5_i_3_0_a2_3[1] ), + .F0(\wb_adr_5_i_3_0_0[1] ), .F1(\FS_RNIS637[9] )); + SLICE_72 SLICE_72( .C1(\FS[9] ), .B1(\FS[10] ), .A1(\FS[11] ), .D0(\FS[12] ), + .C0(\FS[13] ), .B0(\wb_dati_5_1_iv_0_o2_0[4] ), .A0(\FS_RNI7U6M[14] ), + .F0(\wb_dati_5_1_iv_0_o2_0_RNIMDJC1[4] ), .F1(\wb_dati_5_1_iv_0_o2_0[4] )); + SLICE_73 SLICE_73( .C1(\wb_dati_5_1_iv_0_a2_5[7] ), + .B1(\wb_dati_5_1_iv_0_0_o2[4] ), .A1(\FS[14] ), .D0(\FS[9] ), + .C0(\FS_RNIHVJI[15] ), .B0(\FS[12] ), .A0(\wb_dati_5_1_iv_0_o2[7] ), + .F0(\wb_dati_5_1_iv_0_1_RNO[7] ), .F1(\wb_dati_5_1_iv_0_o2[7] )); + SLICE_74 SLICE_74( .D1(\FS_RNIHVJI[15] ), .C1(\FS[14] ), .B1(\FS[13] ), + .A1(\FS[12] ), .D0(\FS[9] ), .C0(\FS[10] ), .B0(\FS[11] ), + .A0(\FS_RNIGOCT[12] ), .F0(\wb_dati_5_1_iv_0_RNO[7] ), + .F1(\FS_RNIGOCT[12] )); + SLICE_75 SLICE_75( .D1(m3_0_a2_0), .C1(Ready), .B1(CO0), .A1(CBR_fast), + .D0(nRWE_s_i_tz_0), .C0(N_142), .B0(N_141), .A0(nRCAS_0_sqmuxa_1), + .F0(N_252_i), .F1(nRCAS_0_sqmuxa_1)); + SLICE_76 SLICE_76( .C1(N_482), .B1(N_457), .A1(\MAin_c[1] ), + .D0(un1_CmdEnable20_0_0_a2_1_1), .C0(un1_CmdEnable20_0_0_0), .B0(N_367), + .A0(C1Submitted), .M1(nCCAS_c_i), .M0(nCCAS_c_i), .CLK(nCRAS_c), + .F0(un1_CmdEnable20_i), .Q0(CBR), .F1(un1_CmdEnable20_0_0_a2_1_1), .Q1(CBR_fast)); - SLICE_74 SLICE_74( .D1(N_134), .C1(\Din_c[5] ), .B1(\Din_c[4] ), - .A1(\Din_c[3] ), .D0(N_382), .C0(N_380), .B0(\MAin_c[1] ), .A0(CmdEnable), - .F0(CmdUFMData_1_sqmuxa), .F1(N_380)); - SLICE_75 SLICE_75( .D1(un1_ADWR_i_o2_11), .C1(un1_ADWR_i_o2_10), - .B1(\Bank[3] ), .A1(\Bank[1] ), .B0(N_294), .A0(\MAin_c[0] ), .F0(N_382), - .F1(N_294)); - SLICE_76 SLICE_76( .B1(N_374), .A1(\MAin_c[1] ), .D0(N_393), .C0(N_378), - .B0(N_294), .A0(ADSubmitted), .M0(CASr2), .CLK(RCLK_c), - .F0(CmdEnable_0_sqmuxa), .Q0(CASr3), .F1(N_378)); - SLICE_77 SLICE_77( .C1(\FS[14] ), .B1(N_132), .A1(\wb_adr_5_i_i_a2_6_0[0] ), - .D0(\wb_adr_5_i_i_1[0] ), .C0(N_384), .B0(N_315), .A0(N_314), - .F0(\wb_adr_5_i_i_5[0] ), .F1(N_314)); - SLICE_78 SLICE_78( .B1(Ready), .A1(N_43), .D0(IS_0_sqmuxa_0_o2), + SLICE_77 SLICE_77( .D1(\Din_c[3] ), .C1(\Din_c[5] ), .B1(\Din_c[4] ), + .A1(N_353), .B0(XOR8MEG18), .A0(N_461), .M0(CASr2), .CLK(RCLK_c), + .F0(CmdUFMData_1_sqmuxa), .Q0(CASr3), .F1(N_461)); + SLICE_78 SLICE_78( .B1(FWEr), .A1(CO0), .D0(nRCS_9_u_i_0), .C0(N_251_i_1), + .B0(N_142), .A0(N_141), .F0(N_37_i), .F1(N_251_i_1)); + SLICE_79 SLICE_79( .B1(Ready), .A1(IS_0_sqmuxa_0_o2), .D0(IS_0_sqmuxa_0_o3), .C0(\IS[3] ), .B0(\IS[2] ), .A0(\IS[1] ), .F0(RA10s_i), - .F1(IS_0_sqmuxa_0_o2)); - SLICE_79 SLICE_79( .C1(\FS[9] ), .B1(N_132), .A1(\FS[10] ), - .D0(\wb_adr_5_i_i_a2_6_0[0] ), .C0(N_383), .B0(N_367), .A0(N_348_2), - .F0(\wb_dati_5_1_iv_0_2[4] ), .F1(N_383)); - SLICE_80 SLICE_80( .B1(\FS[10] ), .A1(\FS[9] ), .D0(N_367), .C0(N_125), - .B0(\FS[12] ), .A0(\FS[11] ), .F0(N_233), .F1(N_125)); - SLICE_81 SLICE_81( .D1(nRCS_9_u_i_0), .C1(N_37_i_1), .B1(nRCS_0io_RNO_0), - .A1(N_28_i_1), .D0(nRCS_9_u_i_0_0), .C0(N_49), .B0(N_43), .A0(\IS[0] ), - .F0(nRCS_9_u_i_0), .F1(N_28_i)); - SLICE_82 SLICE_82( .B1(\FS[12] ), .A1(\FS[11] ), .D0(N_383), .C0(N_376), - .B0(\FS[14] ), .A0(\FS[13] ), .F0(N_345), .F1(N_376)); - SLICE_83 SLICE_83( .D1(\FS[9] ), .C1(\FS[10] ), .B1(\FS[11] ), .A1(\FS[12] ), - .D0(N_394), .C0(N_226), .B0(N_133), .A0(N_132), - .F0(\wb_dati_5_1_iv_0_o2_0[5] ), .F1(N_394)); - SLICE_84 SLICE_84( .B1(N_132), .A1(\FS[14] ), - .D0(\wb_dati_5_1_iv_0_a2_1[6] ), .C0(\wb_dati[5] ), .B0(N_362), - .A0(InitReady), .F0(\wb_dati_5_1_iv_0_0[6] ), .F1(N_362)); - SLICE_85 SLICE_85( .D1(N_132), .C1(N_125), .B1(\FS[13] ), .A1(\FS[12] ), - .D0(\wb_dati[7] ), .C0(\wb_adr_5_i_i_1_0[0] ), .B0(N_307), .A0(InitReady), - .F0(\wb_adr_5_i_i_1[0] ), .F1(N_307)); - SLICE_86 SLICE_86( .B1(\FS[14] ), .A1(\FS[13] ), - .D0(\wb_adr_5_i_i_1_0_tz_0[0] ), .C0(N_133), .B0(N_132), .A0(\FS[12] ), - .F0(\wb_adr_5_i_i_1_0[0] ), .F1(N_133)); - SLICE_87 SLICE_87( .B1(wb_req), .A1(\FS[0] ), .D0(wb_ack), .C0(N_330_4), - .B0(N_295), .A0(N_132), .F0(N_103), .F1(N_295)); - SLICE_88 SLICE_88( .B1(N_132), .A1(\FS[9] ), .D0(N_375), .C0(\FS[13] ), - .B0(\FS[11] ), .A0(\FS[10] ), .F0(N_315), .F1(N_375)); - SLICE_89 SLICE_89( .D1(\MAin_c[7] ), .C1(\MAin_c[5] ), .B1(\MAin_c[4] ), - .A1(\MAin_c[2] ), .D0(un1_ADWR_i_o2_4), .C0(un1_ADWR_i_o2_3), - .B0(\Bank[2] ), .A0(\Bank[0] ), .F0(un1_ADWR_i_o2_10), - .F1(un1_ADWR_i_o2_4)); - SLICE_90 SLICE_90( .D1(\IS[0] ), .C1(N_43), .B1(N_49), .A1(nRCS_9_u_i_0_0), - .D0(Ready), .C0(RCKE_c), .B0(RASr2), .A0(N_41), .F0(nRCS_9_u_i_0_0), - .F1(N_25_i)); - SLICE_91 SLICE_91( .B1(\FS[7] ), .A1(\FS[6] ), - .D0(wb_cyc_stb_2_sqmuxa_i_a2_3_4), .C0(wb_cyc_stb_2_sqmuxa_i_a2_3_3), - .B0(\FS[8] ), .A0(\FS[3] ), .F0(N_330_4), - .F1(wb_cyc_stb_2_sqmuxa_i_a2_3_3)); - SLICE_92 SLICE_92( .D1(nRCAS_0_sqmuxa_1), .C1(nRWE_0io_RNO_0), .B1(N_37_i_1), - .A1(N_28_i_1), .D0(FWEr_fast), .C0(CO0), .B0(CASr3), .A0(CASr2), - .F0(N_37_i_1), .F1(N_37_i)); - SLICE_93 SLICE_93( .B1(\Din_c[4] ), .A1(\Din_c[0] ), .D0(N_381), .C0(N_371), - .B0(N_134), .A0(\Din_c[3] ), .F0(XOR8MEG_3_u_0_a2_0_2), .F1(N_371)); - SLICE_94 SLICE_94( .B1(\FS[10] ), .A1(\FS[9] ), .D0(N_141), .C0(\FS[13] ), - .B0(\FS[12] ), .A0(\FS[11] ), .F0(\wb_dati_5_1_iv_0_a2_1[6] ), .F1(N_141)); - SLICE_95 SLICE_95( .B1(PHI2r3), .A1(PHI2r2), .D0(InitReady), - .C0(G_8_0_a3_0_0), .B0(CmdValid_fast), .A0(CmdUFMShift), .F0(N_122), - .F1(G_8_0_a3_0_0)); - SLICE_96 SLICE_96( .D1(nRCAS_0io_RNO_1), .C1(FWEr), .B1(CO0), .A1(CBR), - .D0(\S[1] ), .C0(N_242_i_1), .B0(nRCAS_0_sqmuxa_1), .A0(N_39), - .F0(N_242_i), .F1(N_242_i_1)); - SLICE_97 SLICE_97( .C1(PHI2r3), .B1(PHI2r2), .A1(CmdValid), .D0(PHI2r3), - .C0(PHI2r2), .B0(InitReady), .A0(CmdValid), .F0(N_94_i), .F1(un1_PHI2r3)); - SLICE_98 SLICE_98( .C1(\FS[12] ), .B1(\FS[10] ), .A1(\FS[9] ), .D0(\FS[12] ), - .C0(\FS[11] ), .B0(\FS[10] ), .A0(\FS[9] ), .F0(N_223), - .F1(\wb_adr_5_i_i_a2_6_0[0] )); - SLICE_99 SLICE_99( .C1(N_132), .B1(\FS[14] ), .A1(\FS[13] ), .D0(N_394), - .C0(N_132), .B0(\FS[14] ), .A0(\FS[13] ), .F0(N_303), .F1(N_367)); - SLICE_100 SLICE_100( .D1(\FS[14] ), .C1(\FS[13] ), .B1(\FS[12] ), - .A1(\FS[11] ), .D0(\FS[14] ), .C0(\FS[12] ), .B0(\FS[11] ), .A0(\FS[10] ), - .F0(N_129), .F1(\wb_dati_5_0_iv_0_a2_0[0] )); - SLICE_101 SLICE_101( .B1(\FS[12] ), .A1(\FS[11] ), .D0(N_362), .C0(N_125), - .B0(\FS[12] ), .A0(\FS[11] ), .F0(N_341), .F1(N_142)); - SLICE_102 SLICE_102( .B1(nRowColSel), .A1(\MAin_c[9] ), .B0(nRowColSel), + .F1(IS_0_sqmuxa_0_o3)); + SLICE_80 SLICE_80( .D1(\Bank[6] ), .C1(\Bank[5] ), .B1(\Bank[3] ), + .A1(\Bank[2] ), .D0(un1_CmdEnable20_0_0_o2_11), + .C0(un1_CmdEnable20_0_0_o2_10), .B0(\Bank[4] ), .A0(\Bank[0] ), .F0(N_367), + .F1(un1_CmdEnable20_0_0_o2_11)); + SLICE_81 SLICE_81( .D1(\wb_dati_5_1_iv_0_a2_12[3] ), + .C1(\wb_dati_5_1_iv_0_a2_7[4] ), .B1(\wb_dati_5_1_iv_0_a2_6[4] ), + .A1(\FS[10] ), .D0(\wb_dati[5] ), .C0(\wb_dati_5_1_iv_0_0_a2[6] ), + .B0(\wb_dati_5_1_iv_0_a2_2[4] ), .A0(InitReady), + .F0(\wb_dati_5_1_iv_0_0_1[6] ), .F1(\wb_dati_5_1_iv_0_a2_2[4] )); + SLICE_82 SLICE_82( .D1(\wb_dati_5_1_iv_0_a2_0_0[7] ), .C1(\FS_RNIHVJI[15] ), + .B1(\FS[10] ), .A1(\FS[9] ), .D0(\wb_dati[6] ), + .C0(\wb_dati_5_1_iv_0_1_RNO[7] ), .B0(\wb_dati_5_1_iv_0_a2_0[7] ), + .A0(InitReady), .F0(\wb_dati_5_1_iv_0_1[7] ), + .F1(\wb_dati_5_1_iv_0_a2_0[7] )); + SLICE_83 SLICE_83( .C1(\IS[3] ), .B1(\IS[2] ), .A1(\IS[1] ), + .D0(nRCS_9_u_i_0_0), .C0(un1_nRCAS_6_sqmuxa_i_o2), .B0(IS_0_sqmuxa_0_o2), + .A0(\IS[0] ), .F0(nRCS_9_u_i_0), .F1(un1_nRCAS_6_sqmuxa_i_o2)); + SLICE_84 SLICE_84( .C1(\FS[14] ), .B1(\FS_RNIHVJI[15] ), .A1(\FS[12] ), + .D0(\wb_dati_5_1_iv_0_a2_13[3] ), .C0(\wb_dati_5_1_iv_0_o2_0[7] ), + .B0(\FS[13] ), .A0(\FS[11] ), .F0(\wb_dati_5_1_iv_0_0_a2[6] ), + .F1(\wb_dati_5_1_iv_0_a2_13[3] )); + SLICE_85 SLICE_85( .D1(\FS[14] ), .C1(\FS[12] ), .B1(\FS[11] ), + .A1(\FS[10] ), .D0(\wb_dati_5_1_iv_0_0[1] ), + .C0(\wb_dati_5_1_iv_0_a2_12[3] ), .B0(\wb_dati_5_1_iv_0_0_o2[3] ), + .A0(\FS[13] ), .F0(\wb_dati_5_1_iv_0_1[1] ), + .F1(\wb_dati_5_1_iv_0_0_o2[3] )); + SLICE_86 SLICE_86( .D1(\FS_RNI7U6M[14] ), .C1(\FS_RNIS637[9] ), + .B1(\FS[12] ), .A1(\FS[11] ), .C0(\wb_dati[2] ), + .B0(\wb_dati_5_1_iv_0_a2_7[3] ), .A0(InitReady), + .F0(\wb_dati_5_1_iv_0_0_0[3] ), .F1(\wb_dati_5_1_iv_0_a2_7[3] )); + SLICE_87 SLICE_87( .B1(\FS_RNIHVJI[15] ), .A1(\FS[9] ), + .D0(\wb_dati_5_1_iv_0_a2_12[3] ), .C0(\wb_dati_5_1_iv_0_a2_5[3] ), + .B0(\wb_dati_5_1_iv_0_0_o2[3] ), .A0(\FS[13] ), + .F0(\wb_dati_5_1_iv_0_0_1[3] ), .F1(\wb_dati_5_1_iv_0_a2_12[3] )); + SLICE_88 SLICE_88( .B1(\FS_RNIHVJI[15] ), .A1(\FS[14] ), + .D0(\wb_dati_5_1_iv_0_a2_11[3] ), .C0(\FS_RNI7U6M[14] ), + .B0(\FS_RNIS637[9] ), .A0(\FS[11] ), .F0(\wb_dati_5_1_iv_0_a2_5[3] ), + .F1(\FS_RNI7U6M[14] )); + SLICE_89 SLICE_89( .C1(wb_req), .B1(N_99_1), .A1(\FS[0] ), + .D0(wb_cyc_stb_2_sqmuxa_i_0_0_a2_0), .C0(wb_ack), .B0(\FS_RNIHVJI[15] ), + .A0(N_99_2), .F0(wb_cyc_stb_2_sqmuxa_i_0_0), + .F1(wb_cyc_stb_2_sqmuxa_i_0_0_a2_0)); + SLICE_90 SLICE_90( .D1(nFWE_c), .C1(\MAin_c[7] ), .B1(\MAin_c[6] ), + .A1(\MAin_c[4] ), .D0(un1_CmdEnable20_0_0_o2_4), + .C0(un1_CmdEnable20_0_0_o2_3), .B0(\Bank[7] ), .A0(\Bank[1] ), + .F0(un1_CmdEnable20_0_0_o2_10), .F1(un1_CmdEnable20_0_0_o2_4)); + SLICE_91 SLICE_91( .C1(\FS[17] ), .B1(\FS[16] ), .A1(\FS[15] ), + .D0(\wb_dati[7] ), .C0(\wb_adr_5_i_0_0[0] ), .B0(\FS_RNI82PA[15] ), + .A0(InitReady), .F0(\wb_adr_5_i_0_2[0] ), .F1(\FS_RNI82PA[15] )); + SLICE_92 SLICE_92( .B1(\Din_c[5] ), .A1(\Din_c[3] ), .D0(N_442), + .C0(\MAin_c[0] ), .B0(\Din_c[6] ), .A0(\Din_c[2] ), .F0(N_482), .F1(N_442)); + SLICE_93 SLICE_93( .D1(\wb_dati_5_1_iv_0_a2_11[3] ), .C1(wb_we_0_0_i_a2_0), + .B1(\wb_dati_5_1_iv_0_o2_0[4] ), .A1(InitReady), + .D0(\wb_adr_5_i_0_a2_6[0] ), .C0(\FS_RNIS637[9] ), .B0(\FS[13] ), + .A0(\FS[12] ), .F0(wb_we_0_0_i_a2_0), .F1(wb_we_0_0_i_1_1)); + SLICE_94 SLICE_94( .B1(InitReady), .A1(\FS[14] ), + .D0(\wb_adr_5_i_3_0_a2_3[1] ), .C0(\FS[17] ), .B0(\FS[16] ), .A0(\FS[15] ), + .F0(wb_rst_3), .F1(\wb_adr_5_i_3_0_a2_3[1] )); + SLICE_95 SLICE_95( .B1(\FS[7] ), .A1(\FS[1] ), + .D0(wb_cyc_stb_2_sqmuxa_i_a2_2_0), .C0(\FS[5] ), .B0(\FS[4] ), + .A0(\FS[2] ), .F0(N_99_2), .F1(wb_cyc_stb_2_sqmuxa_i_a2_2_0)); + SLICE_96 SLICE_96( .B1(\Din_c[7] ), .A1(\Din_c[6] ), .D0(N_466), .C0(N_452), + .B0(N_353), .A0(\Din_c[3] ), .F0(XOR8MEG_3_u_0_0_a2_0_2), .F1(N_353)); + SLICE_97 SLICE_97( .B1(\FS[10] ), .A1(\FS[9] ), + .D0(\wb_dati_5_1_iv_0_a2_7[4] ), .C0(\wb_dati_5_1_iv_0_o2_0[7] ), + .B0(\FS[13] ), .A0(\FS[11] ), .F0(\wb_dati_5_1_iv_0_a2_0_2[1] ), + .F1(\wb_dati_5_1_iv_0_o2_0[7] )); + SLICE_98 SLICE_98( .B1(\FS[13] ), .A1(\FS[11] ), + .D0(\wb_dati_5_1_iv_0_a2_6[4] ), .C0(\FS[14] ), .B0(\FS[12] ), + .A0(\FS[10] ), .F0(\wb_dati_5_0_iv_0_a2_1[0] ), + .F1(\wb_dati_5_1_iv_0_a2_6[4] )); + SLICE_99 SLICE_99( .D1(\FS_RNI9Q57[12] ), .C1(InitReady3_0_a2_1_0), + .B1(\FS[14] ), .A1(\FS[11] ), .D0(\FS[17] ), .C0(\FS[16] ), .B0(\FS[15] ), + .A0(\FS[10] ), .F0(InitReady3_0_a2_1_0), .F1(InitReady3)); + SLICE_100 SLICE_100( .B1(PHI2r3), .A1(PHI2r2), .D0(InitReady), + .C0(G_4_0_a3_0), .B0(CmdValid_fast), .A0(CmdUFMShift), .F0(N_126_i), + .F1(G_4_0_a3_0)); + SLICE_101 SLICE_101( .D1(nRCS_9_u_i_o3_0_2), .C1(N_251_i_sx), + .B1(N_251_i_1_0), .A1(N_251_i_1), .C0(\S[1] ), .B0(nRCAS_0_sqmuxa_1), + .A0(N_48), .F0(N_251_i_sx), .F1(N_251_i)); + SLICE_102 SLICE_102( .D1(\FS[12] ), .C1(\FS[14] ), .B1(\FS[13] ), + .A1(\FS[11] ), .D0(wb_ack), .C0(\FS[14] ), .B0(\FS[13] ), .A0(\FS[12] ), + .F0(\ufmefb/g0_0_a3_2 ), .F1(\wb_dati_5_1_iv_0_a2_0_0[7] )); + SLICE_103 SLICE_103( .D1(\S[1] ), .C1(FWEr), .B1(CO0), .A1(CASr2), .D0(FWEr), + .C0(CO0), .B0(CASr3), .A0(CASr2), .F0(N_142), .F1(RCKEEN_8_u_1)); + SLICE_104 SLICE_104( .D1(\FS[13] ), .C1(\FS[11] ), .B1(\FS[10] ), + .A1(\FS[9] ), .C0(\FS[13] ), .B0(\FS[11] ), .A0(\FS[10] ), + .F0(\wb_dati_5_1_iv_0_a2_5[7] ), .F1(\wb_dati_5_1_iv_0_0_a2_1[3] )); + SLICE_105 SLICE_105( .B1(\FS[13] ), .A1(\FS[12] ), .D0(\FS_RNIOVGI[9] ), + .C0(\FS[14] ), .B0(\FS[13] ), .A0(\FS[12] ), .F0(\wb_adr_5_i_3_0_a2[1] ), + .F1(\FS_RNI9Q57[12] )); + SLICE_106 SLICE_106( .C1(\S[1] ), .B1(Ready), .A1(CBR), .D0(nCRAS_c), + .C0(Ready), .B0(LEDEN), .A0(CBR), .F0(LED_c), .F1(N_141)); + SLICE_107 SLICE_107( .B1(InitReady), .A1(\FS[14] ), .D0(\FS_RNIF2MA[9] ), + .C0(InitReady), .B0(\FS[14] ), .A0(\FS[13] ), + .F0(\wb_adr_5_i_3_0_a2_0[1] ), .F1(\wb_adr_5_i_0_a2_6[0] )); + SLICE_108 SLICE_108( .B1(nRowColSel), .A1(\MAin_c[9] ), .B0(nRowColSel), .A0(\MAin_c[9] ), .F0(RDQMH_c), .F1(RDQML_c)); - SLICE_103 SLICE_103( .D1(\FS[17] ), .C1(\FS[16] ), .B1(\FS[15] ), - .A1(\FS[10] ), .C0(InitReady), .B0(\FS[17] ), .A0(\FS[16] ), .F0(N_131), - .F1(InitReady3_0_a2_2)); - SLICE_104 SLICE_104( .D1(\Din_c[6] ), .C1(\Din_c[7] ), .B1(\Din_c[4] ), - .A1(\Din_c[5] ), .B0(\Din_c[7] ), .A0(\Din_c[6] ), .F0(N_134), - .F1(CmdLEDEN_4_u_i_a2_0_0)); - SLICE_105 SLICE_105( .B1(FWEr), .A1(CO0), .D0(\S[1] ), .C0(FWEr), .B0(CO0), - .A0(CASr2), .F0(RCKEEN_8_u_1), .F1(nRCS_0io_RNO_0)); - SLICE_106 SLICE_106( .D1(\MAin_c[0] ), .C1(N_294), .B1(CmdEnable), - .A1(\MAin_c[1] ), .D0(un1_CmdEnable20_0_a2_3_0), .C0(\MAin_c[0] ), - .B0(\Din_c[6] ), .A0(\Din_c[2] ), .F0(un1_CmdEnable20_0_a2_1_0), - .F1(XOR8MEG18)); - SLICE_107 SLICE_107( .D1(N_132), .C1(N_125), .B1(\FS[14] ), .A1(\FS[13] ), - .C0(N_383), .B0(\FS[13] ), .A0(\FS[12] ), .F0(N_313), .F1(N_384)); - SLICE_108 SLICE_108( .C1(\wb_dato[0] ), .B1(InitReady), .A1(Cmdn8MEGEN), - .D0(\wb_dati_5_1_iv_0_a2_3_0[7] ), .C0(\wb_dati[6] ), .B0(N_132), - .A0(InitReady), .F0(\wb_dati_5_1_iv_0_0[7] ), .F1(n8MEGENe_1_0)); - SLICE_109 SLICE_109( .C1(nRowColSel), .B1(\RowA[3] ), .A1(\MAin_c[3] ), - .C0(nFWE_c), .B0(\MAin_c[6] ), .A0(\MAin_c[3] ), .F0(un1_ADWR_i_o2_3), - .F1(\RA_c[3] )); - SLICE_110 SLICE_110( .C1(nRowColSel), .B1(\RowA[8] ), .A1(\MAin_c[8] ), - .C0(nRowColSel), .B0(\RowA[9] ), .A0(\MAin_c[9] ), .F0(\RA_c[9] ), + SLICE_109 SLICE_109( .D1(\Din_c[0] ), .C1(\Din_c[4] ), .B1(\Din_c[1] ), + .A1(\Din_c[7] ), .B0(\Din_c[4] ), .A0(\Din_c[0] ), .F0(N_452), .F1(N_457)); + SLICE_110 SLICE_110( .B1(PHI2r3), .A1(PHI2r2), .C0(PHI2r3), .B0(PHI2r2), + .A0(CmdValid), .F0(un1_PHI2r3_i_li), .F1(g1_0)); + SLICE_111 SLICE_111( .C1(\wb_dato[0] ), .B1(InitReady), .A1(Cmdn8MEGEN), + .D0(\wb_dati[3] ), .C0(\wb_dati_5_1_iv_0_a2_2[4] ), + .B0(\wb_dati_5_1_iv_0_o2_0_RNIMDJC1[4] ), .A0(InitReady), + .F0(\wb_dati_5_1_iv_0_0_1[4] ), .F1(n8MEGENe_1_0)); + SLICE_112 SLICE_112( .C1(nRowColSel), .B1(\RowA[2] ), .A1(\MAin_c[2] ), + .C0(\MAin_c[5] ), .B0(\MAin_c[3] ), .A0(\MAin_c[2] ), + .F0(un1_CmdEnable20_0_0_o2_3), .F1(\RA_c[2] )); + SLICE_113 SLICE_113( .C1(nRowColSel), .B1(\RowA[8] ), .A1(\MAin_c[8] ), + .C0(nRowColSel), .B0(\RowA[0] ), .A0(\MAin_c[0] ), .F0(\RA_c[0] ), .F1(\RA_c[8] )); - SLICE_111 SLICE_111( .C1(nRowColSel), .B1(\RowA[0] ), .A1(\MAin_c[0] ), - .C0(nRowColSel), .B0(\RowA[7] ), .A0(\MAin_c[7] ), .F0(\RA_c[7] ), - .F1(\RA_c[0] )); - SLICE_112 SLICE_112( .C1(nRowColSel), .B1(\RowA[1] ), .A1(\MAin_c[1] ), - .C0(nRowColSel), .B0(\RowA[6] ), .A0(\MAin_c[6] ), .F0(\RA_c[6] ), - .F1(\RA_c[1] )); - SLICE_113 SLICE_113( .C1(nRowColSel), .B1(\RowA[2] ), .A1(\MAin_c[2] ), + SLICE_114 SLICE_114( .C1(nRowColSel), .B1(\RowA[3] ), .A1(\MAin_c[3] ), + .C0(nRowColSel), .B0(\RowA[1] ), .A0(\MAin_c[1] ), .F0(\RA_c[1] ), + .F1(\RA_c[3] )); + SLICE_115 SLICE_115( .C1(nRowColSel), .B1(\RowA[9] ), .A1(\MAin_c[9] ), + .C0(nRowColSel), .B0(\RowA[4] ), .A0(\MAin_c[4] ), .F0(\RA_c[4] ), + .F1(\RA_c[9] )); + SLICE_116 SLICE_116( .C1(nRowColSel), .B1(\RowA[7] ), .A1(\MAin_c[7] ), .C0(nRowColSel), .B0(\RowA[5] ), .A0(\MAin_c[5] ), .F0(\RA_c[5] ), - .F1(\RA_c[2] )); - SLICE_114 SLICE_114( .A1(\IS[0] ), .C0(\IS[2] ), .B0(\IS[1] ), .A0(\IS[0] ), - .F0(nRWE_0io_RNO_1), .F1(\IS_i[0] )); - SLICE_115 SLICE_115( .B1(Ready_fast), .A1(\CROW_c[0] ), .D0(n8MEGEN), + .F1(\RA_c[7] )); + SLICE_117 SLICE_117( .B1(\S[1] ), .A1(CO0), .B0(CO0), .A0(CASr2), + .F0(RCKEEN_8_u_0_o3), .F1(N_70_i)); + SLICE_118 SLICE_118( .B1(\FS[14] ), .A1(\FS[12] ), .B0(\FS[13] ), + .A0(\FS[12] ), .F0(\wb_dati_5_1_iv_0_a2_11[3] ), + .F1(\wb_dati_5_1_iv_0_a2_7[4] )); + SLICE_119 SLICE_119( .D1(\Din_c[6] ), .C1(\Din_c[7] ), .B1(\Din_c[4] ), + .A1(\Din_c[5] ), .B0(\Din_c[5] ), .A0(\Din_c[2] ), .F0(N_466), + .F1(CmdLEDEN_4_u_i_m2_i_a2_0_0)); + SLICE_120 SLICE_120( .B1(Ready_fast), .A1(\CROW_c[1] ), .D0(n8MEGEN), .C0(XOR8MEG), .B0(Ready_fast), .A0(\Din_c[6] ), .F0(RA11d_0), - .F1(\RBAd_0[0] )); - SLICE_116 SLICE_116( .B1(\wb_dati[0] ), .A1(InitReady), .B0(PHI2r3), - .A0(PHI2r2), .F0(g1_0), .F1(N_302)); - SLICE_117 SLICE_117( .C1(\S[1] ), .B1(Ready), .A1(CBR_fast), .B0(CASr3), - .A0(CASr2), .F0(nRCAS_0io_RNO_1), .F1(N_28_i_1)); + .F1(\RBAd_0[1] )); + SLICE_121 SLICE_121( .B1(wb_req), .A1(\FS[0] ), .C0(\FS[8] ), .B0(\FS[6] ), + .A0(\FS[3] ), .F0(N_99_1), .F1(wb_cyc_stb_4_iv_0_0_a2_0_0)); + SLICE_122 SLICE_122( .C1(\wb_adr[0] ), .B1(\FS_RNI82PA[15] ), .A1(InitReady), + .B0(IS_0_sqmuxa_0_o2), .A0(Ready), .F0(N_261_i), .F1(N_216)); RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .IOLDO(\WRD[0] ), .PADDT(RD_1_i), .RD0(RD[0])); RD_0__MGIOL \RD[0]_MGIOL ( .IOLDO(\WRD[0] ), .OPOS(\Din_c[0] ), @@ -460,18 +527,18 @@ module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, RDQML RDQML_I( .PADDO(RDQML_c), .RDQML(RDQML)); RDQMH RDQMH_I( .PADDO(RDQMH_c), .RDQMH(RDQMH)); nRCAS nRCAS_I( .IOLDO(nRCAS_c), .nRCAS(nRCAS)); - nRCAS_MGIOL nRCAS_MGIOL( .IOLDO(nRCAS_c), .OPOS(N_242_i), .CLK(RCLK_c)); + nRCAS_MGIOL nRCAS_MGIOL( .IOLDO(nRCAS_c), .OPOS(N_251_i), .CLK(RCLK_c)); nRRAS nRRAS_I( .IOLDO(nRRAS_c), .nRRAS(nRRAS)); - nRRAS_MGIOL nRRAS_MGIOL( .IOLDO(nRRAS_c), .OPOS(N_25_i), .CLK(RCLK_c)); + nRRAS_MGIOL nRRAS_MGIOL( .IOLDO(nRRAS_c), .OPOS(N_32_i), .CLK(RCLK_c)); nRWE nRWE_I( .IOLDO(nRWE_c), .nRWE(nRWE)); - nRWE_MGIOL nRWE_MGIOL( .IOLDO(nRWE_c), .OPOS(N_37_i), .CLK(RCLK_c)); + nRWE_MGIOL nRWE_MGIOL( .IOLDO(nRWE_c), .OPOS(N_252_i), .CLK(RCLK_c)); RCKE RCKE_I( .PADDO(RCKE_c), .RCKE(RCKE)); RCLKout RCLKout_I( .IOLDO(RCLKout_c), .RCLKout(RCLKout)); RCLKout_MGIOL RCLKout_MGIOL( .IOLDO(RCLKout_c), .ONEG(VCC), .OPOS(GND), .CLK(RCLK_c)); RCLK RCLK_I( .PADDI(RCLK_c), .RCLK(RCLK)); nRCS nRCS_I( .IOLDO(nRCS_c), .nRCS(nRCS)); - nRCS_MGIOL nRCS_MGIOL( .IOLDO(nRCS_c), .OPOS(N_28_i), .CLK(RCLK_c)); + nRCS_MGIOL nRCS_MGIOL( .IOLDO(nRCS_c), .OPOS(N_37_i), .CLK(RCLK_c)); RD_7_ \RD[7]_I ( .PADDI(\RD_in[7] ), .IOLDO(\WRD[7] ), .PADDT(RD_1_i), .RD7(RD[7])); RD_7__MGIOL \RD[7]_MGIOL ( .IOLDO(\WRD[7] ), .OPOS(\Din_c[7] ), @@ -914,9 +981,9 @@ endmodule module SLICE_10 ( input B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly; - lut4 ADSubmitted_r_0_RNO( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut4 un1_ADWR_i_i_a2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40003 ADSubmitted_r_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40003 ADSubmitted_r_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre ADSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -956,7 +1023,7 @@ module SLICE_11 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly; - lut40004 CmdEnable16_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40004 CmdEnable16_0_a2_1_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40005 C1Submitted_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre C1Submitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); @@ -983,7 +1050,7 @@ endmodule module lut40004 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40005 ( input A, B, C, D, output Z ); @@ -1023,10 +1090,10 @@ module SLICE_16 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; - lut40007 Ready_0_sqmuxa_0_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40008 \S_RNO[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40004 Ready_0_sqmuxa_0_a2_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40007 \S_RNO[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0009 \S[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + vmuxregsre0008 \S[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); @@ -1051,15 +1118,10 @@ endmodule module lut40007 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40008 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module vmuxregsre0009 ( input D0, D1, SD, SP, CK, LSR, output Q ); +module vmuxregsre0008 ( input D0, D1, SD, SP, CK, LSR, output Q ); FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); defparam INST01.GSR = "DISABLED"; @@ -1069,8 +1131,9 @@ module SLICE_17 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly; - lut40010 CmdEnable_s_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40011 CmdEnable_s( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40004 un1_CmdEnable20_0_0_a2_3_RNIJ3N91( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40009 CmdEnable_s( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre CmdEnable( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1094,12 +1157,7 @@ module SLICE_17 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, endmodule -module lut40010 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0203) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40011 ( input A, B, C, D, output Z ); +module lut40009 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFFCA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule @@ -1108,8 +1166,8 @@ module SLICE_18 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; - lut40012 CmdLEDEN_4_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40013 CmdLEDEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40010 CmdLEDEN_4_u_i_m2_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40011 CmdLEDEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre CmdLEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); @@ -1133,28 +1191,28 @@ module SLICE_18 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, endmodule -module lut40012 ( input A, B, C, D, output Z ); +module lut40010 ( input A, B, C, D, output Z ); ROM16X1A #(16'h5D0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40013 ( input A, B, C, D, output Z ); +module lut40011 ( input A, B, C, D, output Z ); ROM16X1A #(16'h4545) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_19 ( input M0, CE, CLK, output F0, Q0, F1 ); +module SLICE_19 ( input A0, M0, CE, CLK, output F0, Q0 ); wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; - lut40014 GND( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F1)); + lut40006 RA10_0io_RNO( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40015 VCC( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre CmdUFMData( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); specify + (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); @@ -1164,33 +1222,18 @@ module SLICE_19 ( input M0, CE, CLK, output F0, Q0, F1 ); endmodule -module lut40014 ( input A, B, C, D, output Z ); +module SLICE_20 ( input D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; - ROM16X1A #(16'h0000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40015 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_20 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output - F0, Q0, F1 ); - wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly; - - lut40016 un1_CmdEnable20_0_a2_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40017 CmdUFMShift_3_u_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40012 GND( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40013 CmdUFMShift_3_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre CmdUFMShift( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); @@ -1204,12 +1247,12 @@ module SLICE_20 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output endmodule -module lut40016 ( input A, B, C, D, output Z ); +module lut40012 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40017 ( input A, B, C, D, output Z ); +module lut40013 ( input A, B, C, D, output Z ); ROM16X1A #(16'hB3A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule @@ -1218,9 +1261,10 @@ module SLICE_21 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; - lut40018 CmdUFMWrite_3_u_0_a2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40014 CmdUFMWrite_3_u_0_0_0_a2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40019 CmdUFMWrite_3_u_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40015 CmdUFMWrite_3_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre CmdUFMWrite( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1242,12 +1286,12 @@ module SLICE_21 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, endmodule -module lut40018 ( input A, B, C, D, output Z ); +module lut40014 ( input A, B, C, D, output Z ); ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40019 ( input A, B, C, D, output Z ); +module lut40015 ( input A, B, C, D, output Z ); ROM16X1A #(16'hF4F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule @@ -1255,8 +1299,8 @@ endmodule module SLICE_22 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly; - lut40020 CmdValid_2_i_o2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40021 CmdValid_r( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40016 CmdValid_2_i_o2_0_o2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut4 CmdValid_r( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre CmdValid( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); @@ -1278,21 +1322,16 @@ module SLICE_22 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); endmodule -module lut40020 ( input A, B, C, D, output Z ); +module lut40016 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFF73) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40021 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module SLICE_23 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly; - lut40022 CmdEnable_RNI7PMB1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40021 CmdValid_r_fast( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40017 CmdUFMData_1_sqmuxa_0_a2_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut4 CmdValid_r_fast( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre CmdValid_fast( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); @@ -1314,17 +1353,17 @@ module SLICE_23 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); endmodule -module lut40022 ( input A, B, C, D, output Z ); +module lut40017 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_24 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; - lut40017 Cmdn8MEGEN_4_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40023 Cmdn8MEGEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40013 Cmdn8MEGEN_4_u_i_m2_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40018 Cmdn8MEGEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre Cmdn8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); @@ -1348,7 +1387,7 @@ module SLICE_24 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, endmodule -module lut40023 ( input A, B, C, D, output Z ); +module lut40018 ( input A, B, C, D, output Z ); ROM16X1A #(16'h5151) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule @@ -1356,9 +1395,9 @@ endmodule module SLICE_25 ( input B1, A1, A0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly; - lut40024 nCCAS_pad_RNI01SJ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40019 nCCAS_pad_RNI01SJ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40006 nFWE_pad_RNI420B( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); + lut40006 FWEr_RNO( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre FWEr( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1376,47 +1415,25 @@ module SLICE_25 ( input B1, A1, A0, DI0, CLK, output F0, Q0, F1 ); endmodule -module lut40024 ( input A, B, C, D, output Z ); +module lut40019 ( input A, B, C, D, output Z ); ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_26 ( input B1, A1, B0, A0, M0, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly; - - lut40018 \RBAd[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40021 XOR8MEG_3_u_0_a2_2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre FWEr_fast( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - endspecify - -endmodule - -module SLICE_27 ( input B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); +module SLICE_26 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, + F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly; - lut40021 IS_0_sqmuxa_0_o2_0_RNIS63D( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); + lut40020 nRRAS_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40021 \IS_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40025 \IS_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \IS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); @@ -1430,18 +1447,23 @@ module SLICE_27 ( input B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); endmodule -module lut40025 ( input A, B, C, D, output Z ); +module lut40020 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5051) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40021 ( input A, B, C, D, output Z ); ROM16X1A #(16'hA9A9) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_28 ( input C1, B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, +module SLICE_27 ( input C1, B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40026 \IS_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40022 \IS_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40027 IS_n1_0_x2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40023 IS_n1_0_x2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre \IS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1465,28 +1487,29 @@ module SLICE_28 ( input C1, B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, endmodule -module lut40026 ( input A, B, C, D, output Z ); +module lut40022 ( input A, B, C, D, output Z ); ROM16X1A #(16'h7878) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40027 ( input A, B, C, D, output Z ); +module lut40023 ( input A, B, C, D, output Z ); ROM16X1A #(16'h6666) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_29 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, - Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; +module SLICE_28 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; - lut40028 un1_nRCAS_6_sqmuxa_i_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 \IS_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40024 nRWE_s_i_a2_1_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40025 \IS_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \IS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -1503,21 +1526,21 @@ module SLICE_29 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, endmodule -module lut40028 ( input A, B, C, D, output Z ); +module lut40024 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40029 ( input A, B, C, D, output Z ); +module lut40025 ( input A, B, C, D, output Z ); ROM16X1A #(16'h6AAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_30 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); +module SLICE_29 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly; - lut40030 InitReady3_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40024 InitReady_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40026 \FS_RNIHVJI_0[15] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40019 InitReady_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre InitReady( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); @@ -1538,17 +1561,17 @@ module SLICE_30 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); endmodule -module lut40030 ( input A, B, C, D, output Z ); +module lut40026 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_31 ( input C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); +module SLICE_30 ( input C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly; - lut40031 LEDEN_6_i_m2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40027 LEDEN_6_i_m2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40032 LEDENe( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40028 LEDENe( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre LEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1568,23 +1591,22 @@ module SLICE_31 ( input C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); endmodule -module lut40031 ( input A, B, C, D, output Z ); +module lut40027 ( input A, B, C, D, output Z ); ROM16X1A #(16'hB8B8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40032 ( input A, B, C, D, output Z ); +module lut40028 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hE2E2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hCACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_32 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, - F1, Q1 ); +module SLICE_31 ( input B0, A0, M1, M0, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; - lut40033 \un9_RA_i_m2[4] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40029 VCC( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40034 un1_ADWR_i_o2_11( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40014 \RBAd[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre PHI2r3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1592,11 +1614,6 @@ module SLICE_32 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); @@ -1609,20 +1626,15 @@ module SLICE_32 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, endmodule -module lut40033 ( input A, B, C, D, output Z ); +module lut40029 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hACAC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40034 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_33 ( input C1, B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); +module SLICE_32 ( input C1, B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; - lut40035 LED_pad_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40030 \un9_RA_i_m2_i_m2[6] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40006 RASr_RNO( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre RASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), @@ -1646,31 +1658,26 @@ module SLICE_33 ( input C1, B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); endmodule -module lut40035 ( input A, B, C, D, output Z ); +module lut40030 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFBFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hACAC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_34 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0, - F1 ); - wire VCCI, GNDI, M0_dly, CLK_dly; +module SLICE_33 ( input C1, B1, A1, B0, A0, M0, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, M0_dly, CLK_dly; - lut40036 wb_cyc_stb_2_sqmuxa_i_a2_3_4( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40037 \wb_dati_5_1_iv_0_a2_1_1[7] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40031 \wb_adr_5_i_0_o2[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40014 CmdEnable_0_sqmuxa_0_a2_0_a2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre RASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); @@ -1681,22 +1688,17 @@ module SLICE_34 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0, endmodule -module lut40036 ( input A, B, C, D, output Z ); +module lut40031 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hB1B1) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40037 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_35 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, +module SLICE_34 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire VCCI, GNDI, DI0_dly, CLK_dly; - lut40038 RCKEEN_8_u_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40039 RCKEEN_8_u( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40032 RCKEEN_8_u_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40033 RCKEEN_8_u( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre RCKEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1719,22 +1721,22 @@ module SLICE_35 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, endmodule -module lut40038 ( input A, B, C, D, output Z ); +module lut40032 ( input A, B, C, D, output Z ); ROM16X1A #(16'h5072) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40039 ( input A, B, C, D, output Z ); +module lut40033 ( input A, B, C, D, output Z ); ROM16X1A #(16'hDCCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_36 ( input B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); +module SLICE_35 ( input B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly; - lut40040 nRWE_0io_RNO_2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut4 RASr2_RNI6PUF( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40041 RCKE_2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40034 RCKE_2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre RCKE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1754,23 +1756,18 @@ module SLICE_36 ( input B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); endmodule -module lut40040 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40041 ( input A, B, C, D, output Z ); +module lut40034 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFE30) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_37 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, +module SLICE_36 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly; - lut40042 Ready_0_sqmuxa_0_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40035 Ready_0_sqmuxa_0_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40043 Ready_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40036 Ready_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre Ready( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1791,21 +1788,21 @@ module SLICE_37 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, endmodule -module lut40042 ( input A, B, C, D, output Z ); +module lut40035 ( input A, B, C, D, output Z ); ROM16X1A #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40043 ( input A, B, C, D, output Z ); +module lut40036 ( input A, B, C, D, output Z ); ROM16X1A #(16'hAEAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_38 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); +module SLICE_37 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly; - lut40016 Ready_0_sqmuxa_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40024 Ready_fast_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40037 Ready_0_sqmuxa_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40019 Ready_fast_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre Ready_fast( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); @@ -1826,12 +1823,17 @@ module SLICE_38 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); endmodule -module SLICE_39 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); +module lut40037 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_38 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly; - lut40018 \RowAd[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40014 \RowAd[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40018 \RowAd[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40014 \RowAd[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre \RowA[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1854,12 +1856,12 @@ module SLICE_39 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); endmodule -module SLICE_40 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); +module SLICE_39 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly; - lut40018 \RowAd[3] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40014 \RowAd[3] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40018 \RowAd[2] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40014 \RowAd[2] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre \RowA[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1882,12 +1884,12 @@ module SLICE_40 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); endmodule -module SLICE_41 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); +module SLICE_40 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly; - lut40044 \RowAd[5] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40038 \RowAd[5] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40018 \RowAd[4] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40014 \RowAd[4] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre \RowA[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1910,17 +1912,17 @@ module SLICE_41 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); endmodule -module lut40044 ( input A, B, C, D, output Z ); +module lut40038 ( input A, B, C, D, output Z ); ROM16X1A #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_42 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); +module SLICE_41 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly; - lut40018 \RowAd[7] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40014 \RowAd[7] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40018 \RowAd[6] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40014 \RowAd[6] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre \RowA[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1943,12 +1945,12 @@ module SLICE_42 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); endmodule -module SLICE_43 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); +module SLICE_42 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly; - lut40044 \RowAd[9] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40038 \RowAd[9] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40018 \RowAd[8] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40014 \RowAd[8] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre \RowA[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1971,14 +1973,14 @@ module SLICE_43 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); endmodule -module SLICE_44 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, +module SLICE_43 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; - lut40004 nRCAS_0_sqmuxa_1_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40024 \S_0_i_o2[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40039 nRCS_9_u_i_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40019 \S_0_i_o3[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0009 \S[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + vmuxregsre0008 \S[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); @@ -2001,12 +2003,17 @@ module SLICE_44 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, endmodule -module SLICE_45 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output +module lut40039 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_44 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly; - lut40045 XOR8MEG_3_u_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40046 XOR8MEG_3_u_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40040 XOR8MEG_3_u_0_0_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40041 XOR8MEG_3_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre XOR8MEG( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -2031,22 +2038,22 @@ module SLICE_45 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output endmodule -module lut40045 ( input A, B, C, D, output Z ); +module lut40040 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFE00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40046 ( input A, B, C, D, output Z ); +module lut40041 ( input A, B, C, D, output Z ); ROM16X1A #(16'hF7F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_46 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, +module SLICE_45 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly; - lut40047 CmdValid_RNITBH02( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40048 n8MEGEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40042 CmdValid_RNIOOBE2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40043 n8MEGEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre n8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); @@ -2068,29 +2075,28 @@ module SLICE_46 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, endmodule -module lut40047 ( input A, B, C, D, output Z ); +module lut40042 ( input A, B, C, D, output Z ); ROM16X1A #(16'hF8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40048 ( input A, B, C, D, output Z ); +module lut40043 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h4E4E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h3A3A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_47 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output - F0, Q0, F1 ); - wire VCCI, DI0_dly, CLK_dly, LSR_dly; +module SLICE_46 ( input B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; - lut40049 nRowColSel_0_0_a3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40050 nRowColSel_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0009 nRowColSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + lut40044 nRowColSel_0_0_a2_1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40045 nRowColSel_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0008 nRowColSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); @@ -2108,22 +2114,22 @@ module SLICE_47 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output endmodule -module lut40049 ( input A, B, C, D, output Z ); +module lut40044 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h4444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40050 ( input A, B, C, D, output Z ); +module lut40045 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hDCEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hDC00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_48 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, +module SLICE_47 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40051 \wb_adr_5_i_i[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40052 \wb_adr_5_i_i[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40024 \wb_adr_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40046 \wb_adr_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \wb_adr[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -2151,23 +2157,18 @@ module SLICE_48 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, endmodule -module lut40051 ( input A, B, C, D, output Z ); +module lut40046 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFF80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0007) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40052 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_49 ( input B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, +module SLICE_48 ( input B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40018 \wb_adr_5[3] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40014 \wb_adr_5[3] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40018 \wb_adr_5[2] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40014 \wb_adr_5[2] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre \wb_adr[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -2190,13 +2191,13 @@ module SLICE_49 ( input B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, endmodule -module SLICE_50 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, +module SLICE_49 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40053 \wb_adr_5_i_m2_0[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40031 \wb_adr_5_i_m2[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40053 \wb_adr_5_i_m2_0[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40031 \wb_adr_5_i_m2[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \wb_adr[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -2221,18 +2222,13 @@ module SLICE_50 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, endmodule -module lut40053 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hB3B3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_51 ( input B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, +module SLICE_50 ( input B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40018 \wb_adr_5[7] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40014 \wb_adr_5[7] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40053 \wb_adr_5_i_m2_0[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40031 \wb_adr_5_i_m2[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \wb_adr[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -2256,13 +2252,13 @@ module SLICE_51 ( input B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, endmodule -module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, +module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); wire VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; - lut40004 wb_cyc_stb_4_iv_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40047 wb_cyc_stb_4_iv_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0009 wb_cyc_stb( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + lut40004 wb_cyc_stb_4_iv_0_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40042 wb_cyc_stb_4_iv_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0008 wb_cyc_stb( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -2287,12 +2283,12 @@ module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, endmodule -module SLICE_53 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, +module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40054 \wb_dati_5_1_iv_0_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40055 \wb_dati_5_0_iv_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40047 \wb_dati_5_1_iv_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40048 \wb_dati_5_0_iv_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \wb_dati[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -2320,31 +2316,72 @@ module SLICE_53 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, endmodule -module lut40054 ( input A, B, C, D, output Z ); +module lut40047 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFF10) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40055 ( input A, B, C, D, output Z ); +module lut40048 ( input A, B, C, D, output Z ); ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_54 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; +module SLICE_53 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40052 \wb_dati_5_1_iv_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40052 \wb_dati_5_1_iv_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40049 \wb_dati_5_1_iv_0_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40050 \wb_dati_5_1_iv_0_0[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \wb_dati[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \wb_dati[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40049 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40050 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hECEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_54 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40050 \wb_dati_5_1_iv_0_0[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40051 \wb_dati_5_1_iv_0_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \wb_dati[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \wb_dati[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -2363,44 +2400,17 @@ module SLICE_54 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, endmodule -module SLICE_55 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40052 \wb_dati_5_1_iv_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40028 \wb_dati_5_1_iv_0[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \wb_dati[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \wb_dati[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify +module lut40051 ( input A, B, C, D, output Z ); + ROM16X1A #(16'hF4FA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_56 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, +module SLICE_55 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40056 \wb_dati_5_1_iv_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40057 \wb_dati_5_1_iv_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40052 \wb_dati_5_1_iv_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40047 \wb_dati_5_1_iv_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \wb_dati[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -2428,24 +2438,19 @@ module SLICE_56 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, endmodule -module lut40056 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hEFAF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40057 ( input A, B, C, D, output Z ); +module lut40052 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFFEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_57 ( input D1, C1, B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, +module SLICE_56 ( input D1, C1, B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; - lut40058 wb_reqe_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40031 wb_reqe( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40053 wb_reqe_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40054 wb_reqe( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0009 wb_req( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + vmuxregsre0008 wb_req( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -2468,28 +2473,32 @@ module SLICE_57 ( input D1, C1, B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, endmodule -module lut40058 ( input A, B, C, D, output Z ); +module lut40053 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h007F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h1555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_58 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, - Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly; +module lut40054 ( input A, B, C, D, output Z ); - lut40036 \FS_RNIHVJI[15] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40059 wb_rste( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + ROM16X1A #(16'hD8D8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_57 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly; + + lut40055 un1_InitReady_4_i_0_a2_i( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40056 wb_rste( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre wb_rst( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); @@ -2501,23 +2510,28 @@ module SLICE_58 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, endmodule -module lut40059 ( input A, B, C, D, output Z ); +module lut40055 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h7430) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h3B33) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, - output F0, Q0, F1 ); - wire VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; +module lut40056 ( input A, B, C, D, output Z ); - lut40055 \wb_dati_5_1_iv_0_0[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40060 wb_we_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0009 wb_we( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + ROM16X1A #(16'hE4E4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_58 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output + F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40057 un1_wb_rst14_2_0_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40058 wb_we_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0008 wb_we( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -2537,38 +2551,105 @@ module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, endmodule -module lut40060 ( input A, B, C, D, output Z ); +module lut40057 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_60 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module lut40058 ( input A, B, C, D, output Z ); - lut40061 \wb_dati_5_1_iv_0_0_a2[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40019 \wb_dati_5_1_iv_0_1[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + ROM16X1A #(16'h008F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module wb_dati_5_1_iv_0_0_o2_5__SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, + A0, M0, output OFX0 ); + wire + \wb_dati_5_1_iv_0_0_o2[5]/SLICE_59/wb_dati_5_1_iv_0_0_o2[5]/SLICE_59_K1_H1 + , + \wb_dati_5_1_iv_0_0_o2[5]/SLICE_59/wb_dati_5_1_iv_0_0_o2[5]/GATE_H0 ; + + lut40059 \wb_dati_5_1_iv_0_0_o2[5]/SLICE_59_K1 ( .A(A1), .B(B1), .C(C1), + .D(D1), + .Z(\wb_dati_5_1_iv_0_0_o2[5]/SLICE_59/wb_dati_5_1_iv_0_0_o2[5]/SLICE_59_K1_H1 ) + ); + lut40060 \wb_dati_5_1_iv_0_0_o2[5]/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\wb_dati_5_1_iv_0_0_o2[5]/SLICE_59/wb_dati_5_1_iv_0_0_o2[5]/GATE_H0 )); + selmux2 \wb_dati_5_1_iv_0_0_o2[5]/SLICE_59_K0K1MUX ( + .D0(\wb_dati_5_1_iv_0_0_o2[5]/SLICE_59/wb_dati_5_1_iv_0_0_o2[5]/GATE_H0 ), + .D1(\wb_dati_5_1_iv_0_0_o2[5]/SLICE_59/wb_dati_5_1_iv_0_0_o2[5]/SLICE_59_K1_H1 ) + , .SD(M0), .Z(OFX0)); specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40059 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAABA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40060 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hBAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module selmux2 ( input D0, D1, SD, output Z ); + + MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z)); +endmodule + +module wb_adr_5_i_0_1_0__SLICE_60 ( input C1, B1, A1, D0, C0, B0, A0, M0, + output OFX0 ); + wire GNDI, \wb_adr_5_i_0_1[0]/SLICE_60/wb_adr_5_i_0_1[0]/SLICE_60_K1_H1 , + \wb_adr_5_i_0_1[0]/SLICE_60/wb_adr_5_i_0_1[0]/GATE_H0 ; + + lut40061 \wb_adr_5_i_0_1[0]/SLICE_60_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(\wb_adr_5_i_0_1[0]/SLICE_60/wb_adr_5_i_0_1[0]/SLICE_60_K1_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40062 \wb_adr_5_i_0_1[0]/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\wb_adr_5_i_0_1[0]/SLICE_60/wb_adr_5_i_0_1[0]/GATE_H0 )); + selmux2 \wb_adr_5_i_0_1[0]/SLICE_60_K0K1MUX ( + .D0(\wb_adr_5_i_0_1[0]/SLICE_60/wb_adr_5_i_0_1[0]/GATE_H0 ), + .D1(\wb_adr_5_i_0_1[0]/SLICE_60/wb_adr_5_i_0_1[0]/SLICE_60_K1_H1 ), + .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule module lut40061 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40062 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0060) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_61 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40062 wb_cyc_stb_2_sqmuxa_i_o2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40063 \wb_adr_5_i_i_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40063 \wb_adr_5_i_0_2_RNO[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40004 \wb_adr_5_i_0_2_RNO_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -2583,19 +2664,14 @@ module SLICE_61 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); endmodule -module lut40062 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40063 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hBA30) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hCECC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40064 IS_0_sqmuxa_0_o2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40064 IS_0_sqmuxa_0_o2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40065 un1_nRCAS_6_sqmuxa_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify @@ -2623,8 +2699,8 @@ endmodule module SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40036 wb_we_0_0_0_a2_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40066 wb_we_0_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40066 un1_CmdEnable20_0_0_a2_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40067 un1_CmdEnable20_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -2641,41 +2717,18 @@ endmodule module lut40066 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFF10) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_64 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40067 CmdEnable_0_sqmuxa_0_a2_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40068 un1_CmdEnable20_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - + ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40067 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40068 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hF111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_64 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40069 \wb_adr_5_i_i_0_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40070 \wb_adr_5_i_i_a2_0_1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40068 \FS_RNIHVJI[15] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40013 \wb_dati_5_1_iv_0_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -2690,51 +2743,16 @@ module SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); endmodule -module lut40069 ( input A, B, C, D, output Z ); +module lut40068 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFF40) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFFFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40070 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0804) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_66 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_65 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40071 \wb_adr_5_i_i_a2_3_0[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40072 \wb_adr_5_i_i_1_0_tz_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40071 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40072 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFF02) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_67 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40037 wb_cyc_stb_2_sqmuxa_i_o2_RNI167R( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40073 \ufmefb/EFBInst_0_RNI8K48 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + lut40069 \wb_dati_5_1_iv_0_1_0[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40070 \wb_dati_5_1_iv_0_0_o2[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); @@ -2750,16 +2768,74 @@ module SLICE_67 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); endmodule +module lut40069 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1BBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40070 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1919) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_66 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40035 \FS_RNIF2MA[9] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 \ufmefb/EFBInst_0_RNISI191 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40071 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_67 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40072 \wb_adr_5_i_0_3[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40073 \FS_RNIJO0F[12] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40072 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF40) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + module lut40073 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_68 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40074 nRWE_0io_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40071 \S_RNICVV51[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40072 nRWE_s_i_tz_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40074 \S_RNICVV51[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -2776,15 +2852,14 @@ endmodule module lut40074 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h31F5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_69 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40075 \wb_dati_5_1_iv_0_1[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40076 \wb_dati_5_1_iv_0_1_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); + lut40075 nRCAS_0io_RNO_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40018 nRCAS_0io_RNO_2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -2801,70 +2876,120 @@ endmodule module lut40075 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h00BF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h1500) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_70 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40076 wb_we_0_0_i_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40077 \FS_RNIOVGI[9] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + endmodule module lut40076 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h9B9B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_70 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40007 \wb_dati_5_1_iv_0_a2_3_2[7] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40073 \wb_dati_5_1_iv_0_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module SLICE_71 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40077 wb_we_0_0_0_a2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40078 wb_we_0_0_0_a2_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - + ROM16X1A #(16'hA8FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40077 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_71 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40078 \FS_RNIS637[9] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40079 \wb_adr_RNO_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + endmodule module lut40078 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h2BBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_72 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module lut40079 ( input A, B, C, D, output Z ); - lut40079 \wb_dati_5_1_iv_0_a2[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40080 \wb_dati_5_1_iv_0_a2_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(D0), + ROM16X1A #(16'h08AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_72 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40080 \wb_dati_5_1_iv_0_o2_0[4] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40004 \wb_dati_5_1_iv_0_o2_0_RNIMDJC1[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40080 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h6A6A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_73 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40081 \wb_dati_5_1_iv_0_o2[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40024 \wb_dati_5_1_iv_0_1_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40081 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF4F4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_74 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40017 \FS_RNIGOCT[12] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40082 \wb_dati_5_1_iv_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); @@ -2878,32 +3003,55 @@ module SLICE_72 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); endmodule -module lut40079 ( input A, B, C, D, output Z ); +module lut40082 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h2022) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40080 ( input A, B, C, D, output Z ); +module SLICE_75 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40083 CBR_fast_RNIQ31K1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40084 nRWE_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify - ROM16X1A #(16'h6888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, - Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; +module lut40083 ( input A, B, C, D, output Z ); - lut40081 un1_CmdEnable20_0_a2_3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40004 CmdEnable17_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40084 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAABF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_76 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40085 un1_CmdEnable20_0_0_a2_1_1( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40086 CmdEnable_s_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre CBR_fast( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre CBR( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -2921,63 +3069,32 @@ module SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, endmodule -module lut40081 ( input A, B, C, D, output Z ); +module lut40085 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_74 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40030 CmdUFMData_1_sqmuxa_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40004 CmdUFMData_1_sqmuxa_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify +module lut40086 ( input A, B, C, D, output Z ); + ROM16X1A #(16'h0203) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_75 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); - wire GNDI; - - lut40064 un1_ADWR_i_o2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut4 XOR8MEG18_0_a2_0( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module SLICE_76 ( input B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0, F1 ); +module SLICE_77 ( input D1, C1, B1, A1, B0, A0, M0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, M0_dly, CLK_dly; - lut40018 CmdEnable_0_sqmuxa_0_a2_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); + lut40077 Cmdn8MEGEN_4_u_i_m2_i_a2_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40014 CmdUFMData_1_sqmuxa_0_a2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), + .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40004 CmdEnable_0_sqmuxa_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre CASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); @@ -2988,129 +3105,12 @@ module SLICE_76 ( input B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0, F1 ); endmodule -module SLICE_77 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40071 \wb_adr_5_i_i_a2_6[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40054 \wb_adr_5_i_i_5[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - module SLICE_78 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40024 IS_0_sqmuxa_0_o2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40087 nRCS_9_u_i_a2_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40082 RA10_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40082 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_79 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40071 \wb_adr_5_i_i_a2_11[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40083 \wb_dati_5_1_iv_0_2[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40083 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_80 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40084 \FS_RNIS637[9] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40067 \wb_dati_5_1_iv_0_a2_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40084 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40085 nRCS_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40086 nRCS_9_u_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40085 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0057) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40086 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFF32) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_82 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut4 \wb_dati_5_1_iv_0_a2_2[6] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40087 \wb_dati_5_1_iv_0_a2_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40088 nRCS_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (B1 => F1) = (0:0:0,0:0:0); @@ -3125,82 +3125,45 @@ endmodule module lut40087 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h9000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_83 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40037 \wb_dati_5_1_iv_0_a2_9[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40019 \wb_dati_5_1_iv_0_o2_0[5] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module SLICE_84 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40021 \FS_RNICHC8[14] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40083 \wb_dati_5_1_iv_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40088 \wb_adr_5_i_i_a2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40089 \wb_adr_5_i_i_1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - + ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40088 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0021) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0057) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_79 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40019 IS_0_sqmuxa_0_o3( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40089 RA10_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + endmodule module lut40089 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFEFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFFEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_86 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; +module SLICE_80 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40044 \wb_dati_5_1_iv_0_o2[7] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40090 \wb_adr_5_i_i_1_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40090 un1_CmdEnable20_0_0_o2_11( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40064 un1_CmdEnable20_0_0_o2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); @@ -3213,69 +3176,13 @@ endmodule module lut40090 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h3301) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hBFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_87 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; +module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40008 wb_cyc_stb_2_sqmuxa_i_o2_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40057 wb_cyc_stb_2_sqmuxa_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module SLICE_88 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40021 \wb_dati_5_1_iv_0_a2_7[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40067 \wb_adr_5_i_i_a2_7[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module SLICE_89 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40034 un1_ADWR_i_o2_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40062 un1_ADWR_i_o2_10( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module SLICE_90 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40091 nRRAS_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40092 nRCS_9_u_i_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40091 \wb_dati_5_1_iv_0_a2_2[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40049 \wb_dati_5_1_iv_0_0_1[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -3292,37 +3199,13 @@ endmodule module lut40091 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h5051) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40092 ( input A, B, C, D, output Z ); +module SLICE_82 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - ROM16X1A #(16'h5400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_91 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40021 wb_cyc_stb_2_sqmuxa_i_a2_3_3( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40049 wb_cyc_stb_2_sqmuxa_i_a2_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module SLICE_92 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40093 nRWE_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40004 nRWE_s_i_a2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40092 \wb_dati_5_1_iv_0_a2_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40049 \wb_dati_5_1_iv_0_1[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -3337,57 +3220,45 @@ module SLICE_92 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); endmodule +module lut40092 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0600) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_83 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40057 un1_nRCAS_6_sqmuxa_i_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40093 nRCS_9_u_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + module lut40093 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFF70) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFF32) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_93 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_84 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; - lut4 XOR8MEG_3_u_0_a2_1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40004 XOR8MEG_3_u_0_a2_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module SLICE_94 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40008 \wb_dati_5_1_iv_0_o2_0[6] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + lut40073 \wb_dati_5_1_iv_0_a2_13[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40088 \wb_dati_5_1_iv_0_a2_1_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module SLICE_95 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40040 PHI2r3_RNIFT0I_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40094 CmdValid_fast_RNI3K0H1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40094 \wb_dati_5_1_iv_0_0_a2[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); @@ -3400,13 +3271,13 @@ endmodule module lut40094 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h80FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0900) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_96 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40095 nRCAS_0io_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40096 nRCAS_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40095 \wb_dati_5_1_iv_0_0_o2[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40096 \wb_dati_5_1_iv_0_1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -3423,20 +3294,77 @@ endmodule module lut40095 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h4101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0810) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40096 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h2322) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFF80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_97 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_86 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40073 wb_cyc_stb_4_iv_0_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40066 \wb_dati_5_1_iv_0_a2_7[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40050 \wb_dati_5_1_iv_0_0_0[3] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40097 CmdValid_RNIS5A51( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_87 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40087 \wb_dati_5_1_iv_0_a2_12[3] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \wb_dati_5_1_iv_0_0_1[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_88 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40087 \FS_RNI7U6M[14] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40091 \wb_dati_5_1_iv_0_a2_5[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_89 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40097 wb_cyc_stb_2_sqmuxa_i_0_0_a2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40049 wb_cyc_stb_2_sqmuxa_i_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -3452,17 +3380,16 @@ endmodule module lut40097 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h3B33) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hC4C4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_98 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; +module SLICE_90 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40077 \wb_adr_5_i_i_a2_6_0[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40098 \wb_dati_5_1_iv_0_o2[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40098 un1_CmdEnable20_0_0_o2_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40064 un1_CmdEnable20_0_0_o2_10( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -3476,15 +3403,15 @@ endmodule module lut40098 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h7084) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFF7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_99 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_91 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40071 \FS_RNI1FVB[14] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40099 \FS_RNI82PA[15] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40007 \wb_dati_5_1_iv_0_a2_2[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40100 \wb_adr_5_i_0_2[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -3498,41 +3425,23 @@ module SLICE_99 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); endmodule -module SLICE_100 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40099 \wb_dati_5_0_iv_0_a2_0_0[0] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40100 \wb_dati_5_1_iv_0_0_o2[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - module lut40099 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h2080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFDFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40100 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0810) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hF4FE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_101 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_92 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40084 \FS_RNI7O57[11] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40014 Cmdn8MEGEN_4_u_i_m2_i_a2_3( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40067 \wb_dati_5_1_iv_0_a2_1[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40083 un1_CmdEnable20_0_0_a2_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (B1 => F1) = (0:0:0,0:0:0); @@ -3545,34 +3454,17 @@ module SLICE_101 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); endmodule -module SLICE_102 ( input B1, A1, B0, A0, output F0, F1 ); - wire GNDI; +module SLICE_93 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40084 RDQML_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40044 RDQMH_pad_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module SLICE_103 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40081 InitReady3_0_a2_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40028 \FS_RNIQV0F[16] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); + lut40101 wb_we_0_0_i_1_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40102 wb_we_0_0_i_a2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); @@ -3580,60 +3472,25 @@ module SLICE_103 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); endmodule -module SLICE_104 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); - wire GNDI; - - lut40101 CmdLEDEN_4_u_i_a2_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40024 XOR8MEG_3_u_0_o2_1( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - module lut40101 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_105 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40021 nRCS_0io_RNO_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40102 RCKEEN_8_u_1_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - + ROM16X1A #(16'h0B0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40102 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h70CF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h3100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_106 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_94 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; - lut40067 XOR8MEG18_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40004 un1_CmdEnable20_0_a2_1_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40087 \wb_adr_5_i_3_0_a2_3[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40103 wb_rst_3_0_a2_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); @@ -3644,39 +3501,77 @@ module SLICE_106 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); endmodule -module SLICE_107 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40079 \FS_RNITL2J[14] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40103 \wb_adr_5_i_i_a2_5[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - module lut40103 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_108 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_95 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40104 n8MEGEN_RNO_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40087 wb_cyc_stb_2_sqmuxa_i_a2_2_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40017 \wb_dati_5_1_iv_0_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40103 wb_cyc_stb_2_sqmuxa_i_a2_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_96 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40019 XOR8MEG_3_u_0_0_o2_1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40083 XOR8MEG_3_u_0_0_a2_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_97 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40007 \wb_dati_5_1_iv_0_o2_0[7] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40066 \wb_dati_5_1_iv_0_a2_0_2[1] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_98 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40014 \wb_dati_5_1_iv_0_a2_6[4] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40104 \wb_dati_5_0_iv_0_a2_1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify - (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); @@ -3689,20 +3584,20 @@ endmodule module lut40104 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h4747) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h2800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_109 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; +module SLICE_99 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40033 \un9_RA_i_m2[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40105 un1_ADWR_i_o2_3( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40004 InitReady3_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40105 InitReady3_0_a2_1_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); @@ -3712,17 +3607,41 @@ endmodule module lut40105 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hF7F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h7FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_110 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); +module SLICE_100 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40033 \un9_RA[8] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40044 PHI2r3_RNIFT0I_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40033 \un9_RA_i_m2[9] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40106 CmdValid_fast_RNI3K0H1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40106 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h80FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_101 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40107 nRCAS_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40108 nRCAS_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -3733,14 +3652,74 @@ module SLICE_110 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); endmodule -module SLICE_111 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; +module lut40107 ( input A, B, C, D, output Z ); - lut40033 \un9_RA_i_m2[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40033 \un9_RA_i_m2[7] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + ROM16X1A #(16'h010F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40108 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCDCD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_102 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40109 \wb_dati_5_1_iv_0_a2_0_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40004 \ufmefb/EFBInst_0_RNISGNB ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40109 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_103 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40110 RCKEEN_8_u_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40083 nRWE_s_i_a2_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40110 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h70CF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_104 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40111 \wb_dati_5_1_iv_0_0_a2_1[3] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40071 \wb_dati_5_1_iv_0_a2_5[7] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -3751,12 +3730,172 @@ module SLICE_111 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); endmodule +module lut40111 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0084) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_105 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40014 \FS_RNI9Q57[12] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40112 \wb_adr_5_i_3_0_a2[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40112 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_106 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40113 RCKEEN_8_u_0_a2_2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40114 LED_pad_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40113 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40114 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFBF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_107 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut4 \wb_adr_5_i_0_a2_6[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40115 \wb_adr_5_i_3_0_a2_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40115 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0A08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_108 ( input B1, A1, B0, A0, output F0, F1 ); + wire GNDI; + + lut40078 RDQML_0_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40038 RDQMH_pad_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_109 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); + wire GNDI; + + lut40037 un1_CmdEnable20_0_0_a2_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut4 XOR8MEG_3_u_0_0_a2_1( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_110 ( input B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40044 PHI2r3_RNIFT0I( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40116 wb_cyc_stb_4_iv_0_0_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40116 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_111 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40117 n8MEGEN_RNO_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40049 \wb_dati_5_1_iv_0_0_1[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40117 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4747) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + module SLICE_112 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40033 \un9_RA_i_m2[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40030 \un9_RA_i_m2_i_m2[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40033 \un9_RA_i_m2[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40035 un1_CmdEnable20_0_0_o2_3( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -3772,9 +3911,9 @@ endmodule module SLICE_113 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40033 \un9_RA_i_m2[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40030 \un9_RA[8] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40033 \un9_RA_i_m2[5] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40030 \un9_RA_i_m2_i_m2[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -3787,14 +3926,16 @@ module SLICE_113 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); endmodule -module SLICE_114 ( input A1, C0, B0, A0, output F0, F1 ); +module SLICE_114 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40006 RA10_0io_RNO( .A(A1), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F1)); + lut40030 \un9_RA_i_m2_i_m2[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 nRWE_0io_RNO_1( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40030 \un9_RA_i_m2_i_m2[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); @@ -3803,12 +3944,104 @@ module SLICE_114 ( input A1, C0, B0, A0, output F0, F1 ); endmodule -module SLICE_115 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_115 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40018 \RBAd[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40030 \un9_RA_i_m2_i_m2[9] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40106 RA11d( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40030 \un9_RA_i_m2_i_m2[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_116 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40030 \un9_RA_i_m2_i_m2[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40030 \un9_RA_i_m2_i_m2[5] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_117 ( input B1, A1, B0, A0, output F0, F1 ); + wire GNDI; + + lut40023 nRowColSel_0_0_x2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40078 RCKEEN_8_u_0_o3( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_118 ( input B1, A1, B0, A0, output F0, F1 ); + wire GNDI; + + lut40044 \wb_dati_5_1_iv_0_a2_7[4] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut4 \wb_dati_5_1_iv_0_a2_11[3] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_119 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); + wire GNDI; + + lut40118 CmdLEDEN_4_u_i_m2_i_a2_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40087 XOR8MEG_3_u_0_0_a2_2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40118 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_120 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40014 \RBAd[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40119 RA11d( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (B1 => F1) = (0:0:0,0:0:0); @@ -3821,34 +4054,37 @@ module SLICE_115 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); endmodule -module lut40106 ( input A, B, C, D, output Z ); +module lut40119 ( input A, B, C, D, output Z ); ROM16X1A #(16'hC048) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_116 ( input B1, A1, B0, A0, output F0, F1 ); +module SLICE_121 ( input B1, A1, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40018 \wb_dati_5_1_iv_0_a2_1[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + lut40014 wb_cyc_stb_4_iv_0_0_a2_0_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40040 PHI2r3_RNIFT0I( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40073 wb_cyc_stb_2_sqmuxa_i_a2_1( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule -module SLICE_117 ( input C1, B1, A1, B0, A0, output F0, F1 ); +module SLICE_122 ( input C1, B1, A1, B0, A0, output F0, F1 ); wire GNDI; - lut40103 RCKEEN_8_u_0_a2_1( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40031 \wb_adr_5_i_3_0_m2[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut4 nRCAS_0io_RNO_1( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40087 IS_0_sqmuxa_0_o2_RNIDJQJ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), + .Z(F0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -3906,7 +4142,7 @@ endmodule module Dout_0_ ( input PADDO, output Dout0 ); - xo2iobuf0107 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0)); + xo2iobuf0120 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0)); specify (PADDO => Dout0) = (0:0:0,0:0:0); @@ -3914,14 +4150,14 @@ module Dout_0_ ( input PADDO, output Dout0 ); endmodule -module xo2iobuf0107 ( input I, output PAD ); +module xo2iobuf0120 ( input I, output PAD ); OB INST5( .I(I), .O(PAD)); endmodule module PHI2 ( output PADDI, input PHI2 ); - xo2iobuf0108 PHI2_pad( .Z(PADDI), .PAD(PHI2)); + xo2iobuf0121 PHI2_pad( .Z(PADDI), .PAD(PHI2)); specify (PHI2 => PADDI) = (0:0:0,0:0:0); @@ -3931,7 +4167,7 @@ module PHI2 ( output PADDI, input PHI2 ); endmodule -module xo2iobuf0108 ( output Z, input PAD ); +module xo2iobuf0121 ( output Z, input PAD ); IB INST1( .I(PAD), .O(Z)); endmodule @@ -3961,7 +4197,7 @@ endmodule module RDQML ( input PADDO, output RDQML ); - xo2iobuf0109 RDQML_pad( .I(PADDO), .PAD(RDQML)); + xo2iobuf0122 RDQML_pad( .I(PADDO), .PAD(RDQML)); specify (PADDO => RDQML) = (0:0:0,0:0:0); @@ -3969,14 +4205,14 @@ module RDQML ( input PADDO, output RDQML ); endmodule -module xo2iobuf0109 ( input I, output PAD ); +module xo2iobuf0122 ( input I, output PAD ); OB INST5( .I(I), .O(PAD)); endmodule module RDQMH ( input PADDO, output RDQMH ); - xo2iobuf0109 RDQMH_pad( .I(PADDO), .PAD(RDQMH)); + xo2iobuf0122 RDQMH_pad( .I(PADDO), .PAD(RDQMH)); specify (PADDO => RDQMH) = (0:0:0,0:0:0); @@ -3986,7 +4222,7 @@ endmodule module nRCAS ( input IOLDO, output nRCAS ); - xo2iobuf0109 nRCAS_pad( .I(IOLDO), .PAD(nRCAS)); + xo2iobuf0122 nRCAS_pad( .I(IOLDO), .PAD(nRCAS)); specify (IOLDO => nRCAS) = (0:0:0,0:0:0); @@ -3997,7 +4233,7 @@ endmodule module nRCAS_MGIOL ( output IOLDO, input OPOS, CLK ); wire VCCI, GNDI, OPOS_dly, CLK_dly; - mfflsre0110 nRCAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + mfflsre0123 nRCAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); @@ -4011,7 +4247,7 @@ module nRCAS_MGIOL ( output IOLDO, input OPOS, CLK ); endmodule -module mfflsre0110 ( input D0, SP, CK, LSR, output Q ); +module mfflsre0123 ( input D0, SP, CK, LSR, output Q ); FD1P3BX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q)); defparam INST01.GSR = "DISABLED"; @@ -4019,7 +4255,7 @@ endmodule module nRRAS ( input IOLDO, output nRRAS ); - xo2iobuf0109 nRRAS_pad( .I(IOLDO), .PAD(nRRAS)); + xo2iobuf0122 nRRAS_pad( .I(IOLDO), .PAD(nRRAS)); specify (IOLDO => nRRAS) = (0:0:0,0:0:0); @@ -4030,7 +4266,7 @@ endmodule module nRRAS_MGIOL ( output IOLDO, input OPOS, CLK ); wire VCCI, GNDI, OPOS_dly, CLK_dly; - mfflsre0110 nRRAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + mfflsre0123 nRRAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); @@ -4046,7 +4282,7 @@ endmodule module nRWE ( input IOLDO, output nRWE ); - xo2iobuf0109 nRWE_pad( .I(IOLDO), .PAD(nRWE)); + xo2iobuf0122 nRWE_pad( .I(IOLDO), .PAD(nRWE)); specify (IOLDO => nRWE) = (0:0:0,0:0:0); @@ -4057,7 +4293,7 @@ endmodule module nRWE_MGIOL ( output IOLDO, input OPOS, CLK ); wire VCCI, GNDI, OPOS_dly, CLK_dly; - mfflsre0110 nRWE_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + mfflsre0123 nRWE_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); @@ -4073,7 +4309,7 @@ endmodule module RCKE ( input PADDO, output RCKE ); - xo2iobuf0109 RCKE_pad( .I(PADDO), .PAD(RCKE)); + xo2iobuf0122 RCKE_pad( .I(PADDO), .PAD(RCKE)); specify (PADDO => RCKE) = (0:0:0,0:0:0); @@ -4083,7 +4319,7 @@ endmodule module RCLKout ( input IOLDO, output RCLKout ); - xo2iobuf0107 RCLKout_pad( .I(IOLDO), .PAD(RCLKout)); + xo2iobuf0124 RCLKout_pad( .I(IOLDO), .PAD(RCLKout)); specify (IOLDO => RCLKout) = (0:0:0,0:0:0); @@ -4091,10 +4327,15 @@ module RCLKout ( input IOLDO, output RCLKout ); endmodule +module xo2iobuf0124 ( input I, output PAD ); + + OB INST5( .I(I), .O(PAD)); +endmodule + module RCLKout_MGIOL ( output IOLDO, input ONEG, OPOS, CLK ); wire GNDI, ONEG_dly, CLK_dly, OPOS_dly; - xo2oddr rck( .D0(OPOS_dly), .D1(ONEG_dly), .SCLK(CLK_dly), .RST(GNDI), + xo2oddr rclk_oddr( .D0(OPOS_dly), .D1(ONEG_dly), .SCLK(CLK_dly), .RST(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); @@ -4116,7 +4357,7 @@ endmodule module RCLK ( output PADDI, input RCLK ); - xo2iobuf0108 RCLK_pad( .Z(PADDI), .PAD(RCLK)); + xo2iobuf0121 RCLK_pad( .Z(PADDI), .PAD(RCLK)); specify (RCLK => PADDI) = (0:0:0,0:0:0); @@ -4128,7 +4369,7 @@ endmodule module nRCS ( input IOLDO, output nRCS ); - xo2iobuf0109 nRCS_pad( .I(IOLDO), .PAD(nRCS)); + xo2iobuf0122 nRCS_pad( .I(IOLDO), .PAD(nRCS)); specify (IOLDO => nRCS) = (0:0:0,0:0:0); @@ -4139,7 +4380,7 @@ endmodule module nRCS_MGIOL ( output IOLDO, input OPOS, CLK ); wire VCCI, GNDI, OPOS_dly, CLK_dly; - mfflsre0110 nRCS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + mfflsre0123 nRCS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); @@ -4379,7 +4620,7 @@ endmodule module RA_11_ ( input IOLDO, output RA11 ); - xo2iobuf0109 \RA_pad[11] ( .I(IOLDO), .PAD(RA11)); + xo2iobuf0122 \RA_pad[11] ( .I(IOLDO), .PAD(RA11)); specify (IOLDO => RA11) = (0:0:0,0:0:0); @@ -4406,7 +4647,7 @@ endmodule module RA_10_ ( input IOLDO, output RA10 ); - xo2iobuf0109 \RA_pad[10] ( .I(IOLDO), .PAD(RA10)); + xo2iobuf0122 \RA_pad[10] ( .I(IOLDO), .PAD(RA10)); specify (IOLDO => RA10) = (0:0:0,0:0:0); @@ -4417,7 +4658,7 @@ endmodule module RA_10__MGIOL ( output IOLDO, input OPOS, LSR, CLK ); wire VCCI, OPOS_dly, CLK_dly, LSR_dly; - mfflsre0111 RA10_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), + mfflsre0125 RA10_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -4431,7 +4672,7 @@ module RA_10__MGIOL ( output IOLDO, input OPOS, LSR, CLK ); endmodule -module mfflsre0111 ( input D0, SP, CK, LSR, output Q ); +module mfflsre0125 ( input D0, SP, CK, LSR, output Q ); FD1P3JX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q)); defparam INST01.GSR = "DISABLED"; @@ -4439,7 +4680,7 @@ endmodule module RA_9_ ( input PADDO, output RA9 ); - xo2iobuf0109 \RA_pad[9] ( .I(PADDO), .PAD(RA9)); + xo2iobuf0122 \RA_pad[9] ( .I(PADDO), .PAD(RA9)); specify (PADDO => RA9) = (0:0:0,0:0:0); @@ -4449,7 +4690,7 @@ endmodule module RA_8_ ( input PADDO, output RA8 ); - xo2iobuf0109 \RA_pad[8] ( .I(PADDO), .PAD(RA8)); + xo2iobuf0122 \RA_pad[8] ( .I(PADDO), .PAD(RA8)); specify (PADDO => RA8) = (0:0:0,0:0:0); @@ -4459,7 +4700,7 @@ endmodule module RA_7_ ( input PADDO, output RA7 ); - xo2iobuf0109 \RA_pad[7] ( .I(PADDO), .PAD(RA7)); + xo2iobuf0122 \RA_pad[7] ( .I(PADDO), .PAD(RA7)); specify (PADDO => RA7) = (0:0:0,0:0:0); @@ -4469,7 +4710,7 @@ endmodule module RA_6_ ( input PADDO, output RA6 ); - xo2iobuf0109 \RA_pad[6] ( .I(PADDO), .PAD(RA6)); + xo2iobuf0122 \RA_pad[6] ( .I(PADDO), .PAD(RA6)); specify (PADDO => RA6) = (0:0:0,0:0:0); @@ -4479,7 +4720,7 @@ endmodule module RA_5_ ( input PADDO, output RA5 ); - xo2iobuf0109 \RA_pad[5] ( .I(PADDO), .PAD(RA5)); + xo2iobuf0122 \RA_pad[5] ( .I(PADDO), .PAD(RA5)); specify (PADDO => RA5) = (0:0:0,0:0:0); @@ -4489,7 +4730,7 @@ endmodule module RA_4_ ( input PADDO, output RA4 ); - xo2iobuf0109 \RA_pad[4] ( .I(PADDO), .PAD(RA4)); + xo2iobuf0122 \RA_pad[4] ( .I(PADDO), .PAD(RA4)); specify (PADDO => RA4) = (0:0:0,0:0:0); @@ -4499,7 +4740,7 @@ endmodule module RA_3_ ( input PADDO, output RA3 ); - xo2iobuf0109 \RA_pad[3] ( .I(PADDO), .PAD(RA3)); + xo2iobuf0122 \RA_pad[3] ( .I(PADDO), .PAD(RA3)); specify (PADDO => RA3) = (0:0:0,0:0:0); @@ -4509,7 +4750,7 @@ endmodule module RA_2_ ( input PADDO, output RA2 ); - xo2iobuf0109 \RA_pad[2] ( .I(PADDO), .PAD(RA2)); + xo2iobuf0122 \RA_pad[2] ( .I(PADDO), .PAD(RA2)); specify (PADDO => RA2) = (0:0:0,0:0:0); @@ -4519,7 +4760,7 @@ endmodule module RA_1_ ( input PADDO, output RA1 ); - xo2iobuf0109 \RA_pad[1] ( .I(PADDO), .PAD(RA1)); + xo2iobuf0122 \RA_pad[1] ( .I(PADDO), .PAD(RA1)); specify (PADDO => RA1) = (0:0:0,0:0:0); @@ -4529,7 +4770,7 @@ endmodule module RA_0_ ( input PADDO, output RA0 ); - xo2iobuf0109 \RA_pad[0] ( .I(PADDO), .PAD(RA0)); + xo2iobuf0122 \RA_pad[0] ( .I(PADDO), .PAD(RA0)); specify (PADDO => RA0) = (0:0:0,0:0:0); @@ -4539,7 +4780,7 @@ endmodule module RBA_1_ ( input IOLDO, output RBA1 ); - xo2iobuf0109 \RBA_pad[1] ( .I(IOLDO), .PAD(RBA1)); + xo2iobuf0122 \RBA_pad[1] ( .I(IOLDO), .PAD(RBA1)); specify (IOLDO => RBA1) = (0:0:0,0:0:0); @@ -4567,7 +4808,7 @@ endmodule module RBA_0_ ( input IOLDO, output RBA0 ); - xo2iobuf0109 \RBA_pad[0] ( .I(IOLDO), .PAD(RBA0)); + xo2iobuf0122 \RBA_pad[0] ( .I(IOLDO), .PAD(RBA0)); specify (IOLDO => RBA0) = (0:0:0,0:0:0); @@ -4595,7 +4836,7 @@ endmodule module LED ( input PADDO, output LED ); - xo2iobuf0112 LED_pad( .I(PADDO), .PAD(LED)); + xo2iobuf0126 LED_pad( .I(PADDO), .PAD(LED)); specify (PADDO => LED) = (0:0:0,0:0:0); @@ -4603,14 +4844,14 @@ module LED ( input PADDO, output LED ); endmodule -module xo2iobuf0112 ( input I, output PAD ); +module xo2iobuf0126 ( input I, output PAD ); OB INST5( .I(I), .O(PAD)); endmodule module nFWE ( output PADDI, input nFWE ); - xo2iobuf0108 nFWE_pad( .Z(PADDI), .PAD(nFWE)); + xo2iobuf0121 nFWE_pad( .Z(PADDI), .PAD(nFWE)); specify (nFWE => PADDI) = (0:0:0,0:0:0); @@ -4622,7 +4863,7 @@ endmodule module nCRAS ( output PADDI, input nCRAS ); - xo2iobuf0108 nCRAS_pad( .Z(PADDI), .PAD(nCRAS)); + xo2iobuf0121 nCRAS_pad( .Z(PADDI), .PAD(nCRAS)); specify (nCRAS => PADDI) = (0:0:0,0:0:0); @@ -4634,7 +4875,7 @@ endmodule module nCCAS ( output PADDI, input nCCAS ); - xo2iobuf0108 nCCAS_pad( .Z(PADDI), .PAD(nCCAS)); + xo2iobuf0121 nCCAS_pad( .Z(PADDI), .PAD(nCCAS)); specify (nCCAS => PADDI) = (0:0:0,0:0:0); @@ -4646,7 +4887,7 @@ endmodule module Dout_7_ ( input PADDO, output Dout7 ); - xo2iobuf0107 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7)); + xo2iobuf0120 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7)); specify (PADDO => Dout7) = (0:0:0,0:0:0); @@ -4656,7 +4897,7 @@ endmodule module Dout_6_ ( input PADDO, output Dout6 ); - xo2iobuf0107 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6)); + xo2iobuf0120 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6)); specify (PADDO => Dout6) = (0:0:0,0:0:0); @@ -4666,7 +4907,7 @@ endmodule module Dout_5_ ( input PADDO, output Dout5 ); - xo2iobuf0107 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5)); + xo2iobuf0120 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5)); specify (PADDO => Dout5) = (0:0:0,0:0:0); @@ -4676,7 +4917,7 @@ endmodule module Dout_4_ ( input PADDO, output Dout4 ); - xo2iobuf0107 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4)); + xo2iobuf0120 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4)); specify (PADDO => Dout4) = (0:0:0,0:0:0); @@ -4686,7 +4927,7 @@ endmodule module Dout_3_ ( input PADDO, output Dout3 ); - xo2iobuf0107 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3)); + xo2iobuf0120 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3)); specify (PADDO => Dout3) = (0:0:0,0:0:0); @@ -4696,7 +4937,7 @@ endmodule module Dout_2_ ( input PADDO, output Dout2 ); - xo2iobuf0107 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2)); + xo2iobuf0120 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2)); specify (PADDO => Dout2) = (0:0:0,0:0:0); @@ -4706,7 +4947,7 @@ endmodule module Dout_1_ ( input PADDO, output Dout1 ); - xo2iobuf0107 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1)); + xo2iobuf0120 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1)); specify (PADDO => Dout1) = (0:0:0,0:0:0); @@ -4716,7 +4957,7 @@ endmodule module Din_7_ ( output PADDI, input Din7 ); - xo2iobuf0108 \Din_pad[7] ( .Z(PADDI), .PAD(Din7)); + xo2iobuf0121 \Din_pad[7] ( .Z(PADDI), .PAD(Din7)); specify (Din7 => PADDI) = (0:0:0,0:0:0); @@ -4745,7 +4986,7 @@ endmodule module Din_6_ ( output PADDI, input Din6 ); - xo2iobuf0108 \Din_pad[6] ( .Z(PADDI), .PAD(Din6)); + xo2iobuf0121 \Din_pad[6] ( .Z(PADDI), .PAD(Din6)); specify (Din6 => PADDI) = (0:0:0,0:0:0); @@ -4774,7 +5015,7 @@ endmodule module Din_5_ ( output PADDI, input Din5 ); - xo2iobuf0108 \Din_pad[5] ( .Z(PADDI), .PAD(Din5)); + xo2iobuf0121 \Din_pad[5] ( .Z(PADDI), .PAD(Din5)); specify (Din5 => PADDI) = (0:0:0,0:0:0); @@ -4803,7 +5044,7 @@ endmodule module Din_4_ ( output PADDI, input Din4 ); - xo2iobuf0108 \Din_pad[4] ( .Z(PADDI), .PAD(Din4)); + xo2iobuf0121 \Din_pad[4] ( .Z(PADDI), .PAD(Din4)); specify (Din4 => PADDI) = (0:0:0,0:0:0); @@ -4832,7 +5073,7 @@ endmodule module Din_3_ ( output PADDI, input Din3 ); - xo2iobuf0108 \Din_pad[3] ( .Z(PADDI), .PAD(Din3)); + xo2iobuf0121 \Din_pad[3] ( .Z(PADDI), .PAD(Din3)); specify (Din3 => PADDI) = (0:0:0,0:0:0); @@ -4861,7 +5102,7 @@ endmodule module Din_2_ ( output PADDI, input Din2 ); - xo2iobuf0108 \Din_pad[2] ( .Z(PADDI), .PAD(Din2)); + xo2iobuf0121 \Din_pad[2] ( .Z(PADDI), .PAD(Din2)); specify (Din2 => PADDI) = (0:0:0,0:0:0); @@ -4890,7 +5131,7 @@ endmodule module Din_1_ ( output PADDI, input Din1 ); - xo2iobuf0108 \Din_pad[1] ( .Z(PADDI), .PAD(Din1)); + xo2iobuf0121 \Din_pad[1] ( .Z(PADDI), .PAD(Din1)); specify (Din1 => PADDI) = (0:0:0,0:0:0); @@ -4919,7 +5160,7 @@ endmodule module Din_0_ ( output PADDI, input Din0 ); - xo2iobuf0108 \Din_pad[0] ( .Z(PADDI), .PAD(Din0)); + xo2iobuf0121 \Din_pad[0] ( .Z(PADDI), .PAD(Din0)); specify (Din0 => PADDI) = (0:0:0,0:0:0); @@ -4948,7 +5189,7 @@ endmodule module CROW_1_ ( output PADDI, input CROW1 ); - xo2iobuf0108 \CROW_pad[1] ( .Z(PADDI), .PAD(CROW1)); + xo2iobuf0121 \CROW_pad[1] ( .Z(PADDI), .PAD(CROW1)); specify (CROW1 => PADDI) = (0:0:0,0:0:0); @@ -4960,7 +5201,7 @@ endmodule module CROW_0_ ( output PADDI, input CROW0 ); - xo2iobuf0108 \CROW_pad[0] ( .Z(PADDI), .PAD(CROW0)); + xo2iobuf0121 \CROW_pad[0] ( .Z(PADDI), .PAD(CROW0)); specify (CROW0 => PADDI) = (0:0:0,0:0:0); @@ -4972,7 +5213,7 @@ endmodule module MAin_9_ ( output PADDI, input MAin9 ); - xo2iobuf0108 \MAin_pad[9] ( .Z(PADDI), .PAD(MAin9)); + xo2iobuf0121 \MAin_pad[9] ( .Z(PADDI), .PAD(MAin9)); specify (MAin9 => PADDI) = (0:0:0,0:0:0); @@ -4984,7 +5225,7 @@ endmodule module MAin_8_ ( output PADDI, input MAin8 ); - xo2iobuf0108 \MAin_pad[8] ( .Z(PADDI), .PAD(MAin8)); + xo2iobuf0121 \MAin_pad[8] ( .Z(PADDI), .PAD(MAin8)); specify (MAin8 => PADDI) = (0:0:0,0:0:0); @@ -4996,7 +5237,7 @@ endmodule module MAin_7_ ( output PADDI, input MAin7 ); - xo2iobuf0108 \MAin_pad[7] ( .Z(PADDI), .PAD(MAin7)); + xo2iobuf0121 \MAin_pad[7] ( .Z(PADDI), .PAD(MAin7)); specify (MAin7 => PADDI) = (0:0:0,0:0:0); @@ -5008,7 +5249,7 @@ endmodule module MAin_6_ ( output PADDI, input MAin6 ); - xo2iobuf0108 \MAin_pad[6] ( .Z(PADDI), .PAD(MAin6)); + xo2iobuf0121 \MAin_pad[6] ( .Z(PADDI), .PAD(MAin6)); specify (MAin6 => PADDI) = (0:0:0,0:0:0); @@ -5020,7 +5261,7 @@ endmodule module MAin_5_ ( output PADDI, input MAin5 ); - xo2iobuf0108 \MAin_pad[5] ( .Z(PADDI), .PAD(MAin5)); + xo2iobuf0121 \MAin_pad[5] ( .Z(PADDI), .PAD(MAin5)); specify (MAin5 => PADDI) = (0:0:0,0:0:0); @@ -5032,7 +5273,7 @@ endmodule module MAin_4_ ( output PADDI, input MAin4 ); - xo2iobuf0108 \MAin_pad[4] ( .Z(PADDI), .PAD(MAin4)); + xo2iobuf0121 \MAin_pad[4] ( .Z(PADDI), .PAD(MAin4)); specify (MAin4 => PADDI) = (0:0:0,0:0:0); @@ -5044,7 +5285,7 @@ endmodule module MAin_3_ ( output PADDI, input MAin3 ); - xo2iobuf0108 \MAin_pad[3] ( .Z(PADDI), .PAD(MAin3)); + xo2iobuf0121 \MAin_pad[3] ( .Z(PADDI), .PAD(MAin3)); specify (MAin3 => PADDI) = (0:0:0,0:0:0); @@ -5056,7 +5297,7 @@ endmodule module MAin_2_ ( output PADDI, input MAin2 ); - xo2iobuf0108 \MAin_pad[2] ( .Z(PADDI), .PAD(MAin2)); + xo2iobuf0121 \MAin_pad[2] ( .Z(PADDI), .PAD(MAin2)); specify (MAin2 => PADDI) = (0:0:0,0:0:0); @@ -5068,7 +5309,7 @@ endmodule module MAin_1_ ( output PADDI, input MAin1 ); - xo2iobuf0108 \MAin_pad[1] ( .Z(PADDI), .PAD(MAin1)); + xo2iobuf0121 \MAin_pad[1] ( .Z(PADDI), .PAD(MAin1)); specify (MAin1 => PADDI) = (0:0:0,0:0:0); @@ -5080,7 +5321,7 @@ endmodule module MAin_0_ ( output PADDI, input MAin0 ); - xo2iobuf0108 \MAin_pad[0] ( .Z(PADDI), .PAD(MAin0)); + xo2iobuf0121 \MAin_pad[0] ( .Z(PADDI), .PAD(MAin0)); specify (MAin0 => PADDI) = (0:0:0,0:0:0); diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mrp.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mrp.html index 11861ea..d08a79b 100644 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mrp.html +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mrp.html @@ -23,19 +23,19 @@ Target Vendor: LATTICE Target Device: LCMXO2-1200HCTQFP100 Target Performance: 4 Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454 -Mapped on: 10/19/23 23:50:56 +Mapped on: 11/18/23 02:05:52 Design Summary - Number of registers: 110 out of 1520 (7%) - PFU registers: 85 out of 1280 (7%) + Number of registers: 109 out of 1520 (7%) + PFU registers: 84 out of 1280 (7%) PIO registers: 25 out of 240 (10%) - Number of SLICEs: 115 out of 640 (18%) - SLICEs as Logic/ROM: 115 out of 640 (18%) + Number of SLICEs: 120 out of 640 (19%) + SLICEs as Logic/ROM: 120 out of 640 (19%) SLICEs as RAM: 0 out of 480 (0%) SLICEs as Carry: 10 out of 640 (2%) - Number of LUT4s: 229 out of 1280 (18%) - Number used as logic LUTs: 209 + Number of LUT4s: 238 out of 1280 (19%) + Number used as logic LUTs: 218 Number used as distributed RAM: 0 Number used as ripple logic: 20 Number used as shift registers: 0 @@ -80,13 +80,13 @@ Mapped on: 10/19/23 23:50:56 Number of clocks: 4 Net PHI2_c: 20 loads, 9 rising, 11 falling (Driver: PIO PHI2 ) Net RCLK_c: 48 loads, 48 rising, 0 falling (Driver: PIO RCLK ) - Net nCRAS_c: 10 loads, 0 rising, 10 falling (Driver: PIO nCRAS ) + Net nCRAS_c: 9 loads, 0 rising, 9 falling (Driver: PIO nCRAS ) Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS ) Number of Clock Enables: 5 - Net N_103: 1 loads, 1 LSLICEs + Net wb_cyc_stb_2_sqmuxa_i_0_0: 1 loads, 1 LSLICEs Net XOR8MEG18: 5 loads, 5 LSLICEs - Net N_122: 9 loads, 9 LSLICEs - Net N_244_i: 2 loads, 2 LSLICEs + Net N_126_i: 9 loads, 9 LSLICEs + Net N_261_i: 2 loads, 2 LSLICEs Net CmdUFMData_1_sqmuxa: 1 loads, 1 LSLICEs Number of LSRs: 5 Net RA10s_i: 1 loads, 0 LSLICEs @@ -96,16 +96,16 @@ Mapped on: 10/19/23 23:50:56 Net RASr2: 2 loads, 2 LSLICEs Number of nets driven by tri-state buffers: 0 Top 10 highest fanout non-clock nets: - Net InitReady: 31 loads - Net FS[12]: 23 loads - Net FS[13]: 23 loads + Net InitReady: 40 loads + Net FS[13]: 22 loads Net FS[11]: 21 loads - Net N_132: 20 loads - Net FS[14]: 18 loads - Net FS[10]: 16 loads - Net FS[9]: 14 loads + Net FS[12]: 19 loads + Net FS[14]: 19 loads + Net FS[10]: 18 loads + Net FS[9]: 17 loads Net Ready: 14 loads Net Ready_fast: 14 loads + Net CO0: 12 loads @@ -399,7 +399,7 @@ Instance Name: ufmefb/EFBInst_0 Total CPU Time: 0 secs Total REAL Time: 0 secs - Peak Memory Usage: 63 MB + Peak Memory Usage: 64 MB diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_pad.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_pad.html index 2dd6f36..baeee75 100644 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_pad.html +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_pad.html @@ -14,7 +14,7 @@ Performance Grade: 4 PACKAGE: TQFP100 Package Status: Final Version 1.44 -Thu Oct 19 23:51:05 2023 +Sat Nov 18 02:06:05 2023 Pinout by Port Name: +-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ @@ -61,12 +61,12 @@ Pinout by Port Name: | RA[6] | 68/1 | LVCMOS33_OUT | PR4B | | | DRIVE:4mA SLEW:SLOW | | RA[7] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW | | RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW | -| RA[9] | 47/2 | LVCMOS33_OUT | PB18D | | | DRIVE:4mA SLEW:SLOW | +| RA[9] | 62/1 | LVCMOS33_OUT | PR5D | | | DRIVE:4mA SLEW:SLOW | | RBA[0] | 58/1 | LVCMOS33_OUT | PR9A | | | DRIVE:4mA SLEW:SLOW | -| RBA[1] | 60/1 | LVCMOS33_OUT | PR8C | | | DRIVE:4mA SLEW:SLOW | +| RBA[1] | 47/2 | LVCMOS33_OUT | PB18D | | | DRIVE:4mA SLEW:SLOW | | RCKE | 53/1 | LVCMOS33_OUT | PR9D | | | DRIVE:4mA SLEW:SLOW | | RCLK | 63/1 | LVCMOS33_IN | PR5C | | | CLAMP:ON HYSTERESIS:SMALL | -| RCLKout | 62/1 | LVCMOS33_OUT | PR5D | | | DRIVE:4mA SLEW:FAST | +| RCLKout | 60/1 | LVCMOS33_OUT | PR8C | | | DRIVE:24mA SLEW:FAST | | RDQMH | 51/1 | LVCMOS33_OUT | PR10D | | | DRIVE:4mA SLEW:SLOW | | RDQML | 48/2 | LVCMOS33_OUT | PB20C | | | DRIVE:4mA SLEW:SLOW | | RD[0] | 36/2 | LVCMOS33_BIDI | PB11C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | @@ -144,7 +144,7 @@ Vccio by Bank: | 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB18A | | | | | 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB18B | | | | | 45/2 | unused, PULL:DOWN | | | PB18C | | | | -| 47/2 | RA[9] | LOCATED | LVCMOS33_OUT | PB18D | | | | +| 47/2 | RBA[1] | LOCATED | LVCMOS33_OUT | PB18D | | | | | 48/2 | RDQML | LOCATED | LVCMOS33_OUT | PB20C | SN | | | | 49/2 | nRWE | LOCATED | LVCMOS33_OUT | PB20D | SI/SISPI | | | | 51/1 | RDQMH | LOCATED | LVCMOS33_OUT | PR10D | DQ1 | | | @@ -154,9 +154,9 @@ Vccio by Bank: | 57/1 | nRCS | LOCATED | LVCMOS33_OUT | PR9B | DQ1 | | | | 58/1 | RBA[0] | LOCATED | LVCMOS33_OUT | PR9A | DQ1 | | | | 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR8D | DQ1 | | | -| 60/1 | RBA[1] | LOCATED | LVCMOS33_OUT | PR8C | DQ1 | | | +| 60/1 | RCLKout | LOCATED | LVCMOS33_OUT | PR8C | DQ1 | | | | 61/1 | unused, PULL:DOWN | | | PR8A | DQS1 | | | -| 62/1 | RCLKout | LOCATED | LVCMOS33_OUT | PR5D | PCLKC1_0/DQ0 | | | +| 62/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5D | PCLKC1_0/DQ0 | | | | 63/1 | RCLK | LOCATED | LVCMOS33_IN | PR5C | PCLKT1_0/DQ0 | | | | 64/1 | RA[10] | LOCATED | LVCMOS33_OUT | PR5B | DQS0N | | | | 65/1 | RA[8] | LOCATED | LVCMOS33_OUT | PR5A | DQS0 | | | @@ -274,12 +274,12 @@ LOCATE COMP "RA[5]" SITE "70"; LOCATE COMP "RA[6]" SITE "68"; LOCATE COMP "RA[7]" SITE "75"; LOCATE COMP "RA[8]" SITE "65"; -LOCATE COMP "RA[9]" SITE "47"; +LOCATE COMP "RA[9]" SITE "62"; LOCATE COMP "RBA[0]" SITE "58"; -LOCATE COMP "RBA[1]" SITE "60"; +LOCATE COMP "RBA[1]" SITE "47"; LOCATE COMP "RCKE" SITE "53"; LOCATE COMP "RCLK" SITE "63"; -LOCATE COMP "RCLKout" SITE "62"; +LOCATE COMP "RCLKout" SITE "60"; LOCATE COMP "RDQMH" SITE "51"; LOCATE COMP "RDQML" SITE "48"; LOCATE COMP "RD[0]" SITE "36"; @@ -308,7 +308,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Thu Oct 19 23:51:08 2023 +Sat Nov 18 02:06:09 2023 diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_par.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_par.html index 99bd304..a310e7f 100644 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_par.html +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_par.html @@ -12,7 +12,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Thu Oct 19 23:50:59 2023 +Sat Nov 18 02:05:57 2023 C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_1200HC_impl1.p2t RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir @@ -26,17 +26,17 @@ Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf. Level/ Number Worst Timing Worst Timing Run NCD Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status ---------- -------- ----- ------ ----------- ----------- ---- ------ -5_1 * 0 5.798 0 0.304 0 12 Completed +5_1 * 0 6.215 0 0.304 0 15 Completed * : Design saved. -Total (real) run time for 1-seed: 12 secs +Total (real) run time for 1-seed: 15 secs par done! Note: user must run 'Trace' for timing closure signoff. Lattice Place and Route Report for Design "RAM2GS_LCMXO2_1200HC_impl1_map.ncd" -Thu Oct 19 23:50:59 2023 +Sat Nov 18 02:05:57 2023 Best Par Run @@ -67,43 +67,43 @@ Ignore Preference Error(s): True 64+4(JTAG)/80 85% bonded IOLOGIC 26/108 24% used - SLICE 115/640 17% used + SLICE 120/640 18% used EFB 1/1 100% used -Number of Signals: 383 -Number of Connections: 993 +Number of Signals: 389 +Number of Connections: 1011 Pin Constraint Summary: 64 out of 64 pins locked (100% locked). -The following 3 signals are selected to use the primary clock routing resources: +The following 2 signals are selected to use the primary clock routing resources: RCLK_c (driver: RCLK, clk load #: 48) PHI2_c (driver: PHI2, clk load #: 20) - nCRAS_c (driver: nCRAS, clk load #: 10) WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. -WARNING - par: Signal "nCRAS_c" is selected to use Primary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. -The following 1 signal is selected to use the secondary clock routing resources: +The following 2 signals are selected to use the secondary clock routing resources: + nCRAS_c (driver: nCRAS, clk load #: 9, sr load #: 0, ce load #: 0) nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0) +WARNING - par: Signal "nCRAS_c" is selected to use Secondary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. WARNING - par: Signal "nCCAS_c" is selected to use Secondary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. No signal is selected as Global Set/Reset. Starting Placer Phase 0. -........ -Finished Placer Phase 0. REAL time: 2 secs +......... +Finished Placer Phase 0. REAL time: 0 secs Starting Placer Phase 1. -..................... -Placer score = 66969. -Finished Placer Phase 1. REAL time: 6 secs +.................... +Placer score = 71673. +Finished Placer Phase 1. REAL time: 8 secs Starting Placer Phase 2. . -Placer score = 66494 -Finished Placer Phase 2. REAL time: 6 secs +Placer score = 70957 +Finished Placer Phase 2. REAL time: 8 secs @@ -119,11 +119,11 @@ Global Clock Resources: Global Clocks: PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "63 (PR5C)", clk load = 48 PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3D)", clk load = 20 - PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL8B)", clk load = 10 + SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL8B)", clk load = 9, ce load = 0, sr load = 0 SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL4A)", clk load = 8, ce load = 0, sr load = 0 - PRIMARY : 3 out of 8 (37%) - SECONDARY: 1 out of 8 (12%) + PRIMARY : 2 out of 8 (25%) + SECONDARY: 2 out of 8 (25%) Edge Clocks: No edge clock selected. @@ -147,17 +147,16 @@ I/O Bank Usage Summary: | 3 | 18 / 20 ( 90%) | 3.3V | - | +----------+----------------+------------+-----------+ -Total placer CPU time: 5 secs +Total placer CPU time: 8 secs Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd. -0 connections routed; 993 unrouted. +0 connections routed; 1011 unrouted. Starting router resource preassignment -WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew. -Completed router resource preassignment. Real time: 10 secs +Completed router resource preassignment. Real time: 13 secs -Start NBR router at 23:51:09 10/19/23 +Start NBR router at 02:06:10 11/18/23 ***************************************************************** Info: NBR allows conflicts(one node used by more than one signal) @@ -172,50 +171,41 @@ Note: NBR uses a different method to calculate timing slacks. The your design. ***************************************************************** -Start NBR special constraint process at 23:51:09 10/19/23 +Start NBR special constraint process at 02:06:10 11/18/23 -Start NBR section for initial routing at 23:51:09 10/19/23 +Start NBR section for initial routing at 02:06:11 11/18/23 Level 1, iteration 1 -0(0.00%) conflict; 795(80.06%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 6.138ns/0.000ns; real time: 10 secs +0(0.00%) conflict; 814(80.51%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack<setup>: 5.987ns/0.000ns; real time: 14 secs Level 2, iteration 1 -0(0.00%) conflict; 795(80.06%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 6.138ns/0.000ns; real time: 10 secs +0(0.00%) conflict; 803(79.43%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack<setup>: 6.236ns/0.000ns; real time: 14 secs Level 3, iteration 1 -0(0.00%) conflict; 795(80.06%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 6.138ns/0.000ns; real time: 10 secs +0(0.00%) conflict; 803(79.43%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack<setup>: 5.836ns/0.000ns; real time: 14 secs Level 4, iteration 1 -17(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 5.804ns/0.000ns; real time: 11 secs +16(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack<setup>: 6.236ns/0.000ns; real time: 14 secs Info: Initial congestion level at 75% usage is 0 Info: Initial congestion area at 75% usage is 0 (0.00%) -Start NBR section for normal routing at 23:51:10 10/19/23 +Start NBR section for normal routing at 02:06:11 11/18/23 Level 4, iteration 1 -11(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 5.798ns/0.000ns; real time: 11 secs +3(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack<setup>: 6.222ns/0.000ns; real time: 14 secs Level 4, iteration 2 -4(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 5.798ns/0.000ns; real time: 11 secs -Level 4, iteration 3 -2(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 5.798ns/0.000ns; real time: 11 secs -Level 4, iteration 4 -1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 5.798ns/0.000ns; real time: 11 secs -Level 4, iteration 5 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 5.798ns/0.000ns; real time: 11 secs +Estimated worst slack/total negative slack<setup>: 6.215ns/0.000ns; real time: 14 secs -Start NBR section for setup/hold timing optimization with effort level 3 at 23:51:10 10/19/23 +Start NBR section for setup/hold timing optimization with effort level 3 at 02:06:11 11/18/23 -Start NBR section for re-routing at 23:51:10 10/19/23 +Start NBR section for re-routing at 02:06:11 11/18/23 Level 4, iteration 1 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 5.798ns/0.000ns; real time: 11 secs +Estimated worst slack/total negative slack<setup>: 6.215ns/0.000ns; real time: 14 secs -Start NBR section for post-routing at 23:51:10 10/19/23 +Start NBR section for post-routing at 02:06:11 11/18/23 End NBR router with 0 unrouted connection @@ -223,17 +213,17 @@ NBR Summary ----------- Number of unrouted connections : 0 (0.00%) Number of connections with timing violations : 0 (0.00%) - Estimated worst slack<setup> : 5.798ns + Estimated worst slack<setup> : 6.215ns Timing score<setup> : 0 ----------- Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. -Total CPU time 11 secs -Total REAL time: 12 secs +Total CPU time 14 secs +Total REAL time: 15 secs Completely routed. -End of route. 993 routed (100.00%); 0 unrouted. +End of route. 1011 routed (100.00%); 0 unrouted. Hold time timing score: 0, hold timing errors: 0 @@ -247,14 +237,14 @@ All signals are completely routed. PAR_SUMMARY::Run status = Completed PAR_SUMMARY::Number of unrouted conns = 0 -PAR_SUMMARY::Worst slack<setup/<ns>> = 5.798 +PAR_SUMMARY::Worst slack<setup/<ns>> = 6.215 PAR_SUMMARY::Timing score<setup/<ns>> = 0.000 PAR_SUMMARY::Worst slack<hold /<ns>> = 0.304 PAR_SUMMARY::Timing score<hold /<ns>> = 0.000 PAR_SUMMARY::Number of errors = 0 -Total CPU time to completion: 11 secs -Total REAL time to completion: 12 secs +Total CPU time to completion: 15 secs +Total REAL time to completion: 15 secs par done! diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_scck.rpt b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_scck.rpt index 5f70fd7..05b0877 100644 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_scck.rpt +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_scck.rpt @@ -13,7 +13,7 @@ Hostname: ZANEMACWIN11 Implementation : impl1 -# Written on Thu Oct 19 23:50:49 2023 +# Written on Sat Nov 18 02:05:43 2023 ##### FILES SYNTAX CHECKED ############################################## Constraint File(s): "\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc" diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_summary.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_summary.html index 5850c48..c41f075 100644 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_summary.html +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_summary.html @@ -24,9 +24,9 @@ Last Process: -JEDEC File + State: -Passed + Target Device: @@ -62,7 +62,7 @@ Updated: -2023/10/20 00:05:05 +2023/11/18 02:59:50 Implementation Location: diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_synplify.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_synplify.html index 629aef2..ad9365f 100644 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_synplify.html +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_synplify.html @@ -12,7 +12,7 @@ #OS: Windows 8 6.2 #Hostname: ZANEMACWIN11 -# Thu Oct 19 23:50:47 2023 +# Sat Nov 18 02:05:40 2023 #Implementation: impl1 @@ -60,19 +60,17 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202 @I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v" (library work) @I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC\REFB.v" (library work) Verilog syntax check successful! - -Compiler output is up to date. No re-compile necessary - +File \\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v changed - recompiling Selecting top level module RAM2GS @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1601:7:1601:12|Synthesizing module ODDRXE in library work. Running optimization stage 1 on ODDRXE ....... -Finished optimization stage 1 on ODDRXE (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB) +Finished optimization stage 1 on ODDRXE (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB) @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work. Running optimization stage 1 on VHI ....... -Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB) +Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB) @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work. Running optimization stage 1 on VLO ....... -Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB) +Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB) @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work. Running optimization stage 1 on EFB ....... Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB) @@ -80,9 +78,6 @@ Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: Running optimization stage 1 on REFB ....... Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB) @N: CG364 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v":1:7:1:12|Synthesizing module RAM2GS in library work. -@W: CS263 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v":46:6:46:6|Port-width mismatch for port D0. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port. -@W: CS263 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v":46:14:46:14|Port-width mismatch for port D1. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port. -@W: CS263 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v":47:7:47:7|Port-width mismatch for port RST. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port. Running optimization stage 1 on RAM2GS ....... Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB) Running optimization stage 2 on RAM2GS ....... @@ -98,12 +93,12 @@ Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: Running optimization stage 2 on ODDRXE ....... Finished optimization stage 2 on ODDRXE (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) -At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 96MB peak: 97MB) +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Oct 19 23:50:47 2023 +# Sat Nov 18 02:05:41 2023 ###########################################################] ###########################################################[ @@ -130,7 +125,7 @@ At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Oct 19 23:50:48 2023 +# Sat Nov 18 02:05:41 2023 ###########################################################] @@ -145,7 +140,7 @@ At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Oct 19 23:50:48 2023 +# Sat Nov 18 02:05:41 2023 ###########################################################] ###########################################################[ @@ -173,10 +168,10 @@ At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Oct 19 23:50:49 2023 +# Sat Nov 18 02:05:43 2023 ###########################################################] -# Thu Oct 19 23:50:49 2023 +# Sat Nov 18 02:05:43 2023 Copyright (C) 1994-2021 Synopsys, Inc. @@ -195,7 +190,7 @@ Implementation : impl1 Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @ -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB) +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB) Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 140MB) @@ -222,7 +217,6 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h @W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. @N: FX493 |Applying initial value "0" on instance Ready. @N: FX493 |Applying initial value "0" on instance RCKE. -@N: FX493 |Applying initial value "0" on instance LEDEN. @N: FX493 |Applying initial value "0" on instance n8MEGEN. @N: FX493 |Applying initial value "1" on instance nRCAS. @N: FX493 |Applying initial value "0" on instance CmdLEDEN. @@ -248,11 +242,11 @@ Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapse Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB) -Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) +Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB) @N: FX1184 |Applying syn_allowed_resources blockrams=7 on top level netlist RAM2GS -Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB) @@ -333,13 +327,13 @@ Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:0 Pre-mapping successful! -At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 103MB peak: 185MB) +At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 185MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu Oct 19 23:50:50 2023 +# Sat Nov 18 02:05:44 2023 ###########################################################] -# Thu Oct 19 23:50:50 2023 +# Sat Nov 18 02:05:44 2023 Copyright (C) 1994-2021 Synopsys, Inc. @@ -358,42 +352,42 @@ Implementation : impl1 Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @ -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB) +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB) @N: MF916 |Option synthesis_strategy=base is enabled. @N: MF248 |Running in 64-bit mode. @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 139MB) +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB) -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 139MB) +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB) -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB) +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB) -Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 178MB peak: 178MB) +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 179MB peak: 179MB) -Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) +Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB) -@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":169:4:169:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] -@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":156:4:156:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] +@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":166:4:166:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] +@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":153:4:153:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] @N: FX493 |Applying initial value "0" on instance IS[0]. @W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. @N: FX493 |Applying initial value "0" on instance IS[1]. @N: FX493 |Applying initial value "0" on instance IS[2]. @N: FX493 |Applying initial value "0" on instance IS[3]. -Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 185MB peak: 185MB) +Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 185MB peak: 185MB) -Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB) +Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB) Available hyper_sources - for debug and ip models @@ -415,63 +409,51 @@ Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CP Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB) -Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 195MB peak: 195MB) +Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 197MB peak: 197MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ - 1 0h:00m:01s -2.76ns 193 / 106 - 2 0h:00m:01s -2.76ns 209 / 106 - 3 0h:00m:01s -2.76ns 208 / 106 - 4 0h:00m:01s -2.76ns 206 / 106 - 5 0h:00m:01s -2.76ns 206 / 106 - 6 0h:00m:01s -2.76ns 205 / 106 - 7 0h:00m:01s -2.76ns 205 / 106 -@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":310:4:310:9|Replicating instance CmdValid (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing. -@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":169:4:169:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing. -@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":127:4:127:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing. -@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":127:4:127:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing. + 1 0h:00m:02s -2.98ns 202 / 106 + 2 0h:00m:02s -2.98ns 215 / 106 + 3 0h:00m:02s -2.76ns 215 / 106 +@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":124:4:124:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing. +@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":307:4:307:9|Replicating instance CmdValid (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing. +@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":166:4:166:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing. Timing driven replication report -Added 4 Registers via timing driven replication -Added 2 LUTs via timing driven replication +Added 3 Registers via timing driven replication +Added 1 LUTs via timing driven replication - 8 0h:00m:01s -1.83ns 209 / 110 - 9 0h:00m:01s -1.83ns 209 / 110 - 10 0h:00m:01s -1.83ns 209 / 110 - 11 0h:00m:01s -1.83ns 209 / 110 - 12 0h:00m:01s -1.83ns 209 / 110 + 4 0h:00m:02s -1.97ns 220 / 109 - 13 0h:00m:01s -1.83ns 208 / 110 - 14 0h:00m:01s -1.83ns 209 / 110 - 15 0h:00m:01s -1.83ns 209 / 110 - 16 0h:00m:01s -1.83ns 209 / 110 + 5 0h:00m:02s -1.97ns 220 / 109 -Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 196MB peak: 196MB) +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 197MB peak: 197MB) @N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. -Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 196MB peak: 196MB) +Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 198MB peak: 198MB) -Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 160MB peak: 196MB) +Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 160MB peak: 198MB) Writing Analyst data base \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2GS_LCMXO2_1200HC_impl1_m.srm -Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 197MB peak: 197MB) +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 198MB peak: 198MB) Writing EDIF Netlist and constraint files @N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC\impl1\RAM2GS_LCMXO2_1200HC_impl1.edi @N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF -Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 201MB peak: 201MB) +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 203MB peak: 203MB) -Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 201MB peak: 202MB) +Finished Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 203MB peak: 203MB) -Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 200MB peak: 202MB) +Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 201MB peak: 203MB) -@W: MT246 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":43:8:43:10|Blackbox ODDRXE is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) +@W: MT246 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":43:11:43:19|Blackbox ODDRXE is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W: MT246 :"\\mac\icloud\repos\ram2gs\cpld\lcmxo2-1200hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @N: MT615 |Found clock RCLK with period 16.00ns @N: MT615 |Found clock PHI2 with period 350.00ns @@ -480,7 +462,7 @@ Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:0 ##### START OF TIMING REPORT #####[ -# Timing report written on Thu Oct 19 23:50:54 2023 +# Timing report written on Sat Nov 18 02:05:49 2023 # @@ -500,15 +482,15 @@ Performance Summary ******************* -Worst slack in design: -1.828 +Worst slack in design: -2.605 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------- PHI2 2.9 MHz 1.0 MHz 350.000 989.870 -1.828 declared default_clkgroup -RCLK 62.5 MHz 22.1 MHz 16.000 45.251 -0.784 declared default_clkgroup +RCLK 62.5 MHz 17.3 MHz 16.000 57.686 -0.784 declared default_clkgroup nCCAS 2.9 MHz NA 350.000 NA NA declared default_clkgroup -nCRAS 2.9 MHz 1.1 MHz 350.000 942.410 -1.693 declared default_clkgroup +nCRAS 2.9 MHz 0.8 MHz 350.000 1261.890 -2.605 declared default_clkgroup System 100.0 MHz NA 10.000 NA 12.918 system system_clkgroup =================================================================================================================== Estimated period and frequency reported as NA means no slack depends directly on the clock waveform @@ -531,12 +513,12 @@ Starting Ending | constraint slack | constraint slack | constraint --------------------------------------------------------------------------------------------------------------- System RCLK | 16.000 12.918 | No paths - | No paths - | No paths - RCLK System | 16.000 14.956 | No paths - | No paths - | No paths - -RCLK RCLK | 16.000 9.100 | No paths - | No paths - | No paths - +RCLK RCLK | 16.000 9.237 | No paths - | No paths - | No paths - RCLK PHI2 | 2.000 0.216 | No paths - | 1.000 -0.676 | No paths - RCLK nCRAS | No paths - | No paths - | 1.000 -0.784 | No paths - PHI2 RCLK | No paths - | No paths - | No paths - | 1.000 -1.828 -PHI2 PHI2 | No paths - | 350.000 347.156 | 175.000 169.041 | 175.000 173.428 -nCRAS RCLK | No paths - | No paths - | No paths - | 1.000 -1.693 +PHI2 PHI2 | No paths - | 350.000 346.603 | 175.000 169.081 | 175.000 173.428 +nCRAS RCLK | No paths - | No paths - | No paths - | 1.000 -2.605 =============================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. @@ -570,30 +552,30 @@ CmdLEDEN PHI2 FD1P3AX Q CmdLEDEN 1.044 Cmdn8MEGEN PHI2 FD1P3AX Q Cmdn8MEGEN 1.044 -1.589 CmdUFMWrite PHI2 FD1P3AX Q CmdUFMWrite 1.044 -0.572 CmdUFMData PHI2 FD1P3AX Q CmdUFMData 0.972 -0.500 -Bank_0io[0] PHI2 IFS1P3DX Q Bank[0] 0.972 169.041 -Bank_0io[2] PHI2 IFS1P3DX Q Bank[2] 0.972 169.041 -Bank_0io[4] PHI2 IFS1P3DX Q Bank[4] 0.972 169.041 +Bank_0io[1] PHI2 IFS1P3DX Q Bank[1] 0.972 169.081 +Bank_0io[2] PHI2 IFS1P3DX Q Bank[2] 0.972 169.081 +Bank_0io[3] PHI2 IFS1P3DX Q Bank[3] 0.972 169.081 ========================================================================================== Ending Points with Worst Slack ****************************** - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------- -wb_adr[0] PHI2 FD1P3AX SP N_122 0.528 -1.828 -wb_adr[1] PHI2 FD1P3AX SP N_122 0.528 -1.828 -wb_adr[2] PHI2 FD1P3AX SP N_122 0.528 -1.828 -wb_adr[3] PHI2 FD1P3AX SP N_122 0.528 -1.828 -wb_adr[4] PHI2 FD1P3AX SP N_122 0.528 -1.828 -wb_adr[5] PHI2 FD1P3AX SP N_122 0.528 -1.828 -wb_adr[6] PHI2 FD1P3AX SP N_122 0.528 -1.828 -wb_adr[7] PHI2 FD1P3AX SP N_122 0.528 -1.828 -wb_dati[0] PHI2 FD1P3AX SP N_122 0.528 -1.828 -wb_dati[1] PHI2 FD1P3AX SP N_122 0.528 -1.828 -============================================================================== + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------- +wb_adr[0] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +wb_adr[1] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +wb_adr[2] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +wb_adr[3] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +wb_adr[4] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +wb_adr[5] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +wb_adr[6] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +wb_adr[7] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +wb_dati[0] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +wb_dati[1] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +================================================================================ @@ -609,7 +591,7 @@ Path information for path number 1: - Propagation time: 2.357 - Clock delay at starting point: 0.000 (ideal) - = Slack (critical) : -1.828 + = Slack (non-critical) : -1.828 Number of logic level(s): 1 Starting point: CmdUFMShift / Q @@ -624,7 +606,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r - CmdUFMShift Net - - - - 2 CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r - CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r - -N_122 Net - - - - 17 +N_126_i Net - - - - 17 wb_adr[0] FD1P3AX SP In 0.000 2.357 r - ========================================================================================= @@ -637,7 +619,7 @@ Path information for path number 2: - Propagation time: 2.357 - Clock delay at starting point: 0.000 (ideal) - = Slack (critical) : -1.828 + = Slack (non-critical) : -1.828 Number of logic level(s): 1 Starting point: CmdUFMShift / Q @@ -652,7 +634,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r - CmdUFMShift Net - - - - 2 CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r - CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r - -N_122 Net - - - - 17 +N_126_i Net - - - - 17 wb_adr[7] FD1P3AX SP In 0.000 2.357 r - ========================================================================================= @@ -665,7 +647,7 @@ Path information for path number 3: - Propagation time: 2.357 - Clock delay at starting point: 0.000 (ideal) - = Slack (critical) : -1.828 + = Slack (non-critical) : -1.828 Number of logic level(s): 1 Starting point: CmdUFMShift / Q @@ -680,7 +662,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r - CmdUFMShift Net - - - - 2 CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r - CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r - -N_122 Net - - - - 17 +N_126_i Net - - - - 17 wb_adr[6] FD1P3AX SP In 0.000 2.357 r - ========================================================================================= @@ -693,7 +675,7 @@ Path information for path number 4: - Propagation time: 2.357 - Clock delay at starting point: 0.000 (ideal) - = Slack (critical) : -1.828 + = Slack (non-critical) : -1.828 Number of logic level(s): 1 Starting point: CmdUFMShift / Q @@ -708,7 +690,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r - CmdUFMShift Net - - - - 2 CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r - CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r - -N_122 Net - - - - 17 +N_126_i Net - - - - 17 wb_adr[5] FD1P3AX SP In 0.000 2.357 r - ========================================================================================= @@ -721,7 +703,7 @@ Path information for path number 5: - Propagation time: 2.357 - Clock delay at starting point: 0.000 (ideal) - = Slack (critical) : -1.828 + = Slack (non-critical) : -1.828 Number of logic level(s): 1 Starting point: CmdUFMShift / Q @@ -736,7 +718,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r - CmdUFMShift Net - - - - 2 CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r - CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r - -N_122 Net - - - - 17 +N_126_i Net - - - - 17 wb_adr[4] FD1P3AX SP In 0.000 2.357 r - ========================================================================================= @@ -759,13 +741,13 @@ Instance Reference Type Pin Net Time Slac Ready_fast RCLK FD1S3AX Q Ready_fast 1.256 -0.784 LEDEN RCLK FD1S3AX Q LEDEN 1.148 -0.676 n8MEGEN RCLK FD1S3AX Q n8MEGEN 1.108 -0.636 -FS[12] RCLK FD1S3AX Q FS[12] 1.288 9.100 -FS[11] RCLK FD1S3AX Q FS[11] 1.280 9.108 -FS[9] RCLK FD1S3AX Q FS[9] 1.256 9.132 -InitReady RCLK FD1S3AX Q InitReady 1.317 9.708 -FS[16] RCLK FD1S3AX Q FS[16] 1.180 9.845 -FS[17] RCLK FD1S3AX Q FS[17] 1.180 9.845 -FS[15] RCLK FD1S3AX Q FS[15] 1.148 9.877 +InitReady RCLK FD1S3AX Q InitReady 1.337 9.237 +FS[16] RCLK FD1S3AX Q FS[16] 1.204 9.371 +FS[17] RCLK FD1S3AX Q FS[17] 1.204 9.371 +FS[15] RCLK FD1S3AX Q FS[15] 1.188 9.387 +S[0] RCLK FD1S3IX Q CO0 1.244 9.873 +S[1] RCLK FD1S3IX Q S[1] 1.236 9.881 +RASr2 RCLK FD1S3AX Q RASr2 1.228 9.889 ================================================================================== @@ -860,6 +842,34 @@ Path information for path number 3: - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.784 + Number of logic level(s): 1 + Starting point: Ready_fast / Q + Ending point: RBA_0io[1] / D + The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK + The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin SCLK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------- +Ready_fast FD1S3AX Q Out 1.256 1.256 r - +Ready_fast Net - - - - 14 +RBAd[1] ORCALUT4 B In 0.000 1.256 r - +RBAd[1] ORCALUT4 Z Out 0.617 1.873 r - +RBAd_0[1] Net - - - - 1 +RBA_0io[1] OFS1P3DX D In 0.000 1.873 r - +================================================================================= + + +Path information for path number 4: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 1.873 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -0.784 + Number of logic level(s): 1 Starting point: Ready_fast / Q Ending point: RowA[1] / D @@ -878,34 +888,6 @@ RowA[1] FD1S3AX D In 0.000 1.873 r - ================================================================================= -Path information for path number 4: - Requested Period: 1.000 - - Setup time: -0.089 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 1.089 - - - Propagation time: 1.873 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : -0.784 - - Number of logic level(s): 1 - Starting point: Ready_fast / Q - Ending point: RowA[4] / D - The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK - The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------- -Ready_fast FD1S3AX Q Out 1.256 1.256 r - -Ready_fast Net - - - - 14 -RowAd[4] ORCALUT4 B In 0.000 1.256 r - -RowAd[4] ORCALUT4 Z Out 0.617 1.873 r - -RowAd_0[4] Net - - - - 1 -RowA[4] FD1S3AX D In 0.000 1.873 r - -================================================================================= - - Path information for path number 5: Requested Period: 1.000 - Setup time: -0.089 @@ -918,7 +900,7 @@ Path information for path number 5: Number of logic level(s): 1 Starting point: Ready_fast / Q - Ending point: RowA[2] / D + Ending point: RowA[5] / D The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK @@ -927,10 +909,10 @@ Name Type Name Dir Delay Time Fan Out(s --------------------------------------------------------------------------------- Ready_fast FD1S3AX Q Out 1.256 1.256 r - Ready_fast Net - - - - 14 -RowAd[2] ORCALUT4 B In 0.000 1.256 r - -RowAd[2] ORCALUT4 Z Out 0.617 1.873 r - -RowAd_0[2] Net - - - - 1 -RowA[2] FD1S3AX D In 0.000 1.873 r - +RowAd[5] ORCALUT4 B In 0.000 1.256 r - +RowAd[5] ORCALUT4 Z Out 0.617 1.873 f - +RowAd_0[5] Net - - - - 1 +RowA[5] FD1S3AX D In 0.000 1.873 f - ================================================================================= @@ -945,15 +927,14 @@ Detailed Report for Clock: nCRAS Starting Points with Worst Slack ******************************** - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock --------------------------------------------------------------------------------- -CBR nCRAS FD1S3AX Q CBR 1.148 -1.693 -FWEr nCRAS FD1S3AX Q FWEr 1.148 -1.693 -CBR_fast nCRAS FD1S3AX Q CBR_fast 1.044 -1.661 -FWEr_fast nCRAS FD1S3AX Q FWEr_fast 0.972 -1.589 -================================================================================ + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------ +CBR_fast nCRAS FD1S3AX Q CBR_fast 0.972 -2.605 +CBR nCRAS FD1S3AX Q CBR 1.180 -1.797 +FWEr nCRAS FD1S3AX Q FWEr 1.180 -1.797 +============================================================================== Ending Points with Worst Slack @@ -963,11 +944,11 @@ Ending Points with Worst Slack Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------- -RCKEEN nCRAS FD1S3AX D RCKEEN_8 1.089 -1.693 -nRCAS_0io nCRAS OFS1P3BX D N_242_i 1.089 -1.693 -nRCS_0io nCRAS OFS1P3BX D N_28_i 1.089 -1.693 -nRowColSel nCRAS FD1S3IX D nRowColSel_0_0 1.089 -1.693 -nRWE_0io nCRAS OFS1P3BX D N_37_i 1.089 -1.661 +nRCAS_0io nCRAS OFS1P3BX D N_251_i 1.089 -2.605 +nRCS_0io nCRAS OFS1P3BX D N_37_i 1.089 -1.797 +nRWE_0io nCRAS OFS1P3BX D N_252_i 1.089 -1.797 +nRowColSel nCRAS FD1S3IX D nRowColSel_0_0 1.089 -1.797 +RCKEEN nCRAS FD1S3AX D RCKEEN_8 1.089 -1.725 ======================================================================================== @@ -982,29 +963,32 @@ Path information for path number 1: + Clock delay at ending point: 0.000 (ideal) = Required time: 1.089 - - Propagation time: 2.781 + - Propagation time: 3.694 - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : -1.693 + = Slack (critical) : -2.605 - Number of logic level(s): 2 - Starting point: CBR / Q + Number of logic level(s): 3 + Starting point: CBR_fast / Q Ending point: nRCAS_0io / D The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------- -CBR FD1S3AX Q Out 1.148 1.148 r - -CBR Net - - - - 4 -nRCAS_0io_RNO_0 ORCALUT4 A In 0.000 1.148 r - -nRCAS_0io_RNO_0 ORCALUT4 Z Out 1.017 2.165 f - -N_242_i_1 Net - - - - 1 -nRCAS_0io_RNO ORCALUT4 C In 0.000 2.165 f - -nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.781 r - -N_242_i Net - - - - 1 -nRCAS_0io OFS1P3BX D In 0.000 2.781 r - -================================================================================== +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +------------------------------------------------------------------------------------ +CBR_fast FD1S3AX Q Out 0.972 0.972 r - +CBR_fast Net - - - - 1 +CBR_fast_RNIQ31K1 ORCALUT4 A In 0.000 0.972 r - +CBR_fast_RNIQ31K1 ORCALUT4 Z Out 1.089 2.061 r - +nRCAS_0_sqmuxa_1 Net - - - - 2 +nRCAS_0io_RNO_0 ORCALUT4 B In 0.000 2.061 r - +nRCAS_0io_RNO_0 ORCALUT4 Z Out 1.017 3.077 r - +N_251_i_sx Net - - - - 1 +nRCAS_0io_RNO ORCALUT4 C In 0.000 3.077 r - +nRCAS_0io_RNO ORCALUT4 Z Out 0.617 3.694 f - +N_251_i Net - - - - 1 +nRCAS_0io OFS1P3BX D In 0.000 3.694 f - +==================================================================================== Path information for path number 2: @@ -1013,29 +997,29 @@ Path information for path number 2: + Clock delay at ending point: 0.000 (ideal) = Required time: 1.089 - - Propagation time: 2.781 + - Propagation time: 2.885 - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : -1.693 + = Slack (non-critical) : -1.797 Number of logic level(s): 2 - Starting point: FWEr / Q - Ending point: RCKEEN / D + Starting point: CBR / Q + Ending point: nRCS_0io / D The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK - The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK + The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------- -FWEr FD1S3AX Q Out 1.148 1.148 r - -FWEr Net - - - - 4 -RCKEEN_8_u_1_0 ORCALUT4 C In 0.000 1.148 r - -RCKEEN_8_u_1_0 ORCALUT4 Z Out 1.017 2.165 r - -RCKEEN_8_u_1 Net - - - - 1 -RCKEEN_8_u ORCALUT4 C In 0.000 2.165 r - -RCKEEN_8_u ORCALUT4 Z Out 0.617 2.781 r - -RCKEEN_8 Net - - - - 1 -RCKEEN FD1S3AX D In 0.000 2.781 r - -================================================================================= +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +------------------------------------------------------------------------------------ +CBR FD1S3AX Q Out 1.180 1.180 r - +CBR Net - - - - 5 +RCKEEN_8_u_0_a2_2 ORCALUT4 A In 0.000 1.180 r - +RCKEEN_8_u_0_a2_2 ORCALUT4 Z Out 1.089 2.269 f - +N_141 Net - - - - 2 +nRCS_0io_RNO ORCALUT4 A In 0.000 2.269 f - +nRCS_0io_RNO ORCALUT4 Z Out 0.617 2.885 r - +N_37_i Net - - - - 1 +nRCS_0io OFS1P3BX D In 0.000 2.885 r - +==================================================================================== Path information for path number 3: @@ -1044,71 +1028,9 @@ Path information for path number 3: + Clock delay at ending point: 0.000 (ideal) = Required time: 1.089 - - Propagation time: 2.781 + - Propagation time: 2.885 - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : -1.693 - - Number of logic level(s): 2 - Starting point: CBR / Q - Ending point: nRowColSel / D - The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK - The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------- -CBR FD1S3AX Q Out 1.148 1.148 r - -CBR Net - - - - 4 -nRowColSel_0_0_a3_0 ORCALUT4 B In 0.000 1.148 r - -nRowColSel_0_0_a3_0 ORCALUT4 Z Out 1.017 2.165 f - -N_255 Net - - - - 1 -nRowColSel_0_0 ORCALUT4 B In 0.000 2.165 f - -nRowColSel_0_0 ORCALUT4 Z Out 0.617 2.781 f - -nRowColSel_0_0 Net - - - - 1 -nRowColSel FD1S3IX D In 0.000 2.781 f - -====================================================================================== - - -Path information for path number 4: - Requested Period: 1.000 - - Setup time: -0.089 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 1.089 - - - Propagation time: 2.781 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : -1.693 - - Number of logic level(s): 2 - Starting point: FWEr / Q - Ending point: nRCS_0io / D - The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK - The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------- -FWEr FD1S3AX Q Out 1.148 1.148 r - -FWEr Net - - - - 4 -nRCS_0io_RNO_0 ORCALUT4 B In 0.000 1.148 r - -nRCS_0io_RNO_0 ORCALUT4 Z Out 1.017 2.165 f - -nRCS_0io_RNO_0 Net - - - - 1 -nRCS_0io_RNO ORCALUT4 B In 0.000 2.165 f - -nRCS_0io_RNO ORCALUT4 Z Out 0.617 2.781 r - -N_28_i Net - - - - 1 -nRCS_0io OFS1P3BX D In 0.000 2.781 r - -================================================================================= - - -Path information for path number 5: - Requested Period: 1.000 - - Setup time: -0.089 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 1.089 - - - Propagation time: 2.781 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : -1.693 + = Slack (non-critical) : -1.797 Number of logic level(s): 2 Starting point: FWEr / Q @@ -1119,18 +1041,80 @@ Path information for path number 5: Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------- -FWEr FD1S3AX Q Out 1.148 1.148 r - -FWEr Net - - - - 4 -nRCAS_0io_RNO_0 ORCALUT4 C In 0.000 1.148 r - -nRCAS_0io_RNO_0 ORCALUT4 Z Out 1.017 2.165 r - -N_242_i_1 Net - - - - 1 -nRCAS_0io_RNO ORCALUT4 C In 0.000 2.165 r - -nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.781 f - -N_242_i Net - - - - 1 -nRCAS_0io OFS1P3BX D In 0.000 2.781 f - +FWEr FD1S3AX Q Out 1.180 1.180 r - +FWEr Net - - - - 5 +nRCS_9_u_i_a2_0 ORCALUT4 B In 0.000 1.180 r - +nRCS_9_u_i_a2_0 ORCALUT4 Z Out 1.089 2.269 f - +N_251_i_1 Net - - - - 2 +nRCAS_0io_RNO ORCALUT4 A In 0.000 2.269 f - +nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.885 r - +N_251_i Net - - - - 1 +nRCAS_0io OFS1P3BX D In 0.000 2.885 r - ================================================================================== +Path information for path number 4: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 2.885 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -1.797 + + Number of logic level(s): 2 + Starting point: CBR / Q + Ending point: nRWE_0io / D + The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +------------------------------------------------------------------------------------ +CBR FD1S3AX Q Out 1.180 1.180 r - +CBR Net - - - - 5 +RCKEEN_8_u_0_a2_2 ORCALUT4 A In 0.000 1.180 r - +RCKEEN_8_u_0_a2_2 ORCALUT4 Z Out 1.089 2.269 f - +N_141 Net - - - - 2 +nRWE_0io_RNO ORCALUT4 B In 0.000 2.269 f - +nRWE_0io_RNO ORCALUT4 Z Out 0.617 2.885 r - +N_252_i Net - - - - 1 +nRWE_0io OFS1P3BX D In 0.000 2.885 r - +==================================================================================== + + +Path information for path number 5: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 2.885 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -1.797 + + Number of logic level(s): 2 + Starting point: FWEr / Q + Ending point: nRCAS_0io / D + The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------- +FWEr FD1S3AX Q Out 1.180 1.180 r - +FWEr Net - - - - 5 +nRowColSel_0_0_a2_1 ORCALUT4 B In 0.000 1.180 r - +nRowColSel_0_0_a2_1 ORCALUT4 Z Out 1.089 2.269 r - +N_251_i_1_0 Net - - - - 2 +nRCAS_0io_RNO ORCALUT4 B In 0.000 2.269 r - +nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.885 f - +N_251_i Net - - - - 1 +nRCAS_0io OFS1P3BX D In 0.000 2.885 f - +====================================================================================== + + ==================================== @@ -1155,14 +1139,14 @@ ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 Ending Points with Worst Slack ****************************** - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------ -LEDEN System FD1S3AX D LEDENe_0 16.089 12.918 -n8MEGEN System FD1S3AX D n8MEGENe_0 16.089 12.918 -wb_cyc_stb System FD1P3IX SP N_103 15.528 14.912 -=================================================================================== + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------------------------- +LEDEN System FD1S3AX D LEDENe_0 16.089 12.918 +n8MEGEN System FD1S3AX D n8MEGENe_0 16.089 12.918 +wb_cyc_stb System FD1P3IX SP wb_cyc_stb_2_sqmuxa_i_0_0 15.528 14.912 +================================================================================================== @@ -1187,25 +1171,25 @@ Path information for path number 1: The start point is clocked by System [rising] The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------ -ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 r - -wb_ack Net - - - - 2 -ufmefb.EFBInst_0_RNI8K48 ORCALUT4 C In 0.000 0.000 r - -ufmefb.EFBInst_0_RNI8K48 ORCALUT4 Z Out 0.449 0.449 r - -g0_0_a3_1 Net - - - - 1 -wb_cyc_stb_2_sqmuxa_i_o2_RNI167R ORCALUT4 D In 0.000 0.449 r - -wb_cyc_stb_2_sqmuxa_i_o2_RNI167R ORCALUT4 Z Out 1.017 1.466 r - -N_4 Net - - - - 1 -CmdValid_RNITBH02 ORCALUT4 C In 0.000 1.466 r - -CmdValid_RNITBH02 ORCALUT4 Z Out 1.089 2.554 r - -CmdValid_RNITBH02 Net - - - - 2 -LEDENe ORCALUT4 B In 0.000 2.554 r - -LEDENe ORCALUT4 Z Out 0.617 3.171 r - -LEDENe_0 Net - - - - 1 -LEDEN FD1S3AX D In 0.000 3.171 r - -===================================================================================================== +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +---------------------------------------------------------------------------------------------- +ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 r - +wb_ack Net - - - - 2 +ufmefb.EFBInst_0_RNISGNB ORCALUT4 D In 0.000 0.000 r - +ufmefb.EFBInst_0_RNISGNB ORCALUT4 Z Out 1.017 1.017 r - +g0_0_a3_2 Net - - - - 1 +ufmefb.EFBInst_0_RNISI191 ORCALUT4 C In 0.000 1.017 r - +ufmefb.EFBInst_0_RNISI191 ORCALUT4 Z Out 0.449 1.466 r - +N_4 Net - - - - 1 +CmdValid_RNIOOBE2 ORCALUT4 C In 0.000 1.466 r - +CmdValid_RNIOOBE2 ORCALUT4 Z Out 1.089 2.554 r - +un1_FS_38_i Net - - - - 2 +LEDENe ORCALUT4 C In 0.000 2.554 r - +LEDENe ORCALUT4 Z Out 0.617 3.171 r - +LEDENe_0 Net - - - - 1 +LEDEN FD1S3AX D In 0.000 3.171 r - +============================================================================================== @@ -1213,16 +1197,16 @@ LEDEN FD1S3AX D In 0.000 3 Timing exceptions that could not be applied -Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 201MB peak: 202MB) +Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 202MB peak: 203MB) -Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 201MB peak: 202MB) +Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 202MB peak: 203MB) --------------------------------------- Resource Usage Report Part: lcmxo2_1200hc-4 -Register bits: 110 of 1280 (9%) +Register bits: 109 of 1280 (9%) PIC Latch: 0 I/O cells: 64 @@ -1233,7 +1217,7 @@ CCU2D: 10 EFB: 1 FD1P3AX: 25 FD1P3IX: 2 -FD1S3AX: 54 +FD1S3AX: 53 FD1S3IX: 4 GSR: 1 IB: 25 @@ -1244,16 +1228,17 @@ ODDRXE: 1 OFS1P3BX: 4 OFS1P3DX: 11 OFS1P3JX: 1 -ORCALUT4: 203 +ORCALUT4: 212 +PFUMX: 2 PUR: 1 VHI: 2 VLO: 2 Mapper successful! -At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 78MB peak: 202MB) +At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 78MB peak: 203MB) -Process took 0h:00m:03s realtime, 0h:00m:03s cputime -# Thu Oct 19 23:50:54 2023 +Process took 0h:00m:04s realtime, 0h:00m:04s cputime +# Sat Nov 18 02:05:49 2023 ###########################################################] diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_tw1.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_tw1.html index 44d8626..ca5a07b 100644 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_tw1.html +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_tw1.html @@ -22,7 +22,7 @@ Setup and Hold Report -------------------------------------------------------------------------------- Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 -Thu Oct 19 23:50:57 2023 +Sat Nov 18 02:05:54 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -42,7 +42,7 @@ Report level: verbose report, limited to 1 item per preference Preference Summary
  • FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)
    • 147 items scored, 0 timing errors detected. -Report: 57.904MHz is the maximum frequency for this preference. +Report: 53.254MHz is the maximum frequency for this preference.
  • FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)
    • 0 items scored, 0 timing errors detected. Report: 150.150MHz is the maximum frequency for this preference. @@ -50,8 +50,8 @@ Report: 150.150MHz is the maximum frequency for this preference.
  • FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)
    • 0 items scored, 0 timing errors detected. Report: 150.150MHz is the maximum frequency for this preference. -
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    • 868 items scored, 0 timing errors detected. -Report: 97.666MHz is the maximum frequency for this preference. +
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    • 891 items scored, 0 timing errors detected. +Report: 95.383MHz is the maximum frequency for this preference. BLOCK ASYNCPATHS BLOCK RESETPATHS @@ -65,42 +65,42 @@ BLOCK RESETPATHS -------------------------------------------------------------------------------- -Passed: The following path meets requirements by 163.779ns (weighted slack = 327.558ns) +Passed: The following path meets requirements by 163.025ns (weighted slack = 326.050ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_0io[0] (from PHI2_c +) - Destination: FF Data in ADSubmitted (to PHI2_c -) + Source: FF Q Bank_0io[1] (from PHI2_c +) + Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 8.469ns (36.0% logic, 64.0% route), 6 logic levels. + Delay: 9.223ns (33.1% logic, 66.9% route), 6 logic levels. Constraint Details: - 8.469ns physical path delay Din[0]_MGIOL to SLICE_10 meets + 9.223ns physical path delay Din[1]_MGIOL to SLICE_17 meets 172.414ns delay constraint less - 0.166ns DIN_SET requirement (totaling 172.248ns) by 163.779ns + 0.166ns DIN_SET requirement (totaling 172.248ns) by 163.025ns Physical Path Details: - Data path Din[0]_MGIOL to SLICE_10: + Data path Din[1]_MGIOL to SLICE_17: Name Fanout Delay (ns) Site Resource -C2INP_DEL --- 0.577 *[0]_MGIOL.CLK to *n[0]_MGIOL.IN Din[0]_MGIOL (from PHI2_c) -ROUTE 1 e 1.234 *n[0]_MGIOL.IN to SLICE_89.A0 Bank[0] -CTOF_DEL --- 0.495 SLICE_89.A0 to SLICE_89.F0 SLICE_89 -ROUTE 1 e 1.234 SLICE_89.F0 to SLICE_75.C1 un1_ADWR_i_o2_10 -CTOF_DEL --- 0.495 SLICE_75.C1 to SLICE_75.F1 SLICE_75 -ROUTE 8 e 0.480 SLICE_75.F1 to SLICE_75.B0 N_294 -CTOF_DEL --- 0.495 SLICE_75.B0 to SLICE_75.F0 SLICE_75 -ROUTE 2 e 1.234 SLICE_75.F0 to SLICE_73.C0 N_382 -CTOF_DEL --- 0.495 SLICE_73.C0 to SLICE_73.F0 SLICE_73 -ROUTE 2 e 1.234 SLICE_73.F0 to SLICE_10.C0 CmdEnable17 -CTOF_DEL --- 0.495 SLICE_10.C0 to SLICE_10.F0 SLICE_10 -ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r_0 (to PHI2_c) +C2INP_DEL --- 0.577 *[1]_MGIOL.CLK to *n[1]_MGIOL.IN Din[1]_MGIOL (from PHI2_c) +ROUTE 1 e 1.234 *n[1]_MGIOL.IN to SLICE_90.A0 Bank[1] +CTOF_DEL --- 0.495 SLICE_90.A0 to SLICE_90.F0 SLICE_90 +ROUTE 1 e 1.234 SLICE_90.F0 to SLICE_80.C0 un1_CmdEnable20_0_0_o2_10 +CTOF_DEL --- 0.495 SLICE_80.C0 to SLICE_80.F0 SLICE_80 +ROUTE 6 e 1.234 SLICE_80.F0 to SLICE_11.C1 N_367 +CTOF_DEL --- 0.495 SLICE_11.C1 to SLICE_11.F1 SLICE_11 +ROUTE 3 e 1.234 SLICE_11.F1 to SLICE_33.B0 CmdEnable16 +CTOF_DEL --- 0.495 SLICE_33.B0 to SLICE_33.F0 SLICE_33 +ROUTE 1 e 1.234 SLICE_33.F0 to SLICE_17.D0 CmdEnable_0_sqmuxa +CTOF_DEL --- 0.495 SLICE_17.D0 to SLICE_17.F0 SLICE_17 +ROUTE 1 e 0.001 SLICE_17.F0 to SLICE_17.DI0 CmdEnable_s (to PHI2_c) -------- - 8.469 (36.0% logic, 64.0% route), 6 logic levels. + 9.223 (33.1% logic, 66.9% route), 6 logic levels. -Report: 57.904MHz is the maximum frequency for this preference. +Report: 53.254MHz is the maximum frequency for this preference. ================================================================================ @@ -141,48 +141,46 @@ Report: 150.150MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; - 868 items scored, 0 timing errors detected. + 891 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- -Passed: The following path meets requirements by 5.761ns +Passed: The following path meets requirements by 5.516ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS[11] (from RCLK_c +) - Destination: FF Data in wb_adr[0] (to RCLK_c +) + Source: FF Q S[0] (from RCLK_c +) + Destination: FF Data in nRWE_0io (to RCLK_c +) - Delay: 10.073ns (34.0% logic, 66.0% route), 7 logic levels. + Delay: 10.331ns (28.3% logic, 71.7% route), 6 logic levels. Constraint Details: - 10.073ns physical path delay SLICE_4 to SLICE_48 meets + 10.331ns physical path delay SLICE_16 to nRWE_MGIOL meets 16.000ns delay constraint less - 0.166ns DIN_SET requirement (totaling 15.834ns) by 5.761ns + 0.153ns DO_SET requirement (totaling 15.847ns) by 5.516ns Physical Path Details: - Data path SLICE_4 to SLICE_48: + Data path SLICE_16 to nRWE_MGIOL: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 SLICE_4.CLK to SLICE_4.Q0 SLICE_4 (from RCLK_c) -ROUTE 21 e 1.234 SLICE_4.Q0 to SLICE_66.B1 FS[11] -CTOF_DEL --- 0.495 SLICE_66.B1 to SLICE_66.F1 SLICE_66 -ROUTE 1 e 0.480 SLICE_66.F1 to SLICE_66.D0 wb_adr_5_i_i_a2_3_0[0] -CTOF_DEL --- 0.495 SLICE_66.D0 to SLICE_66.F0 SLICE_66 -ROUTE 1 e 1.234 SLICE_66.F0 to SLICE_86.D0 wb_adr_5_i_i_1_0_tz_0[0] -CTOF_DEL --- 0.495 SLICE_86.D0 to SLICE_86.F0 SLICE_86 -ROUTE 1 e 1.234 SLICE_86.F0 to SLICE_85.C0 wb_adr_5_i_i_1_0[0] -CTOF_DEL --- 0.495 SLICE_85.C0 to SLICE_85.F0 SLICE_85 -ROUTE 1 e 1.234 SLICE_85.F0 to SLICE_77.D0 wb_adr_5_i_i_1[0] -CTOF_DEL --- 0.495 SLICE_77.D0 to SLICE_77.F0 SLICE_77 -ROUTE 1 e 1.234 SLICE_77.F0 to SLICE_48.D0 wb_adr_5_i_i_5[0] -CTOF_DEL --- 0.495 SLICE_48.D0 to SLICE_48.F0 SLICE_48 -ROUTE 1 e 0.001 SLICE_48.F0 to SLICE_48.DI0 N_283 (to RCLK_c) +REG_DEL --- 0.452 SLICE_16.CLK to SLICE_16.Q0 SLICE_16 (from RCLK_c) +ROUTE 12 e 1.234 SLICE_16.Q0 to SLICE_62.D1 CO0 +CTOF_DEL --- 0.495 SLICE_62.D1 to SLICE_62.F1 SLICE_62 +ROUTE 6 e 1.234 SLICE_62.F1 to SLICE_79.A1 IS_0_sqmuxa_0_o2 +CTOF_DEL --- 0.495 SLICE_79.A1 to SLICE_79.F1 SLICE_79 +ROUTE 2 e 1.234 SLICE_79.F1 to SLICE_28.D1 IS_0_sqmuxa_0_o3 +CTOF_DEL --- 0.495 SLICE_28.D1 to SLICE_28.F1 SLICE_28 +ROUTE 1 e 1.234 SLICE_28.F1 to SLICE_68.D1 nRWE_s_i_a2_1_0 +CTOF_DEL --- 0.495 SLICE_68.D1 to SLICE_68.F1 SLICE_68 +ROUTE 1 e 1.234 SLICE_68.F1 to SLICE_75.D0 nRWE_s_i_tz_0 +CTOF_DEL --- 0.495 SLICE_75.D0 to SLICE_75.F0 SLICE_75 +ROUTE 1 e 1.234 SLICE_75.F0 to *WE_MGIOL.OPOS N_252_i (to RCLK_c) -------- - 10.073 (34.0% logic, 66.0% route), 7 logic levels. + 10.331 (28.3% logic, 71.7% route), 6 logic levels. -Report: 97.666MHz is the maximum frequency for this preference. +Report: 95.383MHz is the maximum frequency for this preference. Report Summary -------------- @@ -190,13 +188,13 @@ Report: 97.666MHz is the maximum frequency for this preference. Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | -FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 57.904 MHz| 6 +FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 53.254 MHz| 6 | | | FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0 | | | FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0 | | | -FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 97.666 MHz| 7 +FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 95.383 MHz| 6 | | | ---------------------------------------------------------------------------- @@ -209,7 +207,7 @@ All preferences were met. Found 4 clocks: -Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12 +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11 No transfer within this clock domain is found Data transfers from: @@ -251,11 +249,11 @@ Clock Domain: PHI2_c Source: PHI2.PAD Loads: 21 Timing errors: 0 Score: 0 Cumulative negative slack: 0 -Constraints cover 1015 paths, 4 nets, and 706 connections (71.10% coverage) +Constraints cover 1038 paths, 4 nets, and 732 connections (72.40% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 -Thu Oct 19 23:50:58 2023 +Sat Nov 18 02:05:54 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -280,7 +278,7 @@ Report level: verbose report, limited to 1 item per preference
  • FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)
    • 0 items scored, 0 timing errors detected. -
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    • 868 items scored, 0 timing errors detected. +
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    • 891 items scored, 0 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS @@ -317,7 +315,7 @@ Passed: The following path meets requirements by 0.447ns REG_DEL --- 0.133 SLICE_10.CLK to SLICE_10.Q0 SLICE_10 (from PHI2_c) ROUTE 2 e 0.199 SLICE_10.Q0 to SLICE_10.A0 ADSubmitted CTOF_DEL --- 0.101 SLICE_10.A0 to SLICE_10.F0 SLICE_10 -ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r_0 (to PHI2_c) +ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r_0_0 (to PHI2_c) -------- 0.434 (53.9% logic, 46.1% route), 2 logic levels. @@ -336,7 +334,7 @@ ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r_0 (to P ================================================================================ Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; - 868 items scored, 0 timing errors detected. + 891 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- @@ -390,7 +388,7 @@ All preferences were met. Found 4 clocks: -Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12 +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11 No transfer within this clock domain is found Data transfers from: @@ -432,7 +430,7 @@ Clock Domain: PHI2_c Source: PHI2.PAD Loads: 21 Timing errors: 0 Score: 0 Cumulative negative slack: 0 -Constraints cover 1015 paths, 4 nets, and 706 connections (71.10% coverage) +Constraints cover 1038 paths, 4 nets, and 732 connections (72.40% coverage) diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_twr.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_twr.html index d59b6fe..5738d9e 100644 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_twr.html +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_twr.html @@ -22,7 +22,7 @@ Setup and Hold Report -------------------------------------------------------------------------------- Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 -Thu Oct 19 23:51:11 2023 +Sat Nov 18 02:06:13 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -42,7 +42,7 @@ Report level: verbose report, limited to 10 items per preference Preference Summary
  • FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)
    • 147 items scored, 0 timing errors detected. -Report: 50.206MHz is the maximum frequency for this preference. +Report: 48.464MHz is the maximum frequency for this preference.
  • FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)
    • 0 items scored, 0 timing errors detected. Report: 150.150MHz is the maximum frequency for this preference. @@ -50,8 +50,8 @@ Report: 150.150MHz is the maximum frequency for this preference.
  • FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)
    • 0 items scored, 0 timing errors detected. Report: 150.150MHz is the maximum frequency for this preference. -
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    • 868 items scored, 0 timing errors detected. -Report: 98.020MHz is the maximum frequency for this preference. +
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    • 891 items scored, 0 timing errors detected. +Report: 102.197MHz is the maximum frequency for this preference. BLOCK ASYNCPATHS BLOCK RESETPATHS @@ -65,127 +65,174 @@ BLOCK RESETPATHS -------------------------------------------------------------------------------- -Passed: The following path meets requirements by 162.455ns (weighted slack = 324.910ns) +Passed: The following path meets requirements by 162.097ns (weighted slack = 324.194ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_0io[0] (from PHI2_c +) - Destination: FF Data in CmdEnable (to PHI2_c -) + Source: FF Q Bank_0io[7] (from PHI2_c +) + Destination: FF Data in CmdUFMData (to PHI2_c -) - Delay: 9.620ns (31.7% logic, 68.3% route), 6 logic levels. + Delay: 9.837ns (26.0% logic, 74.0% route), 5 logic levels. Constraint Details: - 9.620ns physical path delay Din[0]_MGIOL to SLICE_17 meets + 9.837ns physical path delay Din[7]_MGIOL to SLICE_19 meets 172.414ns delay constraint less 0.173ns skew and - 0.166ns DIN_SET requirement (totaling 172.075ns) by 162.455ns + 0.307ns CE_SET requirement (totaling 171.934ns) by 162.097ns Physical Path Details: - Data path Din[0]_MGIOL to SLICE_17: + Data path Din[7]_MGIOL to SLICE_19: Name Fanout Delay (ns) Site Resource -C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c) -ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0] -CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_89 -ROUTE 1 1.001 R4C11A.F0 to R4C10A.B1 un1_ADWR_i_o2_10 -CTOF_DEL --- 0.495 R4C10A.B1 to R4C10A.F1 SLICE_75 -ROUTE 8 0.710 R4C10A.F1 to R4C10A.B0 N_294 -CTOF_DEL --- 0.495 R4C10A.B0 to R4C10A.F0 SLICE_75 -ROUTE 2 1.093 R4C10A.F0 to R5C11A.C0 N_382 -CTOF_DEL --- 0.495 R5C11A.C0 to R5C11A.F0 SLICE_73 -ROUTE 2 1.013 R5C11A.F0 to R5C11D.B0 CmdEnable17 -CTOF_DEL --- 0.495 R5C11D.B0 to R5C11D.F0 SLICE_17 -ROUTE 1 0.000 R5C11D.F0 to R5C11D.DI0 CmdEnable_s (to PHI2_c) +C2INP_DEL --- 0.577 IOL_L2C.CLK to IOL_L2C.IN Din[7]_MGIOL (from PHI2_c) +ROUTE 1 2.215 IOL_L2C.IN to R4C10D.A0 Bank[7] +CTOF_DEL --- 0.495 R4C10D.A0 to R4C10D.F0 SLICE_90 +ROUTE 1 0.958 R4C10D.F0 to R2C9D.D0 un1_CmdEnable20_0_0_o2_10 +CTOF_DEL --- 0.495 R2C9D.D0 to R2C9D.F0 SLICE_80 +ROUTE 6 1.104 R2C9D.F0 to R5C9A.D1 N_367 +CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_23 +ROUTE 8 1.295 R5C9A.F1 to R7C10B.C0 XOR8MEG18 +CTOF_DEL --- 0.495 R7C10B.C0 to R7C10B.F0 SLICE_77 +ROUTE 1 1.708 R7C10B.F0 to R7C11B.CE CmdUFMData_1_sqmuxa (to PHI2_c) -------- - 9.620 (31.7% logic, 68.3% route), 6 logic levels. + 9.837 (26.0% logic, 74.0% route), 5 logic levels. Clock Skew Details: - Source Clock Path PHI2 to Din[0]_MGIOL: + Source Clock Path PHI2 to Din[7]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c +ROUTE 21 4.369 8.PADDI to IOL_L2C.CLK PHI2_c -------- 4.369 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_17: + Destination Clock Path PHI2 to SLICE_19: Name Fanout Delay (ns) Site Resource -ROUTE 21 4.196 8.PADDI to R5C11D.CLK PHI2_c +ROUTE 21 4.196 8.PADDI to R7C11B.CLK PHI2_c -------- 4.196 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 162.715ns (weighted slack = 325.430ns) +Passed: The following path meets requirements by 162.937ns (weighted slack = 325.874ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_0io[0] (from PHI2_c +) - Destination: FF Data in ADSubmitted (to PHI2_c -) + Source: FF Q Bank_0io[1] (from PHI2_c +) + Destination: FF Data in CmdUFMData (to PHI2_c -) - Delay: 9.360ns (32.6% logic, 67.4% route), 6 logic levels. + Delay: 8.997ns (28.4% logic, 71.6% route), 5 logic levels. Constraint Details: - 9.360ns physical path delay Din[0]_MGIOL to SLICE_10 meets + 8.997ns physical path delay Din[1]_MGIOL to SLICE_19 meets 172.414ns delay constraint less 0.173ns skew and - 0.166ns DIN_SET requirement (totaling 172.075ns) by 162.715ns + 0.307ns CE_SET requirement (totaling 171.934ns) by 162.937ns Physical Path Details: - Data path Din[0]_MGIOL to SLICE_10: + Data path Din[1]_MGIOL to SLICE_19: Name Fanout Delay (ns) Site Resource -C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c) -ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0] -CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_89 -ROUTE 1 1.001 R4C11A.F0 to R4C10A.B1 un1_ADWR_i_o2_10 -CTOF_DEL --- 0.495 R4C10A.B1 to R4C10A.F1 SLICE_75 -ROUTE 8 0.710 R4C10A.F1 to R4C10A.B0 N_294 -CTOF_DEL --- 0.495 R4C10A.B0 to R4C10A.F0 SLICE_75 -ROUTE 2 1.093 R4C10A.F0 to R5C11A.C0 N_382 -CTOF_DEL --- 0.495 R5C11A.C0 to R5C11A.F0 SLICE_73 -ROUTE 2 0.753 R5C11A.F0 to R5C12C.C0 CmdEnable17 -CTOF_DEL --- 0.495 R5C12C.C0 to R5C12C.F0 SLICE_10 -ROUTE 1 0.000 R5C12C.F0 to R5C12C.DI0 ADSubmitted_r_0 (to PHI2_c) +C2INP_DEL --- 0.577 IOL_T10B.CLK to IOL_T10B.IN Din[1]_MGIOL (from PHI2_c) +ROUTE 1 1.375 IOL_T10B.IN to R4C10D.D0 Bank[1] +CTOF_DEL --- 0.495 R4C10D.D0 to R4C10D.F0 SLICE_90 +ROUTE 1 0.958 R4C10D.F0 to R2C9D.D0 un1_CmdEnable20_0_0_o2_10 +CTOF_DEL --- 0.495 R2C9D.D0 to R2C9D.F0 SLICE_80 +ROUTE 6 1.104 R2C9D.F0 to R5C9A.D1 N_367 +CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_23 +ROUTE 8 1.295 R5C9A.F1 to R7C10B.C0 XOR8MEG18 +CTOF_DEL --- 0.495 R7C10B.C0 to R7C10B.F0 SLICE_77 +ROUTE 1 1.708 R7C10B.F0 to R7C11B.CE CmdUFMData_1_sqmuxa (to PHI2_c) -------- - 9.360 (32.6% logic, 67.4% route), 6 logic levels. + 8.997 (28.4% logic, 71.6% route), 5 logic levels. Clock Skew Details: - Source Clock Path PHI2 to Din[0]_MGIOL: + Source Clock Path PHI2 to Din[1]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c +ROUTE 21 4.369 8.PADDI to IOL_T10B.CLK PHI2_c -------- 4.369 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_10: + Destination Clock Path PHI2 to SLICE_19: Name Fanout Delay (ns) Site Resource -ROUTE 21 4.196 8.PADDI to R5C12C.CLK PHI2_c +ROUTE 21 4.196 8.PADDI to R7C11B.CLK PHI2_c -------- 4.196 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 162.913ns (weighted slack = 325.826ns) +Passed: The following path meets requirements by 163.032ns (weighted slack = 326.064ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_0io[6] (from PHI2_c +) + Destination: FF Data in CmdUFMData (to PHI2_c -) + + Delay: 8.902ns (28.7% logic, 71.3% route), 5 logic levels. + + Constraint Details: + + 8.902ns physical path delay Din[6]_MGIOL to SLICE_19 meets + 172.414ns delay constraint less + 0.173ns skew and + 0.307ns CE_SET requirement (totaling 171.934ns) by 163.032ns + + Physical Path Details: + + Data path Din[6]_MGIOL to SLICE_19: + + Name Fanout Delay (ns) Site Resource +C2INP_DEL --- 0.577 IOL_L2D.CLK to IOL_L2D.IN Din[6]_MGIOL (from PHI2_c) +ROUTE 1 1.802 IOL_L2D.IN to R2C9D.D1 Bank[6] +CTOF_DEL --- 0.495 R2C9D.D1 to R2C9D.F1 SLICE_80 +ROUTE 1 0.436 R2C9D.F1 to R2C9D.C0 un1_CmdEnable20_0_0_o2_11 +CTOF_DEL --- 0.495 R2C9D.C0 to R2C9D.F0 SLICE_80 +ROUTE 6 1.104 R2C9D.F0 to R5C9A.D1 N_367 +CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_23 +ROUTE 8 1.295 R5C9A.F1 to R7C10B.C0 XOR8MEG18 +CTOF_DEL --- 0.495 R7C10B.C0 to R7C10B.F0 SLICE_77 +ROUTE 1 1.708 R7C10B.F0 to R7C11B.CE CmdUFMData_1_sqmuxa (to PHI2_c) + -------- + 8.902 (28.7% logic, 71.3% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to Din[6]_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 4.369 8.PADDI to IOL_L2D.CLK PHI2_c + -------- + 4.369 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 4.196 8.PADDI to R7C11B.CLK PHI2_c + -------- + 4.196 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 163.085ns (weighted slack = 326.170ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Bank_0io[7] (from PHI2_c +) Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 9.162ns (33.3% logic, 66.7% route), 6 logic levels. + Delay: 8.990ns (33.9% logic, 66.1% route), 6 logic levels. Constraint Details: - 9.162ns physical path delay Din[7]_MGIOL to SLICE_17 meets + 8.990ns physical path delay Din[7]_MGIOL to SLICE_17 meets 172.414ns delay constraint less 0.173ns skew and - 0.166ns DIN_SET requirement (totaling 172.075ns) by 162.913ns + 0.166ns DIN_SET requirement (totaling 172.075ns) by 163.085ns Physical Path Details: @@ -193,19 +240,19 @@ Passed: The following path meets requirements by 162.913ns (weighted slack = 325 Name Fanout Delay (ns) Site Resource C2INP_DEL --- 0.577 IOL_L2C.CLK to IOL_L2C.IN Din[7]_MGIOL (from PHI2_c) -ROUTE 1 2.215 IOL_L2C.IN to R3C9D.A0 Bank[7] -CTOF_DEL --- 0.495 R3C9D.A0 to R3C9D.F0 SLICE_32 -ROUTE 1 1.079 R3C9D.F0 to R4C10A.C1 un1_ADWR_i_o2_11 -CTOF_DEL --- 0.495 R4C10A.C1 to R4C10A.F1 SLICE_75 -ROUTE 8 0.710 R4C10A.F1 to R4C10A.B0 N_294 -CTOF_DEL --- 0.495 R4C10A.B0 to R4C10A.F0 SLICE_75 -ROUTE 2 1.093 R4C10A.F0 to R5C11A.C0 N_382 -CTOF_DEL --- 0.495 R5C11A.C0 to R5C11A.F0 SLICE_73 -ROUTE 2 1.013 R5C11A.F0 to R5C11D.B0 CmdEnable17 -CTOF_DEL --- 0.495 R5C11D.B0 to R5C11D.F0 SLICE_17 -ROUTE 1 0.000 R5C11D.F0 to R5C11D.DI0 CmdEnable_s (to PHI2_c) +ROUTE 1 2.215 IOL_L2C.IN to R4C10D.A0 Bank[7] +CTOF_DEL --- 0.495 R4C10D.A0 to R4C10D.F0 SLICE_90 +ROUTE 1 0.958 R4C10D.F0 to R2C9D.D0 un1_CmdEnable20_0_0_o2_10 +CTOF_DEL --- 0.495 R2C9D.D0 to R2C9D.F0 SLICE_80 +ROUTE 6 1.048 R2C9D.F0 to R4C9A.B1 N_367 +CTOF_DEL --- 0.495 R4C9A.B1 to R4C9A.F1 SLICE_11 +ROUTE 3 0.753 R4C9A.F1 to R4C8A.C0 CmdEnable16 +CTOF_DEL --- 0.495 R4C8A.C0 to R4C8A.F0 SLICE_33 +ROUTE 1 0.964 R4C8A.F0 to R4C9B.A0 CmdEnable_0_sqmuxa +CTOF_DEL --- 0.495 R4C9B.A0 to R4C9B.F0 SLICE_17 +ROUTE 1 0.000 R4C9B.F0 to R4C9B.DI0 CmdEnable_s (to PHI2_c) -------- - 9.162 (33.3% logic, 66.7% route), 6 logic levels. + 8.990 (33.9% logic, 66.1% route), 6 logic levels. Clock Skew Details: @@ -219,95 +266,195 @@ ROUTE 21 4.369 8.PADDI to IOL_L2C.CLK PHI2_c Destination Clock Path PHI2 to SLICE_17: Name Fanout Delay (ns) Site Resource -ROUTE 21 4.196 8.PADDI to R5C11D.CLK PHI2_c +ROUTE 21 4.196 8.PADDI to R4C9B.CLK PHI2_c -------- 4.196 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 163.173ns (weighted slack = 326.346ns) +Passed: The following path meets requirements by 163.118ns (weighted slack = 326.236ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_0io[7] (from PHI2_c +) - Destination: FF Data in ADSubmitted (to PHI2_c -) + Source: FF Q Bank_0io[2] (from PHI2_c +) + Destination: FF Data in CmdUFMData (to PHI2_c -) - Delay: 8.902ns (34.3% logic, 65.7% route), 6 logic levels. + Delay: 8.816ns (29.0% logic, 71.0% route), 5 logic levels. Constraint Details: - 8.902ns physical path delay Din[7]_MGIOL to SLICE_10 meets + 8.816ns physical path delay Din[2]_MGIOL to SLICE_19 meets 172.414ns delay constraint less 0.173ns skew and - 0.166ns DIN_SET requirement (totaling 172.075ns) by 163.173ns + 0.307ns CE_SET requirement (totaling 171.934ns) by 163.118ns Physical Path Details: - Data path Din[7]_MGIOL to SLICE_10: + Data path Din[2]_MGIOL to SLICE_19: Name Fanout Delay (ns) Site Resource -C2INP_DEL --- 0.577 IOL_L2C.CLK to IOL_L2C.IN Din[7]_MGIOL (from PHI2_c) -ROUTE 1 2.215 IOL_L2C.IN to R3C9D.A0 Bank[7] -CTOF_DEL --- 0.495 R3C9D.A0 to R3C9D.F0 SLICE_32 -ROUTE 1 1.079 R3C9D.F0 to R4C10A.C1 un1_ADWR_i_o2_11 -CTOF_DEL --- 0.495 R4C10A.C1 to R4C10A.F1 SLICE_75 -ROUTE 8 0.710 R4C10A.F1 to R4C10A.B0 N_294 -CTOF_DEL --- 0.495 R4C10A.B0 to R4C10A.F0 SLICE_75 -ROUTE 2 1.093 R4C10A.F0 to R5C11A.C0 N_382 -CTOF_DEL --- 0.495 R5C11A.C0 to R5C11A.F0 SLICE_73 -ROUTE 2 0.753 R5C11A.F0 to R5C12C.C0 CmdEnable17 -CTOF_DEL --- 0.495 R5C12C.C0 to R5C12C.F0 SLICE_10 -ROUTE 1 0.000 R5C12C.F0 to R5C12C.DI0 ADSubmitted_r_0 (to PHI2_c) +C2INP_DEL --- 0.577 IOL_T12A.CLK to IOL_T12A.IN Din[2]_MGIOL (from PHI2_c) +ROUTE 1 1.716 IOL_T12A.IN to R2C9D.A1 Bank[2] +CTOF_DEL --- 0.495 R2C9D.A1 to R2C9D.F1 SLICE_80 +ROUTE 1 0.436 R2C9D.F1 to R2C9D.C0 un1_CmdEnable20_0_0_o2_11 +CTOF_DEL --- 0.495 R2C9D.C0 to R2C9D.F0 SLICE_80 +ROUTE 6 1.104 R2C9D.F0 to R5C9A.D1 N_367 +CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_23 +ROUTE 8 1.295 R5C9A.F1 to R7C10B.C0 XOR8MEG18 +CTOF_DEL --- 0.495 R7C10B.C0 to R7C10B.F0 SLICE_77 +ROUTE 1 1.708 R7C10B.F0 to R7C11B.CE CmdUFMData_1_sqmuxa (to PHI2_c) -------- - 8.902 (34.3% logic, 65.7% route), 6 logic levels. + 8.816 (29.0% logic, 71.0% route), 5 logic levels. Clock Skew Details: - Source Clock Path PHI2 to Din[7]_MGIOL: + Source Clock Path PHI2 to Din[2]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 21 4.369 8.PADDI to IOL_L2C.CLK PHI2_c +ROUTE 21 4.369 8.PADDI to IOL_T12A.CLK PHI2_c -------- 4.369 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_10: + Destination Clock Path PHI2 to SLICE_19: Name Fanout Delay (ns) Site Resource -ROUTE 21 4.196 8.PADDI to R5C12C.CLK PHI2_c +ROUTE 21 4.196 8.PADDI to R7C11B.CLK PHI2_c -------- 4.196 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 163.263ns (weighted slack = 326.526ns) +Passed: The following path meets requirements by 163.196ns (weighted slack = 326.392ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_0io[5] (from PHI2_c +) + Destination: FF Data in CmdUFMData (to PHI2_c -) + + Delay: 8.738ns (29.3% logic, 70.7% route), 5 logic levels. + + Constraint Details: + + 8.738ns physical path delay Din[5]_MGIOL to SLICE_19 meets + 172.414ns delay constraint less + 0.173ns skew and + 0.307ns CE_SET requirement (totaling 171.934ns) by 163.196ns + + Physical Path Details: + + Data path Din[5]_MGIOL to SLICE_19: + + Name Fanout Delay (ns) Site Resource +C2INP_DEL --- 0.577 IOL_T9B.CLK to IOL_T9B.IN Din[5]_MGIOL (from PHI2_c) +ROUTE 1 1.638 IOL_T9B.IN to R2C9D.B1 Bank[5] +CTOF_DEL --- 0.495 R2C9D.B1 to R2C9D.F1 SLICE_80 +ROUTE 1 0.436 R2C9D.F1 to R2C9D.C0 un1_CmdEnable20_0_0_o2_11 +CTOF_DEL --- 0.495 R2C9D.C0 to R2C9D.F0 SLICE_80 +ROUTE 6 1.104 R2C9D.F0 to R5C9A.D1 N_367 +CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_23 +ROUTE 8 1.295 R5C9A.F1 to R7C10B.C0 XOR8MEG18 +CTOF_DEL --- 0.495 R7C10B.C0 to R7C10B.F0 SLICE_77 +ROUTE 1 1.708 R7C10B.F0 to R7C11B.CE CmdUFMData_1_sqmuxa (to PHI2_c) + -------- + 8.738 (29.3% logic, 70.7% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to Din[5]_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 4.369 8.PADDI to IOL_T9B.CLK PHI2_c + -------- + 4.369 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 4.196 8.PADDI to R7C11B.CLK PHI2_c + -------- + 4.196 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 163.537ns (weighted slack = 327.074ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_0io[3] (from PHI2_c +) + Destination: FF Data in CmdUFMData (to PHI2_c -) + + Delay: 8.397ns (30.5% logic, 69.5% route), 5 logic levels. + + Constraint Details: + + 8.397ns physical path delay Din[3]_MGIOL to SLICE_19 meets + 172.414ns delay constraint less + 0.173ns skew and + 0.307ns CE_SET requirement (totaling 171.934ns) by 163.537ns + + Physical Path Details: + + Data path Din[3]_MGIOL to SLICE_19: + + Name Fanout Delay (ns) Site Resource +C2INP_DEL --- 0.577 IOL_T10A.CLK to IOL_T10A.IN Din[3]_MGIOL (from PHI2_c) +ROUTE 1 1.297 IOL_T10A.IN to R2C9D.C1 Bank[3] +CTOF_DEL --- 0.495 R2C9D.C1 to R2C9D.F1 SLICE_80 +ROUTE 1 0.436 R2C9D.F1 to R2C9D.C0 un1_CmdEnable20_0_0_o2_11 +CTOF_DEL --- 0.495 R2C9D.C0 to R2C9D.F0 SLICE_80 +ROUTE 6 1.104 R2C9D.F0 to R5C9A.D1 N_367 +CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_23 +ROUTE 8 1.295 R5C9A.F1 to R7C10B.C0 XOR8MEG18 +CTOF_DEL --- 0.495 R7C10B.C0 to R7C10B.F0 SLICE_77 +ROUTE 1 1.708 R7C10B.F0 to R7C11B.CE CmdUFMData_1_sqmuxa (to PHI2_c) + -------- + 8.397 (30.5% logic, 69.5% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to Din[3]_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 4.369 8.PADDI to IOL_T10A.CLK PHI2_c + -------- + 4.369 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 4.196 8.PADDI to R7C11B.CLK PHI2_c + -------- + 4.196 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 163.622ns (weighted slack = 327.244ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Bank_0io[0] (from PHI2_c +) - Destination: FF Data in CmdLEDEN (to PHI2_c -) + Destination: FF Data in CmdUFMData (to PHI2_c -) - Delay: 8.671ns (23.8% logic, 76.2% route), 4 logic levels. + Delay: 8.312ns (24.8% logic, 75.2% route), 4 logic levels. Constraint Details: - 8.671ns physical path delay Din[0]_MGIOL to SLICE_18 meets + 8.312ns physical path delay Din[0]_MGIOL to SLICE_19 meets 172.414ns delay constraint less 0.173ns skew and - 0.307ns CE_SET requirement (totaling 171.934ns) by 163.263ns + 0.307ns CE_SET requirement (totaling 171.934ns) by 163.622ns Physical Path Details: - Data path Din[0]_MGIOL to SLICE_18: + Data path Din[0]_MGIOL to SLICE_19: Name Fanout Delay (ns) Site Resource C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c) -ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0] -CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_89 -ROUTE 1 1.001 R4C11A.F0 to R4C10A.B1 un1_ADWR_i_o2_10 -CTOF_DEL --- 0.495 R4C10A.B1 to R4C10A.F1 SLICE_75 -ROUTE 8 1.444 R4C10A.F1 to R5C11C.A1 N_294 -CTOF_DEL --- 0.495 R5C11C.A1 to R5C11C.F1 SLICE_106 -ROUTE 5 1.413 R5C11C.F1 to R3C10B.CE XOR8MEG18 (to PHI2_c) +ROUTE 1 2.143 IOL_L3A.IN to R2C9D.A0 Bank[0] +CTOF_DEL --- 0.495 R2C9D.A0 to R2C9D.F0 SLICE_80 +ROUTE 6 1.104 R2C9D.F0 to R5C9A.D1 N_367 +CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_23 +ROUTE 8 1.295 R5C9A.F1 to R7C10B.C0 XOR8MEG18 +CTOF_DEL --- 0.495 R7C10B.C0 to R7C10B.F0 SLICE_77 +ROUTE 1 1.708 R7C10B.F0 to R7C11B.CE CmdUFMData_1_sqmuxa (to PHI2_c) -------- - 8.671 (23.8% logic, 76.2% route), 4 logic levels. + 8.312 (24.8% logic, 75.2% route), 4 logic levels. Clock Skew Details: @@ -318,176 +465,82 @@ ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c -------- 4.369 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_18: + Destination Clock Path PHI2 to SLICE_19: Name Fanout Delay (ns) Site Resource -ROUTE 21 4.196 8.PADDI to R3C10B.CLK PHI2_c +ROUTE 21 4.196 8.PADDI to R7C11B.CLK PHI2_c -------- 4.196 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 163.263ns (weighted slack = 326.526ns) +Passed: The following path meets requirements by 163.925ns (weighted slack = 327.850ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_0io[0] (from PHI2_c +) - Destination: FF Data in CmdUFMShift (to PHI2_c -) + Source: FF Q Bank_0io[1] (from PHI2_c +) + Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 8.671ns (23.8% logic, 76.2% route), 4 logic levels. + Delay: 8.150ns (37.4% logic, 62.6% route), 6 logic levels. Constraint Details: - 8.671ns physical path delay Din[0]_MGIOL to SLICE_20 meets + 8.150ns physical path delay Din[1]_MGIOL to SLICE_17 meets 172.414ns delay constraint less 0.173ns skew and - 0.307ns CE_SET requirement (totaling 171.934ns) by 163.263ns + 0.166ns DIN_SET requirement (totaling 172.075ns) by 163.925ns Physical Path Details: - Data path Din[0]_MGIOL to SLICE_20: + Data path Din[1]_MGIOL to SLICE_17: Name Fanout Delay (ns) Site Resource -C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c) -ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0] -CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_89 -ROUTE 1 1.001 R4C11A.F0 to R4C10A.B1 un1_ADWR_i_o2_10 -CTOF_DEL --- 0.495 R4C10A.B1 to R4C10A.F1 SLICE_75 -ROUTE 8 1.444 R4C10A.F1 to R5C11C.A1 N_294 -CTOF_DEL --- 0.495 R5C11C.A1 to R5C11C.F1 SLICE_106 -ROUTE 5 1.413 R5C11C.F1 to R4C10B.CE XOR8MEG18 (to PHI2_c) +C2INP_DEL --- 0.577 IOL_T10B.CLK to IOL_T10B.IN Din[1]_MGIOL (from PHI2_c) +ROUTE 1 1.375 IOL_T10B.IN to R4C10D.D0 Bank[1] +CTOF_DEL --- 0.495 R4C10D.D0 to R4C10D.F0 SLICE_90 +ROUTE 1 0.958 R4C10D.F0 to R2C9D.D0 un1_CmdEnable20_0_0_o2_10 +CTOF_DEL --- 0.495 R2C9D.D0 to R2C9D.F0 SLICE_80 +ROUTE 6 1.048 R2C9D.F0 to R4C9A.B1 N_367 +CTOF_DEL --- 0.495 R4C9A.B1 to R4C9A.F1 SLICE_11 +ROUTE 3 0.753 R4C9A.F1 to R4C8A.C0 CmdEnable16 +CTOF_DEL --- 0.495 R4C8A.C0 to R4C8A.F0 SLICE_33 +ROUTE 1 0.964 R4C8A.F0 to R4C9B.A0 CmdEnable_0_sqmuxa +CTOF_DEL --- 0.495 R4C9B.A0 to R4C9B.F0 SLICE_17 +ROUTE 1 0.000 R4C9B.F0 to R4C9B.DI0 CmdEnable_s (to PHI2_c) -------- - 8.671 (23.8% logic, 76.2% route), 4 logic levels. + 8.150 (37.4% logic, 62.6% route), 6 logic levels. Clock Skew Details: - Source Clock Path PHI2 to Din[0]_MGIOL: + Source Clock Path PHI2 to Din[1]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c +ROUTE 21 4.369 8.PADDI to IOL_T10B.CLK PHI2_c -------- 4.369 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_20: + Destination Clock Path PHI2 to SLICE_17: Name Fanout Delay (ns) Site Resource -ROUTE 21 4.196 8.PADDI to R4C10B.CLK PHI2_c +ROUTE 21 4.196 8.PADDI to R4C9B.CLK PHI2_c -------- 4.196 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 163.263ns (weighted slack = 326.526ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_0io[0] (from PHI2_c +) - Destination: FF Data in CmdUFMWrite (to PHI2_c -) - - Delay: 8.671ns (23.8% logic, 76.2% route), 4 logic levels. - - Constraint Details: - - 8.671ns physical path delay Din[0]_MGIOL to SLICE_21 meets - 172.414ns delay constraint less - 0.173ns skew and - 0.307ns CE_SET requirement (totaling 171.934ns) by 163.263ns - - Physical Path Details: - - Data path Din[0]_MGIOL to SLICE_21: - - Name Fanout Delay (ns) Site Resource -C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c) -ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0] -CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_89 -ROUTE 1 1.001 R4C11A.F0 to R4C10A.B1 un1_ADWR_i_o2_10 -CTOF_DEL --- 0.495 R4C10A.B1 to R4C10A.F1 SLICE_75 -ROUTE 8 1.444 R4C10A.F1 to R5C11C.A1 N_294 -CTOF_DEL --- 0.495 R5C11C.A1 to R5C11C.F1 SLICE_106 -ROUTE 5 1.413 R5C11C.F1 to R4C10D.CE XOR8MEG18 (to PHI2_c) - -------- - 8.671 (23.8% logic, 76.2% route), 4 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to Din[0]_MGIOL: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c - -------- - 4.369 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_21: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 4.196 8.PADDI to R4C10D.CLK PHI2_c - -------- - 4.196 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 163.263ns (weighted slack = 326.526ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_0io[0] (from PHI2_c +) - Destination: FF Data in Cmdn8MEGEN (to PHI2_c -) - - Delay: 8.671ns (23.8% logic, 76.2% route), 4 logic levels. - - Constraint Details: - - 8.671ns physical path delay Din[0]_MGIOL to SLICE_24 meets - 172.414ns delay constraint less - 0.173ns skew and - 0.307ns CE_SET requirement (totaling 171.934ns) by 163.263ns - - Physical Path Details: - - Data path Din[0]_MGIOL to SLICE_24: - - Name Fanout Delay (ns) Site Resource -C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c) -ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0] -CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_89 -ROUTE 1 1.001 R4C11A.F0 to R4C10A.B1 un1_ADWR_i_o2_10 -CTOF_DEL --- 0.495 R4C10A.B1 to R4C10A.F1 SLICE_75 -ROUTE 8 1.444 R4C10A.F1 to R5C11C.A1 N_294 -CTOF_DEL --- 0.495 R5C11C.A1 to R5C11C.F1 SLICE_106 -ROUTE 5 1.413 R5C11C.F1 to R3C10C.CE XOR8MEG18 (to PHI2_c) - -------- - 8.671 (23.8% logic, 76.2% route), 4 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to Din[0]_MGIOL: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c - -------- - 4.369 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_24: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 4.196 8.PADDI to R3C10C.CLK PHI2_c - -------- - 4.196 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 163.326ns (weighted slack = 326.652ns) +Passed: The following path meets requirements by 164.020ns (weighted slack = 328.040ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Bank_0io[6] (from PHI2_c +) Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 8.749ns (34.9% logic, 65.1% route), 6 logic levels. + Delay: 8.055ns (37.9% logic, 62.1% route), 6 logic levels. Constraint Details: - 8.749ns physical path delay Din[6]_MGIOL to SLICE_17 meets + 8.055ns physical path delay Din[6]_MGIOL to SLICE_17 meets 172.414ns delay constraint less 0.173ns skew and - 0.166ns DIN_SET requirement (totaling 172.075ns) by 163.326ns + 0.166ns DIN_SET requirement (totaling 172.075ns) by 164.020ns Physical Path Details: @@ -495,19 +548,19 @@ Passed: The following path meets requirements by 163.326ns (weighted slack = 326 Name Fanout Delay (ns) Site Resource C2INP_DEL --- 0.577 IOL_L2D.CLK to IOL_L2D.IN Din[6]_MGIOL (from PHI2_c) -ROUTE 1 1.802 IOL_L2D.IN to R3C9D.D0 Bank[6] -CTOF_DEL --- 0.495 R3C9D.D0 to R3C9D.F0 SLICE_32 -ROUTE 1 1.079 R3C9D.F0 to R4C10A.C1 un1_ADWR_i_o2_11 -CTOF_DEL --- 0.495 R4C10A.C1 to R4C10A.F1 SLICE_75 -ROUTE 8 0.710 R4C10A.F1 to R4C10A.B0 N_294 -CTOF_DEL --- 0.495 R4C10A.B0 to R4C10A.F0 SLICE_75 -ROUTE 2 1.093 R4C10A.F0 to R5C11A.C0 N_382 -CTOF_DEL --- 0.495 R5C11A.C0 to R5C11A.F0 SLICE_73 -ROUTE 2 1.013 R5C11A.F0 to R5C11D.B0 CmdEnable17 -CTOF_DEL --- 0.495 R5C11D.B0 to R5C11D.F0 SLICE_17 -ROUTE 1 0.000 R5C11D.F0 to R5C11D.DI0 CmdEnable_s (to PHI2_c) +ROUTE 1 1.802 IOL_L2D.IN to R2C9D.D1 Bank[6] +CTOF_DEL --- 0.495 R2C9D.D1 to R2C9D.F1 SLICE_80 +ROUTE 1 0.436 R2C9D.F1 to R2C9D.C0 un1_CmdEnable20_0_0_o2_11 +CTOF_DEL --- 0.495 R2C9D.C0 to R2C9D.F0 SLICE_80 +ROUTE 6 1.048 R2C9D.F0 to R4C9A.B1 N_367 +CTOF_DEL --- 0.495 R4C9A.B1 to R4C9A.F1 SLICE_11 +ROUTE 3 0.753 R4C9A.F1 to R4C8A.C0 CmdEnable16 +CTOF_DEL --- 0.495 R4C8A.C0 to R4C8A.F0 SLICE_33 +ROUTE 1 0.964 R4C8A.F0 to R4C9B.A0 CmdEnable_0_sqmuxa +CTOF_DEL --- 0.495 R4C9B.A0 to R4C9B.F0 SLICE_17 +ROUTE 1 0.000 R4C9B.F0 to R4C9B.DI0 CmdEnable_s (to PHI2_c) -------- - 8.749 (34.9% logic, 65.1% route), 6 logic levels. + 8.055 (37.9% logic, 62.1% route), 6 logic levels. Clock Skew Details: @@ -521,62 +574,11 @@ ROUTE 21 4.369 8.PADDI to IOL_L2D.CLK PHI2_c Destination Clock Path PHI2 to SLICE_17: Name Fanout Delay (ns) Site Resource -ROUTE 21 4.196 8.PADDI to R5C11D.CLK PHI2_c +ROUTE 21 4.196 8.PADDI to R4C9B.CLK PHI2_c -------- 4.196 (0.0% logic, 100.0% route), 0 logic levels. - -Passed: The following path meets requirements by 163.343ns (weighted slack = 326.686ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_0io[0] (from PHI2_c +) - Destination: FF Data in ADSubmitted (to PHI2_c -) - - Delay: 8.732ns (29.3% logic, 70.7% route), 5 logic levels. - - Constraint Details: - - 8.732ns physical path delay Din[0]_MGIOL to SLICE_10 meets - 172.414ns delay constraint less - 0.173ns skew and - 0.166ns DIN_SET requirement (totaling 172.075ns) by 163.343ns - - Physical Path Details: - - Data path Din[0]_MGIOL to SLICE_10: - - Name Fanout Delay (ns) Site Resource -C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c) -ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0] -CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_89 -ROUTE 1 1.001 R4C11A.F0 to R4C10A.B1 un1_ADWR_i_o2_10 -CTOF_DEL --- 0.495 R4C10A.B1 to R4C10A.F1 SLICE_75 -ROUTE 8 1.456 R4C10A.F1 to R5C12C.A1 N_294 -CTOF_DEL --- 0.495 R5C12C.A1 to R5C12C.F1 SLICE_10 -ROUTE 1 0.967 R5C12C.F1 to R5C12C.A0 N_22_i -CTOF_DEL --- 0.495 R5C12C.A0 to R5C12C.F0 SLICE_10 -ROUTE 1 0.000 R5C12C.F0 to R5C12C.DI0 ADSubmitted_r_0 (to PHI2_c) - -------- - 8.732 (29.3% logic, 70.7% route), 5 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to Din[0]_MGIOL: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c - -------- - 4.369 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_10: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 4.196 8.PADDI to R5C12C.CLK PHI2_c - -------- - 4.196 (0.0% logic, 100.0% route), 0 logic levels. - -Report: 50.206MHz is the maximum frequency for this preference. +Report: 48.464MHz is the maximum frequency for this preference. ================================================================================ @@ -617,90 +619,92 @@ Report: 150.150MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; - 868 items scored, 0 timing errors detected. + 891 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- -Passed: The following path meets requirements by 5.798ns +Passed: The following path meets requirements by 6.215ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS[12] (from RCLK_c +) - Destination: FF Data in wb_adr[1] (to RCLK_c +) + Source: FF Q RASr2 (from RCLK_c +) + Destination: FF Data in nRWE_0io (to RCLK_c +) - Delay: 10.036ns (24.2% logic, 75.8% route), 5 logic levels. + Delay: 9.805ns (29.9% logic, 70.1% route), 6 logic levels. Constraint Details: - 10.036ns physical path delay SLICE_4 to SLICE_48 meets + 9.805ns physical path delay SLICE_32 to nRWE_MGIOL meets 16.000ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 15.834ns) by 5.798ns + -0.173ns skew and + 0.153ns DO_SET requirement (totaling 16.020ns) by 6.215ns Physical Path Details: - Data path SLICE_4 to SLICE_48: + Data path SLICE_32 to nRWE_MGIOL: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C5C.CLK to R5C5C.Q1 SLICE_4 (from RCLK_c) -ROUTE 23 2.663 R5C5C.Q1 to R2C7A.A1 FS[12] -CTOF_DEL --- 0.495 R2C7A.A1 to R2C7A.F1 SLICE_101 -ROUTE 4 2.173 R2C7A.F1 to R4C7C.B1 N_142 -CTOF_DEL --- 0.495 R4C7C.B1 to R4C7C.F1 SLICE_65 -ROUTE 1 0.967 R4C7C.F1 to R4C7A.A0 N_428_tz -CTOF_DEL --- 0.495 R4C7A.A0 to R4C7A.F0 SLICE_61 -ROUTE 1 1.801 R4C7A.F0 to R4C6C.A1 wb_adr_5_i_i_0[1] -CTOF_DEL --- 0.495 R4C6C.A1 to R4C6C.F1 SLICE_48 -ROUTE 1 0.000 R4C6C.F1 to R4C6C.DI1 N_282 (to RCLK_c) +REG_DEL --- 0.452 R4C12C.CLK to R4C12C.Q1 SLICE_32 (from RCLK_c) +ROUTE 10 1.963 R4C12C.Q1 to R8C11B.A1 RASr2 +CTOF_DEL --- 0.495 R8C11B.A1 to R8C11B.F1 SLICE_62 +ROUTE 6 1.078 R8C11B.F1 to R7C12C.D1 IS_0_sqmuxa_0_o2 +CTOF_DEL --- 0.495 R7C12C.D1 to R7C12C.F1 SLICE_79 +ROUTE 2 0.635 R7C12C.F1 to R7C12A.D1 IS_0_sqmuxa_0_o3 +CTOF_DEL --- 0.495 R7C12A.D1 to R7C12A.F1 SLICE_28 +ROUTE 1 0.744 R7C12A.F1 to R8C12B.C1 nRWE_s_i_a2_1_0 +CTOF_DEL --- 0.495 R8C12B.C1 to R8C12B.F1 SLICE_68 +ROUTE 1 0.744 R8C12B.F1 to R9C12D.C0 nRWE_s_i_tz_0 +CTOF_DEL --- 0.495 R9C12D.C0 to R9C12D.F0 SLICE_75 +ROUTE 1 1.714 R9C12D.F0 to IOL_B20D.OPOS N_252_i (to RCLK_c) -------- - 10.036 (24.2% logic, 75.8% route), 5 logic levels. + 9.805 (29.9% logic, 70.1% route), 6 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_4: + Source Clock Path RCLK to SLICE_32: Name Fanout Delay (ns) Site Resource -ROUTE 48 2.264 63.PADDI to R5C5C.CLK RCLK_c +ROUTE 48 2.264 63.PADDI to R4C12C.CLK RCLK_c -------- 2.264 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_48: + Destination Clock Path RCLK to nRWE_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 48 2.264 63.PADDI to R4C6C.CLK RCLK_c +ROUTE 48 2.437 63.PADDI to IOL_B20D.CLK RCLK_c -------- - 2.264 (0.0% logic, 100.0% route), 0 logic levels. + 2.437 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 6.138ns +Passed: The following path meets requirements by 6.236ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: EFB Port ufmefb/EFBInst_0(ASIC) (from RCLK_c +) Destination: FF Data in n8MEGEN (to RCLK_c +) - Delay: 9.523ns (76.3% logic, 23.7% route), 3 logic levels. + Delay: 9.425ns (77.1% logic, 22.9% route), 3 logic levels. Constraint Details: - 9.523ns physical path delay ufmefb/EFBInst_0 to SLICE_46 meets + 9.425ns physical path delay ufmefb/EFBInst_0 to SLICE_45 meets 16.000ns delay constraint less 0.173ns skew and - 0.166ns DIN_SET requirement (totaling 15.661ns) by 6.138ns + 0.166ns DIN_SET requirement (totaling 15.661ns) by 6.236ns Physical Path Details: - Data path ufmefb/EFBInst_0 to SLICE_46: + Data path ufmefb/EFBInst_0 to SLICE_45: Name Fanout Delay (ns) Site Resource WCLKI2WBDA --- 6.278 EFB.WBCLKI to EFB.WBDATO0 ufmefb/EFBInst_0 (from RCLK_c) -ROUTE 1 1.297 EFB.WBDATO0 to R3C5B.C1 wb_dato[0] -CTOF_DEL --- 0.495 R3C5B.C1 to R3C5B.F1 SLICE_108 -ROUTE 1 0.958 R3C5B.F1 to R3C8B.D0 n8MEGENe_1_0 -CTOF_DEL --- 0.495 R3C8B.D0 to R3C8B.F0 SLICE_46 -ROUTE 1 0.000 R3C8B.F0 to R3C8B.DI0 n8MEGENe_0 (to RCLK_c) +ROUTE 1 1.512 EFB.WBDATO0 to R4C5C.C1 wb_dato[0] +CTOF_DEL --- 0.495 R4C5C.C1 to R4C5C.F1 SLICE_111 +ROUTE 1 0.645 R4C5C.F1 to R5C5B.D0 n8MEGENe_1_0 +CTOF_DEL --- 0.495 R5C5B.D0 to R5C5B.F0 SLICE_45 +ROUTE 1 0.000 R5C5B.F0 to R5C5B.DI0 n8MEGENe_0 (to RCLK_c) -------- - 9.523 (76.3% logic, 23.7% route), 3 logic levels. + 9.425 (77.1% logic, 22.9% route), 3 logic levels. Clock Skew Details: @@ -711,420 +715,100 @@ ROUTE 48 2.437 63.PADDI to EFB.WBCLKI RCLK_c -------- 2.437 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_46: - - Name Fanout Delay (ns) Site Resource -ROUTE 48 2.264 63.PADDI to R3C8B.CLK RCLK_c - -------- - 2.264 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 6.414ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[12] (from RCLK_c +) - Destination: FF Data in wb_adr[0] (to RCLK_c +) - - Delay: 9.420ns (36.3% logic, 63.7% route), 7 logic levels. - - Constraint Details: - - 9.420ns physical path delay SLICE_4 to SLICE_48 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 15.834ns) by 6.414ns - - Physical Path Details: - - Data path SLICE_4 to SLICE_48: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C5C.CLK to R5C5C.Q1 SLICE_4 (from RCLK_c) -ROUTE 23 2.237 R5C5C.Q1 to R2C7D.A1 FS[12] -CTOF_DEL --- 0.495 R2C7D.A1 to R2C7D.F1 SLICE_66 -ROUTE 1 0.436 R2C7D.F1 to R2C7D.C0 wb_adr_5_i_i_a2_3_0[0] -CTOF_DEL --- 0.495 R2C7D.C0 to R2C7D.F0 SLICE_66 -ROUTE 1 0.967 R2C7D.F0 to R2C7B.A0 wb_adr_5_i_i_1_0_tz_0[0] -CTOF_DEL --- 0.495 R2C7B.A0 to R2C7B.F0 SLICE_86 -ROUTE 1 1.001 R2C7B.F0 to R2C6A.B0 wb_adr_5_i_i_1_0[0] -CTOF_DEL --- 0.495 R2C6A.B0 to R2C6A.F0 SLICE_85 -ROUTE 1 1.042 R2C6A.F0 to R4C6D.D0 wb_adr_5_i_i_1[0] -CTOF_DEL --- 0.495 R4C6D.D0 to R4C6D.F0 SLICE_77 -ROUTE 1 0.315 R4C6D.F0 to R4C6C.D0 wb_adr_5_i_i_5[0] -CTOF_DEL --- 0.495 R4C6C.D0 to R4C6C.F0 SLICE_48 -ROUTE 1 0.000 R4C6C.F0 to R4C6C.DI0 N_283 (to RCLK_c) - -------- - 9.420 (36.3% logic, 63.7% route), 7 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_4: - - Name Fanout Delay (ns) Site Resource -ROUTE 48 2.264 63.PADDI to R5C5C.CLK RCLK_c - -------- - 2.264 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_48: - - Name Fanout Delay (ns) Site Resource -ROUTE 48 2.264 63.PADDI to R4C6C.CLK RCLK_c - -------- - 2.264 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 6.769ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[9] (from RCLK_c +) - Destination: FF Data in wb_adr[1] (to RCLK_c +) - - Delay: 9.065ns (32.3% logic, 67.7% route), 6 logic levels. - - Constraint Details: - - 9.065ns physical path delay SLICE_5 to SLICE_48 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 15.834ns) by 6.769ns - - Physical Path Details: - - Data path SLICE_5 to SLICE_48: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C5B.CLK to R5C5B.Q0 SLICE_5 (from RCLK_c) -ROUTE 14 1.803 R5C5B.Q0 to R3C6D.B1 FS[9] -CTOF_DEL --- 0.495 R3C6D.B1 to R3C6D.F1 SLICE_80 -ROUTE 7 1.131 R3C6D.F1 to R4C7C.C0 N_125 -CTOF_DEL --- 0.495 R4C7C.C0 to R4C7C.F0 SLICE_65 -ROUTE 1 0.436 R4C7C.F0 to R4C7C.C1 wb_adr_5_i_i_a2_0[1] -CTOF_DEL --- 0.495 R4C7C.C1 to R4C7C.F1 SLICE_65 -ROUTE 1 0.967 R4C7C.F1 to R4C7A.A0 N_428_tz -CTOF_DEL --- 0.495 R4C7A.A0 to R4C7A.F0 SLICE_61 -ROUTE 1 1.801 R4C7A.F0 to R4C6C.A1 wb_adr_5_i_i_0[1] -CTOF_DEL --- 0.495 R4C6C.A1 to R4C6C.F1 SLICE_48 -ROUTE 1 0.000 R4C6C.F1 to R4C6C.DI1 N_282 (to RCLK_c) - -------- - 9.065 (32.3% logic, 67.7% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_5: + Destination Clock Path RCLK to SLICE_45: Name Fanout Delay (ns) Site Resource ROUTE 48 2.264 63.PADDI to R5C5B.CLK RCLK_c -------- 2.264 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_48: - Name Fanout Delay (ns) Site Resource -ROUTE 48 2.264 63.PADDI to R4C6C.CLK RCLK_c - -------- - 2.264 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 7.019ns +Passed: The following path meets requirements by 6.365ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS[13] (from RCLK_c +) - Destination: FF Data in wb_dati[7] (to RCLK_c +) + Source: EFB Port ufmefb/EFBInst_0(ASIC) (from RCLK_c +) + Destination: FF Data in LEDEN (to RCLK_c +) - Delay: 8.815ns (33.2% logic, 66.8% route), 6 logic levels. + Delay: 9.296ns (69.4% logic, 30.6% route), 3 logic levels. Constraint Details: - 8.815ns physical path delay SLICE_3 to SLICE_56 meets + 9.296ns physical path delay ufmefb/EFBInst_0 to SLICE_30 meets 16.000ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.019ns + 0.173ns skew and + 0.166ns DIN_SET requirement (totaling 15.661ns) by 6.365ns Physical Path Details: - Data path SLICE_3 to SLICE_56: + Data path ufmefb/EFBInst_0 to SLICE_30: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C5D.CLK to R5C5D.Q0 SLICE_3 (from RCLK_c) -ROUTE 23 1.929 R5C5D.Q0 to R3C5D.A1 FS[13] -CTOF_DEL --- 0.495 R3C5D.A1 to R3C5D.F1 SLICE_70 -ROUTE 3 1.021 R3C5D.F1 to R3C5D.B0 N_348_2 -CTOF_DEL --- 0.495 R3C5D.B0 to R3C5D.F0 SLICE_70 -ROUTE 1 0.967 R3C5D.F0 to R3C5B.A0 wb_dati_5_1_iv_0_a2_3_0[7] -CTOF_DEL --- 0.495 R3C5B.A0 to R3C5B.F0 SLICE_108 -ROUTE 1 0.967 R3C5B.F0 to R3C5A.A1 wb_dati_5_1_iv_0_0[7] -CTOF_DEL --- 0.495 R3C5A.A1 to R3C5A.F1 SLICE_69 -ROUTE 1 1.004 R3C5A.F1 to R3C5C.B1 wb_dati_5_1_iv_0_1[7] -CTOF_DEL --- 0.495 R3C5C.B1 to R3C5C.F1 SLICE_56 -ROUTE 1 0.000 R3C5C.F1 to R3C5C.DI1 wb_dati_5[7] (to RCLK_c) +WCLKI2WBDA --- 5.461 EFB.WBCLKI to EFB.WBDATO1 ufmefb/EFBInst_0 (from RCLK_c) +ROUTE 1 2.152 EFB.WBDATO1 to R7C5A.A1 wb_dato[1] +CTOF_DEL --- 0.495 R7C5A.A1 to R7C5A.F1 SLICE_30 +ROUTE 1 0.693 R7C5A.F1 to R7C5A.B0 LEDEN_6 +CTOF_DEL --- 0.495 R7C5A.B0 to R7C5A.F0 SLICE_30 +ROUTE 1 0.000 R7C5A.F0 to R7C5A.DI0 LEDENe_0 (to RCLK_c) -------- - 8.815 (33.2% logic, 66.8% route), 6 logic levels. + 9.296 (69.4% logic, 30.6% route), 3 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_3: + Source Clock Path RCLK to ufmefb/EFBInst_0: Name Fanout Delay (ns) Site Resource -ROUTE 48 2.264 63.PADDI to R5C5D.CLK RCLK_c +ROUTE 48 2.437 63.PADDI to EFB.WBCLKI RCLK_c -------- - 2.264 (0.0% logic, 100.0% route), 0 logic levels. + 2.437 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_56: + Destination Clock Path RCLK to SLICE_30: Name Fanout Delay (ns) Site Resource -ROUTE 48 2.264 63.PADDI to R3C5C.CLK RCLK_c +ROUTE 48 2.264 63.PADDI to R7C5A.CLK RCLK_c -------- 2.264 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 7.040ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[13] (from RCLK_c +) - Destination: FF Data in wb_adr[1] (to RCLK_c +) - - Delay: 8.794ns (27.7% logic, 72.3% route), 5 logic levels. - - Constraint Details: - - 8.794ns physical path delay SLICE_3 to SLICE_48 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.040ns - - Physical Path Details: - - Data path SLICE_3 to SLICE_48: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C5D.CLK to R5C5D.Q0 SLICE_3 (from RCLK_c) -ROUTE 23 3.158 R5C5D.Q0 to R4C7C.A0 FS[13] -CTOF_DEL --- 0.495 R4C7C.A0 to R4C7C.F0 SLICE_65 -ROUTE 1 0.436 R4C7C.F0 to R4C7C.C1 wb_adr_5_i_i_a2_0[1] -CTOF_DEL --- 0.495 R4C7C.C1 to R4C7C.F1 SLICE_65 -ROUTE 1 0.967 R4C7C.F1 to R4C7A.A0 N_428_tz -CTOF_DEL --- 0.495 R4C7A.A0 to R4C7A.F0 SLICE_61 -ROUTE 1 1.801 R4C7A.F0 to R4C6C.A1 wb_adr_5_i_i_0[1] -CTOF_DEL --- 0.495 R4C6C.A1 to R4C6C.F1 SLICE_48 -ROUTE 1 0.000 R4C6C.F1 to R4C6C.DI1 N_282 (to RCLK_c) - -------- - 8.794 (27.7% logic, 72.3% route), 5 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_3: - - Name Fanout Delay (ns) Site Resource -ROUTE 48 2.264 63.PADDI to R5C5D.CLK RCLK_c - -------- - 2.264 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_48: - - Name Fanout Delay (ns) Site Resource -ROUTE 48 2.264 63.PADDI to R4C6C.CLK RCLK_c - -------- - 2.264 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 7.108ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[12] (from RCLK_c +) - Destination: FF Data in wb_dati[7] (to RCLK_c +) - - Delay: 8.726ns (33.5% logic, 66.5% route), 6 logic levels. - - Constraint Details: - - 8.726ns physical path delay SLICE_4 to SLICE_56 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.108ns - - Physical Path Details: - - Data path SLICE_4 to SLICE_56: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C5C.CLK to R5C5C.Q1 SLICE_4 (from RCLK_c) -ROUTE 23 1.840 R5C5C.Q1 to R3C5D.B1 FS[12] -CTOF_DEL --- 0.495 R3C5D.B1 to R3C5D.F1 SLICE_70 -ROUTE 3 1.021 R3C5D.F1 to R3C5D.B0 N_348_2 -CTOF_DEL --- 0.495 R3C5D.B0 to R3C5D.F0 SLICE_70 -ROUTE 1 0.967 R3C5D.F0 to R3C5B.A0 wb_dati_5_1_iv_0_a2_3_0[7] -CTOF_DEL --- 0.495 R3C5B.A0 to R3C5B.F0 SLICE_108 -ROUTE 1 0.967 R3C5B.F0 to R3C5A.A1 wb_dati_5_1_iv_0_0[7] -CTOF_DEL --- 0.495 R3C5A.A1 to R3C5A.F1 SLICE_69 -ROUTE 1 1.004 R3C5A.F1 to R3C5C.B1 wb_dati_5_1_iv_0_1[7] -CTOF_DEL --- 0.495 R3C5C.B1 to R3C5C.F1 SLICE_56 -ROUTE 1 0.000 R3C5C.F1 to R3C5C.DI1 wb_dati_5[7] (to RCLK_c) - -------- - 8.726 (33.5% logic, 66.5% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_4: - - Name Fanout Delay (ns) Site Resource -ROUTE 48 2.264 63.PADDI to R5C5C.CLK RCLK_c - -------- - 2.264 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_56: - - Name Fanout Delay (ns) Site Resource -ROUTE 48 2.264 63.PADDI to R3C5C.CLK RCLK_c - -------- - 2.264 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 7.132ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[10] (from RCLK_c +) - Destination: FF Data in wb_adr[1] (to RCLK_c +) - - Delay: 8.702ns (33.6% logic, 66.4% route), 6 logic levels. - - Constraint Details: - - 8.702ns physical path delay SLICE_5 to SLICE_48 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.132ns - - Physical Path Details: - - Data path SLICE_5 to SLICE_48: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C5B.CLK to R5C5B.Q1 SLICE_5 (from RCLK_c) -ROUTE 16 1.440 R5C5B.Q1 to R3C6D.A1 FS[10] -CTOF_DEL --- 0.495 R3C6D.A1 to R3C6D.F1 SLICE_80 -ROUTE 7 1.131 R3C6D.F1 to R4C7C.C0 N_125 -CTOF_DEL --- 0.495 R4C7C.C0 to R4C7C.F0 SLICE_65 -ROUTE 1 0.436 R4C7C.F0 to R4C7C.C1 wb_adr_5_i_i_a2_0[1] -CTOF_DEL --- 0.495 R4C7C.C1 to R4C7C.F1 SLICE_65 -ROUTE 1 0.967 R4C7C.F1 to R4C7A.A0 N_428_tz -CTOF_DEL --- 0.495 R4C7A.A0 to R4C7A.F0 SLICE_61 -ROUTE 1 1.801 R4C7A.F0 to R4C6C.A1 wb_adr_5_i_i_0[1] -CTOF_DEL --- 0.495 R4C6C.A1 to R4C6C.F1 SLICE_48 -ROUTE 1 0.000 R4C6C.F1 to R4C6C.DI1 N_282 (to RCLK_c) - -------- - 8.702 (33.6% logic, 66.4% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_5: - - Name Fanout Delay (ns) Site Resource -ROUTE 48 2.264 63.PADDI to R5C5B.CLK RCLK_c - -------- - 2.264 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_48: - - Name Fanout Delay (ns) Site Resource -ROUTE 48 2.264 63.PADDI to R4C6C.CLK RCLK_c - -------- - 2.264 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 7.246ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[11] (from RCLK_c +) - Destination: FF Data in wb_adr[1] (to RCLK_c +) - - Delay: 8.588ns (28.3% logic, 71.7% route), 5 logic levels. - - Constraint Details: - - 8.588ns physical path delay SLICE_4 to SLICE_48 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.246ns - - Physical Path Details: - - Data path SLICE_4 to SLICE_48: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C5C.CLK to R5C5C.Q0 SLICE_4 (from RCLK_c) -ROUTE 21 1.215 R5C5C.Q0 to R2C7A.D1 FS[11] -CTOF_DEL --- 0.495 R2C7A.D1 to R2C7A.F1 SLICE_101 -ROUTE 4 2.173 R2C7A.F1 to R4C7C.B1 N_142 -CTOF_DEL --- 0.495 R4C7C.B1 to R4C7C.F1 SLICE_65 -ROUTE 1 0.967 R4C7C.F1 to R4C7A.A0 N_428_tz -CTOF_DEL --- 0.495 R4C7A.A0 to R4C7A.F0 SLICE_61 -ROUTE 1 1.801 R4C7A.F0 to R4C6C.A1 wb_adr_5_i_i_0[1] -CTOF_DEL --- 0.495 R4C6C.A1 to R4C6C.F1 SLICE_48 -ROUTE 1 0.000 R4C6C.F1 to R4C6C.DI1 N_282 (to RCLK_c) - -------- - 8.588 (28.3% logic, 71.7% route), 5 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_4: - - Name Fanout Delay (ns) Site Resource -ROUTE 48 2.264 63.PADDI to R5C5C.CLK RCLK_c - -------- - 2.264 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_48: - - Name Fanout Delay (ns) Site Resource -ROUTE 48 2.264 63.PADDI to R4C6C.CLK RCLK_c - -------- - 2.264 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 7.249ns +Passed: The following path meets requirements by 6.454ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q InitReady (from RCLK_c +) Destination: FF Data in nRWE_0io (to RCLK_c +) - Delay: 8.771ns (27.7% logic, 72.3% route), 5 logic levels. + Delay: 9.566ns (30.6% logic, 69.4% route), 6 logic levels. Constraint Details: - 8.771ns physical path delay SLICE_30 to nRWE_MGIOL meets + 9.566ns physical path delay SLICE_29 to nRWE_MGIOL meets 16.000ns delay constraint less -0.173ns skew and - 0.153ns DO_SET requirement (totaling 16.020ns) by 7.249ns + 0.153ns DO_SET requirement (totaling 16.020ns) by 6.454ns Physical Path Details: - Data path SLICE_30 to nRWE_MGIOL: + Data path SLICE_29 to nRWE_MGIOL: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R4C8D.CLK to R4C8D.Q0 SLICE_30 (from RCLK_c) -ROUTE 31 1.714 R4C8D.Q0 to R7C15A.D1 InitReady -CTOF_DEL --- 0.495 R7C15A.D1 to R7C15A.F1 SLICE_62 -ROUTE 6 1.032 R7C15A.F1 to R7C16A.B1 N_43 -CTOF_DEL --- 0.495 R7C16A.B1 to R7C16A.F1 SLICE_78 -ROUTE 2 0.775 R7C16A.F1 to R7C14B.C1 IS_0_sqmuxa_0_o2 -CTOF_DEL --- 0.495 R7C14B.C1 to R7C14B.F1 SLICE_68 -ROUTE 1 1.023 R7C14B.F1 to R8C14C.B1 nRWE_0io_RNO_0 -CTOF_DEL --- 0.495 R8C14C.B1 to R8C14C.F1 SLICE_92 -ROUTE 1 1.795 R8C14C.F1 to IOL_B20D.OPOS N_37_i (to RCLK_c) +REG_DEL --- 0.452 R4C8D.CLK to R4C8D.Q0 SLICE_29 (from RCLK_c) +ROUTE 40 1.724 R4C8D.Q0 to R8C11B.D1 InitReady +CTOF_DEL --- 0.495 R8C11B.D1 to R8C11B.F1 SLICE_62 +ROUTE 6 1.078 R8C11B.F1 to R7C12C.D1 IS_0_sqmuxa_0_o2 +CTOF_DEL --- 0.495 R7C12C.D1 to R7C12C.F1 SLICE_79 +ROUTE 2 0.635 R7C12C.F1 to R7C12A.D1 IS_0_sqmuxa_0_o3 +CTOF_DEL --- 0.495 R7C12A.D1 to R7C12A.F1 SLICE_28 +ROUTE 1 0.744 R7C12A.F1 to R8C12B.C1 nRWE_s_i_a2_1_0 +CTOF_DEL --- 0.495 R8C12B.C1 to R8C12B.F1 SLICE_68 +ROUTE 1 0.744 R8C12B.F1 to R9C12D.C0 nRWE_s_i_tz_0 +CTOF_DEL --- 0.495 R9C12D.C0 to R9C12D.F0 SLICE_75 +ROUTE 1 1.714 R9C12D.F0 to IOL_B20D.OPOS N_252_i (to RCLK_c) -------- - 8.771 (27.7% logic, 72.3% route), 5 logic levels. + 9.566 (30.6% logic, 69.4% route), 6 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_30: + Source Clock Path RCLK to SLICE_29: Name Fanout Delay (ns) Site Resource ROUTE 48 2.264 63.PADDI to R4C8D.CLK RCLK_c @@ -1138,7 +822,321 @@ ROUTE 48 2.437 63.PADDI to IOL_B20D.CLK RCLK_c -------- 2.437 (0.0% logic, 100.0% route), 0 logic levels. -Report: 98.020MHz is the maximum frequency for this preference. + +Passed: The following path meets requirements by 6.646ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS[1] (from RCLK_c +) + Destination: FF Data in nRCAS_0io (to RCLK_c +) + + Delay: 9.373ns (31.2% logic, 68.8% route), 6 logic levels. + + Constraint Details: + + 9.373ns physical path delay SLICE_27 to nRCAS_MGIOL meets + 16.000ns delay constraint less + -0.172ns skew and + 0.153ns DO_SET requirement (totaling 16.019ns) by 6.646ns + + Physical Path Details: + + Data path SLICE_27 to nRCAS_MGIOL: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R7C11C.CLK to R7C11C.Q0 SLICE_27 (from RCLK_c) +ROUTE 7 1.445 R7C11C.Q0 to R8C12A.A1 IS[1] +CTOF_DEL --- 0.495 R8C12A.A1 to R8C12A.F1 SLICE_83 +ROUTE 3 0.973 R8C12A.F1 to R8C11B.A0 un1_nRCAS_6_sqmuxa_i_o2 +CTOF_DEL --- 0.495 R8C11B.A0 to R8C11B.F0 SLICE_62 +ROUTE 2 0.632 R8C11B.F0 to R9C11A.D0 N_48 +CTOF_DEL --- 0.495 R9C11A.D0 to R9C11A.F0 SLICE_69 +ROUTE 1 0.626 R9C11A.F0 to R9C11A.D1 nRCS_9_u_i_o3_0_0 +CTOF_DEL --- 0.495 R9C11A.D1 to R9C11A.F1 SLICE_69 +ROUTE 1 0.744 R9C11A.F1 to R9C12C.C1 nRCS_9_u_i_o3_0_2 +CTOF_DEL --- 0.495 R9C12C.C1 to R9C12C.F1 SLICE_101 +ROUTE 1 2.026 R9C12C.F1 to IOL_R10C.OPOS N_251_i (to RCLK_c) + -------- + 9.373 (31.2% logic, 68.8% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_27: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.264 63.PADDI to R7C11C.CLK RCLK_c + -------- + 2.264 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to nRCAS_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.436 63.PADDI to IOL_R10C.CLK RCLK_c + -------- + 2.436 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 6.656ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RASr2 (from RCLK_c +) + Destination: FF Data in nRCAS_0io (to RCLK_c +) + + Delay: 9.363ns (31.3% logic, 68.7% route), 6 logic levels. + + Constraint Details: + + 9.363ns physical path delay SLICE_32 to nRCAS_MGIOL meets + 16.000ns delay constraint less + -0.172ns skew and + 0.153ns DO_SET requirement (totaling 16.019ns) by 6.656ns + + Physical Path Details: + + Data path SLICE_32 to nRCAS_MGIOL: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R4C12C.CLK to R4C12C.Q1 SLICE_32 (from RCLK_c) +ROUTE 10 1.963 R4C12C.Q1 to R8C11B.A1 RASr2 +CTOF_DEL --- 0.495 R8C11B.A1 to R8C11B.F1 SLICE_62 +ROUTE 6 0.445 R8C11B.F1 to R8C11B.C0 IS_0_sqmuxa_0_o2 +CTOF_DEL --- 0.495 R8C11B.C0 to R8C11B.F0 SLICE_62 +ROUTE 2 0.632 R8C11B.F0 to R9C11A.D0 N_48 +CTOF_DEL --- 0.495 R9C11A.D0 to R9C11A.F0 SLICE_69 +ROUTE 1 0.626 R9C11A.F0 to R9C11A.D1 nRCS_9_u_i_o3_0_0 +CTOF_DEL --- 0.495 R9C11A.D1 to R9C11A.F1 SLICE_69 +ROUTE 1 0.744 R9C11A.F1 to R9C12C.C1 nRCS_9_u_i_o3_0_2 +CTOF_DEL --- 0.495 R9C12C.C1 to R9C12C.F1 SLICE_101 +ROUTE 1 2.026 R9C12C.F1 to IOL_R10C.OPOS N_251_i (to RCLK_c) + -------- + 9.363 (31.3% logic, 68.7% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_32: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.264 63.PADDI to R4C12C.CLK RCLK_c + -------- + 2.264 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to nRCAS_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.436 63.PADDI to IOL_R10C.CLK RCLK_c + -------- + 2.436 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 6.868ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS[1] (from RCLK_c +) + Destination: FF Data in nRCAS_0io (to RCLK_c +) + + Delay: 9.151ns (26.6% logic, 73.4% route), 5 logic levels. + + Constraint Details: + + 9.151ns physical path delay SLICE_27 to nRCAS_MGIOL meets + 16.000ns delay constraint less + -0.172ns skew and + 0.153ns DO_SET requirement (totaling 16.019ns) by 6.868ns + + Physical Path Details: + + Data path SLICE_27 to nRCAS_MGIOL: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R7C11C.CLK to R7C11C.Q0 SLICE_27 (from RCLK_c) +ROUTE 7 1.445 R7C11C.Q0 to R8C12A.A1 IS[1] +CTOF_DEL --- 0.495 R8C12A.A1 to R8C12A.F1 SLICE_83 +ROUTE 3 0.973 R8C12A.F1 to R8C11B.A0 un1_nRCAS_6_sqmuxa_i_o2 +CTOF_DEL --- 0.495 R8C11B.A0 to R8C11B.F0 SLICE_62 +ROUTE 2 1.308 R8C11B.F0 to R9C12C.A0 N_48 +CTOF_DEL --- 0.495 R9C12C.A0 to R9C12C.F0 SLICE_101 +ROUTE 1 0.967 R9C12C.F0 to R9C12C.A1 N_251_i_sx +CTOF_DEL --- 0.495 R9C12C.A1 to R9C12C.F1 SLICE_101 +ROUTE 1 2.026 R9C12C.F1 to IOL_R10C.OPOS N_251_i (to RCLK_c) + -------- + 9.151 (26.6% logic, 73.4% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_27: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.264 63.PADDI to R7C11C.CLK RCLK_c + -------- + 2.264 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to nRCAS_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.436 63.PADDI to IOL_R10C.CLK RCLK_c + -------- + 2.436 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 6.878ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RASr2 (from RCLK_c +) + Destination: FF Data in nRCAS_0io (to RCLK_c +) + + Delay: 9.141ns (26.6% logic, 73.4% route), 5 logic levels. + + Constraint Details: + + 9.141ns physical path delay SLICE_32 to nRCAS_MGIOL meets + 16.000ns delay constraint less + -0.172ns skew and + 0.153ns DO_SET requirement (totaling 16.019ns) by 6.878ns + + Physical Path Details: + + Data path SLICE_32 to nRCAS_MGIOL: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R4C12C.CLK to R4C12C.Q1 SLICE_32 (from RCLK_c) +ROUTE 10 1.963 R4C12C.Q1 to R8C11B.A1 RASr2 +CTOF_DEL --- 0.495 R8C11B.A1 to R8C11B.F1 SLICE_62 +ROUTE 6 0.445 R8C11B.F1 to R8C11B.C0 IS_0_sqmuxa_0_o2 +CTOF_DEL --- 0.495 R8C11B.C0 to R8C11B.F0 SLICE_62 +ROUTE 2 1.308 R8C11B.F0 to R9C12C.A0 N_48 +CTOF_DEL --- 0.495 R9C12C.A0 to R9C12C.F0 SLICE_101 +ROUTE 1 0.967 R9C12C.F0 to R9C12C.A1 N_251_i_sx +CTOF_DEL --- 0.495 R9C12C.A1 to R9C12C.F1 SLICE_101 +ROUTE 1 2.026 R9C12C.F1 to IOL_R10C.OPOS N_251_i (to RCLK_c) + -------- + 9.141 (26.6% logic, 73.4% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_32: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.264 63.PADDI to R4C12C.CLK RCLK_c + -------- + 2.264 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to nRCAS_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.436 63.PADDI to IOL_R10C.CLK RCLK_c + -------- + 2.436 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 6.895ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q InitReady (from RCLK_c +) + Destination: FF Data in nRCAS_0io (to RCLK_c +) + + Delay: 9.124ns (32.1% logic, 67.9% route), 6 logic levels. + + Constraint Details: + + 9.124ns physical path delay SLICE_29 to nRCAS_MGIOL meets + 16.000ns delay constraint less + -0.172ns skew and + 0.153ns DO_SET requirement (totaling 16.019ns) by 6.895ns + + Physical Path Details: + + Data path SLICE_29 to nRCAS_MGIOL: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R4C8D.CLK to R4C8D.Q0 SLICE_29 (from RCLK_c) +ROUTE 40 1.724 R4C8D.Q0 to R8C11B.D1 InitReady +CTOF_DEL --- 0.495 R8C11B.D1 to R8C11B.F1 SLICE_62 +ROUTE 6 0.445 R8C11B.F1 to R8C11B.C0 IS_0_sqmuxa_0_o2 +CTOF_DEL --- 0.495 R8C11B.C0 to R8C11B.F0 SLICE_62 +ROUTE 2 0.632 R8C11B.F0 to R9C11A.D0 N_48 +CTOF_DEL --- 0.495 R9C11A.D0 to R9C11A.F0 SLICE_69 +ROUTE 1 0.626 R9C11A.F0 to R9C11A.D1 nRCS_9_u_i_o3_0_0 +CTOF_DEL --- 0.495 R9C11A.D1 to R9C11A.F1 SLICE_69 +ROUTE 1 0.744 R9C11A.F1 to R9C12C.C1 nRCS_9_u_i_o3_0_2 +CTOF_DEL --- 0.495 R9C12C.C1 to R9C12C.F1 SLICE_101 +ROUTE 1 2.026 R9C12C.F1 to IOL_R10C.OPOS N_251_i (to RCLK_c) + -------- + 9.124 (32.1% logic, 67.9% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_29: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.264 63.PADDI to R4C8D.CLK RCLK_c + -------- + 2.264 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to nRCAS_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.436 63.PADDI to IOL_R10C.CLK RCLK_c + -------- + 2.436 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 6.966ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS[2] (from RCLK_c +) + Destination: FF Data in nRCAS_0io (to RCLK_c +) + + Delay: 9.053ns (32.3% logic, 67.7% route), 6 logic levels. + + Constraint Details: + + 9.053ns physical path delay SLICE_27 to nRCAS_MGIOL meets + 16.000ns delay constraint less + -0.172ns skew and + 0.153ns DO_SET requirement (totaling 16.019ns) by 6.966ns + + Physical Path Details: + + Data path SLICE_27 to nRCAS_MGIOL: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R7C11C.CLK to R7C11C.Q1 SLICE_27 (from RCLK_c) +ROUTE 6 1.125 R7C11C.Q1 to R8C12A.C1 IS[2] +CTOF_DEL --- 0.495 R8C12A.C1 to R8C12A.F1 SLICE_83 +ROUTE 3 0.973 R8C12A.F1 to R8C11B.A0 un1_nRCAS_6_sqmuxa_i_o2 +CTOF_DEL --- 0.495 R8C11B.A0 to R8C11B.F0 SLICE_62 +ROUTE 2 0.632 R8C11B.F0 to R9C11A.D0 N_48 +CTOF_DEL --- 0.495 R9C11A.D0 to R9C11A.F0 SLICE_69 +ROUTE 1 0.626 R9C11A.F0 to R9C11A.D1 nRCS_9_u_i_o3_0_0 +CTOF_DEL --- 0.495 R9C11A.D1 to R9C11A.F1 SLICE_69 +ROUTE 1 0.744 R9C11A.F1 to R9C12C.C1 nRCS_9_u_i_o3_0_2 +CTOF_DEL --- 0.495 R9C12C.C1 to R9C12C.F1 SLICE_101 +ROUTE 1 2.026 R9C12C.F1 to IOL_R10C.OPOS N_251_i (to RCLK_c) + -------- + 9.053 (32.3% logic, 67.7% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_27: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.264 63.PADDI to R7C11C.CLK RCLK_c + -------- + 2.264 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to nRCAS_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.436 63.PADDI to IOL_R10C.CLK RCLK_c + -------- + 2.436 (0.0% logic, 100.0% route), 0 logic levels. + +Report: 102.197MHz is the maximum frequency for this preference. Report Summary -------------- @@ -1146,13 +1144,13 @@ Report: 98.020MHz is the maximum frequency for this preference. Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | -FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 50.206 MHz| 6 +FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 48.464 MHz| 5 | | | FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0 | | | FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0 | | | -FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 98.020 MHz| 5 +FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 102.197 MHz| 6 | | | ---------------------------------------------------------------------------- @@ -1165,7 +1163,7 @@ All preferences were met. Found 4 clocks: -Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12 +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11 No transfer within this clock domain is found Data transfers from: @@ -1207,11 +1205,11 @@ Clock Domain: PHI2_c Source: PHI2.PAD Loads: 21 Timing errors: 0 Score: 0 Cumulative negative slack: 0 -Constraints cover 1015 paths, 4 nets, and 725 connections (73.01% coverage) +Constraints cover 1038 paths, 4 nets, and 750 connections (74.18% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 -Thu Oct 19 23:51:11 2023 +Sat Nov 18 02:06:13 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -1236,7 +1234,7 @@ Report level: verbose report, limited to 10 items per preference
  • FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)
    • 0 items scored, 0 timing errors detected. -
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    • 868 items scored, 0 timing errors detected. +
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    • 891 items scored, 0 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS @@ -1254,43 +1252,43 @@ Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q C1Submitted (from PHI2_c -) - Destination: FF Data in C1Submitted (to PHI2_c -) + Source: FF Q ADSubmitted (from PHI2_c -) + Destination: FF Data in ADSubmitted (to PHI2_c -) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: - 0.366ns physical path delay SLICE_11 to SLICE_11 meets + 0.366ns physical path delay SLICE_10 to SLICE_10 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: - Data path SLICE_11 to SLICE_11: + Data path SLICE_10 to SLICE_10: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C12A.CLK to R5C12A.Q0 SLICE_11 (from PHI2_c) -ROUTE 2 0.132 R5C12A.Q0 to R5C12A.A0 C1Submitted -CTOF_DEL --- 0.101 R5C12A.A0 to R5C12A.F0 SLICE_11 -ROUTE 1 0.000 R5C12A.F0 to R5C12A.DI0 C1Submitted_RNO (to PHI2_c) +REG_DEL --- 0.133 R4C9D.CLK to R4C9D.Q0 SLICE_10 (from PHI2_c) +ROUTE 2 0.132 R4C9D.Q0 to R4C9D.A0 ADSubmitted +CTOF_DEL --- 0.101 R4C9D.A0 to R4C9D.F0 SLICE_10 +ROUTE 1 0.000 R4C9D.F0 to R4C9D.DI0 ADSubmitted_r_0_0 (to PHI2_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_11: + Source Clock Path PHI2 to SLICE_10: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R5C12A.CLK PHI2_c +ROUTE 21 1.423 8.PADDI to R4C9D.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_11: + Destination Clock Path PHI2 to SLICE_10: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R5C12A.CLK PHI2_c +ROUTE 21 1.423 8.PADDI to R4C9D.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. @@ -1316,10 +1314,10 @@ Passed: The following path meets requirements by 0.379ns Data path SLICE_20 to SLICE_20: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R4C10B.CLK to R4C10B.Q0 SLICE_20 (from PHI2_c) -ROUTE 2 0.132 R4C10B.Q0 to R4C10B.A0 CmdUFMShift -CTOF_DEL --- 0.101 R4C10B.A0 to R4C10B.F0 SLICE_20 -ROUTE 1 0.000 R4C10B.F0 to R4C10B.DI0 CmdUFMShift_3 (to PHI2_c) +REG_DEL --- 0.133 R7C9A.CLK to R7C9A.Q0 SLICE_20 (from PHI2_c) +ROUTE 2 0.132 R7C9A.Q0 to R7C9A.A0 CmdUFMShift +CTOF_DEL --- 0.101 R7C9A.A0 to R7C9A.F0 SLICE_20 +ROUTE 1 0.000 R7C9A.F0 to R7C9A.DI0 CmdUFMShift_3 (to PHI2_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. @@ -1328,384 +1326,384 @@ ROUTE 1 0.000 R4C10B.F0 to R4C10B.DI0 CmdUFMShift_3 (to PHI Source Clock Path PHI2 to SLICE_20: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R4C10B.CLK PHI2_c +ROUTE 21 1.423 8.PADDI to R7C9A.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_20: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R4C10B.CLK PHI2_c +ROUTE 21 1.423 8.PADDI to R7C9A.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 0.382ns +Passed: The following path meets requirements by 0.385ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q ADSubmitted (from PHI2_c -) - Destination: FF Data in ADSubmitted (to PHI2_c -) + Source: FF Q C1Submitted (from PHI2_c -) + Destination: FF Data in C1Submitted (to PHI2_c -) - Delay: 0.369ns (63.4% logic, 36.6% route), 2 logic levels. + Delay: 0.372ns (62.9% logic, 37.1% route), 2 logic levels. Constraint Details: - 0.369ns physical path delay SLICE_10 to SLICE_10 meets + 0.372ns physical path delay SLICE_11 to SLICE_11 meets -0.013ns DIN_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.382ns + 0.000ns skew requirement (totaling -0.013ns) by 0.385ns Physical Path Details: - Data path SLICE_10 to SLICE_10: + Data path SLICE_11 to SLICE_11: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C12C.CLK to R5C12C.Q0 SLICE_10 (from PHI2_c) -ROUTE 2 0.135 R5C12C.Q0 to R5C12C.D0 ADSubmitted -CTOF_DEL --- 0.101 R5C12C.D0 to R5C12C.F0 SLICE_10 -ROUTE 1 0.000 R5C12C.F0 to R5C12C.DI0 ADSubmitted_r_0 (to PHI2_c) +REG_DEL --- 0.133 R4C9A.CLK to R4C9A.Q0 SLICE_11 (from PHI2_c) +ROUTE 2 0.138 R4C9A.Q0 to R4C9A.C0 C1Submitted +CTOF_DEL --- 0.101 R4C9A.C0 to R4C9A.F0 SLICE_11 +ROUTE 1 0.000 R4C9A.F0 to R4C9A.DI0 C1Submitted_RNO (to PHI2_c) -------- - 0.369 (63.4% logic, 36.6% route), 2 logic levels. + 0.372 (62.9% logic, 37.1% route), 2 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_10: + Source Clock Path PHI2 to SLICE_11: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R5C12C.CLK PHI2_c +ROUTE 21 1.423 8.PADDI to R4C9A.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_10: + Destination Clock Path PHI2 to SLICE_11: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R5C12C.CLK PHI2_c +ROUTE 21 1.423 8.PADDI to R4C9A.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 0.387ns +Passed: The following path meets requirements by 0.471ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CmdEnable (from PHI2_c -) Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 0.374ns (62.6% logic, 37.4% route), 2 logic levels. + Delay: 0.458ns (51.1% logic, 48.9% route), 2 logic levels. Constraint Details: - 0.374ns physical path delay SLICE_17 to SLICE_17 meets + 0.458ns physical path delay SLICE_17 to SLICE_17 meets -0.013ns DIN_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.387ns + 0.000ns skew requirement (totaling -0.013ns) by 0.471ns Physical Path Details: Data path SLICE_17 to SLICE_17: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C11D.CLK to R5C11D.Q0 SLICE_17 (from PHI2_c) -ROUTE 4 0.140 R5C11D.Q0 to R5C11D.D0 CmdEnable -CTOF_DEL --- 0.101 R5C11D.D0 to R5C11D.F0 SLICE_17 -ROUTE 1 0.000 R5C11D.F0 to R5C11D.DI0 CmdEnable_s (to PHI2_c) +REG_DEL --- 0.133 R4C9B.CLK to R4C9B.Q0 SLICE_17 (from PHI2_c) +ROUTE 2 0.224 R4C9B.Q0 to R4C9B.B0 CmdEnable +CTOF_DEL --- 0.101 R4C9B.B0 to R4C9B.F0 SLICE_17 +ROUTE 1 0.000 R4C9B.F0 to R4C9B.DI0 CmdEnable_s (to PHI2_c) -------- - 0.374 (62.6% logic, 37.4% route), 2 logic levels. + 0.458 (51.1% logic, 48.9% route), 2 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_17: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R5C11D.CLK PHI2_c +ROUTE 21 1.423 8.PADDI to R4C9B.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_17: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R5C11D.CLK PHI2_c +ROUTE 21 1.423 8.PADDI to R4C9B.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.616ns - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CmdUFMWrite (from PHI2_c -) - Destination: FF Data in CmdUFMWrite (to PHI2_c -) - - Delay: 0.603ns (55.6% logic, 44.4% route), 3 logic levels. - - Constraint Details: - - 0.603ns physical path delay SLICE_21 to SLICE_21 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.616ns - - Physical Path Details: - - Data path SLICE_21 to SLICE_21: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R4C10D.CLK to R4C10D.Q0 SLICE_21 (from PHI2_c) -ROUTE 2 0.212 R4C10D.Q0 to R4C10D.A1 CmdUFMWrite -CTOF_DEL --- 0.101 R4C10D.A1 to R4C10D.F1 SLICE_21 -ROUTE 1 0.056 R4C10D.F1 to R4C10D.C0 N_279 -CTOF_DEL --- 0.101 R4C10D.C0 to R4C10D.F0 SLICE_21 -ROUTE 1 0.000 R4C10D.F0 to R4C10D.DI0 CmdUFMWrite_3 (to PHI2_c) - -------- - 0.603 (55.6% logic, 44.4% route), 3 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_21: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R4C10D.CLK PHI2_c - -------- - 1.423 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_21: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R4C10D.CLK PHI2_c - -------- - 1.423 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.616ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Cmdn8MEGEN (from PHI2_c -) - Destination: FF Data in Cmdn8MEGEN (to PHI2_c -) - - Delay: 0.603ns (55.6% logic, 44.4% route), 3 logic levels. - - Constraint Details: - - 0.603ns physical path delay SLICE_24 to SLICE_24 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.616ns - - Physical Path Details: - - Data path SLICE_24 to SLICE_24: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C10C.CLK to R3C10C.Q0 SLICE_24 (from PHI2_c) -ROUTE 2 0.212 R3C10C.Q0 to R3C10C.A1 Cmdn8MEGEN -CTOF_DEL --- 0.101 R3C10C.A1 to R3C10C.F1 SLICE_24 -ROUTE 1 0.056 R3C10C.F1 to R3C10C.C0 Cmdn8MEGEN_4_u_i_0 -CTOF_DEL --- 0.101 R3C10C.C0 to R3C10C.F0 SLICE_24 -ROUTE 1 0.000 R3C10C.F0 to R3C10C.DI0 N_285_i (to PHI2_c) - -------- - 0.603 (55.6% logic, 44.4% route), 3 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_24: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R3C10C.CLK PHI2_c - -------- - 1.423 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_24: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R3C10C.CLK PHI2_c - -------- - 1.423 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.616ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q XOR8MEG (from PHI2_c -) - Destination: FF Data in XOR8MEG (to PHI2_c -) - - Delay: 0.603ns (55.6% logic, 44.4% route), 3 logic levels. - - Constraint Details: - - 0.603ns physical path delay SLICE_45 to SLICE_45 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.616ns - - Physical Path Details: - - Data path SLICE_45 to SLICE_45: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C10D.CLK to R5C10D.Q0 SLICE_45 (from PHI2_c) -ROUTE 2 0.212 R5C10D.Q0 to R5C10D.A1 XOR8MEG -CTOF_DEL --- 0.101 R5C10D.A1 to R5C10D.F1 SLICE_45 -ROUTE 1 0.056 R5C10D.F1 to R5C10D.C0 N_274 -CTOF_DEL --- 0.101 R5C10D.C0 to R5C10D.F0 SLICE_45 -ROUTE 1 0.000 R5C10D.F0 to R5C10D.DI0 XOR8MEG_3 (to PHI2_c) - -------- - 0.603 (55.6% logic, 44.4% route), 3 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_45: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R5C10D.CLK PHI2_c - -------- - 1.423 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_45: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R5C10D.CLK PHI2_c - -------- - 1.423 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.628ns - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CmdLEDEN (from PHI2_c -) Destination: FF Data in CmdLEDEN (to PHI2_c -) - Delay: 0.615ns (54.5% logic, 45.5% route), 3 logic levels. + Delay: 0.603ns (55.6% logic, 44.4% route), 3 logic levels. Constraint Details: - 0.615ns physical path delay SLICE_18 to SLICE_18 meets + 0.603ns physical path delay SLICE_18 to SLICE_18 meets -0.013ns DIN_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.628ns + 0.000ns skew requirement (totaling -0.013ns) by 0.616ns Physical Path Details: Data path SLICE_18 to SLICE_18: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C10B.CLK to R3C10B.Q0 SLICE_18 (from PHI2_c) -ROUTE 2 0.224 R3C10B.Q0 to R3C10B.B1 CmdLEDEN -CTOF_DEL --- 0.101 R3C10B.B1 to R3C10B.F1 SLICE_18 -ROUTE 1 0.056 R3C10B.F1 to R3C10B.C0 CmdLEDEN_4_u_i_0 -CTOF_DEL --- 0.101 R3C10B.C0 to R3C10B.F0 SLICE_18 -ROUTE 1 0.000 R3C10B.F0 to R3C10B.DI0 N_284_i (to PHI2_c) +REG_DEL --- 0.133 R7C8C.CLK to R7C8C.Q0 SLICE_18 (from PHI2_c) +ROUTE 2 0.212 R7C8C.Q0 to R7C8C.A1 CmdLEDEN +CTOF_DEL --- 0.101 R7C8C.A1 to R7C8C.F1 SLICE_18 +ROUTE 1 0.056 R7C8C.F1 to R7C8C.C0 CmdLEDEN_4_u_i_m2_i_0 +CTOF_DEL --- 0.101 R7C8C.C0 to R7C8C.F0 SLICE_18 +ROUTE 1 0.000 R7C8C.F0 to R7C8C.DI0 N_17_i (to PHI2_c) -------- - 0.615 (54.5% logic, 45.5% route), 3 logic levels. + 0.603 (55.6% logic, 44.4% route), 3 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_18: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R3C10B.CLK PHI2_c +ROUTE 21 1.423 8.PADDI to R7C8C.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_18: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R3C10B.CLK PHI2_c +ROUTE 21 1.423 8.PADDI to R7C8C.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 0.632ns +Passed: The following path meets requirements by 0.622ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q C1Submitted (from PHI2_c -) + Destination: FF Data in CmdEnable (to PHI2_c -) + + Delay: 0.609ns (55.0% logic, 45.0% route), 3 logic levels. + + Constraint Details: + + 0.609ns physical path delay SLICE_11 to SLICE_17 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.622ns + + Physical Path Details: + + Data path SLICE_11 to SLICE_17: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R4C9A.CLK to R4C9A.Q0 SLICE_11 (from PHI2_c) +ROUTE 2 0.137 R4C9A.Q0 to R5C9D.D0 C1Submitted +CTOF_DEL --- 0.101 R5C9D.D0 to R5C9D.F0 SLICE_76 +ROUTE 1 0.137 R5C9D.F0 to R4C9B.C0 un1_CmdEnable20_i +CTOF_DEL --- 0.101 R4C9B.C0 to R4C9B.F0 SLICE_17 +ROUTE 1 0.000 R4C9B.F0 to R4C9B.DI0 CmdEnable_s (to PHI2_c) + -------- + 0.609 (55.0% logic, 45.0% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_11: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 1.423 8.PADDI to R4C9A.CLK PHI2_c + -------- + 1.423 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_17: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 1.423 8.PADDI to R4C9B.CLK PHI2_c + -------- + 1.423 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.705ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Cmdn8MEGEN (from PHI2_c -) + Destination: FF Data in Cmdn8MEGEN (to PHI2_c -) + + Delay: 0.692ns (48.4% logic, 51.6% route), 3 logic levels. + + Constraint Details: + + 0.692ns physical path delay SLICE_24 to SLICE_24 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.705ns + + Physical Path Details: + + Data path SLICE_24 to SLICE_24: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R7C8B.CLK to R7C8B.Q0 SLICE_24 (from PHI2_c) +ROUTE 2 0.135 R7C8B.Q0 to R7C8B.D1 Cmdn8MEGEN +CTOF_DEL --- 0.101 R7C8B.D1 to R7C8B.F1 SLICE_24 +ROUTE 1 0.222 R7C8B.F1 to R7C8B.B0 Cmdn8MEGEN_4_u_i_m2_i_0 +CTOF_DEL --- 0.101 R7C8B.B0 to R7C8B.F0 SLICE_24 +ROUTE 1 0.000 R7C8B.F0 to R7C8B.DI0 N_15_i (to PHI2_c) + -------- + 0.692 (48.4% logic, 51.6% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_24: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 1.423 8.PADDI to R7C8B.CLK PHI2_c + -------- + 1.423 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_24: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 1.423 8.PADDI to R7C8B.CLK PHI2_c + -------- + 1.423 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.728ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable (from PHI2_c -) + Destination: FF Data in CmdUFMShift (to PHI2_c -) + + Delay: 0.700ns (33.4% logic, 66.6% route), 2 logic levels. + + Constraint Details: + + 0.700ns physical path delay SLICE_17 to SLICE_20 meets + -0.028ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.028ns) by 0.728ns + + Physical Path Details: + + Data path SLICE_17 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R4C9B.CLK to R4C9B.Q0 SLICE_17 (from PHI2_c) +ROUTE 2 0.277 R4C9B.Q0 to R5C9A.C1 CmdEnable +CTOF_DEL --- 0.101 R5C9A.C1 to R5C9A.F1 SLICE_23 +ROUTE 8 0.189 R5C9A.F1 to R7C9A.CE XOR8MEG18 (to PHI2_c) + -------- + 0.700 (33.4% logic, 66.6% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_17: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 1.423 8.PADDI to R4C9B.CLK PHI2_c + -------- + 1.423 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 1.423 8.PADDI to R7C9A.CLK PHI2_c + -------- + 1.423 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.770ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CmdEnable (from PHI2_c -) Destination: FF Data in CmdValid_fast (to PHI2_c -) - Delay: 0.619ns (54.1% logic, 45.9% route), 3 logic levels. + Delay: 0.757ns (44.3% logic, 55.7% route), 3 logic levels. Constraint Details: - 0.619ns physical path delay SLICE_17 to SLICE_23 meets + 0.757ns physical path delay SLICE_17 to SLICE_23 meets -0.013ns DIN_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.632ns + 0.000ns skew requirement (totaling -0.013ns) by 0.770ns Physical Path Details: Data path SLICE_17 to SLICE_23: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C11D.CLK to R5C11D.Q0 SLICE_17 (from PHI2_c) -ROUTE 4 0.226 R5C11D.Q0 to R4C10C.C1 CmdEnable -CTOF_DEL --- 0.101 R4C10C.C1 to R4C10C.F1 SLICE_23 -ROUTE 2 0.058 R4C10C.F1 to R4C10C.C0 XOR8MEG18_i -CTOF_DEL --- 0.101 R4C10C.C0 to R4C10C.F0 SLICE_23 -ROUTE 1 0.000 R4C10C.F0 to R4C10C.DI0 N_36_fast (to PHI2_c) +REG_DEL --- 0.133 R4C9B.CLK to R4C9B.Q0 SLICE_17 (from PHI2_c) +ROUTE 2 0.277 R4C9B.Q0 to R5C9A.C1 CmdEnable +CTOF_DEL --- 0.101 R5C9A.C1 to R5C9A.F1 SLICE_23 +ROUTE 8 0.145 R5C9A.F1 to R5C9A.B0 XOR8MEG18 +CTOF_DEL --- 0.101 R5C9A.B0 to R5C9A.F0 SLICE_23 +ROUTE 1 0.000 R5C9A.F0 to R5C9A.DI0 N_34_fast (to PHI2_c) -------- - 0.619 (54.1% logic, 45.9% route), 3 logic levels. + 0.757 (44.3% logic, 55.7% route), 3 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_17: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R5C11D.CLK PHI2_c +ROUTE 21 1.423 8.PADDI to R4C9B.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_23: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R4C10C.CLK PHI2_c +ROUTE 21 1.423 8.PADDI to R5C9A.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 0.661ns +Passed: The following path meets requirements by 0.782ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q CmdEnable (from PHI2_c -) - Destination: FF Data in XOR8MEG (to PHI2_c -) + Source: FF Q CmdUFMWrite (from PHI2_c -) + Destination: FF Data in CmdUFMWrite (to PHI2_c -) - Delay: 0.633ns (37.0% logic, 63.0% route), 2 logic levels. + Delay: 0.769ns (43.6% logic, 56.4% route), 3 logic levels. Constraint Details: - 0.633ns physical path delay SLICE_17 to SLICE_45 meets - -0.028ns CE_HLD and + 0.769ns physical path delay SLICE_21 to SLICE_21 meets + -0.013ns DIN_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.028ns) by 0.661ns + 0.000ns skew requirement (totaling -0.013ns) by 0.782ns Physical Path Details: - Data path SLICE_17 to SLICE_45: + Data path SLICE_21 to SLICE_21: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C11D.CLK to R5C11D.Q0 SLICE_17 (from PHI2_c) -ROUTE 4 0.140 R5C11D.Q0 to R5C11C.D1 CmdEnable -CTOF_DEL --- 0.101 R5C11C.D1 to R5C11C.F1 SLICE_106 -ROUTE 5 0.259 R5C11C.F1 to R5C10D.CE XOR8MEG18 (to PHI2_c) +REG_DEL --- 0.133 R7C8D.CLK to R7C8D.Q0 SLICE_21 (from PHI2_c) +ROUTE 2 0.224 R7C8D.Q0 to R7C8D.B1 CmdUFMWrite +CTOF_DEL --- 0.101 R7C8D.B1 to R7C8D.F1 SLICE_21 +ROUTE 1 0.210 R7C8D.F1 to R7C8D.A0 N_415 +CTOF_DEL --- 0.101 R7C8D.A0 to R7C8D.F0 SLICE_21 +ROUTE 1 0.000 R7C8D.F0 to R7C8D.DI0 CmdUFMWrite_3 (to PHI2_c) -------- - 0.633 (37.0% logic, 63.0% route), 2 logic levels. + 0.769 (43.6% logic, 56.4% route), 3 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_17: + Source Clock Path PHI2 to SLICE_21: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R5C11D.CLK PHI2_c +ROUTE 21 1.423 8.PADDI to R7C8D.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_45: + Destination Clock Path PHI2 to SLICE_21: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.423 8.PADDI to R5C10D.CLK PHI2_c +ROUTE 21 1.423 8.PADDI to R7C8D.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. @@ -1724,7 +1722,7 @@ ROUTE 21 1.423 8.PADDI to R5C10D.CLK PHI2_c ================================================================================ Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; - 868 items scored, 0 timing errors detected. + 891 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- @@ -1749,8 +1747,8 @@ Passed: The following path meets requirements by 0.304ns Data path SLICE_12 to SLICE_12: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C12B.CLK to R5C12B.Q0 SLICE_12 (from RCLK_c) -ROUTE 1 0.152 R5C12B.Q0 to R5C12B.M1 CASr (to RCLK_c) +REG_DEL --- 0.133 R5C10B.CLK to R5C10B.Q0 SLICE_12 (from RCLK_c) +ROUTE 1 0.152 R5C10B.Q0 to R5C10B.M1 CASr (to RCLK_c) -------- 0.285 (46.7% logic, 53.3% route), 1 logic levels. @@ -1759,57 +1757,14 @@ ROUTE 1 0.152 R5C12B.Q0 to R5C12B.M1 CASr (to RCLK_c) Source Clock Path RCLK to SLICE_12: Name Fanout Delay (ns) Site Resource -ROUTE 48 0.788 63.PADDI to R5C12B.CLK RCLK_c +ROUTE 48 0.788 63.PADDI to R5C10B.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_12: Name Fanout Delay (ns) Site Resource -ROUTE 48 0.788 63.PADDI to R5C12B.CLK RCLK_c - -------- - 0.788 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.306ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CASr2 (from RCLK_c +) - Destination: FF Data in CASr3 (to RCLK_c +) - - Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. - - Constraint Details: - - 0.287ns physical path delay SLICE_12 to SLICE_76 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.306ns - - Physical Path Details: - - Data path SLICE_12 to SLICE_76: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C12B.CLK to R5C12B.Q1 SLICE_12 (from RCLK_c) -ROUTE 4 0.154 R5C12B.Q1 to R5C12D.M0 CASr2 (to RCLK_c) - -------- - 0.287 (46.3% logic, 53.7% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_12: - - Name Fanout Delay (ns) Site Resource -ROUTE 48 0.788 63.PADDI to R5C12B.CLK RCLK_c - -------- - 0.788 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_76: - - Name Fanout Delay (ns) Site Resource -ROUTE 48 0.788 63.PADDI to R5C12D.CLK RCLK_c +ROUTE 48 0.788 63.PADDI to R5C10B.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. @@ -1825,113 +1780,113 @@ Passed: The following path meets requirements by 0.306ns Constraint Details: - 0.287ns physical path delay SLICE_33 to SLICE_33 meets + 0.287ns physical path delay SLICE_32 to SLICE_32 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns - Physical Path Details: - - Data path SLICE_33 to SLICE_33: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R7C10D.CLK to R7C10D.Q0 SLICE_33 (from RCLK_c) -ROUTE 2 0.154 R7C10D.Q0 to R7C10D.M1 RASr (to RCLK_c) - -------- - 0.287 (46.3% logic, 53.7% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_33: - - Name Fanout Delay (ns) Site Resource -ROUTE 48 0.788 63.PADDI to R7C10D.CLK RCLK_c - -------- - 0.788 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_33: - - Name Fanout Delay (ns) Site Resource -ROUTE 48 0.788 63.PADDI to R7C10D.CLK RCLK_c - -------- - 0.788 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.311ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q PHI2r2 (from RCLK_c +) - Destination: FF Data in PHI2r3 (to RCLK_c +) - - Delay: 0.292ns (45.5% logic, 54.5% route), 1 logic levels. - - Constraint Details: - - 0.292ns physical path delay SLICE_32 to SLICE_32 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.311ns - Physical Path Details: Data path SLICE_32 to SLICE_32: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C9D.CLK to R3C9D.Q0 SLICE_32 (from RCLK_c) -ROUTE 5 0.159 R3C9D.Q0 to R3C9D.M1 PHI2r2 (to RCLK_c) +REG_DEL --- 0.133 R4C12C.CLK to R4C12C.Q0 SLICE_32 (from RCLK_c) +ROUTE 2 0.154 R4C12C.Q0 to R4C12C.M1 RASr (to RCLK_c) -------- - 0.292 (45.5% logic, 54.5% route), 1 logic levels. + 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_32: Name Fanout Delay (ns) Site Resource -ROUTE 48 0.788 63.PADDI to R3C9D.CLK RCLK_c +ROUTE 48 0.788 63.PADDI to R4C12C.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_32: Name Fanout Delay (ns) Site Resource -ROUTE 48 0.788 63.PADDI to R3C9D.CLK RCLK_c +ROUTE 48 0.788 63.PADDI to R4C12C.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 0.347ns +Passed: The following path meets requirements by 0.322ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q wb_dati[3] (from RCLK_c +) - Destination: EFB Port ufmefb/EFBInst_0(ASIC) (to RCLK_c +) + Source: FF Q PHI2r2 (from RCLK_c +) + Destination: FF Data in PHI2r3 (to RCLK_c +) - Delay: 0.306ns (43.5% logic, 56.5% route), 1 logic levels. + Delay: 0.303ns (43.9% logic, 56.1% route), 1 logic levels. Constraint Details: - 0.306ns physical path delay SLICE_54 to ufmefb/EFBInst_0 meets - -0.095ns WBDATI_HLD and + 0.303ns physical path delay SLICE_31 to SLICE_31 meets + -0.019ns M_HLD and 0.000ns delay constraint less - -0.054ns skew requirement (totaling -0.041ns) by 0.347ns + 0.000ns skew requirement (totaling -0.019ns) by 0.322ns Physical Path Details: - Data path SLICE_54 to ufmefb/EFBInst_0: + Data path SLICE_31 to SLICE_31: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R2C6D.CLK to R2C6D.Q1 SLICE_54 (from RCLK_c) -ROUTE 2 0.173 R2C6D.Q1 to EFB.WBDATI3 wb_dati[3] (to RCLK_c) +REG_DEL --- 0.133 R5C8B.CLK to R5C8B.Q0 SLICE_31 (from RCLK_c) +ROUTE 5 0.170 R5C8B.Q0 to R5C8B.M1 PHI2r2 (to RCLK_c) -------- - 0.306 (43.5% logic, 56.5% route), 1 logic levels. + 0.303 (43.9% logic, 56.1% route), 1 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_54: + Source Clock Path RCLK to SLICE_31: Name Fanout Delay (ns) Site Resource -ROUTE 48 0.788 63.PADDI to R2C6D.CLK RCLK_c +ROUTE 48 0.788 63.PADDI to R5C8B.CLK RCLK_c + -------- + 0.788 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_31: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 0.788 63.PADDI to R5C8B.CLK RCLK_c + -------- + 0.788 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.326ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q wb_dati[7] (from RCLK_c +) + Destination: EFB Port ufmefb/EFBInst_0(ASIC) (to RCLK_c +) + + Delay: 0.307ns (43.3% logic, 56.7% route), 1 logic levels. + + Constraint Details: + + 0.307ns physical path delay SLICE_55 to ufmefb/EFBInst_0 meets + -0.073ns WBDATI_HLD and + 0.000ns delay constraint less + -0.054ns skew requirement (totaling -0.019ns) by 0.326ns + + Physical Path Details: + + Data path SLICE_55 to ufmefb/EFBInst_0: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R3C6C.CLK to R3C6C.Q1 SLICE_55 (from RCLK_c) +ROUTE 2 0.174 R3C6C.Q1 to EFB.WBDATI7 wb_dati[7] (to RCLK_c) + -------- + 0.307 (43.3% logic, 56.7% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_55: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 0.788 63.PADDI to R3C6C.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. @@ -1964,10 +1919,10 @@ Passed: The following path meets requirements by 0.379ns Data path SLICE_0 to SLICE_0: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C4A.CLK to R5C4A.Q1 SLICE_0 (from RCLK_c) -ROUTE 3 0.132 R5C4A.Q1 to R5C4A.A1 FS[0] -CTOF_DEL --- 0.101 R5C4A.A1 to R5C4A.F1 SLICE_0 -ROUTE 1 0.000 R5C4A.F1 to R5C4A.DI1 FS_s[0] (to RCLK_c) +REG_DEL --- 0.133 R2C7A.CLK to R2C7A.Q1 SLICE_0 (from RCLK_c) +ROUTE 3 0.132 R2C7A.Q1 to R2C7A.A1 FS[0] +CTOF_DEL --- 0.101 R2C7A.A1 to R2C7A.F1 SLICE_0 +ROUTE 1 0.000 R2C7A.F1 to R2C7A.DI1 FS_s[0] (to RCLK_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. @@ -1976,14 +1931,14 @@ ROUTE 1 0.000 R5C4A.F1 to R5C4A.DI1 FS_s[0] (to RCLK_c) Source Clock Path RCLK to SLICE_0: Name Fanout Delay (ns) Site Resource -ROUTE 48 0.788 63.PADDI to R5C4A.CLK RCLK_c +ROUTE 48 0.788 63.PADDI to R2C7A.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_0: Name Fanout Delay (ns) Site Resource -ROUTE 48 0.788 63.PADDI to R5C4A.CLK RCLK_c +ROUTE 48 0.788 63.PADDI to R2C7A.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. @@ -2009,10 +1964,10 @@ Passed: The following path meets requirements by 0.379ns Data path SLICE_1 to SLICE_1: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C6B.CLK to R5C6B.Q0 SLICE_1 (from RCLK_c) -ROUTE 5 0.132 R5C6B.Q0 to R5C6B.A0 FS[17] -CTOF_DEL --- 0.101 R5C6B.A0 to R5C6B.F0 SLICE_1 -ROUTE 1 0.000 R5C6B.F0 to R5C6B.DI0 FS_s[17] (to RCLK_c) +REG_DEL --- 0.133 R2C9B.CLK to R2C9B.Q0 SLICE_1 (from RCLK_c) +ROUTE 7 0.132 R2C9B.Q0 to R2C9B.A0 FS[17] +CTOF_DEL --- 0.101 R2C9B.A0 to R2C9B.F0 SLICE_1 +ROUTE 1 0.000 R2C9B.F0 to R2C9B.DI0 FS_s[17] (to RCLK_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. @@ -2021,14 +1976,14 @@ ROUTE 1 0.000 R5C6B.F0 to R5C6B.DI0 FS_s[17] (to RCLK_c) Source Clock Path RCLK to SLICE_1: Name Fanout Delay (ns) Site Resource -ROUTE 48 0.788 63.PADDI to R5C6B.CLK RCLK_c +ROUTE 48 0.788 63.PADDI to R2C9B.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_1: Name Fanout Delay (ns) Site Resource -ROUTE 48 0.788 63.PADDI to R5C6B.CLK RCLK_c +ROUTE 48 0.788 63.PADDI to R2C9B.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. @@ -2054,10 +2009,10 @@ Passed: The following path meets requirements by 0.379ns Data path SLICE_2 to SLICE_2: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C6A.CLK to R5C6A.Q0 SLICE_2 (from RCLK_c) -ROUTE 4 0.132 R5C6A.Q0 to R5C6A.A0 FS[15] -CTOF_DEL --- 0.101 R5C6A.A0 to R5C6A.F0 SLICE_2 -ROUTE 1 0.000 R5C6A.F0 to R5C6A.DI0 FS_s[15] (to RCLK_c) +REG_DEL --- 0.133 R2C9A.CLK to R2C9A.Q0 SLICE_2 (from RCLK_c) +ROUTE 6 0.132 R2C9A.Q0 to R2C9A.A0 FS[15] +CTOF_DEL --- 0.101 R2C9A.A0 to R2C9A.F0 SLICE_2 +ROUTE 1 0.000 R2C9A.F0 to R2C9A.DI0 FS_s[15] (to RCLK_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. @@ -2066,14 +2021,14 @@ ROUTE 1 0.000 R5C6A.F0 to R5C6A.DI0 FS_s[15] (to RCLK_c) Source Clock Path RCLK to SLICE_2: Name Fanout Delay (ns) Site Resource -ROUTE 48 0.788 63.PADDI to R5C6A.CLK RCLK_c +ROUTE 48 0.788 63.PADDI to R2C9A.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_2: Name Fanout Delay (ns) Site Resource -ROUTE 48 0.788 63.PADDI to R5C6A.CLK RCLK_c +ROUTE 48 0.788 63.PADDI to R2C9A.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. @@ -2082,43 +2037,43 @@ Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS[16] (from RCLK_c +) - Destination: FF Data in FS[16] (to RCLK_c +) + Source: FF Q FS[14] (from RCLK_c +) + Destination: FF Data in FS[14] (to RCLK_c +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: - 0.366ns physical path delay SLICE_2 to SLICE_2 meets + 0.366ns physical path delay SLICE_3 to SLICE_3 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: - Data path SLICE_2 to SLICE_2: + Data path SLICE_3 to SLICE_3: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C6A.CLK to R5C6A.Q1 SLICE_2 (from RCLK_c) -ROUTE 5 0.132 R5C6A.Q1 to R5C6A.A1 FS[16] -CTOF_DEL --- 0.101 R5C6A.A1 to R5C6A.F1 SLICE_2 -ROUTE 1 0.000 R5C6A.F1 to R5C6A.DI1 FS_s[16] (to RCLK_c) +REG_DEL --- 0.133 R2C8D.CLK to R2C8D.Q1 SLICE_3 (from RCLK_c) +ROUTE 19 0.132 R2C8D.Q1 to R2C8D.A1 FS[14] +CTOF_DEL --- 0.101 R2C8D.A1 to R2C8D.F1 SLICE_3 +ROUTE 1 0.000 R2C8D.F1 to R2C8D.DI1 FS_s[14] (to RCLK_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_2: + Source Clock Path RCLK to SLICE_3: Name Fanout Delay (ns) Site Resource -ROUTE 48 0.788 63.PADDI to R5C6A.CLK RCLK_c +ROUTE 48 0.788 63.PADDI to R2C8D.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_2: + Destination Clock Path RCLK to SLICE_3: Name Fanout Delay (ns) Site Resource -ROUTE 48 0.788 63.PADDI to R5C6A.CLK RCLK_c +ROUTE 48 0.788 63.PADDI to R2C8D.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. @@ -2127,43 +2082,88 @@ Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS[12] (from RCLK_c +) - Destination: FF Data in FS[12] (to RCLK_c +) + Source: FF Q LEDEN (from RCLK_c +) + Destination: FF Data in LEDEN (to RCLK_c +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: - 0.366ns physical path delay SLICE_4 to SLICE_4 meets + 0.366ns physical path delay SLICE_30 to SLICE_30 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: - Data path SLICE_4 to SLICE_4: + Data path SLICE_30 to SLICE_30: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C5C.CLK to R5C5C.Q1 SLICE_4 (from RCLK_c) -ROUTE 23 0.132 R5C5C.Q1 to R5C5C.A1 FS[12] -CTOF_DEL --- 0.101 R5C5C.A1 to R5C5C.F1 SLICE_4 -ROUTE 1 0.000 R5C5C.F1 to R5C5C.DI1 FS_s[12] (to RCLK_c) +REG_DEL --- 0.133 R7C5A.CLK to R7C5A.Q0 SLICE_30 (from RCLK_c) +ROUTE 4 0.132 R7C5A.Q0 to R7C5A.A0 LEDEN +CTOF_DEL --- 0.101 R7C5A.A0 to R7C5A.F0 SLICE_30 +ROUTE 1 0.000 R7C5A.F0 to R7C5A.DI0 LEDENe_0 (to RCLK_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_4: + Source Clock Path RCLK to SLICE_30: Name Fanout Delay (ns) Site Resource -ROUTE 48 0.788 63.PADDI to R5C5C.CLK RCLK_c +ROUTE 48 0.788 63.PADDI to R7C5A.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_4: + Destination Clock Path RCLK to SLICE_30: Name Fanout Delay (ns) Site Resource -ROUTE 48 0.788 63.PADDI to R5C5C.CLK RCLK_c +ROUTE 48 0.788 63.PADDI to R7C5A.CLK RCLK_c + -------- + 0.788 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.379ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q n8MEGEN (from RCLK_c +) + Destination: FF Data in n8MEGEN (to RCLK_c +) + + Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. + + Constraint Details: + + 0.366ns physical path delay SLICE_45 to SLICE_45 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.379ns + + Physical Path Details: + + Data path SLICE_45 to SLICE_45: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C5B.CLK to R5C5B.Q0 SLICE_45 (from RCLK_c) +ROUTE 3 0.132 R5C5B.Q0 to R5C5B.A0 n8MEGEN +CTOF_DEL --- 0.101 R5C5B.A0 to R5C5B.F0 SLICE_45 +ROUTE 1 0.000 R5C5B.F0 to R5C5B.DI0 n8MEGENe_0 (to RCLK_c) + -------- + 0.366 (63.9% logic, 36.1% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_45: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 0.788 63.PADDI to R5C5B.CLK RCLK_c + -------- + 0.788 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_45: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 0.788 63.PADDI to R5C5B.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. @@ -2192,7 +2192,7 @@ All preferences were met. Found 4 clocks: -Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12 +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11 No transfer within this clock domain is found Data transfers from: @@ -2234,7 +2234,7 @@ Clock Domain: PHI2_c Source: PHI2.PAD Loads: 21 Timing errors: 0 Score: 0 Cumulative negative slack: 0 -Constraints cover 1015 paths, 4 nets, and 725 connections (73.01% coverage) +Constraints cover 1038 paths, 4 nets, and 750 connections (74.18% coverage) diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_vo.sdf b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_vo.sdf index 6eacea8..49d3162 100644 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_vo.sdf +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_vo.sdf @@ -1,7 +1,7 @@ (DELAYFILE (SDFVERSION "3.0") (DESIGN "RAM2GS") - (DATE "Thu Oct 19 23:51:19 2023") + (DATE "Sat Nov 18 02:06:23 2023") (VENDOR "Lattice") (PROGRAM "ldbanno") (VERSION "Diamond (64-bit) 3.12.1.454") @@ -260,7 +260,7 @@ (DELAY (ABSOLUTE (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) @@ -305,7 +305,7 @@ (INSTANCE SLICE_12) (DELAY (ABSOLUTE - (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) (IOPATH CLK Q1 (392:422:452)(392:422:452)) ) @@ -328,8 +328,8 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) ) ) @@ -397,6 +397,7 @@ (INSTANCE SLICE_19) (DELAY (ABSOLUTE + (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) ) ) @@ -414,10 +415,6 @@ (INSTANCE SLICE_20) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) @@ -440,7 +437,7 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) @@ -466,8 +463,8 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) ) ) @@ -488,7 +485,7 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) ) @@ -510,9 +507,9 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) ) ) @@ -530,9 +527,9 @@ (INSTANCE SLICE_25) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) ) ) @@ -549,30 +546,12 @@ (INSTANCE SLICE_26) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) - ) - ) - (CELL - (CELLTYPE "SLICE_27") - (INSTANCE SLICE_27) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) ) @@ -586,14 +565,14 @@ ) ) (CELL - (CELLTYPE "SLICE_28") - (INSTANCE SLICE_28) + (CELLTYPE "SLICE_27") + (INSTANCE SLICE_27) (DELAY (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) (IOPATH CLK Q1 (392:422:452)(392:422:452)) @@ -610,12 +589,13 @@ ) ) (CELL - (CELLTYPE "SLICE_29") - (INSTANCE SLICE_29) + (CELLTYPE "SLICE_28") + (INSTANCE SLICE_28) (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) @@ -634,15 +614,37 @@ ) ) (CELL - (CELLTYPE "SLICE_30") - (INSTANCE SLICE_30) + (CELLTYPE "SLICE_29") + (INSTANCE SLICE_29) (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_30") + (INSTANCE SLICE_30) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) ) @@ -660,35 +662,8 @@ (INSTANCE SLICE_31) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "SLICE_32") - (INSTANCE SLICE_32) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) (IOPATH CLK Q1 (392:422:452)(392:422:452)) ) @@ -703,14 +678,14 @@ ) ) (CELL - (CELLTYPE "SLICE_33") - (INSTANCE SLICE_33) + (CELLTYPE "SLICE_32") + (INSTANCE SLICE_32) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) (IOPATH CLK Q1 (392:422:452)(392:422:452)) ) @@ -724,6 +699,27 @@ (WIDTH (negedge CLK) (1250:1250:1250)) ) ) + (CELL + (CELLTYPE "SLICE_33") + (INSTANCE SLICE_33) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) (CELL (CELLTYPE "SLICE_34") (INSTANCE SLICE_34) @@ -741,7 +737,7 @@ ) ) (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) ) (TIMINGCHECK (WIDTH (posedge CLK) (1250:1250:1250)) @@ -754,8 +750,6 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) @@ -778,7 +772,8 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) @@ -800,10 +795,9 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) @@ -823,31 +817,31 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) ) ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - ) (TIMINGCHECK (WIDTH (posedge CLK) (1250:1250:1250)) (WIDTH (negedge CLK) (1250:1250:1250)) ) + (TIMINGCHECK + (SETUPHOLD DI1 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + ) ) (CELL (CELLTYPE "SLICE_39") (INSTANCE SLICE_39) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) (IOPATH CLK Q1 (392:422:452)(392:422:452)) ) @@ -867,9 +861,9 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) (IOPATH CLK Q1 (392:422:452)(392:422:452)) ) @@ -889,9 +883,9 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) (IOPATH CLK Q1 (392:422:452)(392:422:452)) ) @@ -930,28 +924,6 @@ (CELL (CELLTYPE "SLICE_43") (INSTANCE SLICE_43) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (negedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) - ) - ) - (CELL - (CELLTYPE "SLICE_44") - (INSTANCE SLICE_44) (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) @@ -975,8 +947,8 @@ ) ) (CELL - (CELLTYPE "SLICE_45") - (INSTANCE SLICE_45) + (CELLTYPE "SLICE_44") + (INSTANCE SLICE_44) (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) @@ -1000,8 +972,8 @@ ) ) (CELL - (CELLTYPE "SLICE_46") - (INSTANCE SLICE_46) + (CELLTYPE "SLICE_45") + (INSTANCE SLICE_45) (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) @@ -1023,14 +995,12 @@ ) ) (CELL - (CELLTYPE "SLICE_47") - (INSTANCE SLICE_47) + (CELLTYPE "SLICE_46") + (INSTANCE SLICE_46) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) @@ -1050,8 +1020,8 @@ ) ) (CELL - (CELLTYPE "SLICE_48") - (INSTANCE SLICE_48) + (CELLTYPE "SLICE_47") + (INSTANCE SLICE_47) (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) @@ -1076,14 +1046,39 @@ (WIDTH (negedge CLK) (1250:1250:1250)) ) ) + (CELL + (CELLTYPE "SLICE_48") + (INSTANCE SLICE_48) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) (CELL (CELLTYPE "SLICE_49") (INSTANCE SLICE_49) (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) (IOPATH CLK Q1 (392:422:452)(392:422:452)) @@ -1105,32 +1100,7 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "SLICE_51") - (INSTANCE SLICE_51) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -1149,8 +1119,8 @@ ) ) (CELL - (CELLTYPE "SLICE_52") - (INSTANCE SLICE_52) + (CELLTYPE "SLICE_51") + (INSTANCE SLICE_51) (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) @@ -1176,6 +1146,33 @@ (WIDTH (negedge CLK) (1250:1250:1250)) ) ) + (CELL + (CELLTYPE "SLICE_52") + (INSTANCE SLICE_52) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) (CELL (CELLTYPE "SLICE_53") (INSTANCE SLICE_53) @@ -1187,7 +1184,6 @@ (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) (IOPATH CLK Q1 (392:422:452)(392:422:452)) @@ -1210,7 +1206,6 @@ (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) @@ -1239,6 +1234,7 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -1267,18 +1263,17 @@ (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) ) ) (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) ) (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) (WIDTH (posedge CLK) (1250:1250:1250)) (WIDTH (negedge CLK) (1250:1250:1250)) ) @@ -1292,33 +1287,6 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (4000:4000:4000)) - (WIDTH (negedge LSR) (4000:4000:4000)) - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "SLICE_58") - (INSTANCE SLICE_58) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -1334,12 +1302,11 @@ ) ) (CELL - (CELLTYPE "SLICE_59") - (INSTANCE SLICE_59) + (CELLTYPE "SLICE_58") + (INSTANCE SLICE_58) (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) @@ -1362,18 +1329,35 @@ ) ) (CELL - (CELLTYPE "SLICE_60") - (INSTANCE SLICE_60) + (CELLTYPE "wb_dati_5_1_iv_0_0_o2_5__SLICE_59") + (INSTANCE wb_dati_5_1_iv_0_0_o2\[5\]\/SLICE_59) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH D1 OFX0 (457:589:721)(457:589:721)) + (IOPATH C1 OFX0 (457:589:721)(457:589:721)) + (IOPATH B1 OFX0 (457:589:721)(457:589:721)) + (IOPATH A1 OFX0 (457:589:721)(457:589:721)) + (IOPATH D0 OFX0 (457:589:721)(457:589:721)) + (IOPATH C0 OFX0 (457:589:721)(457:589:721)) + (IOPATH B0 OFX0 (457:589:721)(457:589:721)) + (IOPATH A0 OFX0 (457:589:721)(457:589:721)) + (IOPATH M0 OFX0 (322:349:376)(322:349:376)) + ) + ) + ) + (CELL + (CELLTYPE "wb_adr_5_i_0_1_0__SLICE_60") + (INSTANCE wb_adr_5_i_0_1\[0\]\/SLICE_60) + (DELAY + (ABSOLUTE + (IOPATH C1 OFX0 (457:589:721)(457:589:721)) + (IOPATH B1 OFX0 (457:589:721)(457:589:721)) + (IOPATH A1 OFX0 (457:589:721)(457:589:721)) + (IOPATH D0 OFX0 (457:589:721)(457:589:721)) + (IOPATH C0 OFX0 (457:589:721)(457:589:721)) + (IOPATH B0 OFX0 (457:589:721)(457:589:721)) + (IOPATH A0 OFX0 (457:589:721)(457:589:721)) + (IOPATH M0 OFX0 (322:349:376)(322:349:376)) ) ) ) @@ -1451,7 +1435,6 @@ (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) ) @@ -1462,10 +1445,9 @@ (INSTANCE SLICE_66) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -1481,7 +1463,7 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) ) @@ -1496,9 +1478,9 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) ) ) ) @@ -1512,7 +1494,7 @@ (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) ) ) @@ -1526,6 +1508,7 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -1537,7 +1520,6 @@ (INSTANCE SLICE_71) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) @@ -1555,7 +1537,6 @@ (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) @@ -1568,7 +1549,6 @@ (INSTANCE SLICE_73) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) @@ -1576,18 +1556,8 @@ (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) ) ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) - (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) - ) ) (CELL (CELLTYPE "SLICE_74") @@ -1615,7 +1585,9 @@ (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) ) ) ) @@ -1624,13 +1596,38 @@ (INSTANCE SLICE_76) (DELAY (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + ) + ) + (CELL + (CELLTYPE "SLICE_77") + (INSTANCE SLICE_77) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) ) ) (TIMINGCHECK @@ -1641,27 +1638,12 @@ (WIDTH (negedge CLK) (1250:1250:1250)) ) ) - (CELL - (CELLTYPE "SLICE_77") - (INSTANCE SLICE_77) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) (CELL (CELLTYPE "SLICE_78") (INSTANCE SLICE_78) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) @@ -1676,7 +1658,6 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) @@ -1690,6 +1671,8 @@ (INSTANCE SLICE_80) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) @@ -1721,6 +1704,8 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) @@ -1736,7 +1721,6 @@ (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) @@ -1752,6 +1736,7 @@ (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) @@ -1781,11 +1766,12 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) ) ) ) @@ -1794,7 +1780,7 @@ (INSTANCE SLICE_87) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) @@ -1808,8 +1794,8 @@ (INSTANCE SLICE_88) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) @@ -1825,7 +1811,6 @@ (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) @@ -1856,6 +1841,7 @@ (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) @@ -1868,9 +1854,7 @@ (INSTANCE SLICE_92) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) @@ -1884,7 +1868,9 @@ (INSTANCE SLICE_93) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) @@ -1898,7 +1884,7 @@ (INSTANCE SLICE_94) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) @@ -1912,7 +1898,7 @@ (INSTANCE SLICE_95) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) @@ -1926,10 +1912,8 @@ (INSTANCE SLICE_96) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) @@ -1943,8 +1927,7 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) @@ -1959,7 +1942,6 @@ (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) @@ -1975,6 +1957,7 @@ (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) @@ -1988,9 +1971,7 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) @@ -2004,8 +1985,9 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -2018,8 +2000,12 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) ) ) @@ -2036,6 +2022,7 @@ (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) ) ) ) @@ -2049,7 +2036,8 @@ (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) ) ) ) @@ -2074,7 +2062,6 @@ (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) @@ -2088,10 +2075,9 @@ (INSTANCE SLICE_107) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -2105,11 +2091,8 @@ (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) ) ) ) @@ -2120,10 +2103,10 @@ (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) ) ) ) @@ -2132,11 +2115,10 @@ (INSTANCE SLICE_110) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) ) ) @@ -2147,11 +2129,12 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) ) ) ) @@ -2160,8 +2143,8 @@ (INSTANCE SLICE_112) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) @@ -2188,7 +2171,9 @@ (INSTANCE SLICE_114) (DELAY (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -2201,9 +2186,9 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) ) @@ -2215,7 +2200,9 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) ) @@ -2224,13 +2211,78 @@ (CELL (CELLTYPE "SLICE_117") (INSTANCE SLICE_117) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_118") + (INSTANCE SLICE_118) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_119") + (INSTANCE SLICE_119) (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_120") + (INSTANCE SLICE_120) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_121") + (INSTANCE SLICE_121) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_122") + (INSTANCE SLICE_122) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) ) ) ) @@ -2411,7 +2463,7 @@ (INSTANCE RCLKout_I) (DELAY (ABSOLUTE - (IOPATH IOLDO RCLKout (2773:2901:3030)(2773:2901:3030)) + (IOPATH IOLDO RCLKout (1946:2086:2226)(1946:2086:2226)) ) ) ) @@ -3427,8 +3479,8 @@ (DELAY (ABSOLUTE (INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_0/Q1 SLICE_52/D1 (973:1072:1171)(973:1072:1171)) - (INTERCONNECT SLICE_0/Q1 SLICE_87/B1 (1215:1382:1549)(1215:1382:1549)) + (INTERCONNECT SLICE_0/Q1 SLICE_89/C1 (914:1060:1207)(914:1060:1207)) + (INTERCONNECT SLICE_0/Q1 SLICE_121/C1 (914:1060:1207)(914:1060:1207)) (INTERCONNECT SLICE_0/F1 SLICE_0/DI1 (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_0/CLK (2061:2162:2264)(2061:2162:2264)) (INTERCONNECT RCLK_I/PADDI SLICE_1/CLK (2061:2162:2264)(2061:2162:2264)) @@ -3451,24 +3503,26 @@ (INTERCONNECT RCLK_I/PADDI SLICE_12/CLK (2061:2162:2264)(2061:2162:2264)) (INTERCONNECT RCLK_I/PADDI SLICE_12/CLK (2061:2162:2264)(2061:2162:2264)) (INTERCONNECT RCLK_I/PADDI SLICE_16/CLK (2061:2162:2264)(2061:2162:2264)) + (INTERCONNECT RCLK_I/PADDI SLICE_26/CLK (2061:2162:2264)(2061:2162:2264)) + (INTERCONNECT RCLK_I/PADDI SLICE_27/CLK (2061:2162:2264)(2061:2162:2264)) (INTERCONNECT RCLK_I/PADDI SLICE_27/CLK (2061:2162:2264)(2061:2162:2264)) - (INTERCONNECT RCLK_I/PADDI SLICE_28/CLK (2061:2162:2264)(2061:2162:2264)) (INTERCONNECT RCLK_I/PADDI SLICE_28/CLK (2061:2162:2264)(2061:2162:2264)) (INTERCONNECT RCLK_I/PADDI SLICE_29/CLK (2061:2162:2264)(2061:2162:2264)) (INTERCONNECT RCLK_I/PADDI SLICE_30/CLK (2061:2162:2264)(2061:2162:2264)) (INTERCONNECT RCLK_I/PADDI SLICE_31/CLK (2061:2162:2264)(2061:2162:2264)) + (INTERCONNECT RCLK_I/PADDI SLICE_31/CLK (2061:2162:2264)(2061:2162:2264)) (INTERCONNECT RCLK_I/PADDI SLICE_32/CLK (2061:2162:2264)(2061:2162:2264)) (INTERCONNECT RCLK_I/PADDI SLICE_32/CLK (2061:2162:2264)(2061:2162:2264)) (INTERCONNECT RCLK_I/PADDI SLICE_33/CLK (2061:2162:2264)(2061:2162:2264)) - (INTERCONNECT RCLK_I/PADDI SLICE_33/CLK (2061:2162:2264)(2061:2162:2264)) (INTERCONNECT RCLK_I/PADDI SLICE_34/CLK (2061:2162:2264)(2061:2162:2264)) (INTERCONNECT RCLK_I/PADDI SLICE_35/CLK (2061:2162:2264)(2061:2162:2264)) (INTERCONNECT RCLK_I/PADDI SLICE_36/CLK (2061:2162:2264)(2061:2162:2264)) (INTERCONNECT RCLK_I/PADDI SLICE_37/CLK (2061:2162:2264)(2061:2162:2264)) - (INTERCONNECT RCLK_I/PADDI SLICE_38/CLK (2061:2162:2264)(2061:2162:2264)) - (INTERCONNECT RCLK_I/PADDI SLICE_44/CLK (2061:2162:2264)(2061:2162:2264)) + (INTERCONNECT RCLK_I/PADDI SLICE_43/CLK (2061:2162:2264)(2061:2162:2264)) + (INTERCONNECT RCLK_I/PADDI SLICE_45/CLK (2061:2162:2264)(2061:2162:2264)) (INTERCONNECT RCLK_I/PADDI SLICE_46/CLK (2061:2162:2264)(2061:2162:2264)) (INTERCONNECT RCLK_I/PADDI SLICE_47/CLK (2061:2162:2264)(2061:2162:2264)) + (INTERCONNECT RCLK_I/PADDI SLICE_47/CLK (2061:2162:2264)(2061:2162:2264)) (INTERCONNECT RCLK_I/PADDI SLICE_48/CLK (2061:2162:2264)(2061:2162:2264)) (INTERCONNECT RCLK_I/PADDI SLICE_48/CLK (2061:2162:2264)(2061:2162:2264)) (INTERCONNECT RCLK_I/PADDI SLICE_49/CLK (2061:2162:2264)(2061:2162:2264)) @@ -3476,7 +3530,7 @@ (INTERCONNECT RCLK_I/PADDI SLICE_50/CLK (2061:2162:2264)(2061:2162:2264)) (INTERCONNECT RCLK_I/PADDI SLICE_50/CLK (2061:2162:2264)(2061:2162:2264)) (INTERCONNECT RCLK_I/PADDI SLICE_51/CLK (2061:2162:2264)(2061:2162:2264)) - (INTERCONNECT RCLK_I/PADDI SLICE_51/CLK (2061:2162:2264)(2061:2162:2264)) + (INTERCONNECT RCLK_I/PADDI SLICE_52/CLK (2061:2162:2264)(2061:2162:2264)) (INTERCONNECT RCLK_I/PADDI SLICE_52/CLK (2061:2162:2264)(2061:2162:2264)) (INTERCONNECT RCLK_I/PADDI SLICE_53/CLK (2061:2162:2264)(2061:2162:2264)) (INTERCONNECT RCLK_I/PADDI SLICE_53/CLK (2061:2162:2264)(2061:2162:2264)) @@ -3485,11 +3539,9 @@ (INTERCONNECT RCLK_I/PADDI SLICE_55/CLK (2061:2162:2264)(2061:2162:2264)) (INTERCONNECT RCLK_I/PADDI SLICE_55/CLK (2061:2162:2264)(2061:2162:2264)) (INTERCONNECT RCLK_I/PADDI SLICE_56/CLK (2061:2162:2264)(2061:2162:2264)) - (INTERCONNECT RCLK_I/PADDI SLICE_56/CLK (2061:2162:2264)(2061:2162:2264)) (INTERCONNECT RCLK_I/PADDI SLICE_57/CLK (2061:2162:2264)(2061:2162:2264)) (INTERCONNECT RCLK_I/PADDI SLICE_58/CLK (2061:2162:2264)(2061:2162:2264)) - (INTERCONNECT RCLK_I/PADDI SLICE_59/CLK (2061:2162:2264)(2061:2162:2264)) - (INTERCONNECT RCLK_I/PADDI SLICE_76/CLK (2061:2162:2264)(2061:2162:2264)) + (INTERCONNECT RCLK_I/PADDI SLICE_77/CLK (2061:2162:2264)(2061:2162:2264)) (INTERCONNECT RCLK_I/PADDI PHI2_MGIOL/CLK (2208:2322:2436)(2208:2322:2436)) (INTERCONNECT RCLK_I/PADDI nRCAS_MGIOL/CLK (2208:2322:2436)(2208:2322:2436)) (INTERCONNECT RCLK_I/PADDI nRRAS_MGIOL/CLK (2208:2322:2436)(2208:2322:2436)) @@ -3502,201 +3554,212 @@ (2208:2322:2437)) (INTERCONNECT SLICE_0/FCO SLICE_9/FCI (0:0:0)(0:0:0)) (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_1/Q0 SLICE_58/C1 (819:962:1105)(819:962:1105)) - (INTERCONNECT SLICE_1/Q0 SLICE_61/C1 (819:962:1105)(819:962:1105)) - (INTERCONNECT SLICE_1/Q0 SLICE_103/C1 (819:962:1105)(819:962:1105)) - (INTERCONNECT SLICE_1/Q0 SLICE_103/C0 (819:962:1105)(819:962:1105)) + (INTERCONNECT SLICE_1/Q0 SLICE_29/B1 (1166:1327:1489)(1166:1327:1489)) + (INTERCONNECT SLICE_1/Q0 SLICE_58/D1 (1251:1379:1508)(1251:1379:1508)) + (INTERCONNECT SLICE_1/Q0 SLICE_64/A1 (1440:1632:1824)(1440:1632:1824)) + (INTERCONNECT SLICE_1/Q0 SLICE_91/B1 (1166:1327:1489)(1166:1327:1489)) + (INTERCONNECT SLICE_1/Q0 SLICE_94/B0 (1166:1327:1489)(1166:1327:1489)) + (INTERCONNECT SLICE_1/Q0 SLICE_99/B0 (1166:1327:1489)(1166:1327:1489)) (INTERCONNECT SLICE_1/F0 SLICE_1/DI0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_2/FCO SLICE_1/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_2/Q1 SLICE_58/B1 (1493:1691:1890)(1493:1691:1890)) - (INTERCONNECT SLICE_2/Q1 SLICE_61/D1 (1230:1356:1483)(1230:1356:1483)) - (INTERCONNECT SLICE_2/Q1 SLICE_103/B1 (1493:1691:1890)(1493:1691:1890)) - (INTERCONNECT SLICE_2/Q1 SLICE_103/B0 (1493:1691:1890)(1493:1691:1890)) + (INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (481:575:669)(481:575:669)) + (INTERCONNECT SLICE_2/Q1 SLICE_29/C1 (816:960:1105)(816:960:1105)) + (INTERCONNECT SLICE_2/Q1 SLICE_58/B1 (1374:1566:1759)(1374:1566:1759)) + (INTERCONNECT SLICE_2/Q1 SLICE_64/C1 (916:1064:1213)(916:1064:1213)) + (INTERCONNECT SLICE_2/Q1 SLICE_91/C1 (916:1064:1213)(916:1064:1213)) + (INTERCONNECT SLICE_2/Q1 SLICE_94/D0 (1175:1296:1418)(1175:1296:1418)) + (INTERCONNECT SLICE_2/Q1 SLICE_99/D0 (1175:1296:1418)(1175:1296:1418)) (INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_2/Q0 SLICE_58/A1 (1013:1166:1319)(1013:1166:1319)) - (INTERCONNECT SLICE_2/Q0 SLICE_61/A1 (1013:1166:1319)(1013:1166:1319)) - (INTERCONNECT SLICE_2/Q0 SLICE_103/A1 (1013:1166:1319)(1013:1166:1319)) + (INTERCONNECT SLICE_2/Q0 SLICE_29/D1 (903:994:1086)(903:994:1086)) + (INTERCONNECT SLICE_2/Q0 SLICE_64/D1 (1246:1374:1502)(1246:1374:1502)) + (INTERCONNECT SLICE_2/Q0 SLICE_91/D1 (919:1012:1105)(919:1012:1105)) + (INTERCONNECT SLICE_2/Q0 SLICE_94/C0 (930:1078:1226)(930:1078:1226)) + (INTERCONNECT SLICE_2/Q0 SLICE_99/A0 (1129:1287:1446)(1129:1287:1446)) (INTERCONNECT SLICE_2/F1 SLICE_2/DI1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_2/F0 SLICE_2/DI0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_3/FCO SLICE_2/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q1 SLICE_3/A1 (481:575:669)(481:575:669)) - (INTERCONNECT SLICE_3/Q1 SLICE_30/C1 (1006:1165:1324)(1006:1165:1324)) - (INTERCONNECT SLICE_3/Q1 SLICE_57/D1 (995:1099:1203)(995:1099:1203)) - (INTERCONNECT SLICE_3/Q1 SLICE_58/B0 (1237:1409:1581)(1237:1409:1581)) - (INTERCONNECT SLICE_3/Q1 SLICE_65/D1 (1370:1506:1643)(1370:1506:1643)) - (INTERCONNECT SLICE_3/Q1 SLICE_67/D0 (1380:1517:1655)(1380:1517:1655)) - (INTERCONNECT SLICE_3/Q1 SLICE_70/C1 (557:674:792)(557:674:792)) - (INTERCONNECT SLICE_3/Q1 SLICE_71/D1 (1380:1517:1655)(1380:1517:1655)) - (INTERCONNECT SLICE_3/Q1 SLICE_72/D1 (916:1010:1105)(916:1010:1105)) - (INTERCONNECT SLICE_3/Q1 SLICE_77/D1 (1370:1506:1643)(1370:1506:1643)) - (INTERCONNECT SLICE_3/Q1 SLICE_82/B0 (788:918:1049)(788:918:1049)) - (INTERCONNECT SLICE_3/Q1 SLICE_84/C1 (927:1076:1226)(927:1076:1226)) - (INTERCONNECT SLICE_3/Q1 SLICE_86/A1 (1630:1824:2018)(1630:1824:2018)) - (INTERCONNECT SLICE_3/Q1 SLICE_99/D1 (1380:1517:1655)(1380:1517:1655)) - (INTERCONNECT SLICE_3/Q1 SLICE_99/D0 (1380:1517:1655)(1380:1517:1655)) - (INTERCONNECT SLICE_3/Q1 SLICE_100/A1 (1928:2168:2408)(1928:2168:2408)) - (INTERCONNECT SLICE_3/Q1 SLICE_100/A0 (1928:2168:2408)(1928:2168:2408)) - (INTERCONNECT SLICE_3/Q1 SLICE_107/D1 (1370:1506:1643)(1370:1506:1643)) + (INTERCONNECT SLICE_3/Q1 SLICE_3/A1 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_3/Q1 SLICE_56/D1 (544:604:665)(544:604:665)) + (INTERCONNECT SLICE_3/Q1 SLICE_61/A1 (1502:1702:1902)(1502:1702:1902)) + (INTERCONNECT SLICE_3/Q1 SLICE_61/A0 (1502:1702:1902)(1502:1702:1902)) + (INTERCONNECT SLICE_3/Q1 SLICE_67/A0 (1529:1722:1916)(1529:1722:1916)) + (INTERCONNECT SLICE_3/Q1 SLICE_73/A1 (1529:1722:1916)(1529:1722:1916)) + (INTERCONNECT SLICE_3/Q1 SLICE_74/D1 (1646:1809:1972)(1646:1809:1972)) + (INTERCONNECT SLICE_3/Q1 SLICE_84/D1 (944:1039:1135)(944:1039:1135)) + (INTERCONNECT SLICE_3/Q1 SLICE_85/D1 (1683:1842:2002)(1683:1842:2002)) + (INTERCONNECT SLICE_3/Q1 SLICE_88/D1 (1314:1441:1569)(1314:1441:1569)) + (INTERCONNECT SLICE_3/Q1 SLICE_94/A1 (1502:1702:1902)(1502:1702:1902)) + (INTERCONNECT SLICE_3/Q1 SLICE_98/A0 (1851:2079:2307)(1851:2079:2307)) + (INTERCONNECT SLICE_3/Q1 SLICE_99/D1 (944:1039:1135)(944:1039:1135)) + (INTERCONNECT SLICE_3/Q1 SLICE_102/D1 (914:1006:1099)(914:1006:1099)) + (INTERCONNECT SLICE_3/Q1 SLICE_102/D0 (914:1006:1099)(914:1006:1099)) + (INTERCONNECT SLICE_3/Q1 SLICE_105/D0 (1308:1435:1562)(1308:1435:1562)) + (INTERCONNECT SLICE_3/Q1 SLICE_107/C1 (1330:1513:1696)(1330:1513:1696)) + (INTERCONNECT SLICE_3/Q1 SLICE_107/C0 (1330:1513:1696)(1330:1513:1696)) + (INTERCONNECT SLICE_3/Q1 SLICE_118/D1 (944:1039:1135)(944:1039:1135)) (INTERCONNECT SLICE_3/Q0 SLICE_3/A0 (481:575:669)(481:575:669)) - (INTERCONNECT SLICE_3/Q0 SLICE_30/B1 (1478:1671:1864)(1478:1671:1864)) - (INTERCONNECT SLICE_3/Q0 SLICE_57/C1 (1247:1427:1607)(1247:1427:1607)) - (INTERCONNECT SLICE_3/Q0 SLICE_60/D1 (2307:2531:2756)(2307:2531:2756)) - (INTERCONNECT SLICE_3/Q0 SLICE_60/C0 (1991:2235:2480)(1991:2235:2480)) - (INTERCONNECT SLICE_3/Q0 SLICE_63/A1 (2580:2869:3158)(2580:2869:3158)) - (INTERCONNECT SLICE_3/Q0 SLICE_65/A1 (2580:2869:3158)(2580:2869:3158)) - (INTERCONNECT SLICE_3/Q0 SLICE_65/A0 (2580:2869:3158)(2580:2869:3158)) - (INTERCONNECT SLICE_3/Q0 SLICE_66/A0 (1200:1369:1538)(1200:1369:1538)) - (INTERCONNECT SLICE_3/Q0 SLICE_67/B0 (1923:2161:2399)(1923:2161:2399)) - (INTERCONNECT SLICE_3/Q0 SLICE_70/A1 (1522:1725:1929)(1522:1725:1929)) - (INTERCONNECT SLICE_3/Q0 SLICE_71/C0 (2708:3021:3335)(2708:3021:3335)) - (INTERCONNECT SLICE_3/Q0 SLICE_72/A1 (2560:2847:3134)(2560:2847:3134)) - (INTERCONNECT SLICE_3/Q0 SLICE_82/D0 (1323:1463:1603)(1323:1463:1603)) - (INTERCONNECT SLICE_3/Q0 SLICE_85/B1 (1559:1765:1972)(1559:1765:1972)) - (INTERCONNECT SLICE_3/Q0 SLICE_86/D1 (1317:1455:1594)(1317:1455:1594)) - (INTERCONNECT SLICE_3/Q0 SLICE_88/A0 (1533:1738:1944)(1533:1738:1944)) - (INTERCONNECT SLICE_3/Q0 SLICE_94/C0 (2688:2999:3311)(2688:2999:3311)) - (INTERCONNECT SLICE_3/Q0 SLICE_99/C1 (1698:1924:2151)(1698:1924:2151)) - (INTERCONNECT SLICE_3/Q0 SLICE_99/C0 (2745:3055:3365)(2745:3055:3365)) - (INTERCONNECT SLICE_3/Q0 SLICE_100/C1 (1698:1924:2151)(1698:1924:2151)) - (INTERCONNECT SLICE_3/Q0 SLICE_107/B1 (3309:3667:4026)(3309:3667:4026)) - (INTERCONNECT SLICE_3/Q0 SLICE_107/C0 (2751:3061:3372)(2751:3061:3372)) + (INTERCONNECT SLICE_3/Q0 SLICE_56/C1 (991:1148:1306)(991:1148:1306)) + (INTERCONNECT SLICE_3/Q0 wb_dati_5_1_iv_0_0_o2\[5\]\/SLICE_59/A0 (1945:2178:2412) + (1945:2178:2412)) + (INTERCONNECT SLICE_3/Q0 wb_adr_5_i_0_1\[0\]\/SLICE_60/A1 (1210:1380:1550) + (1210:1380:1550)) + (INTERCONNECT SLICE_3/Q0 SLICE_61/B0 (1939:2178:2418)(1939:2178:2418)) + (INTERCONNECT SLICE_3/Q0 SLICE_65/D0 (551:614:677)(551:614:677)) + (INTERCONNECT SLICE_3/Q0 SLICE_72/C0 (1381:1572:1764)(1381:1572:1764)) + (INTERCONNECT SLICE_3/Q0 SLICE_74/A1 (1570:1771:1972)(1570:1771:1972)) + (INTERCONNECT SLICE_3/Q0 SLICE_84/D0 (1730:1897:2065)(1730:1897:2065)) + (INTERCONNECT SLICE_3/Q0 SLICE_85/A0 (1945:2178:2412)(1945:2178:2412)) + (INTERCONNECT SLICE_3/Q0 SLICE_87/A0 (1945:2178:2412)(1945:2178:2412)) + (INTERCONNECT SLICE_3/Q0 SLICE_93/C0 (1381:1572:1764)(1381:1572:1764)) + (INTERCONNECT SLICE_3/Q0 SLICE_97/C0 (1375:1566:1757)(1375:1566:1757)) + (INTERCONNECT SLICE_3/Q0 SLICE_98/D1 (1285:1411:1538)(1285:1411:1538)) + (INTERCONNECT SLICE_3/Q0 SLICE_102/C1 (1698:1923:2149)(1698:1923:2149)) + (INTERCONNECT SLICE_3/Q0 SLICE_102/B0 (1939:2178:2418)(1939:2178:2418)) + (INTERCONNECT SLICE_3/Q0 SLICE_104/D1 (551:614:677)(551:614:677)) + (INTERCONNECT SLICE_3/Q0 SLICE_104/D0 (551:614:677)(551:614:677)) + (INTERCONNECT SLICE_3/Q0 SLICE_105/A1 (1210:1380:1550)(1210:1380:1550)) + (INTERCONNECT SLICE_3/Q0 SLICE_105/A0 (1210:1380:1550)(1210:1380:1550)) + (INTERCONNECT SLICE_3/Q0 SLICE_107/B0 (1972:2207:2443)(1972:2207:2443)) + (INTERCONNECT SLICE_3/Q0 SLICE_118/B0 (1163:1326:1489)(1163:1326:1489)) (INTERCONNECT SLICE_3/F1 SLICE_3/DI1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_3/F0 SLICE_3/DI0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_4/FCO SLICE_3/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/Q1 SLICE_4/A1 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_4/Q1 SLICE_34/C0 (539:652:765)(539:652:765)) - (INTERCONNECT SLICE_4/Q1 SLICE_48/C1 (2283:2565:2848)(2283:2565:2848)) - (INTERCONNECT SLICE_4/Q1 SLICE_57/B1 (1442:1638:1834)(1442:1638:1834)) - (INTERCONNECT SLICE_4/Q1 SLICE_63/B0 (1817:2045:2274)(1817:2045:2274)) - (INTERCONNECT SLICE_4/Q1 SLICE_65/B0 (1442:1638:1834)(1442:1638:1834)) - (INTERCONNECT SLICE_4/Q1 SLICE_66/A1 (1785:2011:2237)(1785:2011:2237)) - (INTERCONNECT SLICE_4/Q1 SLICE_69/B0 (1447:1643:1840)(1447:1643:1840)) - (INTERCONNECT SLICE_4/Q1 SLICE_70/B1 (1447:1643:1840)(1447:1643:1840)) - (INTERCONNECT SLICE_4/Q1 SLICE_72/C0 (1918:2170:2422)(1918:2170:2422)) - (INTERCONNECT SLICE_4/Q1 SLICE_80/A0 (1035:1196:1357)(1035:1196:1357)) - (INTERCONNECT SLICE_4/Q1 SLICE_82/D1 (1575:1735:1896)(1575:1735:1896)) - (INTERCONNECT SLICE_4/Q1 SLICE_83/B1 (1857:2097:2337)(1857:2097:2337)) - (INTERCONNECT SLICE_4/Q1 SLICE_85/D1 (1615:1787:1959)(1615:1787:1959)) - (INTERCONNECT SLICE_4/Q1 SLICE_86/D0 (1923:2122:2322)(1923:2122:2322)) - (INTERCONNECT SLICE_4/Q1 SLICE_94/A0 (2117:2379:2642)(2117:2379:2642)) - (INTERCONNECT SLICE_4/Q1 SLICE_98/D1 (825:920:1016)(825:920:1016)) - (INTERCONNECT SLICE_4/Q1 SLICE_98/D0 (825:920:1016)(825:920:1016)) - (INTERCONNECT SLICE_4/Q1 SLICE_100/B1 (1857:2097:2337)(1857:2097:2337)) - (INTERCONNECT SLICE_4/Q1 SLICE_100/B0 (1067:1230:1394)(1067:1230:1394)) - (INTERCONNECT SLICE_4/Q1 SLICE_101/A1 (2133:2398:2663)(2133:2398:2663)) - (INTERCONNECT SLICE_4/Q1 SLICE_101/A0 (2133:2398:2663)(2133:2398:2663)) - (INTERCONNECT SLICE_4/Q1 SLICE_107/B0 (2187:2447:2708)(2187:2447:2708)) - (INTERCONNECT SLICE_4/Q0 SLICE_4/A0 (481:575:669)(481:575:669)) - (INTERCONNECT SLICE_4/Q0 SLICE_34/B0 (1413:1608:1803)(1413:1608:1803)) - (INTERCONNECT SLICE_4/Q0 SLICE_48/B1 (1413:1608:1803)(1413:1608:1803)) - (INTERCONNECT SLICE_4/Q0 SLICE_48/B0 (1413:1608:1803)(1413:1608:1803)) - (INTERCONNECT SLICE_4/Q0 SLICE_65/D0 (1380:1517:1655)(1380:1517:1655)) - (INTERCONNECT SLICE_4/Q0 SLICE_66/D1 (1005:1110:1215)(1005:1110:1215)) - (INTERCONNECT SLICE_4/Q0 SLICE_66/D0 (1005:1110:1215)(1005:1110:1215)) - (INTERCONNECT SLICE_4/Q0 SLICE_69/D1 (1755:1925:2095)(1755:1925:2095)) - (INTERCONNECT SLICE_4/Q0 SLICE_70/D1 (1233:1363:1494)(1233:1363:1494)) - (INTERCONNECT SLICE_4/Q0 SLICE_71/A0 (1590:1793:1996)(1590:1793:1996)) - (INTERCONNECT SLICE_4/Q0 SLICE_72/D0 (2119:2320:2522)(2119:2320:2522)) - (INTERCONNECT SLICE_4/Q0 SLICE_80/C0 (1386:1578:1770)(1386:1578:1770)) - (INTERCONNECT SLICE_4/Q0 SLICE_82/A1 (1195:1363:1532)(1195:1363:1532)) - (INTERCONNECT SLICE_4/Q0 SLICE_83/D1 (1005:1110:1215)(1005:1110:1215)) - (INTERCONNECT SLICE_4/Q0 SLICE_88/C0 (1323:1516:1709)(1323:1516:1709)) - (INTERCONNECT SLICE_4/Q0 SLICE_94/D0 (1560:1725:1891)(1560:1725:1891)) - (INTERCONNECT SLICE_4/Q0 SLICE_98/A0 (1559:1759:1959)(1559:1759:1959)) - (INTERCONNECT SLICE_4/Q0 SLICE_100/D1 (1755:1925:2095)(1755:1925:2095)) - (INTERCONNECT SLICE_4/Q0 SLICE_100/D0 (1375:1512:1649)(1375:1512:1649)) - (INTERCONNECT SLICE_4/Q0 SLICE_101/D1 (1005:1110:1215)(1005:1110:1215)) - (INTERCONNECT SLICE_4/Q0 SLICE_101/B0 (1574:1782:1990)(1574:1782:1990)) + (INTERCONNECT SLICE_4/Q1 SLICE_4/A1 (481:575:669)(481:575:669)) + (INTERCONNECT SLICE_4/Q1 SLICE_56/A1 (1078:1240:1403)(1078:1240:1403)) + (INTERCONNECT SLICE_4/Q1 wb_dati_5_1_iv_0_0_o2\[5\]\/SLICE_59/A1 (1651:1847:2043) + (1651:1847:2043)) + (INTERCONNECT SLICE_4/Q1 SLICE_67/B0 (1564:1771:1978)(1564:1771:1978)) + (INTERCONNECT SLICE_4/Q1 SLICE_71/A0 (1205:1374:1544)(1205:1374:1544)) + (INTERCONNECT SLICE_4/Q1 SLICE_72/A0 (1575:1776:1978)(1575:1776:1978)) + (INTERCONNECT SLICE_4/Q1 SLICE_73/D0 (1816:1979:2142)(1816:1979:2142)) + (INTERCONNECT SLICE_4/Q1 SLICE_74/C1 (2154:2407:2660)(2154:2407:2660)) + (INTERCONNECT SLICE_4/Q1 SLICE_84/A1 (1126:1286:1446)(1126:1286:1446)) + (INTERCONNECT SLICE_4/Q1 SLICE_85/B1 (1683:1881:2080)(1683:1881:2080)) + (INTERCONNECT SLICE_4/Q1 SLICE_86/B1 (2374:2639:2904)(2374:2639:2904)) + (INTERCONNECT SLICE_4/Q1 SLICE_93/D0 (1692:1863:2034)(1692:1863:2034)) + (INTERCONNECT SLICE_4/Q1 SLICE_98/C0 (1452:1637:1823)(1452:1637:1823)) + (INTERCONNECT SLICE_4/Q1 SLICE_102/B1 (2385:2651:2917)(2385:2651:2917)) + (INTERCONNECT SLICE_4/Q1 SLICE_102/A0 (1569:1770:1971)(1569:1770:1971)) + (INTERCONNECT SLICE_4/Q1 SLICE_105/B1 (1575:1784:1993)(1575:1784:1993)) + (INTERCONNECT SLICE_4/Q1 SLICE_105/B0 (1575:1784:1993)(1575:1784:1993)) + (INTERCONNECT SLICE_4/Q1 SLICE_118/A1 (1126:1286:1446)(1126:1286:1446)) + (INTERCONNECT SLICE_4/Q1 SLICE_118/A0 (1126:1286:1446)(1126:1286:1446)) + (INTERCONNECT SLICE_4/Q0 SLICE_4/A0 (483:579:675)(483:579:675)) + (INTERCONNECT SLICE_4/Q0 SLICE_33/A1 (758:888:1018)(758:888:1018)) + (INTERCONNECT SLICE_4/Q0 SLICE_52/A1 (1518:1714:1910)(1518:1714:1910)) + (INTERCONNECT SLICE_4/Q0 SLICE_55/C0 (1271:1459:1647)(1271:1459:1647)) + (INTERCONNECT SLICE_4/Q0 wb_adr_5_i_0_1\[0\]\/SLICE_60/M0 (1268:1386:1505) + (1268:1386:1505)) + (INTERCONNECT SLICE_4/Q0 SLICE_65/A0 (758:888:1018)(758:888:1018)) + (INTERCONNECT SLICE_4/Q0 SLICE_66/A1 (1143:1306:1470)(1143:1306:1470)) + (INTERCONNECT SLICE_4/Q0 SLICE_70/B0 (1872:2105:2338)(1872:2105:2338)) + (INTERCONNECT SLICE_4/Q0 SLICE_71/D0 (1297:1426:1556)(1297:1426:1556)) + (INTERCONNECT SLICE_4/Q0 SLICE_72/B1 (1588:1791:1994)(1588:1791:1994)) + (INTERCONNECT SLICE_4/Q0 SLICE_74/A0 (1143:1306:1470)(1143:1306:1470)) + (INTERCONNECT SLICE_4/Q0 SLICE_84/A0 (1143:1306:1470)(1143:1306:1470)) + (INTERCONNECT SLICE_4/Q0 SLICE_85/A1 (1518:1714:1910)(1518:1714:1910)) + (INTERCONNECT SLICE_4/Q0 SLICE_86/D1 (1672:1834:1996)(1672:1834:1996)) + (INTERCONNECT SLICE_4/Q0 SLICE_88/A0 (1192:1361:1530)(1192:1361:1530)) + (INTERCONNECT SLICE_4/Q0 SLICE_97/A0 (1143:1306:1470)(1143:1306:1470)) + (INTERCONNECT SLICE_4/Q0 SLICE_98/C1 (993:1151:1310)(993:1151:1310)) + (INTERCONNECT SLICE_4/Q0 SLICE_99/A1 (1143:1306:1470)(1143:1306:1470)) + (INTERCONNECT SLICE_4/Q0 SLICE_102/A1 (1143:1306:1470)(1143:1306:1470)) + (INTERCONNECT SLICE_4/Q0 SLICE_104/A1 (758:888:1018)(758:888:1018)) + (INTERCONNECT SLICE_4/Q0 SLICE_104/A0 (758:888:1018)(758:888:1018)) (INTERCONNECT SLICE_4/F1 SLICE_4/DI1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_4/F0 SLICE_4/DI0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_5/FCO SLICE_4/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_5/Q1 SLICE_5/A1 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_5/Q1 SLICE_34/D0 (871:966:1062)(871:966:1062)) - (INTERCONNECT SLICE_5/Q1 SLICE_66/B0 (1595:1813:2031)(1595:1813:2031)) - (INTERCONNECT SLICE_5/Q1 SLICE_69/A0 (1938:2186:2434)(1938:2186:2434)) - (INTERCONNECT SLICE_5/Q1 SLICE_70/C0 (2066:2338:2611)(2066:2338:2611)) - (INTERCONNECT SLICE_5/Q1 SLICE_71/D0 (1353:1503:1653)(1353:1503:1653)) - (INTERCONNECT SLICE_5/Q1 SLICE_72/A0 (1938:2186:2434)(1938:2186:2434)) - (INTERCONNECT SLICE_5/Q1 SLICE_79/D1 (2098:2312:2527)(2098:2312:2527)) - (INTERCONNECT SLICE_5/Q1 SLICE_80/A1 (1124:1282:1440)(1124:1282:1440)) - (INTERCONNECT SLICE_5/Q1 SLICE_83/A1 (1938:2186:2434)(1938:2186:2434)) - (INTERCONNECT SLICE_5/Q1 SLICE_88/D0 (2425:2674:2924)(2425:2674:2924)) - (INTERCONNECT SLICE_5/Q1 SLICE_94/A1 (1938:2186:2434)(1938:2186:2434)) - (INTERCONNECT SLICE_5/Q1 SLICE_98/C1 (1686:1926:2167)(1686:1926:2167)) - (INTERCONNECT SLICE_5/Q1 SLICE_98/C0 (1686:1926:2167)(1686:1926:2167)) - (INTERCONNECT SLICE_5/Q1 SLICE_100/C0 (1252:1434:1617)(1252:1434:1617)) - (INTERCONNECT SLICE_5/Q1 SLICE_103/D1 (1664:1847:2031)(1664:1847:2031)) + (INTERCONNECT SLICE_5/Q1 SLICE_5/A1 (483:579:675)(483:579:675)) + (INTERCONNECT SLICE_5/Q1 SLICE_33/D1 (543:607:671)(543:607:671)) + (INTERCONNECT SLICE_5/Q1 wb_adr_5_i_0_1\[0\]\/SLICE_60/B0 (1535:1732:1929) + (1535:1732:1929)) + (INTERCONNECT SLICE_5/Q1 SLICE_65/B1 (800:933:1067)(800:933:1067)) + (INTERCONNECT SLICE_5/Q1 SLICE_65/B0 (800:933:1067)(800:933:1067)) + (INTERCONNECT SLICE_5/Q1 SLICE_66/B1 (1165:1330:1495)(1165:1330:1495)) + (INTERCONNECT SLICE_5/Q1 SLICE_70/A0 (1830:2059:2289)(1830:2059:2289)) + (INTERCONNECT SLICE_5/Q1 SLICE_71/C1 (1298:1481:1665)(1298:1481:1665)) + (INTERCONNECT SLICE_5/Q1 SLICE_72/C1 (1362:1552:1743)(1362:1552:1743)) + (INTERCONNECT SLICE_5/Q1 SLICE_74/D0 (933:1031:1129)(933:1031:1129)) + (INTERCONNECT SLICE_5/Q1 SLICE_81/C1 (998:1157:1316)(998:1157:1316)) + (INTERCONNECT SLICE_5/Q1 SLICE_82/A1 (1143:1306:1470)(1143:1306:1470)) + (INTERCONNECT SLICE_5/Q1 SLICE_85/C1 (998:1157:1316)(998:1157:1316)) + (INTERCONNECT SLICE_5/Q1 SLICE_97/B1 (1175:1341:1507)(1175:1341:1507)) + (INTERCONNECT SLICE_5/Q1 SLICE_98/D0 (987:1091:1195)(987:1091:1195)) + (INTERCONNECT SLICE_5/Q1 SLICE_99/C0 (1261:1448:1635)(1261:1448:1635)) + (INTERCONNECT SLICE_5/Q1 SLICE_104/B1 (800:933:1067)(800:933:1067)) + (INTERCONNECT SLICE_5/Q1 SLICE_104/B0 (800:933:1067)(800:933:1067)) (INTERCONNECT SLICE_5/Q0 SLICE_5/A0 (481:575:669)(481:575:669)) - (INTERCONNECT SLICE_5/Q0 SLICE_60/C1 (1001:1159:1318)(1001:1159:1318)) - (INTERCONNECT SLICE_5/Q0 SLICE_66/C1 (1001:1159:1318)(1001:1159:1318)) - (INTERCONNECT SLICE_5/Q0 SLICE_69/D0 (990:1093:1197)(990:1093:1197)) - (INTERCONNECT SLICE_5/Q0 SLICE_70/A0 (1200:1369:1538)(1200:1369:1538)) - (INTERCONNECT SLICE_5/Q0 SLICE_71/B0 (1596:1799:2002)(1596:1799:2002)) - (INTERCONNECT SLICE_5/Q0 SLICE_72/B0 (1049:1212:1376)(1049:1212:1376)) - (INTERCONNECT SLICE_5/Q0 SLICE_79/B1 (772:900:1028)(772:900:1028)) - (INTERCONNECT SLICE_5/Q0 SLICE_80/B1 (1413:1608:1803)(1413:1608:1803)) - (INTERCONNECT SLICE_5/Q0 SLICE_83/C1 (1001:1159:1318)(1001:1159:1318)) - (INTERCONNECT SLICE_5/Q0 SLICE_88/A1 (1200:1369:1538)(1200:1369:1538)) - (INTERCONNECT SLICE_5/Q0 SLICE_94/D1 (807:902:998)(807:902:998)) - (INTERCONNECT SLICE_5/Q0 SLICE_98/B1 (1602:1805:2009)(1602:1805:2009)) - (INTERCONNECT SLICE_5/Q0 SLICE_98/B0 (1602:1805:2009)(1602:1805:2009)) + (INTERCONNECT SLICE_5/Q0 SLICE_33/B1 (1110:1275:1440)(1110:1275:1440)) + (INTERCONNECT SLICE_5/Q0 SLICE_54/D0 (812:908:1004)(812:908:1004)) + (INTERCONNECT SLICE_5/Q0 wb_dati_5_1_iv_0_0_o2\[5\]\/SLICE_59/M0 (1474:1625:1777) + (1474:1625:1777)) + (INTERCONNECT SLICE_5/Q0 wb_adr_5_i_0_1\[0\]\/SLICE_60/C0 (1624:1841:2059) + (1624:1841:2059)) + (INTERCONNECT SLICE_5/Q0 SLICE_65/C1 (1161:1349:1537)(1161:1349:1537)) + (INTERCONNECT SLICE_5/Q0 SLICE_66/C1 (1208:1392:1577)(1208:1392:1577)) + (INTERCONNECT SLICE_5/Q0 SLICE_67/B1 (1517:1710:1904)(1517:1710:1904)) + (INTERCONNECT SLICE_5/Q0 SLICE_70/C0 (1624:1841:2059)(1624:1841:2059)) + (INTERCONNECT SLICE_5/Q0 SLICE_71/A1 (1376:1568:1760)(1376:1568:1760)) + (INTERCONNECT SLICE_5/Q0 SLICE_72/D1 (1530:1688:1846)(1530:1688:1846)) + (INTERCONNECT SLICE_5/Q0 SLICE_73/A0 (1407:1602:1797)(1407:1602:1797)) + (INTERCONNECT SLICE_5/Q0 SLICE_74/B0 (1439:1636:1834)(1439:1636:1834)) + (INTERCONNECT SLICE_5/Q0 SLICE_82/C1 (1208:1392:1577)(1208:1392:1577)) + (INTERCONNECT SLICE_5/Q0 SLICE_87/C1 (1193:1376:1559)(1193:1376:1559)) + (INTERCONNECT SLICE_5/Q0 SLICE_97/D1 (1197:1326:1456)(1197:1326:1456)) + (INTERCONNECT SLICE_5/Q0 SLICE_104/C1 (1161:1349:1537)(1161:1349:1537)) (INTERCONNECT SLICE_5/F1 SLICE_5/DI1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_5/F0 SLICE_5/DI0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_6/FCO SLICE_5/FCI (0:0:0)(0:0:0)) (INTERCONNECT SLICE_6/Q1 SLICE_6/A1 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_6/Q1 SLICE_91/D0 (526:578:630)(526:578:630)) + (INTERCONNECT SLICE_6/Q1 SLICE_121/C0 (871:1020:1170)(871:1020:1170)) (INTERCONNECT SLICE_6/Q0 SLICE_6/A0 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_6/Q0 SLICE_91/C1 (544:658:773)(544:658:773)) + (INTERCONNECT SLICE_6/Q0 SLICE_95/B1 (1034:1188:1343)(1034:1188:1343)) (INTERCONNECT SLICE_6/F1 SLICE_6/DI1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_6/F0 SLICE_6/DI0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_7/FCO SLICE_6/FCI (0:0:0)(0:0:0)) (INTERCONNECT SLICE_7/Q1 SLICE_7/A1 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_7/Q1 SLICE_91/D1 (533:592:652)(533:592:652)) + (INTERCONNECT SLICE_7/Q1 SLICE_121/D0 (897:988:1079)(897:988:1079)) (INTERCONNECT SLICE_7/Q0 SLICE_7/A0 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_7/Q0 SLICE_34/C1 (803:944:1086)(803:944:1086)) + (INTERCONNECT SLICE_7/Q0 SLICE_95/D0 (967:1065:1164)(967:1065:1164)) (INTERCONNECT SLICE_7/F1 SLICE_7/DI1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_7/F0 SLICE_7/DI0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_8/FCO SLICE_7/FCI (0:0:0)(0:0:0)) (INTERCONNECT SLICE_8/Q1 SLICE_8/A1 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_8/Q1 SLICE_34/A1 (743:868:993)(743:868:993)) + (INTERCONNECT SLICE_8/Q1 SLICE_95/A0 (1070:1230:1390)(1070:1230:1390)) (INTERCONNECT SLICE_8/Q0 SLICE_8/A0 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_8/Q0 SLICE_91/B0 (1102:1264:1427)(1102:1264:1427)) + (INTERCONNECT SLICE_8/Q0 SLICE_121/A0 (1107:1263:1420)(1107:1263:1420)) (INTERCONNECT SLICE_8/F1 SLICE_8/DI1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_8/F0 SLICE_8/DI0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_9/FCO SLICE_8/FCI (0:0:0)(0:0:0)) (INTERCONNECT SLICE_9/Q1 SLICE_9/A1 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_9/Q1 SLICE_34/B1 (775:902:1030)(775:902:1030)) + (INTERCONNECT SLICE_9/Q1 SLICE_95/B0 (775:902:1030)(775:902:1030)) (INTERCONNECT SLICE_9/Q0 SLICE_9/A0 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_9/Q0 SLICE_34/D1 (860:954:1049)(860:954:1049)) + (INTERCONNECT SLICE_9/Q0 SLICE_95/A1 (1177:1341:1505)(1177:1341:1505)) (INTERCONNECT SLICE_9/F1 SLICE_9/DI1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_9/F0 SLICE_9/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT MAin\[1\]_I/PADDI SLICE_10/C1 (2061:2277:2494)(2061:2277:2494)) - (INTERCONNECT MAin\[1\]_I/PADDI SLICE_11/D1 (2779:3003:3228)(2779:3003:3228)) - (INTERCONNECT MAin\[1\]_I/PADDI SLICE_11/D0 (2779:3003:3228)(2779:3003:3228)) - (INTERCONNECT MAin\[1\]_I/PADDI SLICE_23/B1 (2271:2498:2726)(2271:2498:2726)) - (INTERCONNECT MAin\[1\]_I/PADDI SLICE_39/B1 (2287:2516:2745)(2287:2516:2745)) - (INTERCONNECT MAin\[1\]_I/PADDI SLICE_64/D0 (2377:2573:2770)(2377:2573:2770)) - (INTERCONNECT MAin\[1\]_I/PADDI SLICE_73/B1 (2619:2883:3148)(2619:2883:3148)) - (INTERCONNECT MAin\[1\]_I/PADDI SLICE_74/D0 (2736:2963:3191)(2736:2963:3191)) - (INTERCONNECT MAin\[1\]_I/PADDI SLICE_76/C1 (2061:2277:2494)(2061:2277:2494)) - (INTERCONNECT MAin\[1\]_I/PADDI SLICE_106/C1 (2061:2277:2494)(2061:2277:2494)) - (INTERCONNECT MAin\[1\]_I/PADDI SLICE_112/A1 (2255:2481:2708)(2255:2481:2708)) - (INTERCONNECT SLICE_75/F1 SLICE_10/A1 (1131:1293:1456)(1131:1293:1456)) - (INTERCONNECT SLICE_75/F1 SLICE_11/C1 (932:1084:1236)(932:1084:1236)) - (INTERCONNECT SLICE_75/F1 SLICE_11/C0 (932:1084:1236)(932:1084:1236)) - (INTERCONNECT SLICE_75/F1 SLICE_17/D1 (911:1007:1103)(911:1007:1103)) - (INTERCONNECT SLICE_75/F1 SLICE_23/A1 (481:577:673)(481:577:673)) - (INTERCONNECT SLICE_75/F1 SLICE_75/B0 (513:611:710)(513:611:710)) - (INTERCONNECT SLICE_75/F1 SLICE_76/D0 (921:1018:1115)(921:1018:1115)) - (INTERCONNECT SLICE_75/F1 SLICE_106/A1 (1121:1282:1444)(1121:1282:1444)) - (INTERCONNECT SLICE_10/Q0 SLICE_10/D0 (523:578:633)(523:578:633)) - (INTERCONNECT SLICE_10/Q0 SLICE_76/C0 (534:644:754)(534:644:754)) - (INTERCONNECT SLICE_73/F0 SLICE_10/C0 (537:645:753)(537:645:753)) - (INTERCONNECT SLICE_73/F0 SLICE_17/B0 (765:889:1013)(765:889:1013)) - (INTERCONNECT SLICE_11/F1 SLICE_10/B0 (511:606:702)(511:606:702)) - (INTERCONNECT SLICE_11/F1 SLICE_11/B0 (511:606:702)(511:606:702)) - (INTERCONNECT SLICE_10/F1 SLICE_10/A0 (730:848:967)(730:848:967)) + (INTERCONNECT SLICE_80/F0 SLICE_10/C1 (562:676:791)(562:676:791)) + (INTERCONNECT SLICE_80/F0 SLICE_11/B1 (793:920:1048)(793:920:1048)) + (INTERCONNECT SLICE_80/F0 SLICE_11/B0 (793:920:1048)(793:920:1048)) + (INTERCONNECT SLICE_80/F0 SLICE_17/A1 (761:886:1011)(761:886:1011)) + (INTERCONNECT SLICE_80/F0 SLICE_23/D1 (921:1012:1104)(921:1012:1104)) + (INTERCONNECT SLICE_80/F0 SLICE_76/A0 (1131:1288:1445)(1131:1288:1445)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_10/B1 (2078:2300:2522)(2078:2300:2522)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_11/D1 (2184:2377:2570)(2184:2377:2570)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_11/D0 (2184:2377:2570)(2184:2377:2570)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_17/D1 (2184:2377:2570)(2184:2377:2570)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_23/A1 (2056:2276:2497)(2056:2276:2497)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_38/D1 (2631:2862:3093)(2631:2862:3093)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_63/A0 (2056:2276:2497)(2056:2276:2497)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_76/B1 (2415:2673:2931)(2415:2673:2931)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_114/D0 (3359:3653:3947)(3359:3653:3947)) + (INTERCONNECT SLICE_17/F1 SLICE_10/D0 (269:296:324)(269:296:324)) + (INTERCONNECT SLICE_17/F1 SLICE_17/D0 (523:579:635)(523:579:635)) + (INTERCONNECT SLICE_10/F1 SLICE_10/C0 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_11/F1 SLICE_10/B0 (776:902:1028)(776:902:1028)) + (INTERCONNECT SLICE_11/F1 SLICE_11/A0 (744:867:991)(744:867:991)) + (INTERCONNECT SLICE_11/F1 SLICE_33/C0 (537:645:753)(537:645:753)) + (INTERCONNECT SLICE_10/Q0 SLICE_10/A0 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_10/Q0 SLICE_33/B0 (768:888:1008)(768:888:1008)) (INTERCONNECT SLICE_10/F0 SLICE_10/DI0 (0:0:0)(0:0:0)) (INTERCONNECT PHI2_I/PADDI SLICE_10/CLK (3649:3922:4196)(3649:3922:4196)) (INTERCONNECT PHI2_I/PADDI SLICE_11/CLK (3649:3922:4196)(3649:3922:4196)) @@ -3708,7 +3771,7 @@ (INTERCONNECT PHI2_I/PADDI SLICE_22/CLK (3649:3922:4196)(3649:3922:4196)) (INTERCONNECT PHI2_I/PADDI SLICE_23/CLK (3649:3922:4196)(3649:3922:4196)) (INTERCONNECT PHI2_I/PADDI SLICE_24/CLK (3649:3922:4196)(3649:3922:4196)) - (INTERCONNECT PHI2_I/PADDI SLICE_45/CLK (3649:3922:4196)(3649:3922:4196)) + (INTERCONNECT PHI2_I/PADDI SLICE_44/CLK (3649:3922:4196)(3649:3922:4196)) (INTERCONNECT PHI2_I/PADDI PHI2_MGIOL/DI (424:441:459)(424:441:459)) (INTERCONNECT PHI2_I/PADDI RA\[11\]_MGIOL/CLK (3796:4082:4369)(3796:4082:4369)) (INTERCONNECT PHI2_I/PADDI Din\[7\]_MGIOL/CLK (3796:4082:4369)(3796:4082:4369)) @@ -3719,764 +3782,790 @@ (INTERCONNECT PHI2_I/PADDI Din\[2\]_MGIOL/CLK (3796:4082:4369)(3796:4082:4369)) (INTERCONNECT PHI2_I/PADDI Din\[1\]_MGIOL/CLK (3796:4082:4369)(3796:4082:4369)) (INTERCONNECT PHI2_I/PADDI Din\[0\]_MGIOL/CLK (3796:4082:4369)(3796:4082:4369)) - (INTERCONNECT SLICE_64/F1 SLICE_11/B1 (770:894:1018)(770:894:1018)) - (INTERCONNECT SLICE_64/F1 SLICE_64/B0 (767:894:1021)(767:894:1021)) - (INTERCONNECT SLICE_64/F1 SLICE_76/B0 (777:908:1040)(777:908:1040)) - (INTERCONNECT SLICE_20/F1 SLICE_11/A1 (1640:1837:2034)(1640:1837:2034)) - (INTERCONNECT SLICE_20/F1 SLICE_64/C0 (917:1062:1207)(917:1062:1207)) - (INTERCONNECT SLICE_20/F1 SLICE_73/D1 (906:996:1086)(906:996:1086)) - (INTERCONNECT SLICE_20/F1 SLICE_76/A1 (1116:1271:1427)(1116:1271:1427)) - (INTERCONNECT SLICE_11/Q0 SLICE_11/A0 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_11/Q0 SLICE_17/B1 (1102:1264:1427)(1102:1264:1427)) + (INTERCONNECT SLICE_63/F1 SLICE_11/C1 (1167:1341:1515)(1167:1341:1515)) + (INTERCONNECT SLICE_63/F1 SLICE_63/D0 (523:579:635)(523:579:635)) + (INTERCONNECT SLICE_109/F1 SLICE_11/A1 (735:859:984)(735:859:984)) + (INTERCONNECT SLICE_109/F1 SLICE_17/C1 (536:650:764)(536:650:764)) + (INTERCONNECT SLICE_109/F1 SLICE_63/C0 (552:671:790)(552:671:790)) + (INTERCONNECT SLICE_109/F1 SLICE_76/D1 (868:967:1066)(868:967:1066)) + (INTERCONNECT SLICE_11/Q0 SLICE_11/C0 (534:644:754)(534:644:754)) + (INTERCONNECT SLICE_11/Q0 SLICE_76/D0 (533:592:652)(533:592:652)) (INTERCONNECT SLICE_11/F0 SLICE_11/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT nCCAS_I/PADDI SLICE_12/D0 (4075:4484:4893)(4075:4484:4893)) - (INTERCONNECT nCCAS_I/PADDI SLICE_25/A1 (3609:4008:4408)(3609:4008:4408)) - (INTERCONNECT nCCAS_I/PADDI RD\[0\]_MGIOL/CLK (3021:3312:3603)(3021:3312:3603)) - (INTERCONNECT nCCAS_I/PADDI RD\[7\]_MGIOL/CLK (3021:3312:3603)(3021:3312:3603)) - (INTERCONNECT nCCAS_I/PADDI RD\[6\]_MGIOL/CLK (3021:3312:3603)(3021:3312:3603)) - (INTERCONNECT nCCAS_I/PADDI RD\[5\]_MGIOL/CLK (3021:3312:3603)(3021:3312:3603)) - (INTERCONNECT nCCAS_I/PADDI RD\[4\]_MGIOL/CLK (3021:3312:3603)(3021:3312:3603)) - (INTERCONNECT nCCAS_I/PADDI RD\[3\]_MGIOL/CLK (3021:3312:3603)(3021:3312:3603)) - (INTERCONNECT nCCAS_I/PADDI RD\[2\]_MGIOL/CLK (3021:3312:3603)(3021:3312:3603)) - (INTERCONNECT nCCAS_I/PADDI RD\[1\]_MGIOL/CLK (3021:3312:3603)(3021:3312:3603)) + (INTERCONNECT nCCAS_I/PADDI SLICE_12/B0 (4429:4911:5394)(4429:4911:5394)) + (INTERCONNECT nCCAS_I/PADDI SLICE_25/B1 (3606:4001:4396)(3606:4001:4396)) + (INTERCONNECT nCCAS_I/PADDI RD\[0\]_MGIOL/CLK (2716:2971:3226)(2716:2971:3226)) + (INTERCONNECT nCCAS_I/PADDI RD\[7\]_MGIOL/CLK (2716:2971:3226)(2716:2971:3226)) + (INTERCONNECT nCCAS_I/PADDI RD\[6\]_MGIOL/CLK (2716:2971:3226)(2716:2971:3226)) + (INTERCONNECT nCCAS_I/PADDI RD\[5\]_MGIOL/CLK (2716:2971:3226)(2716:2971:3226)) + (INTERCONNECT nCCAS_I/PADDI RD\[4\]_MGIOL/CLK (2716:2971:3226)(2716:2971:3226)) + (INTERCONNECT nCCAS_I/PADDI RD\[3\]_MGIOL/CLK (2716:2971:3226)(2716:2971:3226)) + (INTERCONNECT nCCAS_I/PADDI RD\[2\]_MGIOL/CLK (2716:2971:3226)(2716:2971:3226)) + (INTERCONNECT nCCAS_I/PADDI RD\[1\]_MGIOL/CLK (2716:2971:3226)(2716:2971:3226)) (INTERCONNECT SLICE_12/F0 SLICE_12/DI0 (3:6:9)(3:6:9)) - (INTERCONNECT SLICE_12/F0 SLICE_73/M0 (1127:1235:1343)(1127:1235:1343)) - (INTERCONNECT SLICE_12/F0 SLICE_73/M1 (1127:1235:1343)(1127:1235:1343)) + (INTERCONNECT SLICE_12/F0 SLICE_76/M0 (836:922:1008)(836:922:1008)) + (INTERCONNECT SLICE_12/F0 SLICE_76/M1 (836:922:1008)(836:922:1008)) (INTERCONNECT SLICE_12/Q0 SLICE_12/M1 (485:526:568)(485:526:568)) - (INTERCONNECT SLICE_12/Q1 SLICE_76/M0 (488:531:575)(488:531:575)) - (INTERCONNECT SLICE_12/Q1 SLICE_92/C0 (1002:1158:1314)(1002:1158:1314)) - (INTERCONNECT SLICE_12/Q1 SLICE_105/C0 (1366:1553:1741)(1366:1553:1741)) - (INTERCONNECT SLICE_12/Q1 SLICE_117/C0 (1002:1158:1314)(1002:1158:1314)) - (INTERCONNECT SLICE_33/Q1 SLICE_16/D1 (1003:1106:1209)(1003:1106:1209)) - (INTERCONNECT SLICE_33/Q1 SLICE_16/LSR (1022:1129:1236)(1022:1129:1236)) - (INTERCONNECT SLICE_33/Q1 SLICE_34/M0 (1661:1809:1957)(1661:1809:1957)) - (INTERCONNECT SLICE_33/Q1 SLICE_35/B1 (1572:1778:1984)(1572:1778:1984)) - (INTERCONNECT SLICE_33/Q1 SLICE_36/D1 (1003:1106:1209)(1003:1106:1209)) - (INTERCONNECT SLICE_33/Q1 SLICE_36/D0 (1003:1106:1209)(1003:1106:1209)) - (INTERCONNECT SLICE_33/Q1 SLICE_44/A1 (1583:1783:1984)(1583:1783:1984)) - (INTERCONNECT SLICE_33/Q1 SLICE_44/LSR (1392:1531:1670)(1392:1531:1670)) - (INTERCONNECT SLICE_33/Q1 SLICE_62/A1 (1182:1347:1513)(1182:1347:1513)) - (INTERCONNECT SLICE_33/Q1 SLICE_90/A0 (1577:1777:1977)(1577:1777:1977)) - (INTERCONNECT SLICE_29/Q0 SLICE_16/C1 (873:1024:1176)(873:1024:1176)) - (INTERCONNECT SLICE_29/Q0 SLICE_29/C1 (547:661:775)(547:661:775)) - (INTERCONNECT SLICE_29/Q0 SLICE_29/C0 (547:661:775)(547:661:775)) - (INTERCONNECT SLICE_29/Q0 SLICE_78/A0 (735:857:980)(735:857:980)) - (INTERCONNECT SLICE_16/Q0 SLICE_16/B1 (788:917:1046)(788:917:1046)) - (INTERCONNECT SLICE_16/Q0 SLICE_16/B0 (788:917:1046)(788:917:1046)) - (INTERCONNECT SLICE_16/Q0 SLICE_44/B0 (1163:1326:1489)(1163:1326:1489)) - (INTERCONNECT SLICE_16/Q0 SLICE_47/B0 (783:913:1043)(783:913:1043)) - (INTERCONNECT SLICE_16/Q0 SLICE_62/C1 (557:673:789)(557:673:789)) - (INTERCONNECT SLICE_16/Q0 SLICE_68/B0 (783:913:1043)(783:913:1043)) - (INTERCONNECT SLICE_16/Q0 SLICE_92/B0 (1163:1326:1489)(1163:1326:1489)) - (INTERCONNECT SLICE_16/Q0 SLICE_96/B1 (1163:1326:1489)(1163:1326:1489)) - (INTERCONNECT SLICE_16/Q0 SLICE_105/A1 (756:884:1012)(756:884:1012)) - (INTERCONNECT SLICE_16/Q0 SLICE_105/A0 (756:884:1012)(756:884:1012)) - (INTERCONNECT SLICE_44/Q0 SLICE_16/A1 (1349:1541:1734)(1349:1541:1734)) - (INTERCONNECT SLICE_44/Q0 SLICE_16/C0 (823:970:1117)(823:970:1117)) - (INTERCONNECT SLICE_44/Q0 SLICE_44/A0 (483:579:675)(483:579:675)) - (INTERCONNECT SLICE_44/Q0 SLICE_47/A0 (804:943:1083)(804:943:1083)) - (INTERCONNECT SLICE_44/Q0 SLICE_62/B1 (1200:1373:1547)(1200:1373:1547)) - (INTERCONNECT SLICE_44/Q0 SLICE_62/D0 (1139:1266:1393)(1139:1266:1393)) - (INTERCONNECT SLICE_44/Q0 SLICE_68/C0 (605:734:863)(605:734:863)) - (INTERCONNECT SLICE_44/Q0 SLICE_96/D0 (538:599:660)(538:599:660)) - (INTERCONNECT SLICE_44/Q0 SLICE_105/D0 (1176:1299:1423)(1176:1299:1423)) - (INTERCONNECT SLICE_44/Q0 SLICE_117/C1 (549:665:781)(549:665:781)) + (INTERCONNECT SLICE_12/Q1 SLICE_69/A0 (1462:1652:1843)(1462:1652:1843)) + (INTERCONNECT SLICE_12/Q1 SLICE_77/M0 (871:963:1056)(871:963:1056)) + (INTERCONNECT SLICE_12/Q1 SLICE_103/D1 (1579:1739:1899)(1579:1739:1899)) + (INTERCONNECT SLICE_12/Q1 SLICE_103/C0 (1263:1443:1623)(1263:1443:1623)) + (INTERCONNECT SLICE_12/Q1 SLICE_117/B0 (1494:1687:1880)(1494:1687:1880)) + (INTERCONNECT SLICE_32/Q1 SLICE_16/D1 (1376:1511:1647)(1376:1511:1647)) + (INTERCONNECT SLICE_32/Q1 SLICE_16/LSR (1733:1909:2086)(1733:1909:2086)) + (INTERCONNECT SLICE_32/Q1 SLICE_33/M0 (1259:1381:1503)(1259:1381:1503)) + (INTERCONNECT SLICE_32/Q1 SLICE_34/A1 (1565:1764:1963)(1565:1764:1963)) + (INTERCONNECT SLICE_32/Q1 SLICE_35/D1 (1001:1104:1207)(1001:1104:1207)) + (INTERCONNECT SLICE_32/Q1 SLICE_35/D0 (1001:1104:1207)(1001:1104:1207)) + (INTERCONNECT SLICE_32/Q1 SLICE_43/D1 (1376:1511:1647)(1376:1511:1647)) + (INTERCONNECT SLICE_32/Q1 SLICE_43/LSR (1733:1909:2086)(1733:1909:2086)) + (INTERCONNECT SLICE_32/Q1 SLICE_62/A1 (1565:1764:1963)(1565:1764:1963)) + (INTERCONNECT SLICE_32/Q1 SLICE_68/A1 (1211:1379:1548)(1211:1379:1548)) + (INTERCONNECT SLICE_16/Q0 SLICE_16/C1 (559:677:795)(559:677:795)) + (INTERCONNECT SLICE_16/Q0 SLICE_16/C0 (559:677:795)(559:677:795)) + (INTERCONNECT SLICE_16/Q0 SLICE_43/B0 (769:896:1023)(769:896:1023)) + (INTERCONNECT SLICE_16/Q0 SLICE_62/B1 (790:921:1052)(790:921:1052)) + (INTERCONNECT SLICE_16/Q0 SLICE_68/C0 (548:666:785)(548:666:785)) + (INTERCONNECT SLICE_16/Q0 SLICE_69/C0 (574:695:816)(574:695:816)) + (INTERCONNECT SLICE_16/Q0 SLICE_75/C1 (944:1097:1250)(944:1097:1250)) + (INTERCONNECT SLICE_16/Q0 SLICE_78/C1 (944:1097:1250)(944:1097:1250)) + (INTERCONNECT SLICE_16/Q0 SLICE_103/A1 (773:904:1036)(773:904:1036)) + (INTERCONNECT SLICE_16/Q0 SLICE_103/A0 (773:904:1036)(773:904:1036)) + (INTERCONNECT SLICE_16/Q0 SLICE_117/D1 (563:629:695)(563:629:695)) + (INTERCONNECT SLICE_16/Q0 SLICE_117/D0 (563:629:695)(563:629:695)) + (INTERCONNECT SLICE_28/Q0 SLICE_16/B1 (1038:1196:1355)(1038:1196:1355)) + (INTERCONNECT SLICE_28/Q0 SLICE_28/D0 (527:586:645)(527:586:645)) + (INTERCONNECT SLICE_28/Q0 SLICE_79/D0 (527:586:645)(527:586:645)) + (INTERCONNECT SLICE_28/Q0 SLICE_83/D1 (530:586:642)(530:586:642)) + (INTERCONNECT SLICE_43/Q0 SLICE_16/A1 (1185:1357:1529)(1185:1357:1529)) + (INTERCONNECT SLICE_43/Q0 SLICE_16/D0 (542:607:672)(542:607:672)) + (INTERCONNECT SLICE_43/Q0 SLICE_35/A1 (762:896:1030)(762:896:1030)) + (INTERCONNECT SLICE_43/Q0 SLICE_43/A0 (487:587:687)(487:587:687)) + (INTERCONNECT SLICE_43/Q0 SLICE_62/C1 (542:660:778)(542:660:778)) + (INTERCONNECT SLICE_43/Q0 SLICE_62/D0 (542:607:672)(542:607:672)) + (INTERCONNECT SLICE_43/Q0 SLICE_68/A0 (762:896:1030)(762:896:1030)) + (INTERCONNECT SLICE_43/Q0 SLICE_101/C0 (927:1082:1237)(927:1082:1237)) + (INTERCONNECT SLICE_43/Q0 SLICE_103/C1 (563:686:810)(563:686:810)) + (INTERCONNECT SLICE_43/Q0 SLICE_106/A1 (1126:1291:1457)(1126:1291:1457)) + (INTERCONNECT SLICE_43/Q0 SLICE_117/B1 (794:930:1067)(794:930:1067)) (INTERCONNECT SLICE_16/F0 SLICE_16/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_16/F1 SLICE_37/D0 (269:296:324)(269:296:324)) - (INTERCONNECT SLICE_16/F1 SLICE_38/C1 (534:645:756)(534:645:756)) - (INTERCONNECT SLICE_64/F0 SLICE_17/C1 (531:639:747)(531:639:747)) - (INTERCONNECT SLICE_106/F0 SLICE_17/A1 (730:848:967)(730:848:967)) - (INTERCONNECT SLICE_17/Q0 SLICE_17/D0 (534:591:648)(534:591:648)) - (INTERCONNECT SLICE_17/Q0 SLICE_23/C1 (809:951:1093)(809:951:1093)) - (INTERCONNECT SLICE_17/Q0 SLICE_74/A0 (1372:1556:1740)(1372:1556:1740)) - (INTERCONNECT SLICE_17/Q0 SLICE_106/D1 (534:591:648)(534:591:648)) - (INTERCONNECT SLICE_17/F1 SLICE_17/C0 (277:356:436)(277:356:436)) - (INTERCONNECT SLICE_76/F0 SLICE_17/A0 (733:848:964)(733:848:964)) + (INTERCONNECT SLICE_16/F1 SLICE_36/B0 (767:891:1015)(767:891:1015)) + (INTERCONNECT SLICE_16/F1 SLICE_37/D1 (525:581:637)(525:581:637)) + (INTERCONNECT SLICE_92/F0 SLICE_17/B1 (768:889:1010)(768:889:1010)) + (INTERCONNECT SLICE_92/F0 SLICE_76/A1 (733:854:976)(733:854:976)) + (INTERCONNECT SLICE_76/F0 SLICE_17/C0 (534:639:744)(534:639:744)) + (INTERCONNECT SLICE_17/Q0 SLICE_17/B0 (765:888:1011)(765:888:1011)) + (INTERCONNECT SLICE_17/Q0 SLICE_23/C1 (978:1131:1285)(978:1131:1285)) + (INTERCONNECT SLICE_33/F0 SLICE_17/A0 (733:848:964)(733:848:964)) (INTERCONNECT SLICE_17/F0 SLICE_17/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_104/F1 SLICE_18/D1 (269:296:324)(269:296:324)) - (INTERCONNECT SLICE_104/F1 SLICE_24/D1 (523:579:635)(523:579:635)) - (INTERCONNECT SLICE_22/F1 SLICE_18/C1 (536:650:764)(536:650:764)) - (INTERCONNECT SLICE_22/F1 SLICE_20/B0 (1125:1295:1466)(1125:1295:1466)) - (INTERCONNECT SLICE_22/F1 SLICE_21/D1 (883:985:1088)(883:985:1088)) - (INTERCONNECT SLICE_22/F1 SLICE_22/B0 (778:907:1036)(778:907:1036)) - (INTERCONNECT SLICE_22/F1 SLICE_23/A0 (1093:1261:1429)(1093:1261:1429)) - (INTERCONNECT SLICE_22/F1 SLICE_24/B1 (778:907:1036)(778:907:1036)) - (INTERCONNECT SLICE_18/Q0 SLICE_18/B1 (765:888:1011)(765:888:1011)) - (INTERCONNECT SLICE_18/Q0 SLICE_31/B1 (775:902:1030)(775:902:1030)) - (INTERCONNECT Din\[1\]_I/PADDI SLICE_18/A1 (1731:1913:2096)(1731:1913:2096)) - (INTERCONNECT Din\[1\]_I/PADDI SLICE_20/D1 (1542:1661:1780)(1542:1661:1780)) - (INTERCONNECT Din\[1\]_I/PADDI SLICE_20/D0 (1542:1661:1780)(1542:1661:1780)) - (INTERCONNECT Din\[1\]_I/PADDI SLICE_21/B0 (1784:1971:2158)(1784:1971:2158)) - (INTERCONNECT Din\[1\]_I/PADDI SLICE_45/D0 (1906:2056:2207)(1906:2056:2207)) - (INTERCONNECT Din\[1\]_I/PADDI RD\[1\]_MGIOL/OPOS (2846:3095:3344)(2846:3095:3344)) + (INTERCONNECT SLICE_22/F1 SLICE_18/D1 (548:615:683)(548:615:683)) + (INTERCONNECT SLICE_22/F1 SLICE_20/D0 (527:589:651)(527:589:651)) + (INTERCONNECT SLICE_22/F1 SLICE_21/D1 (548:615:683)(548:615:683)) + (INTERCONNECT SLICE_22/F1 SLICE_22/C0 (284:372:461)(284:372:461)) + (INTERCONNECT SLICE_22/F1 SLICE_23/A0 (1071:1236:1401)(1071:1236:1401)) + (INTERCONNECT SLICE_22/F1 SLICE_24/B1 (1117:1287:1458)(1117:1287:1458)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_18/C1 (2194:2403:2612)(2194:2403:2612)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_20/C0 (2194:2403:2612)(2194:2403:2612)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_21/C0 (2194:2403:2612)(2194:2403:2612)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_44/A0 (2763:3014:3266)(2763:3014:3266)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_109/C1 (2178:2385:2593)(2178:2385:2593)) + (INTERCONNECT Din\[1\]_I/PADDI RD\[1\]_MGIOL/OPOS (3725:4020:4315)(3725:4020:4315)) (INTERCONNECT Din\[1\]_I/PADDI Din\[1\]_MGIOL/DI (544:554:565)(544:554:565)) + (INTERCONNECT SLICE_119/F1 SLICE_18/B1 (768:889:1010)(768:889:1010)) + (INTERCONNECT SLICE_119/F1 SLICE_24/A1 (736:854:973)(736:854:973)) + (INTERCONNECT SLICE_18/Q0 SLICE_18/A1 (733:853:974)(733:853:974)) + (INTERCONNECT SLICE_18/Q0 SLICE_30/C1 (803:944:1086)(803:944:1086)) (INTERCONNECT SLICE_18/F1 SLICE_18/C0 (277:356:436)(277:356:436)) - (INTERCONNECT SLICE_74/F1 SLICE_18/B0 (1044:1209:1374)(1044:1209:1374)) - (INTERCONNECT SLICE_74/F1 SLICE_20/C0 (873:1026:1180)(873:1026:1180)) - (INTERCONNECT SLICE_74/F1 SLICE_21/A0 (740:867:995)(740:867:995)) - (INTERCONNECT SLICE_74/F1 SLICE_24/A0 (1012:1174:1337)(1012:1174:1337)) - (INTERCONNECT SLICE_74/F1 SLICE_74/B0 (767:894:1021)(767:894:1021)) - (INTERCONNECT SLICE_31/Q0 SLICE_18/A0 (749:874:1000)(749:874:1000)) - (INTERCONNECT SLICE_31/Q0 SLICE_31/B0 (765:888:1011)(765:888:1011)) - (INTERCONNECT SLICE_31/Q0 SLICE_33/B1 (1623:1816:2010)(1623:1816:2010)) - (INTERCONNECT SLICE_31/Q0 SLICE_45/B0 (1151:1311:1471)(1151:1311:1471)) + (INTERCONNECT SLICE_77/F1 SLICE_18/B0 (791:921:1051)(791:921:1051)) + (INTERCONNECT SLICE_77/F1 SLICE_20/B0 (791:921:1051)(791:921:1051)) + (INTERCONNECT SLICE_77/F1 SLICE_21/B0 (791:921:1051)(791:921:1051)) + (INTERCONNECT SLICE_77/F1 SLICE_24/D0 (876:973:1070)(876:973:1070)) + (INTERCONNECT SLICE_77/F1 SLICE_77/B0 (765:889:1013)(765:889:1013)) + (INTERCONNECT SLICE_30/Q0 SLICE_18/A0 (1008:1160:1313)(1008:1160:1313)) + (INTERCONNECT SLICE_30/Q0 SLICE_30/A0 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_30/Q0 SLICE_44/C0 (1179:1353:1527)(1179:1353:1527)) + (INTERCONNECT SLICE_30/Q0 SLICE_106/B0 (2101:2354:2608)(2101:2354:2608)) (INTERCONNECT SLICE_18/F0 SLICE_18/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_106/F1 SLICE_18/CE (1155:1284:1413)(1155:1284:1413)) - (INTERCONNECT SLICE_106/F1 SLICE_20/CE (1155:1284:1413)(1155:1284:1413)) - (INTERCONNECT SLICE_106/F1 SLICE_21/CE (1155:1284:1413)(1155:1284:1413)) - (INTERCONNECT SLICE_106/F1 SLICE_24/CE (1155:1284:1413)(1155:1284:1413)) - (INTERCONNECT SLICE_106/F1 SLICE_45/CE (879:978:1078)(879:978:1078)) - (INTERCONNECT Din\[0\]_I/PADDI SLICE_19/M0 (2687:2899:3112)(2687:2899:3112)) - (INTERCONNECT Din\[0\]_I/PADDI SLICE_20/B1 (2653:2911:3170)(2653:2911:3170)) - (INTERCONNECT Din\[0\]_I/PADDI SLICE_21/D0 (2411:2601:2792)(2411:2601:2792)) - (INTERCONNECT Din\[0\]_I/PADDI SLICE_24/C1 (2042:2254:2467)(2042:2254:2467)) - (INTERCONNECT Din\[0\]_I/PADDI SLICE_93/A1 (2621:2877:3133)(2621:2877:3133)) - (INTERCONNECT Din\[0\]_I/PADDI RD\[0\]_MGIOL/OPOS (4042:4397:4753)(4042:4397:4753)) + (INTERCONNECT SLICE_23/F1 SLICE_18/CE (1037:1139:1241)(1037:1139:1241)) + (INTERCONNECT SLICE_23/F1 SLICE_20/CE (611:689:767)(611:689:767)) + (INTERCONNECT SLICE_23/F1 SLICE_21/CE (1037:1139:1241)(1037:1139:1241)) + (INTERCONNECT SLICE_23/F1 SLICE_22/D0 (592:666:740)(592:666:740)) + (INTERCONNECT SLICE_23/F1 SLICE_23/B0 (513:611:710)(513:611:710)) + (INTERCONNECT SLICE_23/F1 SLICE_24/CE (1037:1139:1241)(1037:1139:1241)) + (INTERCONNECT SLICE_23/F1 SLICE_44/CE (981:1091:1201)(981:1091:1201)) + (INTERCONNECT SLICE_23/F1 SLICE_77/C0 (973:1134:1295)(973:1134:1295)) + (INTERCONNECT SLICE_26/Q0 SLICE_19/D0 (1355:1489:1623)(1355:1489:1623)) + (INTERCONNECT SLICE_26/Q0 SLICE_26/C1 (547:661:775)(547:661:775)) + (INTERCONNECT SLICE_26/Q0 SLICE_26/A0 (481:575:669)(481:575:669)) + (INTERCONNECT SLICE_26/Q0 SLICE_27/B1 (1935:2174:2413)(1935:2174:2413)) + (INTERCONNECT SLICE_26/Q0 SLICE_27/D0 (1355:1489:1623)(1355:1489:1623)) + (INTERCONNECT SLICE_26/Q0 SLICE_28/B1 (1222:1391:1561)(1222:1391:1561)) + (INTERCONNECT SLICE_26/Q0 SLICE_28/B0 (1222:1391:1561)(1222:1391:1561)) + (INTERCONNECT SLICE_26/Q0 SLICE_36/B1 (1935:2174:2413)(1935:2174:2413)) + (INTERCONNECT SLICE_26/Q0 SLICE_83/C0 (547:661:775)(547:661:775)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_19/M0 (2819:3025:3232)(2819:3025:3232)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_21/D0 (3594:3876:4158)(3594:3876:4158)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_24/C1 (3932:4304:4676)(3932:4304:4676)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_109/B1 (4308:4691:5075)(4308:4691:5075)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_109/B0 (4308:4691:5075)(4308:4691:5075)) + (INTERCONNECT Din\[0\]_I/PADDI RD\[0\]_MGIOL/OPOS (3329:3589:3849)(3329:3589:3849)) (INTERCONNECT Din\[0\]_I/PADDI Din\[0\]_MGIOL/DI (424:441:459)(424:441:459)) - (INTERCONNECT SLICE_74/F0 SLICE_19/CE (539:596:653)(539:596:653)) - (INTERCONNECT SLICE_19/F0 RCLKout_MGIOL/ONEG (1854:2023:2192)(1854:2023:2192)) - (INTERCONNECT SLICE_19/Q0 SLICE_59/A0 (1620:1808:1997)(1620:1808:1997)) - (INTERCONNECT SLICE_19/F1 RCLKout_MGIOL/OPOS (2236:2438:2640)(2236:2438:2640)) - (INTERCONNECT Din\[4\]_I/PADDI SLICE_20/C1 (1727:1909:2092)(1727:1909:2092)) - (INTERCONNECT Din\[4\]_I/PADDI SLICE_22/A1 (2307:2533:2759)(2307:2533:2759)) - (INTERCONNECT Din\[4\]_I/PADDI SLICE_45/B1 (2671:2936:3201)(2671:2936:3201)) - (INTERCONNECT Din\[4\]_I/PADDI SLICE_74/B1 (1969:2165:2362)(1969:2165:2362)) - (INTERCONNECT Din\[4\]_I/PADDI SLICE_93/C1 (2440:2692:2944)(2440:2692:2944)) - (INTERCONNECT Din\[4\]_I/PADDI SLICE_104/A1 (2634:2895:3156)(2634:2895:3156)) - (INTERCONNECT Din\[4\]_I/PADDI RD\[4\]_MGIOL/OPOS (3052:3278:3505)(3052:3278:3505)) - (INTERCONNECT Din\[4\]_I/PADDI Din\[4\]_MGIOL/DI (544:554:565)(544:554:565)) - (INTERCONNECT Din\[7\]_I/PADDI SLICE_20/A1 (2731:3026:3322)(2731:3026:3322)) - (INTERCONNECT Din\[7\]_I/PADDI SLICE_104/D1 (2194:2389:2584)(2194:2389:2584)) - (INTERCONNECT Din\[7\]_I/PADDI SLICE_104/D0 (2194:2389:2584)(2194:2389:2584)) - (INTERCONNECT Din\[7\]_I/PADDI RD\[7\]_MGIOL/OPOS (4271:4657:5044)(4271:4657:5044)) - (INTERCONNECT Din\[7\]_I/PADDI Din\[7\]_MGIOL/DI (424:441:459)(424:441:459)) + (INTERCONNECT SLICE_77/F0 SLICE_19/CE (1451:1579:1708)(1451:1579:1708)) + (INTERCONNECT SLICE_19/F0 RA\[10\]_MGIOL/OPOS (1985:2155:2325)(1985:2155:2325)) + (INTERCONNECT SLICE_19/Q0 SLICE_58/B0 (1583:1780:1978)(1583:1780:1978)) (INTERCONNECT SLICE_20/Q0 SLICE_20/A0 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_20/Q0 SLICE_95/A0 (1002:1154:1306)(1002:1154:1306)) + (INTERCONNECT SLICE_20/Q0 SLICE_100/A0 (1480:1681:1882)(1480:1681:1882)) (INTERCONNECT SLICE_20/F0 SLICE_20/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_21/Q0 SLICE_21/A1 (733:853:974)(733:853:974)) - (INTERCONNECT SLICE_21/Q0 SLICE_52/B0 (1034:1188:1343)(1034:1188:1343)) - (INTERCONNECT SLICE_21/F1 SLICE_21/C0 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_20/F1 RCLKout_MGIOL/OPOS (2218:2418:2619)(2218:2418:2619)) + (INTERCONNECT SLICE_21/Q0 SLICE_21/B1 (765:888:1011)(765:888:1011)) + (INTERCONNECT SLICE_21/Q0 SLICE_51/A0 (1190:1355:1521)(1190:1355:1521)) + (INTERCONNECT SLICE_21/F1 SLICE_21/A0 (730:848:967)(730:848:967)) (INTERCONNECT SLICE_21/F0 SLICE_21/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_104/F0 SLICE_22/D1 (523:579:635)(523:579:635)) - (INTERCONNECT SLICE_104/F0 SLICE_45/C1 (814:957:1101)(814:957:1101)) - (INTERCONNECT SLICE_104/F0 SLICE_74/D1 (1531:1682:1834)(1531:1682:1834)) - (INTERCONNECT SLICE_104/F0 SLICE_93/D0 (803:891:980)(803:891:980)) - (INTERCONNECT Din\[5\]_I/PADDI SLICE_22/C1 (1725:1907:2089)(1725:1907:2089)) - (INTERCONNECT Din\[5\]_I/PADDI SLICE_26/C0 (2296:2506:2716)(2296:2506:2716)) - (INTERCONNECT Din\[5\]_I/PADDI SLICE_45/D1 (2073:2231:2389)(2073:2231:2389)) - (INTERCONNECT Din\[5\]_I/PADDI SLICE_73/C1 (2448:2692:2937)(2448:2692:2937)) - (INTERCONNECT Din\[5\]_I/PADDI SLICE_74/A1 (2288:2512:2736)(2288:2512:2736)) - (INTERCONNECT Din\[5\]_I/PADDI SLICE_104/B1 (2283:2513:2743)(2283:2513:2743)) - (INTERCONNECT Din\[5\]_I/PADDI RD\[5\]_MGIOL/OPOS (3066:3294:3522)(3066:3294:3522)) - (INTERCONNECT Din\[5\]_I/PADDI Din\[5\]_MGIOL/DI (544:554:565)(544:554:565)) - (INTERCONNECT Din\[3\]_I/PADDI SLICE_22/B1 (1835:2022:2210)(1835:2022:2210)) - (INTERCONNECT Din\[3\]_I/PADDI SLICE_64/D1 (2380:2561:2742)(2380:2561:2742)) - (INTERCONNECT Din\[3\]_I/PADDI SLICE_73/A1 (2590:2836:3083)(2590:2836:3083)) - (INTERCONNECT Din\[3\]_I/PADDI SLICE_74/C1 (2338:2576:2814)(2338:2576:2814)) - (INTERCONNECT Din\[3\]_I/PADDI SLICE_93/A0 (2954:3232:3510)(2954:3232:3510)) - (INTERCONNECT Din\[3\]_I/PADDI RD\[3\]_MGIOL/OPOS (3320:3599:3879)(3320:3599:3879)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_22/D1 (1976:2132:2288)(1976:2132:2288)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_44/D1 (2094:2248:2403)(2094:2248:2403)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_77/C1 (2432:2676:2921)(2432:2676:2921)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_109/D1 (1976:2132:2288)(1976:2132:2288)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_109/D0 (1976:2132:2288)(1976:2132:2288)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_119/D1 (1976:2132:2288)(1976:2132:2288)) + (INTERCONNECT Din\[4\]_I/PADDI RD\[4\]_MGIOL/OPOS (3436:3703:3971)(3436:3703:3971)) + (INTERCONNECT Din\[4\]_I/PADDI Din\[4\]_MGIOL/DI (544:554:565)(544:554:565)) + (INTERCONNECT SLICE_96/F1 SLICE_22/C1 (282:367:453)(282:367:453)) + (INTERCONNECT SLICE_96/F1 SLICE_44/C1 (541:658:775)(541:658:775)) + (INTERCONNECT SLICE_96/F1 SLICE_77/A1 (740:867:995)(740:867:995)) + (INTERCONNECT SLICE_96/F1 SLICE_96/C0 (282:367:453)(282:367:453)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_22/B1 (1955:2148:2341)(1955:2148:2341)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_63/A1 (3097:3389:3682)(3097:3389:3682)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_77/D1 (1974:2124:2274)(1974:2124:2274)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_92/A1 (3097:3389:3682)(3097:3389:3682)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_96/A0 (2511:2761:3012)(2511:2761:3012)) + (INTERCONNECT Din\[3\]_I/PADDI RD\[3\]_MGIOL/OPOS (2531:2718:2905)(2531:2718:2905)) (INTERCONNECT Din\[3\]_I/PADDI Din\[3\]_MGIOL/DI (544:554:565)(544:554:565)) - (INTERCONNECT SLICE_23/F1 SLICE_22/C0 (537:645:753)(537:645:753)) - (INTERCONNECT SLICE_23/F1 SLICE_23/C0 (280:362:445)(280:362:445)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_22/A1 (2061:2254:2447)(2061:2254:2447)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_44/B1 (2463:2690:2918)(2463:2690:2918)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_77/B1 (2463:2690:2918)(2463:2690:2918)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_92/C1 (1710:1889:2069)(1710:1889:2069)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_119/C1 (2189:2406:2624)(2189:2406:2624)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_119/B0 (2093:2288:2484)(2093:2288:2484)) + (INTERCONNECT Din\[5\]_I/PADDI RD\[5\]_MGIOL/OPOS (3557:3829:4101)(3557:3829:4101)) + (INTERCONNECT Din\[5\]_I/PADDI Din\[5\]_MGIOL/DI (544:554:565)(544:554:565)) (INTERCONNECT SLICE_22/F0 SLICE_22/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_22/Q0 SLICE_46/C1 (889:1040:1192)(889:1040:1192)) - (INTERCONNECT SLICE_22/Q0 SLICE_97/C1 (889:1040:1192)(889:1040:1192)) - (INTERCONNECT SLICE_22/Q0 SLICE_97/C0 (889:1040:1192)(889:1040:1192)) - (INTERCONNECT MAin\[0\]_I/PADDI SLICE_23/D1 (2210:2396:2583)(2210:2396:2583)) - (INTERCONNECT MAin\[0\]_I/PADDI SLICE_39/B0 (2822:3108:3395)(2822:3108:3395)) - (INTERCONNECT MAin\[0\]_I/PADDI SLICE_64/A1 (2800:3085:3370)(2800:3085:3370)) - (INTERCONNECT MAin\[0\]_I/PADDI SLICE_64/A0 (2800:3085:3370)(2800:3085:3370)) - (INTERCONNECT MAin\[0\]_I/PADDI SLICE_75/D0 (2210:2396:2583)(2210:2396:2583)) - (INTERCONNECT MAin\[0\]_I/PADDI SLICE_106/B1 (3159:3481:3804)(3159:3481:3804)) - (INTERCONNECT MAin\[0\]_I/PADDI SLICE_106/D0 (2590:2809:3029)(2590:2809:3029)) - (INTERCONNECT MAin\[0\]_I/PADDI SLICE_111/B1 (2822:3108:3395)(2822:3108:3395)) + (INTERCONNECT SLICE_22/Q0 SLICE_45/B1 (1557:1756:1955)(1557:1756:1955)) + (INTERCONNECT SLICE_22/Q0 SLICE_57/D1 (951:1050:1150)(951:1050:1150)) + (INTERCONNECT SLICE_22/Q0 SLICE_110/D0 (951:1050:1150)(951:1050:1150)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_23/B1 (1837:2037:2237)(1837:2037:2237)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_38/D0 (2744:2983:3223)(2744:2983:3223)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_63/B1 (1837:2037:2237)(1837:2037:2237)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_63/B0 (1837:2037:2237)(1837:2037:2237)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_92/B0 (1837:2037:2237)(1837:2037:2237)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_113/D0 (2744:2983:3223)(2744:2983:3223)) (INTERCONNECT SLICE_23/F0 SLICE_23/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_23/Q0 SLICE_95/D0 (1410:1533:1656)(1410:1533:1656)) - (INTERCONNECT SLICE_24/Q0 SLICE_24/A1 (733:853:974)(733:853:974)) - (INTERCONNECT SLICE_24/Q0 SLICE_108/A1 (1177:1341:1505)(1177:1341:1505)) - (INTERCONNECT SLICE_24/F1 SLICE_24/C0 (277:356:436)(277:356:436)) - (INTERCONNECT SLICE_46/Q0 SLICE_24/B0 (781:909:1037)(781:909:1037)) - (INTERCONNECT SLICE_46/Q0 SLICE_46/A0 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_46/Q0 SLICE_115/B0 (1560:1763:1967)(1560:1763:1967)) + (INTERCONNECT SLICE_23/Q0 SLICE_100/D0 (523:573:623)(523:573:623)) + (INTERCONNECT SLICE_24/Q0 SLICE_24/D1 (523:578:633)(523:578:633)) + (INTERCONNECT SLICE_24/Q0 SLICE_111/D1 (1462:1593:1724)(1462:1593:1724)) + (INTERCONNECT SLICE_45/Q0 SLICE_24/C0 (1115:1270:1425)(1115:1270:1425)) + (INTERCONNECT SLICE_45/Q0 SLICE_45/A0 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_45/Q0 SLICE_120/A0 (2005:2237:2469)(2005:2237:2469)) + (INTERCONNECT SLICE_24/F1 SLICE_24/B0 (762:883:1004)(762:883:1004)) (INTERCONNECT SLICE_24/F0 SLICE_24/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT nFWE_I/PADDI SLICE_25/D1 (2526:2717:2908)(2526:2717:2908)) - (INTERCONNECT nFWE_I/PADDI SLICE_25/D0 (2526:2717:2908)(2526:2717:2908)) - (INTERCONNECT nFWE_I/PADDI SLICE_109/C0 (2363:2611:2859)(2363:2611:2859)) - (INTERCONNECT SLICE_25/F0 SLICE_25/DI0 (3:6:9)(3:6:9)) - (INTERCONNECT SLICE_25/F0 SLICE_26/M0 (488:532:577)(488:532:577)) - (INTERCONNECT nCRAS_I/PADDI SLICE_25/CLK (4050:4346:4642)(4050:4346:4642)) - (INTERCONNECT nCRAS_I/PADDI SLICE_26/CLK (4050:4346:4642)(4050:4346:4642)) - (INTERCONNECT nCRAS_I/PADDI SLICE_33/A1 (2300:2518:2736)(2300:2518:2736)) - (INTERCONNECT nCRAS_I/PADDI SLICE_33/A0 (2300:2518:2736)(2300:2518:2736)) - (INTERCONNECT nCRAS_I/PADDI SLICE_39/CLK (4050:4346:4642)(4050:4346:4642)) - (INTERCONNECT nCRAS_I/PADDI SLICE_39/CLK (4050:4346:4642)(4050:4346:4642)) - (INTERCONNECT nCRAS_I/PADDI SLICE_40/CLK (4050:4346:4642)(4050:4346:4642)) - (INTERCONNECT nCRAS_I/PADDI SLICE_40/CLK (4050:4346:4642)(4050:4346:4642)) - (INTERCONNECT nCRAS_I/PADDI SLICE_41/CLK (4050:4346:4642)(4050:4346:4642)) - (INTERCONNECT nCRAS_I/PADDI SLICE_41/CLK (4050:4346:4642)(4050:4346:4642)) - (INTERCONNECT nCRAS_I/PADDI SLICE_42/CLK (4050:4346:4642)(4050:4346:4642)) - (INTERCONNECT nCRAS_I/PADDI SLICE_42/CLK (4050:4346:4642)(4050:4346:4642)) - (INTERCONNECT nCRAS_I/PADDI SLICE_43/CLK (4050:4346:4642)(4050:4346:4642)) - (INTERCONNECT nCRAS_I/PADDI SLICE_43/CLK (4050:4346:4642)(4050:4346:4642)) - (INTERCONNECT nCRAS_I/PADDI SLICE_73/CLK (4050:4346:4642)(4050:4346:4642)) - (INTERCONNECT nCRAS_I/PADDI SLICE_73/CLK (4050:4346:4642)(4050:4346:4642)) - (INTERCONNECT nCRAS_I/PADDI RBA\[1\]_MGIOL/CLK (4197:4506:4815)(4197:4506:4815)) - (INTERCONNECT nCRAS_I/PADDI RBA\[0\]_MGIOL/CLK (4197:4506:4815)(4197:4506:4815)) - (INTERCONNECT SLICE_25/Q0 SLICE_47/B1 (1581:1778:1975)(1581:1778:1975)) - (INTERCONNECT SLICE_25/Q0 SLICE_96/C1 (1677:1896:2115)(1677:1896:2115)) - (INTERCONNECT SLICE_25/Q0 SLICE_105/B1 (2283:2548:2814)(2283:2548:2814)) - (INTERCONNECT SLICE_25/Q0 SLICE_105/B0 (2283:2548:2814)(2283:2548:2814)) - (INTERCONNECT SLICE_25/F1 RD\[0\]_I/PADDT (1314:1454:1595)(1314:1454:1595)) - (INTERCONNECT SLICE_25/F1 RD\[7\]_I/PADDT (1826:1998:2170)(1826:1998:2170)) - (INTERCONNECT SLICE_25/F1 RD\[6\]_I/PADDT (1826:1998:2170)(1826:1998:2170)) - (INTERCONNECT SLICE_25/F1 RD\[5\]_I/PADDT (1826:1998:2170)(1826:1998:2170)) - (INTERCONNECT SLICE_25/F1 RD\[4\]_I/PADDT (1826:1998:2170)(1826:1998:2170)) - (INTERCONNECT SLICE_25/F1 RD\[3\]_I/PADDT (1646:1823:2000)(1646:1823:2000)) - (INTERCONNECT SLICE_25/F1 RD\[2\]_I/PADDT (1646:1823:2000)(1646:1823:2000)) - (INTERCONNECT SLICE_25/F1 RD\[1\]_I/PADDT (1314:1454:1595)(1314:1454:1595)) - (INTERCONNECT CROW\[1\]_I/PADDI SLICE_26/C1 (2222:2468:2714)(2222:2468:2714)) - (INTERCONNECT SLICE_38/Q0 SLICE_26/A1 (1184:1351:1519)(1184:1351:1519)) - (INTERCONNECT SLICE_38/Q0 SLICE_38/A0 (481:575:669)(481:575:669)) - (INTERCONNECT SLICE_38/Q0 SLICE_39/D1 (1468:1601:1735)(1468:1601:1735)) - (INTERCONNECT SLICE_38/Q0 SLICE_39/D0 (1468:1601:1735)(1468:1601:1735)) - (INTERCONNECT SLICE_38/Q0 SLICE_40/B1 (2151:2378:2606)(2151:2378:2606)) - (INTERCONNECT SLICE_38/Q0 SLICE_40/B0 (2151:2378:2606)(2151:2378:2606)) - (INTERCONNECT SLICE_38/Q0 SLICE_41/D1 (1909:2068:2228)(1909:2068:2228)) - (INTERCONNECT SLICE_38/Q0 SLICE_41/D0 (1909:2068:2228)(1909:2068:2228)) - (INTERCONNECT SLICE_38/Q0 SLICE_42/D1 (1468:1601:1735)(1468:1601:1735)) - (INTERCONNECT SLICE_38/Q0 SLICE_42/D0 (1468:1601:1735)(1468:1601:1735)) - (INTERCONNECT SLICE_38/Q0 SLICE_43/B1 (1147:1308:1470)(1147:1308:1470)) - (INTERCONNECT SLICE_38/Q0 SLICE_43/B0 (1147:1308:1470)(1147:1308:1470)) - (INTERCONNECT SLICE_38/Q0 SLICE_115/D1 (1838:2003:2169)(1838:2003:2169)) - (INTERCONNECT SLICE_38/Q0 SLICE_115/D0 (1838:2003:2169)(1838:2003:2169)) - (INTERCONNECT Din\[2\]_I/PADDI SLICE_26/D0 (1836:1962:2088)(1836:1962:2088)) - (INTERCONNECT Din\[2\]_I/PADDI SLICE_73/D0 (2069:2225:2382)(2069:2225:2382)) - (INTERCONNECT Din\[2\]_I/PADDI SLICE_106/C0 (2407:2653:2900)(2407:2653:2900)) - (INTERCONNECT Din\[2\]_I/PADDI RD\[2\]_MGIOL/OPOS (3059:3306:3554)(3059:3306:3554)) - (INTERCONNECT Din\[2\]_I/PADDI Din\[2\]_MGIOL/DI (544:554:565)(544:554:565)) - (INTERCONNECT SLICE_26/F0 SLICE_64/B1 (1225:1391:1558)(1225:1391:1558)) - (INTERCONNECT SLICE_26/F0 SLICE_93/B0 (1225:1391:1558)(1225:1391:1558)) - (INTERCONNECT SLICE_26/Q0 SLICE_92/A0 (1067:1225:1383)(1067:1225:1383)) - (INTERCONNECT SLICE_26/F1 RBA\[1\]_MGIOL/OPOS (1445:1584:1723)(1445:1584:1723)) - (INTERCONNECT SLICE_37/Q0 SLICE_27/B1 (1162:1328:1495)(1162:1328:1495)) - (INTERCONNECT SLICE_37/Q0 SLICE_27/B0 (1162:1328:1495)(1162:1328:1495)) - (INTERCONNECT SLICE_37/Q0 SLICE_35/C1 (877:1032:1188)(877:1032:1188)) - (INTERCONNECT SLICE_37/Q0 SLICE_35/B0 (778:922:1066)(778:922:1066)) - (INTERCONNECT SLICE_37/Q0 SLICE_37/A0 (485:583:681)(485:583:681)) - (INTERCONNECT SLICE_37/Q0 SLICE_38/A1 (750:878:1007)(750:878:1007)) - (INTERCONNECT SLICE_37/Q0 SLICE_44/D1 (1295:1426:1557)(1295:1426:1557)) - (INTERCONNECT SLICE_37/Q0 SLICE_47/D1 (536:612:688)(536:612:688)) - (INTERCONNECT SLICE_37/Q0 SLICE_47/D0 (536:612:688)(536:612:688)) - (INTERCONNECT SLICE_37/Q0 SLICE_62/A0 (750:878:1007)(750:878:1007)) - (INTERCONNECT SLICE_37/Q0 SLICE_68/D0 (536:612:688)(536:612:688)) - (INTERCONNECT SLICE_37/Q0 SLICE_78/D1 (545:611:677)(545:611:677)) - (INTERCONNECT SLICE_37/Q0 SLICE_90/D0 (1295:1426:1557)(1295:1426:1557)) - (INTERCONNECT SLICE_37/Q0 SLICE_117/D1 (1295:1426:1557)(1295:1426:1557)) - (INTERCONNECT SLICE_62/F1 SLICE_27/A1 (1012:1174:1337)(1012:1174:1337)) - (INTERCONNECT SLICE_62/F1 SLICE_27/A0 (1012:1174:1337)(1012:1174:1337)) - (INTERCONNECT SLICE_62/F1 SLICE_62/B0 (513:611:710)(513:611:710)) - (INTERCONNECT SLICE_62/F1 SLICE_78/B1 (772:902:1032)(772:902:1032)) - (INTERCONNECT SLICE_62/F1 SLICE_81/C0 (552:671:790)(552:671:790)) - (INTERCONNECT SLICE_62/F1 SLICE_90/B1 (783:915:1047)(783:915:1047)) - (INTERCONNECT SLICE_27/Q0 SLICE_27/C0 (538:652:766)(538:652:766)) - (INTERCONNECT SLICE_27/Q0 SLICE_28/C1 (544:667:790)(544:667:790)) - (INTERCONNECT SLICE_27/Q0 SLICE_28/C0 (544:667:790)(544:667:790)) - (INTERCONNECT SLICE_27/Q0 SLICE_29/B0 (1224:1395:1567)(1224:1395:1567)) - (INTERCONNECT SLICE_27/Q0 SLICE_37/A1 (2034:2268:2503)(2034:2268:2503)) - (INTERCONNECT SLICE_27/Q0 SLICE_81/A0 (1889:2125:2361)(1889:2125:2361)) - (INTERCONNECT SLICE_27/Q0 SLICE_90/D1 (530:586:642)(530:586:642)) - (INTERCONNECT SLICE_27/Q0 SLICE_114/C1 (544:667:790)(544:667:790)) - (INTERCONNECT SLICE_27/Q0 SLICE_114/A0 (1192:1361:1530)(1192:1361:1530)) + (INTERCONNECT nFWE_I/PADDI SLICE_25/C1 (2947:3215:3483)(2947:3215:3483)) + (INTERCONNECT nFWE_I/PADDI SLICE_25/C0 (2947:3215:3483)(2947:3215:3483)) + (INTERCONNECT nFWE_I/PADDI SLICE_90/A1 (3608:3914:4220)(3608:3914:4220)) + (INTERCONNECT SLICE_25/F0 SLICE_25/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_25/CLK (2802:3073:3344)(2802:3073:3344)) + (INTERCONNECT nCRAS_I/PADDI SLICE_32/B0 (3567:3956:4345)(3567:3956:4345)) + (INTERCONNECT nCRAS_I/PADDI SLICE_38/CLK (2802:3073:3344)(2802:3073:3344)) + (INTERCONNECT nCRAS_I/PADDI SLICE_38/CLK (2802:3073:3344)(2802:3073:3344)) + (INTERCONNECT nCRAS_I/PADDI SLICE_39/CLK (2802:3073:3344)(2802:3073:3344)) + (INTERCONNECT nCRAS_I/PADDI SLICE_39/CLK (2802:3073:3344)(2802:3073:3344)) + (INTERCONNECT nCRAS_I/PADDI SLICE_40/CLK (2802:3073:3344)(2802:3073:3344)) + (INTERCONNECT nCRAS_I/PADDI SLICE_40/CLK (2802:3073:3344)(2802:3073:3344)) + (INTERCONNECT nCRAS_I/PADDI SLICE_41/CLK (2802:3073:3344)(2802:3073:3344)) + (INTERCONNECT nCRAS_I/PADDI SLICE_41/CLK (2802:3073:3344)(2802:3073:3344)) + (INTERCONNECT nCRAS_I/PADDI SLICE_42/CLK (2802:3073:3344)(2802:3073:3344)) + (INTERCONNECT nCRAS_I/PADDI SLICE_42/CLK (2802:3073:3344)(2802:3073:3344)) + (INTERCONNECT nCRAS_I/PADDI SLICE_76/CLK (2802:3073:3344)(2802:3073:3344)) + (INTERCONNECT nCRAS_I/PADDI SLICE_76/CLK (2802:3073:3344)(2802:3073:3344)) + (INTERCONNECT nCRAS_I/PADDI SLICE_106/C0 (3336:3712:4088)(3336:3712:4088)) + (INTERCONNECT nCRAS_I/PADDI RBA\[1\]_MGIOL/CLK (2949:3233:3517)(2949:3233:3517)) + (INTERCONNECT nCRAS_I/PADDI RBA\[0\]_MGIOL/CLK (2949:3233:3517)(2949:3233:3517)) + (INTERCONNECT SLICE_25/Q0 SLICE_46/B1 (783:913:1043)(783:913:1043)) + (INTERCONNECT SLICE_25/Q0 SLICE_69/B1 (778:905:1032)(778:905:1032)) + (INTERCONNECT SLICE_25/Q0 SLICE_78/B1 (783:913:1043)(783:913:1043)) + (INTERCONNECT SLICE_25/Q0 SLICE_103/B1 (767:892:1017)(767:892:1017)) + (INTERCONNECT SLICE_25/Q0 SLICE_103/D0 (536:595:654)(536:595:654)) + (INTERCONNECT SLICE_25/F1 RD\[0\]_I/PADDT (688:769:851)(688:769:851)) + (INTERCONNECT SLICE_25/F1 RD\[7\]_I/PADDT (1491:1644:1798)(1491:1644:1798)) + (INTERCONNECT SLICE_25/F1 RD\[6\]_I/PADDT (1491:1644:1798)(1491:1644:1798)) + (INTERCONNECT SLICE_25/F1 RD\[5\]_I/PADDT (1491:1644:1798)(1491:1644:1798)) + (INTERCONNECT SLICE_25/F1 RD\[4\]_I/PADDT (1491:1644:1798)(1491:1644:1798)) + (INTERCONNECT SLICE_25/F1 RD\[3\]_I/PADDT (947:1055:1164)(947:1055:1164)) + (INTERCONNECT SLICE_25/F1 RD\[2\]_I/PADDT (947:1055:1164)(947:1055:1164)) + (INTERCONNECT SLICE_25/F1 RD\[1\]_I/PADDT (688:769:851)(688:769:851)) + (INTERCONNECT SLICE_62/F1 SLICE_26/D1 (530:601:672)(530:601:672)) + (INTERCONNECT SLICE_62/F1 SLICE_26/D0 (530:601:672)(530:601:672)) + (INTERCONNECT SLICE_62/F1 SLICE_62/C0 (280:362:445)(280:362:445)) + (INTERCONNECT SLICE_62/F1 SLICE_79/D1 (848:963:1078)(848:963:1078)) + (INTERCONNECT SLICE_62/F1 SLICE_83/B0 (772:911:1050)(772:911:1050)) + (INTERCONNECT SLICE_62/F1 SLICE_122/D0 (1212:1358:1505)(1212:1358:1505)) + (INTERCONNECT SLICE_83/F1 SLICE_26/B1 (776:902:1028)(776:902:1028)) + (INTERCONNECT SLICE_83/F1 SLICE_62/A0 (736:854:973)(736:854:973)) + (INTERCONNECT SLICE_83/F1 SLICE_83/A0 (744:867:991)(744:867:991)) + (INTERCONNECT SLICE_43/F1 SLICE_26/A1 (743:869:995)(743:869:995)) + (INTERCONNECT SLICE_43/F1 SLICE_83/D0 (269:296:324)(269:296:324)) + (INTERCONNECT SLICE_36/Q0 SLICE_26/C0 (933:1088:1244)(933:1088:1244)) + (INTERCONNECT SLICE_36/Q0 SLICE_34/C1 (1002:1166:1330)(1002:1166:1330)) + (INTERCONNECT SLICE_36/Q0 SLICE_34/C0 (1002:1166:1330)(1002:1166:1330)) + (INTERCONNECT SLICE_36/Q0 SLICE_36/A0 (487:587:687)(487:587:687)) + (INTERCONNECT SLICE_36/Q0 SLICE_37/A1 (741:869:998)(741:869:998)) + (INTERCONNECT SLICE_36/Q0 SLICE_43/C1 (997:1160:1324)(997:1160:1324)) + (INTERCONNECT SLICE_36/Q0 SLICE_46/A0 (1132:1298:1464)(1132:1298:1464)) + (INTERCONNECT SLICE_36/Q0 SLICE_62/B0 (776:904:1032)(776:904:1032)) + (INTERCONNECT SLICE_36/Q0 SLICE_68/B0 (1491:1694:1898)(1491:1694:1898)) + (INTERCONNECT SLICE_36/Q0 SLICE_75/D1 (1355:1495:1636)(1355:1495:1636)) + (INTERCONNECT SLICE_36/Q0 SLICE_79/B1 (1116:1287:1458)(1116:1287:1458)) + (INTERCONNECT SLICE_36/Q0 SLICE_106/D1 (1683:1858:2034)(1683:1858:2034)) + (INTERCONNECT SLICE_36/Q0 SLICE_106/A0 (1566:1772:1978)(1566:1772:1978)) + (INTERCONNECT SLICE_36/Q0 SLICE_122/A0 (744:869:995)(744:869:995)) + (INTERCONNECT SLICE_26/F0 SLICE_26/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/F1 nRRAS_MGIOL/OPOS (1809:1979:2150)(1809:1979:2150)) + (INTERCONNECT SLICE_27/Q0 SLICE_27/D1 (536:595:654)(536:595:654)) + (INTERCONNECT SLICE_27/Q0 SLICE_27/A0 (481:575:669)(481:575:669)) + (INTERCONNECT SLICE_27/Q0 SLICE_28/A1 (761:889:1018)(761:889:1018)) + (INTERCONNECT SLICE_27/Q0 SLICE_28/A0 (761:889:1018)(761:889:1018)) + (INTERCONNECT SLICE_27/Q0 SLICE_36/D1 (536:595:654)(536:595:654)) + (INTERCONNECT SLICE_27/Q0 SLICE_79/A0 (761:889:1018)(761:889:1018)) + (INTERCONNECT SLICE_27/Q0 SLICE_83/A1 (1125:1285:1445)(1125:1285:1445)) + (INTERCONNECT SLICE_27/Q1 SLICE_27/A1 (483:579:675)(483:579:675)) + (INTERCONNECT SLICE_27/Q1 SLICE_28/C1 (544:667:790)(544:667:790)) + (INTERCONNECT SLICE_27/Q1 SLICE_28/C0 (544:667:790)(544:667:790)) + (INTERCONNECT SLICE_27/Q1 SLICE_36/C1 (538:652:766)(538:652:766)) + (INTERCONNECT SLICE_27/Q1 SLICE_79/B0 (772:896:1020)(772:896:1020)) + (INTERCONNECT SLICE_27/Q1 SLICE_83/C1 (810:967:1125)(810:967:1125)) + (INTERCONNECT SLICE_27/F1 SLICE_27/DI1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_27/F0 SLICE_27/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_27/F1 SLICE_28/CE (601:672:744)(601:672:744)) - (INTERCONNECT SLICE_27/F1 SLICE_28/CE (601:672:744)(601:672:744)) - (INTERCONNECT SLICE_27/F1 SLICE_29/CE (601:672:744)(601:672:744)) - (INTERCONNECT SLICE_28/Q0 SLICE_28/B1 (808:941:1074)(808:941:1074)) - (INTERCONNECT SLICE_28/Q0 SLICE_28/A0 (481:575:669)(481:575:669)) - (INTERCONNECT SLICE_28/Q0 SLICE_29/A1 (776:906:1037)(776:906:1037)) - (INTERCONNECT SLICE_28/Q0 SLICE_29/A0 (776:906:1037)(776:906:1037)) - (INTERCONNECT SLICE_28/Q0 SLICE_37/B1 (777:906:1036)(777:906:1036)) - (INTERCONNECT SLICE_28/Q0 SLICE_78/C0 (577:697:817)(577:697:817)) - (INTERCONNECT SLICE_28/Q0 SLICE_114/D0 (566:631:696)(566:631:696)) - (INTERCONNECT SLICE_28/Q1 SLICE_28/A1 (483:579:675)(483:579:675)) - (INTERCONNECT SLICE_28/Q1 SLICE_29/D1 (548:611:674)(548:611:674)) - (INTERCONNECT SLICE_28/Q1 SLICE_29/D0 (548:611:674)(548:611:674)) - (INTERCONNECT SLICE_28/Q1 SLICE_37/D1 (530:586:642)(530:586:642)) - (INTERCONNECT SLICE_28/Q1 SLICE_78/D0 (527:586:645)(527:586:645)) - (INTERCONNECT SLICE_28/Q1 SLICE_114/C0 (559:677:795)(559:677:795)) - (INTERCONNECT SLICE_28/F1 SLICE_28/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_122/F0 SLICE_27/CE (882:979:1076)(882:979:1076)) + (INTERCONNECT SLICE_122/F0 SLICE_27/CE (882:979:1076)(882:979:1076)) + (INTERCONNECT SLICE_122/F0 SLICE_28/CE (882:979:1076)(882:979:1076)) + (INTERCONNECT SLICE_79/F1 SLICE_28/D1 (523:579:635)(523:579:635)) + (INTERCONNECT SLICE_79/F1 SLICE_79/C0 (280:362:445)(280:362:445)) (INTERCONNECT SLICE_28/F0 SLICE_28/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_28/F1 SLICE_68/C1 (534:639:744)(534:639:744)) + (INTERCONNECT SLICE_29/Q0 SLICE_29/A1 (762:894:1027)(762:894:1027)) + (INTERCONNECT SLICE_29/Q0 SLICE_29/A0 (487:587:687)(487:587:687)) + (INTERCONNECT SLICE_29/Q0 SLICE_30/D1 (1363:1504:1646)(1363:1504:1646)) + (INTERCONNECT SLICE_29/Q0 SLICE_34/B1 (1692:1897:2102)(1692:1897:2102)) + (INTERCONNECT SLICE_29/Q0 SLICE_36/C0 (2382:2651:2921)(2382:2651:2921)) + (INTERCONNECT SLICE_29/Q0 SLICE_37/B1 (2613:2895:3178)(2613:2895:3178)) + (INTERCONNECT SLICE_29/Q0 SLICE_45/A1 (2061:2303:2545)(2061:2303:2545)) + (INTERCONNECT SLICE_29/Q0 SLICE_48/A1 (2871:3192:3514)(2871:3192:3514)) + (INTERCONNECT SLICE_29/Q0 SLICE_48/A0 (2871:3192:3514)(2871:3192:3514)) + (INTERCONNECT SLICE_29/Q0 SLICE_49/A1 (2871:3192:3514)(2871:3192:3514)) + (INTERCONNECT SLICE_29/Q0 SLICE_49/A0 (2871:3192:3514)(2871:3192:3514)) + (INTERCONNECT SLICE_29/Q0 SLICE_50/A1 (2871:3192:3514)(2871:3192:3514)) + (INTERCONNECT SLICE_29/Q0 SLICE_50/A0 (2871:3192:3514)(2871:3192:3514)) + (INTERCONNECT SLICE_29/Q0 SLICE_51/B0 (779:919:1059)(779:919:1059)) + (INTERCONNECT SLICE_29/Q0 SLICE_52/C0 (2662:2972:3282)(2662:2972:3282)) + (INTERCONNECT SLICE_29/Q0 SLICE_53/A0 (1455:1663:1872)(1455:1663:1872)) + (INTERCONNECT SLICE_29/Q0 SLICE_54/C1 (1256:1454:1652)(1256:1454:1652)) + (INTERCONNECT SLICE_29/Q0 SLICE_57/B1 (1810:2051:2292)(1810:2051:2292)) + (INTERCONNECT SLICE_29/Q0 SLICE_58/A1 (762:894:1027)(762:894:1027)) + (INTERCONNECT SLICE_29/Q0 SLICE_58/A0 (762:894:1027)(762:894:1027)) + (INTERCONNECT SLICE_29/Q0 wb_adr_5_i_0_1\[0\]\/SLICE_60/D0 (2215:2423:2631) + (2215:2423:2631)) + (INTERCONNECT SLICE_29/Q0 SLICE_61/D1 (538:616:694)(538:616:694)) + (INTERCONNECT SLICE_29/Q0 SLICE_61/D0 (538:616:694)(538:616:694)) + (INTERCONNECT SLICE_29/Q0 SLICE_62/D1 (1450:1587:1724)(1450:1587:1724)) + (INTERCONNECT SLICE_29/Q0 SLICE_64/B1 (1061:1237:1413)(1061:1237:1413)) + (INTERCONNECT SLICE_29/Q0 SLICE_64/B0 (1061:1237:1413)(1061:1237:1413)) + (INTERCONNECT SLICE_29/Q0 SLICE_67/C0 (1215:1411:1608)(1215:1411:1608)) + (INTERCONNECT SLICE_29/Q0 SLICE_70/D0 (1204:1345:1487)(1204:1345:1487)) + (INTERCONNECT SLICE_29/Q0 SLICE_81/A0 (2861:3181:3502)(2861:3181:3502)) + (INTERCONNECT SLICE_29/Q0 SLICE_82/B0 (1061:1237:1413)(1061:1237:1413)) + (INTERCONNECT SLICE_29/Q0 SLICE_86/B0 (1487:1698:1909)(1487:1698:1909)) + (INTERCONNECT SLICE_29/Q0 SLICE_91/D0 (538:616:694)(538:616:694)) + (INTERCONNECT SLICE_29/Q0 SLICE_93/C1 (1862:2093:2325)(1862:2093:2325)) + (INTERCONNECT SLICE_29/Q0 SLICE_94/B1 (780:926:1072)(780:926:1072)) + (INTERCONNECT SLICE_29/Q0 SLICE_100/C0 (552:674:797)(552:674:797)) + (INTERCONNECT SLICE_29/Q0 SLICE_107/A1 (1414:1621:1828)(1414:1621:1828)) + (INTERCONNECT SLICE_29/Q0 SLICE_107/A0 (1414:1621:1828)(1414:1621:1828)) + (INTERCONNECT SLICE_29/Q0 SLICE_111/A1 (3188:3543:3899)(3188:3543:3899)) + (INTERCONNECT SLICE_29/Q0 SLICE_111/C0 (2662:2972:3282)(2662:2972:3282)) + (INTERCONNECT SLICE_29/Q0 SLICE_122/D1 (2735:2981:3227)(2735:2981:3227)) + (INTERCONNECT SLICE_99/F1 SLICE_29/D0 (523:573:623)(523:573:623)) (INTERCONNECT SLICE_29/F0 SLICE_29/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_29/F1 SLICE_62/C0 (536:647:758)(536:647:758)) - (INTERCONNECT SLICE_29/F1 SLICE_81/D0 (1228:1354:1481)(1228:1354:1481)) - (INTERCONNECT SLICE_29/F1 SLICE_90/A1 (1765:1992:2219)(1765:1992:2219)) - (INTERCONNECT SLICE_101/F1 SLICE_30/D1 (800:885:971)(800:885:971)) - (INTERCONNECT SLICE_101/F1 SLICE_63/C1 (1181:1353:1526)(1181:1353:1526)) - (INTERCONNECT SLICE_101/F1 SLICE_65/B1 (1733:1953:2173)(1733:1953:2173)) - (INTERCONNECT SLICE_101/F1 SLICE_67/C1 (1181:1353:1526)(1181:1353:1526)) - (INTERCONNECT SLICE_103/F1 SLICE_30/A1 (730:848:967)(730:848:967)) - (INTERCONNECT SLICE_30/F1 SLICE_30/C0 (277:356:436)(277:356:436)) - (INTERCONNECT SLICE_30/Q0 SLICE_30/A0 (485:583:681)(485:583:681)) - (INTERCONNECT SLICE_30/Q0 SLICE_31/D1 (539:633:727)(539:633:727)) - (INTERCONNECT SLICE_30/Q0 SLICE_35/D1 (1456:1596:1736)(1456:1596:1736)) - (INTERCONNECT SLICE_30/Q0 SLICE_37/B0 (2068:2308:2548)(2068:2308:2548)) - (INTERCONNECT SLICE_30/Q0 SLICE_38/B1 (2068:2308:2548)(2068:2308:2548)) - (INTERCONNECT SLICE_30/Q0 SLICE_46/B1 (781:943:1105)(781:943:1105)) - (INTERCONNECT SLICE_30/Q0 SLICE_49/A1 (1836:2099:2363)(1836:2099:2363)) - (INTERCONNECT SLICE_30/Q0 SLICE_49/A0 (1836:2099:2363)(1836:2099:2363)) - (INTERCONNECT SLICE_30/Q0 SLICE_50/C1 (1637:1890:2143)(1637:1890:2143)) - (INTERCONNECT SLICE_30/Q0 SLICE_50/C0 (1637:1890:2143)(1637:1890:2143)) - (INTERCONNECT SLICE_30/Q0 SLICE_51/B1 (1868:2134:2400)(1868:2134:2400)) - (INTERCONNECT SLICE_30/Q0 SLICE_51/B0 (1868:2134:2400)(1868:2134:2400)) - (INTERCONNECT SLICE_30/Q0 SLICE_52/D0 (535:605:675)(535:605:675)) - (INTERCONNECT SLICE_30/Q0 SLICE_53/B0 (1063:1261:1459)(1063:1261:1459)) - (INTERCONNECT SLICE_30/Q0 SLICE_54/A1 (1411:1639:1868)(1411:1639:1868)) - (INTERCONNECT SLICE_30/Q0 SLICE_54/A0 (1411:1639:1868)(1411:1639:1868)) - (INTERCONNECT SLICE_30/Q0 SLICE_55/B1 (1818:2081:2345)(1818:2081:2345)) - (INTERCONNECT SLICE_30/Q0 SLICE_58/D1 (540:603:666)(540:603:666)) - (INTERCONNECT SLICE_30/Q0 SLICE_59/B1 (1063:1261:1459)(1063:1261:1459)) - (INTERCONNECT SLICE_30/Q0 SLICE_59/B0 (1063:1261:1459)(1063:1261:1459)) - (INTERCONNECT SLICE_30/Q0 SLICE_61/B1 (777:915:1053)(777:915:1053)) - (INTERCONNECT SLICE_30/Q0 SLICE_61/B0 (777:915:1053)(777:915:1053)) - (INTERCONNECT SLICE_30/Q0 SLICE_62/D1 (1446:1580:1714)(1446:1580:1714)) - (INTERCONNECT SLICE_30/Q0 SLICE_84/B0 (1818:2081:2345)(1818:2081:2345)) - (INTERCONNECT SLICE_30/Q0 SLICE_85/D0 (1201:1364:1527)(1201:1364:1527)) - (INTERCONNECT SLICE_30/Q0 SLICE_95/C0 (816:999:1183)(816:999:1183)) - (INTERCONNECT SLICE_30/Q0 SLICE_97/B0 (781:943:1105)(781:943:1105)) - (INTERCONNECT SLICE_30/Q0 SLICE_103/D0 (540:603:666)(540:603:666)) - (INTERCONNECT SLICE_30/Q0 SLICE_108/D1 (2273:2535:2798)(2273:2535:2798)) - (INTERCONNECT SLICE_30/Q0 SLICE_108/C0 (1957:2239:2522)(1957:2239:2522)) - (INTERCONNECT SLICE_30/Q0 SLICE_116/D1 (539:633:727)(539:633:727)) + (INTERCONNECT SLICE_29/F1 SLICE_51/LSR (552:616:681)(552:616:681)) + (INTERCONNECT SLICE_29/F1 SLICE_56/LSR (553:615:677)(553:615:677)) + (INTERCONNECT SLICE_29/F1 SLICE_58/LSR (553:615:677)(553:615:677)) + (INTERCONNECT ufmefb\/EFBInst_0/WBDATO1 SLICE_30/A1 (1747:1949:2152) + (1747:1949:2152)) + (INTERCONNECT SLICE_45/F1 SLICE_30/D0 (579:649:719)(579:649:719)) + (INTERCONNECT SLICE_45/F1 SLICE_45/C0 (280:362:445)(280:362:445)) + (INTERCONNECT SLICE_30/F1 SLICE_30/B0 (508:600:693)(508:600:693)) (INTERCONNECT SLICE_30/F0 SLICE_30/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT ufmefb\/EFBInst_0/WBDATO1 SLICE_31/C1 (1161:1328:1496) - (1161:1328:1496)) - (INTERCONNECT SLICE_31/F1 SLICE_31/C0 (277:356:436)(277:356:436)) - (INTERCONNECT SLICE_46/F1 SLICE_31/A0 (733:854:976)(733:854:976)) - (INTERCONNECT SLICE_46/F1 SLICE_46/C0 (280:362:445)(280:362:445)) - (INTERCONNECT SLICE_31/F0 SLICE_31/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_47/Q0 SLICE_32/D1 (1887:2040:2194)(1887:2040:2194)) - (INTERCONNECT SLICE_47/Q0 SLICE_102/A1 (1193:1358:1524)(1193:1358:1524)) - (INTERCONNECT SLICE_47/Q0 SLICE_102/A0 (1193:1358:1524)(1193:1358:1524)) - (INTERCONNECT SLICE_47/Q0 SLICE_109/C1 (2642:2915:3188)(2642:2915:3188)) - (INTERCONNECT SLICE_47/Q0 SLICE_110/A1 (1193:1358:1524)(1193:1358:1524)) - (INTERCONNECT SLICE_47/Q0 SLICE_110/C0 (1321:1511:1701)(1321:1511:1701)) - (INTERCONNECT SLICE_47/Q0 SLICE_111/D1 (3011:3262:3513)(3011:3262:3513)) - (INTERCONNECT SLICE_47/Q0 SLICE_111/D0 (3011:3262:3513)(3011:3262:3513)) - (INTERCONNECT SLICE_47/Q0 SLICE_112/D1 (3011:3262:3513)(3011:3262:3513)) - (INTERCONNECT SLICE_47/Q0 SLICE_112/C0 (3349:3690:4031)(3349:3690:4031)) - (INTERCONNECT SLICE_47/Q0 SLICE_113/A1 (2841:3124:3408)(2841:3124:3408)) - (INTERCONNECT SLICE_47/Q0 SLICE_113/A0 (2841:3124:3408)(2841:3124:3408)) - (INTERCONNECT MAin\[4\]_I/PADDI SLICE_32/C1 (1992:2199:2406)(1992:2199:2406)) - (INTERCONNECT MAin\[4\]_I/PADDI SLICE_41/A0 (2970:3263:3556)(2970:3263:3556)) - (INTERCONNECT MAin\[4\]_I/PADDI SLICE_89/A1 (2919:3199:3480)(2919:3199:3480)) - (INTERCONNECT SLICE_41/Q0 SLICE_32/B1 (1462:1650:1838)(1462:1650:1838)) - (INTERCONNECT Din\[6\]_MGIOL/IN SLICE_32/D0 (1514:1658:1802)(1514:1658:1802)) - (INTERCONNECT Din\[4\]_MGIOL/IN SLICE_32/C0 (986:1141:1297)(986:1141:1297)) - (INTERCONNECT Din\[5\]_MGIOL/IN SLICE_32/B0 (1285:1461:1638)(1285:1461:1638)) - (INTERCONNECT Din\[7\]_MGIOL/IN SLICE_32/A0 (1806:2010:2215)(1806:2010:2215)) - (INTERCONNECT SLICE_32/Q0 SLICE_32/M1 (499:544:590)(499:544:590)) - (INTERCONNECT SLICE_32/Q0 SLICE_95/D1 (534:591:648)(534:591:648)) - (INTERCONNECT SLICE_32/Q0 SLICE_97/D1 (529:593:657)(529:593:657)) - (INTERCONNECT SLICE_32/Q0 SLICE_97/D0 (529:593:657)(529:593:657)) - (INTERCONNECT SLICE_32/Q0 SLICE_116/B0 (771:903:1035)(771:903:1035)) - (INTERCONNECT PHI2_MGIOL/IN SLICE_32/M0 (1817:1968:2119)(1817:1968:2119)) - (INTERCONNECT SLICE_32/F0 SLICE_75/C1 (800:939:1079)(800:939:1079)) - (INTERCONNECT SLICE_32/F1 RA\[4\]_I/PADDO (1916:2133:2351)(1916:2133:2351)) - (INTERCONNECT SLICE_32/Q1 SLICE_95/A1 (733:853:974)(733:853:974)) - (INTERCONNECT SLICE_32/Q1 SLICE_97/A1 (739:868:998)(739:868:998)) - (INTERCONNECT SLICE_32/Q1 SLICE_97/A0 (739:868:998)(739:868:998)) - (INTERCONNECT SLICE_32/Q1 SLICE_116/C0 (540:659:778)(540:659:778)) - (INTERCONNECT SLICE_73/Q0 SLICE_33/D1 (1008:1099:1191)(1008:1099:1191)) - (INTERCONNECT SLICE_73/Q0 SLICE_35/D0 (2075:2265:2456)(2075:2265:2456)) - (INTERCONNECT SLICE_73/Q0 SLICE_47/A1 (1952:2172:2393)(1952:2172:2393)) - (INTERCONNECT SLICE_73/Q0 SLICE_96/A1 (2649:2936:3224)(2649:2936:3224)) - (INTERCONNECT SLICE_33/F0 SLICE_33/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_33/Q0 SLICE_33/M1 (488:531:575)(488:531:575)) - (INTERCONNECT SLICE_33/Q0 SLICE_36/B0 (1139:1298:1457)(1139:1298:1457)) - (INTERCONNECT SLICE_33/F1 LED_I/PADDO (1475:1620:1766)(1475:1620:1766)) - (INTERCONNECT SLICE_86/F1 SLICE_34/A0 (1511:1715:1920)(1511:1715:1920)) - (INTERCONNECT SLICE_86/F1 SLICE_63/A0 (1184:1353:1523)(1184:1353:1523)) - (INTERCONNECT SLICE_86/F1 SLICE_83/C0 (539:650:761)(539:650:761)) - (INTERCONNECT SLICE_86/F1 SLICE_86/B0 (767:894:1021)(767:894:1021)) - (INTERCONNECT SLICE_34/F0 SLICE_56/C1 (800:939:1079)(800:939:1079)) - (INTERCONNECT SLICE_34/Q0 SLICE_36/C0 (1447:1632:1817)(1447:1632:1817)) - (INTERCONNECT SLICE_34/F1 SLICE_91/A0 (476:566:656)(476:566:656)) - (INTERCONNECT SLICE_44/F0 SLICE_35/A1 (740:864:989)(740:864:989)) - (INTERCONNECT SLICE_44/F0 SLICE_44/C1 (284:372:461)(284:372:461)) - (INTERCONNECT SLICE_44/F0 SLICE_44/DI0 (7:16:25)(7:16:25)) - (INTERCONNECT SLICE_44/F0 SLICE_90/B0 (779:913:1048)(779:913:1048)) - (INTERCONNECT SLICE_105/F0 SLICE_35/C0 (846:994:1143)(846:994:1143)) - (INTERCONNECT SLICE_35/F1 SLICE_35/A0 (730:848:967)(730:848:967)) + (INTERCONNECT CROW\[0\]_I/PADDI SLICE_31/C0 (1841:2049:2258)(1841:2049:2258)) + (INTERCONNECT SLICE_37/Q0 SLICE_31/B0 (1344:1515:1687)(1344:1515:1687)) + (INTERCONNECT SLICE_37/Q0 SLICE_37/A0 (483:579:675)(483:579:675)) + (INTERCONNECT SLICE_37/Q0 SLICE_38/B1 (1711:1918:2126)(1711:1918:2126)) + (INTERCONNECT SLICE_37/Q0 SLICE_38/B0 (1711:1918:2126)(1711:1918:2126)) + (INTERCONNECT SLICE_37/Q0 SLICE_39/B1 (1702:1903:2105)(1702:1903:2105)) + (INTERCONNECT SLICE_37/Q0 SLICE_39/B0 (1702:1903:2105)(1702:1903:2105)) + (INTERCONNECT SLICE_37/Q0 SLICE_40/A1 (2049:2286:2523)(2049:2286:2523)) + (INTERCONNECT SLICE_37/Q0 SLICE_40/A0 (2049:2286:2523)(2049:2286:2523)) + (INTERCONNECT SLICE_37/Q0 SLICE_41/B1 (1702:1903:2105)(1702:1903:2105)) + (INTERCONNECT SLICE_37/Q0 SLICE_41/B0 (1702:1903:2105)(1702:1903:2105)) + (INTERCONNECT SLICE_37/Q0 SLICE_42/C1 (1480:1674:1869)(1480:1674:1869)) + (INTERCONNECT SLICE_37/Q0 SLICE_42/C0 (1480:1674:1869)(1480:1674:1869)) + (INTERCONNECT SLICE_37/Q0 SLICE_120/B1 (774:904:1034)(774:904:1034)) + (INTERCONNECT SLICE_37/Q0 SLICE_120/B0 (774:904:1034)(774:904:1034)) + (INTERCONNECT SLICE_31/Q0 SLICE_31/M1 (526:575:625)(526:575:625)) + (INTERCONNECT SLICE_31/Q0 SLICE_57/A1 (771:897:1024)(771:897:1024)) + (INTERCONNECT SLICE_31/Q0 SLICE_100/D1 (561:622:683)(561:622:683)) + (INTERCONNECT SLICE_31/Q0 SLICE_110/C1 (572:688:804)(572:688:804)) + (INTERCONNECT SLICE_31/Q0 SLICE_110/C0 (572:688:804)(572:688:804)) + (INTERCONNECT PHI2_MGIOL/IN SLICE_31/M0 (1817:1968:2119)(1817:1968:2119)) + (INTERCONNECT SLICE_31/F0 RBA\[0\]_MGIOL/OPOS (2759:2982:3206)(2759:2982:3206)) + (INTERCONNECT SLICE_31/F1 RCLKout_MGIOL/ONEG (1995:2157:2319)(1995:2157:2319)) + (INTERCONNECT SLICE_31/Q1 SLICE_57/C1 (562:676:790)(562:676:790)) + (INTERCONNECT SLICE_31/Q1 SLICE_100/B1 (793:920:1047)(793:920:1047)) + (INTERCONNECT SLICE_31/Q1 SLICE_110/A1 (761:885:1010)(761:885:1010)) + (INTERCONNECT SLICE_31/Q1 SLICE_110/A0 (761:885:1010)(761:885:1010)) + (INTERCONNECT SLICE_41/Q0 SLICE_32/C1 (531:639:747)(531:639:747)) + (INTERCONNECT MAin\[6\]_I/PADDI SLICE_32/B1 (2669:2915:3162)(2669:2915:3162)) + (INTERCONNECT MAin\[6\]_I/PADDI SLICE_41/D0 (2754:2967:3181)(2754:2967:3181)) + (INTERCONNECT MAin\[6\]_I/PADDI SLICE_90/D1 (2791:3001:3211)(2791:3001:3211)) + (INTERCONNECT SLICE_46/Q0 SLICE_32/A1 (1196:1362:1528)(1196:1362:1528)) + (INTERCONNECT SLICE_46/Q0 SLICE_108/D1 (978:1078:1179)(978:1078:1179)) + (INTERCONNECT SLICE_46/Q0 SLICE_108/D0 (978:1078:1179)(978:1078:1179)) + (INTERCONNECT SLICE_46/Q0 SLICE_112/B1 (1919:2154:2389)(1919:2154:2389)) + (INTERCONNECT SLICE_46/Q0 SLICE_113/C1 (1820:2044:2268)(1820:2044:2268)) + (INTERCONNECT SLICE_46/Q0 SLICE_113/A0 (1671:1866:2062)(1671:1866:2062)) + (INTERCONNECT SLICE_46/Q0 SLICE_114/B1 (2041:2276:2511)(2041:2276:2511)) + (INTERCONNECT SLICE_46/Q0 SLICE_114/A0 (1671:1866:2062)(1671:1866:2062)) + (INTERCONNECT SLICE_46/Q0 SLICE_115/D1 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SLICE_42/C1 (2429:2662:2896)(2429:2662:2896)) - (INTERCONNECT MAin\[7\]_I/PADDI SLICE_89/D1 (3109:3354:3599)(3109:3354:3599)) - (INTERCONNECT MAin\[7\]_I/PADDI SLICE_111/B0 (2660:2906:3153)(2660:2906:3153)) - (INTERCONNECT MAin\[6\]_I/PADDI SLICE_42/C0 (2424:2657:2890)(2424:2657:2890)) - (INTERCONNECT MAin\[6\]_I/PADDI SLICE_109/D0 (3275:3531:3788)(3275:3531:3788)) - (INTERCONNECT MAin\[6\]_I/PADDI SLICE_112/D0 (2751:2966:3181)(2751:2966:3181)) + (INTERCONNECT SLICE_41/Q1 SLICE_116/D1 (1220:1340:1460)(1220:1340:1460)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_42/D1 (2424:2598:2772)(2424:2598:2772)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_108/C1 (1989:2191:2394)(1989:2191:2394)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_108/C0 (1989:2191:2394)(1989:2191:2394)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_115/B1 (2666:2908:3150)(2666:2908:3150)) + (INTERCONNECT MAin\[8\]_I/PADDI SLICE_42/D0 (2868:3072:3277)(2868:3072:3277)) + (INTERCONNECT MAin\[8\]_I/PADDI SLICE_113/A1 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(762:883:1004)(762:883:1004)) + (INTERCONNECT SLICE_44/F0 SLICE_44/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_110/F1 SLICE_45/D1 (789:873:958)(789:873:958)) + (INTERCONNECT SLICE_66/F0 SLICE_45/C1 (800:939:1079)(800:939:1079)) + (INTERCONNECT SLICE_111/F1 SLICE_45/D0 (530:587:645)(530:587:645)) (INTERCONNECT SLICE_45/F0 SLICE_45/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_67/F1 SLICE_46/D1 (523:573:623)(523:573:623)) - (INTERCONNECT SLICE_116/F0 SLICE_46/A1 (730:848:967)(730:848:967)) - (INTERCONNECT SLICE_108/F1 SLICE_46/D0 (789:873:958)(789:873:958)) + (INTERCONNECT SLICE_77/Q0 SLICE_46/C1 (911:1055:1200)(911:1055:1200)) + (INTERCONNECT SLICE_77/Q0 SLICE_103/B0 (1506:1695:1884)(1506:1695:1884)) + (INTERCONNECT SLICE_46/F1 SLICE_46/C0 (280:362:445)(280:362:445)) + (INTERCONNECT SLICE_46/F1 SLICE_101/D1 (269:296:324)(269:296:324)) + (INTERCONNECT SLICE_117/F1 SLICE_46/B0 (508:600:693)(508:600:693)) (INTERCONNECT SLICE_46/F0 SLICE_46/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_76/Q0 SLICE_47/C1 (1019:1165:1312)(1019:1165:1312)) - (INTERCONNECT SLICE_76/Q0 SLICE_92/D0 (1378:1501:1625)(1378:1501:1625)) - (INTERCONNECT SLICE_76/Q0 SLICE_117/B0 (1620:1811:2003)(1620:1811:2003)) - (INTERCONNECT SLICE_47/F1 SLICE_47/C0 (277:356:436)(277:356:436)) - (INTERCONNECT SLICE_47/F0 SLICE_47/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_68/F0 SLICE_47/LSR (542:602:662)(542:602:662)) + (INTERCONNECT SLICE_68/F0 SLICE_46/LSR (879:978:1078)(879:978:1078)) (INTERCONNECT SLICE_68/F0 SLICE_68/B1 (765:889:1013)(765:889:1013)) - (INTERCONNECT SLICE_107/F1 SLICE_48/D1 (269:296:324)(269:296:324)) - (INTERCONNECT SLICE_107/F1 SLICE_77/C0 (534:645:756)(534:645:756)) - (INTERCONNECT SLICE_61/F0 SLICE_48/A1 (1430:1615:1801)(1430:1615:1801)) - (INTERCONNECT SLICE_77/F0 SLICE_48/D0 (266:290:315)(266:290:315)) - (INTERCONNECT SLICE_107/F0 SLICE_48/C0 (531:639:747)(531:639:747)) - (INTERCONNECT SLICE_99/F1 SLICE_48/A0 (738:859:981)(738:859:981)) - (INTERCONNECT SLICE_99/F1 SLICE_69/B1 (772:902:1032)(772:902:1032)) - (INTERCONNECT SLICE_99/F1 SLICE_79/A0 (1006:1168:1330)(1006:1168:1330)) - (INTERCONNECT SLICE_99/F1 SLICE_80/D0 (271:301:332)(271:301:332)) - (INTERCONNECT SLICE_48/F1 SLICE_48/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_48/F0 SLICE_48/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_95/F0 SLICE_48/CE (1315:1452:1589)(1315:1452:1589)) - (INTERCONNECT SLICE_95/F0 SLICE_48/CE (1315:1452:1589)(1315:1452:1589)) - (INTERCONNECT SLICE_95/F0 SLICE_49/CE (1450:1581:1712)(1450:1581:1712)) - (INTERCONNECT SLICE_95/F0 SLICE_49/CE (1450:1581:1712)(1450:1581:1712)) - (INTERCONNECT SLICE_95/F0 SLICE_50/CE (1450:1581:1712)(1450:1581:1712)) - (INTERCONNECT SLICE_95/F0 SLICE_50/CE (1450:1581:1712)(1450:1581:1712)) - (INTERCONNECT SLICE_95/F0 SLICE_51/CE (1450:1581:1712)(1450:1581:1712)) - (INTERCONNECT SLICE_95/F0 SLICE_51/CE (1450:1581:1712)(1450:1581:1712)) - (INTERCONNECT SLICE_95/F0 SLICE_53/CE (1455:1586:1718)(1455:1586:1718)) - (INTERCONNECT SLICE_95/F0 SLICE_53/CE (1455:1586:1718)(1455:1586:1718)) - (INTERCONNECT SLICE_95/F0 SLICE_54/CE (1825:1988:2152)(1825:1988:2152)) - (INTERCONNECT SLICE_95/F0 SLICE_54/CE (1825:1988:2152)(1825:1988:2152)) - (INTERCONNECT SLICE_95/F0 SLICE_55/CE (2189:2384:2579)(2189:2384:2579)) - (INTERCONNECT SLICE_95/F0 SLICE_55/CE (2189:2384:2579)(2189:2384:2579)) - (INTERCONNECT SLICE_95/F0 SLICE_56/CE (1455:1586:1718)(1455:1586:1718)) - (INTERCONNECT SLICE_95/F0 SLICE_56/CE (1455:1586:1718)(1455:1586:1718)) - (INTERCONNECT SLICE_95/F0 SLICE_59/CE (1819:1982:2145)(1819:1982:2145)) - (INTERCONNECT SLICE_48/Q0 SLICE_61/C0 (536:647:758)(536:647:758)) + (INTERCONNECT SLICE_105/F0 SLICE_47/D1 (266:290:315)(266:290:315)) + (INTERCONNECT SLICE_107/F0 SLICE_47/C1 (534:639:744)(534:639:744)) + (INTERCONNECT SLICE_71/F0 SLICE_47/B1 (508:600:693)(508:600:693)) + (INTERCONNECT SLICE_122/F1 SLICE_47/A1 (1305:1468:1631)(1305:1468:1631)) + (INTERCONNECT SLICE_70/F0 SLICE_47/D0 (866:962:1058)(866:962:1058)) + (INTERCONNECT SLICE_70/F0 SLICE_70/C1 (534:645:756)(534:645:756)) + (INTERCONNECT SLICE_70/F0 SLICE_105/C0 (550:666:782)(550:666:782)) + (INTERCONNECT SLICE_118/F0 SLICE_47/C0 (806:946:1086)(806:946:1086)) + (INTERCONNECT SLICE_118/F0 SLICE_88/B0 (1771:1987:2204)(1771:1987:2204)) + (INTERCONNECT SLICE_118/F0 SLICE_93/D1 (1529:1677:1826)(1529:1677:1826)) + (INTERCONNECT SLICE_67/F1 SLICE_47/B0 (765:883:1001)(765:883:1001)) + (INTERCONNECT SLICE_91/F0 SLICE_47/A0 (733:848:964)(733:848:964)) + (INTERCONNECT SLICE_47/F1 SLICE_47/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_47/F0 SLICE_47/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F0 SLICE_47/CE (887:990:1093)(887:990:1093)) + (INTERCONNECT SLICE_100/F0 SLICE_47/CE (887:990:1093)(887:990:1093)) + (INTERCONNECT SLICE_100/F0 SLICE_48/CE (2006:2208:2410)(2006:2208:2410)) + (INTERCONNECT SLICE_100/F0 SLICE_48/CE (2006:2208:2410)(2006:2208:2410)) + (INTERCONNECT SLICE_100/F0 SLICE_49/CE (2006:2208:2410)(2006:2208:2410)) + (INTERCONNECT SLICE_100/F0 SLICE_49/CE (2006:2208:2410)(2006:2208:2410)) + (INTERCONNECT SLICE_100/F0 SLICE_50/CE (2006:2208:2410)(2006:2208:2410)) + (INTERCONNECT SLICE_100/F0 SLICE_50/CE (2006:2208:2410)(2006:2208:2410)) + (INTERCONNECT SLICE_100/F0 SLICE_52/CE (1621:1787:1954)(1621:1787:1954)) + (INTERCONNECT SLICE_100/F0 SLICE_52/CE (1621:1787:1954)(1621:1787:1954)) + (INTERCONNECT SLICE_100/F0 SLICE_53/CE (1363:1502:1641)(1363:1502:1641)) + (INTERCONNECT SLICE_100/F0 SLICE_53/CE (1363:1502:1641)(1363:1502:1641)) + (INTERCONNECT SLICE_100/F0 SLICE_54/CE (1363:1502:1641)(1363:1502:1641)) + (INTERCONNECT SLICE_100/F0 SLICE_54/CE (1363:1502:1641)(1363:1502:1641)) + (INTERCONNECT SLICE_100/F0 SLICE_55/CE (2091:2293:2495)(2091:2293:2495)) + (INTERCONNECT SLICE_100/F0 SLICE_55/CE (2091:2293:2495)(2091:2293:2495)) + (INTERCONNECT SLICE_100/F0 SLICE_58/CE (881:983:1086)(881:983:1086)) + (INTERCONNECT SLICE_47/Q0 SLICE_122/A1 (1308:1473:1638)(1308:1473:1638)) + (INTERCONNECT SLICE_47/Q0 + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI0in (1340:1473:1606) + (1340:1473:1606)) + (INTERCONNECT SLICE_47/Q1 SLICE_48/C0 (1345:1528:1712)(1345:1528:1712)) + (INTERCONNECT SLICE_47/Q1 + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI1in (1451:1590:1730) + (1451:1590:1730)) + (INTERCONNECT SLICE_48/Q0 SLICE_48/C1 (534:644:754)(534:644:754)) (INTERCONNECT SLICE_48/Q0 - ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI0in (1666:1838:2010) - (1666:1838:2010)) - (INTERCONNECT SLICE_48/Q1 SLICE_49/C0 (911:1055:1200)(911:1055:1200)) - (INTERCONNECT SLICE_48/Q1 - ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI1in (1381:1513:1645) - (1381:1513:1645)) - (INTERCONNECT SLICE_49/Q0 SLICE_49/D1 (523:578:633)(523:578:633)) - (INTERCONNECT SLICE_49/Q0 ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI2in (909:1006:1104) (909:1006:1104)) + (INTERCONNECT SLICE_48/F1 SLICE_48/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_48/F0 SLICE_48/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_48/Q1 SLICE_49/B0 (765:888:1011)(765:888:1011)) + (INTERCONNECT SLICE_48/Q1 + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI3in (1236:1368:1501) + (1236:1368:1501)) + (INTERCONNECT SLICE_49/Q0 SLICE_49/D1 (523:578:633)(523:578:633)) + (INTERCONNECT SLICE_49/Q0 + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI4in (1378:1511:1645) + (1378:1511:1645)) + (INTERCONNECT SLICE_91/F1 SLICE_49/C1 (991:1149:1308)(991:1149:1308)) + (INTERCONNECT SLICE_91/F1 SLICE_49/C0 (991:1149:1308)(991:1149:1308)) + (INTERCONNECT SLICE_91/F1 SLICE_50/B0 (1222:1393:1565)(1222:1393:1565)) + (INTERCONNECT SLICE_91/F1 SLICE_91/C0 (282:367:453)(282:367:453)) + (INTERCONNECT SLICE_91/F1 SLICE_122/B1 (1588:1791:1995)(1588:1791:1995)) (INTERCONNECT SLICE_49/F1 SLICE_49/DI1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_49/F0 SLICE_49/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_49/Q1 SLICE_50/A0 (733:853:974)(733:853:974)) + (INTERCONNECT SLICE_49/Q1 SLICE_50/C0 (534:644:754)(534:644:754)) (INTERCONNECT SLICE_49/Q1 - ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI3in (1014:1116:1218) - (1014:1116:1218)) - (INTERCONNECT SLICE_61/F1 SLICE_50/D1 (993:1109:1225)(993:1109:1225)) - (INTERCONNECT SLICE_61/F1 SLICE_50/D0 (993:1109:1225)(993:1109:1225)) - (INTERCONNECT SLICE_61/F1 SLICE_51/C0 (1004:1175:1346)(1004:1175:1346)) - (INTERCONNECT SLICE_61/F1 SLICE_52/C1 (544:670:796)(544:670:796)) - (INTERCONNECT SLICE_61/F1 SLICE_60/B1 (1610:1826:2043)(1610:1826:2043)) - (INTERCONNECT SLICE_61/F1 SLICE_61/D0 (533:604:675)(533:604:675)) - (INTERCONNECT SLICE_61/F1 SLICE_67/D1 (538:612:686)(538:612:686)) - (INTERCONNECT SLICE_61/F1 SLICE_72/B1 (1610:1826:2043)(1610:1826:2043)) - (INTERCONNECT SLICE_61/F1 SLICE_77/B1 (521:631:742)(521:631:742)) - (INTERCONNECT SLICE_61/F1 SLICE_79/C1 (575:707:840)(575:707:840)) - (INTERCONNECT SLICE_61/F1 SLICE_83/B0 (1610:1826:2043)(1610:1826:2043)) - (INTERCONNECT SLICE_61/F1 SLICE_84/D1 (934:1043:1153)(934:1043:1153)) - (INTERCONNECT SLICE_61/F1 SLICE_85/C1 (950:1115:1280)(950:1115:1280)) - (INTERCONNECT SLICE_61/F1 SLICE_86/C0 (815:978:1142)(815:978:1142)) - (INTERCONNECT SLICE_61/F1 SLICE_87/C0 (290:387:485)(290:387:485)) - (INTERCONNECT SLICE_61/F1 SLICE_88/C1 (575:707:840)(575:707:840)) - (INTERCONNECT SLICE_61/F1 SLICE_99/B1 (1181:1359:1537)(1181:1359:1537)) - (INTERCONNECT SLICE_61/F1 SLICE_99/B0 (1181:1359:1537)(1181:1359:1537)) - (INTERCONNECT SLICE_61/F1 SLICE_107/C1 (575:707:840)(575:707:840)) - (INTERCONNECT SLICE_61/F1 SLICE_108/B0 (1176:1353:1531)(1176:1353:1531)) - (INTERCONNECT SLICE_50/Q0 SLICE_50/A1 (733:853:974)(733:853:974)) + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI5in (1341:1478:1615) + (1341:1478:1615)) + (INTERCONNECT SLICE_50/Q0 SLICE_50/D1 (523:578:633)(523:578:633)) (INTERCONNECT SLICE_50/Q0 - ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI4in (909:1006:1104) + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI6in (909:1006:1104) (909:1006:1104)) (INTERCONNECT SLICE_50/F1 SLICE_50/DI1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_50/F0 SLICE_50/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_50/Q1 SLICE_51/A0 (733:853:974)(733:853:974)) (INTERCONNECT SLICE_50/Q1 - ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI5in (1341:1478:1615) - (1341:1478:1615)) - (INTERCONNECT SLICE_51/Q0 SLICE_51/D1 (523:578:633)(523:578:633)) - (INTERCONNECT SLICE_51/Q0 - ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI6in (909:1006:1104) - (909:1006:1104)) - (INTERCONNECT SLICE_51/F1 SLICE_51/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_51/F0 SLICE_51/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_51/Q1 ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI7in (906:1001:1097) (906:1001:1097)) - (INTERCONNECT SLICE_57/Q0 SLICE_52/B1 (1509:1700:1891)(1509:1700:1891)) - (INTERCONNECT SLICE_57/Q0 SLICE_57/A0 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_57/Q0 SLICE_87/D1 (1267:1390:1513)(1267:1390:1513)) - (INTERCONNECT SLICE_91/F0 SLICE_52/A1 (1005:1155:1306)(1005:1155:1306)) - (INTERCONNECT SLICE_91/F0 SLICE_87/A0 (1332:1517:1703)(1332:1517:1703)) - (INTERCONNECT SLICE_52/F1 SLICE_52/C0 (277:356:436)(277:356:436)) - (INTERCONNECT SLICE_97/F1 SLICE_52/A0 (999:1149:1299)(999:1149:1299)) + (INTERCONNECT SLICE_95/F0 SLICE_51/D1 (525:581:637)(525:581:637)) + (INTERCONNECT SLICE_95/F0 SLICE_89/D0 (525:581:637)(525:581:637)) + (INTERCONNECT SLICE_121/F0 SLICE_51/C1 (280:362:445)(280:362:445)) + (INTERCONNECT SLICE_121/F0 SLICE_89/D1 (269:296:324)(269:296:324)) + (INTERCONNECT SLICE_121/F1 SLICE_51/B1 (762:883:1004)(762:883:1004)) + (INTERCONNECT SLICE_64/F1 SLICE_51/A1 (740:867:995)(740:867:995)) + (INTERCONNECT SLICE_64/F1 wb_dati_5_1_iv_0_0_o2\[5\]\/SLICE_59/C1 (915:1073:1232) + (915:1073:1232)) + (INTERCONNECT SLICE_64/F1 wb_dati_5_1_iv_0_0_o2\[5\]\/SLICE_59/C0 (915:1073:1232) + (915:1073:1232)) + (INTERCONNECT SLICE_64/F1 SLICE_64/C0 (282:367:453)(282:367:453)) + (INTERCONNECT SLICE_64/F1 SLICE_66/A0 (1146:1310:1474)(1146:1310:1474)) + (INTERCONNECT SLICE_64/F1 SLICE_73/B0 (808:942:1077)(808:942:1077)) + (INTERCONNECT SLICE_64/F1 SLICE_74/B1 (808:942:1077)(808:942:1077)) + (INTERCONNECT SLICE_64/F1 SLICE_82/B1 (808:942:1077)(808:942:1077)) + (INTERCONNECT SLICE_64/F1 SLICE_84/C1 (947:1100:1254)(947:1100:1254)) + (INTERCONNECT SLICE_64/F1 SLICE_87/B1 (808:942:1077)(808:942:1077)) + (INTERCONNECT SLICE_64/F1 SLICE_88/C1 (941:1094:1247)(941:1094:1247)) + (INTERCONNECT SLICE_64/F1 SLICE_89/A0 (740:867:995)(740:867:995)) + (INTERCONNECT SLICE_110/F0 SLICE_51/D0 (789:873:958)(789:873:958)) + (INTERCONNECT SLICE_51/F1 SLICE_51/C0 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_51/F0 SLICE_51/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/F0 SLICE_51/CE (539:596:653)(539:596:653)) + (INTERCONNECT SLICE_51/Q0 ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBCYCIin + (1276:1403:1531)(1276:1403:1531)) + (INTERCONNECT SLICE_51/Q0 ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBSTBIin + (1622:1788:1955)(1622:1788:1955)) + (INTERCONNECT SLICE_85/F0 SLICE_52/D1 (520:573:626)(520:573:626)) + (INTERCONNECT SLICE_74/F1 SLICE_52/C1 (539:653:767)(539:653:767)) + (INTERCONNECT SLICE_74/F1 SLICE_54/C0 (1242:1426:1611)(1242:1426:1611)) + (INTERCONNECT SLICE_74/F1 SLICE_55/D0 (523:579:635)(523:579:635)) + (INTERCONNECT SLICE_74/F1 SLICE_74/C0 (1606:1822:2038)(1606:1822:2038)) + (INTERCONNECT SLICE_71/F1 SLICE_52/B1 (1161:1323:1485)(1161:1323:1485)) + (INTERCONNECT SLICE_71/F1 SLICE_55/A0 (1820:2046:2272)(1820:2046:2272)) + (INTERCONNECT SLICE_71/F1 SLICE_71/C0 (280:362:445)(280:362:445)) + (INTERCONNECT SLICE_71/F1 SLICE_86/A1 (1493:1684:1875)(1493:1684:1875)) + (INTERCONNECT SLICE_71/F1 SLICE_88/D0 (1246:1375:1504)(1246:1375:1504)) + (INTERCONNECT SLICE_71/F1 SLICE_93/B0 (781:910:1039)(781:910:1039)) + (INTERCONNECT SLICE_58/Q0 SLICE_52/D0 (1159:1275:1392)(1159:1275:1392)) + (INTERCONNECT SLICE_58/Q0 ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBWEIin + (1603:1765:1928)(1603:1765:1928)) + (INTERCONNECT SLICE_87/F1 SLICE_52/B0 (515:616:718)(515:616:718)) + (INTERCONNECT SLICE_87/F1 SLICE_81/B1 (779:913:1048)(779:913:1048)) + (INTERCONNECT SLICE_87/F1 SLICE_85/B0 (769:899:1029)(769:899:1029)) + (INTERCONNECT SLICE_87/F1 SLICE_87/C0 (284:372:461)(284:372:461)) + (INTERCONNECT SLICE_98/F0 SLICE_52/A0 (733:848:964)(733:848:964)) + (INTERCONNECT SLICE_52/F1 SLICE_52/DI1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_52/F0 SLICE_52/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_87/F0 SLICE_52/CE (539:596:653)(539:596:653)) - (INTERCONNECT SLICE_58/F1 SLICE_52/LSR (885:985:1085)(885:985:1085)) - (INTERCONNECT SLICE_58/F1 SLICE_57/LSR (553:615:677)(553:615:677)) - (INTERCONNECT SLICE_58/F1 SLICE_58/C0 (545:658:771)(545:658:771)) - (INTERCONNECT SLICE_58/F1 SLICE_59/LSR (1249:1380:1512)(1249:1380:1512)) - (INTERCONNECT SLICE_52/Q0 ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBCYCIin - (1087:1195:1303)(1087:1195:1303)) - (INTERCONNECT SLICE_52/Q0 ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBSTBIin - (1433:1580:1727)(1433:1580:1727)) - (INTERCONNECT SLICE_60/F1 SLICE_53/D1 (535:598:662)(535:598:662)) - (INTERCONNECT SLICE_60/F1 SLICE_60/B0 (767:894:1021)(767:894:1021)) - (INTERCONNECT SLICE_60/F1 SLICE_83/D0 (525:584:643)(525:584:643)) - (INTERCONNECT SLICE_116/F1 SLICE_53/C1 (541:653:766)(541:653:766)) - (INTERCONNECT SLICE_99/F0 SLICE_53/B1 (508:600:693)(508:600:693)) - (INTERCONNECT SLICE_80/F0 SLICE_53/A1 (733:854:976)(733:854:976)) - (INTERCONNECT SLICE_80/F0 SLICE_56/C0 (537:645:753)(537:645:753)) - (INTERCONNECT SLICE_100/F1 SLICE_53/D0 (520:573:626)(520:573:626)) - (INTERCONNECT SLICE_79/F1 SLICE_53/C0 (984:1147:1311)(984:1147:1311)) - (INTERCONNECT SLICE_79/F1 SLICE_56/A0 (1439:1636:1834)(1439:1636:1834)) - (INTERCONNECT SLICE_79/F1 SLICE_79/C0 (286:377:469)(286:377:469)) - (INTERCONNECT SLICE_79/F1 SLICE_82/A0 (739:869:1000)(739:869:1000)) - (INTERCONNECT SLICE_79/F1 SLICE_107/A0 (742:869:997)(742:869:997)) - (INTERCONNECT SLICE_59/Q0 SLICE_53/A0 (1436:1622:1808)(1436:1622:1808)) - (INTERCONNECT SLICE_59/Q0 ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBWEIin - (2034:2232:2430)(2034:2232:2430)) + (INTERCONNECT SLICE_52/Q0 SLICE_64/D0 (863:956:1049)(863:956:1049)) + (INTERCONNECT SLICE_52/Q0 + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI0in (1017:1117:1218) + (1017:1117:1218)) + (INTERCONNECT SLICE_52/Q1 SLICE_53/C0 (547:660:773)(547:660:773)) + (INTERCONNECT SLICE_52/Q1 + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI1in (1344:1479:1615) + (1344:1479:1615)) + (INTERCONNECT SLICE_104/F1 SLICE_53/D1 (1291:1422:1554)(1291:1422:1554)) + (INTERCONNECT SLICE_84/F1 SLICE_53/C1 (1246:1429:1612)(1246:1429:1612)) + (INTERCONNECT SLICE_84/F1 SLICE_55/B1 (786:915:1045)(786:915:1045)) + (INTERCONNECT SLICE_84/F1 SLICE_65/D1 (544:605:667)(544:605:667)) + (INTERCONNECT SLICE_84/F1 SLICE_84/C0 (280:362:445)(280:362:445)) + (INTERCONNECT SLICE_86/F0 SLICE_53/B1 (508:600:693)(508:600:693)) + (INTERCONNECT SLICE_87/F0 SLICE_53/A1 (733:848:964)(733:848:964)) + (INTERCONNECT wb_dati_5_1_iv_0_0_o2\[5\]\/SLICE_59/OFX0 SLICE_53/D0 (525:581:637) + (525:581:637)) + (INTERCONNECT wb_dati_5_1_iv_0_0_o2\[5\]\/SLICE_59/OFX0 SLICE_54/D1 (525:581:637) + (525:581:637)) (INTERCONNECT SLICE_53/F1 SLICE_53/DI1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_53/F0 SLICE_53/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_53/Q0 SLICE_116/B1 (1034:1188:1343)(1034:1188:1343)) + (INTERCONNECT SLICE_53/Q0 SLICE_86/D0 (900:989:1079)(900:989:1079)) (INTERCONNECT SLICE_53/Q0 - ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI0in (977:1082:1188) - (977:1082:1188)) - (INTERCONNECT SLICE_53/Q1 SLICE_54/C0 (1170:1341:1513)(1170:1341:1513)) + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI2in (1344:1479:1615) + (1344:1479:1615)) + (INTERCONNECT SLICE_53/Q1 SLICE_111/D0 (1222:1348:1474)(1222:1348:1474)) (INTERCONNECT SLICE_53/Q1 - ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI1in (1239:1370:1501) - (1239:1370:1501)) - (INTERCONNECT SLICE_54/Q0 SLICE_54/D1 (1227:1351:1476)(1227:1351:1476)) + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI3in (1272:1405:1538) + (1272:1405:1538)) + (INTERCONNECT SLICE_54/Q0 SLICE_54/A1 (733:853:974)(733:853:974)) (INTERCONNECT SLICE_54/Q0 - ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI2in (980:1084:1188) - (980:1084:1188)) - (INTERCONNECT SLICE_101/F0 SLICE_54/C1 (541:653:766)(541:653:766)) - (INTERCONNECT SLICE_60/F0 SLICE_54/B1 (762:883:1004)(762:883:1004)) - (INTERCONNECT SLICE_72/F1 SLICE_54/D0 (526:579:632)(526:579:632)) - (INTERCONNECT SLICE_72/F1 SLICE_55/A1 (744:867:991)(744:867:991)) - (INTERCONNECT SLICE_72/F1 SLICE_55/A0 (744:867:991)(744:867:991)) - (INTERCONNECT SLICE_83/F0 SLICE_54/B0 (511:606:702)(511:606:702)) - (INTERCONNECT SLICE_83/F0 SLICE_55/D1 (526:579:632)(526:579:632)) + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI4in (909:1006:1104) + (909:1006:1104)) + (INTERCONNECT SLICE_65/F1 SLICE_54/B0 (765:883:1001)(765:883:1001)) + (INTERCONNECT SLICE_111/F0 SLICE_54/A0 (740:863:986)(740:863:986)) (INTERCONNECT SLICE_54/F1 SLICE_54/DI1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_54/F0 SLICE_54/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_54/Q1 SLICE_59/D1 (1155:1277:1399)(1155:1277:1399)) + (INTERCONNECT SLICE_54/Q1 SLICE_81/C0 (802:947:1093)(802:947:1093)) (INTERCONNECT SLICE_54/Q1 - ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI3in (642:709:776) - (642:709:776)) - (INTERCONNECT SLICE_55/Q0 SLICE_55/C1 (802:947:1093)(802:947:1093)) - (INTERCONNECT SLICE_55/Q0 - ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI4in (1235:1371:1508) - (1235:1371:1508)) - (INTERCONNECT SLICE_79/F0 SLICE_55/C0 (541:653:766)(541:653:766)) - (INTERCONNECT SLICE_59/F1 SLICE_55/B0 (1031:1183:1336)(1031:1183:1336)) + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI5in (1339:1476:1613) + (1339:1476:1613)) + (INTERCONNECT SLICE_104/F0 SLICE_55/D1 (526:579:632)(526:579:632)) + (INTERCONNECT SLICE_104/F0 SLICE_73/C1 (544:659:775)(544:659:775)) + (INTERCONNECT SLICE_82/F0 SLICE_55/C1 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_74/F0 SLICE_55/A1 (730:848:967)(730:848:967)) + (INTERCONNECT SLICE_81/F0 SLICE_55/B0 (1031:1183:1336)(1031:1183:1336)) (INTERCONNECT SLICE_55/F1 SLICE_55/DI1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_55/F0 SLICE_55/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_55/Q1 SLICE_84/A0 (733:853:974)(733:853:974)) + (INTERCONNECT SLICE_55/Q0 SLICE_82/A0 (1369:1551:1733)(1369:1551:1733)) + (INTERCONNECT SLICE_55/Q0 + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI6in (912:1008:1104) + (912:1008:1104)) + (INTERCONNECT SLICE_55/Q1 SLICE_91/A0 (1177:1341:1505)(1177:1341:1505)) (INTERCONNECT SLICE_55/Q1 - ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI5in (1014:1116:1218) - (1014:1116:1218)) - (INTERCONNECT SLICE_82/F0 SLICE_56/D1 (523:573:623)(523:573:623)) - (INTERCONNECT SLICE_69/F1 SLICE_56/B1 (762:883:1004)(762:883:1004)) - (INTERCONNECT SLICE_88/F1 SLICE_56/A1 (736:854:973)(736:854:973)) - (INTERCONNECT SLICE_88/F1 SLICE_88/B0 (765:889:1013)(765:889:1013)) - (INTERCONNECT SLICE_84/F0 SLICE_56/D0 (530:587:645)(530:587:645)) - (INTERCONNECT SLICE_70/F1 SLICE_56/B0 (513:611:710)(513:611:710)) - (INTERCONNECT SLICE_70/F1 SLICE_70/B0 (767:894:1021)(767:894:1021)) - (INTERCONNECT SLICE_70/F1 SLICE_79/B0 (770:894:1018)(770:894:1018)) - (INTERCONNECT SLICE_56/F1 SLICE_56/DI1 (0:0:0)(0:0:0)) + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI7in (650:720:791) + (650:720:791)) + (INTERCONNECT SLICE_58/F1 SLICE_56/B1 (765:889:1013)(765:889:1013)) + (INTERCONNECT SLICE_58/F1 SLICE_58/D0 (523:579:635)(523:579:635)) + (INTERCONNECT SLICE_57/F1 SLICE_56/D0 (526:579:632)(526:579:632)) + (INTERCONNECT SLICE_57/F1 SLICE_57/C0 (280:362:445)(280:362:445)) + (INTERCONNECT SLICE_56/F1 SLICE_56/C0 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_56/Q0 SLICE_56/A0 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_56/Q0 SLICE_89/B1 (781:909:1037)(781:909:1037)) + (INTERCONNECT SLICE_56/Q0 SLICE_121/D1 (866:961:1056)(866:961:1056)) (INTERCONNECT SLICE_56/F0 SLICE_56/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_56/Q0 SLICE_108/D0 (523:578:633)(523:578:633)) - (INTERCONNECT SLICE_56/Q0 - ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI6in (1411:1555:1700) - (1411:1555:1700)) - (INTERCONNECT SLICE_56/Q1 SLICE_85/C0 (806:946:1086)(806:946:1086)) - (INTERCONNECT SLICE_56/Q1 - ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI7in (1603:1765:1928) - (1603:1765:1928)) - (INTERCONNECT SLICE_103/F0 SLICE_57/A1 (733:854:976)(733:854:976)) - (INTERCONNECT SLICE_103/F0 SLICE_63/D1 (803:891:980)(803:891:980)) - (INTERCONNECT SLICE_103/F0 SLICE_63/D0 (803:891:980)(803:891:980)) - (INTERCONNECT SLICE_103/F0 SLICE_71/A1 (1340:1529:1718)(1340:1529:1718)) - (INTERCONNECT SLICE_97/F0 SLICE_57/D0 (536:594:652)(536:594:652)) - (INTERCONNECT SLICE_97/F0 SLICE_58/D0 (863:956:1049)(863:956:1049)) - (INTERCONNECT SLICE_57/F1 SLICE_57/C0 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_94/F0 SLICE_57/B0 (1358:1545:1733)(1358:1545:1733)) + (INTERCONNECT SLICE_57/Q0 SLICE_57/A0 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_57/Q0 ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBRSTIin + (1859:2050:2241)(1859:2050:2241)) (INTERCONNECT SLICE_57/F0 SLICE_57/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_58/Q0 SLICE_58/A0 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_58/Q0 ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBRSTIin - (1495:1654:1814)(1495:1654:1814)) + (INTERCONNECT SLICE_70/F1 SLICE_58/C0 (800:939:1079)(800:939:1079)) (INTERCONNECT SLICE_58/F0 SLICE_58/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_84/F1 SLICE_59/C1 (919:1067:1215)(919:1067:1215)) - (INTERCONNECT SLICE_84/F1 SLICE_60/D0 (544:605:667)(544:605:667)) - (INTERCONNECT SLICE_84/F1 SLICE_84/C0 (280:362:445)(280:362:445)) - (INTERCONNECT SLICE_84/F1 SLICE_101/D0 (544:605:667)(544:605:667)) - (INTERCONNECT SLICE_83/F1 SLICE_59/A1 (1113:1271:1429)(1113:1271:1429)) - (INTERCONNECT SLICE_83/F1 SLICE_83/A0 (733:854:976)(733:854:976)) - (INTERCONNECT SLICE_83/F1 SLICE_99/A0 (1076:1237:1399)(1076:1237:1399)) - (INTERCONNECT SLICE_71/F1 SLICE_59/D0 (266:290:315)(266:290:315)) - (INTERCONNECT SLICE_63/F0 SLICE_59/C0 (531:639:747)(531:639:747)) - (INTERCONNECT SLICE_59/F0 SLICE_59/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_100/F0 SLICE_60/A1 (1174:1336:1498)(1174:1336:1498)) - (INTERCONNECT SLICE_98/F0 SLICE_60/A0 (999:1149:1299)(999:1149:1299)) - (INTERCONNECT SLICE_65/F1 SLICE_61/A0 (730:848:967)(730:848:967)) - (INTERCONNECT SLICE_62/F0 SLICE_96/A0 (999:1149:1299)(999:1149:1299)) - (INTERCONNECT SLICE_80/F1 SLICE_63/B1 (775:914:1053)(775:914:1053)) - (INTERCONNECT SLICE_80/F1 SLICE_65/C0 (810:970:1131)(810:970:1131)) - (INTERCONNECT SLICE_80/F1 SLICE_67/B1 (775:914:1053)(775:914:1053)) - (INTERCONNECT SLICE_80/F1 SLICE_80/B0 (769:899:1029)(769:899:1029)) - (INTERCONNECT SLICE_80/F1 SLICE_85/A1 (742:872:1003)(742:872:1003)) - (INTERCONNECT SLICE_80/F1 SLICE_101/C0 (1136:1325:1515)(1136:1325:1515)) - (INTERCONNECT SLICE_80/F1 SLICE_107/A1 (747:879:1011)(747:879:1011)) - (INTERCONNECT SLICE_63/F1 SLICE_63/C0 (277:356:436)(277:356:436)) - (INTERCONNECT Din\[6\]_I/PADDI SLICE_64/C1 (2385:2647:2910)(2385:2647:2910)) - (INTERCONNECT Din\[6\]_I/PADDI SLICE_73/A0 (2922:3232:3542)(2922:3232:3542)) - (INTERCONNECT Din\[6\]_I/PADDI SLICE_104/C1 (2755:3049:3344)(2755:3049:3344)) - (INTERCONNECT Din\[6\]_I/PADDI SLICE_104/C0 (2755:3049:3344)(2755:3049:3344)) - (INTERCONNECT Din\[6\]_I/PADDI SLICE_106/A0 (2922:3232:3542)(2922:3232:3542)) - (INTERCONNECT Din\[6\]_I/PADDI SLICE_115/C0 (2749:3043:3337)(2749:3043:3337)) - (INTERCONNECT Din\[6\]_I/PADDI RD\[6\]_MGIOL/OPOS (4065:4422:4779)(4065:4422:4779)) + (INTERCONNECT SLICE_73/F1 wb_dati_5_1_iv_0_0_o2\[5\]\/SLICE_59/D1 (526:579:632) + (526:579:632)) + (INTERCONNECT SLICE_73/F1 SLICE_73/C0 (280:362:445)(280:362:445)) + (INTERCONNECT SLICE_72/F0 wb_dati_5_1_iv_0_0_o2\[5\]\/SLICE_59/B1 (783:909:1036) + (783:909:1036)) + (INTERCONNECT SLICE_72/F0 wb_dati_5_1_iv_0_0_o2\[5\]\/SLICE_59/B0 (783:909:1036) + (783:909:1036)) + (INTERCONNECT SLICE_72/F0 SLICE_111/A0 (751:875:999)(751:875:999)) + (INTERCONNECT SLICE_85/F1 wb_dati_5_1_iv_0_0_o2\[5\]\/SLICE_59/D0 (523:579:635) + (523:579:635)) + (INTERCONNECT SLICE_85/F1 SLICE_85/C0 (545:658:771)(545:658:771)) + (INTERCONNECT SLICE_85/F1 SLICE_87/D0 (534:592:650)(534:592:650)) + (INTERCONNECT SLICE_97/F1 wb_adr_5_i_0_1\[0\]\/SLICE_60/C1 (546:664:783) + (546:664:783)) + (INTERCONNECT SLICE_97/F1 SLICE_84/B0 (513:611:710)(513:611:710)) + (INTERCONNECT SLICE_97/F1 SLICE_97/B0 (767:894:1021)(767:894:1021)) + (INTERCONNECT SLICE_67/F0 wb_adr_5_i_0_1\[0\]\/SLICE_60/B1 (511:606:702) + (511:606:702)) + (INTERCONNECT SLICE_67/F0 SLICE_67/A1 (733:854:976)(733:854:976)) + (INTERCONNECT SLICE_105/F1 wb_adr_5_i_0_1\[0\]\/SLICE_60/A0 (749:875:1002) + (749:875:1002)) + (INTERCONNECT SLICE_105/F1 SLICE_61/B1 (770:897:1024)(770:897:1024)) + (INTERCONNECT SLICE_105/F1 SLICE_70/A1 (749:875:1002)(749:875:1002)) + (INTERCONNECT SLICE_105/F1 SLICE_99/B1 (1467:1664:1861)(1467:1664:1861)) + (INTERCONNECT wb_adr_5_i_0_1\[0\]\/SLICE_60/OFX0 SLICE_67/C1 (531:639:747) + (531:639:747)) + (INTERCONNECT SLICE_61/F0 SLICE_61/C1 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_61/F1 SLICE_91/B0 (762:883:1004)(762:883:1004)) + (INTERCONNECT SLICE_62/F0 SLICE_69/D0 (526:579:632)(526:579:632)) + (INTERCONNECT SLICE_62/F0 SLICE_101/A0 (1002:1155:1308)(1002:1155:1308)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_63/D1 (2299:2498:2698)(2299:2498:2698)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_92/A0 (2509:2774:3039)(2509:2774:3039)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_96/C1 (2793:3082:3371)(2793:3082:3371)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_119/B1 (3024:3326:3628)(3024:3326:3628)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_120/C0 (3473:3827:4182)(3473:3827:4182)) + (INTERCONNECT Din\[6\]_I/PADDI RD\[6\]_MGIOL/OPOS (4488:4866:5245)(4488:4866:5245)) (INTERCONNECT Din\[6\]_I/PADDI Din\[6\]_MGIOL/DI (424:441:459)(424:441:459)) - (INTERCONNECT SLICE_65/F0 SLICE_65/C1 (277:356:436)(277:356:436)) - (INTERCONNECT SLICE_66/F1 SLICE_66/C0 (277:356:436)(277:356:436)) - (INTERCONNECT SLICE_66/F0 SLICE_86/A0 (730:848:967)(730:848:967)) - (INTERCONNECT SLICE_67/F0 SLICE_67/A1 (476:566:656)(476:566:656)) - (INTERCONNECT ufmefb\/EFBInst_0/WBACKO SLICE_67/A0 (1191:1357:1524) - (1191:1357:1524)) - (INTERCONNECT ufmefb\/EFBInst_0/WBACKO SLICE_87/D0 (1672:1839:2007) - (1672:1839:2007)) - (INTERCONNECT SLICE_78/F1 SLICE_68/C1 (544:659:775)(544:659:775)) - (INTERCONNECT SLICE_78/F1 SLICE_78/B0 (511:606:702)(511:606:702)) - (INTERCONNECT SLICE_114/F0 SLICE_68/A1 (1067:1225:1383)(1067:1225:1383)) - (INTERCONNECT SLICE_68/F1 SLICE_92/B1 (772:897:1023)(772:897:1023)) - (INTERCONNECT SLICE_69/F0 SLICE_69/C1 (531:639:747)(531:639:747)) - (INTERCONNECT SLICE_108/F0 SLICE_69/A1 (730:848:967)(730:848:967)) - (INTERCONNECT SLICE_70/F0 SLICE_108/A0 (730:848:967)(730:848:967)) - (INTERCONNECT SLICE_71/F0 SLICE_71/C1 (277:356:436)(277:356:436)) - (INTERCONNECT SLICE_72/F0 SLICE_72/C1 (277:356:436)(277:356:436)) - (INTERCONNECT SLICE_75/F0 SLICE_73/C0 (802:947:1093)(802:947:1093)) - (INTERCONNECT SLICE_75/F0 SLICE_74/C0 (536:647:758)(536:647:758)) - (INTERCONNECT SLICE_73/F1 SLICE_73/B0 (511:606:702)(511:606:702)) - (INTERCONNECT SLICE_73/F1 SLICE_106/B0 (511:606:702)(511:606:702)) - (INTERCONNECT Din\[3\]_MGIOL/IN SLICE_75/D1 (1150:1262:1375)(1150:1262:1375)) - (INTERCONNECT SLICE_89/F0 SLICE_75/B1 (765:883:1001)(765:883:1001)) - (INTERCONNECT Din\[1\]_MGIOL/IN SLICE_75/A1 (1290:1460:1631)(1290:1460:1631)) - (INTERCONNECT SLICE_76/F1 SLICE_76/A0 (730:848:967)(730:848:967)) - (INTERCONNECT SLICE_98/F1 SLICE_77/C1 (534:645:756)(534:645:756)) - (INTERCONNECT SLICE_98/F1 SLICE_79/D0 (526:579:632)(526:579:632)) - (INTERCONNECT SLICE_85/F0 SLICE_77/D0 (857:949:1042)(857:949:1042)) - (INTERCONNECT SLICE_77/F1 SLICE_77/B0 (1206:1370:1535)(1206:1370:1535)) - (INTERCONNECT SLICE_88/F0 SLICE_77/A0 (1067:1225:1383)(1067:1225:1383)) - (INTERCONNECT SLICE_78/F0 RA\[10\]_MGIOL/LSR (1558:1705:1853)(1558:1705:1853)) - (INTERCONNECT SLICE_105/F1 SLICE_81/D1 (520:573:626)(520:573:626)) - (INTERCONNECT SLICE_92/F0 SLICE_81/C1 (537:645:753)(537:645:753)) - (INTERCONNECT SLICE_92/F0 SLICE_92/C1 (280:362:445)(280:362:445)) - (INTERCONNECT SLICE_117/F1 SLICE_81/B1 (768:889:1010)(768:889:1010)) - (INTERCONNECT SLICE_117/F1 SLICE_92/A1 (479:572:665)(479:572:665)) - (INTERCONNECT SLICE_81/F0 SLICE_81/A1 (476:566:656)(476:566:656)) - (INTERCONNECT SLICE_90/F0 SLICE_81/B0 (765:889:1013)(765:889:1013)) - (INTERCONNECT SLICE_90/F0 SLICE_90/C1 (280:362:445)(280:362:445)) - (INTERCONNECT SLICE_81/F1 nRCS_MGIOL/OPOS (1337:1468:1599)(1337:1468:1599)) - (INTERCONNECT SLICE_82/F1 SLICE_82/C0 (531:639:747)(531:639:747)) - (INTERCONNECT SLICE_94/F0 SLICE_84/D0 (520:573:626)(520:573:626)) - (INTERCONNECT SLICE_86/F0 SLICE_85/B0 (765:883:1001)(765:883:1001)) - (INTERCONNECT SLICE_85/F1 SLICE_85/A0 (730:848:967)(730:848:967)) - (INTERCONNECT SLICE_87/F1 SLICE_87/B0 (762:883:1004)(762:883:1004)) - (INTERCONNECT SLICE_109/F0 SLICE_89/D0 (530:587:645)(530:587:645)) - (INTERCONNECT Din\[2\]_MGIOL/IN SLICE_89/C0 (1174:1343:1512)(1174:1343:1512)) - (INTERCONNECT Din\[0\]_MGIOL/IN SLICE_89/B0 (2284:2517:2751)(2284:2517:2751)) - (INTERCONNECT SLICE_89/F1 SLICE_89/A0 (1430:1615:1801)(1430:1615:1801)) - (INTERCONNECT SLICE_90/F1 nRRAS_MGIOL/OPOS (1772:1946:2120)(1772:1946:2120)) - (INTERCONNECT SLICE_91/F1 SLICE_91/C0 (277:356:436)(277:356:436)) - (INTERCONNECT SLICE_92/F1 nRWE_MGIOL/OPOS (1527:1661:1795)(1527:1661:1795)) - (INTERCONNECT SLICE_93/F1 SLICE_93/C0 (277:356:436)(277:356:436)) - (INTERCONNECT SLICE_94/F1 SLICE_94/B0 (508:600:693)(508:600:693)) - (INTERCONNECT SLICE_95/F1 SLICE_95/B0 (508:600:693)(508:600:693)) - (INTERCONNECT SLICE_117/F0 SLICE_96/D1 (520:573:626)(520:573:626)) - (INTERCONNECT SLICE_96/F1 SLICE_96/B0 (762:883:1004)(762:883:1004)) - (INTERCONNECT SLICE_96/F0 nRCAS_MGIOL/OPOS (1527:1661:1795)(1527:1661:1795)) - (INTERCONNECT SLICE_102/F0 RDQMH_I/PADDO (1346:1504:1662)(1346:1504:1662)) - (INTERCONNECT SLICE_102/F1 RDQML_I/PADDO (1367:1504:1642)(1367:1504:1642)) - (INTERCONNECT ufmefb\/EFBInst_0/WBDATO0 SLICE_108/C1 (986:1141:1297) - (986:1141:1297)) - (INTERCONNECT SLICE_109/F1 RA\[3\]_I/PADDO (1916:2133:2351)(1916:2133:2351)) - (INTERCONNECT SLICE_110/F0 RA\[9\]_I/PADDO (1111:1225:1339)(1111:1225:1339)) - (INTERCONNECT SLICE_110/F1 RA\[8\]_I/PADDO (1929:2148:2367)(1929:2148:2367)) - (INTERCONNECT SLICE_111/F0 RA\[7\]_I/PADDO (1834:2056:2279)(1834:2056:2279)) - (INTERCONNECT SLICE_111/F1 RA\[0\]_I/PADDO (1362:1545:1728)(1362:1545:1728)) - (INTERCONNECT SLICE_112/F0 RA\[6\]_I/PADDO (1778:2009:2240)(1778:2009:2240)) - (INTERCONNECT SLICE_112/F1 RA\[1\]_I/PADDO (1470:1661:1852)(1470:1661:1852)) - (INTERCONNECT SLICE_113/F0 RA\[5\]_I/PADDO (1726:1940:2155)(1726:1940:2155)) - (INTERCONNECT SLICE_113/F1 RA\[2\]_I/PADDO (1797:2023:2249)(1797:2023:2249)) - (INTERCONNECT SLICE_114/F1 RA\[10\]_MGIOL/OPOS (1212:1320:1429)(1212:1320:1429)) - (INTERCONNECT CROW\[0\]_I/PADDI SLICE_115/A1 (2230:2452:2674)(2230:2452:2674)) - (INTERCONNECT SLICE_115/F0 RA\[11\]_MGIOL/OPOS (1986:2148:2310)(1986:2148:2310)) - (INTERCONNECT SLICE_115/F1 RBA\[0\]_MGIOL/OPOS (1995:2157:2319)(1995:2157:2319)) + (INTERCONNECT SLICE_119/F0 SLICE_63/C1 (590:715:840)(590:715:840)) + (INTERCONNECT SLICE_119/F0 SLICE_96/B0 (765:889:1013)(765:889:1013)) + (INTERCONNECT SLICE_63/F0 SLICE_76/B0 (508:600:693)(508:600:693)) + (INTERCONNECT SLICE_97/F0 SLICE_64/A0 (999:1149:1299)(999:1149:1299)) + (INTERCONNECT SLICE_64/F0 SLICE_85/D0 (857:949:1042)(857:949:1042)) + (INTERCONNECT SLICE_65/F0 SLICE_65/A1 (479:572:665)(479:572:665)) + (INTERCONNECT SLICE_65/F0 SLICE_67/D1 (903:995:1088)(903:995:1088)) + (INTERCONNECT SLICE_65/F0 SLICE_73/B1 (781:910:1039)(781:910:1039)) + (INTERCONNECT SLICE_102/F0 SLICE_66/C0 (800:939:1079)(800:939:1079)) + (INTERCONNECT SLICE_66/F1 SLICE_66/B0 (765:889:1013)(765:889:1013)) + (INTERCONNECT SLICE_66/F1 SLICE_107/D0 (1223:1346:1469)(1223:1346:1469)) + (INTERCONNECT SLICE_68/F1 SLICE_75/C0 (534:639:744)(534:639:744)) + (INTERCONNECT SLICE_69/F0 SLICE_69/D1 (520:573:626)(520:573:626)) + (INTERCONNECT SLICE_117/F0 SLICE_69/C1 (531:639:747)(531:639:747)) + (INTERCONNECT SLICE_69/F1 SLICE_101/C1 (534:639:744)(534:639:744)) + (INTERCONNECT SLICE_107/F1 SLICE_70/D1 (523:579:635)(523:579:635)) + (INTERCONNECT SLICE_107/F1 SLICE_93/A0 (736:854:973)(736:854:973)) + (INTERCONNECT SLICE_93/F1 SLICE_70/B1 (508:600:693)(508:600:693)) + (INTERCONNECT SLICE_94/F1 SLICE_71/B0 (775:903:1032)(775:903:1032)) + (INTERCONNECT SLICE_94/F1 SLICE_94/A0 (733:854:976)(733:854:976)) + (INTERCONNECT SLICE_88/F1 SLICE_72/D0 (535:598:662)(535:598:662)) + (INTERCONNECT SLICE_88/F1 SLICE_86/C1 (546:664:783)(546:664:783)) + (INTERCONNECT SLICE_88/F1 SLICE_88/C0 (282:367:453)(282:367:453)) + (INTERCONNECT SLICE_72/F1 SLICE_72/B0 (511:606:702)(511:606:702)) + (INTERCONNECT SLICE_72/F1 SLICE_93/B1 (765:889:1013)(765:889:1013)) + (INTERCONNECT SLICE_73/F0 SLICE_82/C0 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_76/Q1 SLICE_75/A1 (1669:1863:2058)(1669:1863:2058)) + (INTERCONNECT SLICE_103/F0 SLICE_75/D0 (525:581:637)(525:581:637)) + (INTERCONNECT SLICE_103/F0 SLICE_78/B0 (767:891:1015)(767:891:1015)) + (INTERCONNECT SLICE_75/F1 SLICE_75/B0 (765:889:1013)(765:889:1013)) + (INTERCONNECT SLICE_75/F1 SLICE_101/B0 (511:606:702)(511:606:702)) + (INTERCONNECT SLICE_106/F1 SLICE_75/A0 (746:869:993)(746:869:993)) + (INTERCONNECT SLICE_106/F1 SLICE_78/A0 (746:869:993)(746:869:993)) + (INTERCONNECT SLICE_75/F0 nRWE_MGIOL/OPOS (1426:1570:1714)(1426:1570:1714)) + (INTERCONNECT SLICE_76/F1 SLICE_76/C0 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_83/F0 SLICE_78/D0 (523:573:623)(523:573:623)) + (INTERCONNECT SLICE_78/F1 SLICE_78/C0 (534:645:756)(534:645:756)) + (INTERCONNECT SLICE_78/F1 SLICE_101/B1 (765:889:1013)(765:889:1013)) + (INTERCONNECT SLICE_78/F0 nRCS_MGIOL/OPOS (1445:1584:1723)(1445:1584:1723)) + (INTERCONNECT SLICE_79/F0 RA\[10\]_MGIOL/LSR (2018:2189:2361)(2018:2189:2361)) + (INTERCONNECT Din\[6\]_MGIOL/IN SLICE_80/D1 (1514:1658:1802)(1514:1658:1802)) + (INTERCONNECT Din\[3\]_MGIOL/IN SLICE_80/C1 (986:1141:1297)(986:1141:1297)) + (INTERCONNECT Din\[5\]_MGIOL/IN SLICE_80/B1 (1285:1461:1638)(1285:1461:1638)) + (INTERCONNECT Din\[2\]_MGIOL/IN SLICE_80/A1 (1360:1538:1716)(1360:1538:1716)) + (INTERCONNECT SLICE_90/F0 SLICE_80/D0 (789:873:958)(789:873:958)) + (INTERCONNECT SLICE_80/F1 SLICE_80/C0 (277:356:436)(277:356:436)) + (INTERCONNECT Din\[4\]_MGIOL/IN SLICE_80/B0 (1285:1461:1638)(1285:1461:1638)) + (INTERCONNECT Din\[0\]_MGIOL/IN SLICE_80/A0 (1724:1933:2143)(1724:1933:2143)) + (INTERCONNECT SLICE_118/F1 SLICE_81/D1 (860:955:1051)(860:955:1051)) + (INTERCONNECT SLICE_118/F1 SLICE_97/D0 (523:579:635)(523:579:635)) + (INTERCONNECT SLICE_98/F1 SLICE_81/A1 (733:854:976)(733:854:976)) + (INTERCONNECT SLICE_98/F1 SLICE_98/B0 (765:889:1013)(765:889:1013)) + (INTERCONNECT SLICE_81/F1 SLICE_81/D0 (523:579:635)(523:579:635)) + (INTERCONNECT SLICE_81/F1 SLICE_111/B0 (511:606:702)(511:606:702)) + (INTERCONNECT SLICE_84/F0 SLICE_81/B0 (765:883:1001)(765:883:1001)) + (INTERCONNECT SLICE_102/F1 SLICE_82/D1 (857:949:1042)(857:949:1042)) + (INTERCONNECT SLICE_82/F1 SLICE_82/D0 (520:573:626)(520:573:626)) + (INTERCONNECT SLICE_86/F1 SLICE_86/C0 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_88/F0 SLICE_87/B0 (765:883:1001)(765:883:1001)) + (INTERCONNECT ufmefb\/EFBInst_0/WBACKO SLICE_89/C0 (1161:1328:1496) + (1161:1328:1496)) + (INTERCONNECT ufmefb\/EFBInst_0/WBACKO SLICE_102/C0 (986:1141:1297)(986:1141:1297)) + (INTERCONNECT SLICE_89/F1 SLICE_89/B0 (762:883:1004)(762:883:1004)) + (INTERCONNECT Din\[1\]_MGIOL/IN SLICE_90/D0 (1150:1262:1375)(1150:1262:1375)) + (INTERCONNECT SLICE_90/F1 SLICE_90/C0 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_112/F0 SLICE_90/B0 (1031:1183:1336)(1031:1183:1336)) + (INTERCONNECT Din\[7\]_MGIOL/IN SLICE_90/A0 (1806:2010:2215)(1806:2010:2215)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_92/D0 (2478:2663:2849)(2478:2663:2849)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_119/D0 (2623:2807:2991)(2623:2807:2991)) + (INTERCONNECT Din\[2\]_I/PADDI RD\[2\]_MGIOL/OPOS (3418:3702:3986)(3418:3702:3986)) + (INTERCONNECT Din\[2\]_I/PADDI Din\[2\]_MGIOL/DI (544:554:565)(544:554:565)) + (INTERCONNECT SLICE_92/F1 SLICE_92/C0 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_93/F0 SLICE_93/A1 (730:848:967)(730:848:967)) + (INTERCONNECT SLICE_95/F1 SLICE_95/C0 (277:356:436)(277:356:436)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_96/B1 (2755:3033:3312)(2755:3033:3312)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_109/A1 (3087:3394:3702)(3087:3394:3702)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_119/A1 (2723:2999:3275)(2723:2999:3275)) + (INTERCONNECT Din\[7\]_I/PADDI RD\[7\]_MGIOL/OPOS (3744:4048:4352)(3744:4048:4352)) + (INTERCONNECT Din\[7\]_I/PADDI Din\[7\]_MGIOL/DI (424:441:459)(424:441:459)) + (INTERCONNECT SLICE_109/F0 SLICE_96/D0 (1002:1093:1184)(1002:1093:1184)) + (INTERCONNECT SLICE_99/F0 SLICE_99/C1 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_100/F1 SLICE_100/B0 (762:883:1004)(762:883:1004)) + (INTERCONNECT SLICE_101/F0 SLICE_101/A1 (730:848:967)(730:848:967)) + (INTERCONNECT SLICE_101/F1 nRCAS_MGIOL/OPOS (1701:1863:2026)(1701:1863:2026)) + (INTERCONNECT SLICE_106/F0 LED_I/PADDO (1041:1147:1254)(1041:1147:1254)) + (INTERCONNECT SLICE_108/F0 RDQMH_I/PADDO (1279:1433:1587)(1279:1433:1587)) + (INTERCONNECT SLICE_108/F1 RDQML_I/PADDO (1263:1400:1537)(1263:1400:1537)) + (INTERCONNECT ufmefb\/EFBInst_0/WBDATO0 SLICE_111/C1 (1174:1343:1512) + (1174:1343:1512)) + (INTERCONNECT SLICE_112/F1 RA\[2\]_I/PADDO (1362:1545:1728)(1362:1545:1728)) + (INTERCONNECT SLICE_113/F0 RA\[0\]_I/PADDO (1295:1474:1653)(1295:1474:1653)) + (INTERCONNECT SLICE_113/F1 RA\[8\]_I/PADDO (1106:1265:1425)(1106:1265:1425)) + (INTERCONNECT SLICE_114/F0 RA\[1\]_I/PADDO (1106:1265:1425)(1106:1265:1425)) + (INTERCONNECT SLICE_114/F1 RA\[3\]_I/PADDO (1295:1474:1653)(1295:1474:1653)) + (INTERCONNECT SLICE_115/F0 RA\[4\]_I/PADDO (1470:1661:1852)(1470:1661:1852)) + (INTERCONNECT SLICE_115/F1 RA\[9\]_I/PADDO (1036:1188:1340)(1036:1188:1340)) + (INTERCONNECT SLICE_116/F0 RA\[5\]_I/PADDO (1451:1647:1843)(1451:1647:1843)) + (INTERCONNECT SLICE_116/F1 RA\[7\]_I/PADDO (1400:1583:1767)(1400:1583:1767)) + (INTERCONNECT CROW\[1\]_I/PADDI SLICE_120/D1 (2079:2229:2380)(2079:2229:2380)) + (INTERCONNECT SLICE_120/F0 RA\[11\]_MGIOL/OPOS (1854:2023:2192)(1854:2023:2192)) + (INTERCONNECT SLICE_120/F1 RBA\[1\]_MGIOL/OPOS (2218:2418:2619)(2218:2418:2619)) (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_I/PADDO (2674:2873:3073)(2674:2873:3073)) (INTERCONNECT RD\[0\]_MGIOL/IOLDO RD\[0\]_I/IOLDO (30:36:43)(30:36:43)) (INTERCONNECT nRCAS_MGIOL/IOLDO nRCAS_I/IOLDO (9:36:63)(9:36:63)) (INTERCONNECT nRRAS_MGIOL/IOLDO nRRAS_I/IOLDO (9:36:63)(9:36:63)) (INTERCONNECT nRWE_MGIOL/IOLDO nRWE_I/IOLDO (30:36:43)(30:36:43)) - (INTERCONNECT RCLKout_MGIOL/IOLDO RCLKout_I/IOLDO (25:77:129)(25:77:129)) + (INTERCONNECT RCLKout_MGIOL/IOLDO RCLKout_I/IOLDO (9:36:63)(9:36:63)) (INTERCONNECT nRCS_MGIOL/IOLDO nRCS_I/IOLDO (9:36:63)(9:36:63)) (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_I/PADDO (3098:3322:3547)(3098:3322:3547)) (INTERCONNECT RD\[7\]_MGIOL/IOLDO RD\[7\]_I/IOLDO (30:36:43)(30:36:43)) @@ -4488,13 +4577,13 @@ (INTERCONNECT RD\[4\]_MGIOL/IOLDO RD\[4\]_I/IOLDO (30:36:43)(30:36:43)) (INTERCONNECT RD\[3\]_I/PADDI Dout\[3\]_I/PADDO (2615:2816:3018)(2615:2816:3018)) (INTERCONNECT RD\[3\]_MGIOL/IOLDO RD\[3\]_I/IOLDO (30:36:43)(30:36:43)) - (INTERCONNECT RD\[2\]_I/PADDI Dout\[2\]_I/PADDO (2825:3034:3244)(2825:3034:3244)) + (INTERCONNECT RD\[2\]_I/PADDI Dout\[2\]_I/PADDO (2583:2787:2992)(2583:2787:2992)) (INTERCONNECT RD\[2\]_MGIOL/IOLDO RD\[2\]_I/IOLDO (30:36:43)(30:36:43)) - (INTERCONNECT RD\[1\]_I/PADDI Dout\[1\]_I/PADDO (2615:2816:3018)(2615:2816:3018)) + (INTERCONNECT RD\[1\]_I/PADDI Dout\[1\]_I/PADDO (2583:2787:2992)(2583:2787:2992)) (INTERCONNECT RD\[1\]_MGIOL/IOLDO RD\[1\]_I/IOLDO (30:36:43)(30:36:43)) (INTERCONNECT RA\[11\]_MGIOL/IOLDO RA\[11\]_I/IOLDO (9:36:63)(9:36:63)) (INTERCONNECT RA\[10\]_MGIOL/IOLDO RA\[10\]_I/IOLDO (25:77:129)(25:77:129)) - (INTERCONNECT RBA\[1\]_MGIOL/IOLDO RBA\[1\]_I/IOLDO (9:36:63)(9:36:63)) + (INTERCONNECT RBA\[1\]_MGIOL/IOLDO RBA\[1\]_I/IOLDO (30:36:43)(30:36:43)) (INTERCONNECT RBA\[0\]_MGIOL/IOLDO RBA\[0\]_I/IOLDO (9:36:63)(9:36:63)) ) ) diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_vo.vo b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_vo.vo index 501ed17..bfe6702 100644 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_vo.vo +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_vo.vo @@ -2,8 +2,8 @@ // Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454 // ldbanno -n Verilog -o RAM2GS_LCMXO2_1200HC_impl1_vo.vo -w -neg -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd -// Netlist created on Thu Oct 19 23:50:56 2023 -// Netlist written on Thu Oct 19 23:51:19 2023 +// Netlist created on Sat Nov 18 02:05:52 2023 +// Netlist written on Sat Nov 18 02:06:23 2023 // Design is for device LCMXO2-1200HC // Design is for package TQFP100 // Design is for performance grade 4 @@ -31,70 +31,86 @@ module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, \FS_cry[10] , \FS[10] , \FS[9] , \FS_s[10] , \FS_s[9] , \FS_cry[8] , \FS[8] , \FS[7] , \FS_s[8] , \FS_s[7] , \FS_cry[6] , \FS[6] , \FS[5] , \FS_s[6] , \FS_s[5] , \FS_cry[4] , \FS[4] , \FS[3] , \FS_s[4] , - \FS_s[3] , \FS_cry[2] , \FS[2] , \FS[1] , \FS_s[2] , \FS_s[1] , - \MAin_c[1] , N_294, ADSubmitted, CmdEnable17, CmdEnable16, N_22_i, - ADSubmitted_r_0, PHI2_c, N_393, N_374, C1Submitted, C1Submitted_RNO, - nCCAS_c, nCCAS_c_i, CASr, CASr2, RASr2, \IS[3] , CO0, \S[1] , N_253_i, - Ready_0_sqmuxa_0_a3_2, un1_CmdEnable20_0_0, un1_CmdEnable20_0_a2_1_0, - CmdEnable, un1_CmdEnable20_i, CmdEnable_0_sqmuxa, CmdEnable_s, - CmdLEDEN_4_u_i_a2_0_0, N_140, CmdLEDEN, \Din_c[1] , CmdLEDEN_4_u_i_0, - N_380, LEDEN, N_284_i, XOR8MEG18, \Din_c[0] , CmdUFMData_1_sqmuxa, - VCC, CmdUFMData, GND, \Din_c[4] , \Din_c[7] , CmdUFMShift, - CmdUFMShift_3, CmdUFMWrite, N_279, CmdUFMWrite_3, N_134, \Din_c[5] , - \Din_c[3] , XOR8MEG18_i, CmdValid_r, CmdValid, \MAin_c[0] , N_36_fast, - CmdValid_fast, Cmdn8MEGEN, Cmdn8MEGEN_4_u_i_0, n8MEGEN, N_285_i, - nFWE_c, nFWE_c_i, nCRAS_c, FWEr, RD_1_i, \CROW_c[1] , Ready_fast, - \Din_c[2] , N_381, FWEr_fast, \RBAd_0[1] , Ready, N_43, \IS[0] , - N_60_i_i, N_244_i, \IS[1] , \IS[2] , N_57_i_i, N_53_i, N_58_i_i, N_49, - N_142, InitReady3_0_a2_2, InitReady3, InitReady, N_586_0, - \wb_dato[1] , LEDEN_6_i_m2, CmdValid_RNITBH02, LEDENe_0, nRowColSel, - \MAin_c[4] , \RowA[4] , \Bank[6] , \Bank[4] , \Bank[5] , \Bank[7] , - PHI2r2, PHI2r, un1_ADWR_i_o2_11, \RA_c[4] , PHI2r3, CBR, nCRAS_c_i_0, - RASr, LED_c, N_133, \wb_dati_5_1_iv_0_a2_1_1[7] , RASr3, - wb_cyc_stb_2_sqmuxa_i_a2_3_4, N_41, RCKEEN_8_u_1, RCKEEN_8_u_0_0, - RCKEEN_8, RCKEEN, RCKE_c, RCKE_2, nRWE_0io_RNO_2, N_248, N_587_0, - Ready_0_sqmuxa, N_588_0, \RowAd_0[1] , \RowAd_0[0] , \RowA[0] , + \FS_s[3] , \FS_cry[2] , \FS[2] , \FS[1] , \FS_s[2] , \FS_s[1] , N_367, + \MAin_c[1] , CmdEnable17, N_293_i, CmdEnable16, ADSubmitted, + ADSubmitted_r_0_0, PHI2_c, N_483, N_457, C1Submitted, C1Submitted_RNO, + nCCAS_c, nCCAS_c_i, CASr, CASr2, RASr2, CO0, \IS[3] , \S[1] , N_279_i, + Ready_0_sqmuxa_0_a2_2, N_482, un1_CmdEnable20_i, CmdEnable, + CmdEnable_0_sqmuxa, CmdEnable_s, N_260, \Din_c[1] , + CmdLEDEN_4_u_i_m2_i_a2_0_0, CmdLEDEN, CmdLEDEN_4_u_i_m2_i_0, N_461, + LEDEN, N_17_i, XOR8MEG18, \IS[0] , \Din_c[0] , CmdUFMData_1_sqmuxa, + \IS_i[0] , CmdUFMData, CmdUFMShift, CmdUFMShift_3, GND, CmdUFMWrite, + N_415, CmdUFMWrite_3, \Din_c[4] , N_353, \Din_c[3] , \Din_c[5] , + CmdValid_r, CmdValid, \MAin_c[0] , N_34_fast, CmdValid_fast, + Cmdn8MEGEN, n8MEGEN, Cmdn8MEGEN_4_u_i_m2_i_0, N_15_i, nFWE_c, + nFWE_c_i, nCRAS_c, FWEr, RD_1_i, IS_0_sqmuxa_0_o2, + un1_nRCAS_6_sqmuxa_i_o2, nRCS_9_u_i_0_0, Ready, N_76_i_i, N_32_i, + \IS[1] , \IS[2] , N_73_i_i, N_69_i, N_261_i, IS_0_sqmuxa_0_o3, + N_74_i_i, nRWE_s_i_a2_1_0, InitReady, InitReady3, N_705_0, wb_rst10, + \wb_dato[1] , un1_FS_38_i, LEDEN_6, LEDENe_0, \CROW_c[0] , Ready_fast, + PHI2r2, PHI2r, \RBAd_0[0] , VCC, PHI2r3, \RowA[6] , \MAin_c[6] , + nRowColSel, nCRAS_c_i_0, RASr, \RA_c[6] , RASr3, \wb_adr_5_i_0_o2[0] , + \S_0_i_o3[1] , RCKEEN_8_u_0_0, RCKEEN_8_u_1, CBR, RCKEEN_8, RCKEEN, + RCKE_2, RCKE_c, m3_0_a2_0, Ready_0_sqmuxa_0_o2, N_706_0, + Ready_0_sqmuxa, N_707_0, \RowAd_0[1] , \RowAd_0[0] , \RowA[0] , \RowA[1] , \MAin_c[3] , \MAin_c[2] , \RowAd_0[3] , \RowAd_0[2] , - \RowA[2] , \RowA[3] , \MAin_c[5] , \RowAd_0[5] , \RowAd_0[4] , - \RowA[5] , \MAin_c[7] , \MAin_c[6] , \RowAd_0[7] , \RowAd_0[6] , - \RowA[6] , \RowA[7] , \MAin_c[9] , \MAin_c[8] , \RowAd_0[9] , - \RowAd_0[8] , \RowA[8] , \RowA[9] , CBR_fast, nRCAS_0_sqmuxa_1, - XOR8MEG, N_274, XOR8MEG_3_u_0_a2_0_2, XOR8MEG_3, N_4, g1_0, - n8MEGENe_1_0, n8MEGENe_0, CASr3, N_255, nRowColSel_0_0, - nRRAS_0_sqmuxa, N_384, \wb_adr_5_i_i_0[1] , \wb_adr_5_i_i_5[0] , - N_313, N_367, N_282, N_283, N_122, \wb_adr[0] , \wb_adr[1] , - \wb_adr[2] , \wb_adr_5[3] , \wb_adr_5[2] , \wb_adr[3] , N_132, - \wb_adr[4] , N_80, N_81, \wb_adr[5] , \wb_adr[6] , \wb_adr_5[7] , - \wb_adr_5_i_m2_0[6] , \wb_adr[7] , wb_req, N_330_4, N_330, un1_PHI2r3, - wb_cyc_stb_4, N_103, wb_rst10, wb_cyc_stb, N_226, N_302, N_303, N_233, - \wb_dati_5_0_iv_0_a2_0[0] , N_383, wb_we, \wb_dati_5[1] , - \wb_dati_5[0] , \wb_dati[0] , \wb_dati[1] , \wb_dati[2] , N_341, - \wb_dati_5_1_iv_0_1[3] , N_335, \wb_dati_5_1_iv_0_o2_0[5] , - \wb_dati_5[3] , \wb_dati_5[2] , \wb_dati[3] , \wb_dati[4] , - \wb_dati_5_1_iv_0_2[4] , \wb_dati_5_1_iv_0_0[4] , \wb_dati_5[5] , - \wb_dati_5[4] , \wb_dati[5] , N_345, \wb_dati_5_1_iv_0_1[7] , N_375, - \wb_dati_5_1_iv_0_0[6] , N_348_2, \wb_dati_5[7] , \wb_dati_5[6] , - \wb_dati[6] , \wb_dati[7] , N_131, N_94_i, N_34_i, wb_reqe_0, wb_rst, - wb_rste_0, N_362, N_394, N_353, wb_we_0_0_0_0, wb_we_0_0_0, N_129, - N_223, N_428_tz, N_39, N_125, N_356, \Din_c[6] , - \wb_adr_5_i_i_a2_0[1] , \wb_adr_5_i_i_a2_3_0[0] , - \wb_adr_5_i_i_1_0_tz_0[0] , g0_0_a3_1, wb_ack, IS_0_sqmuxa_0_o2, - nRWE_0io_RNO_1, nRWE_0io_RNO_0, N_220, \wb_dati_5_1_iv_0_0[7] , - \wb_dati_5_1_iv_0_a2_3_0[7] , N_143, N_137, N_382, - un1_CmdEnable20_0_a2_3_0, \Bank[3] , un1_ADWR_i_o2_10, \Bank[1] , - N_378, \wb_adr_5_i_i_a2_6_0[0] , \wb_adr_5_i_i_1[0] , N_314, N_315, - RA10s_i, nRCS_0io_RNO_0, N_37_i_1, N_28_i_1, nRCS_9_u_i_0, - nRCS_9_u_i_0_0, N_28_i, N_376, \wb_dati_5_1_iv_0_a2_1[6] , - \wb_adr_5_i_i_1_0[0] , N_307, N_295, un1_ADWR_i_o2_3, \Bank[2] , - \Bank[0] , un1_ADWR_i_o2_4, N_25_i, wb_cyc_stb_2_sqmuxa_i_a2_3_3, - N_37_i, N_371, N_141, G_8_0_a3_0_0, nRCAS_0io_RNO_1, N_242_i_1, - N_242_i, RDQMH_c, RDQML_c, \wb_dato[0] , \RA_c[3] , \RA_c[9] , - \RA_c[8] , \RA_c[7] , \RA_c[0] , \RA_c[6] , \RA_c[1] , \RA_c[5] , - \RA_c[2] , \IS_i[0] , \CROW_c[0] , RA11d_0, \RBAd_0[0] , \RD_in[0] , - \WRD[0] , nRCAS_c, nRRAS_c, nRWE_c, RCLKout_c, nRCS_c, \RD_in[7] , - \WRD[7] , \RD_in[6] , \WRD[6] , \RD_in[5] , \WRD[5] , \RD_in[4] , - \WRD[4] , \RD_in[3] , \WRD[3] , \RD_in[2] , \WRD[2] , \RD_in[1] , - \WRD[1] , \RA_c[11] , \RA_c[10] , \RBA_c[1] , \RBA_c[0] , VCCI; + \RowA[2] , \RowA[3] , \MAin_c[5] , \MAin_c[4] , \RowAd_0[5] , + \RowAd_0[4] , \RowA[4] , \RowA[5] , \MAin_c[7] , \RowAd_0[7] , + \RowAd_0[6] , \RowA[7] , \MAin_c[9] , \MAin_c[8] , \RowAd_0[9] , + \RowAd_0[8] , \RowA[8] , \RowA[9] , XOR8MEG, XOR8MEG_3_u_0_0_a2_0_2, + N_411, XOR8MEG_3, g1_0, N_4, n8MEGENe_1_0, n8MEGENe_0, CASr3, + N_251_i_1_0, N_70_i, nRowColSel_0_0, nRRAS_0_sqmuxa, + \wb_adr_5_i_3_0_a2[1] , \wb_adr_5_i_3_0_a2_0[1] , + \wb_adr_5_i_3_0_0[1] , N_216, \FS_RNIOVGI[9] , + \wb_dati_5_1_iv_0_a2_11[3] , \wb_adr_5_i_0_3[0] , \wb_adr_5_i_0_2[0] , + N_45_i, N_47_i, N_126_i, \wb_adr[0] , \wb_adr[1] , \wb_adr[2] , + \wb_adr_5[3] , \wb_adr_5[2] , \wb_adr[3] , \wb_adr[4] , + \FS_RNI82PA[15] , \wb_adr_5[5] , \wb_adr_5[4] , \wb_adr[5] , + \wb_adr[6] , \wb_adr_5[7] , \wb_adr_5[6] , \wb_adr[7] , N_99_2, + N_99_1, wb_cyc_stb_4_iv_0_0_a2_0_0, \FS_RNIHVJI[15] , un1_PHI2r3_i_li, + wb_cyc_stb_4_iv_0_0_a2_0, wb_cyc_stb_4, wb_cyc_stb_2_sqmuxa_i_0_0, + wb_cyc_stb, \wb_dati_5_1_iv_0_1[1] , \FS_RNIGOCT[12] , + \FS_RNIS637[9] , wb_we, \wb_dati_5_1_iv_0_a2_12[3] , + \wb_dati_5_0_iv_0_a2_1[0] , \wb_dati_5[1] , \wb_dati_5[0] , + \wb_dati[0] , \wb_dati[1] , \wb_dati_5_1_iv_0_0_a2_1[3] , + \wb_dati_5_1_iv_0_a2_13[3] , \wb_dati_5_1_iv_0_0_0[3] , + \wb_dati_5_1_iv_0_0_1[3] , \wb_dati_5_1_iv_0_0_o2[5] , \wb_dati_5[3] , + \wb_dati_5[2] , \wb_dati[2] , \wb_dati[3] , \wb_dati[4] , + \wb_dati_5_1_iv_0_1_0[4] , \wb_dati_5_1_iv_0_0_1[4] , \wb_dati_5[5] , + \wb_dati_5[4] , \wb_dati[5] , \wb_dati_5_1_iv_0_a2_5[7] , + \wb_dati_5_1_iv_0_1[7] , \wb_dati_5_1_iv_0_RNO[7] , + \wb_dati_5_1_iv_0_0_1[6] , \wb_dati_5[7] , \wb_dati_5[6] , + \wb_dati[6] , \wb_dati[7] , un1_wb_rst14_2_0_o2, N_122_i, + un1_wb_rst14_2_i, wb_req, wb_reqe_0, wb_rst_3, wb_rst, wb_rste_0, + wb_we_0_0_i_1, N_346_i, \wb_dati_5_1_iv_0_o2[7] , + \wb_dati_5_1_iv_0_o2_0_RNIMDJC1[4] , \wb_dati_5_1_iv_0_0_o2[3] , + \wb_dati_5_1_iv_0_o2_0[7] , \FS_RNIJO0F[12] , \FS_RNI9Q57[12] , + \wb_adr_5_i_0_1[0] , N_313, \wb_adr_5_i_0_0[0] , N_48, \Din_c[6] , + N_466, un1_CmdEnable20_0_0_0, \wb_dati_5_1_iv_0_a2_0_2[1] , + \wb_dati_5_1_iv_0_0[1] , \wb_dati_5_1_iv_0_0_o2[4] , + \ufmefb/g0_0_a3_2 , \FS_RNIF2MA[9] , nRWE_s_i_tz_0, nRCS_9_u_i_o3_0_0, + RCKEEN_8_u_0_o3, nRCS_9_u_i_o3_0_2, \wb_adr_5_i_0_a2_6[0] , + wb_we_0_0_i_1_1, \wb_adr_5_i_3_0_a2_3[1] , \FS_RNI7U6M[14] , + \wb_dati_5_1_iv_0_o2_0[4] , \wb_dati_5_1_iv_0_1_RNO[7] , CBR_fast, + N_142, nRCAS_0_sqmuxa_1, N_141, N_252_i, un1_CmdEnable20_0_0_a2_1_1, + nRCS_9_u_i_0, N_251_i_1, N_37_i, RA10s_i, \Bank[6] , \Bank[3] , + \Bank[5] , \Bank[2] , un1_CmdEnable20_0_0_o2_10, + un1_CmdEnable20_0_0_o2_11, \Bank[4] , \Bank[0] , + \wb_dati_5_1_iv_0_a2_7[4] , \wb_dati_5_1_iv_0_a2_6[4] , + \wb_dati_5_1_iv_0_a2_2[4] , \wb_dati_5_1_iv_0_0_a2[6] , + \wb_dati_5_1_iv_0_a2_0_0[7] , \wb_dati_5_1_iv_0_a2_0[7] , + \wb_dati_5_1_iv_0_a2_7[3] , \wb_dati_5_1_iv_0_a2_5[3] , wb_ack, + wb_cyc_stb_2_sqmuxa_i_0_0_a2_0, \Bank[1] , un1_CmdEnable20_0_0_o2_4, + un1_CmdEnable20_0_0_o2_3, \Bank[7] , \Din_c[2] , N_442, + wb_we_0_0_i_a2_0, wb_cyc_stb_2_sqmuxa_i_a2_2_0, \Din_c[7] , N_452, + InitReady3_0_a2_1_0, G_4_0_a3_0, N_251_i_sx, N_251_i, LED_c, RDQMH_c, + RDQML_c, \wb_dato[0] , \RA_c[2] , \RA_c[0] , \RA_c[8] , \RA_c[1] , + \RA_c[3] , \RA_c[4] , \RA_c[9] , \RA_c[5] , \RA_c[7] , \CROW_c[1] , + RA11d_0, \RBAd_0[1] , \RD_in[0] , \WRD[0] , nRCAS_c, nRRAS_c, nRWE_c, + RCLKout_c, nRCS_c, \RD_in[7] , \WRD[7] , \RD_in[6] , \WRD[6] , + \RD_in[5] , \WRD[5] , \RD_in[4] , \WRD[4] , \RD_in[3] , \WRD[3] , + \RD_in[2] , \WRD[2] , \RD_in[1] , \WRD[1] , \RA_c[11] , \RA_c[10] , + \RBA_c[1] , \RBA_c[0] , VCCI; SLICE_0 SLICE_0( .A1(\FS[0] ), .DI1(\FS_s[0] ), .CLK(RCLK_c), .F1(\FS_s[0] ), .Q1(\FS[0] ), .FCO(\FS_cry[0] )); @@ -124,329 +140,380 @@ module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, SLICE_9 SLICE_9( .A1(\FS[2] ), .A0(\FS[1] ), .DI1(\FS_s[2] ), .DI0(\FS_s[1] ), .CLK(RCLK_c), .FCI(\FS_cry[0] ), .F0(\FS_s[1] ), .Q0(\FS[1] ), .F1(\FS_s[2] ), .Q1(\FS[2] ), .FCO(\FS_cry[2] )); - SLICE_10 SLICE_10( .C1(\MAin_c[1] ), .A1(N_294), .D0(ADSubmitted), - .C0(CmdEnable17), .B0(CmdEnable16), .A0(N_22_i), .DI0(ADSubmitted_r_0), - .CLK(PHI2_c), .F0(ADSubmitted_r_0), .Q0(ADSubmitted), .F1(N_22_i)); - SLICE_11 SLICE_11( .D1(\MAin_c[1] ), .C1(N_294), .B1(N_393), .A1(N_374), - .D0(\MAin_c[1] ), .C0(N_294), .B0(CmdEnable16), .A0(C1Submitted), + SLICE_10 SLICE_10( .C1(N_367), .B1(\MAin_c[1] ), .D0(CmdEnable17), + .C0(N_293_i), .B0(CmdEnable16), .A0(ADSubmitted), .DI0(ADSubmitted_r_0_0), + .CLK(PHI2_c), .F0(ADSubmitted_r_0_0), .Q0(ADSubmitted), .F1(N_293_i)); + SLICE_11 SLICE_11( .D1(\MAin_c[1] ), .C1(N_483), .B1(N_367), .A1(N_457), + .D0(\MAin_c[1] ), .C0(C1Submitted), .B0(N_367), .A0(CmdEnable16), .DI0(C1Submitted_RNO), .CLK(PHI2_c), .F0(C1Submitted_RNO), .Q0(C1Submitted), .F1(CmdEnable16)); - SLICE_12 SLICE_12( .D0(nCCAS_c), .DI0(nCCAS_c_i), .M1(CASr), .CLK(RCLK_c), + SLICE_12 SLICE_12( .B0(nCCAS_c), .DI0(nCCAS_c_i), .M1(CASr), .CLK(RCLK_c), .F0(nCCAS_c_i), .Q0(CASr), .Q1(CASr2)); - SLICE_16 SLICE_16( .D1(RASr2), .C1(\IS[3] ), .B1(CO0), .A1(\S[1] ), - .C0(\S[1] ), .B0(CO0), .DI0(N_253_i), .LSR(RASr2), .CLK(RCLK_c), - .F0(N_253_i), .Q0(CO0), .F1(Ready_0_sqmuxa_0_a3_2)); - SLICE_17 SLICE_17( .D1(N_294), .C1(un1_CmdEnable20_0_0), .B1(C1Submitted), - .A1(un1_CmdEnable20_0_a2_1_0), .D0(CmdEnable), .C0(un1_CmdEnable20_i), - .B0(CmdEnable17), .A0(CmdEnable_0_sqmuxa), .DI0(CmdEnable_s), .CLK(PHI2_c), - .F0(CmdEnable_s), .Q0(CmdEnable), .F1(un1_CmdEnable20_i)); - SLICE_18 SLICE_18( .D1(CmdLEDEN_4_u_i_a2_0_0), .C1(N_140), .B1(CmdLEDEN), - .A1(\Din_c[1] ), .C0(CmdLEDEN_4_u_i_0), .B0(N_380), .A0(LEDEN), - .DI0(N_284_i), .CE(XOR8MEG18), .CLK(PHI2_c), .F0(N_284_i), .Q0(CmdLEDEN), - .F1(CmdLEDEN_4_u_i_0)); - SLICE_19 SLICE_19( .M0(\Din_c[0] ), .CE(CmdUFMData_1_sqmuxa), .CLK(PHI2_c), - .F0(VCC), .Q0(CmdUFMData), .F1(GND)); - SLICE_20 SLICE_20( .D1(\Din_c[1] ), .C1(\Din_c[4] ), .B1(\Din_c[0] ), - .A1(\Din_c[7] ), .D0(\Din_c[1] ), .C0(N_380), .B0(N_140), .A0(CmdUFMShift), + SLICE_16 SLICE_16( .D1(RASr2), .C1(CO0), .B1(\IS[3] ), .A1(\S[1] ), + .D0(\S[1] ), .C0(CO0), .DI0(N_279_i), .LSR(RASr2), .CLK(RCLK_c), + .F0(N_279_i), .Q0(CO0), .F1(Ready_0_sqmuxa_0_a2_2)); + SLICE_17 SLICE_17( .D1(\MAin_c[1] ), .C1(N_457), .B1(N_482), .A1(N_367), + .D0(CmdEnable17), .C0(un1_CmdEnable20_i), .B0(CmdEnable), + .A0(CmdEnable_0_sqmuxa), .DI0(CmdEnable_s), .CLK(PHI2_c), .F0(CmdEnable_s), + .Q0(CmdEnable), .F1(CmdEnable17)); + SLICE_18 SLICE_18( .D1(N_260), .C1(\Din_c[1] ), + .B1(CmdLEDEN_4_u_i_m2_i_a2_0_0), .A1(CmdLEDEN), .C0(CmdLEDEN_4_u_i_m2_i_0), + .B0(N_461), .A0(LEDEN), .DI0(N_17_i), .CE(XOR8MEG18), .CLK(PHI2_c), + .F0(N_17_i), .Q0(CmdLEDEN), .F1(CmdLEDEN_4_u_i_m2_i_0)); + SLICE_19 SLICE_19( .D0(\IS[0] ), .M0(\Din_c[0] ), .CE(CmdUFMData_1_sqmuxa), + .CLK(PHI2_c), .F0(\IS_i[0] ), .Q0(CmdUFMData)); + SLICE_20 SLICE_20( .D0(N_260), .C0(\Din_c[1] ), .B0(N_461), .A0(CmdUFMShift), .DI0(CmdUFMShift_3), .CE(XOR8MEG18), .CLK(PHI2_c), .F0(CmdUFMShift_3), - .Q0(CmdUFMShift), .F1(N_374)); - SLICE_21 SLICE_21( .D1(N_140), .A1(CmdUFMWrite), .D0(\Din_c[0] ), .C0(N_279), - .B0(\Din_c[1] ), .A0(N_380), .DI0(CmdUFMWrite_3), .CE(XOR8MEG18), - .CLK(PHI2_c), .F0(CmdUFMWrite_3), .Q0(CmdUFMWrite), .F1(N_279)); - SLICE_22 SLICE_22( .D1(N_134), .C1(\Din_c[5] ), .B1(\Din_c[3] ), - .A1(\Din_c[4] ), .C0(XOR8MEG18_i), .B0(N_140), .DI0(CmdValid_r), - .CLK(PHI2_c), .F0(CmdValid_r), .Q0(CmdValid), .F1(N_140)); - SLICE_23 SLICE_23( .D1(\MAin_c[0] ), .C1(CmdEnable), .B1(\MAin_c[1] ), - .A1(N_294), .C0(XOR8MEG18_i), .A0(N_140), .DI0(N_36_fast), .CLK(PHI2_c), - .F0(N_36_fast), .Q0(CmdValid_fast), .F1(XOR8MEG18_i)); - SLICE_24 SLICE_24( .D1(CmdLEDEN_4_u_i_a2_0_0), .C1(\Din_c[0] ), .B1(N_140), - .A1(Cmdn8MEGEN), .C0(Cmdn8MEGEN_4_u_i_0), .B0(n8MEGEN), .A0(N_380), - .DI0(N_285_i), .CE(XOR8MEG18), .CLK(PHI2_c), .F0(N_285_i), .Q0(Cmdn8MEGEN), - .F1(Cmdn8MEGEN_4_u_i_0)); - SLICE_25 SLICE_25( .D1(nFWE_c), .A1(nCCAS_c), .D0(nFWE_c), .DI0(nFWE_c_i), + .Q0(CmdUFMShift), .F1(GND)); + SLICE_21 SLICE_21( .D1(N_260), .B1(CmdUFMWrite), .D0(\Din_c[0] ), + .C0(\Din_c[1] ), .B0(N_461), .A0(N_415), .DI0(CmdUFMWrite_3), + .CE(XOR8MEG18), .CLK(PHI2_c), .F0(CmdUFMWrite_3), .Q0(CmdUFMWrite), + .F1(N_415)); + SLICE_22 SLICE_22( .D1(\Din_c[4] ), .C1(N_353), .B1(\Din_c[3] ), + .A1(\Din_c[5] ), .D0(XOR8MEG18), .C0(N_260), .DI0(CmdValid_r), + .CLK(PHI2_c), .F0(CmdValid_r), .Q0(CmdValid), .F1(N_260)); + SLICE_23 SLICE_23( .D1(N_367), .C1(CmdEnable), .B1(\MAin_c[0] ), + .A1(\MAin_c[1] ), .B0(XOR8MEG18), .A0(N_260), .DI0(N_34_fast), + .CLK(PHI2_c), .F0(N_34_fast), .Q0(CmdValid_fast), .F1(XOR8MEG18)); + SLICE_24 SLICE_24( .D1(Cmdn8MEGEN), .C1(\Din_c[0] ), .B1(N_260), + .A1(CmdLEDEN_4_u_i_m2_i_a2_0_0), .D0(N_461), .C0(n8MEGEN), + .B0(Cmdn8MEGEN_4_u_i_m2_i_0), .DI0(N_15_i), .CE(XOR8MEG18), .CLK(PHI2_c), + .F0(N_15_i), .Q0(Cmdn8MEGEN), .F1(Cmdn8MEGEN_4_u_i_m2_i_0)); + SLICE_25 SLICE_25( .C1(nFWE_c), .B1(nCCAS_c), .C0(nFWE_c), .DI0(nFWE_c_i), .CLK(nCRAS_c), .F0(nFWE_c_i), .Q0(FWEr), .F1(RD_1_i)); - SLICE_26 SLICE_26( .C1(\CROW_c[1] ), .A1(Ready_fast), .D0(\Din_c[2] ), - .C0(\Din_c[5] ), .M0(nFWE_c_i), .CLK(nCRAS_c), .F0(N_381), .Q0(FWEr_fast), - .F1(\RBAd_0[1] )); - SLICE_27 SLICE_27( .B1(Ready), .A1(N_43), .C0(\IS[0] ), .B0(Ready), - .A0(N_43), .DI0(N_60_i_i), .CLK(RCLK_c), .F0(N_60_i_i), .Q0(\IS[0] ), - .F1(N_244_i)); - SLICE_28 SLICE_28( .C1(\IS[0] ), .B1(\IS[1] ), .A1(\IS[2] ), .C0(\IS[0] ), - .A0(\IS[1] ), .DI1(N_57_i_i), .DI0(N_53_i), .CE(N_244_i), .CLK(RCLK_c), - .F0(N_53_i), .Q0(\IS[1] ), .F1(N_57_i_i), .Q1(\IS[2] )); - SLICE_29 SLICE_29( .D1(\IS[2] ), .C1(\IS[3] ), .A1(\IS[1] ), .D0(\IS[2] ), - .C0(\IS[3] ), .B0(\IS[0] ), .A0(\IS[1] ), .DI0(N_58_i_i), .CE(N_244_i), - .CLK(RCLK_c), .F0(N_58_i_i), .Q0(\IS[3] ), .F1(N_49)); - SLICE_30 SLICE_30( .D1(N_142), .C1(\FS[14] ), .B1(\FS[13] ), - .A1(InitReady3_0_a2_2), .C0(InitReady3), .A0(InitReady), .DI0(N_586_0), - .CLK(RCLK_c), .F0(N_586_0), .Q0(InitReady), .F1(InitReady3)); - SLICE_31 SLICE_31( .D1(InitReady), .C1(\wb_dato[1] ), .B1(CmdLEDEN), - .C0(LEDEN_6_i_m2), .B0(LEDEN), .A0(CmdValid_RNITBH02), .DI0(LEDENe_0), - .CLK(RCLK_c), .F0(LEDENe_0), .Q0(LEDEN), .F1(LEDEN_6_i_m2)); - SLICE_32 SLICE_32( .D1(nRowColSel), .C1(\MAin_c[4] ), .B1(\RowA[4] ), - .D0(\Bank[6] ), .C0(\Bank[4] ), .B0(\Bank[5] ), .A0(\Bank[7] ), - .M1(PHI2r2), .M0(PHI2r), .CLK(RCLK_c), .F0(un1_ADWR_i_o2_11), .Q0(PHI2r2), - .F1(\RA_c[4] ), .Q1(PHI2r3)); - SLICE_33 SLICE_33( .D1(CBR), .B1(LEDEN), .A1(nCRAS_c), .A0(nCRAS_c), - .DI0(nCRAS_c_i_0), .M1(RASr), .CLK(RCLK_c), .F0(nCRAS_c_i_0), .Q0(RASr), - .F1(LED_c), .Q1(RASr2)); - SLICE_34 SLICE_34( .D1(\FS[1] ), .C1(\FS[5] ), .B1(\FS[2] ), .A1(\FS[4] ), - .D0(\FS[10] ), .C0(\FS[12] ), .B0(\FS[11] ), .A0(N_133), .M0(RASr2), - .CLK(RCLK_c), .F0(\wb_dati_5_1_iv_0_a2_1_1[7] ), .Q0(RASr3), - .F1(wb_cyc_stb_2_sqmuxa_i_a2_3_4)); - SLICE_35 SLICE_35( .D1(InitReady), .C1(Ready), .B1(RASr2), .A1(N_41), - .D0(CBR), .C0(RCKEEN_8_u_1), .B0(Ready), .A0(RCKEEN_8_u_0_0), + SLICE_26 SLICE_26( .D1(IS_0_sqmuxa_0_o2), .C1(\IS[0] ), + .B1(un1_nRCAS_6_sqmuxa_i_o2), .A1(nRCS_9_u_i_0_0), .D0(IS_0_sqmuxa_0_o2), + .C0(Ready), .A0(\IS[0] ), .DI0(N_76_i_i), .CLK(RCLK_c), .F0(N_76_i_i), + .Q0(\IS[0] ), .F1(N_32_i)); + SLICE_27 SLICE_27( .D1(\IS[1] ), .B1(\IS[0] ), .A1(\IS[2] ), .D0(\IS[0] ), + .A0(\IS[1] ), .DI1(N_73_i_i), .DI0(N_69_i), .CE(N_261_i), .CLK(RCLK_c), + .F0(N_69_i), .Q0(\IS[1] ), .F1(N_73_i_i), .Q1(\IS[2] )); + SLICE_28 SLICE_28( .D1(IS_0_sqmuxa_0_o3), .C1(\IS[2] ), .B1(\IS[0] ), + .A1(\IS[1] ), .D0(\IS[3] ), .C0(\IS[2] ), .B0(\IS[0] ), .A0(\IS[1] ), + .DI0(N_74_i_i), .CE(N_261_i), .CLK(RCLK_c), .F0(N_74_i_i), .Q0(\IS[3] ), + .F1(nRWE_s_i_a2_1_0)); + SLICE_29 SLICE_29( .D1(\FS[15] ), .C1(\FS[16] ), .B1(\FS[17] ), + .A1(InitReady), .D0(InitReady3), .A0(InitReady), .DI0(N_705_0), + .CLK(RCLK_c), .F0(N_705_0), .Q0(InitReady), .F1(wb_rst10)); + SLICE_30 SLICE_30( .D1(InitReady), .C1(CmdLEDEN), .A1(\wb_dato[1] ), + .D0(un1_FS_38_i), .B0(LEDEN_6), .A0(LEDEN), .DI0(LEDENe_0), .CLK(RCLK_c), + .F0(LEDENe_0), .Q0(LEDEN), .F1(LEDEN_6)); + SLICE_31 SLICE_31( .C0(\CROW_c[0] ), .B0(Ready_fast), .M1(PHI2r2), + .M0(PHI2r), .CLK(RCLK_c), .F0(\RBAd_0[0] ), .Q0(PHI2r2), .F1(VCC), + .Q1(PHI2r3)); + SLICE_32 SLICE_32( .C1(\RowA[6] ), .B1(\MAin_c[6] ), .A1(nRowColSel), + .B0(nCRAS_c), .DI0(nCRAS_c_i_0), .M1(RASr), .CLK(RCLK_c), .F0(nCRAS_c_i_0), + .Q0(RASr), .F1(\RA_c[6] ), .Q1(RASr2)); + SLICE_33 SLICE_33( .D1(\FS[10] ), .B1(\FS[9] ), .A1(\FS[11] ), + .C0(CmdEnable16), .B0(ADSubmitted), .M0(RASr2), .CLK(RCLK_c), + .F0(CmdEnable_0_sqmuxa), .Q0(RASr3), .F1(\wb_adr_5_i_0_o2[0] )); + SLICE_34 SLICE_34( .D1(\S_0_i_o3[1] ), .C1(Ready), .B1(InitReady), + .A1(RASr2), .D0(RCKEEN_8_u_0_0), .C0(Ready), .B0(RCKEEN_8_u_1), .A0(CBR), .DI0(RCKEEN_8), .CLK(RCLK_c), .F0(RCKEEN_8), .Q0(RCKEEN), .F1(RCKEEN_8_u_0_0)); - SLICE_36 SLICE_36( .D1(RASr2), .A1(RCKE_c), .D0(RASr2), .C0(RASr3), - .B0(RASr), .A0(RCKEEN), .DI0(RCKE_2), .CLK(RCLK_c), .F0(RCKE_2), - .Q0(RCKE_c), .F1(nRWE_0io_RNO_2)); - SLICE_37 SLICE_37( .D1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), - .D0(Ready_0_sqmuxa_0_a3_2), .C0(N_248), .B0(InitReady), .A0(Ready), - .DI0(N_587_0), .CLK(RCLK_c), .F0(N_587_0), .Q0(Ready), .F1(N_248)); - SLICE_38 SLICE_38( .D1(N_248), .C1(Ready_0_sqmuxa_0_a3_2), .B1(InitReady), - .A1(Ready), .C0(Ready_0_sqmuxa), .A0(Ready_fast), .DI0(N_588_0), - .CLK(RCLK_c), .F0(N_588_0), .Q0(Ready_fast), .F1(Ready_0_sqmuxa)); - SLICE_39 SLICE_39( .D1(Ready_fast), .B1(\MAin_c[1] ), .D0(Ready_fast), - .B0(\MAin_c[0] ), .DI1(\RowAd_0[1] ), .DI0(\RowAd_0[0] ), .CLK(nCRAS_c), + SLICE_35 SLICE_35( .D1(RASr2), .A1(\S[1] ), .D0(RASr2), .C0(RASr), + .B0(RASr3), .A0(RCKEEN), .DI0(RCKE_2), .CLK(RCLK_c), .F0(RCKE_2), + .Q0(RCKE_c), .F1(m3_0_a2_0)); + SLICE_36 SLICE_36( .D1(\IS[1] ), .C1(\IS[2] ), .B1(\IS[0] ), + .D0(Ready_0_sqmuxa_0_o2), .C0(InitReady), .B0(Ready_0_sqmuxa_0_a2_2), + .A0(Ready), .DI0(N_706_0), .CLK(RCLK_c), .F0(N_706_0), .Q0(Ready), + .F1(Ready_0_sqmuxa_0_o2)); + SLICE_37 SLICE_37( .D1(Ready_0_sqmuxa_0_a2_2), .C1(Ready_0_sqmuxa_0_o2), + .B1(InitReady), .A1(Ready), .B0(Ready_0_sqmuxa), .A0(Ready_fast), + .DI0(N_707_0), .CLK(RCLK_c), .F0(N_707_0), .Q0(Ready_fast), + .F1(Ready_0_sqmuxa)); + SLICE_38 SLICE_38( .D1(\MAin_c[1] ), .B1(Ready_fast), .D0(\MAin_c[0] ), + .B0(Ready_fast), .DI1(\RowAd_0[1] ), .DI0(\RowAd_0[0] ), .CLK(nCRAS_c), .F0(\RowAd_0[0] ), .Q0(\RowA[0] ), .F1(\RowAd_0[1] ), .Q1(\RowA[1] )); - SLICE_40 SLICE_40( .D1(\MAin_c[3] ), .B1(Ready_fast), .D0(\MAin_c[2] ), - .B0(Ready_fast), .DI1(\RowAd_0[3] ), .DI0(\RowAd_0[2] ), .CLK(nCRAS_c), + SLICE_39 SLICE_39( .B1(Ready_fast), .A1(\MAin_c[3] ), .B0(Ready_fast), + .A0(\MAin_c[2] ), .DI1(\RowAd_0[3] ), .DI0(\RowAd_0[2] ), .CLK(nCRAS_c), .F0(\RowAd_0[2] ), .Q0(\RowA[2] ), .F1(\RowAd_0[3] ), .Q1(\RowA[3] )); - SLICE_41 SLICE_41( .D1(Ready_fast), .A1(\MAin_c[5] ), .D0(Ready_fast), - .A0(\MAin_c[4] ), .DI1(\RowAd_0[5] ), .DI0(\RowAd_0[4] ), .CLK(nCRAS_c), + SLICE_40 SLICE_40( .D1(\MAin_c[5] ), .A1(Ready_fast), .C0(\MAin_c[4] ), + .A0(Ready_fast), .DI1(\RowAd_0[5] ), .DI0(\RowAd_0[4] ), .CLK(nCRAS_c), .F0(\RowAd_0[4] ), .Q0(\RowA[4] ), .F1(\RowAd_0[5] ), .Q1(\RowA[5] )); - SLICE_42 SLICE_42( .D1(Ready_fast), .C1(\MAin_c[7] ), .D0(Ready_fast), - .C0(\MAin_c[6] ), .DI1(\RowAd_0[7] ), .DI0(\RowAd_0[6] ), .CLK(nCRAS_c), + SLICE_41 SLICE_41( .D1(\MAin_c[7] ), .B1(Ready_fast), .D0(\MAin_c[6] ), + .B0(Ready_fast), .DI1(\RowAd_0[7] ), .DI0(\RowAd_0[6] ), .CLK(nCRAS_c), .F0(\RowAd_0[6] ), .Q0(\RowA[6] ), .F1(\RowAd_0[7] ), .Q1(\RowA[7] )); - SLICE_43 SLICE_43( .B1(Ready_fast), .A1(\MAin_c[9] ), .C0(\MAin_c[8] ), - .B0(Ready_fast), .DI1(\RowAd_0[9] ), .DI0(\RowAd_0[8] ), .CLK(nCRAS_c), + SLICE_42 SLICE_42( .D1(\MAin_c[9] ), .C1(Ready_fast), .D0(\MAin_c[8] ), + .C0(Ready_fast), .DI1(\RowAd_0[9] ), .DI0(\RowAd_0[8] ), .CLK(nCRAS_c), .F0(\RowAd_0[8] ), .Q0(\RowA[8] ), .F1(\RowAd_0[9] ), .Q1(\RowA[9] )); - SLICE_44 SLICE_44( .D1(Ready), .C1(N_41), .B1(CBR_fast), .A1(RASr2), - .B0(CO0), .A0(\S[1] ), .DI0(N_41), .LSR(RASr2), .CLK(RCLK_c), .F0(N_41), - .Q0(\S[1] ), .F1(nRCAS_0_sqmuxa_1)); - SLICE_45 SLICE_45( .D1(\Din_c[5] ), .C1(N_134), .B1(\Din_c[4] ), - .A1(XOR8MEG), .D0(\Din_c[1] ), .C0(N_274), .B0(LEDEN), - .A0(XOR8MEG_3_u_0_a2_0_2), .DI0(XOR8MEG_3), .CE(XOR8MEG18), .CLK(PHI2_c), - .F0(XOR8MEG_3), .Q0(XOR8MEG), .F1(N_274)); - SLICE_46 SLICE_46( .D1(N_4), .C1(CmdValid), .B1(InitReady), .A1(g1_0), - .D0(n8MEGENe_1_0), .C0(CmdValid_RNITBH02), .A0(n8MEGEN), .DI0(n8MEGENe_0), - .CLK(RCLK_c), .F0(n8MEGENe_0), .Q0(n8MEGEN), .F1(CmdValid_RNITBH02)); - SLICE_47 SLICE_47( .D1(Ready), .C1(CASr3), .B1(FWEr), .A1(CBR), .D0(Ready), - .C0(N_255), .B0(CO0), .A0(\S[1] ), .DI0(nRowColSel_0_0), - .LSR(nRRAS_0_sqmuxa), .CLK(RCLK_c), .F0(nRowColSel_0_0), .Q0(nRowColSel), - .F1(N_255)); - SLICE_48 SLICE_48( .D1(N_384), .C1(\FS[12] ), .B1(\FS[11] ), - .A1(\wb_adr_5_i_i_0[1] ), .D0(\wb_adr_5_i_i_5[0] ), .C0(N_313), - .B0(\FS[11] ), .A0(N_367), .DI1(N_282), .DI0(N_283), .CE(N_122), - .CLK(RCLK_c), .F0(N_283), .Q0(\wb_adr[0] ), .F1(N_282), .Q1(\wb_adr[1] )); - SLICE_49 SLICE_49( .D1(\wb_adr[2] ), .A1(InitReady), .C0(\wb_adr[1] ), - .A0(InitReady), .DI1(\wb_adr_5[3] ), .DI0(\wb_adr_5[2] ), .CE(N_122), + SLICE_43 SLICE_43( .D1(RASr2), .C1(Ready), .B1(RCKE_c), .A1(\S_0_i_o3[1] ), + .B0(CO0), .A0(\S[1] ), .DI0(\S_0_i_o3[1] ), .LSR(RASr2), .CLK(RCLK_c), + .F0(\S_0_i_o3[1] ), .Q0(\S[1] ), .F1(nRCS_9_u_i_0_0)); + SLICE_44 SLICE_44( .D1(\Din_c[4] ), .C1(N_353), .B1(\Din_c[5] ), + .A1(XOR8MEG), .D0(XOR8MEG_3_u_0_0_a2_0_2), .C0(LEDEN), .B0(N_411), + .A0(\Din_c[1] ), .DI0(XOR8MEG_3), .CE(XOR8MEG18), .CLK(PHI2_c), + .F0(XOR8MEG_3), .Q0(XOR8MEG), .F1(N_411)); + SLICE_45 SLICE_45( .D1(g1_0), .C1(N_4), .B1(CmdValid), .A1(InitReady), + .D0(n8MEGENe_1_0), .C0(un1_FS_38_i), .A0(n8MEGEN), .DI0(n8MEGENe_0), + .CLK(RCLK_c), .F0(n8MEGENe_0), .Q0(n8MEGEN), .F1(un1_FS_38_i)); + SLICE_46 SLICE_46( .C1(CASr3), .B1(FWEr), .D0(CBR), .C0(N_251_i_1_0), + .B0(N_70_i), .A0(Ready), .DI0(nRowColSel_0_0), .LSR(nRRAS_0_sqmuxa), + .CLK(RCLK_c), .F0(nRowColSel_0_0), .Q0(nRowColSel), .F1(N_251_i_1_0)); + SLICE_47 SLICE_47( .D1(\wb_adr_5_i_3_0_a2[1] ), + .C1(\wb_adr_5_i_3_0_a2_0[1] ), .B1(\wb_adr_5_i_3_0_0[1] ), .A1(N_216), + .D0(\FS_RNIOVGI[9] ), .C0(\wb_dati_5_1_iv_0_a2_11[3] ), + .B0(\wb_adr_5_i_0_3[0] ), .A0(\wb_adr_5_i_0_2[0] ), .DI1(N_45_i), + .DI0(N_47_i), .CE(N_126_i), .CLK(RCLK_c), .F0(N_47_i), .Q0(\wb_adr[0] ), + .F1(N_45_i), .Q1(\wb_adr[1] )); + SLICE_48 SLICE_48( .C1(\wb_adr[2] ), .A1(InitReady), .C0(\wb_adr[1] ), + .A0(InitReady), .DI1(\wb_adr_5[3] ), .DI0(\wb_adr_5[2] ), .CE(N_126_i), .CLK(RCLK_c), .F0(\wb_adr_5[2] ), .Q0(\wb_adr[2] ), .F1(\wb_adr_5[3] ), .Q1(\wb_adr[3] )); - SLICE_50 SLICE_50( .D1(N_132), .C1(InitReady), .A1(\wb_adr[4] ), .D0(N_132), - .C0(InitReady), .A0(\wb_adr[3] ), .DI1(N_80), .DI0(N_81), .CE(N_122), - .CLK(RCLK_c), .F0(N_81), .Q0(\wb_adr[4] ), .F1(N_80), .Q1(\wb_adr[5] )); - SLICE_51 SLICE_51( .D1(\wb_adr[6] ), .B1(InitReady), .C0(N_132), - .B0(InitReady), .A0(\wb_adr[5] ), .DI1(\wb_adr_5[7] ), - .DI0(\wb_adr_5_i_m2_0[6] ), .CE(N_122), .CLK(RCLK_c), - .F0(\wb_adr_5_i_m2_0[6] ), .Q0(\wb_adr[6] ), .F1(\wb_adr_5[7] ), - .Q1(\wb_adr[7] )); - SLICE_52 SLICE_52( .D1(\FS[0] ), .C1(N_132), .B1(wb_req), .A1(N_330_4), - .D0(InitReady), .C0(N_330), .B0(CmdUFMWrite), .A0(un1_PHI2r3), - .DI0(wb_cyc_stb_4), .CE(N_103), .LSR(wb_rst10), .CLK(RCLK_c), - .F0(wb_cyc_stb_4), .Q0(wb_cyc_stb), .F1(N_330)); - SLICE_53 SLICE_53( .D1(N_226), .C1(N_302), .B1(N_303), .A1(N_233), - .D0(\wb_dati_5_0_iv_0_a2_0[0] ), .C0(N_383), .B0(InitReady), .A0(wb_we), - .DI1(\wb_dati_5[1] ), .DI0(\wb_dati_5[0] ), .CE(N_122), .CLK(RCLK_c), + SLICE_49 SLICE_49( .D1(\wb_adr[4] ), .C1(\FS_RNI82PA[15] ), .A1(InitReady), + .C0(\FS_RNI82PA[15] ), .B0(\wb_adr[3] ), .A0(InitReady), + .DI1(\wb_adr_5[5] ), .DI0(\wb_adr_5[4] ), .CE(N_126_i), .CLK(RCLK_c), + .F0(\wb_adr_5[4] ), .Q0(\wb_adr[4] ), .F1(\wb_adr_5[5] ), .Q1(\wb_adr[5] )); + SLICE_50 SLICE_50( .D1(\wb_adr[6] ), .A1(InitReady), .C0(\wb_adr[5] ), + .B0(\FS_RNI82PA[15] ), .A0(InitReady), .DI1(\wb_adr_5[7] ), + .DI0(\wb_adr_5[6] ), .CE(N_126_i), .CLK(RCLK_c), .F0(\wb_adr_5[6] ), + .Q0(\wb_adr[6] ), .F1(\wb_adr_5[7] ), .Q1(\wb_adr[7] )); + SLICE_51 SLICE_51( .D1(N_99_2), .C1(N_99_1), .B1(wb_cyc_stb_4_iv_0_0_a2_0_0), + .A1(\FS_RNIHVJI[15] ), .D0(un1_PHI2r3_i_li), .C0(wb_cyc_stb_4_iv_0_0_a2_0), + .B0(InitReady), .A0(CmdUFMWrite), .DI0(wb_cyc_stb_4), + .CE(wb_cyc_stb_2_sqmuxa_i_0_0), .LSR(wb_rst10), .CLK(RCLK_c), + .F0(wb_cyc_stb_4), .Q0(wb_cyc_stb), .F1(wb_cyc_stb_4_iv_0_0_a2_0)); + SLICE_52 SLICE_52( .D1(\wb_dati_5_1_iv_0_1[1] ), .C1(\FS_RNIGOCT[12] ), + .B1(\FS_RNIS637[9] ), .A1(\FS[11] ), .D0(wb_we), .C0(InitReady), + .B0(\wb_dati_5_1_iv_0_a2_12[3] ), .A0(\wb_dati_5_0_iv_0_a2_1[0] ), + .DI1(\wb_dati_5[1] ), .DI0(\wb_dati_5[0] ), .CE(N_126_i), .CLK(RCLK_c), .F0(\wb_dati_5[0] ), .Q0(\wb_dati[0] ), .F1(\wb_dati_5[1] ), .Q1(\wb_dati[1] )); - SLICE_54 SLICE_54( .D1(\wb_dati[2] ), .C1(N_341), - .B1(\wb_dati_5_1_iv_0_1[3] ), .A1(InitReady), .D0(N_335), - .C0(\wb_dati[1] ), .B0(\wb_dati_5_1_iv_0_o2_0[5] ), .A0(InitReady), - .DI1(\wb_dati_5[3] ), .DI0(\wb_dati_5[2] ), .CE(N_122), .CLK(RCLK_c), - .F0(\wb_dati_5[2] ), .Q0(\wb_dati[2] ), .F1(\wb_dati_5[3] ), - .Q1(\wb_dati[3] )); - SLICE_55 SLICE_55( .D1(\wb_dati_5_1_iv_0_o2_0[5] ), .C1(\wb_dati[4] ), - .B1(InitReady), .A1(N_335), .C0(\wb_dati_5_1_iv_0_2[4] ), - .B0(\wb_dati_5_1_iv_0_0[4] ), .A0(N_335), .DI1(\wb_dati_5[5] ), - .DI0(\wb_dati_5[4] ), .CE(N_122), .CLK(RCLK_c), .F0(\wb_dati_5[4] ), - .Q0(\wb_dati[4] ), .F1(\wb_dati_5[5] ), .Q1(\wb_dati[5] )); - SLICE_56 SLICE_56( .D1(N_345), .C1(\wb_dati_5_1_iv_0_a2_1_1[7] ), - .B1(\wb_dati_5_1_iv_0_1[7] ), .A1(N_375), .D0(\wb_dati_5_1_iv_0_0[6] ), - .C0(N_233), .B0(N_348_2), .A0(N_383), .DI1(\wb_dati_5[7] ), - .DI0(\wb_dati_5[6] ), .CE(N_122), .CLK(RCLK_c), .F0(\wb_dati_5[6] ), + SLICE_53 SLICE_53( .D1(\wb_dati_5_1_iv_0_0_a2_1[3] ), + .C1(\wb_dati_5_1_iv_0_a2_13[3] ), .B1(\wb_dati_5_1_iv_0_0_0[3] ), + .A1(\wb_dati_5_1_iv_0_0_1[3] ), .D0(\wb_dati_5_1_iv_0_0_o2[5] ), + .C0(\wb_dati[1] ), .A0(InitReady), .DI1(\wb_dati_5[3] ), + .DI0(\wb_dati_5[2] ), .CE(N_126_i), .CLK(RCLK_c), .F0(\wb_dati_5[2] ), + .Q0(\wb_dati[2] ), .F1(\wb_dati_5[3] ), .Q1(\wb_dati[3] )); + SLICE_54 SLICE_54( .D1(\wb_dati_5_1_iv_0_0_o2[5] ), .C1(InitReady), + .A1(\wb_dati[4] ), .D0(\FS[9] ), .C0(\FS_RNIGOCT[12] ), + .B0(\wb_dati_5_1_iv_0_1_0[4] ), .A0(\wb_dati_5_1_iv_0_0_1[4] ), + .DI1(\wb_dati_5[5] ), .DI0(\wb_dati_5[4] ), .CE(N_126_i), .CLK(RCLK_c), + .F0(\wb_dati_5[4] ), .Q0(\wb_dati[4] ), .F1(\wb_dati_5[5] ), + .Q1(\wb_dati[5] )); + SLICE_55 SLICE_55( .D1(\wb_dati_5_1_iv_0_a2_5[7] ), + .C1(\wb_dati_5_1_iv_0_1[7] ), .B1(\wb_dati_5_1_iv_0_a2_13[3] ), + .A1(\wb_dati_5_1_iv_0_RNO[7] ), .D0(\FS_RNIGOCT[12] ), .C0(\FS[11] ), + .B0(\wb_dati_5_1_iv_0_0_1[6] ), .A0(\FS_RNIS637[9] ), .DI1(\wb_dati_5[7] ), + .DI0(\wb_dati_5[6] ), .CE(N_126_i), .CLK(RCLK_c), .F0(\wb_dati_5[6] ), .Q0(\wb_dati[6] ), .F1(\wb_dati_5[7] ), .Q1(\wb_dati[7] )); - SLICE_57 SLICE_57( .D1(\FS[14] ), .C1(\FS[13] ), .B1(\FS[12] ), .A1(N_131), - .D0(N_94_i), .C0(N_34_i), .A0(wb_req), .DI0(wb_reqe_0), .LSR(wb_rst10), - .CLK(RCLK_c), .F0(wb_reqe_0), .Q0(wb_req), .F1(N_34_i)); - SLICE_58 SLICE_58( .D1(InitReady), .C1(\FS[17] ), .B1(\FS[16] ), - .A1(\FS[15] ), .D0(N_94_i), .C0(wb_rst10), .B0(\FS[14] ), .A0(wb_rst), - .DI0(wb_rste_0), .CLK(RCLK_c), .F0(wb_rste_0), .Q0(wb_rst), .F1(wb_rst10)); - SLICE_59 SLICE_59( .D1(\wb_dati[3] ), .C1(N_362), .B1(InitReady), .A1(N_394), - .D0(N_353), .C0(wb_we_0_0_0_0), .B0(InitReady), .A0(CmdUFMData), - .DI0(wb_we_0_0_0), .CE(N_122), .LSR(wb_rst10), .CLK(RCLK_c), - .F0(wb_we_0_0_0), .Q0(wb_we), .F1(\wb_dati_5_1_iv_0_0[4] )); - SLICE_60 SLICE_60( .D1(\FS[13] ), .C1(\FS[9] ), .B1(N_132), .A1(N_129), - .D0(N_362), .C0(\FS[13] ), .B0(N_226), .A0(N_223), - .F0(\wb_dati_5_1_iv_0_1[3] ), .F1(N_226)); - SLICE_61 SLICE_61( .D1(\FS[16] ), .C1(\FS[17] ), .B1(InitReady), - .A1(\FS[15] ), .D0(N_132), .C0(\wb_adr[0] ), .B0(InitReady), .A0(N_428_tz), - .F0(\wb_adr_5_i_i_0[1] ), .F1(N_132)); - SLICE_62 SLICE_62( .D1(InitReady), .C1(CO0), .B1(\S[1] ), .A1(RASr2), - .D0(\S[1] ), .C0(N_49), .B0(N_43), .A0(Ready), .F0(N_39), .F1(N_43)); - SLICE_63 SLICE_63( .D1(N_131), .C1(N_142), .B1(N_125), .A1(\FS[13] ), - .D0(N_131), .C0(N_356), .B0(\FS[12] ), .A0(N_133), .F0(wb_we_0_0_0_0), - .F1(N_356)); - SLICE_64 SLICE_64( .D1(\Din_c[3] ), .C1(\Din_c[6] ), .B1(N_381), - .A1(\MAin_c[0] ), .D0(\MAin_c[1] ), .C0(N_374), .B0(N_393), - .A0(\MAin_c[0] ), .F0(un1_CmdEnable20_0_0), .F1(N_393)); - SLICE_65 SLICE_65( .D1(\FS[14] ), .C1(\wb_adr_5_i_i_a2_0[1] ), .B1(N_142), - .A1(\FS[13] ), .D0(\FS[11] ), .C0(N_125), .B0(\FS[12] ), .A0(\FS[13] ), - .F0(\wb_adr_5_i_i_a2_0[1] ), .F1(N_428_tz)); - SLICE_66 SLICE_66( .D1(\FS[11] ), .C1(\FS[9] ), .A1(\FS[12] ), .D0(\FS[11] ), - .C0(\wb_adr_5_i_i_a2_3_0[0] ), .B0(\FS[10] ), .A0(\FS[13] ), - .F0(\wb_adr_5_i_i_1_0_tz_0[0] ), .F1(\wb_adr_5_i_i_a2_3_0[0] )); - SLICE_67 SLICE_67( .D1(N_132), .C1(N_142), .B1(N_125), .A1(g0_0_a3_1), - .D0(\FS[14] ), .B0(\FS[13] ), .A0(wb_ack), .F0(g0_0_a3_1), .F1(N_4)); - SLICE_68 SLICE_68( .D1(nRWE_0io_RNO_2), .C1(IS_0_sqmuxa_0_o2), - .B1(nRRAS_0_sqmuxa), .A1(nRWE_0io_RNO_1), .D0(Ready), .C0(\S[1] ), - .B0(CO0), .F0(nRRAS_0_sqmuxa), .F1(nRWE_0io_RNO_0)); - SLICE_69 SLICE_69( .D1(\FS[11] ), .C1(N_220), .B1(N_367), - .A1(\wb_dati_5_1_iv_0_0[7] ), .D0(\FS[9] ), .B0(\FS[12] ), .A0(\FS[10] ), - .F0(N_220), .F1(\wb_dati_5_1_iv_0_1[7] )); - SLICE_70 SLICE_70( .D1(\FS[11] ), .C1(\FS[14] ), .B1(\FS[12] ), - .A1(\FS[13] ), .C0(\FS[10] ), .B0(N_348_2), .A0(\FS[9] ), - .F0(\wb_dati_5_1_iv_0_a2_3_0[7] ), .F1(N_348_2)); - SLICE_71 SLICE_71( .D1(\FS[14] ), .C1(N_143), .A1(N_131), .D0(\FS[10] ), - .C0(\FS[13] ), .B0(\FS[9] ), .A0(\FS[11] ), .F0(N_143), .F1(N_353)); - SLICE_72 SLICE_72( .D1(\FS[14] ), .C1(N_137), .B1(N_132), .A1(\FS[13] ), - .D0(\FS[11] ), .C0(\FS[12] ), .B0(\FS[9] ), .A0(\FS[10] ), .F0(N_137), - .F1(N_335)); - SLICE_73 SLICE_73( .D1(N_374), .C1(\Din_c[5] ), .B1(\MAin_c[1] ), - .A1(\Din_c[3] ), .D0(\Din_c[2] ), .C0(N_382), - .B0(un1_CmdEnable20_0_a2_3_0), .A0(\Din_c[6] ), .M1(nCCAS_c_i), - .M0(nCCAS_c_i), .CLK(nCRAS_c), .F0(CmdEnable17), .Q0(CBR), - .F1(un1_CmdEnable20_0_a2_3_0), .Q1(CBR_fast)); - SLICE_74 SLICE_74( .D1(N_134), .C1(\Din_c[3] ), .B1(\Din_c[4] ), - .A1(\Din_c[5] ), .D0(\MAin_c[1] ), .C0(N_382), .B0(N_380), .A0(CmdEnable), - .F0(CmdUFMData_1_sqmuxa), .F1(N_380)); - SLICE_75 SLICE_75( .D1(\Bank[3] ), .C1(un1_ADWR_i_o2_11), - .B1(un1_ADWR_i_o2_10), .A1(\Bank[1] ), .D0(\MAin_c[0] ), .B0(N_294), - .F0(N_382), .F1(N_294)); - SLICE_76 SLICE_76( .C1(\MAin_c[1] ), .A1(N_374), .D0(N_294), - .C0(ADSubmitted), .B0(N_393), .A0(N_378), .M0(CASr2), .CLK(RCLK_c), - .F0(CmdEnable_0_sqmuxa), .Q0(CASr3), .F1(N_378)); - SLICE_77 SLICE_77( .D1(\FS[14] ), .C1(\wb_adr_5_i_i_a2_6_0[0] ), .B1(N_132), - .D0(\wb_adr_5_i_i_1[0] ), .C0(N_384), .B0(N_314), .A0(N_315), - .F0(\wb_adr_5_i_i_5[0] ), .F1(N_314)); - SLICE_78 SLICE_78( .D1(Ready), .B1(N_43), .D0(\IS[2] ), .C0(\IS[1] ), - .B0(IS_0_sqmuxa_0_o2), .A0(\IS[3] ), .F0(RA10s_i), .F1(IS_0_sqmuxa_0_o2)); - SLICE_79 SLICE_79( .D1(\FS[10] ), .C1(N_132), .B1(\FS[9] ), - .D0(\wb_adr_5_i_i_a2_6_0[0] ), .C0(N_383), .B0(N_348_2), .A0(N_367), - .F0(\wb_dati_5_1_iv_0_2[4] ), .F1(N_383)); - SLICE_80 SLICE_80( .B1(\FS[9] ), .A1(\FS[10] ), .D0(N_367), .C0(\FS[11] ), - .B0(N_125), .A0(\FS[12] ), .F0(N_233), .F1(N_125)); - SLICE_81 SLICE_81( .D1(nRCS_0io_RNO_0), .C1(N_37_i_1), .B1(N_28_i_1), - .A1(nRCS_9_u_i_0), .D0(N_49), .C0(N_43), .B0(nRCS_9_u_i_0_0), .A0(\IS[0] ), - .F0(nRCS_9_u_i_0), .F1(N_28_i)); - SLICE_82 SLICE_82( .D1(\FS[12] ), .A1(\FS[11] ), .D0(\FS[13] ), .C0(N_376), - .B0(\FS[14] ), .A0(N_383), .F0(N_345), .F1(N_376)); - SLICE_83 SLICE_83( .D1(\FS[11] ), .C1(\FS[9] ), .B1(\FS[12] ), .A1(\FS[10] ), - .D0(N_226), .C0(N_133), .B0(N_132), .A0(N_394), - .F0(\wb_dati_5_1_iv_0_o2_0[5] ), .F1(N_394)); - SLICE_84 SLICE_84( .D1(N_132), .C1(\FS[14] ), - .D0(\wb_dati_5_1_iv_0_a2_1[6] ), .C0(N_362), .B0(InitReady), - .A0(\wb_dati[5] ), .F0(\wb_dati_5_1_iv_0_0[6] ), .F1(N_362)); - SLICE_85 SLICE_85( .D1(\FS[12] ), .C1(N_132), .B1(\FS[13] ), .A1(N_125), - .D0(InitReady), .C0(\wb_dati[7] ), .B0(\wb_adr_5_i_i_1_0[0] ), .A0(N_307), - .F0(\wb_adr_5_i_i_1[0] ), .F1(N_307)); - SLICE_86 SLICE_86( .D1(\FS[13] ), .A1(\FS[14] ), .D0(\FS[12] ), .C0(N_132), - .B0(N_133), .A0(\wb_adr_5_i_i_1_0_tz_0[0] ), .F0(\wb_adr_5_i_i_1_0[0] ), - .F1(N_133)); - SLICE_87 SLICE_87( .D1(wb_req), .B1(\FS[0] ), .D0(wb_ack), .C0(N_132), - .B0(N_295), .A0(N_330_4), .F0(N_103), .F1(N_295)); - SLICE_88 SLICE_88( .C1(N_132), .A1(\FS[9] ), .D0(\FS[10] ), .C0(\FS[11] ), - .B0(N_375), .A0(\FS[13] ), .F0(N_315), .F1(N_375)); - SLICE_89 SLICE_89( .D1(\MAin_c[7] ), .C1(\MAin_c[5] ), .B1(\MAin_c[2] ), - .A1(\MAin_c[4] ), .D0(un1_ADWR_i_o2_3), .C0(\Bank[2] ), .B0(\Bank[0] ), - .A0(un1_ADWR_i_o2_4), .F0(un1_ADWR_i_o2_10), .F1(un1_ADWR_i_o2_4)); - SLICE_90 SLICE_90( .D1(\IS[0] ), .C1(nRCS_9_u_i_0_0), .B1(N_43), .A1(N_49), - .D0(Ready), .C0(RCKE_c), .B0(N_41), .A0(RASr2), .F0(nRCS_9_u_i_0_0), - .F1(N_25_i)); - SLICE_91 SLICE_91( .D1(\FS[6] ), .C1(\FS[7] ), .D0(\FS[8] ), - .C0(wb_cyc_stb_2_sqmuxa_i_a2_3_3), .B0(\FS[3] ), - .A0(wb_cyc_stb_2_sqmuxa_i_a2_3_4), .F0(N_330_4), - .F1(wb_cyc_stb_2_sqmuxa_i_a2_3_3)); - SLICE_92 SLICE_92( .D1(nRCAS_0_sqmuxa_1), .C1(N_37_i_1), .B1(nRWE_0io_RNO_0), - .A1(N_28_i_1), .D0(CASr3), .C0(CASr2), .B0(CO0), .A0(FWEr_fast), - .F0(N_37_i_1), .F1(N_37_i)); - SLICE_93 SLICE_93( .C1(\Din_c[4] ), .A1(\Din_c[0] ), .D0(N_134), .C0(N_371), - .B0(N_381), .A0(\Din_c[3] ), .F0(XOR8MEG_3_u_0_a2_0_2), .F1(N_371)); - SLICE_94 SLICE_94( .D1(\FS[9] ), .A1(\FS[10] ), .D0(\FS[11] ), .C0(\FS[13] ), - .B0(N_141), .A0(\FS[12] ), .F0(\wb_dati_5_1_iv_0_a2_1[6] ), .F1(N_141)); - SLICE_95 SLICE_95( .D1(PHI2r2), .A1(PHI2r3), .D0(CmdValid_fast), - .C0(InitReady), .B0(G_8_0_a3_0_0), .A0(CmdUFMShift), .F0(N_122), - .F1(G_8_0_a3_0_0)); - SLICE_96 SLICE_96( .D1(nRCAS_0io_RNO_1), .C1(FWEr), .B1(CO0), .A1(CBR), - .D0(\S[1] ), .C0(nRCAS_0_sqmuxa_1), .B0(N_242_i_1), .A0(N_39), - .F0(N_242_i), .F1(N_242_i_1)); - SLICE_97 SLICE_97( .D1(PHI2r2), .C1(CmdValid), .A1(PHI2r3), .D0(PHI2r2), - .C0(CmdValid), .B0(InitReady), .A0(PHI2r3), .F0(N_94_i), .F1(un1_PHI2r3)); - SLICE_98 SLICE_98( .D1(\FS[12] ), .C1(\FS[10] ), .B1(\FS[9] ), .D0(\FS[12] ), - .C0(\FS[10] ), .B0(\FS[9] ), .A0(\FS[11] ), .F0(N_223), - .F1(\wb_adr_5_i_i_a2_6_0[0] )); - SLICE_99 SLICE_99( .D1(\FS[14] ), .C1(\FS[13] ), .B1(N_132), .D0(\FS[14] ), - .C0(\FS[13] ), .B0(N_132), .A0(N_394), .F0(N_303), .F1(N_367)); - SLICE_100 SLICE_100( .D1(\FS[11] ), .C1(\FS[13] ), .B1(\FS[12] ), - .A1(\FS[14] ), .D0(\FS[11] ), .C0(\FS[10] ), .B0(\FS[12] ), .A0(\FS[14] ), - .F0(N_129), .F1(\wb_dati_5_0_iv_0_a2_0[0] )); - SLICE_101 SLICE_101( .D1(\FS[11] ), .A1(\FS[12] ), .D0(N_362), .C0(N_125), - .B0(\FS[11] ), .A0(\FS[12] ), .F0(N_341), .F1(N_142)); - SLICE_102 SLICE_102( .D1(\MAin_c[9] ), .A1(nRowColSel), .D0(\MAin_c[9] ), - .A0(nRowColSel), .F0(RDQMH_c), .F1(RDQML_c)); - SLICE_103 SLICE_103( .D1(\FS[10] ), .C1(\FS[17] ), .B1(\FS[16] ), - .A1(\FS[15] ), .D0(InitReady), .C0(\FS[17] ), .B0(\FS[16] ), .F0(N_131), - .F1(InitReady3_0_a2_2)); - SLICE_104 SLICE_104( .D1(\Din_c[7] ), .C1(\Din_c[6] ), .B1(\Din_c[5] ), - .A1(\Din_c[4] ), .D0(\Din_c[7] ), .C0(\Din_c[6] ), .F0(N_134), - .F1(CmdLEDEN_4_u_i_a2_0_0)); - SLICE_105 SLICE_105( .B1(FWEr), .A1(CO0), .D0(\S[1] ), .C0(CASr2), .B0(FWEr), - .A0(CO0), .F0(RCKEEN_8_u_1), .F1(nRCS_0io_RNO_0)); - SLICE_106 SLICE_106( .D1(CmdEnable), .C1(\MAin_c[1] ), .B1(\MAin_c[0] ), - .A1(N_294), .D0(\MAin_c[0] ), .C0(\Din_c[2] ), - .B0(un1_CmdEnable20_0_a2_3_0), .A0(\Din_c[6] ), - .F0(un1_CmdEnable20_0_a2_1_0), .F1(XOR8MEG18)); - SLICE_107 SLICE_107( .D1(\FS[14] ), .C1(N_132), .B1(\FS[13] ), .A1(N_125), - .C0(\FS[13] ), .B0(\FS[12] ), .A0(N_383), .F0(N_313), .F1(N_384)); - SLICE_108 SLICE_108( .D1(InitReady), .C1(\wb_dato[0] ), .A1(Cmdn8MEGEN), - .D0(\wb_dati[6] ), .C0(InitReady), .B0(N_132), - .A0(\wb_dati_5_1_iv_0_a2_3_0[7] ), .F0(\wb_dati_5_1_iv_0_0[7] ), + SLICE_56 SLICE_56( .D1(\FS[14] ), .C1(\FS[13] ), .B1(un1_wb_rst14_2_0_o2), + .A1(\FS[12] ), .D0(N_122_i), .C0(un1_wb_rst14_2_i), .A0(wb_req), + .DI0(wb_reqe_0), .LSR(wb_rst10), .CLK(RCLK_c), .F0(wb_reqe_0), .Q0(wb_req), + .F1(un1_wb_rst14_2_i)); + SLICE_57 SLICE_57( .D1(CmdValid), .C1(PHI2r3), .B1(InitReady), .A1(PHI2r2), + .C0(N_122_i), .B0(wb_rst_3), .A0(wb_rst), .DI0(wb_rste_0), .CLK(RCLK_c), + .F0(wb_rste_0), .Q0(wb_rst), .F1(N_122_i)); + SLICE_58 SLICE_58( .D1(\FS[17] ), .B1(\FS[16] ), .A1(InitReady), + .D0(un1_wb_rst14_2_0_o2), .C0(wb_we_0_0_i_1), .B0(CmdUFMData), + .A0(InitReady), .DI0(N_346_i), .CE(N_126_i), .LSR(wb_rst10), .CLK(RCLK_c), + .F0(N_346_i), .Q0(wb_we), .F1(un1_wb_rst14_2_0_o2)); + wb_dati_5_1_iv_0_0_o2_5__SLICE_59 \wb_dati_5_1_iv_0_0_o2[5]/SLICE_59 ( + .D1(\wb_dati_5_1_iv_0_o2[7] ), .C1(\FS_RNIHVJI[15] ), + .B1(\wb_dati_5_1_iv_0_o2_0_RNIMDJC1[4] ), .A1(\FS[12] ), + .D0(\wb_dati_5_1_iv_0_0_o2[3] ), .C0(\FS_RNIHVJI[15] ), + .B0(\wb_dati_5_1_iv_0_o2_0_RNIMDJC1[4] ), .A0(\FS[13] ), .M0(\FS[9] ), + .OFX0(\wb_dati_5_1_iv_0_0_o2[5] )); + wb_adr_5_i_0_1_0__SLICE_60 \wb_adr_5_i_0_1[0]/SLICE_60 ( + .C1(\wb_dati_5_1_iv_0_o2_0[7] ), .B1(\FS_RNIJO0F[12] ), .A1(\FS[13] ), + .D0(InitReady), .C0(\FS[9] ), .B0(\FS[10] ), .A0(\FS_RNI9Q57[12] ), + .M0(\FS[11] ), .OFX0(\wb_adr_5_i_0_1[0] )); + SLICE_61 SLICE_61( .D1(InitReady), .C1(N_313), .B1(\FS_RNI9Q57[12] ), + .A1(\FS[14] ), .D0(InitReady), .C0(\wb_adr_5_i_0_o2[0] ), .B0(\FS[13] ), + .A0(\FS[14] ), .F0(N_313), .F1(\wb_adr_5_i_0_0[0] )); + SLICE_62 SLICE_62( .D1(InitReady), .C1(\S[1] ), .B1(CO0), .A1(RASr2), + .D0(\S[1] ), .C0(IS_0_sqmuxa_0_o2), .B0(Ready), + .A0(un1_nRCAS_6_sqmuxa_i_o2), .F0(N_48), .F1(IS_0_sqmuxa_0_o2)); + SLICE_63 SLICE_63( .D1(\Din_c[6] ), .C1(N_466), .B1(\MAin_c[0] ), + .A1(\Din_c[3] ), .D0(N_483), .C0(N_457), .B0(\MAin_c[0] ), + .A0(\MAin_c[1] ), .F0(un1_CmdEnable20_0_0_0), .F1(N_483)); + SLICE_64 SLICE_64( .D1(\FS[15] ), .C1(\FS[16] ), .B1(InitReady), + .A1(\FS[17] ), .D0(\wb_dati[0] ), .C0(\FS_RNIHVJI[15] ), .B0(InitReady), + .A0(\wb_dati_5_1_iv_0_a2_0_2[1] ), .F0(\wb_dati_5_1_iv_0_0[1] ), + .F1(\FS_RNIHVJI[15] )); + SLICE_65 SLICE_65( .D1(\wb_dati_5_1_iv_0_a2_13[3] ), .C1(\FS[9] ), + .B1(\FS[10] ), .A1(\wb_dati_5_1_iv_0_0_o2[4] ), .D0(\FS[13] ), + .B0(\FS[10] ), .A0(\FS[11] ), .F0(\wb_dati_5_1_iv_0_0_o2[4] ), + .F1(\wb_dati_5_1_iv_0_1_0[4] )); + SLICE_66 SLICE_66( .C1(\FS[9] ), .B1(\FS[10] ), .A1(\FS[11] ), + .C0(\ufmefb/g0_0_a3_2 ), .B0(\FS_RNIF2MA[9] ), .A0(\FS_RNIHVJI[15] ), + .F0(N_4), .F1(\FS_RNIF2MA[9] )); + SLICE_67 SLICE_67( .D1(\wb_dati_5_1_iv_0_0_o2[4] ), .C1(\wb_adr_5_i_0_1[0] ), + .B1(\FS[9] ), .A1(\FS_RNIJO0F[12] ), .C0(InitReady), .B0(\FS[12] ), + .A0(\FS[14] ), .F0(\FS_RNIJO0F[12] ), .F1(\wb_adr_5_i_0_3[0] )); + SLICE_68 SLICE_68( .D1(RCKE_c), .C1(nRWE_s_i_a2_1_0), .B1(nRRAS_0_sqmuxa), + .A1(RASr2), .C0(CO0), .B0(Ready), .A0(\S[1] ), .F0(nRRAS_0_sqmuxa), + .F1(nRWE_s_i_tz_0)); + SLICE_69 SLICE_69( .D1(nRCS_9_u_i_o3_0_0), .C1(RCKEEN_8_u_0_o3), .B1(FWEr), + .A1(CBR), .D0(N_48), .C0(CO0), .A0(CASr2), .F0(nRCS_9_u_i_o3_0_0), + .F1(nRCS_9_u_i_o3_0_2)); + SLICE_70 SLICE_70( .D1(\wb_adr_5_i_0_a2_6[0] ), .C1(\FS_RNIOVGI[9] ), + .B1(wb_we_0_0_i_1_1), .A1(\FS_RNI9Q57[12] ), .D0(InitReady), .C0(\FS[9] ), + .B0(\FS[11] ), .A0(\FS[10] ), .F0(\FS_RNIOVGI[9] ), .F1(wb_we_0_0_i_1)); + SLICE_71 SLICE_71( .C1(\FS[10] ), .A1(\FS[9] ), .D0(\FS[11] ), + .C0(\FS_RNIS637[9] ), .B0(\wb_adr_5_i_3_0_a2_3[1] ), .A0(\FS[12] ), + .F0(\wb_adr_5_i_3_0_0[1] ), .F1(\FS_RNIS637[9] )); + SLICE_72 SLICE_72( .D1(\FS[9] ), .C1(\FS[10] ), .B1(\FS[11] ), + .D0(\FS_RNI7U6M[14] ), .C0(\FS[13] ), .B0(\wb_dati_5_1_iv_0_o2_0[4] ), + .A0(\FS[12] ), .F0(\wb_dati_5_1_iv_0_o2_0_RNIMDJC1[4] ), + .F1(\wb_dati_5_1_iv_0_o2_0[4] )); + SLICE_73 SLICE_73( .C1(\wb_dati_5_1_iv_0_a2_5[7] ), + .B1(\wb_dati_5_1_iv_0_0_o2[4] ), .A1(\FS[14] ), .D0(\FS[12] ), + .C0(\wb_dati_5_1_iv_0_o2[7] ), .B0(\FS_RNIHVJI[15] ), .A0(\FS[9] ), + .F0(\wb_dati_5_1_iv_0_1_RNO[7] ), .F1(\wb_dati_5_1_iv_0_o2[7] )); + SLICE_74 SLICE_74( .D1(\FS[14] ), .C1(\FS[12] ), .B1(\FS_RNIHVJI[15] ), + .A1(\FS[13] ), .D0(\FS[10] ), .C0(\FS_RNIGOCT[12] ), .B0(\FS[9] ), + .A0(\FS[11] ), .F0(\wb_dati_5_1_iv_0_RNO[7] ), .F1(\FS_RNIGOCT[12] )); + SLICE_75 SLICE_75( .D1(Ready), .C1(CO0), .B1(m3_0_a2_0), .A1(CBR_fast), + .D0(N_142), .C0(nRWE_s_i_tz_0), .B0(nRCAS_0_sqmuxa_1), .A0(N_141), + .F0(N_252_i), .F1(nRCAS_0_sqmuxa_1)); + SLICE_76 SLICE_76( .D1(N_457), .B1(\MAin_c[1] ), .A1(N_482), + .D0(C1Submitted), .C0(un1_CmdEnable20_0_0_a2_1_1), + .B0(un1_CmdEnable20_0_0_0), .A0(N_367), .M1(nCCAS_c_i), .M0(nCCAS_c_i), + .CLK(nCRAS_c), .F0(un1_CmdEnable20_i), .Q0(CBR), + .F1(un1_CmdEnable20_0_0_a2_1_1), .Q1(CBR_fast)); + SLICE_77 SLICE_77( .D1(\Din_c[3] ), .C1(\Din_c[4] ), .B1(\Din_c[5] ), + .A1(N_353), .C0(XOR8MEG18), .B0(N_461), .M0(CASr2), .CLK(RCLK_c), + .F0(CmdUFMData_1_sqmuxa), .Q0(CASr3), .F1(N_461)); + SLICE_78 SLICE_78( .C1(CO0), .B1(FWEr), .D0(nRCS_9_u_i_0), .C0(N_251_i_1), + .B0(N_142), .A0(N_141), .F0(N_37_i), .F1(N_251_i_1)); + SLICE_79 SLICE_79( .D1(IS_0_sqmuxa_0_o2), .B1(Ready), .D0(\IS[3] ), + .C0(IS_0_sqmuxa_0_o3), .B0(\IS[2] ), .A0(\IS[1] ), .F0(RA10s_i), + .F1(IS_0_sqmuxa_0_o3)); + SLICE_80 SLICE_80( .D1(\Bank[6] ), .C1(\Bank[3] ), .B1(\Bank[5] ), + .A1(\Bank[2] ), .D0(un1_CmdEnable20_0_0_o2_10), + .C0(un1_CmdEnable20_0_0_o2_11), .B0(\Bank[4] ), .A0(\Bank[0] ), .F0(N_367), + .F1(un1_CmdEnable20_0_0_o2_11)); + SLICE_81 SLICE_81( .D1(\wb_dati_5_1_iv_0_a2_7[4] ), .C1(\FS[10] ), + .B1(\wb_dati_5_1_iv_0_a2_12[3] ), .A1(\wb_dati_5_1_iv_0_a2_6[4] ), + .D0(\wb_dati_5_1_iv_0_a2_2[4] ), .C0(\wb_dati[5] ), + .B0(\wb_dati_5_1_iv_0_0_a2[6] ), .A0(InitReady), + .F0(\wb_dati_5_1_iv_0_0_1[6] ), .F1(\wb_dati_5_1_iv_0_a2_2[4] )); + SLICE_82 SLICE_82( .D1(\wb_dati_5_1_iv_0_a2_0_0[7] ), .C1(\FS[9] ), + .B1(\FS_RNIHVJI[15] ), .A1(\FS[10] ), .D0(\wb_dati_5_1_iv_0_a2_0[7] ), + .C0(\wb_dati_5_1_iv_0_1_RNO[7] ), .B0(InitReady), .A0(\wb_dati[6] ), + .F0(\wb_dati_5_1_iv_0_1[7] ), .F1(\wb_dati_5_1_iv_0_a2_0[7] )); + SLICE_83 SLICE_83( .D1(\IS[3] ), .C1(\IS[2] ), .A1(\IS[1] ), + .D0(nRCS_9_u_i_0_0), .C0(\IS[0] ), .B0(IS_0_sqmuxa_0_o2), + .A0(un1_nRCAS_6_sqmuxa_i_o2), .F0(nRCS_9_u_i_0), + .F1(un1_nRCAS_6_sqmuxa_i_o2)); + SLICE_84 SLICE_84( .D1(\FS[14] ), .C1(\FS_RNIHVJI[15] ), .A1(\FS[12] ), + .D0(\FS[13] ), .C0(\wb_dati_5_1_iv_0_a2_13[3] ), + .B0(\wb_dati_5_1_iv_0_o2_0[7] ), .A0(\FS[11] ), + .F0(\wb_dati_5_1_iv_0_0_a2[6] ), .F1(\wb_dati_5_1_iv_0_a2_13[3] )); + SLICE_85 SLICE_85( .D1(\FS[14] ), .C1(\FS[10] ), .B1(\FS[12] ), + .A1(\FS[11] ), .D0(\wb_dati_5_1_iv_0_0[1] ), + .C0(\wb_dati_5_1_iv_0_0_o2[3] ), .B0(\wb_dati_5_1_iv_0_a2_12[3] ), + .A0(\FS[13] ), .F0(\wb_dati_5_1_iv_0_1[1] ), + .F1(\wb_dati_5_1_iv_0_0_o2[3] )); + SLICE_86 SLICE_86( .D1(\FS[11] ), .C1(\FS_RNI7U6M[14] ), .B1(\FS[12] ), + .A1(\FS_RNIS637[9] ), .D0(\wb_dati[2] ), .C0(\wb_dati_5_1_iv_0_a2_7[3] ), + .B0(InitReady), .F0(\wb_dati_5_1_iv_0_0_0[3] ), + .F1(\wb_dati_5_1_iv_0_a2_7[3] )); + SLICE_87 SLICE_87( .C1(\FS[9] ), .B1(\FS_RNIHVJI[15] ), + .D0(\wb_dati_5_1_iv_0_0_o2[3] ), .C0(\wb_dati_5_1_iv_0_a2_12[3] ), + .B0(\wb_dati_5_1_iv_0_a2_5[3] ), .A0(\FS[13] ), + .F0(\wb_dati_5_1_iv_0_0_1[3] ), .F1(\wb_dati_5_1_iv_0_a2_12[3] )); + SLICE_88 SLICE_88( .D1(\FS[14] ), .C1(\FS_RNIHVJI[15] ), + .D0(\FS_RNIS637[9] ), .C0(\FS_RNI7U6M[14] ), + .B0(\wb_dati_5_1_iv_0_a2_11[3] ), .A0(\FS[11] ), + .F0(\wb_dati_5_1_iv_0_a2_5[3] ), .F1(\FS_RNI7U6M[14] )); + SLICE_89 SLICE_89( .D1(N_99_1), .C1(\FS[0] ), .B1(wb_req), .D0(N_99_2), + .C0(wb_ack), .B0(wb_cyc_stb_2_sqmuxa_i_0_0_a2_0), .A0(\FS_RNIHVJI[15] ), + .F0(wb_cyc_stb_2_sqmuxa_i_0_0), .F1(wb_cyc_stb_2_sqmuxa_i_0_0_a2_0)); + SLICE_90 SLICE_90( .D1(\MAin_c[6] ), .C1(\MAin_c[7] ), .B1(\MAin_c[4] ), + .A1(nFWE_c), .D0(\Bank[1] ), .C0(un1_CmdEnable20_0_0_o2_4), + .B0(un1_CmdEnable20_0_0_o2_3), .A0(\Bank[7] ), + .F0(un1_CmdEnable20_0_0_o2_10), .F1(un1_CmdEnable20_0_0_o2_4)); + SLICE_91 SLICE_91( .D1(\FS[15] ), .C1(\FS[16] ), .B1(\FS[17] ), + .D0(InitReady), .C0(\FS_RNI82PA[15] ), .B0(\wb_adr_5_i_0_0[0] ), + .A0(\wb_dati[7] ), .F0(\wb_adr_5_i_0_2[0] ), .F1(\FS_RNI82PA[15] )); + SLICE_92 SLICE_92( .C1(\Din_c[5] ), .A1(\Din_c[3] ), .D0(\Din_c[2] ), + .C0(N_442), .B0(\MAin_c[0] ), .A0(\Din_c[6] ), .F0(N_482), .F1(N_442)); + SLICE_93 SLICE_93( .D1(\wb_dati_5_1_iv_0_a2_11[3] ), .C1(InitReady), + .B1(\wb_dati_5_1_iv_0_o2_0[4] ), .A1(wb_we_0_0_i_a2_0), .D0(\FS[12] ), + .C0(\FS[13] ), .B0(\FS_RNIS637[9] ), .A0(\wb_adr_5_i_0_a2_6[0] ), + .F0(wb_we_0_0_i_a2_0), .F1(wb_we_0_0_i_1_1)); + SLICE_94 SLICE_94( .B1(InitReady), .A1(\FS[14] ), .D0(\FS[16] ), + .C0(\FS[15] ), .B0(\FS[17] ), .A0(\wb_adr_5_i_3_0_a2_3[1] ), .F0(wb_rst_3), + .F1(\wb_adr_5_i_3_0_a2_3[1] )); + SLICE_95 SLICE_95( .B1(\FS[7] ), .A1(\FS[1] ), .D0(\FS[5] ), + .C0(wb_cyc_stb_2_sqmuxa_i_a2_2_0), .B0(\FS[2] ), .A0(\FS[4] ), .F0(N_99_2), + .F1(wb_cyc_stb_2_sqmuxa_i_a2_2_0)); + SLICE_96 SLICE_96( .C1(\Din_c[6] ), .B1(\Din_c[7] ), .D0(N_452), .C0(N_353), + .B0(N_466), .A0(\Din_c[3] ), .F0(XOR8MEG_3_u_0_0_a2_0_2), .F1(N_353)); + SLICE_97 SLICE_97( .D1(\FS[9] ), .B1(\FS[10] ), + .D0(\wb_dati_5_1_iv_0_a2_7[4] ), .C0(\FS[13] ), + .B0(\wb_dati_5_1_iv_0_o2_0[7] ), .A0(\FS[11] ), + .F0(\wb_dati_5_1_iv_0_a2_0_2[1] ), .F1(\wb_dati_5_1_iv_0_o2_0[7] )); + SLICE_98 SLICE_98( .D1(\FS[13] ), .C1(\FS[11] ), .D0(\FS[10] ), + .C0(\FS[12] ), .B0(\wb_dati_5_1_iv_0_a2_6[4] ), .A0(\FS[14] ), + .F0(\wb_dati_5_0_iv_0_a2_1[0] ), .F1(\wb_dati_5_1_iv_0_a2_6[4] )); + SLICE_99 SLICE_99( .D1(\FS[14] ), .C1(InitReady3_0_a2_1_0), + .B1(\FS_RNI9Q57[12] ), .A1(\FS[11] ), .D0(\FS[16] ), .C0(\FS[10] ), + .B0(\FS[17] ), .A0(\FS[15] ), .F0(InitReady3_0_a2_1_0), .F1(InitReady3)); + SLICE_100 SLICE_100( .D1(PHI2r2), .B1(PHI2r3), .D0(CmdValid_fast), + .C0(InitReady), .B0(G_4_0_a3_0), .A0(CmdUFMShift), .F0(N_126_i), + .F1(G_4_0_a3_0)); + SLICE_101 SLICE_101( .D1(N_251_i_1_0), .C1(nRCS_9_u_i_o3_0_2), + .B1(N_251_i_1), .A1(N_251_i_sx), .C0(\S[1] ), .B0(nRCAS_0_sqmuxa_1), + .A0(N_48), .F0(N_251_i_sx), .F1(N_251_i)); + SLICE_102 SLICE_102( .D1(\FS[14] ), .C1(\FS[13] ), .B1(\FS[12] ), + .A1(\FS[11] ), .D0(\FS[14] ), .C0(wb_ack), .B0(\FS[13] ), .A0(\FS[12] ), + .F0(\ufmefb/g0_0_a3_2 ), .F1(\wb_dati_5_1_iv_0_a2_0_0[7] )); + SLICE_103 SLICE_103( .D1(CASr2), .C1(\S[1] ), .B1(FWEr), .A1(CO0), .D0(FWEr), + .C0(CASr2), .B0(CASr3), .A0(CO0), .F0(N_142), .F1(RCKEEN_8_u_1)); + SLICE_104 SLICE_104( .D1(\FS[13] ), .C1(\FS[9] ), .B1(\FS[10] ), + .A1(\FS[11] ), .D0(\FS[13] ), .B0(\FS[10] ), .A0(\FS[11] ), + .F0(\wb_dati_5_1_iv_0_a2_5[7] ), .F1(\wb_dati_5_1_iv_0_0_a2_1[3] )); + SLICE_105 SLICE_105( .B1(\FS[12] ), .A1(\FS[13] ), .D0(\FS[14] ), + .C0(\FS_RNIOVGI[9] ), .B0(\FS[12] ), .A0(\FS[13] ), + .F0(\wb_adr_5_i_3_0_a2[1] ), .F1(\FS_RNI9Q57[12] )); + SLICE_106 SLICE_106( .D1(Ready), .C1(CBR), .A1(\S[1] ), .D0(CBR), + .C0(nCRAS_c), .B0(LEDEN), .A0(Ready), .F0(LED_c), .F1(N_141)); + SLICE_107 SLICE_107( .C1(\FS[14] ), .A1(InitReady), .D0(\FS_RNIF2MA[9] ), + .C0(\FS[14] ), .B0(\FS[13] ), .A0(InitReady), + .F0(\wb_adr_5_i_3_0_a2_0[1] ), .F1(\wb_adr_5_i_0_a2_6[0] )); + SLICE_108 SLICE_108( .D1(nRowColSel), .C1(\MAin_c[9] ), .D0(nRowColSel), + .C0(\MAin_c[9] ), .F0(RDQMH_c), .F1(RDQML_c)); + SLICE_109 SLICE_109( .D1(\Din_c[4] ), .C1(\Din_c[1] ), .B1(\Din_c[0] ), + .A1(\Din_c[7] ), .D0(\Din_c[4] ), .B0(\Din_c[0] ), .F0(N_452), .F1(N_457)); + SLICE_110 SLICE_110( .C1(PHI2r2), .A1(PHI2r3), .D0(CmdValid), .C0(PHI2r2), + .A0(PHI2r3), .F0(un1_PHI2r3_i_li), .F1(g1_0)); + SLICE_111 SLICE_111( .D1(Cmdn8MEGEN), .C1(\wb_dato[0] ), .A1(InitReady), + .D0(\wb_dati[3] ), .C0(InitReady), .B0(\wb_dati_5_1_iv_0_a2_2[4] ), + .A0(\wb_dati_5_1_iv_0_o2_0_RNIMDJC1[4] ), .F0(\wb_dati_5_1_iv_0_0_1[4] ), .F1(n8MEGENe_1_0)); - SLICE_109 SLICE_109( .D1(\RowA[3] ), .C1(nRowColSel), .A1(\MAin_c[3] ), - .D0(\MAin_c[6] ), .C0(nFWE_c), .A0(\MAin_c[3] ), .F0(un1_ADWR_i_o2_3), - .F1(\RA_c[3] )); - SLICE_110 SLICE_110( .D1(\RowA[8] ), .C1(\MAin_c[8] ), .A1(nRowColSel), - .C0(nRowColSel), .B0(\MAin_c[9] ), .A0(\RowA[9] ), .F0(\RA_c[9] ), + SLICE_112 SLICE_112( .C1(\MAin_c[2] ), .B1(nRowColSel), .A1(\RowA[2] ), + .D0(\MAin_c[3] ), .C0(\MAin_c[2] ), .B0(\MAin_c[5] ), + .F0(un1_CmdEnable20_0_0_o2_3), .F1(\RA_c[2] )); + SLICE_113 SLICE_113( .D1(\RowA[8] ), .C1(nRowColSel), .A1(\MAin_c[8] ), + .D0(\MAin_c[0] ), .B0(\RowA[0] ), .A0(nRowColSel), .F0(\RA_c[0] ), .F1(\RA_c[8] )); - SLICE_111 SLICE_111( .D1(nRowColSel), .B1(\MAin_c[0] ), .A1(\RowA[0] ), - .D0(nRowColSel), .C0(\RowA[7] ), .B0(\MAin_c[7] ), .F0(\RA_c[7] ), - .F1(\RA_c[0] )); - SLICE_112 SLICE_112( .D1(nRowColSel), .C1(\RowA[1] ), .A1(\MAin_c[1] ), - .D0(\MAin_c[6] ), .C0(nRowColSel), .B0(\RowA[6] ), .F0(\RA_c[6] ), - .F1(\RA_c[1] )); - SLICE_113 SLICE_113( .D1(\RowA[2] ), .C1(\MAin_c[2] ), .A1(nRowColSel), - .D0(\RowA[5] ), .B0(\MAin_c[5] ), .A0(nRowColSel), .F0(\RA_c[5] ), - .F1(\RA_c[2] )); - SLICE_114 SLICE_114( .C1(\IS[0] ), .D0(\IS[1] ), .C0(\IS[2] ), .A0(\IS[0] ), - .F0(nRWE_0io_RNO_1), .F1(\IS_i[0] )); - SLICE_115 SLICE_115( .D1(Ready_fast), .A1(\CROW_c[0] ), .D0(Ready_fast), - .C0(\Din_c[6] ), .B0(n8MEGEN), .A0(XOR8MEG), .F0(RA11d_0), - .F1(\RBAd_0[0] )); - SLICE_116 SLICE_116( .D1(InitReady), .B1(\wb_dati[0] ), .C0(PHI2r3), - .B0(PHI2r2), .F0(g1_0), .F1(N_302)); - SLICE_117 SLICE_117( .D1(Ready), .C1(\S[1] ), .B1(CBR_fast), .C0(CASr2), - .B0(CASr3), .F0(nRCAS_0io_RNO_1), .F1(N_28_i_1)); + SLICE_114 SLICE_114( .D1(\RowA[3] ), .B1(nRowColSel), .A1(\MAin_c[3] ), + .D0(\MAin_c[1] ), .C0(\RowA[1] ), .A0(nRowColSel), .F0(\RA_c[1] ), + .F1(\RA_c[3] )); + SLICE_115 SLICE_115( .D1(nRowColSel), .C1(\RowA[9] ), .B1(\MAin_c[9] ), + .D0(nRowColSel), .B0(\RowA[4] ), .A0(\MAin_c[4] ), .F0(\RA_c[4] ), + .F1(\RA_c[9] )); + SLICE_116 SLICE_116( .D1(\RowA[7] ), .C1(nRowColSel), .B1(\MAin_c[7] ), + .D0(nRowColSel), .C0(\RowA[5] ), .B0(\MAin_c[5] ), .F0(\RA_c[5] ), + .F1(\RA_c[7] )); + SLICE_117 SLICE_117( .D1(CO0), .B1(\S[1] ), .D0(CO0), .B0(CASr2), + .F0(RCKEEN_8_u_0_o3), .F1(N_70_i)); + SLICE_118 SLICE_118( .D1(\FS[14] ), .A1(\FS[12] ), .B0(\FS[13] ), + .A0(\FS[12] ), .F0(\wb_dati_5_1_iv_0_a2_11[3] ), + .F1(\wb_dati_5_1_iv_0_a2_7[4] )); + SLICE_119 SLICE_119( .D1(\Din_c[4] ), .C1(\Din_c[5] ), .B1(\Din_c[6] ), + .A1(\Din_c[7] ), .D0(\Din_c[2] ), .B0(\Din_c[5] ), .F0(N_466), + .F1(CmdLEDEN_4_u_i_m2_i_a2_0_0)); + SLICE_120 SLICE_120( .D1(\CROW_c[1] ), .B1(Ready_fast), .D0(XOR8MEG), + .C0(\Din_c[6] ), .B0(Ready_fast), .A0(n8MEGEN), .F0(RA11d_0), + .F1(\RBAd_0[1] )); + SLICE_121 SLICE_121( .D1(wb_req), .C1(\FS[0] ), .D0(\FS[6] ), .C0(\FS[8] ), + .A0(\FS[3] ), .F0(N_99_1), .F1(wb_cyc_stb_4_iv_0_0_a2_0_0)); + SLICE_122 SLICE_122( .D1(InitReady), .B1(\FS_RNI82PA[15] ), .A1(\wb_adr[0] ), + .D0(IS_0_sqmuxa_0_o2), .A0(Ready), .F0(N_261_i), .F1(N_216)); RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .IOLDO(\WRD[0] ), .PADDT(RD_1_i), .RD0(RD[0])); RD_0__MGIOL \RD[0]_MGIOL ( .IOLDO(\WRD[0] ), .OPOS(\Din_c[0] ), @@ -457,18 +524,18 @@ module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, RDQML RDQML_I( .PADDO(RDQML_c), .RDQML(RDQML)); RDQMH RDQMH_I( .PADDO(RDQMH_c), .RDQMH(RDQMH)); nRCAS nRCAS_I( .IOLDO(nRCAS_c), .nRCAS(nRCAS)); - nRCAS_MGIOL nRCAS_MGIOL( .IOLDO(nRCAS_c), .OPOS(N_242_i), .CLK(RCLK_c)); + nRCAS_MGIOL nRCAS_MGIOL( .IOLDO(nRCAS_c), .OPOS(N_251_i), .CLK(RCLK_c)); nRRAS nRRAS_I( .IOLDO(nRRAS_c), .nRRAS(nRRAS)); - nRRAS_MGIOL nRRAS_MGIOL( .IOLDO(nRRAS_c), .OPOS(N_25_i), .CLK(RCLK_c)); + nRRAS_MGIOL nRRAS_MGIOL( .IOLDO(nRRAS_c), .OPOS(N_32_i), .CLK(RCLK_c)); nRWE nRWE_I( .IOLDO(nRWE_c), .nRWE(nRWE)); - nRWE_MGIOL nRWE_MGIOL( .IOLDO(nRWE_c), .OPOS(N_37_i), .CLK(RCLK_c)); + nRWE_MGIOL nRWE_MGIOL( .IOLDO(nRWE_c), .OPOS(N_252_i), .CLK(RCLK_c)); RCKE RCKE_I( .PADDO(RCKE_c), .RCKE(RCKE)); RCLKout RCLKout_I( .IOLDO(RCLKout_c), .RCLKout(RCLKout)); RCLKout_MGIOL RCLKout_MGIOL( .IOLDO(RCLKout_c), .ONEG(VCC), .OPOS(GND), .CLK(RCLK_c)); RCLK RCLK_I( .PADDI(RCLK_c), .RCLK(RCLK)); nRCS nRCS_I( .IOLDO(nRCS_c), .nRCS(nRCS)); - nRCS_MGIOL nRCS_MGIOL( .IOLDO(nRCS_c), .OPOS(N_28_i), .CLK(RCLK_c)); + nRCS_MGIOL nRCS_MGIOL( .IOLDO(nRCS_c), .OPOS(N_37_i), .CLK(RCLK_c)); RD_7_ \RD[7]_I ( .PADDI(\RD_in[7] ), .IOLDO(\WRD[7] ), .PADDT(RD_1_i), .RD7(RD[7])); RD_7__MGIOL \RD[7]_MGIOL ( .IOLDO(\WRD[7] ), .OPOS(\Din_c[7] ), @@ -908,12 +975,12 @@ module SLICE_9 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); endmodule -module SLICE_10 ( input C1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); +module SLICE_10 ( input C1, B1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly; - lut4 ADSubmitted_r_0_RNO( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1)); + lut4 un1_ADWR_i_i_a2( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40003 ADSubmitted_r_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40003 ADSubmitted_r_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre ADSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -921,7 +988,7 @@ module SLICE_10 ( input C1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); specify (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); @@ -936,12 +1003,12 @@ endmodule module lut4 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h5050) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0C0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40003 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h3130) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h3302) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module inverter ( input I, output Z ); @@ -953,7 +1020,7 @@ module SLICE_11 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly; - lut40004 CmdEnable16_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40004 CmdEnable16_0_a2_1_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40005 C1Submitted_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre C1Submitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); @@ -980,18 +1047,18 @@ endmodule module lut40004 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40005 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hECEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hEAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_12 ( input D0, DI0, M1, CLK, output F0, Q0, Q1 ); +module SLICE_12 ( input B0, DI0, M1, CLK, output F0, Q0, Q1 ); wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; - lut40006 nCCAS_pad_RNISUR8( .A(GNDI), .B(GNDI), .C(GNDI), .D(D0), .Z(F0)); + lut40006 nCCAS_pad_RNISUR8( .A(GNDI), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre CASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); @@ -1000,7 +1067,7 @@ module SLICE_12 ( input D0, DI0, M1, CLK, output F0, Q0, Q1 ); .LSR(GNDI), .Q(Q0)); specify - (D0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); @@ -1013,15 +1080,15 @@ endmodule module lut40006 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h00FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h3333) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_16 ( input D1, C1, B1, A1, C0, B0, DI0, LSR, CLK, output F0, Q0, +module SLICE_16 ( input D1, C1, B1, A1, D0, C0, DI0, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; - lut40007 Ready_0_sqmuxa_0_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40008 \S_RNO[0] ( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40007 Ready_0_sqmuxa_0_a2_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40008 \S_RNO[0] ( .A(GNDI), .B(GNDI), .C(C0), .D(D0), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre0009 \S[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); @@ -1033,8 +1100,8 @@ module SLICE_16 ( input D1, C1, B1, A1, C0, B0, DI0, LSR, CLK, output F0, Q0, (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); @@ -1053,7 +1120,7 @@ endmodule module lut40008 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hF3F3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFF0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module vmuxregsre0009 ( input D0, D1, SD, SP, CK, LSR, output Q ); @@ -1066,7 +1133,8 @@ module SLICE_17 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly; - lut40010 CmdEnable_s_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40010 un1_CmdEnable20_0_0_a2_3_RNIJ3N91( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); lut40011 CmdEnable_s( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre CmdEnable( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); @@ -1093,19 +1161,19 @@ endmodule module lut40010 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h000D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40011 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hEFEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFEAE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_18 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; - lut40012 CmdLEDEN_4_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40012 CmdLEDEN_4_u_i_m2_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40013 CmdLEDEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre CmdLEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), @@ -1132,7 +1200,7 @@ endmodule module lut40012 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h7530) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h5D0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40013 ( input A, B, C, D, output Z ); @@ -1140,18 +1208,18 @@ module lut40013 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0B0B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_19 ( input M0, CE, CLK, output F0, Q0, F1 ); +module SLICE_19 ( input D0, M0, CE, CLK, output F0, Q0 ); wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; - lut40014 GND( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F1)); + lut40014 RA10_0io_RNO( .A(GNDI), .B(GNDI), .C(GNDI), .D(D0), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40015 VCC( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre CmdUFMData( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); specify + (D0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); @@ -1163,31 +1231,21 @@ endmodule module lut40014 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h00FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40015 ( input A, B, C, D, output Z ); +module SLICE_20 ( input D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; - ROM16X1A #(16'hFFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_20 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output - F0, Q0, F1 ); - wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly; - - lut40016 un1_CmdEnable20_0_a2_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40017 CmdUFMShift_3_u_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40015 GND( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40016 CmdUFMShift_3_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre CmdUFMShift( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); @@ -1201,23 +1259,24 @@ module SLICE_20 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output endmodule +module lut40015 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + module lut40016 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hAE0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40017 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h88F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_21 ( input D1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, +module SLICE_21 ( input D1, B1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; - lut40018 CmdUFMWrite_3_u_0_a2( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1)); + lut40017 CmdUFMWrite_3_u_0_0_0_a2( .A(GNDI), .B(B1), .C(GNDI), .D(D1), + .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40019 CmdUFMWrite_3_u_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40018 CmdUFMWrite_3_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre CmdUFMWrite( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1225,7 +1284,7 @@ module SLICE_21 ( input D1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, specify (D1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); @@ -1239,21 +1298,21 @@ module SLICE_21 ( input D1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, endmodule +module lut40017 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCC00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + module lut40018 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hAA00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hAAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40019 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF0F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_22 ( input D1, C1, B1, A1, C0, B0, DI0, CLK, output F0, Q0, F1 ); +module SLICE_22 ( input D1, C1, B1, A1, D0, C0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly; - lut40020 CmdValid_2_i_o2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40021 CmdValid_r( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40019 CmdValid_2_i_o2_0_o2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40020 CmdValid_r( .A(GNDI), .B(GNDI), .C(C0), .D(D0), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre CmdValid( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); @@ -1265,8 +1324,8 @@ module SLICE_22 ( input D1, C1, B1, A1, C0, B0, DI0, CLK, output F0, Q0, F1 ); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); @@ -1275,21 +1334,21 @@ module SLICE_22 ( input D1, C1, B1, A1, C0, B0, DI0, CLK, output F0, Q0, F1 ); endmodule +module lut40019 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF2FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + module lut40020 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFF75) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0F00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40021 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0303) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_23 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 ); +module SLICE_23 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly; - lut40022 CmdEnable_RNI7PMB1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40023 CmdValid_r_fast( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); + lut40021 CmdUFMData_1_sqmuxa_0_a2_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40022 CmdValid_r_fast( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre CmdValid_fast( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); @@ -1301,7 +1360,7 @@ module SLICE_23 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 ); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); @@ -1311,22 +1370,22 @@ module SLICE_23 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 ); endmodule +module lut40021 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + module lut40022 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hEFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h4444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40023 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0505) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_24 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, +module SLICE_24 ( input D1, C1, B1, A1, D0, C0, B0, DI0, CE, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; - lut40024 Cmdn8MEGEN_4_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40025 Cmdn8MEGEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40023 Cmdn8MEGEN_4_u_i_m2_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40024 Cmdn8MEGEN_RNO( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre Cmdn8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); @@ -1338,9 +1397,9 @@ module SLICE_24 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); @@ -1350,31 +1409,31 @@ module SLICE_24 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, endmodule +module lut40023 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA0EC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + module lut40024 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hF444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h3033) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40025 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0D0D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_25 ( input D1, A1, D0, DI0, CLK, output F0, Q0, F1 ); +module SLICE_25 ( input C1, B1, C0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly; - lut40026 nCCAS_pad_RNI01SJ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1)); + lut40025 nCCAS_pad_RNI01SJ( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40006 nFWE_pad_RNI420B( .A(GNDI), .B(GNDI), .C(GNDI), .D(D0), .Z(F0)); + lut40026 FWEr_RNO( .A(GNDI), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre FWEr( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); specify - (D1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); @@ -1383,61 +1442,34 @@ module SLICE_25 ( input D1, A1, D0, DI0, CLK, output F0, Q0, F1 ); endmodule +module lut40025 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFCFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + module lut40026 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0F0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_26 ( input C1, A1, D0, C0, M0, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly; - - lut40027 \RBAd[1] ( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40028 XOR8MEG_3_u_0_a2_2( .A(GNDI), .B(GNDI), .C(C0), .D(D0), .Z(F0)); - vmuxregsre FWEr_fast( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - endspecify - -endmodule - -module lut40027 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hA0A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40028 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h000F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_27 ( input B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); +module SLICE_26 ( input D1, C1, B1, A1, D0, C0, A0, DI0, CLK, output F0, Q0, + F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly; - lut40029 IS_0_sqmuxa_0_o2_0_RNIS63D( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); + lut40027 nRRAS_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40028 \IS_RNO[0] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40030 \IS_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \IS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); @@ -1447,23 +1479,23 @@ module SLICE_27 ( input B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); endmodule -module lut40029 ( input A, B, C, D, output Z ); +module lut40027 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h5501) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40030 ( input A, B, C, D, output Z ); +module lut40028 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hE1E1) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hAAA5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_28 ( input C1, B1, A1, C0, A0, DI1, DI0, CE, CLK, output F0, Q0, +module SLICE_27 ( input D1, B1, A1, D0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40031 \IS_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40029 \IS_RNO[2] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40032 IS_n1_0_x2( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); + lut40030 IS_n1_0_x2( .A(A0), .B(GNDI), .C(GNDI), .D(D0), .Z(F0)); vmuxregsre \IS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1471,10 +1503,10 @@ module SLICE_28 ( input C1, B1, A1, C0, A0, DI1, DI0, CE, CLK, output F0, Q0, .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify - (C1 => F1) = (0:0:0,0:0:0); + (D1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); @@ -1487,30 +1519,31 @@ module SLICE_28 ( input C1, B1, A1, C0, A0, DI1, DI0, CE, CLK, output F0, Q0, endmodule -module lut40031 ( input A, B, C, D, output Z ); +module lut40029 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h6A6A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h66AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40032 ( input A, B, C, D, output Z ); +module lut40030 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h5A5A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h55AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_29 ( input D1, C1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, - Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; +module SLICE_28 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; - lut40033 un1_nRCAS_6_sqmuxa_i_o2( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40034 \IS_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40031 nRWE_s_i_a2_1_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40032 \IS_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \IS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); @@ -1525,21 +1558,21 @@ module SLICE_29 ( input D1, C1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, endmodule -module lut40033 ( input A, B, C, D, output Z ); +module lut40031 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40034 ( input A, B, C, D, output Z ); +module lut40032 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h78F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h7F80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_30 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 ); +module SLICE_29 ( input D1, C1, B1, A1, D0, A0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly; - lut40035 InitReady3_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40036 InitReady_RNO( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); + lut40033 \FS_RNIHVJI_0[15] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40034 InitReady_RNO( .A(A0), .B(GNDI), .C(GNDI), .D(D0), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre InitReady( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); @@ -1550,7 +1583,42 @@ module SLICE_30 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 ); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40033 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40034 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_30 ( input D1, C1, A1, D0, B0, A0, DI0, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly; + + lut40035 LEDEN_6_i_m2( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40036 LEDENe( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); + vmuxregsre LEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); @@ -1562,33 +1630,33 @@ endmodule module lut40035 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hF0AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40036 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hCCAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_31 ( input D1, C1, B1, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly; +module SLICE_31 ( input C0, B0, M1, M0, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; - lut40037 LEDEN_6_i_m2( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40037 VCC( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40038 LEDENe( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre LEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + lut40038 \RBAd[0] ( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre PHI2r3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre PHI2r2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify @@ -1597,61 +1665,20 @@ endmodule module lut40037 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hCCF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40038 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hE4E4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hC0C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_32 ( input D1, C1, B1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; - - lut40039 \un9_RA_i_m2[4] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40040 un1_ADWR_i_o2_11( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre PHI2r3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre PHI2r2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40039 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF0CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40040 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_33 ( input D1, B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); +module SLICE_32 ( input C1, B1, A1, B0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; - lut40041 LED_pad_RNO( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + lut40039 \un9_RA_i_m2_i_m2[6] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40042 RASr_RNO( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); + lut40006 RASr_RNO( .A(GNDI), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre RASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1659,10 +1686,10 @@ module SLICE_33 ( input D1, B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); .LSR(GNDI), .Q(Q0)); specify - (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); @@ -1673,38 +1700,28 @@ module SLICE_33 ( input D1, B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); endmodule -module lut40041 ( input A, B, C, D, output Z ); +module lut40039 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hD8D8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40042 ( input A, B, C, D, output Z ); +module SLICE_33 ( input D1, B1, A1, C0, B0, M0, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, M0_dly, CLK_dly; - ROM16X1A #(16'h5555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_34 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0, - F1 ); - wire VCCI, GNDI, M0_dly, CLK_dly; - - lut40043 wb_cyc_stb_2_sqmuxa_i_a2_3_4( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40044 \wb_dati_5_1_iv_0_a2_1_1[7] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40040 \wb_adr_5_i_0_o2[0] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 CmdEnable_0_sqmuxa_0_a2_0_a2( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre RASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); specify (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $width (posedge CLK, 0:0:0); @@ -1713,22 +1730,22 @@ module SLICE_34 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0, endmodule -module lut40043 ( input A, B, C, D, output Z ); +module lut40040 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h88BB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40044 ( input A, B, C, D, output Z ); +module lut40041 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hC0C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_35 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, +module SLICE_34 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire VCCI, GNDI, DI0_dly, CLK_dly; - lut40045 RCKEEN_8_u_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40046 RCKEEN_8_u( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40042 RCKEEN_8_u_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40043 RCKEEN_8_u( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre RCKEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1751,22 +1768,22 @@ module SLICE_35 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, endmodule -module lut40045 ( input A, B, C, D, output Z ); +module lut40042 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h1F10) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0C5C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40046 ( input A, B, C, D, output Z ); +module lut40043 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hAAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFF40) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_36 ( input D1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); +module SLICE_35 ( input D1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly; - lut40047 nRWE_0io_RNO_2( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1)); + lut40044 RASr2_RNI6PUF( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40048 RCKE_2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40045 RCKE_2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre RCKE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1786,31 +1803,31 @@ module SLICE_36 ( input D1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); endmodule -module lut40047 ( input A, B, C, D, output Z ); +module lut40044 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h00AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h5500) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40048 ( input A, B, C, D, output Z ); +module lut40045 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hAAF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hAAEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_37 ( input D1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, +module SLICE_36 ( input D1, C1, B1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly; - lut40049 Ready_0_sqmuxa_0_o2( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + lut40046 Ready_0_sqmuxa_0_o2( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40050 Ready_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40047 Ready_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre Ready( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); specify (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); @@ -1823,21 +1840,21 @@ module SLICE_37 ( input D1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, endmodule -module lut40049 ( input A, B, C, D, output Z ); +module lut40046 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h77FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h3FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40050 ( input A, B, C, D, output Z ); +module lut40047 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hAEAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hAAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_38 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 ); +module SLICE_37 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly; - lut40051 Ready_0_sqmuxa_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40036 Ready_fast_RNO( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); + lut40048 Ready_0_sqmuxa_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40049 Ready_fast_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre Ready_fast( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); @@ -1848,7 +1865,7 @@ module SLICE_38 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 ); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); @@ -1858,17 +1875,22 @@ module SLICE_38 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 ); endmodule -module lut40051 ( input A, B, C, D, output Z ); +module lut40048 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_39 ( input D1, B1, D0, B0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); +module lut40049 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_38 ( input D1, B1, D0, B0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly; - lut40052 \RowAd[1] ( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + lut40050 \RowAd[1] ( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40052 \RowAd[0] ( .A(GNDI), .B(B0), .C(GNDI), .D(D0), .Z(F0)); + lut40050 \RowAd[0] ( .A(GNDI), .B(B0), .C(GNDI), .D(D0), .Z(F0)); vmuxregsre \RowA[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1891,17 +1913,17 @@ module SLICE_39 ( input D1, B1, D0, B0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); endmodule -module lut40052 ( input A, B, C, D, output Z ); +module lut40050 ( input A, B, C, D, output Z ); ROM16X1A #(16'hCC00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_40 ( input D1, B1, D0, B0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); +module SLICE_39 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly; - lut40053 \RowAd[3] ( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + lut40051 \RowAd[3] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40053 \RowAd[2] ( .A(GNDI), .B(B0), .C(GNDI), .D(D0), .Z(F0)); + lut40051 \RowAd[2] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre \RowA[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1909,6 +1931,77 @@ module SLICE_40 ( input D1, B1, D0, B0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); vmuxregsre \RowA[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + endspecify + +endmodule + +module lut40051 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_40 ( input D1, A1, C0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly; + + lut40052 \RowAd[5] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40053 \RowAd[4] ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \RowA[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre \RowA[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + endspecify + +endmodule + +module lut40052 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF55) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40053 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA0A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_41 ( input D1, B1, D0, B0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly; + + lut40050 \RowAd[7] ( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40050 \RowAd[6] ( .A(GNDI), .B(B0), .C(GNDI), .D(D0), .Z(F0)); + vmuxregsre \RowA[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre \RowA[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + specify (D1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); @@ -1924,55 +2017,17 @@ module SLICE_40 ( input D1, B1, D0, B0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); endmodule -module lut40053 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCC00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_41 ( input D1, A1, D0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly; - - lut40054 \RowAd[5] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40018 \RowAd[4] ( .A(A0), .B(GNDI), .C(GNDI), .D(D0), .Z(F0)); - vmuxregsre \RowA[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - vmuxregsre \RowA[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - endspecify - -endmodule - -module lut40054 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hAAFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module SLICE_42 ( input D1, C1, D0, C0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly; - lut40055 \RowAd[7] ( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + lut40008 \RowAd[9] ( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40055 \RowAd[6] ( .A(GNDI), .B(GNDI), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \RowA[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + lut40054 \RowAd[8] ( .A(GNDI), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \RowA[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - vmuxregsre \RowA[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + vmuxregsre \RowA[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify @@ -1990,55 +2045,17 @@ module SLICE_42 ( input D1, C1, D0, C0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); endmodule -module lut40055 ( input A, B, C, D, output Z ); +module lut40054 ( input A, B, C, D, output Z ); ROM16X1A #(16'hF000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_43 ( input B1, A1, C0, B0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly; - - lut40056 \RowAd[9] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40057 \RowAd[8] ( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \RowA[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - vmuxregsre \RowA[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - endspecify - -endmodule - -module lut40056 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40057 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hC0C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_44 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, +module SLICE_43 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; - lut40004 nRCAS_0_sqmuxa_1_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40058 \S_0_i_o2[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40055 nRCS_9_u_i_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40049 \S_0_i_o3[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre0009 \S[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); @@ -2063,17 +2080,17 @@ module SLICE_44 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, endmodule -module lut40058 ( input A, B, C, D, output Z ); +module lut40055 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h5040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_45 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output +module SLICE_44 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly; - lut40059 XOR8MEG_3_u_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40060 XOR8MEG_3_u_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40056 XOR8MEG_3_u_0_0_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40057 XOR8MEG_3_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre XOR8MEG( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -2098,22 +2115,22 @@ module SLICE_45 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output endmodule -module lut40059 ( input A, B, C, D, output Z ); +module lut40056 ( input A, B, C, D, output Z ); ROM16X1A #(16'hAAA8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40060 ( input A, B, C, D, output Z ); +module lut40057 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hF2FA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hDFCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_46 ( input D1, C1, B1, A1, D0, C0, A0, DI0, CLK, output F0, Q0, +module SLICE_45 ( input D1, C1, B1, A1, D0, C0, A0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly; - lut40061 CmdValid_RNITBH02( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40062 n8MEGEN_RNO( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + lut40058 CmdValid_RNIOOBE2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40059 n8MEGEN_RNO( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre n8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); @@ -2135,31 +2152,30 @@ module SLICE_46 ( input D1, C1, B1, A1, D0, C0, A0, DI0, CLK, output F0, Q0, endmodule -module lut40061 ( input A, B, C, D, output Z ); +module lut40058 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFF80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hF8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40062 ( input A, B, C, D, output Z ); +module lut40059 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0AFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_47 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output - F0, Q0, F1 ); - wire VCCI, DI0_dly, CLK_dly, LSR_dly; +module SLICE_46 ( input C1, B1, D0, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; - lut40063 nRowColSel_0_0_a3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40064 nRowColSel_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40060 nRowColSel_0_0_a2_1( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40061 nRowColSel_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0009 nRowColSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); @@ -2175,22 +2191,22 @@ module SLICE_47 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output endmodule -module lut40063 ( input A, B, C, D, output Z ); +module lut40060 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0C0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40064 ( input A, B, C, D, output Z ); +module lut40061 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hF6F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h88A8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_48 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, +module SLICE_47 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40065 \wb_adr_5_i_i[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40066 \wb_adr_5_i_i[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40062 \wb_adr_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40063 \wb_adr_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \wb_adr[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -2218,23 +2234,23 @@ module SLICE_48 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, endmodule -module lut40065 ( input A, B, C, D, output Z ); +module lut40062 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hEAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40066 ( input A, B, C, D, output Z ); +module lut40063 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_49 ( input D1, A1, C0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, +module SLICE_48 ( input C1, A1, C0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40018 \wb_adr_5[3] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1)); + lut40064 \wb_adr_5[3] ( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40067 \wb_adr_5[2] ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); + lut40064 \wb_adr_5[2] ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \wb_adr[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -2242,7 +2258,7 @@ module SLICE_49 ( input D1, A1, C0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify - (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); @@ -2257,18 +2273,18 @@ module SLICE_49 ( input D1, A1, C0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, endmodule -module lut40067 ( input A, B, C, D, output Z ); +module lut40064 ( input A, B, C, D, output Z ); ROM16X1A #(16'hA0A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_50 ( input D1, C1, A1, D0, C0, A0, DI1, DI0, CE, CLK, output F0, +module SLICE_49 ( input D1, C1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40068 \wb_adr_5_i_m2_0[5] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + lut40065 \wb_adr_5_i_m2[5] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40068 \wb_adr_5_i_m2_0[4] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + lut40066 \wb_adr_5_i_m2[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \wb_adr[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -2279,41 +2295,6 @@ module SLICE_50 ( input D1, C1, A1, D0, C0, A0, DI1, DI0, CE, CLK, output F0, (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40068 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hA0FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_51 ( input D1, B1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40052 \wb_adr_5[7] ( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40069 \wb_adr_5_i_m2_0[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \wb_adr[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \wb_adr[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); @@ -2328,17 +2309,62 @@ module SLICE_51 ( input D1, B1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, endmodule -module lut40069 ( input A, B, C, D, output Z ); +module lut40065 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h8F8F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hAF05) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, +module lut40066 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8D8D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_50 ( input D1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40067 \wb_adr_5[7] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40068 \wb_adr_5_i_m2[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \wb_adr[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \wb_adr[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40067 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAA00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40068 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hB1B1) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); wire VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; - lut40070 wb_cyc_stb_4_iv_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40071 wb_cyc_stb_4_iv_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40069 wb_cyc_stb_4_iv_0_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40070 wb_cyc_stb_4_iv_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0009 wb_cyc_stb( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -2364,22 +2390,22 @@ module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, endmodule -module lut40070 ( input A, B, C, D, output Z ); +module lut40069 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40071 ( input A, B, C, D, output Z ); +module lut40070 ( input A, B, C, D, output Z ); ROM16X1A #(16'hF8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_53 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, +module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40072 \wb_dati_5_1_iv_0_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40073 \wb_dati_5_0_iv_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40071 \wb_dati_5_1_iv_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40072 \wb_dati_5_0_iv_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \wb_dati[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -2407,26 +2433,26 @@ module SLICE_53 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, endmodule -module lut40072 ( input A, B, C, D, output Z ); +module lut40071 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFF10) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40073 ( input A, B, C, D, output Z ); +module lut40072 ( input A, B, C, D, output Z ); ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_54 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; +module SLICE_53 ( input D1, C1, B1, A1, D0, C0, A0, DI1, DI0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40074 \wb_dati_5_1_iv_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40075 \wb_dati_5_1_iv_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40073 \wb_dati_5_1_iv_0_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40074 \wb_dati_5_1_iv_0_0[2] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \wb_dati[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \wb_dati[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); @@ -2437,6 +2463,47 @@ module SLICE_54 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40073 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40074 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_54 ( input D1, C1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40075 \wb_dati_5_1_iv_0_0[5] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40076 \wb_dati_5_1_iv_0_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \wb_dati[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \wb_dati[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); @@ -2450,64 +2517,22 @@ module SLICE_54 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, endmodule -module lut40074 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFEFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40075 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_55 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40076 \wb_dati_5_1_iv_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40077 \wb_dati_5_1_iv_0[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \wb_dati[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \wb_dati[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - + ROM16X1A #(16'hFFA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40076 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hBBEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40077 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_56 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, +module SLICE_55 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40078 \wb_dati_5_1_iv_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40079 \wb_dati_5_1_iv_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40077 \wb_dati_5_1_iv_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40078 \wb_dati_5_1_iv_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \wb_dati[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -2535,22 +2560,22 @@ module SLICE_56 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, endmodule +module lut40077 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + module lut40078 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFB3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hCDCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40079 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_57 ( input D1, C1, B1, A1, D0, C0, A0, DI0, LSR, CLK, output F0, +module SLICE_56 ( input D1, C1, B1, A1, D0, C0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; - lut40080 wb_reqe_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40081 wb_reqe( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + lut40079 wb_reqe_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40080 wb_reqe( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre0009 wb_req( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); @@ -2575,33 +2600,32 @@ module SLICE_57 ( input D1, C1, B1, A1, D0, C0, A0, DI0, LSR, CLK, output F0, endmodule -module lut40080 ( input A, B, C, D, output Z ); +module lut40079 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h1555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h1333) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40081 ( input A, B, C, D, output Z ); +module lut40080 ( input A, B, C, D, output Z ); ROM16X1A #(16'hF0AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_58 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, - Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly; +module SLICE_57 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly; - lut40082 \FS_RNIHVJI[15] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40083 wb_rste( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40081 un1_InitReady_4_i_0_a2_i( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40082 wb_rste( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre wb_rst( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); @@ -2613,29 +2637,29 @@ module SLICE_58 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, endmodule +module lut40081 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7333) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + module lut40082 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hCACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40083 ( input A, B, C, D, output Z ); +module SLICE_58 ( input D1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output + F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; - ROM16X1A #(16'h30AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, - output F0, Q0, F1 ); - wire VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; - - lut40084 \wb_dati_5_1_iv_0_0[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40085 wb_we_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40083 un1_wb_rst14_2_0_o2( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40084 wb_we_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0009 wb_we( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); specify (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); @@ -2654,48 +2678,105 @@ module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, endmodule +module lut40083 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + module lut40084 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h080F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module wb_dati_5_1_iv_0_0_o2_5__SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, + A0, M0, output OFX0 ); + wire + \wb_dati_5_1_iv_0_0_o2[5]/SLICE_59/wb_dati_5_1_iv_0_0_o2[5]/SLICE_59_K1_H1 + , + \wb_dati_5_1_iv_0_0_o2[5]/SLICE_59/wb_dati_5_1_iv_0_0_o2[5]/GATE_H0 ; + + lut40085 \wb_dati_5_1_iv_0_0_o2[5]/SLICE_59_K1 ( .A(A1), .B(B1), .C(C1), + .D(D1), + .Z(\wb_dati_5_1_iv_0_0_o2[5]/SLICE_59/wb_dati_5_1_iv_0_0_o2[5]/SLICE_59_K1_H1 ) + ); + lut40086 \wb_dati_5_1_iv_0_0_o2[5]/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\wb_dati_5_1_iv_0_0_o2[5]/SLICE_59/wb_dati_5_1_iv_0_0_o2[5]/GATE_H0 )); + selmux2 \wb_dati_5_1_iv_0_0_o2[5]/SLICE_59_K0K1MUX ( + .D0(\wb_dati_5_1_iv_0_0_o2[5]/SLICE_59/wb_dati_5_1_iv_0_0_o2[5]/GATE_H0 ), + .D1(\wb_dati_5_1_iv_0_0_o2[5]/SLICE_59/wb_dati_5_1_iv_0_0_o2[5]/SLICE_59_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + endmodule module lut40085 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_60 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40086 \wb_dati_5_1_iv_0_0_a2[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40087 \wb_dati_5_1_iv_0_1[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - + ROM16X1A #(16'hCDCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40086 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hCECC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module selmux2 ( input D0, D1, SD, output Z ); + + MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z)); +endmodule + +module wb_adr_5_i_0_1_0__SLICE_60 ( input C1, B1, A1, D0, C0, B0, A0, M0, + output OFX0 ); + wire GNDI, \wb_adr_5_i_0_1[0]/SLICE_60/wb_adr_5_i_0_1[0]/SLICE_60_K1_H1 , + \wb_adr_5_i_0_1[0]/SLICE_60/wb_adr_5_i_0_1[0]/GATE_H0 ; + + lut40087 \wb_adr_5_i_0_1[0]/SLICE_60_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(\wb_adr_5_i_0_1[0]/SLICE_60/wb_adr_5_i_0_1[0]/SLICE_60_K1_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40088 \wb_adr_5_i_0_1[0]/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\wb_adr_5_i_0_1[0]/SLICE_60/wb_adr_5_i_0_1[0]/GATE_H0 )); + selmux2 \wb_adr_5_i_0_1[0]/SLICE_60_K0K1MUX ( + .D0(\wb_adr_5_i_0_1[0]/SLICE_60/wb_adr_5_i_0_1[0]/GATE_H0 ), + .D1(\wb_adr_5_i_0_1[0]/SLICE_60/wb_adr_5_i_0_1[0]/SLICE_60_K1_H1 ), + .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + endmodule module lut40087 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hCECC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40088 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0028) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_61 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40088 wb_cyc_stb_2_sqmuxa_i_o2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40089 \wb_adr_5_i_i_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40089 \wb_adr_5_i_0_2_RNO[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40007 \wb_adr_5_i_0_2_RNO_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -2710,19 +2791,14 @@ module SLICE_61 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); endmodule -module lut40088 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40089 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hC0EA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hF0F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40090 IS_0_sqmuxa_0_o2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40090 IS_0_sqmuxa_0_o2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40091 un1_nRCAS_6_sqmuxa_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify @@ -2745,13 +2821,13 @@ endmodule module lut40091 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h45EF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h31FD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40092 wb_we_0_0_0_a2_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40093 wb_we_0_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40092 un1_CmdEnable20_0_0_a2_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40093 un1_CmdEnable20_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -2768,18 +2844,18 @@ endmodule module lut40092 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40093 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hF0F2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hF111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_64 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40094 CmdEnable_0_sqmuxa_0_a2_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40095 un1_CmdEnable20_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40094 \FS_RNIHVJI[15] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40095 \wb_dati_5_1_iv_0_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -2796,18 +2872,21 @@ endmodule module lut40094 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFEFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40095 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hC0D5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hCE0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_65 ( input D1, C1, B1, A1, D0, B0, A0, output F0, F1 ); + wire GNDI; - lut40096 \wb_adr_5_i_i_0_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40097 \wb_adr_5_i_i_a2_0_1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40096 \wb_dati_5_1_iv_0_1_0[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40097 \wb_dati_5_1_iv_0_0_o2[4] ( .A(A0), .B(B0), .C(GNDI), .D(D0), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -2815,7 +2894,6 @@ module SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); endspecify @@ -2824,26 +2902,26 @@ endmodule module lut40096 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hF4F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h53F3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40097 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h4004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h1199) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_66 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_66 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40098 \wb_adr_5_i_i_a2_3_0[0] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + lut40098 \FS_RNIF2MA[9] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40099 \wb_adr_5_i_i_1_0_tz_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40099 \ufmefb/EFBInst_0_RNISI191 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); @@ -2853,21 +2931,19 @@ endmodule module lut40098 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0050) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40099 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hF0F4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_67 ( input D1, C1, B1, A1, D0, B0, A0, output F0, F1 ); +module SLICE_67 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40100 wb_cyc_stb_2_sqmuxa_i_o2_RNI167R( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40101 \ufmefb/EFBInst_0_RNI8K48 ( .A(A0), .B(B0), .C(GNDI), .D(D0), - .Z(F0)); + lut40100 \wb_adr_5_i_0_3[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40101 \FS_RNIJO0F[12] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -2875,7 +2951,7 @@ module SLICE_67 ( input D1, C1, B1, A1, D0, B0, A0, output F0, F1 ); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); endspecify @@ -2884,19 +2960,48 @@ endmodule module lut40100 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hF2F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40101 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0088) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 ); +module SLICE_68 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40102 nRWE_0io_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40103 \S_RNICVV51[0] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40102 nRWE_s_i_tz_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40103 \S_RNICVV51[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40102 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF4F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40103 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_69 ( input D1, C1, B1, A1, D0, C0, A0, output F0, F1 ); + wire GNDI; + + lut40104 nRCAS_0io_RNO_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40105 nRCAS_0io_RNO_2( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -2906,36 +3011,6 @@ module SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 ); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40102 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h31F5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40103 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_69 ( input D1, C1, B1, A1, D0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40104 \wb_dati_5_1_iv_0_1[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40105 \wb_dati_5_1_iv_0_1_RNO[7] ( .A(A0), .B(B0), .C(GNDI), .D(D0), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); endspecify @@ -2943,28 +3018,25 @@ endmodule module lut40104 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h5515) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h1500) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40105 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h99DD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h00AF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_70 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; +module SLICE_70 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40106 \wb_dati_5_1_iv_0_a2_3_2[7] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40107 \wb_dati_5_1_iv_0_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); + lut40106 wb_we_0_0_i_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40107 \FS_RNIOVGI[9] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); @@ -2974,23 +3046,22 @@ endmodule module lut40106 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hBBB3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40107 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_71 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_71 ( input C1, A1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40108 wb_we_0_0_0_a2( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + lut40108 \FS_RNIS637[9] ( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40109 wb_we_0_0_0_a2_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40109 \wb_adr_RNO_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); @@ -3003,25 +3074,27 @@ endmodule module lut40108 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0050) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h5F5F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40109 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h71F5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h44C4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_72 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_72 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; - lut40110 \wb_dati_5_1_iv_0_a2[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40111 \wb_dati_5_1_iv_0_a2_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40110 \wb_dati_5_1_iv_0_o2_0[4] ( .A(GNDI), .B(B1), .C(C1), .D(D1), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40111 \wb_dati_5_1_iv_0_o2_0_RNIMDJC1[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); @@ -3032,30 +3105,22 @@ endmodule module lut40110 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h3CCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40111 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h7880) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, - Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; +module SLICE_73 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; - lut40112 un1_CmdEnable20_0_a2_3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40113 CmdEnable17_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre CBR_fast( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); + lut40112 \wb_dati_5_1_iv_0_o2[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - vmuxregsre CBR( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(Q0)); + lut40113 \wb_dati_5_1_iv_0_1_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -3063,30 +3128,24 @@ module SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); endspecify endmodule module lut40112 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hF4F4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40113 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_74 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40114 CmdUFMData_1_sqmuxa_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40115 CmdUFMData_1_sqmuxa_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40114 \FS_RNIGOCT[12] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40115 \wb_dati_5_1_iv_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -3103,20 +3162,18 @@ endmodule module lut40114 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40115 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h5010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_75 ( input D1, C1, B1, A1, D0, B0, output F0, F1 ); - wire GNDI; +module SLICE_75 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40090 un1_ADWR_i_o2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40116 XOR8MEG18_0_a2_0( .A(GNDI), .B(B0), .C(GNDI), .D(D0), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); + lut40116 CBR_fast_RNIQ31K1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40117 nRWE_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -3124,35 +3181,85 @@ module SLICE_75 ( input D1, C1, B1, A1, D0, B0, output F0, F1 ); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule module lut40116 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h3300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_76 ( input C1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, M0_dly, CLK_dly; +module lut40117 ( input A, B, C, D, output Z ); - lut40027 CmdEnable_0_sqmuxa_0_a2_0( .A(A1), .B(GNDI), .C(C1), .D(GNDI), + ROM16X1A #(16'hCDCF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_76 ( input D1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40118 un1_CmdEnable20_0_0_a2_1_1( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40117 CmdEnable_0_sqmuxa_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre CASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(GNDI), .Q(Q0)); + lut40119 CmdEnable_s_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CBR_fast( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre CBR( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); specify - (C1 => F1) = (0:0:0,0:0:0); + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module lut40118 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40119 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_77 ( input D1, C1, B1, A1, C0, B0, M0, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, M0_dly, CLK_dly; + + lut40120 Cmdn8MEGEN_4_u_i_m2_i_a2_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40041 CmdUFMData_1_sqmuxa_0_a2( .A(GNDI), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); @@ -3160,20 +3267,19 @@ module SLICE_76 ( input C1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0, F1 ); endmodule -module lut40117 ( input A, B, C, D, output Z ); +module lut40120 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_77 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_78 ( input C1, B1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40118 \wb_adr_5_i_i_a2_6[0] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40121 nRCS_9_u_i_a2_0( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40119 \wb_adr_5_i_i_5[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40122 nRCS_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); @@ -3184,78 +3290,26 @@ module SLICE_77 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 ); endmodule -module lut40118 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0030) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40119 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_78 ( input D1, B1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40120 IS_0_sqmuxa_0_o2( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40121 RA10_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40120 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40121 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_79 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40103 \wb_adr_5_i_i_a2_11[0] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40122 \wb_dati_5_1_iv_0_2[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - + ROM16X1A #(16'h0303) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40122 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0057) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_80 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_79 ( input D1, B1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40123 \FS_RNIS637[9] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40123 IS_0_sqmuxa_0_o3( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40124 \wb_dati_5_1_iv_0_a2_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40124 RA10_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify + (D1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); @@ -3266,18 +3320,18 @@ endmodule module lut40123 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFFCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40124 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFEFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_80 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40125 nRCS_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40126 nRCS_9_u_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40125 un1_CmdEnable20_0_0_o2_11( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40126 un1_CmdEnable20_0_0_o2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -3294,24 +3348,23 @@ endmodule module lut40125 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h1115) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hBFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40126 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hCFCE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_82 ( input D1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; +module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40127 \wb_dati_5_1_iv_0_a2_2[6] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40128 \wb_dati_5_1_iv_0_a2_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40127 \wb_dati_5_1_iv_0_a2_2[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40128 \wb_dati_5_1_iv_0_0_1[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); @@ -3323,18 +3376,18 @@ endmodule module lut40127 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h00AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40128 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h8020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_83 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_82 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40129 \wb_dati_5_1_iv_0_a2_9[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40130 \wb_dati_5_1_iv_0_o2_0[5] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40129 \wb_dati_5_1_iv_0_a2_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40130 \wb_dati_5_1_iv_0_1[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -3351,24 +3404,25 @@ endmodule module lut40129 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h1200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40130 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFF20) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_84 ( input D1, C1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_83 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40131 \FS_RNICHC8[14] ( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + lut40131 un1_nRCAS_6_sqmuxa_i_o2( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40132 \wb_dati_5_1_iv_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40132 nRCS_9_u_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); @@ -3379,23 +3433,25 @@ endmodule module lut40131 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h000F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFFFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40132 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFF32) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_84 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; - lut40133 \wb_adr_5_i_i_a2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40134 \wb_adr_5_i_i_1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40133 \wb_dati_5_1_iv_0_a2_13[3] ( .A(A1), .B(GNDI), .C(C1), .D(D1), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40134 \wb_dati_5_1_iv_0_0_a2[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); @@ -3407,24 +3463,23 @@ endmodule module lut40133 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0201) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0005) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40134 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h2010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_86 ( input D1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; +module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40135 \wb_dati_5_1_iv_0_o2[7] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40136 \wb_adr_5_i_i_1_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40135 \wb_dati_5_1_iv_0_0_o2[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40136 \wb_dati_5_1_iv_0_1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); @@ -3436,72 +3491,54 @@ endmodule module lut40135 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFF55) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h2004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40136 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0A0B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFF80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_87 ( input D1, B1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_86 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 ); wire GNDI; - lut40137 wb_cyc_stb_2_sqmuxa_i_o2_0( .A(GNDI), .B(B1), .C(GNDI), .D(D1), - .Z(F1)); + lut40137 \wb_dati_5_1_iv_0_a2_7[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40138 \wb_dati_5_1_iv_0_0_0[3] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40079 wb_cyc_stb_2_sqmuxa_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule module lut40137 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFF33) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_88 ( input C1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40138 \wb_dati_5_1_iv_0_a2_7[1] ( .A(A1), .B(GNDI), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40094 \wb_adr_5_i_i_a2_7[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - + ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40138 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0505) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFCF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_89 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_87 ( input C1, B1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; - lut40139 un1_ADWR_i_o2_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40140 un1_ADWR_i_o2_10( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40121 \wb_dati_5_1_iv_0_a2_12[3] ( .A(GNDI), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40139 \wb_dati_5_1_iv_0_0_1[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); @@ -3512,24 +3549,49 @@ endmodule module lut40139 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h7FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hECCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_88 ( input D1, C1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40140 \FS_RNI7U6M[14] ( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40141 \wb_dati_5_1_iv_0_a2_5[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + endmodule module lut40140 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h000F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_90 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module lut40141 ( input A, B, C, D, output Z ); - lut40141 nRRAS_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40142 nRCS_9_u_i_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_89 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40142 wb_cyc_stb_2_sqmuxa_i_0_0_a2_0( .A(GNDI), .B(B1), .C(C1), .D(D1), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40143 wb_cyc_stb_2_sqmuxa_i_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); @@ -3538,44 +3600,20 @@ module SLICE_90 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); endmodule -module lut40141 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0C0D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40142 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h3200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_91 ( input D1, C1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40028 wb_cyc_stb_2_sqmuxa_i_a2_3_3( .A(GNDI), .B(GNDI), .C(C1), .D(D1), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40143 wb_cyc_stb_2_sqmuxa_i_a2_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - + ROM16X1A #(16'hCF00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40143 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFEFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_92 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_90 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40144 nRWE_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40145 nRWE_s_i_a2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40144 un1_CmdEnable20_0_0_o2_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40145 un1_CmdEnable20_0_0_o2_10( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -3592,20 +3630,50 @@ endmodule module lut40144 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFF4C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hBFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40145 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFDFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_93 ( input C1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_91 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40146 XOR8MEG_3_u_0_a2_1( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1)); + lut40146 \FS_RNI82PA[15] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40147 XOR8MEG_3_u_0_a2_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40147 \wb_adr_5_i_0_2[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40146 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFCFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40147 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hDDFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_92 ( input C1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40064 Cmdn8MEGEN_4_u_i_m2_i_a2_3( .A(A1), .B(GNDI), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40148 un1_CmdEnable20_0_0_a2_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -3618,68 +3686,15 @@ module SLICE_93 ( input C1, A1, D0, C0, B0, A0, output F0, F1 ); endmodule -module lut40146 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0A0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40147 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_94 ( input D1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40054 \wb_dati_5_1_iv_0_o2_0[6] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40148 \wb_dati_5_1_iv_0_a2_1_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - module lut40148 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h1001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_95 ( input D1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; +module SLICE_93 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40047 PHI2r3_RNIFT0I_0( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40149 CmdValid_fast_RNI3K0H1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40149 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8F0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_96 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40150 nRCAS_0io_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40151 nRCAS_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40149 wb_we_0_0_i_1_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40150 wb_we_0_0_i_a2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -3694,26 +3709,26 @@ module SLICE_96 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); endmodule +module lut40149 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5155) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + module lut40150 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h4101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h080A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40151 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0B0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_97 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_94 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40152 wb_cyc_stb_4_iv_0_RNO( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + lut40151 \wb_adr_5_i_3_0_a2_3[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40153 CmdValid_RNIS5A51( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40152 wb_rst_3_0_a2_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); @@ -3723,25 +3738,48 @@ module SLICE_97 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 ); endmodule +module lut40151 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + module lut40152 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h00A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_95 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40151 wb_cyc_stb_2_sqmuxa_i_a2_2_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40153 wb_cyc_stb_2_sqmuxa_i_a2_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + endmodule module lut40153 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h33B3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_98 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_96 ( input C1, B1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40154 \wb_adr_5_i_i_a2_6_0[0] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40154 XOR8MEG_3_u_0_0_o2_1( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40155 \wb_dati_5_1_iv_0_o2[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40116 XOR8MEG_3_u_0_0_a2_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); @@ -3754,123 +3792,159 @@ endmodule module lut40154 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFCFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_97 ( input D1, B1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40155 \wb_dati_5_1_iv_0_o2_0[7] ( .A(GNDI), .B(B1), .C(GNDI), .D(D1), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40156 \wb_dati_5_1_iv_0_a2_0_2[1] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + endmodule module lut40155 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h2A90) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_99 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40156 \FS_RNI1FVB[14] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40157 \wb_dati_5_1_iv_0_a2_2[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - + ROM16X1A #(16'hCCFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40156 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0030) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_98 ( input D1, C1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40157 \wb_dati_5_1_iv_0_a2_6[4] ( .A(GNDI), .B(GNDI), .C(C1), .D(D1), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40158 \wb_dati_5_0_iv_0_a2_1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + endmodule module lut40157 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_100 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40158 \wb_dati_5_0_iv_0_a2_0_0[0] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40159 \wb_dati_5_1_iv_0_0_o2[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - + ROM16X1A #(16'hF000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40158 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h6000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h4800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_99 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40159 InitReady3_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40160 InitReady3_0_a2_1_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + endmodule module lut40159 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h2004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_101 ( input D1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40160 \FS_RNI7O57[11] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40161 \wb_dati_5_1_iv_0_a2_1[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - + ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40160 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h55FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h7FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40161 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_102 ( input D1, A1, D0, A0, output F0, F1 ); +module SLICE_100 ( input D1, B1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40160 RDQML_0( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1)); + lut40161 PHI2r3_RNIFT0I_0( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40135 RDQMH_pad_RNO( .A(A0), .B(GNDI), .C(GNDI), .D(D0), .Z(F0)); + lut40162 CmdValid_fast_RNI3K0H1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule -module SLICE_103 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 ); +module lut40161 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h00CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40162 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8F0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_101 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40162 InitReady3_0_a2_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40163 \FS_RNIQV0F[16] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40163 nRCAS_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40164 nRCAS_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40163 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0515) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40164 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCDCD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_102 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40165 \wb_dati_5_1_iv_0_a2_0_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40166 \ufmefb/EFBInst_0_RNISGNB ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); @@ -3879,26 +3953,25 @@ module SLICE_103 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 ); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule -module lut40162 ( input A, B, C, D, output Z ); +module lut40165 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40163 ( input A, B, C, D, output Z ); +module lut40166 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_104 ( input D1, C1, B1, A1, D0, C0, output F0, F1 ); - wire GNDI; +module SLICE_103 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40164 CmdLEDEN_4_u_i_a2_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40165 XOR8MEG_3_u_0_o2_1( .A(GNDI), .B(GNDI), .C(C0), .D(D0), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); + lut40167 RCKEEN_8_u_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40168 nRWE_s_i_a2_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -3907,26 +3980,59 @@ module SLICE_104 ( input D1, C1, B1, A1, D0, C0, output F0, F1 ); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule -module lut40164 ( input A, B, C, D, output Z ); +module lut40167 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h4BCB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40165 ( input A, B, C, D, output Z ); +module lut40168 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_104 ( input D1, C1, B1, A1, D0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40169 \wb_dati_5_1_iv_0_0_a2_1[3] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40170 \wb_dati_5_1_iv_0_a2_5[7] ( .A(A0), .B(B0), .C(GNDI), .D(D0), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40169 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0084) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40170 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_105 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40166 nRCS_0io_RNO_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40171 \FS_RNI9Q57[12] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40167 RCKEEN_8_u_1_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40172 \wb_adr_5_i_3_0_a2[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (B1 => F1) = (0:0:0,0:0:0); @@ -3939,248 +4045,168 @@ module SLICE_105 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); endmodule -module lut40166 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40167 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4CBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_106 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40168 XOR8MEG18_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40169 un1_CmdEnable20_0_a2_1_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40168 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40169 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_107 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40170 \FS_RNITL2J[14] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40171 \wb_adr_5_i_i_a2_5[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40170 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40171 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_108 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40172 n8MEGEN_RNO_0( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40173 \wb_dati_5_1_iv_0_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - + ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40172 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h550F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hC050) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_106 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40173 RCKEEN_8_u_0_a2_2( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40174 LED_pad_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + endmodule module lut40173 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hF222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_109 ( input D1, C1, A1, D0, C0, A0, output F0, F1 ); - wire GNDI; - - lut40174 \un9_RA_i_m2[3] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40175 un1_ADWR_i_o2_3( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - + ROM16X1A #(16'h0A00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40174 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hAFA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_107 ( input C1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40175 \wb_adr_5_i_0_a2_6[0] ( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40176 \wb_adr_5_i_3_0_a2_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + endmodule module lut40175 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hF5FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_110 ( input D1, C1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40176 \un9_RA[8] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40177 \un9_RA_i_m2[9] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - + ROM16X1A #(16'h5050) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40176 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hF5A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h4440) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_108 ( input D1, C1, D0, C0, output F0, F1 ); + wire GNDI; + + lut40177 RDQML_0_0( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40178 RDQMH_pad_RNO( .A(GNDI), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + endspecify + endmodule module lut40177 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hCACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_111 ( input D1, B1, A1, D0, C0, B0, output F0, F1 ); - wire GNDI; - - lut40178 \un9_RA_i_m2[0] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40179 \un9_RA_i_m2[7] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - endspecify - + ROM16X1A #(16'h0FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40178 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hCCAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hF0FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40179 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCCF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_112 ( input D1, C1, A1, D0, C0, B0, output F0, F1 ); +module SLICE_109 ( input D1, C1, B1, A1, D0, B0, output F0, F1 ); wire GNDI; - lut40180 \un9_RA_i_m2[1] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + lut40179 un1_CmdEnable20_0_0_a2_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40180 XOR8MEG_3_u_0_0_a2_1( .A(GNDI), .B(B0), .C(GNDI), .D(D0), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40181 \un9_RA_i_m2[6] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); endspecify endmodule +module lut40179 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + module lut40180 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hAAF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h00CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40181 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFC0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_113 ( input D1, C1, A1, D0, B0, A0, output F0, F1 ); +module SLICE_110 ( input C1, A1, D0, C0, A0, output F0, F1 ); wire GNDI; - lut40176 \un9_RA_i_m2[2] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + lut40181 PHI2r3_RNIFT0I( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40182 \un9_RA_i_m2[5] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); + lut40182 wb_cyc_stb_4_iv_0_0_RNO( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule -module lut40182 ( input A, B, C, D, output Z ); +module lut40181 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hDD88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0A0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_114 ( input C1, D0, C0, A0, output F0, F1 ); +module lut40182 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0A00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_111 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40183 RA10_0io_RNO( .A(GNDI), .B(GNDI), .C(C1), .D(GNDI), .Z(F1)); + lut40183 n8MEGEN_RNO_0( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40184 nRWE_0io_RNO_1( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + lut40184 \wb_dati_5_1_iv_0_0_1[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); endspecify @@ -4188,24 +4214,241 @@ endmodule module lut40183 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0F0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h05AF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40184 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h000A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_115 ( input D1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_112 ( input C1, B1, A1, D0, C0, B0, output F0, F1 ); wire GNDI; - lut40018 \RBAd[0] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1)); + lut40185 \un9_RA_i_m2_i_m2[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40185 RA11d( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40186 un1_CmdEnable20_0_0_o2_3( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40185 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hE2E2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40186 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_113 ( input D1, C1, A1, D0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40187 \un9_RA[8] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40188 \un9_RA_i_m2_i_m2[0] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40187 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAFA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40188 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEE44) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_114 ( input D1, B1, A1, D0, C0, A0, output F0, F1 ); + wire GNDI; + + lut40189 \un9_RA_i_m2_i_m2[3] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40190 \un9_RA_i_m2_i_m2[1] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40189 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hBB88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40190 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFA50) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_115 ( input D1, C1, B1, D0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40191 \un9_RA_i_m2_i_m2[9] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40192 \un9_RA_i_m2_i_m2[4] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40191 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCCF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40192 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAACC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_116 ( input D1, C1, B1, D0, C0, B0, output F0, F1 ); + wire GNDI; + + lut40193 \un9_RA_i_m2_i_m2[7] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40191 \un9_RA_i_m2_i_m2[5] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40193 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCFC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_117 ( input D1, B1, D0, B0, output F0, F1 ); + wire GNDI; + + lut40194 nRowColSel_0_0_x2( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40195 RCKEEN_8_u_0_o3( .A(GNDI), .B(B0), .C(GNDI), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40194 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h33CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40195 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h33FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_118 ( input D1, A1, B0, A0, output F0, F1 ); + wire GNDI; + + lut40196 \wb_dati_5_1_iv_0_a2_7[4] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40197 \wb_dati_5_1_iv_0_a2_11[3] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), + .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40196 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5500) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40197 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_119 ( input D1, C1, B1, A1, D0, B0, output F0, F1 ); + wire GNDI; + + lut40198 CmdLEDEN_4_u_i_m2_i_a2_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40199 XOR8MEG_3_u_0_0_a2_2( .A(GNDI), .B(B0), .C(GNDI), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40198 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40199 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0033) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_120 ( input D1, B1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40050 \RBAd[1] ( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40200 RA11d( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); @@ -4214,58 +4457,61 @@ module SLICE_115 ( input D1, A1, D0, C0, B0, A0, output F0, F1 ); endmodule -module lut40185 ( input A, B, C, D, output Z ); +module lut40200 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h9A00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h8C40) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_116 ( input D1, B1, C0, B0, output F0, F1 ); +module SLICE_121 ( input D1, C1, D0, C0, A0, output F0, F1 ); wire GNDI; - lut40053 \wb_dati_5_1_iv_0_a2_1[1] ( .A(GNDI), .B(B1), .C(GNDI), .D(D1), + lut40157 wb_cyc_stb_4_iv_0_0_a2_0_0( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40186 PHI2r3_RNIFT0I( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40186 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h3030) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_117 ( input D1, C1, B1, C0, B0, output F0, F1 ); - wire GNDI; - - lut40187 RCKEEN_8_u_0_a2_1( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40188 nRCAS_0io_RNO_1( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40201 wb_cyc_stb_2_sqmuxa_i_a2_1( .A(A0), .B(GNDI), .C(C0), .D(D0), + .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule -module lut40187 ( input A, B, C, D, output Z ); +module lut40201 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h3000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0005) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40188 ( input A, B, C, D, output Z ); +module SLICE_122 ( input D1, B1, A1, D0, A0, output F0, F1 ); + wire GNDI; - ROM16X1A #(16'h3030) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + lut40202 \wb_adr_5_i_3_0_m2[1] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40203 IS_0_sqmuxa_0_o2_RNIDJQJ( .A(A0), .B(GNDI), .C(GNDI), .D(D0), + .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40202 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAA33) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40203 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0055) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RD_0_ ( output PADDI, input IOLDO, PADDT, inout RD0 ); @@ -4314,7 +4560,7 @@ endmodule module Dout_0_ ( input PADDO, output Dout0 ); - xo2iobuf0189 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0)); + xo2iobuf0204 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0)); specify (PADDO => Dout0) = (0:0:0,0:0:0); @@ -4322,14 +4568,14 @@ module Dout_0_ ( input PADDO, output Dout0 ); endmodule -module xo2iobuf0189 ( input I, output PAD ); +module xo2iobuf0204 ( input I, output PAD ); OB INST5( .I(I), .O(PAD)); endmodule module PHI2 ( output PADDI, input PHI2 ); - xo2iobuf0190 PHI2_pad( .Z(PADDI), .PAD(PHI2)); + xo2iobuf0205 PHI2_pad( .Z(PADDI), .PAD(PHI2)); specify (PHI2 => PADDI) = (0:0:0,0:0:0); @@ -4339,7 +4585,7 @@ module PHI2 ( output PADDI, input PHI2 ); endmodule -module xo2iobuf0190 ( output Z, input PAD ); +module xo2iobuf0205 ( output Z, input PAD ); IB INST1( .I(PAD), .O(Z)); endmodule @@ -4369,7 +4615,7 @@ endmodule module RDQML ( input PADDO, output RDQML ); - xo2iobuf0191 RDQML_pad( .I(PADDO), .PAD(RDQML)); + xo2iobuf0206 RDQML_pad( .I(PADDO), .PAD(RDQML)); specify (PADDO => RDQML) = (0:0:0,0:0:0); @@ -4377,14 +4623,14 @@ module RDQML ( input PADDO, output RDQML ); endmodule -module xo2iobuf0191 ( input I, output PAD ); +module xo2iobuf0206 ( input I, output PAD ); OB INST5( .I(I), .O(PAD)); endmodule module RDQMH ( input PADDO, output RDQMH ); - xo2iobuf0191 RDQMH_pad( .I(PADDO), .PAD(RDQMH)); + xo2iobuf0206 RDQMH_pad( .I(PADDO), .PAD(RDQMH)); specify (PADDO => RDQMH) = (0:0:0,0:0:0); @@ -4394,7 +4640,7 @@ endmodule module nRCAS ( input IOLDO, output nRCAS ); - xo2iobuf0191 nRCAS_pad( .I(IOLDO), .PAD(nRCAS)); + xo2iobuf0206 nRCAS_pad( .I(IOLDO), .PAD(nRCAS)); specify (IOLDO => nRCAS) = (0:0:0,0:0:0); @@ -4405,7 +4651,7 @@ endmodule module nRCAS_MGIOL ( output IOLDO, input OPOS, CLK ); wire VCCI, GNDI, OPOS_dly, CLK_dly; - mfflsre0192 nRCAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + mfflsre0207 nRCAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); @@ -4419,7 +4665,7 @@ module nRCAS_MGIOL ( output IOLDO, input OPOS, CLK ); endmodule -module mfflsre0192 ( input D0, SP, CK, LSR, output Q ); +module mfflsre0207 ( input D0, SP, CK, LSR, output Q ); FD1P3BX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q)); defparam INST01.GSR = "DISABLED"; @@ -4427,7 +4673,7 @@ endmodule module nRRAS ( input IOLDO, output nRRAS ); - xo2iobuf0191 nRRAS_pad( .I(IOLDO), .PAD(nRRAS)); + xo2iobuf0206 nRRAS_pad( .I(IOLDO), .PAD(nRRAS)); specify (IOLDO => nRRAS) = (0:0:0,0:0:0); @@ -4438,7 +4684,7 @@ endmodule module nRRAS_MGIOL ( output IOLDO, input OPOS, CLK ); wire VCCI, GNDI, OPOS_dly, CLK_dly; - mfflsre0192 nRRAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + mfflsre0207 nRRAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); @@ -4454,7 +4700,7 @@ endmodule module nRWE ( input IOLDO, output nRWE ); - xo2iobuf0191 nRWE_pad( .I(IOLDO), .PAD(nRWE)); + xo2iobuf0206 nRWE_pad( .I(IOLDO), .PAD(nRWE)); specify (IOLDO => nRWE) = (0:0:0,0:0:0); @@ -4465,7 +4711,7 @@ endmodule module nRWE_MGIOL ( output IOLDO, input OPOS, CLK ); wire VCCI, GNDI, OPOS_dly, CLK_dly; - mfflsre0192 nRWE_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + mfflsre0207 nRWE_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); @@ -4481,7 +4727,7 @@ endmodule module RCKE ( input PADDO, output RCKE ); - xo2iobuf0191 RCKE_pad( .I(PADDO), .PAD(RCKE)); + xo2iobuf0206 RCKE_pad( .I(PADDO), .PAD(RCKE)); specify (PADDO => RCKE) = (0:0:0,0:0:0); @@ -4491,7 +4737,7 @@ endmodule module RCLKout ( input IOLDO, output RCLKout ); - xo2iobuf0189 RCLKout_pad( .I(IOLDO), .PAD(RCLKout)); + xo2iobuf0208 RCLKout_pad( .I(IOLDO), .PAD(RCLKout)); specify (IOLDO => RCLKout) = (0:0:0,0:0:0); @@ -4499,10 +4745,15 @@ module RCLKout ( input IOLDO, output RCLKout ); endmodule +module xo2iobuf0208 ( input I, output PAD ); + + OB INST5( .I(I), .O(PAD)); +endmodule + module RCLKout_MGIOL ( output IOLDO, input ONEG, OPOS, CLK ); wire GNDI, ONEG_dly, CLK_dly, OPOS_dly; - xo2oddr rck( .D0(OPOS_dly), .D1(ONEG_dly), .SCLK(CLK_dly), .RST(GNDI), + xo2oddr rclk_oddr( .D0(OPOS_dly), .D1(ONEG_dly), .SCLK(CLK_dly), .RST(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); @@ -4524,7 +4775,7 @@ endmodule module RCLK ( output PADDI, input RCLK ); - xo2iobuf0190 RCLK_pad( .Z(PADDI), .PAD(RCLK)); + xo2iobuf0205 RCLK_pad( .Z(PADDI), .PAD(RCLK)); specify (RCLK => PADDI) = (0:0:0,0:0:0); @@ -4536,7 +4787,7 @@ endmodule module nRCS ( input IOLDO, output nRCS ); - xo2iobuf0191 nRCS_pad( .I(IOLDO), .PAD(nRCS)); + xo2iobuf0206 nRCS_pad( .I(IOLDO), .PAD(nRCS)); specify (IOLDO => nRCS) = (0:0:0,0:0:0); @@ -4547,7 +4798,7 @@ endmodule module nRCS_MGIOL ( output IOLDO, input OPOS, CLK ); wire VCCI, GNDI, OPOS_dly, CLK_dly; - mfflsre0192 nRCS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + mfflsre0207 nRCS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); @@ -4787,7 +5038,7 @@ endmodule module RA_11_ ( input IOLDO, output RA11 ); - xo2iobuf0191 \RA_pad[11] ( .I(IOLDO), .PAD(RA11)); + xo2iobuf0206 \RA_pad[11] ( .I(IOLDO), .PAD(RA11)); specify (IOLDO => RA11) = (0:0:0,0:0:0); @@ -4814,7 +5065,7 @@ endmodule module RA_10_ ( input IOLDO, output RA10 ); - xo2iobuf0191 \RA_pad[10] ( .I(IOLDO), .PAD(RA10)); + xo2iobuf0206 \RA_pad[10] ( .I(IOLDO), .PAD(RA10)); specify (IOLDO => RA10) = (0:0:0,0:0:0); @@ -4825,7 +5076,7 @@ endmodule module RA_10__MGIOL ( output IOLDO, input OPOS, LSR, CLK ); wire VCCI, OPOS_dly, CLK_dly, LSR_dly; - mfflsre0193 RA10_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), + mfflsre0209 RA10_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -4839,7 +5090,7 @@ module RA_10__MGIOL ( output IOLDO, input OPOS, LSR, CLK ); endmodule -module mfflsre0193 ( input D0, SP, CK, LSR, output Q ); +module mfflsre0209 ( input D0, SP, CK, LSR, output Q ); FD1P3JX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q)); defparam INST01.GSR = "DISABLED"; @@ -4847,7 +5098,7 @@ endmodule module RA_9_ ( input PADDO, output RA9 ); - xo2iobuf0191 \RA_pad[9] ( .I(PADDO), .PAD(RA9)); + xo2iobuf0206 \RA_pad[9] ( .I(PADDO), .PAD(RA9)); specify (PADDO => RA9) = (0:0:0,0:0:0); @@ -4857,7 +5108,7 @@ endmodule module RA_8_ ( input PADDO, output RA8 ); - xo2iobuf0191 \RA_pad[8] ( .I(PADDO), .PAD(RA8)); + xo2iobuf0206 \RA_pad[8] ( .I(PADDO), .PAD(RA8)); specify (PADDO => RA8) = (0:0:0,0:0:0); @@ -4867,7 +5118,7 @@ endmodule module RA_7_ ( input PADDO, output RA7 ); - xo2iobuf0191 \RA_pad[7] ( .I(PADDO), .PAD(RA7)); + xo2iobuf0206 \RA_pad[7] ( .I(PADDO), .PAD(RA7)); specify (PADDO => RA7) = (0:0:0,0:0:0); @@ -4877,7 +5128,7 @@ endmodule module RA_6_ ( input PADDO, output RA6 ); - xo2iobuf0191 \RA_pad[6] ( .I(PADDO), .PAD(RA6)); + xo2iobuf0206 \RA_pad[6] ( .I(PADDO), .PAD(RA6)); specify (PADDO => RA6) = (0:0:0,0:0:0); @@ -4887,7 +5138,7 @@ endmodule module RA_5_ ( input PADDO, output RA5 ); - xo2iobuf0191 \RA_pad[5] ( .I(PADDO), .PAD(RA5)); + xo2iobuf0206 \RA_pad[5] ( .I(PADDO), .PAD(RA5)); specify (PADDO => RA5) = (0:0:0,0:0:0); @@ -4897,7 +5148,7 @@ endmodule module RA_4_ ( input PADDO, output RA4 ); - xo2iobuf0191 \RA_pad[4] ( .I(PADDO), .PAD(RA4)); + xo2iobuf0206 \RA_pad[4] ( .I(PADDO), .PAD(RA4)); specify (PADDO => RA4) = (0:0:0,0:0:0); @@ -4907,7 +5158,7 @@ endmodule module RA_3_ ( input PADDO, output RA3 ); - xo2iobuf0191 \RA_pad[3] ( .I(PADDO), .PAD(RA3)); + xo2iobuf0206 \RA_pad[3] ( .I(PADDO), .PAD(RA3)); specify (PADDO => RA3) = (0:0:0,0:0:0); @@ -4917,7 +5168,7 @@ endmodule module RA_2_ ( input PADDO, output RA2 ); - xo2iobuf0191 \RA_pad[2] ( .I(PADDO), .PAD(RA2)); + xo2iobuf0206 \RA_pad[2] ( .I(PADDO), .PAD(RA2)); specify (PADDO => RA2) = (0:0:0,0:0:0); @@ -4927,7 +5178,7 @@ endmodule module RA_1_ ( input PADDO, output RA1 ); - xo2iobuf0191 \RA_pad[1] ( .I(PADDO), .PAD(RA1)); + xo2iobuf0206 \RA_pad[1] ( .I(PADDO), .PAD(RA1)); specify (PADDO => RA1) = (0:0:0,0:0:0); @@ -4937,7 +5188,7 @@ endmodule module RA_0_ ( input PADDO, output RA0 ); - xo2iobuf0191 \RA_pad[0] ( .I(PADDO), .PAD(RA0)); + xo2iobuf0206 \RA_pad[0] ( .I(PADDO), .PAD(RA0)); specify (PADDO => RA0) = (0:0:0,0:0:0); @@ -4947,7 +5198,7 @@ endmodule module RBA_1_ ( input IOLDO, output RBA1 ); - xo2iobuf0191 \RBA_pad[1] ( .I(IOLDO), .PAD(RBA1)); + xo2iobuf0206 \RBA_pad[1] ( .I(IOLDO), .PAD(RBA1)); specify (IOLDO => RBA1) = (0:0:0,0:0:0); @@ -4975,7 +5226,7 @@ endmodule module RBA_0_ ( input IOLDO, output RBA0 ); - xo2iobuf0191 \RBA_pad[0] ( .I(IOLDO), .PAD(RBA0)); + xo2iobuf0206 \RBA_pad[0] ( .I(IOLDO), .PAD(RBA0)); specify (IOLDO => RBA0) = (0:0:0,0:0:0); @@ -5003,7 +5254,7 @@ endmodule module LED ( input PADDO, output LED ); - xo2iobuf0194 LED_pad( .I(PADDO), .PAD(LED)); + xo2iobuf0210 LED_pad( .I(PADDO), .PAD(LED)); specify (PADDO => LED) = (0:0:0,0:0:0); @@ -5011,14 +5262,14 @@ module LED ( input PADDO, output LED ); endmodule -module xo2iobuf0194 ( input I, output PAD ); +module xo2iobuf0210 ( input I, output PAD ); OB INST5( .I(I), .O(PAD)); endmodule module nFWE ( output PADDI, input nFWE ); - xo2iobuf0190 nFWE_pad( .Z(PADDI), .PAD(nFWE)); + xo2iobuf0205 nFWE_pad( .Z(PADDI), .PAD(nFWE)); specify (nFWE => PADDI) = (0:0:0,0:0:0); @@ -5030,7 +5281,7 @@ endmodule module nCRAS ( output PADDI, input nCRAS ); - xo2iobuf0190 nCRAS_pad( .Z(PADDI), .PAD(nCRAS)); + xo2iobuf0205 nCRAS_pad( .Z(PADDI), .PAD(nCRAS)); specify (nCRAS => PADDI) = (0:0:0,0:0:0); @@ -5042,7 +5293,7 @@ endmodule module nCCAS ( output PADDI, input nCCAS ); - xo2iobuf0190 nCCAS_pad( .Z(PADDI), .PAD(nCCAS)); + xo2iobuf0205 nCCAS_pad( .Z(PADDI), .PAD(nCCAS)); specify (nCCAS => PADDI) = (0:0:0,0:0:0); @@ -5054,7 +5305,7 @@ endmodule module Dout_7_ ( input PADDO, output Dout7 ); - xo2iobuf0189 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7)); + xo2iobuf0204 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7)); specify (PADDO => Dout7) = (0:0:0,0:0:0); @@ -5064,7 +5315,7 @@ endmodule module Dout_6_ ( input PADDO, output Dout6 ); - xo2iobuf0189 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6)); + xo2iobuf0204 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6)); specify (PADDO => Dout6) = (0:0:0,0:0:0); @@ -5074,7 +5325,7 @@ endmodule module Dout_5_ ( input PADDO, output Dout5 ); - xo2iobuf0189 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5)); + xo2iobuf0204 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5)); specify (PADDO => Dout5) = (0:0:0,0:0:0); @@ -5084,7 +5335,7 @@ endmodule module Dout_4_ ( input PADDO, output Dout4 ); - xo2iobuf0189 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4)); + xo2iobuf0204 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4)); specify (PADDO => Dout4) = (0:0:0,0:0:0); @@ -5094,7 +5345,7 @@ endmodule module Dout_3_ ( input PADDO, output Dout3 ); - xo2iobuf0189 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3)); + xo2iobuf0204 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3)); specify (PADDO => Dout3) = (0:0:0,0:0:0); @@ -5104,7 +5355,7 @@ endmodule module Dout_2_ ( input PADDO, output Dout2 ); - xo2iobuf0189 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2)); + xo2iobuf0204 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2)); specify (PADDO => Dout2) = (0:0:0,0:0:0); @@ -5114,7 +5365,7 @@ endmodule module Dout_1_ ( input PADDO, output Dout1 ); - xo2iobuf0189 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1)); + xo2iobuf0204 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1)); specify (PADDO => Dout1) = (0:0:0,0:0:0); @@ -5124,7 +5375,7 @@ endmodule module Din_7_ ( output PADDI, input Din7 ); - xo2iobuf0190 \Din_pad[7] ( .Z(PADDI), .PAD(Din7)); + xo2iobuf0205 \Din_pad[7] ( .Z(PADDI), .PAD(Din7)); specify (Din7 => PADDI) = (0:0:0,0:0:0); @@ -5153,7 +5404,7 @@ endmodule module Din_6_ ( output PADDI, input Din6 ); - xo2iobuf0190 \Din_pad[6] ( .Z(PADDI), .PAD(Din6)); + xo2iobuf0205 \Din_pad[6] ( .Z(PADDI), .PAD(Din6)); specify (Din6 => PADDI) = (0:0:0,0:0:0); @@ -5182,7 +5433,7 @@ endmodule module Din_5_ ( output PADDI, input Din5 ); - xo2iobuf0190 \Din_pad[5] ( .Z(PADDI), .PAD(Din5)); + xo2iobuf0205 \Din_pad[5] ( .Z(PADDI), .PAD(Din5)); specify (Din5 => PADDI) = (0:0:0,0:0:0); @@ -5211,7 +5462,7 @@ endmodule module Din_4_ ( output PADDI, input Din4 ); - xo2iobuf0190 \Din_pad[4] ( .Z(PADDI), .PAD(Din4)); + xo2iobuf0205 \Din_pad[4] ( .Z(PADDI), .PAD(Din4)); specify (Din4 => PADDI) = (0:0:0,0:0:0); @@ -5240,7 +5491,7 @@ endmodule module Din_3_ ( output PADDI, input Din3 ); - xo2iobuf0190 \Din_pad[3] ( .Z(PADDI), .PAD(Din3)); + xo2iobuf0205 \Din_pad[3] ( .Z(PADDI), .PAD(Din3)); specify (Din3 => PADDI) = (0:0:0,0:0:0); @@ -5269,7 +5520,7 @@ endmodule module Din_2_ ( output PADDI, input Din2 ); - xo2iobuf0190 \Din_pad[2] ( .Z(PADDI), .PAD(Din2)); + xo2iobuf0205 \Din_pad[2] ( .Z(PADDI), .PAD(Din2)); specify (Din2 => PADDI) = (0:0:0,0:0:0); @@ -5298,7 +5549,7 @@ endmodule module Din_1_ ( output PADDI, input Din1 ); - xo2iobuf0190 \Din_pad[1] ( .Z(PADDI), .PAD(Din1)); + xo2iobuf0205 \Din_pad[1] ( .Z(PADDI), .PAD(Din1)); specify (Din1 => PADDI) = (0:0:0,0:0:0); @@ -5327,7 +5578,7 @@ endmodule module Din_0_ ( output PADDI, input Din0 ); - xo2iobuf0190 \Din_pad[0] ( .Z(PADDI), .PAD(Din0)); + xo2iobuf0205 \Din_pad[0] ( .Z(PADDI), .PAD(Din0)); specify (Din0 => PADDI) = (0:0:0,0:0:0); @@ -5356,7 +5607,7 @@ endmodule module CROW_1_ ( output PADDI, input CROW1 ); - xo2iobuf0190 \CROW_pad[1] ( .Z(PADDI), .PAD(CROW1)); + xo2iobuf0205 \CROW_pad[1] ( .Z(PADDI), .PAD(CROW1)); specify (CROW1 => PADDI) = (0:0:0,0:0:0); @@ -5368,7 +5619,7 @@ endmodule module CROW_0_ ( output PADDI, input CROW0 ); - xo2iobuf0190 \CROW_pad[0] ( .Z(PADDI), .PAD(CROW0)); + xo2iobuf0205 \CROW_pad[0] ( .Z(PADDI), .PAD(CROW0)); specify (CROW0 => PADDI) = (0:0:0,0:0:0); @@ -5380,7 +5631,7 @@ endmodule module MAin_9_ ( output PADDI, input MAin9 ); - xo2iobuf0190 \MAin_pad[9] ( .Z(PADDI), .PAD(MAin9)); + xo2iobuf0205 \MAin_pad[9] ( .Z(PADDI), .PAD(MAin9)); specify (MAin9 => PADDI) = (0:0:0,0:0:0); @@ -5392,7 +5643,7 @@ endmodule module MAin_8_ ( output PADDI, input MAin8 ); - xo2iobuf0190 \MAin_pad[8] ( .Z(PADDI), .PAD(MAin8)); + xo2iobuf0205 \MAin_pad[8] ( .Z(PADDI), .PAD(MAin8)); specify (MAin8 => PADDI) = (0:0:0,0:0:0); @@ -5404,7 +5655,7 @@ endmodule module MAin_7_ ( output PADDI, input MAin7 ); - xo2iobuf0190 \MAin_pad[7] ( .Z(PADDI), .PAD(MAin7)); + xo2iobuf0205 \MAin_pad[7] ( .Z(PADDI), .PAD(MAin7)); specify (MAin7 => PADDI) = (0:0:0,0:0:0); @@ -5416,7 +5667,7 @@ endmodule module MAin_6_ ( output PADDI, input MAin6 ); - xo2iobuf0190 \MAin_pad[6] ( .Z(PADDI), .PAD(MAin6)); + xo2iobuf0205 \MAin_pad[6] ( .Z(PADDI), .PAD(MAin6)); specify (MAin6 => PADDI) = (0:0:0,0:0:0); @@ -5428,7 +5679,7 @@ endmodule module MAin_5_ ( output PADDI, input MAin5 ); - xo2iobuf0190 \MAin_pad[5] ( .Z(PADDI), .PAD(MAin5)); + xo2iobuf0205 \MAin_pad[5] ( .Z(PADDI), .PAD(MAin5)); specify (MAin5 => PADDI) = (0:0:0,0:0:0); @@ -5440,7 +5691,7 @@ endmodule module MAin_4_ ( output PADDI, input MAin4 ); - xo2iobuf0190 \MAin_pad[4] ( .Z(PADDI), .PAD(MAin4)); + xo2iobuf0205 \MAin_pad[4] ( .Z(PADDI), .PAD(MAin4)); specify (MAin4 => PADDI) = (0:0:0,0:0:0); @@ -5452,7 +5703,7 @@ endmodule module MAin_3_ ( output PADDI, input MAin3 ); - xo2iobuf0190 \MAin_pad[3] ( .Z(PADDI), .PAD(MAin3)); + xo2iobuf0205 \MAin_pad[3] ( .Z(PADDI), .PAD(MAin3)); specify (MAin3 => PADDI) = (0:0:0,0:0:0); @@ -5464,7 +5715,7 @@ endmodule module MAin_2_ ( output PADDI, input MAin2 ); - xo2iobuf0190 \MAin_pad[2] ( .Z(PADDI), .PAD(MAin2)); + xo2iobuf0205 \MAin_pad[2] ( .Z(PADDI), .PAD(MAin2)); specify (MAin2 => PADDI) = (0:0:0,0:0:0); @@ -5476,7 +5727,7 @@ endmodule module MAin_1_ ( output PADDI, input MAin1 ); - xo2iobuf0190 \MAin_pad[1] ( .Z(PADDI), .PAD(MAin1)); + xo2iobuf0205 \MAin_pad[1] ( .Z(PADDI), .PAD(MAin1)); specify (MAin1 => PADDI) = (0:0:0,0:0:0); @@ -5488,7 +5739,7 @@ endmodule module MAin_0_ ( output PADDI, input MAin0 ); - xo2iobuf0190 \MAin_pad[0] ( .Z(PADDI), .PAD(MAin0)); + xo2iobuf0205 \MAin_pad[0] ( .Z(PADDI), .PAD(MAin0)); specify (MAin0 => PADDI) = (0:0:0,0:0:0); diff --git a/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html b/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html index 68f0f05..5f1dd56 100644 --- a/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html +++ b/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html @@ -2,17 +2,15 @@ Starting: parse design source files (VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v' (VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v' +WARNING - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v(23,47-23,52) (VERI-1875) identifier 'Ready' is used before its declaration (VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/REFB.v' INFO - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v(1,8-1,14) (VERI-1018) compiling module 'RAM2GS' -INFO - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v(1,1-621,10) (VERI-9000) elaborating module 'RAM2GS' +INFO - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v(1,1-618,10) (VERI-9000) elaborating module 'RAM2GS' INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1601,1-1606,10) (VERI-9000) elaborating module 'ODDRXE_uniq_1' INFO - //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/REFB.v(8,1-113,10) (VERI-9000) elaborating module 'REFB_uniq_1' INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_1' INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_1' INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1800,1-1872,10) (VERI-9000) elaborating module 'EFB_uniq_1' -WARNING - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v(46,7-46,8) (VERI-1330) actual bit length 32 differs from formal bit length 1 for port 'D0' -WARNING - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v(46,15-46,16) (VERI-1330) actual bit length 32 differs from formal bit length 1 for port 'D1' -WARNING - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v(47,8-47,9) (VERI-1330) actual bit length 32 differs from formal bit length 1 for port 'RST' -Done: design load finished with (0) errors, and (3) warnings +Done: design load finished with (0) errors, and (1) warnings \ No newline at end of file diff --git a/CPLD/LCMXO2-1200HC/impl1/ram2gs_lcmxo2_1200hc_impl1.ior b/CPLD/LCMXO2-1200HC/impl1/ram2gs_lcmxo2_1200hc_impl1.ior index 0ba1951..74f029a 100644 --- a/CPLD/LCMXO2-1200HC/impl1/ram2gs_lcmxo2_1200hc_impl1.ior +++ b/CPLD/LCMXO2-1200HC/impl1/ram2gs_lcmxo2_1200hc_impl1.ior @@ -29,7 +29,7 @@ Performance Hardware Data Status: Final Version 34.4. // Package: TQFP100 // ncd File: ram2gs_lcmxo2_1200hc_impl1.ncd // Version: Diamond (64-bit) 3.12.1.454 -// Written on Thu Oct 19 23:51:14 2023 +// Written on Sat Nov 18 02:06:17 2023 // M: Minimum Performance Grade // iotiming RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml @@ -41,97 +41,95 @@ Worst Case Results across Performance Grades (M, 6, 5, 4): Port Clock Edge Setup Performance_Grade Hold Performance_Grade ---------------------------------------------------------------------- -CROW[0] nCRAS F 1.569 4 0.268 6 -CROW[1] nCRAS F 1.013 4 0.820 4 -Din[0] PHI2 F 5.478 4 4.293 4 -Din[0] nCCAS F 2.010 4 -0.119 M -Din[1] PHI2 F 4.088 4 4.173 4 -Din[1] nCCAS F 0.601 4 0.796 4 -Din[2] PHI2 F 4.967 4 4.173 4 -Din[2] nCCAS F 0.811 4 0.583 4 -Din[3] PHI2 F 3.810 4 4.173 4 -Din[3] nCCAS F 1.136 4 0.322 4 -Din[4] PHI2 F 4.400 4 4.173 4 -Din[4] nCCAS F 0.762 4 0.590 4 -Din[5] PHI2 F 5.595 4 4.173 4 -Din[5] nCCAS F 0.779 4 0.576 4 -Din[6] PHI2 F 5.120 4 4.293 4 -Din[6] nCCAS F 2.036 4 -0.117 M -Din[7] PHI2 F 5.630 4 4.293 4 -Din[7] nCCAS F 2.301 4 -0.192 M -MAin[0] PHI2 F 4.196 4 1.086 4 -MAin[0] nCRAS F 0.152 6 1.567 4 -MAin[1] PHI2 F 3.875 4 1.164 4 -MAin[1] nCRAS F -0.177 M 2.102 4 -MAin[2] PHI2 F 8.381 4 -0.693 M -MAin[2] nCRAS F -0.315 M 2.358 4 -MAin[3] PHI2 F 7.199 4 -0.405 M -MAin[3] nCRAS F -0.173 M 1.962 4 -MAin[4] PHI2 F 8.710 4 -0.769 M -MAin[4] nCRAS F 0.292 4 1.419 4 -MAin[5] PHI2 F 8.562 4 -0.730 M -MAin[5] nCRAS F -0.055 M 1.752 4 -MAin[6] PHI2 F 7.862 4 -0.604 M -MAin[6] nCRAS F -0.126 M 1.965 4 -MAin[7] PHI2 F 8.829 4 -0.836 M -MAin[7] nCRAS F -0.122 M 1.960 4 -MAin[8] nCRAS F -0.288 M 2.424 4 -MAin[9] nCRAS F -0.212 M 2.196 4 +CROW[0] nCRAS F 3.288 4 -0.390 M +CROW[1] nCRAS F 2.823 4 -0.285 M +Din[0] PHI2 F 6.398 4 4.293 4 +Din[0] nCCAS F 1.411 4 -0.004 M +Din[1] PHI2 F 3.916 4 4.173 4 +Din[1] nCCAS F 1.877 4 -0.123 M +Din[2] PHI2 F 6.180 4 4.173 4 +Din[2] nCCAS F 1.548 4 -0.062 M +Din[3] PHI2 F 5.536 4 4.173 4 +Din[3] nCCAS F 0.467 4 0.734 4 +Din[4] PHI2 F 3.611 4 4.173 4 +Din[4] nCCAS F 1.533 4 -0.043 M +Din[5] PHI2 F 5.673 4 4.173 4 +Din[5] nCCAS F 1.663 4 -0.072 M +Din[6] PHI2 F 5.355 4 4.293 4 +Din[6] nCCAS F 2.807 4 -0.352 M +Din[7] PHI2 F 5.296 4 4.293 4 +Din[7] nCCAS F 1.914 4 -0.136 M +MAin[0] PHI2 F 4.091 4 1.414 4 +MAin[0] nCRAS F 1.207 4 0.347 4 +MAin[1] PHI2 F 3.273 4 1.759 4 +MAin[1] nCRAS F 1.077 4 0.460 4 +MAin[2] PHI2 F 8.126 4 -0.351 M +MAin[2] nCRAS F 0.671 4 0.850 4 +MAin[3] PHI2 F 8.831 4 -0.579 M +MAin[3] nCRAS F 1.100 4 0.463 4 +MAin[4] PHI2 F 8.415 4 -0.447 M +MAin[4] nCRAS F 1.390 4 0.207 4 +MAin[5] PHI2 F 9.742 4 -0.803 M +MAin[5] nCRAS F 1.269 4 0.218 4 +MAin[6] PHI2 F 7.970 4 -0.325 M +MAin[6] nCRAS F 1.165 4 0.337 4 +MAin[7] PHI2 F 8.481 4 -0.438 M +MAin[7] nCRAS F 0.761 4 0.673 4 +MAin[8] nCRAS F 1.261 4 0.223 4 +MAin[9] nCRAS F 0.756 4 0.667 4 PHI2 RCLK R -0.133 M 2.360 4 -nCCAS RCLK R 3.627 4 -0.577 M -nCCAS nCRAS F 3.154 4 -0.145 M -nCRAS RCLK R 1.461 4 -0.017 M -nFWE PHI2 F 6.933 4 -0.318 M -nFWE nCRAS F 0.403 4 1.860 4 +nCCAS RCLK R 4.128 4 -0.675 M +nCCAS nCRAS F 4.568 4 -0.666 M +nCRAS RCLK R 3.070 4 -0.412 M +nFWE PHI2 F 8.979 4 -0.603 M +nFWE nCRAS F 1.467 4 0.144 4 // Clock to Output Delay Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade ------------------------------------------------------------------------ -LED RCLK R 10.948 4 3.270 M -LED nCRAS F 12.507 4 3.690 M -RA[0] RCLK R 13.208 4 4.000 M -RA[0] nCRAS F 13.040 4 3.935 M +LED RCLK R 11.034 4 3.119 M +LED nCRAS F 11.531 4 3.339 M +RA[0] RCLK R 11.682 4 3.586 M +RA[0] nCRAS F 11.704 4 3.483 M RA[10] RCLK R 7.888 4 2.711 M RA[11] PHI2 R 9.755 4 3.200 M -RA[1] RCLK R 13.332 4 4.024 M -RA[1] nCRAS F 12.944 4 3.885 M -RA[2] RCLK R 13.624 4 4.099 M -RA[2] nCRAS F 13.220 4 3.993 M -RA[3] RCLK R 13.506 4 4.055 M -RA[3] nCRAS F 13.322 4 4.022 M -RA[4] RCLK R 12.512 4 3.834 M -RA[4] nCRAS F 14.534 4 4.331 M -RA[5] RCLK R 13.530 4 4.069 M -RA[5] nCRAS F 13.126 4 3.963 M -RA[6] RCLK R 14.238 4 4.245 M -RA[6] nCRAS F 13.589 4 4.077 M -RA[7] RCLK R 13.759 4 4.129 M -RA[7] nCRAS F 13.371 4 3.990 M -RA[8] RCLK R 11.858 4 3.632 M -RA[8] nCRAS F 13.338 4 4.026 M -RA[9] RCLK R 11.007 4 3.423 M -RA[9] nCRAS F 12.651 4 3.856 M -RBA[0] nCRAS F 10.201 4 3.325 M -RBA[1] nCRAS F 10.201 4 3.325 M -RCKE RCLK R 9.754 4 3.167 M -RCLKout RCLK R 7.971 4 2.504 M -RDQMH RCLK R 11.153 4 3.458 M -RDQML RCLK R 11.133 4 3.466 M -RD[0] nCCAS F 9.354 4 3.132 M -RD[1] nCCAS F 9.354 4 3.132 M -RD[2] nCCAS F 9.354 4 3.132 M -RD[3] nCCAS F 9.354 4 3.132 M -RD[4] nCCAS F 9.354 4 3.132 M -RD[5] nCCAS F 9.354 4 3.132 M -RD[6] nCCAS F 9.354 4 3.132 M -RD[7] nCCAS F 9.354 4 3.132 M +RA[1] RCLK R 11.454 4 3.535 M +RA[1] nCRAS F 11.216 4 3.347 M +RA[2] RCLK R 12.084 4 3.693 M +RA[2] nCRAS F 11.742 4 3.501 M +RA[3] RCLK R 12.131 4 3.715 M +RA[3] nCRAS F 11.857 4 3.533 M +RA[4] RCLK R 11.966 4 3.684 M +RA[4] nCRAS F 12.319 4 3.650 M +RA[5] RCLK R 11.928 4 3.670 M +RA[5] nCRAS F 11.637 4 3.446 M +RA[6] RCLK R 11.419 4 3.523 M +RA[6] nCRAS F 11.718 4 3.486 M +RA[7] RCLK R 11.988 4 3.651 M +RA[7] nCRAS F 12.274 4 3.636 M +RA[8] RCLK R 11.660 4 3.582 M +RA[8] nCRAS F 11.098 4 3.343 M +RA[9] RCLK R 11.454 4 3.547 M +RA[9] nCRAS F 11.134 4 3.314 M +RBA[0] nCRAS F 8.903 4 2.891 M +RBA[1] nCRAS F 8.883 4 2.898 M +RCKE RCLK R 9.774 4 3.159 M +RCLKout RCLK R 7.101 4 2.108 M +RDQMH RCLK R 10.733 4 3.351 M +RDQML RCLK R 10.683 4 3.364 M +RD[0] nCCAS F 8.977 4 3.012 M +RD[1] nCCAS F 8.977 4 3.012 M +RD[2] nCCAS F 8.977 4 3.012 M +RD[3] nCCAS F 8.977 4 3.012 M +RD[4] nCCAS F 8.977 4 3.012 M +RD[5] nCCAS F 8.977 4 3.012 M +RD[6] nCCAS F 8.977 4 3.012 M +RD[7] nCCAS F 8.977 4 3.012 M nRCAS RCLK R 7.822 4 2.706 M nRCS RCLK R 7.822 4 2.706 M nRRAS RCLK R 7.822 4 2.706 M nRWE RCLK R 7.803 4 2.713 M WARNING: you must also run trce with hold speed: 4 -WARNING: you must also run trce with setup speed: 6 -WARNING: you must also run trce with hold speed: 6 WARNING: you must also run trce with setup speed: M diff --git a/CPLD/LCMXO2-1200HC/promote.xml b/CPLD/LCMXO2-1200HC/promote.xml index e123aa4..5954a9d 100644 --- a/CPLD/LCMXO2-1200HC/promote.xml +++ b/CPLD/LCMXO2-1200HC/promote.xml @@ -1,3 +1,3 @@ - + diff --git a/CPLD/LCMXO2-1200HC/reportview.xml b/CPLD/LCMXO2-1200HC/reportview.xml index 3b15940..00d2aa3 100644 --- a/CPLD/LCMXO2-1200HC/reportview.xml +++ b/CPLD/LCMXO2-1200HC/reportview.xml @@ -3,7 +3,7 @@ - + diff --git a/CPLD/LCMXO2-640HC/RAM2GS-LCMXO2.ccl b/CPLD/LCMXO2-640HC/RAM2GS-LCMXO2.ccl new file mode 100644 index 0000000..43a374b --- /dev/null +++ b/CPLD/LCMXO2-640HC/RAM2GS-LCMXO2.ccl @@ -0,0 +1 @@ +VERSION=20110520 diff --git a/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcl.html b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcl.html new file mode 100644 index 0000000..6111ed7 --- /dev/null +++ b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcl.html @@ -0,0 +1,90 @@ + +Lattice TCL Log + + +
    pn231117181450
+#Start recording tcl command: 11/16/2023 13:08:29
+#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
+prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
+prj_project close
+#Stop recording: 11/17/2023 18:14:50
+
+
+
+pn231118021827
+#Start recording tcl command: 11/17/2023 18:14:55
+#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
+prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
+prj_run Export -impl impl1
+prj_run PAR -impl impl1
+prj_run Export -impl impl1
+prj_run PAR -impl impl1 -forceAll
+prj_run PAR -impl impl1 -forceAll
+prj_run PAR -impl impl1 -forceAll
+prj_run PAR -impl impl1 -forceAll
+prj_run PAR -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+#Stop recording: 11/18/2023 02:18:27
+
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+
    + + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.alt b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.alt index 96cb6a4..b028858 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.alt +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.alt @@ -1,6 +1,6 @@ NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation * NOTE All Rights Reserved * -NOTE DATE CREATED: Thu Sep 21 05:40:18 2023 * +NOTE DATE CREATED: Sat Nov 18 02:06:30 2023 * NOTE DESIGN NAME: RAM2GS * NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100 * NOTE PIN ASSIGNMENTS * @@ -13,6 +13,7 @@ NOTE PINS nRCAS : 52 : out * NOTE PINS nRRAS : 54 : out * NOTE PINS nRWE : 49 : out * NOTE PINS RCKE : 53 : out * +NOTE PINS RCLKout : 60 : out * NOTE PINS RCLK : 63 : in * NOTE PINS nRCS : 57 : out * NOTE PINS RD[7] : 43 : inout * @@ -34,7 +35,7 @@ NOTE PINS RA[3] : 71 : out * NOTE PINS RA[2] : 69 : out * NOTE PINS RA[1] : 67 : out * NOTE PINS RA[0] : 66 : out * -NOTE PINS RBA[1] : 60 : out * +NOTE PINS RBA[1] : 47 : out * NOTE PINS RBA[0] : 58 : out * NOTE PINS LED : 34 : out * NOTE PINS nFWE : 15 : in * diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.areasrr b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.areasrr index adb67c1..d45b0b0 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.areasrr +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.areasrr @@ -3,7 +3,7 @@ Report for cell RAM2GS.verilog Register bits: 109 of 640 (17%) PIC Latch: 0 -I/O cells: 63 +I/O cells: 64 Cell usage: cell count Res Usage(%) BB 8 100.0 @@ -17,19 +17,20 @@ I/O cells: 63 IB 25 100.0 IFS1P3DX 9 100.0 INV 7 100.0 - OB 30 100.0 + OB 31 100.0 + ODDRXE 1 100.0 OFS1P3BX 4 100.0 OFS1P3DX 11 100.0 OFS1P3JX 1 100.0 - ORCALUT4 213 100.0 - PFUMX 1 100.0 + ORCALUT4 212 100.0 + PFUMX 2 100.0 PUR 1 100.0 VHI 2 100.0 VLO 2 100.0 SUB MODULES REFB 1 100.0 - TOTAL 411 + TOTAL 413 ---------------------------------------------------------------------- Report for cell REFB.netlist Instance path: ufmefb diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.bgn b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.bgn index cd990ca..11bb7df 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.bgn +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.bgn @@ -4,7 +4,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Thu Sep 21 05:40:14 2023 +Sat Nov 18 02:06:26 2023 Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC -w -jedec -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf @@ -81,6 +81,6 @@ UFM Utilization: General Purpose Flash Memory. Available General Purpose Flash Memory: 191 Pages (Page 0 to Page 190). Initialized UFM Pages: 1 Page (Page 190). -Total CPU Time: 3 secs +Total CPU Time: 4 secs Total REAL Time: 4 secs -Peak Memory Usage: 266 MB +Peak Memory Usage: 267 MB diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.bit b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.bit index 24b0f7c..f291142 100644 Binary files a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.bit and b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.bit differ diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.edi b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.edi index 321f62b..e2e19aa 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.edi +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.edi @@ -4,7 +4,7 @@ (keywordMap (keywordLevel 0)) (status (written - (timeStamp 2023 9 21 5 39 41) + (timeStamp 2023 11 18 2 5 48) (author "Synopsys, Inc.") (program "Synplify Pro" (version "R-2021.03L-SP1, mapper map202103lat, Build 070R")) ) @@ -371,14 +371,14 @@ (port (array (rename wb_dati "wb_dati[7:0]") 8) (direction INPUT)) (port (array (rename wb_adr "wb_adr[7:0]") 8) (direction INPUT)) (port (array (rename fs "FS[14:12]") 3) (direction INPUT)) + (port FS_RNIF2MA_0 (direction INPUT)) + (port FS_RNIHVJI_0 (direction INPUT)) (port wb_we (direction INPUT)) (port wb_cyc_stb (direction INPUT)) (port wb_rst (direction INPUT)) (port RCLK_c (direction INPUT)) (port wb_ack (direction OUTPUT)) (port N_4 (direction OUTPUT)) - (port N_226 (direction INPUT)) - (port N_214 (direction INPUT)) ) (contents (instance EFBInst_0_RNISI191 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) @@ -441,12 +441,12 @@ ) (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT))) ) (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) - (net N_214 (joined - (portRef N_214) + (net (rename FS_RNIHVJI_0 "FS_RNIHVJI[15]") (joined + (portRef FS_RNIHVJI_0) (portRef A (instanceRef EFBInst_0_RNISI191)) )) - (net N_226 (joined - (portRef N_226) + (net (rename FS_RNIF2MA_0 "FS_RNIF2MA[9]") (joined + (portRef FS_RNIF2MA_0) (portRef B (instanceRef EFBInst_0_RNISI191)) )) (net g0_0_a3_2 (joined @@ -769,6 +769,19 @@ (property orig_inst_of (string "REFB")) ) ) + (cell ODDRXE (cellType GENERIC) + (view verilog (viewType NETLIST) + (interface + (port D0 (direction INPUT)) + (port D1 (direction INPUT)) + (port SCLK (direction INPUT)) + (port RST (direction INPUT)) + (port Q (direction OUTPUT)) + ) + (property GSR (string "ENABLED")) + (property orig_inst_of (string "ODDRXE")) + ) + ) (cell RAM2GS (cellType GENERIC) (view verilog (viewType NETLIST) (interface @@ -786,6 +799,7 @@ (port (array (rename rd "RD[7:0]") 8) (direction INOUT)) (port nRCS (direction OUTPUT)) (port RCLK (direction INPUT)) + (port RCLKout (direction OUTPUT)) (port RCKE (direction OUTPUT)) (port nRWE (direction OUTPUT)) (port nRRAS (direction OUTPUT)) @@ -803,80 +817,72 @@ (instance nCCAS_pad_RNISUR8 (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) (instance RASr_RNO (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) (instance FWEr_RNO (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) - (instance nRCAS_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (B+!A)+C B)+D B)")) - ) - (instance (rename wb_dati_5_1_iv_0_a3_0_RNO_1 "wb_dati_5_1_iv_0_a3_0_RNO[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (!C (!B A)))")) - ) - (instance wb_we_0_i_0_0_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C (!B !A))")) - ) - (instance (rename FS_RNIHVJI_0_16 "FS_RNIHVJI_0[16]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B !A)))")) - ) - (instance (rename FS_RNIJO0F_14 "FS_RNIJO0F[14]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B !A))")) + (instance (rename wb_dati_5_1_iv_0_a2_0_RNO_7 "wb_dati_5_1_iv_0_a2_0_RNO[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B A))")) ) (instance C1Submitted_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (B+A)+D (!C A+C (B+A)))")) ) - (instance (rename wb_dati_5_1_iv_i_i_1_RNO_3 "wb_dati_5_1_iv_i_i_1_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C A+C (!B A))")) + (instance (rename FS_RNIJO0F_12 "FS_RNIJO0F[12]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B !A))")) ) - (instance Ready_RNICVV51 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance (rename S_RNICVV51_1 "S_RNICVV51[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C (!B A))")) ) - (instance (rename wb_dati_5_1_iv_i_i_0_RNO_3 "wb_dati_5_1_iv_i_i_0_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (!B A)))")) - ) - (instance nRCAS_r_i_0_o2_0_2_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance nRCAS_0io_RNO_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C (!B !A)+C !A)")) ) - (instance un1_nRCAS_6_sqmuxa_i_0_0_o2_0_RNIQVER (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D+(!C+(!B+A)))")) + (instance (rename wb_adr_5_i_0_2_RNO_0_0 "wb_adr_5_i_0_2_RNO_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B A)))")) + ) + (instance (rename FS_RNIOVGI_9 "FS_RNIOVGI[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B !A)))")) + ) + (instance (rename FS_RNIHVJI_0_15 "FS_RNIHVJI_0[15]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B !A)))")) + ) + (instance (rename wb_adr_5_i_0_2_RNO_0 "wb_adr_5_i_0_2_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D B+D (!C (B+A)+C B))")) ) (instance (rename wb_adr_RNO_0_1 "wb_adr_RNO_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D A+D (!C (B A)))")) ) - (instance RCKEEN_8_u_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance RCKEEN_8_u_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (!C (!B A)+C (!B+!A))+D (C !A))")) ) - (instance (rename wb_adr_RNO_0_0 "wb_adr_RNO_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C (!B A))")) - ) - (instance wb_we_0_i_0_1_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C A+C (!B+A))")) - ) (instance (rename IS_RNO_3 "IS_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D A+D (!C A+C (!B A+B !A)))")) ) (instance wb_reqe_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B !A)))")) + (property lut_function (string "(!D !A+D (!C !A+C (!B !A)))")) ) - (instance (rename wb_dati_5_1_iv_0_RNO_0_7 "wb_dati_5_1_iv_0_RNO_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance (rename wb_dati_5_1_iv_0_o2_0_RNIMDJC1_4 "wb_dati_5_1_iv_0_o2_0_RNIMDJC1[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B A)))")) + ) + (instance (rename wb_dati_5_1_iv_0_1_RNO_7 "wb_dati_5_1_iv_0_1_RNO[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (!C (!B A)))")) ) (instance (rename wb_dati_5_1_iv_0_RNO_7 "wb_dati_5_1_iv_0_RNO[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (!B A)+D (C (!B A)))")) ) - (instance un1_CmdEnable20_0_0_a2_0_RNI00E51 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance un1_CmdEnable20_0_0_a2_3_RNIJ3N91 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D (!C (B A)))")) ) (instance Ready_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D A+D (!C (B+A)+C A))")) ) - (instance nRRAS_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B+!A)+C !A))")) + (instance (rename wb_adr_5_i_0_1_0 "wb_adr_5_i_0_1[0]") (viewRef PRIM (cellRef PFUMX (libraryRef LUCENT))) ) + (instance (rename wb_adr_5_i_0_1_bm_0 "wb_adr_5_i_0_1_bm[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B A))")) ) - (instance nRCS_9_u_i_0_o2_1_RNIL2K71_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B !A)))")) + (instance (rename wb_adr_5_i_0_1_am_0 "wb_adr_5_i_0_1_am[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (!B A+B !A)))")) ) - (instance (rename wb_dati_5_1_iv_0_o3_5 "wb_dati_5_1_iv_0_o3[5]") (viewRef PRIM (cellRef PFUMX (libraryRef LUCENT))) ) - (instance (rename wb_dati_5_1_iv_0_o3_bm_5 "wb_dati_5_1_iv_0_o3_bm[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance (rename wb_dati_5_1_iv_0_0_o2_5 "wb_dati_5_1_iv_0_0_o2[5]") (viewRef PRIM (cellRef PFUMX (libraryRef LUCENT))) ) + (instance (rename wb_dati_5_1_iv_0_0_o2_bm_5 "wb_dati_5_1_iv_0_0_o2_bm[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (!C A+C (!B+A))+D A)")) ) - (instance (rename wb_dati_5_1_iv_0_o3_am_5 "wb_dati_5_1_iv_0_o3_am[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance (rename wb_dati_5_1_iv_0_0_o2_am_5 "wb_dati_5_1_iv_0_0_o2_am[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D A+D (!C A+C (!B+A)))")) ) (instance Ready_fast_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) @@ -1128,6 +1134,7 @@ (instance nRRAS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) (instance nRWE_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) (instance RCKE_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance RCLKout_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) (instance RCLK_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) (instance nRCS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) (instance (rename RD_pad_7 "RD_pad[7]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) @@ -1197,44 +1204,47 @@ (instance CmdEnable_s (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D+(!C A+C B))")) ) - (instance CmdEnable_0_sqmuxa_0_a3_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance CmdEnable_0_sqmuxa_0_a2_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(B A)")) ) - (instance (rename wb_dati_5_1_iv_0_2 "wb_dati_5_1_iv_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance nRWE_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C+(!B+A))+D A)")) + ) + (instance (rename wb_dati_5_1_iv_0_0_5 "wb_dati_5_1_iv_0_0[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C B+C (B+A))")) ) - (instance (rename wb_dati_5_1_iv_0_5 "wb_dati_5_1_iv_0[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance (rename wb_dati_5_1_iv_0_0_2 "wb_dati_5_1_iv_0_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C B+C (B+A))")) ) (instance CmdEnable_s_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (!C !B)+D (!C (!B A)))")) ) - (instance nRWE_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C+(!B+A))+D A)")) - ) - (instance CmdUFMData_1_sqmuxa_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance CmdUFMData_1_sqmuxa_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(B A)")) ) (instance wb_we_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B+A)+C (B A)))")) + (property lut_function (string "(!D (!C+(B A)))")) ) (instance (rename wb_adr_RNO_0 "wb_adr_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B A)))")) + (property lut_function (string "(!D (!C (!B+!A)))")) + ) + (instance nRCS_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B+!A)+C !A))")) ) (instance un1_ADWR_i_i_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!B A)")) ) - (instance CmdUFMData_1_sqmuxa_0_a3_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance CmdUFMData_1_sqmuxa_0_a2_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (!C (B A)))")) ) - (instance (rename wb_dati_5_1_iv_i_i_3 "wb_dati_5_1_iv_i_i[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C+B)+D (C+(B+A)))")) - ) - (instance (rename wb_dati_5_1_iv_0_6 "wb_dati_5_1_iv_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance (rename wb_dati_5_1_iv_0_0_6 "wb_dati_5_1_iv_0_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D+(C (!B !A)))")) ) (instance (rename wb_dati_5_1_iv_0_7 "wb_dati_5_1_iv_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C+(B+A)))")) + (property lut_function (string "(D+(!C A+C (B+A)))")) + ) + (instance (rename wb_dati_5_1_iv_0_0_3 "wb_dati_5_1_iv_0_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+B)+D (C+(B+A)))")) ) (instance Cmdn8MEGEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C (!B !A)+C !A)")) @@ -1245,236 +1255,224 @@ (instance (rename wb_adr_RNO_1 "wb_adr_RNO[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (!C (!B A)))")) ) - (instance nRCS_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C !A+C (!B !A))+D (!C !A))")) + (instance RA10_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(!C+(B+A)))")) + ) + (instance un1_CmdEnable20_0_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(!B+!A)))")) ) (instance (rename wb_dati_5_1_iv_0_1 "wb_dati_5_1_iv_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D+(C (!B !A)))")) ) - (instance un1_CmdEnable20_0_0_o3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C+(!B+!A)))")) + (instance nRWE_s_i_tz_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C (B !A)))")) ) - (instance (rename wb_dati_5_1_iv_0_1_6 "wb_dati_5_1_iv_0_1[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance (rename wb_dati_5_1_iv_0_0_1_6 "wb_dati_5_1_iv_0_0_1[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (C+B)+D (C+(B+A)))")) ) - (instance (rename wb_dati_5_1_iv_0_1_4 "wb_dati_5_1_iv_0_1[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance (rename wb_dati_5_1_iv_0_1_7 "wb_dati_5_1_iv_0_1[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (C+B)+D (C+(B+A)))")) ) - (instance (rename wb_dati_5_1_iv_0_a3_3_7 "wb_dati_5_1_iv_0_a3_3[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (!B !A)))")) + (instance (rename wb_dati_5_1_iv_0_0_1_4 "wb_dati_5_1_iv_0_0_1[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+B)+D (C+(B+A)))")) ) (instance (rename wb_dati_5_0_iv_0_0 "wb_dati_5_0_iv_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (C B)+D (!C A+C (B+A)))")) ) - (instance wb_cyc_stb_4_iv_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance wb_cyc_stb_4_iv_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D C+D (C+(B A)))")) ) - (instance RA10_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(!C+(B+A)))")) - ) - (instance (rename wb_dati_5_1_iv_0_a3_6 "wb_dati_5_1_iv_0_a3[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (!C (!B !A+B A)))")) - ) - (instance wb_we_0_i_0_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C (B A)))")) - ) - (instance nRWE_s_i_0_tz_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C (B !A)))")) - ) - (instance (rename wb_dati_5_1_iv_0_1_1 "wb_dati_5_1_iv_0_1[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C+B)+D (C+(B+A)))")) - ) - (instance (rename wb_dati_5_1_iv_i_i_0_3 "wb_dati_5_1_iv_i_i_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C A)+D (!C B+C (B+A)))")) - ) - (instance (rename wb_dati_5_1_iv_i_i_1_3 "wb_dati_5_1_iv_i_i_1[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D A+D (!C A+C (B+A)))")) - ) - (instance (rename IS_RNO_0 "IS_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B !A+B A)")) - ) - (instance XOR8MEG_3_u_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D C+D (C+(!B+!A)))")) - ) - (instance un1_nRCAS_6_sqmuxa_i_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (B+A)+D !C)")) - ) - (instance CmdUFMShift_3_u_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C A)+D (!C !B+C (!B+A)))")) - ) (instance CmdUFMWrite_3_u_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D C+D (C+(B !A)))")) ) - (instance (rename wb_dati_5_1_iv_0_o2_7 "wb_dati_5_1_iv_0_o2[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B !A+B A)+C (!B !A))+D (C (!B !A)))")) - ) - (instance nRCS_9_u_i_0_o3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D A+D (C+(B+A)))")) - ) - (instance nRWE_s_i_0_a3_1_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance nRWE_s_i_a2_1_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (!C (!B A)))")) ) - (instance (rename wb_dati_5_1_iv_0_a3_4 "wb_dati_5_1_iv_0_a3[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (!B !A+B A)))")) + (instance nRCS_9_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(!C (!B A)+C !B))")) ) - (instance wb_cyc_stb_2_sqmuxa_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C+A)+D (C+(B+A)))")) + (instance (rename wb_dati_5_1_iv_0_0_a2_6 "wb_dati_5_1_iv_0_0_a2[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B !A+B A)))")) ) - (instance wb_cyc_stb_4_iv_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (B !A)))")) + (instance (rename wb_dati_5_1_iv_0_1_1 "wb_dati_5_1_iv_0_1[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C (B A)))")) ) - (instance (rename wb_dati_5_1_iv_0_a3_0_6 "wb_dati_5_1_iv_0_a3_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (B A)))")) + (instance (rename wb_dati_5_1_iv_0_0_0_3 "wb_dati_5_1_iv_0_0_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C (B+A))")) ) - (instance Cmdn8MEGEN_4_u_i_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance (rename wb_dati_5_1_iv_0_0_1_3 "wb_dati_5_1_iv_0_0_1[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D C+D (C+(B A)))")) + ) + (instance un1_nRCAS_6_sqmuxa_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+(!B+A))+D (!C (!B+A)))")) + ) + (instance (rename wb_dati_5_1_iv_0_o2_7 "wb_dati_5_1_iv_0_o2[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(B !A))")) + ) + (instance XOR8MEG_3_u_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D C+D (C+(!B+!A)))")) + ) + (instance CmdUFMShift_3_u_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (C A)+D (!C !B+C (!B+A)))")) ) - (instance CmdLEDEN_4_u_i_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance (rename wb_dati_5_1_iv_0_a2_5_3 "wb_dati_5_1_iv_0_a2_5[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance (rename wb_dati_5_1_iv_0_a2_7_3 "wb_dati_5_1_iv_0_a2_7[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B !A)))")) + ) + (instance (rename wb_dati_5_1_iv_0_a2_2_4 "wb_dati_5_1_iv_0_a2_2[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance wb_cyc_stb_4_iv_0_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B A)))")) + ) + (instance wb_cyc_stb_2_sqmuxa_i_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+B)+D (C+(B+A)))")) + ) + (instance Cmdn8MEGEN_4_u_i_m2_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C A)+D (!C !B+C (!B+A)))")) + ) + (instance CmdLEDEN_4_u_i_m2_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (!C B)+D (!C (B+!A)+C !A))")) ) - (instance un1_CmdEnable20_0_0_a3_1_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance un1_CmdEnable20_0_0_a2_1_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(C (B A))")) ) - (instance wb_we_0_i_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D C+D (C+(B+!A)))")) + (instance un1_CmdEnable20_0_0_o2_10 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(!B+!A)))")) ) - (instance un1_CmdEnable20_0_0_o3_10 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C+(B+!A)))")) - ) - (instance nRCAS_r_i_0_o2_0_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance nRCAS_0io_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D (!C !A+C (!B !A)))")) ) (instance un1_CmdEnable20_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (!B !A)+D (C+(!B !A)))")) ) + (instance (rename wb_adr_5_i_0_2_0 "wb_adr_5_i_0_2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+(B+A))+D (C+(B !A)))")) + ) (instance (rename wb_adr_5_i_0_3_0 "wb_adr_5_i_0_3[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D+(C (B !A)))")) ) - (instance (rename wb_dati_5_1_iv_0_0_7 "wb_dati_5_1_iv_0_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance (rename wb_dati_5_1_iv_0_0_1 "wb_dati_5_1_iv_0_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (C A)+D (!C !B+C (!B+A)))")) ) + (instance IS_0_sqmuxa_0_o3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance (rename wb_adr_5_i_3_0_a2_1 "wb_adr_5_i_3_0_a2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C !B+C A))")) + ) + (instance (rename wb_dati_5_1_iv_0_a2_12_3 "wb_dati_5_1_iv_0_a2_12[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B !A)")) + ) + (instance CmdUFMWrite_3_u_0_0_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) (instance CmdValid_r (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!B A)")) ) - (instance CmdValid_RNIS5A51 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D !B+D (!C (!B+A)+C !B))")) + (instance LED_pad_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(!C+(!B+A)))")) ) - (instance CmdUFMWrite_3_u_0_0_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B A)")) - ) - (instance (rename wb_dati_5_1_iv_i_i_a2_3_3 "wb_dati_5_1_iv_i_i_a2_3[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B !A)")) - ) - (instance (rename wb_adr_5_i_0_a3_1 "wb_adr_5_i_0_a3[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (!C !B+C A))")) - ) - (instance wb_we_0_i_0_a3_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (!C (!B !A)+C (!B A)))")) - ) - (instance (rename wb_adr_5_i_0_a3_0_1 "wb_adr_5_i_0_a3_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance (rename wb_adr_5_i_3_0_a2_0_1 "wb_adr_5_i_3_0_a2_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (!C (B A))+D (!C A))")) ) - (instance nRCS_9_u_i_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B A))+D (!C !B))")) + (instance (rename wb_dati_5_1_iv_0_a2_0_7 "wb_dati_5_1_iv_0_a2_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B A+B !A)))")) ) - (instance Ready_0_sqmuxa_0_a2_4_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance Ready_0_sqmuxa_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D (!C (!B A)))")) ) - (instance (rename wb_dati_5_1_iv_0_a3_0_1 "wb_dati_5_1_iv_0_a3_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C (B !A))")) + (instance nRCS_9_u_i_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B !A)+C !A))")) ) - (instance InitReady3_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (B A)))")) + (instance (rename wb_adr_5_i_3_0_m2_1 "wb_adr_5_i_3_0_m2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B !A)+C (!B+A))")) ) - (instance (rename wb_adr_5_i_0_0_0 "wb_adr_5_i_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (!C (B A)+C B))")) + (instance (rename wb_adr_5_i_m2_4 "wb_adr_5_i_m2[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B !A)+C (!B+A))")) ) - (instance (rename wb_adr_5_i_0_1_0 "wb_adr_5_i_0_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D C+D (C+(!B A+B !A)))")) + (instance (rename wb_adr_5_i_m2_5 "wb_adr_5_i_m2[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B !A)+C (!B+A))")) ) - (instance (rename wb_adr_5_i_m2_i_m2_6 "wb_adr_5_i_m2_i_m2[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B A))+D (!C (B+A)+C B))")) - ) - (instance (rename wb_adr_5_i_m2_i_m2_5 "wb_adr_5_i_m2_i_m2[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B A))+D (!C (B+A)+C B))")) - ) - (instance (rename wb_adr_5_i_m2_i_m2_4 "wb_adr_5_i_m2_i_m2[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B A))+D (!C (B+A)+C B))")) - ) - (instance (rename wb_adr_5_i_0_m2_0 "wb_adr_5_i_0_m2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B A))+D (!C (B+A)+C B))")) - ) - (instance (rename wb_adr_5_i_0_m2_1 "wb_adr_5_i_0_m2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B A))+D (!C (B+A)+C B))")) + (instance (rename wb_adr_5_i_m2_6 "wb_adr_5_i_m2[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B !A)+C (!B+A))")) ) (instance (rename IS_RNO_2 "IS_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C (B A)+C (!B+!A))")) ) - (instance XOR8MEG_3_u_0_0_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C+(B+A)))")) + (instance nRowColSel_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C B+C (B+!A)))")) ) - (instance nRowColSel_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C+(B !A)))")) - ) - (instance (rename wb_adr_5_i_0_o2_0 "wb_adr_5_i_0_o2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance (rename wb_dati_5_1_iv_0_0_o2_4 "wb_dati_5_1_iv_0_0_o2[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C (!B !A+B A)+C (!B !A))")) ) - (instance (rename wb_dati_5_1_iv_i_i_o2_3 "wb_dati_5_1_iv_i_i_o2[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance (rename wb_dati_5_1_iv_0_0_o2_3 "wb_dati_5_1_iv_0_0_o2[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (C (!B !A))+D (!C (B A)))")) ) - (instance CmdValid_2_i_o2_1_o3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance XOR8MEG_3_u_0_0_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C+(B+A)))")) + ) + (instance CmdValid_2_i_o2_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D+(!C !B+C (!B+!A)))")) ) + (instance un1_InitReady_4_i_0_a2_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D !B+D (!C (!B+A)+C !B))")) + ) (instance ADSubmitted_r_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (C+(!B A)))")) ) - (instance LED_pad_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C+(!B+A))")) - ) - (instance (rename wb_adr_5_i_0_a3_4_0 "wb_adr_5_i_0_a3_4[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (!C (!B A)))")) - ) - (instance wb_cyc_stb_4_iv_0_a3_0_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (!C (!B !A)))")) - ) - (instance un1_CmdEnable20_0_0_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance un1_CmdEnable20_0_0_a2_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D (!C (B !A)))")) ) - (instance un1_CmdEnable20_0_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance un1_CmdEnable20_0_0_a2_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D (C (!B A)))")) ) - (instance nRWE_s_i_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance wb_we_0_0_i_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B !A)+C !B))")) + ) + (instance wb_rst_3_0_a2_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B !A)))")) + ) + (instance wb_cyc_stb_2_sqmuxa_i_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B !A)))")) + ) + (instance nRWE_s_i_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D (C (!B A)))")) ) - (instance XOR8MEG_3_u_0_0_a3_0_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance XOR8MEG_3_u_0_0_a2_0_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D (C (!B A)))")) ) - (instance wb_cyc_stb_2_sqmuxa_i_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance wb_cyc_stb_2_sqmuxa_i_0_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C (B !A)+C B)")) ) - (instance (rename wb_dati_5_1_iv_0_a3_0_1_7 "wb_dati_5_1_iv_0_a3_0_1[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (!B A+B !A)))")) + (instance (rename wb_dati_5_1_iv_0_a2_0_2_1 "wb_dati_5_1_iv_0_a2_0_2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B !A)))")) ) - (instance (rename wb_dati_5_0_iv_0_a3_1_0 "wb_dati_5_0_iv_0_a3_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance (rename wb_dati_5_0_iv_0_a2_1_0 "wb_dati_5_0_iv_0_a2_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D (!C (B A)+C (!B A)))")) ) - (instance RCKE_2_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance RCKE_2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (C !B)+D (C+(B+A)))")) ) (instance (rename S_RNO_0 "S_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(B+!A)")) ) - (instance un1_nRCAS_6_sqmuxa_i_0_0_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance un1_nRCAS_6_sqmuxa_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(C+(B+A))")) ) - (instance Ready_0_sqmuxa_0_a2_4_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance Ready_0_sqmuxa_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C+(!B+!A))")) ) - (instance (rename wb_adr_5_i_0_o2_0_0 "wb_adr_5_i_0_o2_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance (rename wb_dati_5_1_iv_0_a2_5_7 "wb_dati_5_1_iv_0_a2_5[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (!B !A))")) + ) + (instance (rename wb_adr_5_i_0_o2_0 "wb_adr_5_i_0_o2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C (!B !A)+C (!B+A))")) ) - (instance (rename FS_RNIVOOA_14 "FS_RNIVOOA[14]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C (B A))")) + (instance un1_wb_rst14_2_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(B+A))")) ) (instance RDQMH_pad_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!B+A)")) @@ -1482,35 +1480,29 @@ (instance nCCAS_pad_RNI01SJ (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(B+A)")) ) - (instance wb_cyc_stb_4_iv_0_a3_0_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance wb_cyc_stb_2_sqmuxa_i_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C (!B !A))")) ) - (instance RCKEEN_8_u_0_0_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance RCKEEN_8_u_0_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(C (B !A))")) ) - (instance (rename wb_adr_5_i_0_a3_0_2_0 "wb_adr_5_i_0_a3_0_2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C (B !A)))")) - ) - (instance Ready_0_sqmuxa_0_a2_4_a3_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance Ready_0_sqmuxa_0_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D (!C (B A)))")) ) - (instance InitReady3_0_a3_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C (B A))")) + (instance un1_CmdEnable20_0_0_o2_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C+(!B+!A))")) ) - (instance un1_CmdEnable20_0_0_o3_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C+(!B+!A))")) + (instance un1_CmdEnable20_0_0_o2_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(!C+(!B+!A)))")) ) - (instance un1_CmdEnable20_0_0_o3_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D+(!C+(!B+!A)))")) + (instance un1_CmdEnable20_0_0_o2_11 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D+(!C+(!B+A)))")) ) - (instance un1_CmdEnable20_0_0_o3_11 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D+(!C+(!B+!A)))")) - ) - (instance (rename wb_dati_5_1_iv_i_i_a3_1_1_3 "wb_dati_5_1_iv_i_i_a3_1_1[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance (rename wb_dati_5_1_iv_0_0_a2_1_3 "wb_dati_5_1_iv_0_0_a2_1[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (!C (B !A)+C (B A)))")) ) - (instance (rename un9_RA_8 "un9_RA[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C B+C A)")) + (instance LEDEN_6_i_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B A)+C (!B+A))")) ) (instance (rename un9_RA_i_m2_i_m2_0 "un9_RA_i_m2_i_m2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C B+C A)")) @@ -1518,12 +1510,6 @@ (instance (rename un9_RA_i_m2_i_m2_1 "un9_RA_i_m2_i_m2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C B+C A)")) ) - (instance (rename un9_RA_i_m2_i_m2_2 "un9_RA_i_m2_i_m2[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C B+C A)")) - ) - (instance (rename un9_RA_i_m2_i_m2_3 "un9_RA_i_m2_i_m2[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C B+C A)")) - ) (instance (rename un9_RA_i_m2_i_m2_4 "un9_RA_i_m2_i_m2[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C B+C A)")) ) @@ -1539,104 +1525,113 @@ (instance (rename un9_RA_i_m2_i_m2_9 "un9_RA_i_m2_i_m2[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C B+C A)")) ) - (instance LEDEN_6_i_m2_i_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B A)+C (!B+A))")) + (instance (rename un9_RA_i_m2_i_m2_3 "un9_RA_i_m2_i_m2[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) ) - (instance nRCAS_r_i_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B !A)")) + (instance (rename un9_RA_i_m2_i_m2_2 "un9_RA_i_m2_i_m2[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) ) - (instance CmdLEDEN_4_u_i_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B A)")) + (instance (rename un9_RA_8 "un9_RA[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) ) - (instance XOR8MEG_3_u_0_0_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B A)")) - ) - (instance (rename wb_dati_5_0_iv_0_a2_0 "wb_dati_5_0_iv_0_a2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B A)")) - ) - (instance (rename wb_dati_5_1_iv_0_a2_6 "wb_dati_5_1_iv_0_a2[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B !A)")) - ) - (instance XOR8MEG_3_u_0_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B !A)")) - ) - (instance nRowColSel_0_0_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B !A)")) - ) - (instance RDQML_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B+!A)")) - ) - (instance (rename wb_adr_5_i_0_o2_1 "wb_adr_5_i_0_o2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B+!A)")) - ) - (instance XOR8MEG_3_u_0_0_o2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B+A)")) - ) - (instance (rename S_0_i_o2_i_o2_1 "S_0_i_o2_i_o2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B+A)")) - ) - (instance nRCS_9_u_i_0_o2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B+!A)")) - ) - (instance (rename wb_dati_5_1_iv_0_o2_0_7 "wb_dati_5_1_iv_0_o2_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B+!A)")) - ) - (instance RCKEEN_8_u_0_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B+!A)")) - ) - (instance IS_n1_0_x2_0_x2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B A+B !A)")) - ) - (instance nRowColSel_0_0_0_x2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B A+B !A)")) - ) - (instance (rename FS_RNIH267_16 "FS_RNIH267[16]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B+A)")) - ) - (instance (rename wb_dati_5_1_iv_i_i_a2_2_3 "wb_dati_5_1_iv_i_i_a2_2[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B A)")) - ) - (instance (rename wb_adr_5_i_0_a2_0_1 "wb_adr_5_i_0_a2_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B !A)")) - ) - (instance (rename wb_adr_5_i_0_a2_1_0 "wb_adr_5_i_0_a2_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B A)")) - ) - (instance (rename wb_adr_5_7 "wb_adr_5[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance (rename wb_adr_5_2 "wb_adr_5[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(B A)")) ) (instance (rename wb_adr_5_3 "wb_adr_5[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(B A)")) ) - (instance (rename wb_adr_5_2 "wb_adr_5[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance (rename wb_adr_5_7 "wb_adr_5[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(B A)")) ) - (instance wb_cyc_stb_4_iv_0_a3_0_2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance nRCS_9_u_i_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!B !A)")) ) - (instance wb_cyc_stb_4_iv_0_a3_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance nRowColSel_0_0_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B !A)")) + ) + (instance (rename S_0_i_o3_1 "S_0_i_o3[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance RCKEEN_8_u_0_o3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B+!A)")) + ) + (instance IS_n1_0_x2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B A+B !A)")) + ) + (instance nRowColSel_0_0_x2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B A+B !A)")) + ) + (instance (rename wb_adr_5_i_0_a2_6_0 "wb_adr_5_i_0_a2_6[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B A)")) + ) + (instance (rename wb_dati_5_1_iv_0_a2_6_4 "wb_dati_5_1_iv_0_a2_6[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(B A)")) ) - (instance (rename wb_dati_5_1_iv_0_0_4 "wb_dati_5_1_iv_0_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance (rename wb_adr_5_i_3_0_a2_3_1 "wb_adr_5_i_3_0_a2_3[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B !A)")) + ) + (instance (rename wb_dati_5_1_iv_0_a2_11_3 "wb_dati_5_1_iv_0_a2_11[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B A)")) + ) + (instance (rename wb_dati_5_1_iv_0_a2_7_4 "wb_dati_5_1_iv_0_a2_7[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B !A)")) + ) + (instance (rename wb_dati_5_1_iv_0_o2_0_7 "wb_dati_5_1_iv_0_o2_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+!A)")) + ) + (instance Cmdn8MEGEN_4_u_i_m2_i_a2_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance XOR8MEG_3_u_0_0_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B A)")) + ) + (instance XOR8MEG_3_u_0_0_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B !A)")) + ) + (instance XOR8MEG_3_u_0_0_o2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance RDQML_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B+!A)")) + ) + (instance wb_cyc_stb_2_sqmuxa_i_a2_2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B !A)")) + ) + (instance wb_cyc_stb_4_iv_0_0_a2_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance InitReady3_0_a2_1_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D+(!C+(!B+!A)))")) + ) + (instance InitReady3_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B A)))")) + ) + (instance wb_we_0_0_i_1_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D !C+D (!C (!B+A)))")) + ) + (instance wb_we_0_0_i_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D+(!C (B A)+C A))")) + ) + (instance (rename wb_dati_5_1_iv_0_1_0_4 "wb_dati_5_1_iv_0_1_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (!B+A)+D (!C (!B+A)+C (!B !A)))")) ) - (instance (rename wb_dati_5_1_iv_0_4 "wb_dati_5_1_iv_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(!C A+C (B !A)))")) + (instance (rename wb_dati_5_1_iv_0_0_4 "wb_dati_5_1_iv_0_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+A)+D (C+(B !A)))")) ) - (instance RCKEEN_8_u_0_1_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance RCKEEN_8_u_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (!C+B)+D (C (!B+!A)))")) ) - (instance RCKEEN_8_u_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance RCKEEN_8_u (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D B+D (!C B+C (B+!A)))")) ) (instance LEDENe (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B A)+C (B+A))")) + (property lut_function (string "(!C A+C B)")) ) (instance wb_rste (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C !A)+D (!C (B A)+C (B+!A)))")) + (property lut_function (string "(!C (B !A)+C (B+A))")) ) (instance wb_reqe (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B A)+C (!B+A))")) + (property lut_function (string "(!C (B A)+C (B+!A))")) ) (instance CmdValid_fast_RNI3K0H1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D+(C (B A)))")) @@ -1645,7 +1640,7 @@ (property lut_function (string "(B !A)")) ) (instance n8MEGEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B+A)+C (B !A))")) + (property lut_function (string "(!C A+C !B)")) ) (instance CmdValid_RNIOOBE2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D C+D (C+(B A)))")) @@ -1653,15 +1648,30 @@ (instance (rename FS_RNI7U6M_14 "FS_RNI7U6M[14]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!B !A)")) ) - (instance (rename FS_RNIGOCT_14 "FS_RNIGOCT[14]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance (rename FS_RNIGOCT_12 "FS_RNIGOCT[12]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (!C (B A)))")) ) - (instance wb_cyc_stb_4_iv_0_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance wb_cyc_stb_4_iv_0_0_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(C (!B A))")) ) + (instance (rename FS_RNI82PA_15 "FS_RNI82PA[15]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(B+!A))")) + ) + (instance (rename FS_RNIHVJI_15 "FS_RNIHVJI[15]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(B+!A)))")) + ) + (instance (rename FS_RNIF2MA_9 "FS_RNIF2MA[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C+(!B+!A))")) + ) (instance n8MEGEN_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C (!B+!A)+C (B !A))")) ) + (instance (rename FS_RNIS637_9 "FS_RNIS637[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B+!A)")) + ) + (instance (rename FS_RNI9Q57_12 "FS_RNI9Q57[12]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) (instance PHI2r3_RNIFT0I (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(B !A)")) ) @@ -1674,22 +1684,19 @@ (instance CmdValid_r_fast (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!B A)")) ) + (instance nRCAS_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B+!A)+C B)")) + ) (instance nRCAS_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B+!A)+C !A))")) + (property lut_function (string "(!D !C+D (!C (!B !A)))")) ) (instance RA11d (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (!C (B A)+C (B !A))+D (C B))")) ) - (instance CmdLEDEN_4_u_i_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (B !A)))")) - ) - (instance un1_CmdEnable20_0_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (!C (!B A)))")) - ) - (instance (rename RowAd_7 "RowAd[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance (rename RowAd_8 "RowAd[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(B A)")) ) - (instance (rename RowAd_6 "RowAd[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance (rename RowAd_0 "RowAd[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(B A)")) ) (instance (rename RowAd_2 "RowAd[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) @@ -1701,48 +1708,54 @@ (instance (rename RowAd_4 "RowAd[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(B A)")) ) - (instance (rename RowAd_1 "RowAd[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance (rename RowAd_6 "RowAd[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(B A)")) ) (instance (rename RBAd_0 "RBAd[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(B A)")) ) - (instance (rename RBAd_1 "RBAd[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B A)")) - ) - (instance (rename RowAd_8 "RowAd[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance (rename RowAd_7 "RowAd[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(B A)")) ) (instance (rename RowAd_5 "RowAd[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!B+A)")) ) - (instance (rename RowAd_0 "RowAd[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance (rename RowAd_1 "RowAd[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename RBAd_1 "RBAd[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(B A)")) ) (instance (rename RowAd_9 "RowAd[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!B+A)")) ) - (instance (rename FS_RNIF2MA_9 "FS_RNIF2MA[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C+(!B+!A))")) + (instance IS_0_sqmuxa_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(!B+!A)))")) ) - (instance CmdLEDEN_4_u_i_0_a3_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (B !A)))")) - ) - (instance nRCS_9_u_i_0_o2_1_RNIL2K71 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C+(B+A)))")) - ) - (instance (rename FS_RNIHVJI_16 "FS_RNIHVJI[16]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C+(!B+A)))")) - ) - (instance (rename wb_adr_5_i_0_a2_1_1 "wb_adr_5_i_0_a2_1[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance Cmdn8MEGEN_4_u_i_m2_i_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D (C (B !A)))")) ) - (instance (rename wb_dati_5_1_iv_i_i_a3_0_3 "wb_dati_5_1_iv_i_i_a3_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (B A)))")) + (instance un1_CmdEnable20_0_0_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B A)))")) ) - (instance (rename wb_dati_5_1_iv_i_i_a2_4_3 "wb_dati_5_1_iv_i_i_a2_4[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance CmdLEDEN_4_u_i_m2_i_a2_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B !A)))")) + ) + (instance (rename wb_dati_5_1_iv_0_o2_0_4 "wb_dati_5_1_iv_0_o2_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C A+C (!B A+B !A))")) + ) + (instance (rename wb_dati_5_1_iv_0_a2_13_3 "wb_dati_5_1_iv_0_a2_13[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C (!B !A))")) ) + (instance nRRAS_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B !A)+C !A)+D (C !A))")) + ) + (instance IS_0_sqmuxa_0_o2_RNIDJQJ (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B !A)")) + ) + (instance (rename IS_RNO_0 "IS_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B !A+B A)+C A)")) + ) (instance CmdEnable16_0_a2_1_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D (!C (B A)))")) ) @@ -1806,12 +1819,13 @@ (property INJECT1_0 (string "NO")) (property INIT1 (string "0x300A")) ) + (instance rclk_oddr (viewRef verilog (cellRef ODDRXE)) ) (instance ufmefb (viewRef netlist (cellRef REFB)) ) (net wb_rst (joined (portRef Q (instanceRef wb_rst)) (portRef wb_rst (instanceRef ufmefb)) - (portRef C (instanceRef wb_rste)) + (portRef B (instanceRef wb_rste)) )) (net wb_cyc_stb (joined (portRef Q (instanceRef wb_cyc_stb)) @@ -1825,7 +1839,7 @@ (net (rename wb_adr_0 "wb_adr[0]") (joined (portRef Q (instanceRef wb_adr_0)) (portRef (member wb_adr 7) (instanceRef ufmefb)) - (portRef D (instanceRef wb_adr_5_i_0_m2_1)) + (portRef C (instanceRef wb_adr_5_i_3_0_m2_1)) )) (net (rename wb_adr_1 "wb_adr[1]") (joined (portRef Q (instanceRef wb_adr_1)) @@ -1840,17 +1854,17 @@ (net (rename wb_adr_3 "wb_adr[3]") (joined (portRef Q (instanceRef wb_adr_3)) (portRef (member wb_adr 4) (instanceRef ufmefb)) - (portRef D (instanceRef wb_adr_5_i_m2_i_m2_4)) + (portRef C (instanceRef wb_adr_5_i_m2_4)) )) (net (rename wb_adr_4 "wb_adr[4]") (joined (portRef Q (instanceRef wb_adr_4)) (portRef (member wb_adr 3) (instanceRef ufmefb)) - (portRef D (instanceRef wb_adr_5_i_m2_i_m2_5)) + (portRef C (instanceRef wb_adr_5_i_m2_5)) )) (net (rename wb_adr_5 "wb_adr[5]") (joined (portRef Q (instanceRef wb_adr_5)) (portRef (member wb_adr 2) (instanceRef ufmefb)) - (portRef D (instanceRef wb_adr_5_i_m2_i_m2_6)) + (portRef C (instanceRef wb_adr_5_i_m2_6)) )) (net (rename wb_adr_6 "wb_adr[6]") (joined (portRef Q (instanceRef wb_adr_6)) @@ -1864,42 +1878,42 @@ (net (rename wb_dati_0 "wb_dati[0]") (joined (portRef Q (instanceRef wb_dati_0)) (portRef (member wb_dati 7) (instanceRef ufmefb)) - (portRef D (instanceRef wb_dati_5_1_iv_0_1_1)) + (portRef C (instanceRef wb_dati_5_1_iv_0_0_1)) )) (net (rename wb_dati_1 "wb_dati[1]") (joined (portRef Q (instanceRef wb_dati_1)) (portRef (member wb_dati 6) (instanceRef ufmefb)) - (portRef C (instanceRef wb_dati_5_1_iv_0_2)) + (portRef C (instanceRef wb_dati_5_1_iv_0_0_2)) )) (net (rename wb_dati_2 "wb_dati[2]") (joined (portRef Q (instanceRef wb_dati_2)) (portRef (member wb_dati 5) (instanceRef ufmefb)) - (portRef C (instanceRef wb_dati_5_1_iv_i_i_0_3)) + (portRef C (instanceRef wb_dati_5_1_iv_0_0_0_3)) )) (net (rename wb_dati_3 "wb_dati[3]") (joined (portRef Q (instanceRef wb_dati_3)) (portRef (member wb_dati 4) (instanceRef ufmefb)) - (portRef D (instanceRef wb_dati_5_1_iv_0_1_4)) + (portRef D (instanceRef wb_dati_5_1_iv_0_0_1_4)) )) (net (rename wb_dati_4 "wb_dati[4]") (joined (portRef Q (instanceRef wb_dati_4)) (portRef (member wb_dati 3) (instanceRef ufmefb)) - (portRef C (instanceRef wb_dati_5_1_iv_0_5)) + (portRef C (instanceRef wb_dati_5_1_iv_0_0_5)) )) (net (rename wb_dati_5 "wb_dati[5]") (joined (portRef Q (instanceRef wb_dati_5)) (portRef (member wb_dati 2) (instanceRef ufmefb)) - (portRef D (instanceRef wb_dati_5_1_iv_0_1_6)) + (portRef D (instanceRef wb_dati_5_1_iv_0_0_1_6)) )) (net (rename wb_dati_6 "wb_dati[6]") (joined (portRef Q (instanceRef wb_dati_6)) (portRef (member wb_dati 1) (instanceRef ufmefb)) - (portRef C (instanceRef wb_dati_5_1_iv_0_0_7)) + (portRef D (instanceRef wb_dati_5_1_iv_0_1_7)) )) (net (rename wb_dati_7 "wb_dati[7]") (joined (portRef Q (instanceRef wb_dati_7)) (portRef (member wb_dati 0) (instanceRef ufmefb)) - (portRef D (instanceRef wb_adr_5_i_0_m2_0)) + (portRef D (instanceRef wb_adr_5_i_0_2_0)) )) (net (rename wb_dato_0 "wb_dato[0]") (joined (portRef (member wb_dato 1) (instanceRef ufmefb)) @@ -1907,63 +1921,62 @@ )) (net (rename wb_dato_1 "wb_dato[1]") (joined (portRef (member wb_dato 0) (instanceRef ufmefb)) - (portRef C (instanceRef LEDEN_6_i_m2_i_m2)) + (portRef C (instanceRef LEDEN_6_i_m2)) )) (net wb_ack (joined (portRef wb_ack (instanceRef ufmefb)) - (portRef C (instanceRef wb_cyc_stb_2_sqmuxa_i_0)) + (portRef C (instanceRef wb_cyc_stb_2_sqmuxa_i_0_0)) )) (net CBR (joined (portRef Q (instanceRef CBR)) - (portRef A (instanceRef RCKEEN_8_u_0)) - (portRef A (instanceRef RCKEEN_8_u_0_0_a2_2)) + (portRef A (instanceRef RCKEEN_8_u)) + (portRef A (instanceRef RCKEEN_8_u_0_a2_2)) + (portRef A (instanceRef nRowColSel_0_0)) (portRef A (instanceRef LED_pad_RNO)) - (portRef A (instanceRef nRowColSel_0_0_0)) - (portRef A (instanceRef nRCAS_r_i_0_o2_0_2)) + (portRef A (instanceRef nRCAS_0io_RNO_1)) )) (net InitReady (joined (portRef Q (instanceRef InitReady)) - (portRef A (instanceRef wb_adr_5_i_0_a2_1_1)) - (portRef A (instanceRef FS_RNIHVJI_16)) + (portRef B (instanceRef IS_0_sqmuxa_0_o2)) (portRef B (instanceRef n8MEGEN_RNO_0)) + (portRef D (instanceRef FS_RNIHVJI_15)) (portRef B (instanceRef CmdValid_RNIOOBE2)) (portRef D (instanceRef CmdValid_fast_RNI3K0H1)) - (portRef A (instanceRef wb_adr_5_2)) - (portRef A (instanceRef wb_adr_5_3)) + (portRef A (instanceRef wb_we_0_0_i_1_1)) + (portRef B (instanceRef wb_adr_5_i_3_0_a2_3_1)) + (portRef B (instanceRef wb_adr_5_i_0_a2_6_0)) (portRef A (instanceRef wb_adr_5_7)) - (portRef B (instanceRef wb_adr_5_i_0_a2_1_0)) - (portRef B (instanceRef wb_adr_5_i_0_a2_0_1)) - (portRef A (instanceRef nRCS_9_u_i_0_o2_1)) - (portRef B (instanceRef LEDEN_6_i_m2_i_m2)) - (portRef D (instanceRef wb_adr_5_i_0_a3_0_2_0)) - (portRef B (instanceRef wb_adr_5_i_0_m2_1)) - (portRef B (instanceRef wb_adr_5_i_0_m2_0)) - (portRef B (instanceRef wb_adr_5_i_m2_i_m2_4)) - (portRef B (instanceRef wb_adr_5_i_m2_i_m2_5)) - (portRef B (instanceRef wb_adr_5_i_m2_i_m2_6)) - (portRef A (instanceRef Ready_0_sqmuxa_0_a2_4_a3)) - (portRef C (instanceRef wb_adr_5_i_0_a3_0_1)) - (portRef B (instanceRef wb_we_0_i_0_a3_1)) - (portRef B (instanceRef CmdValid_RNIS5A51)) - (portRef A (instanceRef wb_dati_5_1_iv_0_0_7)) - (portRef A (instanceRef wb_dati_5_1_iv_i_i_0_3)) - (portRef A (instanceRef wb_dati_5_1_iv_0_1_1)) - (portRef B (instanceRef wb_cyc_stb_4_iv_0)) + (portRef A (instanceRef wb_adr_5_3)) + (portRef A (instanceRef wb_adr_5_2)) + (portRef B (instanceRef LEDEN_6_i_m2)) + (portRef C (instanceRef un1_wb_rst14_2_0_o2)) + (portRef B (instanceRef un1_InitReady_4_i_0_a2_i)) + (portRef A (instanceRef wb_adr_5_i_m2_6)) + (portRef A (instanceRef wb_adr_5_i_m2_5)) + (portRef A (instanceRef wb_adr_5_i_m2_4)) + (portRef A (instanceRef wb_adr_5_i_3_0_m2_1)) + (portRef A (instanceRef Ready_0_sqmuxa_0_a2)) + (portRef C (instanceRef wb_adr_5_i_3_0_a2_0_1)) + (portRef A (instanceRef wb_dati_5_1_iv_0_0_1)) + (portRef A (instanceRef wb_adr_5_i_0_2_0)) + (portRef A (instanceRef wb_dati_5_1_iv_0_0_0_3)) + (portRef B (instanceRef wb_cyc_stb_4_iv_0_0)) (portRef A (instanceRef wb_dati_5_0_iv_0_0)) - (portRef A (instanceRef wb_dati_5_1_iv_0_1_4)) - (portRef A (instanceRef wb_dati_5_1_iv_0_1_6)) + (portRef A (instanceRef wb_dati_5_1_iv_0_0_1_4)) + (portRef A (instanceRef wb_dati_5_1_iv_0_1_7)) + (portRef A (instanceRef wb_dati_5_1_iv_0_0_1_6)) (portRef B (instanceRef wb_we_RNO)) - (portRef A (instanceRef wb_dati_5_1_iv_0_5)) - (portRef A (instanceRef wb_dati_5_1_iv_0_2)) + (portRef A (instanceRef wb_dati_5_1_iv_0_0_2)) + (portRef A (instanceRef wb_dati_5_1_iv_0_0_5)) (portRef B (instanceRef InitReady_RNO)) + (portRef D (instanceRef wb_adr_5_i_0_1_am_0)) (portRef D (instanceRef Ready_RNO)) - (portRef B (instanceRef wb_reqe_RNO)) - (portRef B (instanceRef wb_we_0_i_0_1_RNO)) - (portRef C (instanceRef RCKEEN_8_u_0_0_0)) - (portRef D (instanceRef un1_nRCAS_6_sqmuxa_i_0_0_o2_0_RNIQVER)) - (portRef B (instanceRef FS_RNIJO0F_14)) - (portRef A (instanceRef FS_RNIHVJI_0_16)) - (portRef B (instanceRef wb_we_0_i_0_0_RNO)) + (portRef C (instanceRef RCKEEN_8_u_RNO)) + (portRef C (instanceRef wb_adr_5_i_0_2_RNO_0)) + (portRef B (instanceRef FS_RNIHVJI_0_15)) + (portRef A (instanceRef FS_RNIOVGI_9)) + (portRef C (instanceRef wb_adr_5_i_0_2_RNO_0_0)) + (portRef B (instanceRef FS_RNIJO0F_12)) )) (net C1Submitted (joined (portRef Q (instanceRef C1Submitted)) @@ -1977,358 +1990,345 @@ )) (net (rename Bank_2 "Bank[2]") (joined (portRef Q (instanceRef Bank_0io_2)) - (portRef B (instanceRef un1_CmdEnable20_0_0_o3_10)) + (portRef A (instanceRef un1_CmdEnable20_0_0_o2_11)) )) (net Ready (joined (portRef Q (instanceRef Ready)) - (portRef A (instanceRef nRCS_9_u_i_0_o2_1_RNIL2K71)) + (portRef B (instanceRef IS_RNO_0)) + (portRef A (instanceRef IS_0_sqmuxa_0_o2_RNIDJQJ)) (portRef C (instanceRef CBR_fast_RNIQ31K1)) - (portRef D (instanceRef RCKEEN_8_u_0)) - (portRef B (instanceRef RCKEEN_8_u_0_0_a2_2)) - (portRef D (instanceRef nRowColSel_0_0_0)) - (portRef C (instanceRef Ready_0_sqmuxa_0_a2_4_a3)) - (portRef C (instanceRef un1_nRCAS_6_sqmuxa_i_0_0)) - (portRef D (instanceRef nRCS_9_u_i_0_o2_1_RNIL2K71_0)) + (portRef D (instanceRef RCKEEN_8_u)) + (portRef B (instanceRef RCKEEN_8_u_0_a2_2)) + (portRef D (instanceRef nRowColSel_0_0)) + (portRef D (instanceRef nRCS_9_u_i_0_0)) + (portRef C (instanceRef Ready_0_sqmuxa_0_a2)) + (portRef C (instanceRef LED_pad_RNO)) + (portRef B (instanceRef IS_0_sqmuxa_0_o3)) + (portRef C (instanceRef un1_nRCAS_6_sqmuxa_i_0)) (portRef A (instanceRef Ready_RNO)) - (portRef A (instanceRef RCKEEN_8_u_0_0_0)) - (portRef A (instanceRef un1_nRCAS_6_sqmuxa_i_0_0_o2_0_RNIQVER)) - (portRef A (instanceRef Ready_RNICVV51)) + (portRef A (instanceRef RCKEEN_8_u_RNO)) + (portRef A (instanceRef S_RNICVV51_1)) )) (net n8MEGEN (joined (portRef Q (instanceRef n8MEGEN)) (portRef D (instanceRef RA11d)) - (portRef B (instanceRef n8MEGEN_RNO)) + (portRef A (instanceRef n8MEGEN_RNO)) (portRef C (instanceRef Cmdn8MEGEN_RNO)) )) (net CO0 (joined (portRef Q (instanceRef S_0)) - (portRef D (instanceRef nRCS_9_u_i_0_o2_1_RNIL2K71)) + (portRef D (instanceRef IS_0_sqmuxa_0_o2)) (portRef B (instanceRef CBR_fast_RNIQ31K1)) - (portRef B (instanceRef RCKEEN_8_u_0_1_0)) - (portRef A (instanceRef nRowColSel_0_0_0_x2)) - (portRef B (instanceRef RCKEEN_8_u_0_0_o2)) - (portRef A (instanceRef S_0_i_o2_i_o2_1)) - (portRef A (instanceRef nRCAS_r_i_0_a2)) - (portRef A (instanceRef Ready_0_sqmuxa_0_a2_4_a3_2)) + (portRef B (instanceRef RCKEEN_8_u_1)) + (portRef A (instanceRef nRowColSel_0_0_x2)) + (portRef B (instanceRef RCKEEN_8_u_0_o3)) + (portRef A (instanceRef S_0_i_o3_1)) + (portRef A (instanceRef nRCS_9_u_i_a2_0)) + (portRef A (instanceRef Ready_0_sqmuxa_0_a2_2)) (portRef A (instanceRef S_RNO_0)) - (portRef C (instanceRef nRWE_s_i_0_a2)) - (portRef A (instanceRef un1_nRCAS_6_sqmuxa_i_0_0)) - (portRef A (instanceRef nRCS_9_u_i_0_o2_1_RNIL2K71_0)) - (portRef B (instanceRef nRCAS_r_i_0_o2_0_2_RNO)) - (portRef C (instanceRef Ready_RNICVV51)) - (portRef D (instanceRef nRCAS_0io_RNO_0)) + (portRef C (instanceRef nRWE_s_i_a2_2)) + (portRef B (instanceRef nRCAS_0io_RNO_2)) + (portRef C (instanceRef S_RNICVV51_1)) )) (net (rename S_1 "S[1]") (joined (portRef Q (instanceRef S_1)) - (portRef C (instanceRef nRCS_9_u_i_0_o2_1_RNIL2K71)) + (portRef C (instanceRef IS_0_sqmuxa_0_o2)) + (portRef C (instanceRef nRCAS_0io_RNO_0)) (portRef B (instanceRef RASr2_RNI6PUF)) - (portRef D (instanceRef RCKEEN_8_u_0_1_0)) - (portRef B (instanceRef nRowColSel_0_0_0_x2)) - (portRef B (instanceRef S_0_i_o2_i_o2_1)) - (portRef D (instanceRef Ready_0_sqmuxa_0_a2_4_a3_2)) - (portRef C (instanceRef RCKEEN_8_u_0_0_a2_2)) + (portRef D (instanceRef RCKEEN_8_u_1)) + (portRef B (instanceRef nRowColSel_0_0_x2)) + (portRef B (instanceRef S_0_i_o3_1)) + (portRef D (instanceRef Ready_0_sqmuxa_0_a2_2)) + (portRef C (instanceRef RCKEEN_8_u_0_a2_2)) (portRef B (instanceRef S_RNO_0)) - (portRef D (instanceRef un1_nRCAS_6_sqmuxa_i_0_0)) - (portRef B (instanceRef nRCS_9_u_i_0_o2_1_RNIL2K71_0)) - (portRef B (instanceRef Ready_RNICVV51)) - (portRef A (instanceRef nRCAS_0io_RNO_0)) + (portRef D (instanceRef un1_nRCAS_6_sqmuxa_i_0)) + (portRef B (instanceRef S_RNICVV51_1)) )) (net RASr2 (joined (portRef Q (instanceRef RASr2)) + (portRef A (instanceRef IS_0_sqmuxa_0_o2)) (portRef A (instanceRef RASr2_RNI6PUF)) - (portRef B (instanceRef nRCS_9_u_i_0_o2_1)) - (portRef C (instanceRef Ready_0_sqmuxa_0_a2_4_a3_2)) - (portRef B (instanceRef RCKE_2_0_0)) - (portRef B (instanceRef nRCS_9_u_i_0_o3)) - (portRef A (instanceRef nRWE_s_i_0_tz_0)) + (portRef C (instanceRef Ready_0_sqmuxa_0_a2_2)) + (portRef B (instanceRef RCKE_2_0)) + (portRef B (instanceRef nRCS_9_u_i_0_0)) + (portRef A (instanceRef nRWE_s_i_tz_0)) (portRef D (instanceRef RASr3)) - (portRef C (instanceRef nRRAS_0io_RNO)) - (portRef B (instanceRef RCKEEN_8_u_0_0_0)) - (portRef C (instanceRef un1_nRCAS_6_sqmuxa_i_0_0_o2_0_RNIQVER)) + (portRef B (instanceRef RCKEEN_8_u_RNO)) (portRef A (instanceRef RASr2_RNIAFR1)) )) (net (rename FS_14 "FS[14]") (joined (portRef Q (instanceRef FS_14)) (portRef (member fs 0) (instanceRef ufmefb)) (portRef A1 (instanceRef FS_cry_0_13)) - (portRef C (instanceRef wb_dati_5_1_iv_i_i_a2_4_3)) - (portRef C (instanceRef FS_RNIGOCT_14)) + (portRef C (instanceRef wb_dati_5_1_iv_0_a2_13_3)) + (portRef C (instanceRef FS_RNIGOCT_12)) (portRef A (instanceRef FS_RNI7U6M_14)) - (portRef A (instanceRef wb_adr_5_i_0_a2_1_0)) - (portRef A (instanceRef wb_adr_5_i_0_a2_0_1)) - (portRef B (instanceRef wb_dati_5_1_iv_0_a2_6)) - (portRef C (instanceRef FS_RNIVOOA_14)) - (portRef C (instanceRef wb_dati_5_0_iv_0_a3_1_0)) - (portRef D (instanceRef wb_dati_5_1_iv_i_i_o2_3)) - (portRef B (instanceRef wb_adr_5_i_0_a3_0_1)) - (portRef C (instanceRef wb_adr_5_i_0_a3_1)) - (portRef D (instanceRef wb_dati_5_1_iv_0_o2_7)) - (portRef C (instanceRef wb_we_0_i_0_1_RNO)) - (portRef C (instanceRef FS_RNIJO0F_14)) - (portRef C (instanceRef wb_we_0_i_0_0_RNO)) + (portRef B (instanceRef InitReady3_0_a2)) + (portRef B (instanceRef wb_dati_5_1_iv_0_a2_7_4)) + (portRef A (instanceRef wb_adr_5_i_3_0_a2_3_1)) + (portRef A (instanceRef wb_adr_5_i_0_a2_6_0)) + (portRef C (instanceRef wb_dati_5_0_iv_0_a2_1_0)) + (portRef D (instanceRef wb_dati_5_1_iv_0_0_o2_3)) + (portRef B (instanceRef wb_adr_5_i_3_0_a2_0_1)) + (portRef C (instanceRef wb_adr_5_i_3_0_a2_1)) + (portRef A (instanceRef wb_dati_5_1_iv_0_o2_7)) + (portRef B (instanceRef wb_reqe_RNO)) + (portRef D (instanceRef wb_adr_5_i_0_2_RNO_0)) + (portRef D (instanceRef wb_adr_5_i_0_2_RNO_0_0)) + (portRef C (instanceRef FS_RNIJO0F_12)) + (portRef B (instanceRef wb_dati_5_1_iv_0_a2_0_RNO_7)) )) (net FWEr (joined (portRef Q (instanceRef FWEr)) - (portRef C (instanceRef RCKEEN_8_u_0_1_0)) - (portRef B (instanceRef nRowColSel_0_0_0_a2)) - (portRef B (instanceRef nRCAS_r_i_0_a2)) - (portRef D (instanceRef nRWE_s_i_0_a2)) - (portRef B (instanceRef nRCAS_r_i_0_o2_0_2)) + (portRef C (instanceRef RCKEEN_8_u_1)) + (portRef B (instanceRef nRowColSel_0_0_a2_1)) + (portRef B (instanceRef nRCS_9_u_i_a2_0)) + (portRef D (instanceRef nRWE_s_i_a2_2)) + (portRef B (instanceRef nRCAS_0io_RNO_1)) )) (net CASr3 (joined (portRef Q (instanceRef CASr3)) - (portRef A (instanceRef nRowColSel_0_0_0_a2)) - (portRef B (instanceRef nRWE_s_i_0_a2)) + (portRef A (instanceRef nRowColSel_0_0_a2_1)) + (portRef B (instanceRef nRWE_s_i_a2_2)) )) (net (rename IS_0 "IS[0]") (joined (portRef Q (instanceRef IS_0)) - (portRef A (instanceRef IS_n1_0_x2_0_x2)) - (portRef A (instanceRef Ready_0_sqmuxa_0_a2_4_o2)) - (portRef A (instanceRef IS_RNO_2)) - (portRef A (instanceRef nRCS_9_u_i_0_a2)) - (portRef A (instanceRef nRWE_s_i_0_a3_1_0)) (portRef A (instanceRef IS_RNO_0)) + (portRef D (instanceRef nRRAS_0io_RNO)) + (portRef A (instanceRef IS_n1_0_x2)) + (portRef A (instanceRef Ready_0_sqmuxa_0_o2)) + (portRef A (instanceRef IS_RNO_2)) + (portRef A (instanceRef nRCS_9_u_i_0)) + (portRef A (instanceRef nRWE_s_i_a2_1_0)) (portRef D (instanceRef IS_RNO_3)) (portRef A (instanceRef RA10_0io_RNO)) )) (net (rename IS_3 "IS[3]") (joined (portRef Q (instanceRef IS_3)) - (portRef B (instanceRef Ready_0_sqmuxa_0_a2_4_a3_2)) - (portRef C (instanceRef un1_nRCAS_6_sqmuxa_i_0_0_o2_0)) + (portRef B (instanceRef Ready_0_sqmuxa_0_a2_2)) + (portRef C (instanceRef un1_nRCAS_6_sqmuxa_i_o2)) (portRef C (instanceRef RA10_0io_RNO_0)) (portRef A (instanceRef IS_RNO_3)) )) (net (rename IS_1 "IS[1]") (joined (portRef Q (instanceRef IS_1)) - (portRef B (instanceRef IS_n1_0_x2_0_x2)) - (portRef B (instanceRef Ready_0_sqmuxa_0_a2_4_o2)) - (portRef A (instanceRef un1_nRCAS_6_sqmuxa_i_0_0_o2_0)) + (portRef B (instanceRef IS_n1_0_x2)) + (portRef B (instanceRef Ready_0_sqmuxa_0_o2)) + (portRef A (instanceRef un1_nRCAS_6_sqmuxa_i_o2)) (portRef B (instanceRef IS_RNO_2)) - (portRef B (instanceRef nRWE_s_i_0_a3_1_0)) + (portRef B (instanceRef nRWE_s_i_a2_1_0)) (portRef A (instanceRef RA10_0io_RNO_0)) (portRef C (instanceRef IS_RNO_3)) )) (net (rename IS_2 "IS[2]") (joined (portRef Q (instanceRef IS_2)) - (portRef C (instanceRef Ready_0_sqmuxa_0_a2_4_o2)) - (portRef B (instanceRef un1_nRCAS_6_sqmuxa_i_0_0_o2_0)) + (portRef C (instanceRef Ready_0_sqmuxa_0_o2)) + (portRef B (instanceRef un1_nRCAS_6_sqmuxa_i_o2)) (portRef C (instanceRef IS_RNO_2)) - (portRef C (instanceRef nRWE_s_i_0_a3_1_0)) + (portRef C (instanceRef nRWE_s_i_a2_1_0)) (portRef B (instanceRef RA10_0io_RNO_0)) (portRef B (instanceRef IS_RNO_3)) )) (net (rename FS_15 "FS[15]") (joined (portRef Q (instanceRef FS_15)) (portRef A0 (instanceRef FS_cry_0_15)) - (portRef B (instanceRef FS_RNIHVJI_16)) - (portRef A (instanceRef InitReady3_0_a3_1)) - (portRef A (instanceRef wb_adr_5_i_0_m2_1)) - (portRef A (instanceRef wb_adr_5_i_0_m2_0)) - (portRef A (instanceRef wb_adr_5_i_m2_i_m2_4)) - (portRef A (instanceRef wb_adr_5_i_m2_i_m2_5)) - (portRef A (instanceRef wb_adr_5_i_m2_i_m2_6)) - (portRef B (instanceRef FS_RNIHVJI_0_16)) + (portRef A (instanceRef FS_RNIHVJI_15)) + (portRef A (instanceRef FS_RNI82PA_15)) + (portRef B (instanceRef InitReady3_0_a2_1_0)) + (portRef A (instanceRef wb_rst_3_0_a2_0_a2)) + (portRef A (instanceRef FS_RNIHVJI_0_15)) )) (net (rename FS_16 "FS[16]") (joined (portRef Q (instanceRef FS_16)) (portRef A1 (instanceRef FS_cry_0_15)) - (portRef D (instanceRef FS_RNIHVJI_16)) - (portRef A (instanceRef FS_RNIH267_16)) - (portRef B (instanceRef InitReady3_0_a3_1)) - (portRef D (instanceRef wb_reqe_RNO)) - (portRef D (instanceRef FS_RNIHVJI_0_16)) + (portRef B (instanceRef FS_RNIHVJI_15)) + (portRef B (instanceRef FS_RNI82PA_15)) + (portRef C (instanceRef InitReady3_0_a2_1_0)) + (portRef A (instanceRef un1_wb_rst14_2_0_o2)) + (portRef B (instanceRef wb_rst_3_0_a2_0_a2)) + (portRef D (instanceRef FS_RNIHVJI_0_15)) )) (net (rename FS_17 "FS[17]") (joined (portRef Q (instanceRef FS_17)) (portRef A0 (instanceRef FS_s_0_17)) - (portRef C (instanceRef FS_RNIHVJI_16)) - (portRef B (instanceRef FS_RNIH267_16)) - (portRef C (instanceRef InitReady3_0_a3_1)) - (portRef C (instanceRef wb_reqe_RNO)) - (portRef C (instanceRef FS_RNIHVJI_0_16)) + (portRef C (instanceRef FS_RNIHVJI_15)) + (portRef C (instanceRef FS_RNI82PA_15)) + (portRef D (instanceRef InitReady3_0_a2_1_0)) + (portRef B (instanceRef un1_wb_rst14_2_0_o2)) + (portRef C (instanceRef wb_rst_3_0_a2_0_a2)) + (portRef C (instanceRef FS_RNIHVJI_0_15)) )) (net (rename FS_0 "FS[0]") (joined (portRef Q (instanceRef FS_0)) (portRef A1 (instanceRef FS_cry_0_0)) - (portRef A (instanceRef wb_cyc_stb_4_iv_0_a3_0_0)) - (portRef A (instanceRef wb_cyc_stb_2_sqmuxa_i_a3_0)) - )) - (net (rename FS_1 "FS[1]") (joined - (portRef Q (instanceRef FS_1)) - (portRef A0 (instanceRef FS_cry_0_1)) - (portRef A (instanceRef wb_cyc_stb_4_iv_0_a3_0_3)) - )) - (net (rename FS_5 "FS[5]") (joined - (portRef Q (instanceRef FS_5)) - (portRef A0 (instanceRef FS_cry_0_5)) - (portRef B (instanceRef wb_cyc_stb_4_iv_0_a3_0_3)) - )) - (net (rename FS_8 "FS[8]") (joined - (portRef Q (instanceRef FS_8)) - (portRef A1 (instanceRef FS_cry_0_7)) - (portRef C (instanceRef wb_cyc_stb_4_iv_0_a3_0_3)) + (portRef A (instanceRef wb_cyc_stb_4_iv_0_0_a2_0_0)) + (portRef A (instanceRef wb_cyc_stb_2_sqmuxa_i_0_0_a2_0)) )) (net (rename FS_7 "FS[7]") (joined (portRef Q (instanceRef FS_7)) (portRef A0 (instanceRef FS_cry_0_7)) - (portRef C (instanceRef wb_cyc_stb_4_iv_0_a3_0_2)) + (portRef B (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_2_0)) )) - (net (rename FS_4 "FS[4]") (joined - (portRef Q (instanceRef FS_4)) - (portRef A1 (instanceRef FS_cry_0_3)) - (portRef B (instanceRef wb_cyc_stb_4_iv_0_a3_0_2_0)) - )) - (net (rename FS_2 "FS[2]") (joined - (portRef Q (instanceRef FS_2)) - (portRef A1 (instanceRef FS_cry_0_1)) - (portRef A (instanceRef wb_cyc_stb_4_iv_0_a3_0_2)) + (net (rename FS_8 "FS[8]") (joined + (portRef Q (instanceRef FS_8)) + (portRef A1 (instanceRef FS_cry_0_7)) + (portRef C (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_1)) )) (net (rename FS_6 "FS[6]") (joined (portRef Q (instanceRef FS_6)) (portRef A1 (instanceRef FS_cry_0_5)) - (portRef B (instanceRef wb_cyc_stb_4_iv_0_a3_0_2)) + (portRef B (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_1)) + )) + (net (rename FS_2 "FS[2]") (joined + (portRef Q (instanceRef FS_2)) + (portRef A1 (instanceRef FS_cry_0_1)) + (portRef A (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_2)) + )) + (net (rename FS_1 "FS[1]") (joined + (portRef Q (instanceRef FS_1)) + (portRef A0 (instanceRef FS_cry_0_1)) + (portRef A (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_2_0)) + )) + (net (rename FS_4 "FS[4]") (joined + (portRef Q (instanceRef FS_4)) + (portRef A1 (instanceRef FS_cry_0_3)) + (portRef B (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_2)) + )) + (net (rename FS_5 "FS[5]") (joined + (portRef Q (instanceRef FS_5)) + (portRef A0 (instanceRef FS_cry_0_5)) + (portRef C (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_2)) )) (net (rename FS_3 "FS[3]") (joined (portRef Q (instanceRef FS_3)) (portRef A0 (instanceRef FS_cry_0_3)) - (portRef A (instanceRef wb_cyc_stb_4_iv_0_a3_0_2_0)) + (portRef A (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_1)) )) (net PHI2r2 (joined (portRef Q (instanceRef PHI2r2)) (portRef A (instanceRef PHI2r3_RNIFT0I)) - (portRef B (instanceRef wb_cyc_stb_4_iv_0_RNO)) + (portRef B (instanceRef wb_cyc_stb_4_iv_0_0_RNO)) (portRef A (instanceRef PHI2r3_RNIFT0I_0)) - (portRef C (instanceRef CmdValid_RNIS5A51)) + (portRef C (instanceRef un1_InitReady_4_i_0_a2_i)) (portRef D (instanceRef PHI2r3)) )) (net (rename FS_9 "FS[9]") (joined (portRef Q (instanceRef FS_9)) (portRef A0 (instanceRef FS_cry_0_9)) - (portRef D (instanceRef wb_dati_5_1_iv_i_i_a3_0_3)) - (portRef B (instanceRef wb_adr_5_i_0_a2_1_1)) - (portRef C (instanceRef FS_RNIF2MA_9)) - (portRef A (instanceRef wb_dati_5_1_iv_0_4)) + (portRef C (instanceRef wb_dati_5_1_iv_0_o2_0_4)) + (portRef A (instanceRef FS_RNIS637_9)) + (portRef A (instanceRef FS_RNIF2MA_9)) (portRef A (instanceRef wb_dati_5_1_iv_0_0_4)) + (portRef A (instanceRef wb_dati_5_1_iv_0_1_0_4)) (portRef A (instanceRef wb_dati_5_1_iv_0_o2_0_7)) - (portRef A (instanceRef wb_adr_5_i_0_o2_1)) - (portRef A (instanceRef wb_dati_5_1_iv_i_i_a3_1_1_3)) - (portRef A (instanceRef wb_adr_5_i_0_o2_0_0)) - (portRef A (instanceRef wb_dati_5_1_iv_0_a3_0_1_7)) - (portRef A (instanceRef wb_adr_5_i_0_1_0)) - (portRef A (instanceRef wb_dati_5_1_iv_i_i_a2_3_3)) + (portRef A (instanceRef wb_dati_5_1_iv_0_0_a2_1_3)) + (portRef A (instanceRef wb_adr_5_i_0_o2_0)) + (portRef A (instanceRef wb_dati_5_1_iv_0_a2_0_7)) + (portRef A (instanceRef wb_dati_5_1_iv_0_a2_12_3)) (portRef A (instanceRef wb_adr_5_i_0_3_0)) - (portRef C0 (instanceRef wb_dati_5_1_iv_0_o3_5)) + (portRef C0 (instanceRef wb_dati_5_1_iv_0_0_o2_5)) + (portRef B (instanceRef wb_adr_5_i_0_1_am_0)) (portRef D (instanceRef wb_dati_5_1_iv_0_RNO_7)) - (portRef D (instanceRef wb_dati_5_1_iv_0_RNO_0_7)) - (portRef D (instanceRef wb_dati_5_1_iv_i_i_0_RNO_3)) - (portRef C (instanceRef wb_dati_5_1_iv_i_i_1_RNO_3)) - (portRef D (instanceRef wb_dati_5_1_iv_0_a3_0_RNO_1)) + (portRef D (instanceRef wb_dati_5_1_iv_0_1_RNO_7)) + (portRef D (instanceRef FS_RNIOVGI_9)) )) (net (rename FS_10 "FS[10]") (joined (portRef Q (instanceRef FS_10)) (portRef A1 (instanceRef FS_cry_0_9)) - (portRef C (instanceRef wb_adr_5_i_0_a2_1_1)) + (portRef B (instanceRef wb_dati_5_1_iv_0_o2_0_4)) + (portRef B (instanceRef FS_RNIS637_9)) (portRef B (instanceRef FS_RNIF2MA_9)) - (portRef B (instanceRef wb_dati_5_1_iv_0_0_4)) + (portRef B (instanceRef wb_dati_5_1_iv_0_1_0_4)) + (portRef A (instanceRef InitReady3_0_a2_1_0)) (portRef B (instanceRef wb_dati_5_1_iv_0_o2_0_7)) - (portRef B (instanceRef wb_adr_5_i_0_o2_1)) - (portRef B (instanceRef wb_dati_5_1_iv_i_i_a3_1_1_3)) - (portRef B (instanceRef wb_adr_5_i_0_o2_0_0)) - (portRef A (instanceRef wb_dati_5_0_iv_0_a3_1_0)) - (portRef B (instanceRef wb_dati_5_1_iv_0_a3_0_1_7)) - (portRef A (instanceRef wb_dati_5_1_iv_i_i_o2_3)) - (portRef A (instanceRef wb_adr_5_i_0_o2_0)) - (portRef B (instanceRef wb_adr_5_i_0_1_0)) - (portRef A (instanceRef InitReady3_0_a3)) - (portRef A (instanceRef wb_dati_5_1_iv_0_a3_0_6)) - (portRef A (instanceRef wb_dati_5_1_iv_0_o2_7)) - (portRef A (instanceRef wb_dati_5_1_iv_0_a3_3_7)) + (portRef B (instanceRef wb_dati_5_1_iv_0_0_a2_1_3)) + (portRef B (instanceRef wb_adr_5_i_0_o2_0)) + (portRef A (instanceRef wb_dati_5_1_iv_0_a2_5_7)) + (portRef A (instanceRef wb_dati_5_0_iv_0_a2_1_0)) + (portRef A (instanceRef wb_dati_5_1_iv_0_0_o2_3)) + (portRef A (instanceRef wb_dati_5_1_iv_0_0_o2_4)) + (portRef B (instanceRef wb_dati_5_1_iv_0_a2_0_7)) + (portRef A (instanceRef wb_dati_5_1_iv_0_a2_2_4)) + (portRef A (instanceRef wb_adr_5_i_0_1_am_0)) (portRef C (instanceRef wb_dati_5_1_iv_0_RNO_7)) - (portRef C (instanceRef wb_dati_5_1_iv_i_i_0_RNO_3)) - (portRef B (instanceRef wb_dati_5_1_iv_i_i_1_RNO_3)) - (portRef C (instanceRef wb_dati_5_1_iv_0_a3_0_RNO_1)) + (portRef C (instanceRef FS_RNIOVGI_9)) )) (net (rename FS_11 "FS[11]") (joined (portRef Q (instanceRef FS_11)) (portRef A0 (instanceRef FS_cry_0_11)) - (portRef D (instanceRef wb_adr_5_i_0_a2_1_1)) - (portRef A (instanceRef FS_RNIF2MA_9)) - (portRef A (instanceRef wb_dati_5_0_iv_0_a2_0)) - (portRef C (instanceRef wb_dati_5_1_iv_i_i_a3_1_1_3)) - (portRef A (instanceRef wb_adr_5_i_0_a3_0_2_0)) - (portRef C (instanceRef wb_adr_5_i_0_o2_0_0)) - (portRef A (instanceRef wb_adr_5_i_0_a3_4_0)) - (portRef B (instanceRef wb_dati_5_1_iv_i_i_o2_3)) - (portRef B (instanceRef wb_adr_5_i_0_o2_0)) - (portRef B (instanceRef InitReady3_0_a3)) - (portRef A (instanceRef wb_we_0_i_0_a3_1)) - (portRef A (instanceRef wb_dati_5_1_iv_0_a3_4)) - (portRef B (instanceRef wb_dati_5_1_iv_0_o2_7)) - (portRef A (instanceRef wb_dati_5_1_iv_0_a3_6)) - (portRef B (instanceRef wb_dati_5_1_iv_0_a3_3_7)) + (portRef A (instanceRef wb_dati_5_1_iv_0_o2_0_4)) + (portRef C (instanceRef FS_RNIF2MA_9)) + (portRef A (instanceRef InitReady3_0_a2)) + (portRef A (instanceRef wb_dati_5_1_iv_0_a2_6_4)) + (portRef C (instanceRef wb_dati_5_1_iv_0_0_a2_1_3)) + (portRef C (instanceRef wb_adr_5_i_0_o2_0)) + (portRef B (instanceRef wb_dati_5_1_iv_0_a2_5_7)) + (portRef A (instanceRef wb_dati_5_1_iv_0_a2_0_2_1)) + (portRef B (instanceRef wb_dati_5_1_iv_0_0_o2_3)) + (portRef B (instanceRef wb_dati_5_1_iv_0_0_o2_4)) + (portRef A (instanceRef wb_dati_5_1_iv_0_a2_7_3)) + (portRef A (instanceRef wb_dati_5_1_iv_0_a2_5_3)) + (portRef A (instanceRef wb_dati_5_1_iv_0_0_a2_6)) (portRef A (instanceRef wb_dati_5_1_iv_0_1)) - (portRef A (instanceRef wb_dati_5_1_iv_0_6)) + (portRef A (instanceRef wb_dati_5_1_iv_0_0_6)) + (portRef C0 (instanceRef wb_adr_5_i_0_1_0)) (portRef B (instanceRef wb_dati_5_1_iv_0_RNO_7)) (portRef C (instanceRef wb_adr_RNO_0_1)) - (portRef B (instanceRef wb_dati_5_1_iv_i_i_0_RNO_3)) - (portRef A (instanceRef wb_dati_5_1_iv_i_i_1_RNO_3)) - (portRef B (instanceRef wb_dati_5_1_iv_0_a3_0_RNO_1)) + (portRef B (instanceRef FS_RNIOVGI_9)) )) (net (rename FS_12 "FS[12]") (joined (portRef Q (instanceRef FS_12)) (portRef (member fs 2) (instanceRef ufmefb)) (portRef A1 (instanceRef FS_cry_0_11)) - (portRef A (instanceRef wb_dati_5_1_iv_i_i_a2_4_3)) - (portRef A (instanceRef FS_RNIGOCT_14)) - (portRef A (instanceRef wb_dati_5_1_iv_i_i_a2_2_3)) - (portRef A (instanceRef wb_dati_5_1_iv_0_a2_6)) - (portRef B (instanceRef wb_adr_5_i_0_a3_0_2_0)) - (portRef A (instanceRef FS_RNIVOOA_14)) - (portRef B (instanceRef wb_dati_5_0_iv_0_a3_1_0)) - (portRef C (instanceRef wb_dati_5_1_iv_i_i_o2_3)) - (portRef A (instanceRef wb_adr_5_i_0_0_0)) - (portRef A (instanceRef wb_adr_5_i_0_a3_1)) - (portRef A (instanceRef wb_we_0_i_0_0)) - (portRef A (instanceRef wb_we_0_i_0_1)) - (portRef D (instanceRef wb_dati_5_1_iv_0_o3_bm_5)) - (portRef B (instanceRef wb_dati_5_1_iv_0_RNO_0_7)) - (portRef C (instanceRef wb_adr_RNO_0_0)) + (portRef A (instanceRef wb_dati_5_1_iv_0_a2_13_3)) + (portRef A (instanceRef FS_RNI9Q57_12)) + (portRef A (instanceRef FS_RNIGOCT_12)) + (portRef A (instanceRef wb_dati_5_1_iv_0_a2_7_4)) + (portRef A (instanceRef wb_dati_5_1_iv_0_a2_11_3)) + (portRef B (instanceRef wb_dati_5_0_iv_0_a2_1_0)) + (portRef A (instanceRef wb_we_0_0_i_a2_0)) + (portRef C (instanceRef wb_dati_5_1_iv_0_0_o2_3)) + (portRef A (instanceRef wb_adr_5_i_3_0_a2_1)) + (portRef B (instanceRef wb_dati_5_1_iv_0_a2_7_3)) + (portRef D (instanceRef wb_dati_5_1_iv_0_0_o2_bm_5)) + (portRef B (instanceRef wb_dati_5_1_iv_0_1_RNO_7)) + (portRef D (instanceRef wb_dati_5_1_iv_0_o2_0_RNIMDJC1_4)) + (portRef D (instanceRef wb_reqe_RNO)) (portRef D (instanceRef wb_adr_RNO_0_1)) - (portRef A (instanceRef wb_dati_5_1_iv_i_i_0_RNO_3)) - (portRef A (instanceRef FS_RNIJO0F_14)) + (portRef A (instanceRef FS_RNIJO0F_12)) + (portRef C (instanceRef wb_dati_5_1_iv_0_a2_0_RNO_7)) )) (net (rename FS_13 "FS[13]") (joined (portRef Q (instanceRef FS_13)) (portRef (member fs 1) (instanceRef ufmefb)) (portRef A0 (instanceRef FS_cry_0_13)) - (portRef B (instanceRef wb_dati_5_1_iv_i_i_a3_0_3)) - (portRef B (instanceRef FS_RNIGOCT_14)) - (portRef B (instanceRef wb_dati_5_1_iv_i_i_a2_2_3)) - (portRef B (instanceRef wb_dati_5_0_iv_0_a2_0)) - (portRef D (instanceRef wb_dati_5_1_iv_i_i_a3_1_1_3)) - (portRef C (instanceRef wb_adr_5_i_0_a3_0_2_0)) - (portRef B (instanceRef FS_RNIVOOA_14)) - (portRef B (instanceRef wb_adr_5_i_0_a3_4_0)) - (portRef C (instanceRef wb_adr_5_i_0_o2_0)) - (portRef B (instanceRef wb_adr_5_i_0_0_0)) - (portRef A (instanceRef wb_adr_5_i_0_a3_0_1)) - (portRef B (instanceRef wb_adr_5_i_0_a3_1)) - (portRef C (instanceRef wb_dati_5_1_iv_0_o2_7)) - (portRef B (instanceRef wb_we_0_i_0_1)) - (portRef B (instanceRef wb_dati_5_1_iv_0_a3_6)) - (portRef C (instanceRef wb_dati_5_1_iv_0_a3_3_7)) - (portRef D (instanceRef wb_dati_5_1_iv_0_o3_am_5)) - (portRef B (instanceRef wb_adr_RNO_0_0)) - (portRef A (instanceRef wb_we_0_i_0_0_RNO)) - (portRef A (instanceRef wb_dati_5_1_iv_0_a3_0_RNO_1)) + (portRef B (instanceRef FS_RNI9Q57_12)) + (portRef B (instanceRef FS_RNIGOCT_12)) + (portRef B (instanceRef wb_dati_5_1_iv_0_a2_11_3)) + (portRef B (instanceRef wb_dati_5_1_iv_0_a2_6_4)) + (portRef D (instanceRef wb_dati_5_1_iv_0_0_a2_1_3)) + (portRef C (instanceRef wb_dati_5_1_iv_0_a2_5_7)) + (portRef B (instanceRef wb_dati_5_1_iv_0_a2_0_2_1)) + (portRef B (instanceRef wb_we_0_0_i_a2_0)) + (portRef C (instanceRef wb_dati_5_1_iv_0_0_o2_4)) + (portRef A (instanceRef wb_adr_5_i_3_0_a2_0_1)) + (portRef B (instanceRef wb_adr_5_i_3_0_a2_1)) + (portRef A (instanceRef wb_dati_5_1_iv_0_0_1_3)) + (portRef A (instanceRef wb_dati_5_1_iv_0_1_1)) + (portRef B (instanceRef wb_dati_5_1_iv_0_0_a2_6)) + (portRef D (instanceRef wb_dati_5_1_iv_0_0_o2_am_5)) + (portRef C (instanceRef wb_adr_5_i_0_1_bm_0)) + (portRef C (instanceRef wb_dati_5_1_iv_0_o2_0_RNIMDJC1_4)) + (portRef C (instanceRef wb_reqe_RNO)) + (portRef B (instanceRef wb_adr_5_i_0_2_RNO_0_0)) )) (net CASr2 (joined (portRef Q (instanceRef CASr2)) - (portRef A (instanceRef RCKEEN_8_u_0_1_0)) - (portRef A (instanceRef RCKEEN_8_u_0_0_o2)) - (portRef A (instanceRef nRWE_s_i_0_a2)) + (portRef A (instanceRef RCKEEN_8_u_1)) + (portRef A (instanceRef RCKEEN_8_u_0_o3)) + (portRef A (instanceRef nRWE_s_i_a2_2)) (portRef D (instanceRef CASr3)) - (portRef C (instanceRef nRCAS_r_i_0_o2_0_2_RNO)) + (portRef C (instanceRef nRCAS_0io_RNO_2)) )) (net CASr (joined (portRef Q (instanceRef CASr)) @@ -2340,36 +2340,36 @@ )) (net RASr (joined (portRef Q (instanceRef RASr)) - (portRef A (instanceRef RCKE_2_0_0)) + (portRef A (instanceRef RCKE_2_0)) (portRef D (instanceRef RASr2)) )) (net (rename Bank_0 "Bank[0]") (joined (portRef Q (instanceRef Bank_0io_0)) - (portRef A (instanceRef un1_CmdEnable20_0_0_o3_10)) + (portRef A (instanceRef un1_CmdEnable20_0_0_o2)) )) (net (rename Bank_1 "Bank[1]") (joined (portRef Q (instanceRef Bank_0io_1)) - (portRef A (instanceRef un1_CmdEnable20_0_0_o3_11)) + (portRef A (instanceRef un1_CmdEnable20_0_0_o2_10)) )) (net (rename Bank_3 "Bank[3]") (joined (portRef Q (instanceRef Bank_0io_3)) - (portRef B (instanceRef un1_CmdEnable20_0_0_o3_11)) + (portRef B (instanceRef un1_CmdEnable20_0_0_o2_11)) )) (net (rename Bank_4 "Bank[4]") (joined (portRef Q (instanceRef Bank_0io_4)) - (portRef C (instanceRef un1_CmdEnable20_0_0_o3_11)) + (portRef B (instanceRef un1_CmdEnable20_0_0_o2)) )) (net (rename Bank_5 "Bank[5]") (joined (portRef Q (instanceRef Bank_0io_5)) - (portRef D (instanceRef un1_CmdEnable20_0_0_o3_11)) + (portRef C (instanceRef un1_CmdEnable20_0_0_o2_11)) )) (net (rename Bank_6 "Bank[6]") (joined (portRef Q (instanceRef Bank_0io_6)) - (portRef A (instanceRef un1_CmdEnable20_0_0_o3)) + (portRef D (instanceRef un1_CmdEnable20_0_0_o2_11)) )) (net (rename Bank_7 "Bank[7]") (joined (portRef Q (instanceRef Bank_0io_7)) - (portRef B (instanceRef un1_CmdEnable20_0_0_o3)) + (portRef B (instanceRef un1_CmdEnable20_0_0_o2_10)) )) (net (rename RowA_0 "RowA[0]") (joined (portRef Q (instanceRef RowA_0)) @@ -2446,21 +2446,21 @@ (net nRowColSel (joined (portRef Q (instanceRef nRowColSel)) (portRef B (instanceRef RDQML_0_0)) + (portRef C (instanceRef un9_RA_8)) + (portRef C (instanceRef un9_RA_i_m2_i_m2_2)) + (portRef C (instanceRef un9_RA_i_m2_i_m2_3)) (portRef C (instanceRef un9_RA_i_m2_i_m2_9)) (portRef C (instanceRef un9_RA_i_m2_i_m2_7)) (portRef C (instanceRef un9_RA_i_m2_i_m2_6)) (portRef C (instanceRef un9_RA_i_m2_i_m2_5)) (portRef C (instanceRef un9_RA_i_m2_i_m2_4)) - (portRef C (instanceRef un9_RA_i_m2_i_m2_3)) - (portRef C (instanceRef un9_RA_i_m2_i_m2_2)) (portRef C (instanceRef un9_RA_i_m2_i_m2_1)) (portRef C (instanceRef un9_RA_i_m2_i_m2_0)) - (portRef C (instanceRef un9_RA_8)) (portRef B (instanceRef RDQMH_pad_RNO)) )) (net RASr3 (joined (portRef Q (instanceRef RASr3)) - (portRef C (instanceRef RCKE_2_0_0)) + (portRef C (instanceRef RCKE_2_0)) )) (net LEDEN (joined (portRef Q (instanceRef LEDEN)) @@ -2471,113 +2471,125 @@ )) (net CmdLEDEN (joined (portRef Q (instanceRef CmdLEDEN)) - (portRef A (instanceRef LEDEN_6_i_m2_i_m2)) - (portRef A (instanceRef CmdLEDEN_4_u_i_0_0)) + (portRef A (instanceRef LEDEN_6_i_m2)) + (portRef A (instanceRef CmdLEDEN_4_u_i_m2_i_0)) )) (net Cmdn8MEGEN (joined (portRef Q (instanceRef Cmdn8MEGEN)) (portRef A (instanceRef n8MEGEN_RNO_0)) - (portRef B (instanceRef Cmdn8MEGEN_4_u_i_0_0)) + (portRef B (instanceRef Cmdn8MEGEN_4_u_i_m2_i_0)) )) (net PHI2r3 (joined (portRef Q (instanceRef PHI2r3)) (portRef B (instanceRef PHI2r3_RNIFT0I)) - (portRef C (instanceRef wb_cyc_stb_4_iv_0_RNO)) + (portRef C (instanceRef wb_cyc_stb_4_iv_0_0_RNO)) (portRef B (instanceRef PHI2r3_RNIFT0I_0)) - (portRef D (instanceRef CmdValid_RNIS5A51)) + (portRef D (instanceRef un1_InitReady_4_i_0_a2_i)) )) (net CmdValid (joined (portRef Q (instanceRef CmdValid)) - (portRef A (instanceRef wb_cyc_stb_4_iv_0_RNO)) + (portRef A (instanceRef wb_cyc_stb_4_iv_0_0_RNO)) (portRef A (instanceRef CmdValid_RNIOOBE2)) - (portRef A (instanceRef CmdValid_RNIS5A51)) + (portRef A (instanceRef un1_InitReady_4_i_0_a2_i)) )) (net CmdUFMData (joined (portRef Q (instanceRef CmdUFMData)) (portRef A (instanceRef wb_we_RNO)) )) (net wb_rst10 (joined - (portRef Z (instanceRef FS_RNIHVJI_0_16)) - (portRef D (instanceRef wb_rste)) + (portRef Z (instanceRef FS_RNIHVJI_0_15)) (portRef CD (instanceRef wb_cyc_stb)) (portRef CD (instanceRef wb_req)) (portRef CD (instanceRef wb_we)) )) (net InitReady3 (joined - (portRef Z (instanceRef InitReady3_0_a3)) + (portRef Z (instanceRef InitReady3_0_a2)) (portRef A (instanceRef InitReady_RNO)) )) (net RCKEEN (joined (portRef Q (instanceRef RCKEEN)) - (portRef D (instanceRef RCKE_2_0_0)) + (portRef D (instanceRef RCKE_2_0)) )) (net XOR8MEG (joined (portRef Q (instanceRef XOR8MEG)) (portRef C (instanceRef RA11d)) - (portRef D (instanceRef XOR8MEG_3_u_0_0_0_a3)) + (portRef D (instanceRef XOR8MEG_3_u_0_0_0_a2)) )) (net nRRAS_0_sqmuxa (joined - (portRef Z (instanceRef Ready_RNICVV51)) - (portRef D (instanceRef nRCS_9_u_i_0_o3)) - (portRef C (instanceRef nRWE_s_i_0_tz_0)) + (portRef Z (instanceRef S_RNICVV51_1)) + (portRef C (instanceRef nRWE_s_i_tz_0)) (portRef CD (instanceRef nRowColSel)) - (portRef A (instanceRef nRRAS_0io_RNO)) )) (net wb_req (joined (portRef Q (instanceRef wb_req)) (portRef C (instanceRef wb_reqe)) - (portRef B (instanceRef wb_cyc_stb_4_iv_0_a3_0_0)) - (portRef C (instanceRef wb_cyc_stb_2_sqmuxa_i_a3_0)) + (portRef B (instanceRef wb_cyc_stb_4_iv_0_0_a2_0_0)) + (portRef C (instanceRef wb_cyc_stb_2_sqmuxa_i_0_0_a2_0)) )) (net Ready_0_sqmuxa (joined - (portRef Z (instanceRef Ready_0_sqmuxa_0_a2_4_a3)) + (portRef Z (instanceRef Ready_0_sqmuxa_0_a2)) (portRef A (instanceRef Ready_fast_RNO)) )) + (net wb_rst_3 (joined + (portRef Z (instanceRef wb_rst_3_0_a2_0_a2)) + (portRef C (instanceRef wb_rste)) + )) (net RCKE_2 (joined - (portRef Z (instanceRef RCKE_2_0_0)) + (portRef Z (instanceRef RCKE_2_0)) (portRef D (instanceRef RCKE)) )) (net nRCAS_0_sqmuxa_1 (joined (portRef Z (instanceRef CBR_fast_RNIQ31K1)) - (portRef A (instanceRef nRWE_0io_RNO)) (portRef B (instanceRef nRCAS_0io_RNO_0)) + (portRef A (instanceRef nRWE_0io_RNO)) + )) + (net XOR8MEG18 (joined + (portRef Z (instanceRef CmdUFMData_1_sqmuxa_0_a2_3)) + (portRef A (instanceRef CmdValid_r_fast)) + (portRef A (instanceRef CmdValid_r)) + (portRef B (instanceRef CmdUFMData_1_sqmuxa_0_a2)) + (portRef SP (instanceRef CmdLEDEN)) + (portRef SP (instanceRef CmdUFMShift)) + (portRef SP (instanceRef CmdUFMWrite)) + (portRef SP (instanceRef Cmdn8MEGEN)) + (portRef SP (instanceRef XOR8MEG)) )) (net CmdEnable (joined (portRef Q (instanceRef CmdEnable)) - (portRef A (instanceRef CmdUFMData_1_sqmuxa_0_a3_3)) + (portRef A (instanceRef CmdUFMData_1_sqmuxa_0_a2_3)) (portRef A (instanceRef CmdEnable_s)) )) (net CmdUFMWrite (joined (portRef Q (instanceRef CmdUFMWrite)) - (portRef A (instanceRef CmdUFMWrite_3_u_0_0_0_a3)) - (portRef A (instanceRef wb_cyc_stb_4_iv_0)) + (portRef A (instanceRef CmdUFMWrite_3_u_0_0_0_a2)) + (portRef A (instanceRef wb_cyc_stb_4_iv_0_0)) )) (net CmdEnable16 (joined (portRef Z (instanceRef CmdEnable16_0_a2_1_a2)) (portRef D (instanceRef ADSubmitted_r_0_0)) - (portRef B (instanceRef CmdEnable_0_sqmuxa_0_a3_0_a3)) + (portRef B (instanceRef CmdEnable_0_sqmuxa_0_a2_0_a2)) (portRef A (instanceRef C1Submitted_RNO)) )) (net CmdEnable17 (joined - (portRef Z (instanceRef un1_CmdEnable20_0_0_a2_0_RNI00E51)) + (portRef Z (instanceRef un1_CmdEnable20_0_0_a2_3_RNIJ3N91)) (portRef C (instanceRef ADSubmitted_r_0_0)) (portRef B (instanceRef CmdEnable_s)) )) (net CmdUFMData_1_sqmuxa (joined - (portRef Z (instanceRef CmdUFMData_1_sqmuxa_0_a3)) + (portRef Z (instanceRef CmdUFMData_1_sqmuxa_0_a2)) (portRef SP (instanceRef CmdUFMData)) )) (net ADSubmitted (joined (portRef Q (instanceRef ADSubmitted)) (portRef A (instanceRef ADSubmitted_r_0_0)) - (portRef A (instanceRef CmdEnable_0_sqmuxa_0_a3_0_a3)) + (portRef A (instanceRef CmdEnable_0_sqmuxa_0_a2_0_a2)) )) (net CmdEnable_0_sqmuxa (joined - (portRef Z (instanceRef CmdEnable_0_sqmuxa_0_a3_0_a3)) + (portRef Z (instanceRef CmdEnable_0_sqmuxa_0_a2_0_a2)) (portRef D (instanceRef CmdEnable_s)) )) (net wb_cyc_stb_4 (joined - (portRef Z (instanceRef wb_cyc_stb_4_iv_0)) + (portRef Z (instanceRef wb_cyc_stb_4_iv_0_0)) (portRef D (instanceRef wb_cyc_stb)) )) (net (rename wb_dati_5_0 "wb_dati_5[0]") (joined @@ -2588,12 +2600,24 @@ (portRef Z (instanceRef wb_dati_5_1_iv_0_1)) (portRef D (instanceRef wb_dati_1)) )) + (net (rename wb_dati_5_2 "wb_dati_5[2]") (joined + (portRef Z (instanceRef wb_dati_5_1_iv_0_0_2)) + (portRef D (instanceRef wb_dati_2)) + )) + (net (rename wb_dati_5_3 "wb_dati_5[3]") (joined + (portRef Z (instanceRef wb_dati_5_1_iv_0_0_3)) + (portRef D (instanceRef wb_dati_3)) + )) (net (rename wb_dati_5_4 "wb_dati_5[4]") (joined - (portRef Z (instanceRef wb_dati_5_1_iv_0_4)) + (portRef Z (instanceRef wb_dati_5_1_iv_0_0_4)) (portRef D (instanceRef wb_dati_4)) )) + (net (rename wb_dati_5_5 "wb_dati_5[5]") (joined + (portRef Z (instanceRef wb_dati_5_1_iv_0_0_5)) + (portRef D (instanceRef wb_dati_5)) + )) (net (rename wb_dati_5_6 "wb_dati_5[6]") (joined - (portRef Z (instanceRef wb_dati_5_1_iv_0_6)) + (portRef Z (instanceRef wb_dati_5_1_iv_0_0_6)) (portRef D (instanceRef wb_dati_6)) )) (net (rename wb_dati_5_7 "wb_dati_5[7]") (joined @@ -2616,7 +2640,109 @@ (portRef Z (instanceRef CmdEnable_s)) (portRef D (instanceRef CmdEnable)) )) - (net un1_wb_rst14_i_0 (joined + (net nRowColSel_0_0 (joined + (portRef Z (instanceRef nRowColSel_0_0)) + (portRef D (instanceRef nRowColSel)) + )) + (net (rename wb_adr_5_2 "wb_adr_5[2]") (joined + (portRef Z (instanceRef wb_adr_5_2)) + (portRef D (instanceRef wb_adr_2)) + )) + (net (rename wb_adr_5_3 "wb_adr_5[3]") (joined + (portRef Z (instanceRef wb_adr_5_3)) + (portRef D (instanceRef wb_adr_3)) + )) + (net (rename wb_adr_5_7 "wb_adr_5[7]") (joined + (portRef Z (instanceRef wb_adr_5_7)) + (portRef D (instanceRef wb_adr_7)) + )) + (net RCKEEN_8 (joined + (portRef Z (instanceRef RCKEEN_8_u)) + (portRef D (instanceRef RCKEEN)) + )) + (net wb_cyc_stb_2_sqmuxa_i_0_0 (joined + (portRef Z (instanceRef wb_cyc_stb_2_sqmuxa_i_0_0)) + (portRef SP (instanceRef wb_cyc_stb)) + )) + (net N_48 (joined + (portRef Z (instanceRef un1_nRCAS_6_sqmuxa_i_0)) + (portRef A (instanceRef nRCAS_0io_RNO_0)) + (portRef A (instanceRef nRCAS_0io_RNO_2)) + )) + (net (rename S_0_i_o3_1 "S_0_i_o3[1]") (joined + (portRef Z (instanceRef S_0_i_o3_1)) + (portRef A (instanceRef nRCS_9_u_i_0_0)) + (portRef D (instanceRef S_1)) + (portRef D (instanceRef RCKEEN_8_u_RNO)) + )) + (net IS_0_sqmuxa_0_o2 (joined + (portRef Z (instanceRef IS_0_sqmuxa_0_o2)) + (portRef C (instanceRef IS_RNO_0)) + (portRef B (instanceRef IS_0_sqmuxa_0_o2_RNIDJQJ)) + (portRef C (instanceRef nRRAS_0io_RNO)) + (portRef A (instanceRef IS_0_sqmuxa_0_o3)) + (portRef A (instanceRef un1_nRCAS_6_sqmuxa_i_0)) + (portRef B (instanceRef nRCS_9_u_i_0)) + )) + (net IS_0_sqmuxa_0_o3 (joined + (portRef Z (instanceRef IS_0_sqmuxa_0_o3)) + (portRef D (instanceRef nRWE_s_i_a2_1_0)) + (portRef D (instanceRef RA10_0io_RNO_0)) + )) + (net RCKEEN_8_u_0_o3 (joined + (portRef Z (instanceRef RCKEEN_8_u_0_o3)) + (portRef C (instanceRef nRCAS_0io_RNO_1)) + )) + (net un1_nRCAS_6_sqmuxa_i_o2 (joined + (portRef Z (instanceRef un1_nRCAS_6_sqmuxa_i_o2)) + (portRef B (instanceRef nRRAS_0io_RNO)) + (portRef B (instanceRef un1_nRCAS_6_sqmuxa_i_0)) + (portRef C (instanceRef nRCS_9_u_i_0)) + )) + (net Ready_0_sqmuxa_0_o2 (joined + (portRef Z (instanceRef Ready_0_sqmuxa_0_o2)) + (portRef B (instanceRef Ready_0_sqmuxa_0_a2)) + (portRef C (instanceRef Ready_RNO)) + )) + (net N_251_i_1 (joined + (portRef Z (instanceRef nRCS_9_u_i_a2_0)) + (portRef A (instanceRef nRCAS_0io_RNO)) + (portRef C (instanceRef nRCS_0io_RNO)) + )) + (net N_251_i_1_0 (joined + (portRef Z (instanceRef nRowColSel_0_0_a2_1)) + (portRef B (instanceRef nRCAS_0io_RNO)) + (portRef C (instanceRef nRowColSel_0_0)) + )) + (net N_141 (joined + (portRef Z (instanceRef RCKEEN_8_u_0_a2_2)) + (portRef A (instanceRef nRCS_0io_RNO)) + (portRef B (instanceRef nRWE_0io_RNO)) + )) + (net N_142 (joined + (portRef Z (instanceRef nRWE_s_i_a2_2)) + (portRef B (instanceRef nRCS_0io_RNO)) + (portRef C (instanceRef nRWE_0io_RNO)) + )) + (net N_69_i (joined + (portRef Z (instanceRef IS_n1_0_x2)) + (portRef D (instanceRef IS_1)) + )) + (net N_70_i (joined + (portRef Z (instanceRef nRowColSel_0_0_x2)) + (portRef B (instanceRef nRowColSel_0_0)) + )) + (net N_99_1 (joined + (portRef Z (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_1)) + (portRef B (instanceRef wb_cyc_stb_2_sqmuxa_i_0_0_a2_0)) + (portRef A (instanceRef wb_cyc_stb_4_iv_0_0_a2_0)) + )) + (net N_99_2 (joined + (portRef Z (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_2)) + (portRef A (instanceRef wb_cyc_stb_2_sqmuxa_i_0_0)) + (portRef B (instanceRef wb_cyc_stb_4_iv_0_0_a2_0)) + )) + (net N_126_i (joined (portRef Z (instanceRef CmdValid_fast_RNI3K0H1)) (portRef SP (instanceRef wb_adr_7)) (portRef SP (instanceRef wb_adr_6)) @@ -2636,477 +2762,349 @@ (portRef SP (instanceRef wb_dati_0)) (portRef SP (instanceRef wb_we)) )) - (net nRowColSel_0_0_0 (joined - (portRef Z (instanceRef nRowColSel_0_0_0)) - (portRef D (instanceRef nRowColSel)) + (net N_122_i (joined + (portRef Z (instanceRef un1_InitReady_4_i_0_a2_i)) + (portRef A (instanceRef wb_reqe)) + (portRef A (instanceRef wb_rste)) )) - (net CmdUFMShift_3 (joined - (portRef Z (instanceRef CmdUFMShift_3_u_0_0_0)) - (portRef D (instanceRef CmdUFMShift)) + (net un1_FS_38_i (joined + (portRef Z (instanceRef CmdValid_RNIOOBE2)) + (portRef C (instanceRef n8MEGEN_RNO)) + (portRef C (instanceRef LEDENe)) )) - (net CmdUFMWrite_3 (joined - (portRef Z (instanceRef CmdUFMWrite_3_u_0_0_0)) - (portRef D (instanceRef CmdUFMWrite)) + (net (rename FS_RNIS637_9 "FS_RNIS637[9]") (joined + (portRef Z (instanceRef FS_RNIS637_9)) + (portRef C (instanceRef wb_we_0_0_i_a2_0)) + (portRef C (instanceRef wb_dati_5_1_iv_0_a2_7_3)) + (portRef B (instanceRef wb_dati_5_1_iv_0_a2_5_3)) + (portRef B (instanceRef wb_dati_5_1_iv_0_1)) + (portRef B (instanceRef wb_dati_5_1_iv_0_0_6)) + (portRef B (instanceRef wb_adr_RNO_0_1)) )) - (net RCKEEN_8 (joined - (portRef Z (instanceRef RCKEEN_8_u_0)) - (portRef D (instanceRef RCKEEN)) + (net (rename wb_dati_5_1_iv_0_0_o2_4 "wb_dati_5_1_iv_0_0_o2[4]") (joined + (portRef Z (instanceRef wb_dati_5_1_iv_0_0_o2_4)) + (portRef C (instanceRef wb_dati_5_1_iv_0_1_0_4)) + (portRef B (instanceRef wb_adr_5_i_0_3_0)) + (portRef B (instanceRef wb_dati_5_1_iv_0_o2_7)) + )) + (net (rename wb_dati_5_1_iv_0_0_o2_3 "wb_dati_5_1_iv_0_0_o2[3]") (joined + (portRef Z (instanceRef wb_dati_5_1_iv_0_0_o2_3)) + (portRef B (instanceRef wb_dati_5_1_iv_0_0_1_3)) + (portRef B (instanceRef wb_dati_5_1_iv_0_1_1)) + (portRef C (instanceRef wb_dati_5_1_iv_0_0_o2_am_5)) + )) + (net (rename FS_RNI82PA_15 "FS_RNI82PA[15]") (joined + (portRef Z (instanceRef FS_RNI82PA_15)) + (portRef B (instanceRef wb_adr_5_i_m2_6)) + (portRef B (instanceRef wb_adr_5_i_m2_5)) + (portRef B (instanceRef wb_adr_5_i_m2_4)) + (portRef B (instanceRef wb_adr_5_i_3_0_m2_1)) + (portRef B (instanceRef wb_adr_5_i_0_2_0)) + )) + (net (rename wb_dati_5_1_iv_0_o2_0_4 "wb_dati_5_1_iv_0_o2_0[4]") (joined + (portRef Z (instanceRef wb_dati_5_1_iv_0_o2_0_4)) + (portRef B (instanceRef wb_we_0_0_i_1_1)) + (portRef B (instanceRef wb_dati_5_1_iv_0_o2_0_RNIMDJC1_4)) + )) + (net (rename FS_RNIHVJI_15 "FS_RNIHVJI[15]") (joined + (portRef Z (instanceRef FS_RNIHVJI_15)) + (portRef FS_RNIHVJI_0 (instanceRef ufmefb)) + (portRef B (instanceRef wb_dati_5_1_iv_0_a2_13_3)) + (portRef D (instanceRef FS_RNIGOCT_12)) + (portRef B (instanceRef FS_RNI7U6M_14)) + (portRef C (instanceRef wb_dati_5_1_iv_0_a2_0_7)) + (portRef B (instanceRef wb_dati_5_1_iv_0_a2_12_3)) + (portRef B (instanceRef wb_dati_5_1_iv_0_0_1)) + (portRef B (instanceRef wb_cyc_stb_2_sqmuxa_i_0_0)) + (portRef C (instanceRef wb_cyc_stb_4_iv_0_0_a2_0)) + (portRef B (instanceRef wb_dati_5_1_iv_0_0_o2_am_5)) + (portRef B (instanceRef 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(instanceRef wb_dati_5_1_iv_0_0_5)) + )) + (net LEDEN_6 (joined + (portRef Z (instanceRef LEDEN_6_i_m2)) + (portRef B (instanceRef LEDENe)) + )) + (net N_216 (joined + (portRef Z (instanceRef wb_adr_5_i_3_0_m2_1)) + (portRef A (instanceRef wb_adr_RNO_1)) + )) + (net (rename wb_adr_5_4 "wb_adr_5[4]") (joined + (portRef Z (instanceRef wb_adr_5_i_m2_4)) + (portRef D (instanceRef wb_adr_4)) + )) + (net (rename wb_adr_5_5 "wb_adr_5[5]") (joined + (portRef Z (instanceRef wb_adr_5_i_m2_5)) + (portRef D (instanceRef wb_adr_5)) + )) + (net (rename wb_adr_5_6 "wb_adr_5[6]") (joined + (portRef Z (instanceRef wb_adr_5_i_m2_6)) + (portRef D (instanceRef wb_adr_6)) + )) + (net (rename wb_adr_5_i_0_o2_0 "wb_adr_5_i_0_o2[0]") (joined + (portRef Z (instanceRef wb_adr_5_i_0_o2_0)) + (portRef A (instanceRef wb_adr_5_i_0_2_RNO_0_0)) + )) + (net un1_wb_rst14_2_0_o2 (joined + (portRef Z (instanceRef un1_wb_rst14_2_0_o2)) + (portRef C (instanceRef wb_we_RNO)) + (portRef A (instanceRef wb_reqe_RNO)) + )) + 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CmdLEDEN_4_u_i_m2_i_0)) (portRef A (instanceRef CmdLEDEN_RNO)) )) - (net un1_CmdEnable20_0_0_a3_1_1 (joined - (portRef Z (instanceRef un1_CmdEnable20_0_0_a3_1_1)) + (net un1_CmdEnable20_0_0_a2_1_1 (joined + (portRef Z (instanceRef un1_CmdEnable20_0_0_a2_1_1)) (portRef D (instanceRef CmdEnable_s_RNO)) )) - (net wb_cyc_stb_4_iv_0_a3_0_2_0 (joined - (portRef Z (instanceRef wb_cyc_stb_4_iv_0_a3_0_2_0)) - (portRef D (instanceRef wb_cyc_stb_4_iv_0_a3_0_2)) + (net wb_cyc_stb_2_sqmuxa_i_a2_2_0 (joined + (portRef Z (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_2_0)) + (portRef D (instanceRef wb_cyc_stb_2_sqmuxa_i_a2_2)) )) - (net wb_we_0_i_0_0 (joined - (portRef Z (instanceRef wb_we_0_i_0_0)) - (portRef D (instanceRef wb_we_0_i_0_1)) - )) - (net wb_we_0_i_0_1 (joined - (portRef Z (instanceRef wb_we_0_i_0_1)) - (portRef D (instanceRef wb_we_RNO)) - )) - (net (rename wb_adr_5_i_0_a3_0_1_0 "wb_adr_5_i_0_a3_0_1[0]") (joined - (portRef Z (instanceRef wb_adr_5_i_0_a3_0_2_0)) - (portRef D (instanceRef wb_adr_5_i_0_1_0)) - )) - (net wb_we_0_i_0_a3_0_0 (joined - (portRef Z (instanceRef wb_we_0_i_0_0_RNO)) - (portRef D (instanceRef wb_we_0_i_0_0)) - )) - (net XOR8MEG_3_u_0_0_a3_0_2 (joined - (portRef Z (instanceRef XOR8MEG_3_u_0_0_a3_0_2)) + (net XOR8MEG_3_u_0_0_a2_0_2 (joined + (portRef Z (instanceRef XOR8MEG_3_u_0_0_a2_0_2)) (portRef D (instanceRef XOR8MEG_3_u_0_0_0)) )) - (net Ready_0_sqmuxa_0_a2_4_a3_2 (joined - (portRef Z (instanceRef Ready_0_sqmuxa_0_a2_4_a3_2)) - (portRef D (instanceRef Ready_0_sqmuxa_0_a2_4_a3)) + (net wb_we_0_0_i_1 (joined + (portRef Z (instanceRef wb_we_0_0_i_1)) + (portRef D (instanceRef wb_we_RNO)) + )) + (net Ready_0_sqmuxa_0_a2_2 (joined + (portRef Z (instanceRef Ready_0_sqmuxa_0_a2_2)) + (portRef D (instanceRef Ready_0_sqmuxa_0_a2)) (portRef B (instanceRef Ready_RNO)) )) - (net InitReady3_0_a3_1 (joined - (portRef Z (instanceRef InitReady3_0_a3_1)) - (portRef C (instanceRef InitReady3_0_a3)) + (net wb_cyc_stb_2_sqmuxa_i_0_0_a2_0 (joined + (portRef Z (instanceRef wb_cyc_stb_2_sqmuxa_i_0_0_a2_0)) + (portRef D (instanceRef wb_cyc_stb_2_sqmuxa_i_0_0)) )) - (net wb_cyc_stb_2_sqmuxa_i_a3_0 (joined - (portRef Z (instanceRef wb_cyc_stb_2_sqmuxa_i_a3_0)) - (portRef D (instanceRef wb_cyc_stb_2_sqmuxa_i_0)) - )) - (net nRWE_s_i_0_tz_0 (joined - (portRef Z (instanceRef nRWE_s_i_0_tz_0)) + (net nRWE_s_i_tz_0 (joined + (portRef Z (instanceRef nRWE_s_i_tz_0)) (portRef D (instanceRef nRWE_0io_RNO)) )) - (net (rename wb_dati_5_1_iv_0_a3_0_1_7 "wb_dati_5_1_iv_0_a3_0_1[7]") (joined - (portRef Z (instanceRef wb_dati_5_1_iv_0_a3_0_1_7)) - (portRef D (instanceRef wb_dati_5_1_iv_0_0_7)) + (net (rename wb_dati_5_1_iv_0_a2_0_0_7 "wb_dati_5_1_iv_0_a2_0_0[7]") (joined + (portRef Z (instanceRef wb_dati_5_1_iv_0_a2_0_RNO_7)) + (portRef D (instanceRef wb_dati_5_1_iv_0_a2_0_7)) )) - (net un1_CmdEnable20_0_0_o3_3 (joined - (portRef Z (instanceRef un1_CmdEnable20_0_0_o3_3)) - (portRef C (instanceRef un1_CmdEnable20_0_0_o3_10)) + (net un1_CmdEnable20_0_0_o2_3 (joined + (portRef Z (instanceRef un1_CmdEnable20_0_0_o2_3)) + (portRef C (instanceRef un1_CmdEnable20_0_0_o2_10)) )) - (net un1_CmdEnable20_0_0_o3_4 (joined - (portRef Z (instanceRef un1_CmdEnable20_0_0_o3_4)) - (portRef D (instanceRef un1_CmdEnable20_0_0_o3_10)) + (net un1_CmdEnable20_0_0_o2_4 (joined + (portRef Z (instanceRef un1_CmdEnable20_0_0_o2_4)) + (portRef D (instanceRef un1_CmdEnable20_0_0_o2_10)) )) - (net un1_CmdEnable20_0_0_o3_10 (joined - (portRef Z (instanceRef un1_CmdEnable20_0_0_o3_10)) - (portRef C (instanceRef un1_CmdEnable20_0_0_o3)) + (net un1_CmdEnable20_0_0_o2_10 (joined + (portRef Z (instanceRef un1_CmdEnable20_0_0_o2_10)) + (portRef C (instanceRef un1_CmdEnable20_0_0_o2)) )) - (net un1_CmdEnable20_0_0_o3_11 (joined - (portRef Z (instanceRef un1_CmdEnable20_0_0_o3_11)) - (portRef D (instanceRef un1_CmdEnable20_0_0_o3)) + (net un1_CmdEnable20_0_0_o2_11 (joined + (portRef Z (instanceRef un1_CmdEnable20_0_0_o2_11)) + (portRef D (instanceRef un1_CmdEnable20_0_0_o2)) )) - (net nRCAS_r_i_0_o2_0_0 (joined - (portRef Z (instanceRef nRCAS_r_i_0_o2_0_2_RNO)) - (portRef D (instanceRef nRCAS_r_i_0_o2_0_2)) + (net nRCS_9_u_i_o3_0_0 (joined + (portRef Z (instanceRef nRCAS_0io_RNO_2)) + (portRef D (instanceRef nRCAS_0io_RNO_1)) )) - (net N_248_i_1 (joined - (portRef Z (instanceRef nRCAS_r_i_0_o2_0_2)) - (portRef A (instanceRef nRCAS_0io_RNO)) + (net nRCS_9_u_i_o3_0_2 (joined + (portRef Z (instanceRef nRCAS_0io_RNO_1)) + (portRef D (instanceRef nRCAS_0io_RNO)) )) - (net (rename wb_dati_5_1_iv_0_a3_0_1_1 "wb_dati_5_1_iv_0_a3_0_1[1]") (joined - (portRef Z (instanceRef wb_dati_5_1_iv_0_a3_0_RNO_1)) - (portRef C (instanceRef wb_dati_5_1_iv_0_a3_0_1)) + (net (rename wb_dati_5_1_iv_0_a2_0_2_1 "wb_dati_5_1_iv_0_a2_0_2[1]") (joined + (portRef Z (instanceRef wb_dati_5_1_iv_0_a2_0_2_1)) + (portRef D (instanceRef wb_dati_5_1_iv_0_0_1)) )) - (net wb_cyc_stb_4_iv_0_a3_0_0 (joined - (portRef Z (instanceRef wb_cyc_stb_4_iv_0_a3_0_0)) - (portRef D (instanceRef wb_cyc_stb_4_iv_0_a3_0)) + (net wb_cyc_stb_4_iv_0_0_a2_0_0 (joined + (portRef Z (instanceRef wb_cyc_stb_4_iv_0_0_a2_0_0)) + (portRef D (instanceRef wb_cyc_stb_4_iv_0_0_a2_0)) )) - (net (rename wb_dati_5_0_iv_0_a3_1_0 "wb_dati_5_0_iv_0_a3_1[0]") (joined - (portRef Z (instanceRef wb_dati_5_0_iv_0_a3_1_0)) + (net (rename wb_dati_5_0_iv_0_a2_1_0 "wb_dati_5_0_iv_0_a2_1[0]") (joined + (portRef Z (instanceRef wb_dati_5_0_iv_0_a2_1_0)) (portRef C (instanceRef wb_dati_5_0_iv_0_0)) )) - (net (rename wb_dati_5_1_iv_i_i_a3_3_0_3 "wb_dati_5_1_iv_i_i_a3_3_0[3]") (joined - (portRef Z (instanceRef wb_dati_5_1_iv_i_i_0_RNO_3)) - (portRef D (instanceRef wb_dati_5_1_iv_i_i_0_3)) + (net nRCS_9_u_i_0_0 (joined + (portRef Z (instanceRef nRCS_9_u_i_0_0)) + (portRef A (instanceRef nRRAS_0io_RNO)) + (portRef D (instanceRef nRCS_9_u_i_0)) )) (net un1_CmdEnable20_0_0_0 (joined (portRef Z (instanceRef un1_CmdEnable20_0_0_0)) (portRef C (instanceRef CmdEnable_s_RNO)) )) - (net (rename wb_adr_5_i_0_0_1 "wb_adr_5_i_0_0[1]") (joined + (net (rename wb_adr_5_i_3_0_0_1 "wb_adr_5_i_3_0_0[1]") (joined (portRef Z (instanceRef wb_adr_RNO_0_1)) (portRef D (instanceRef wb_adr_RNO_1)) )) - (net (rename wb_dati_5_1_iv_i_i_a3_1_3 "wb_dati_5_1_iv_i_i_a3_1[3]") (joined - (portRef Z (instanceRef wb_dati_5_1_iv_i_i_a3_1_1_3)) - (portRef D (instanceRef wb_dati_5_1_iv_i_i_3)) + (net (rename wb_dati_5_1_iv_0_0_a2_1_3 "wb_dati_5_1_iv_0_0_a2_1[3]") (joined + (portRef Z (instanceRef wb_dati_5_1_iv_0_0_a2_1_3)) + (portRef D (instanceRef wb_dati_5_1_iv_0_0_3)) )) (net (rename wb_adr_5_i_0_0_0 "wb_adr_5_i_0_0[0]") (joined - (portRef Z (instanceRef wb_adr_5_i_0_0_0)) - (portRef C (instanceRef wb_adr_RNO_0)) + (portRef Z (instanceRef wb_adr_5_i_0_2_RNO_0)) + (portRef C (instanceRef wb_adr_5_i_0_2_0)) )) (net (rename wb_adr_5_i_0_1_0 "wb_adr_5_i_0_1[0]") (joined (portRef Z (instanceRef wb_adr_5_i_0_1_0)) (portRef D (instanceRef wb_adr_5_i_0_3_0)) )) + (net (rename wb_adr_5_i_0_2_0 "wb_adr_5_i_0_2[0]") (joined + (portRef Z (instanceRef wb_adr_5_i_0_2_0)) + (portRef C (instanceRef wb_adr_RNO_0)) + )) (net (rename wb_adr_5_i_0_3_0 "wb_adr_5_i_0_3[0]") (joined (portRef Z (instanceRef wb_adr_5_i_0_3_0)) (portRef D (instanceRef wb_adr_RNO_0)) )) + (net (rename wb_dati_5_1_iv_0_0_1 "wb_dati_5_1_iv_0_0[1]") (joined + (portRef Z (instanceRef wb_dati_5_1_iv_0_0_1)) + (portRef D (instanceRef wb_dati_5_1_iv_0_1_1)) + )) (net (rename wb_dati_5_1_iv_0_1_1 "wb_dati_5_1_iv_0_1[1]") (joined (portRef Z (instanceRef wb_dati_5_1_iv_0_1_1)) (portRef D (instanceRef wb_dati_5_1_iv_0_1)) )) - (net (rename wb_dati_5_1_iv_0_1_6 "wb_dati_5_1_iv_0_1[6]") (joined - (portRef Z (instanceRef wb_dati_5_1_iv_0_1_6)) - (portRef D (instanceRef wb_dati_5_1_iv_0_6)) + (net (rename wb_dati_5_1_iv_0_0_1_6 "wb_dati_5_1_iv_0_0_1[6]") (joined + (portRef Z (instanceRef wb_dati_5_1_iv_0_0_1_6)) + (portRef D (instanceRef wb_dati_5_1_iv_0_0_6)) )) - (net (rename wb_dati_5_1_iv_i_i_0_3 "wb_dati_5_1_iv_i_i_0[3]") (joined - (portRef Z (instanceRef wb_dati_5_1_iv_i_i_0_3)) - (portRef B (instanceRef wb_dati_5_1_iv_i_i_3)) + (net (rename wb_dati_5_1_iv_0_0_0_3 "wb_dati_5_1_iv_0_0_0[3]") (joined + (portRef Z (instanceRef wb_dati_5_1_iv_0_0_0_3)) + (portRef B (instanceRef wb_dati_5_1_iv_0_0_3)) )) - (net (rename wb_dati_5_1_iv_i_i_1_3 "wb_dati_5_1_iv_i_i_1[3]") (joined - (portRef Z (instanceRef wb_dati_5_1_iv_i_i_1_3)) - (portRef C (instanceRef wb_dati_5_1_iv_i_i_3)) + (net (rename wb_dati_5_1_iv_0_0_1_3 "wb_dati_5_1_iv_0_0_1[3]") (joined + (portRef Z (instanceRef wb_dati_5_1_iv_0_0_1_3)) + (portRef C (instanceRef wb_dati_5_1_iv_0_0_3)) )) - (net (rename wb_dati_5_1_iv_0_0_7 "wb_dati_5_1_iv_0_0[7]") (joined - (portRef Z (instanceRef wb_dati_5_1_iv_0_0_7)) + (net (rename wb_dati_5_1_iv_0_1_7 "wb_dati_5_1_iv_0_1[7]") (joined + (portRef Z (instanceRef wb_dati_5_1_iv_0_1_7)) (portRef D (instanceRef wb_dati_5_1_iv_0_7)) )) - (net (rename wb_dati_5_1_iv_0_1_4 "wb_dati_5_1_iv_0_1[4]") (joined - (portRef Z (instanceRef wb_dati_5_1_iv_0_1_4)) - (portRef D (instanceRef wb_dati_5_1_iv_0_4)) + (net (rename wb_dati_5_1_iv_0_0_1_4 "wb_dati_5_1_iv_0_0_1[4]") (joined + (portRef Z (instanceRef wb_dati_5_1_iv_0_0_1_4)) + (portRef C (instanceRef wb_dati_5_1_iv_0_0_4)) )) (net (rename FS_cry_0_S0_0 "FS_cry_0_S0[0]") (joined (portRef S0 (instanceRef FS_cry_0_0)) @@ -3464,13 +3465,21 @@ (net (rename FS_s_0_COUT_17 "FS_s_0_COUT[17]") (joined (portRef COUT (instanceRef FS_s_0_17)) )) - (net (rename wb_dati_5_1_iv_0_0_4 "wb_dati_5_1_iv_0_0[4]") (joined - (portRef Z (instanceRef wb_dati_5_1_iv_0_0_4)) - (portRef C (instanceRef wb_dati_5_1_iv_0_4)) + (net InitReady3_0_a2_1_0 (joined + (portRef Z (instanceRef InitReady3_0_a2_1_0)) + (portRef C (instanceRef InitReady3_0_a2)) )) - (net RCKEEN_8_u_0_1_0 (joined - (portRef Z (instanceRef RCKEEN_8_u_0_1_0)) - (portRef C (instanceRef RCKEEN_8_u_0)) + (net wb_we_0_0_i_1_1 (joined + (portRef Z (instanceRef wb_we_0_0_i_1_1)) + (portRef D (instanceRef wb_we_0_0_i_1)) + )) + (net (rename wb_dati_5_1_iv_0_1_0_4 "wb_dati_5_1_iv_0_1_0[4]") (joined + (portRef Z (instanceRef wb_dati_5_1_iv_0_1_0_4)) + (portRef D (instanceRef wb_dati_5_1_iv_0_0_4)) + )) + (net RCKEEN_8_u_1 (joined + (portRef Z (instanceRef RCKEEN_8_u_1)) + (portRef C (instanceRef RCKEEN_8_u)) )) (net LEDENe_0 (joined (portRef Z (instanceRef LEDENe)) @@ -3480,13 +3489,13 @@ (portRef Z (instanceRef n8MEGEN_RNO)) (portRef D (instanceRef n8MEGEN)) )) - (net (rename RowAd_0_7 "RowAd_0[7]") (joined - (portRef Z (instanceRef RowAd_7)) - (portRef D (instanceRef RowA_7)) + (net (rename RowAd_0_8 "RowAd_0[8]") (joined + (portRef Z (instanceRef RowAd_8)) + (portRef D (instanceRef RowA_8)) )) - (net (rename RowAd_0_6 "RowAd_0[6]") (joined - (portRef Z (instanceRef RowAd_6)) - (portRef D (instanceRef RowA_6)) + (net (rename RowAd_0_0 "RowAd_0[0]") (joined + (portRef Z (instanceRef RowAd_0)) + (portRef D (instanceRef RowA_0)) )) (net (rename RowAd_0_2 "RowAd_0[2]") (joined (portRef Z (instanceRef RowAd_2)) @@ -3500,29 +3509,29 @@ (portRef Z (instanceRef RowAd_4)) (portRef D (instanceRef RowA_4)) )) - (net (rename RowAd_0_1 "RowAd_0[1]") (joined - (portRef Z (instanceRef RowAd_1)) - (portRef D (instanceRef RowA_1)) + (net (rename RowAd_0_6 "RowAd_0[6]") (joined + (portRef Z (instanceRef RowAd_6)) + (portRef D (instanceRef RowA_6)) )) (net (rename RBAd_0_0 "RBAd_0[0]") (joined (portRef Z (instanceRef RBAd_0)) (portRef D (instanceRef RBA_0io_0)) )) - (net (rename RBAd_0_1 "RBAd_0[1]") (joined - (portRef Z (instanceRef RBAd_1)) - (portRef D (instanceRef RBA_0io_1)) - )) - (net (rename RowAd_0_8 "RowAd_0[8]") (joined - (portRef Z (instanceRef RowAd_8)) - (portRef D (instanceRef RowA_8)) + (net (rename RowAd_0_7 "RowAd_0[7]") (joined + (portRef Z (instanceRef RowAd_7)) + (portRef D (instanceRef RowA_7)) )) (net (rename RowAd_0_5 "RowAd_0[5]") (joined (portRef Z (instanceRef RowAd_5)) (portRef D (instanceRef RowA_5)) )) - (net (rename RowAd_0_0 "RowAd_0[0]") (joined - (portRef Z (instanceRef RowAd_0)) - (portRef D (instanceRef RowA_0)) + (net (rename RowAd_0_1 "RowAd_0[1]") (joined + (portRef Z (instanceRef RowAd_1)) + (portRef D (instanceRef RowA_1)) + )) + (net (rename RBAd_0_1 "RBAd_0[1]") (joined + (portRef Z (instanceRef RBAd_1)) + (portRef D (instanceRef RBA_0io_1)) )) (net (rename RowAd_0_9 "RowAd_0[9]") (joined (portRef Z (instanceRef RowAd_9)) @@ -3546,7 +3555,7 @@ )) (net n8MEGENe_1_0 (joined (portRef Z (instanceRef n8MEGEN_RNO_0)) - (portRef C (instanceRef n8MEGEN_RNO)) + (portRef B (instanceRef n8MEGEN_RNO)) )) (net N_4 (joined (portRef N_4 (instanceRef ufmefb)) @@ -3568,30 +3577,30 @@ (portRef Q (instanceRef CmdValid_fast)) (portRef B (instanceRef CmdValid_fast_RNI3K0H1)) )) - (net N_36_fast (joined + (net N_34_fast (joined (portRef Z (instanceRef CmdValid_r_fast)) (portRef D (instanceRef CmdValid_fast)) )) (net Ready_fast (joined (portRef Q (instanceRef Ready_fast)) (portRef B (instanceRef RowAd_9)) - (portRef B (instanceRef RowAd_0)) - (portRef B (instanceRef RowAd_5)) - (portRef B (instanceRef RowAd_8)) (portRef B (instanceRef RBAd_1)) - (portRef B (instanceRef RBAd_0)) (portRef B (instanceRef RowAd_1)) + (portRef B (instanceRef RowAd_5)) + (portRef B (instanceRef RowAd_7)) + (portRef B (instanceRef RBAd_0)) + (portRef B (instanceRef RowAd_6)) (portRef B (instanceRef RowAd_4)) (portRef B (instanceRef RowAd_3)) (portRef B (instanceRef RowAd_2)) - (portRef B (instanceRef RowAd_6)) - (portRef B (instanceRef RowAd_7)) + (portRef B (instanceRef RowAd_0)) + (portRef B (instanceRef RowAd_8)) (portRef B (instanceRef RA11d)) (portRef B (instanceRef Ready_fast_RNO)) )) - (net N_248_i_sx (joined + (net N_251_i_sx (joined (portRef Z (instanceRef nRCAS_0io_RNO_0)) - (portRef D (instanceRef nRCAS_0io_RNO)) + (portRef C (instanceRef nRCAS_0io_RNO)) )) (net (rename XOR8MEG_CN "XOR8MEG.CN") (joined (portRef Z (instanceRef XOR8MEG_CN)) @@ -3609,6 +3618,7 @@ )) (net VCC (joined (portRef Z (instanceRef VCC)) + (portRef D1 (instanceRef rclk_oddr)) (portRef B0 (instanceRef FS_cry_0_0)) (portRef SP (instanceRef RA10_0io)) (portRef SP (instanceRef RA11_0io)) @@ -3639,6 +3649,8 @@ )) (net GND (joined (portRef Z (instanceRef GND)) + (portRef RST (instanceRef rclk_oddr)) + (portRef D0 (instanceRef rclk_oddr)) (portRef D1 (instanceRef FS_cry_0_0)) (portRef C1 (instanceRef FS_cry_0_0)) (portRef B1 (instanceRef FS_cry_0_0)) @@ -3747,10 +3759,10 @@ (portRef O (instanceRef MAin_pad_0)) (portRef A (instanceRef RowAd_0)) (portRef A (instanceRef un9_RA_i_m2_i_m2_0)) - (portRef C (instanceRef un1_CmdEnable20_0_0_a2_0)) - (portRef C (instanceRef un1_CmdEnable20_0_0_a2_1)) + (portRef C (instanceRef un1_CmdEnable20_0_0_a2_3)) + (portRef C (instanceRef un1_CmdEnable20_0_0_a2_4)) (portRef A (instanceRef un1_CmdEnable20_0_0_0)) - (portRef B (instanceRef CmdUFMData_1_sqmuxa_0_a3_3)) + (portRef B (instanceRef CmdUFMData_1_sqmuxa_0_a2_3)) )) (net (rename MAin_0 "MAin[0]") (joined (portRef (member main 9)) @@ -3762,10 +3774,10 @@ (portRef A (instanceRef RowAd_1)) (portRef A (instanceRef un9_RA_i_m2_i_m2_1)) (portRef B (instanceRef un1_CmdEnable20_0_0_0)) - (portRef A (instanceRef un1_CmdEnable20_0_0_a3_1_1)) - (portRef C (instanceRef CmdUFMData_1_sqmuxa_0_a3_3)) + (portRef A (instanceRef un1_CmdEnable20_0_0_a2_1_1)) + (portRef C (instanceRef CmdUFMData_1_sqmuxa_0_a2_3)) (portRef A (instanceRef un1_ADWR_i_i_a2)) - (portRef D (instanceRef un1_CmdEnable20_0_0_a2_0_RNI00E51)) + (portRef D (instanceRef un1_CmdEnable20_0_0_a2_3_RNIJ3N91)) (portRef D (instanceRef C1Submitted_RNO)) )) (net (rename MAin_1 "MAin[1]") (joined @@ -3776,7 +3788,7 @@ (portRef O (instanceRef MAin_pad_2)) (portRef A (instanceRef RowAd_2)) (portRef A (instanceRef un9_RA_i_m2_i_m2_2)) - (portRef A (instanceRef un1_CmdEnable20_0_0_o3_4)) + (portRef A (instanceRef un1_CmdEnable20_0_0_o2_3)) )) (net (rename MAin_2 "MAin[2]") (joined (portRef (member main 7)) @@ -3786,7 +3798,7 @@ (portRef O (instanceRef MAin_pad_3)) (portRef A (instanceRef RowAd_3)) (portRef A (instanceRef un9_RA_i_m2_i_m2_3)) - (portRef B (instanceRef un1_CmdEnable20_0_0_o3_4)) + (portRef B (instanceRef un1_CmdEnable20_0_0_o2_3)) )) (net (rename MAin_3 "MAin[3]") (joined (portRef (member main 6)) @@ -3796,7 +3808,7 @@ (portRef O (instanceRef MAin_pad_4)) (portRef A (instanceRef RowAd_4)) (portRef A (instanceRef un9_RA_i_m2_i_m2_4)) - (portRef A (instanceRef un1_CmdEnable20_0_0_o3_3)) + (portRef A (instanceRef un1_CmdEnable20_0_0_o2_4)) )) (net (rename MAin_4 "MAin[4]") (joined (portRef (member main 5)) @@ -3806,7 +3818,7 @@ (portRef O (instanceRef MAin_pad_5)) (portRef A (instanceRef RowAd_5)) (portRef A (instanceRef un9_RA_i_m2_i_m2_5)) - (portRef C (instanceRef un1_CmdEnable20_0_0_o3_4)) + (portRef C (instanceRef un1_CmdEnable20_0_0_o2_3)) )) (net (rename MAin_5 "MAin[5]") (joined (portRef (member main 4)) @@ -3816,7 +3828,7 @@ (portRef O (instanceRef MAin_pad_6)) (portRef A (instanceRef RowAd_6)) (portRef A (instanceRef un9_RA_i_m2_i_m2_6)) - (portRef B (instanceRef un1_CmdEnable20_0_0_o3_3)) + (portRef B (instanceRef un1_CmdEnable20_0_0_o2_4)) )) (net (rename MAin_6 "MAin[6]") (joined (portRef (member main 3)) @@ -3826,7 +3838,7 @@ (portRef O (instanceRef MAin_pad_7)) (portRef A (instanceRef RowAd_7)) (portRef A (instanceRef un9_RA_i_m2_i_m2_7)) - (portRef D (instanceRef un1_CmdEnable20_0_0_o3_4)) + (portRef C (instanceRef un1_CmdEnable20_0_0_o2_4)) )) (net (rename MAin_7 "MAin[7]") (joined (portRef (member main 2)) @@ -3870,9 +3882,9 @@ )) (net (rename Din_c_0 "Din_c[0]") (joined (portRef O (instanceRef Din_pad_0)) - (portRef D (instanceRef un1_CmdEnable20_0_0_a2)) - (portRef A (instanceRef XOR8MEG_3_u_0_0_0_a2)) - (portRef C (instanceRef Cmdn8MEGEN_4_u_i_0_0)) + (portRef D (instanceRef un1_CmdEnable20_0_0_a2_2)) + (portRef A (instanceRef XOR8MEG_3_u_0_0_a2_1)) + (portRef C (instanceRef Cmdn8MEGEN_4_u_i_m2_i_0)) (portRef A (instanceRef CmdUFMWrite_3_u_0_0_0)) (portRef D (instanceRef CmdUFMData)) (portRef D (instanceRef Bank_0io_0)) @@ -3884,11 +3896,11 @@ )) (net (rename Din_c_1 "Din_c[1]") (joined (portRef O (instanceRef Din_pad_1)) - (portRef B (instanceRef un1_CmdEnable20_0_0_a2)) - (portRef C (instanceRef CmdLEDEN_4_u_i_0_0)) - (portRef B (instanceRef CmdUFMWrite_3_u_0_0_0)) + (portRef B (instanceRef un1_CmdEnable20_0_0_a2_2)) + (portRef C (instanceRef CmdLEDEN_4_u_i_m2_i_0)) (portRef B (instanceRef CmdUFMShift_3_u_0_0_0)) (portRef A (instanceRef XOR8MEG_3_u_0_0_0)) + (portRef B (instanceRef CmdUFMWrite_3_u_0_0_0)) (portRef D (instanceRef Bank_0io_1)) (portRef D (instanceRef WRD_0io_1)) )) @@ -3898,8 +3910,8 @@ )) (net (rename Din_c_2 "Din_c[2]") (joined (portRef O (instanceRef Din_pad_2)) - (portRef A (instanceRef XOR8MEG_3_u_0_0_a2_0)) - (portRef A (instanceRef un1_CmdEnable20_0_0_a2_0)) + (portRef A (instanceRef XOR8MEG_3_u_0_0_a2_2)) + (portRef A (instanceRef un1_CmdEnable20_0_0_a2_3)) (portRef D (instanceRef Bank_0io_2)) (portRef D (instanceRef WRD_0io_2)) )) @@ -3909,11 +3921,11 @@ )) (net (rename Din_c_3 "Din_c[3]") (joined (portRef O (instanceRef Din_pad_3)) - (portRef D (instanceRef CmdLEDEN_4_u_i_0_a2)) - (portRef A (instanceRef CmdLEDEN_4_u_i_0_a2_0)) - (portRef A (instanceRef XOR8MEG_3_u_0_0_a3_0_2)) - (portRef A (instanceRef un1_CmdEnable20_0_0_a2_1)) - (portRef A (instanceRef CmdValid_2_i_o2_1_o3)) + (portRef D (instanceRef Cmdn8MEGEN_4_u_i_m2_i_a2_2)) + (portRef A (instanceRef Cmdn8MEGEN_4_u_i_m2_i_a2_3)) + (portRef A (instanceRef XOR8MEG_3_u_0_0_a2_0_2)) + (portRef A (instanceRef un1_CmdEnable20_0_0_a2_4)) + (portRef A (instanceRef CmdValid_2_i_o2_0_o2)) (portRef D (instanceRef Bank_0io_3)) (portRef D (instanceRef WRD_0io_3)) )) @@ -3923,12 +3935,12 @@ )) (net (rename Din_c_4 "Din_c[4]") (joined (portRef O (instanceRef Din_pad_4)) - (portRef B (instanceRef CmdLEDEN_4_u_i_0_a3_0_0)) - (portRef C (instanceRef un1_CmdEnable20_0_0_a2)) - (portRef B (instanceRef CmdLEDEN_4_u_i_0_a2)) - (portRef B (instanceRef XOR8MEG_3_u_0_0_0_a2)) - (portRef B (instanceRef CmdValid_2_i_o2_1_o3)) - (portRef A (instanceRef XOR8MEG_3_u_0_0_0_a3)) + (portRef B (instanceRef CmdLEDEN_4_u_i_m2_i_a2_0_0)) + (portRef C (instanceRef un1_CmdEnable20_0_0_a2_2)) + (portRef B (instanceRef Cmdn8MEGEN_4_u_i_m2_i_a2_2)) + (portRef B (instanceRef XOR8MEG_3_u_0_0_a2_1)) + (portRef B (instanceRef CmdValid_2_i_o2_0_o2)) + (portRef A (instanceRef XOR8MEG_3_u_0_0_0_a2)) (portRef D (instanceRef Bank_0io_4)) (portRef D (instanceRef WRD_0io_4)) )) @@ -3938,12 +3950,12 @@ )) (net (rename Din_c_5 "Din_c[5]") (joined (portRef O (instanceRef Din_pad_5)) - (portRef A (instanceRef CmdLEDEN_4_u_i_0_a3_0_0)) - (portRef C (instanceRef CmdLEDEN_4_u_i_0_a2)) - (portRef B (instanceRef XOR8MEG_3_u_0_0_a2_0)) - (portRef B (instanceRef CmdLEDEN_4_u_i_0_a2_0)) - (portRef C (instanceRef CmdValid_2_i_o2_1_o3)) - (portRef B (instanceRef XOR8MEG_3_u_0_0_0_a3)) + (portRef A (instanceRef CmdLEDEN_4_u_i_m2_i_a2_0_0)) + (portRef C (instanceRef Cmdn8MEGEN_4_u_i_m2_i_a2_2)) + (portRef B (instanceRef XOR8MEG_3_u_0_0_a2_2)) + (portRef B (instanceRef Cmdn8MEGEN_4_u_i_m2_i_a2_3)) + (portRef C (instanceRef CmdValid_2_i_o2_0_o2)) + (portRef B (instanceRef XOR8MEG_3_u_0_0_0_a2)) (portRef D (instanceRef Bank_0io_5)) (portRef D (instanceRef WRD_0io_5)) )) @@ -3953,11 +3965,11 @@ )) (net (rename Din_c_6 "Din_c[6]") (joined (portRef O (instanceRef Din_pad_6)) - (portRef D (instanceRef CmdLEDEN_4_u_i_0_a3_0_0)) + (portRef D (instanceRef CmdLEDEN_4_u_i_m2_i_a2_0_0)) (portRef A (instanceRef RA11d)) (portRef A (instanceRef XOR8MEG_3_u_0_0_o2_1)) - (portRef B (instanceRef un1_CmdEnable20_0_0_a2_0)) - (portRef B (instanceRef un1_CmdEnable20_0_0_a2_1)) + (portRef B (instanceRef un1_CmdEnable20_0_0_a2_3)) + (portRef B (instanceRef un1_CmdEnable20_0_0_a2_4)) (portRef D (instanceRef Bank_0io_6)) (portRef D (instanceRef WRD_0io_6)) )) @@ -3967,8 +3979,8 @@ )) (net (rename Din_c_7 "Din_c[7]") (joined (portRef O (instanceRef Din_pad_7)) - (portRef C (instanceRef CmdLEDEN_4_u_i_0_a3_0_0)) - (portRef A (instanceRef un1_CmdEnable20_0_0_a2)) + (portRef C (instanceRef CmdLEDEN_4_u_i_m2_i_a2_0_0)) + (portRef A (instanceRef un1_CmdEnable20_0_0_a2_2)) (portRef B (instanceRef XOR8MEG_3_u_0_0_o2_1)) (portRef D (instanceRef Bank_0io_7)) (portRef D (instanceRef WRD_0io_7)) @@ -4020,7 +4032,7 @@ )) (net nCRAS_c (joined (portRef O (instanceRef nCRAS_pad)) - (portRef C (instanceRef LED_pad_RNO)) + (portRef D (instanceRef LED_pad_RNO)) (portRef A (instanceRef nCRAS_pad_RNIBPVB)) (portRef A (instanceRef RASr_RNO)) )) @@ -4030,7 +4042,7 @@ )) (net nFWE_c (joined (portRef O (instanceRef nFWE_pad)) - (portRef C (instanceRef un1_CmdEnable20_0_0_o3_3)) + (portRef D (instanceRef un1_CmdEnable20_0_0_o2_4)) (portRef B (instanceRef nCCAS_pad_RNI01SJ)) (portRef A (instanceRef FWEr_RNO)) )) @@ -4233,6 +4245,7 @@ (net RCLK_c (joined (portRef O (instanceRef RCLK_pad)) (portRef RCLK_c (instanceRef ufmefb)) + (portRef SCLK (instanceRef rclk_oddr)) (portRef CK (instanceRef CASr)) (portRef CK (instanceRef CASr2)) (portRef CK (instanceRef CASr3)) @@ -4304,12 +4317,19 @@ (portRef RCLK) (portRef I (instanceRef RCLK_pad)) )) + (net RCLKout_c (joined + (portRef Q (instanceRef rclk_oddr)) + (portRef I (instanceRef RCLKout_pad)) + )) + (net RCLKout (joined + (portRef O (instanceRef RCLKout_pad)) + (portRef RCLKout) + )) (net RCKE_c (joined (portRef Q (instanceRef RCKE)) - (portRef C (instanceRef nRCS_9_u_i_0_o3)) - (portRef B (instanceRef nRWE_s_i_0_tz_0)) + (portRef C (instanceRef nRCS_9_u_i_0_0)) + (portRef B (instanceRef nRWE_s_i_tz_0)) (portRef I (instanceRef RCKE_pad)) - (portRef B (instanceRef nRRAS_0io_RNO)) )) (net RCKE (joined (portRef O (instanceRef RCKE_pad)) @@ -4355,15 +4375,15 @@ (portRef O (instanceRef RDQML_pad)) (portRef RDQML) )) - (net N_757_0 (joined + (net N_705_0 (joined (portRef Z (instanceRef InitReady_RNO)) (portRef D (instanceRef InitReady)) )) - (net N_758_0 (joined + (net N_706_0 (joined (portRef Z (instanceRef Ready_RNO)) (portRef D (instanceRef Ready)) )) - (net N_759_0 (joined + (net N_707_0 (joined (portRef Z (instanceRef Ready_fast_RNO)) (portRef D (instanceRef Ready_fast)) )) @@ -4389,16 +4409,6 @@ (portRef SCLK (instanceRef WRD_0io_1)) (portRef SCLK (instanceRef WRD_0io_0)) )) - (net N_360_i (joined - (portRef Z (instanceRef nRCS_9_u_i_0_o2_1_RNIL2K71_0)) - (portRef SP (instanceRef IS_3)) - (portRef SP (instanceRef IS_2)) - (portRef SP (instanceRef IS_1)) - )) - (net N_246_i (joined - (portRef Z (instanceRef nRRAS_0io_RNO)) - (portRef D (instanceRef nRRAS_0io)) - )) (net (rename IS_i_0 "IS_i[0]") (joined (portRef Z (instanceRef RA10_0io_RNO)) (portRef D (instanceRef RA10_0io)) @@ -4408,13 +4418,21 @@ (portRef CD (instanceRef S_1)) (portRef CD (instanceRef S_0)) )) - (net (rename wb_dati_5_1_iv_0_o3_am_5 "wb_dati_5_1_iv_0_o3_am[5]") (joined - (portRef Z (instanceRef wb_dati_5_1_iv_0_o3_am_5)) - (portRef BLUT (instanceRef wb_dati_5_1_iv_0_o3_5)) + (net (rename wb_dati_5_1_iv_0_0_o2_am_5 "wb_dati_5_1_iv_0_0_o2_am[5]") (joined + (portRef Z (instanceRef wb_dati_5_1_iv_0_0_o2_am_5)) + (portRef BLUT (instanceRef wb_dati_5_1_iv_0_0_o2_5)) )) - (net (rename wb_dati_5_1_iv_0_o3_bm_5 "wb_dati_5_1_iv_0_o3_bm[5]") (joined - (portRef Z (instanceRef wb_dati_5_1_iv_0_o3_bm_5)) - (portRef ALUT (instanceRef wb_dati_5_1_iv_0_o3_5)) + (net (rename wb_dati_5_1_iv_0_0_o2_bm_5 "wb_dati_5_1_iv_0_0_o2_bm[5]") (joined + (portRef Z (instanceRef wb_dati_5_1_iv_0_0_o2_bm_5)) + (portRef ALUT (instanceRef wb_dati_5_1_iv_0_0_o2_5)) + )) + (net (rename wb_adr_5_i_0_1_am_0 "wb_adr_5_i_0_1_am[0]") (joined + (portRef Z (instanceRef wb_adr_5_i_0_1_am_0)) + (portRef BLUT (instanceRef wb_adr_5_i_0_1_0)) + )) + (net (rename wb_adr_5_i_0_1_bm_0 "wb_adr_5_i_0_1_bm[0]") (joined + (portRef Z (instanceRef wb_adr_5_i_0_1_bm_0)) + (portRef ALUT (instanceRef wb_adr_5_i_0_1_0)) )) (net N_1 (joined (portRef CIN (instanceRef FS_cry_0_0)) diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.jed b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.jed index eeacc83..e50b3ec 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.jed +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.jed @@ -2,7 +2,7 @@ NOTE Diamond (64-bit) 3.12.1.454 JEDEC Compatible Fuse File.* NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation.* NOTE All Rights Reserved.* -NOTE DATE CREATED: Thu Sep 21 05:40:14 2023* +NOTE DATE CREATED: Sat Nov 18 02:06:26 2023* NOTE DESIGN NAME: RAM2GS_LCMXO2_640HC_impl1.ncd* NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100* NOTE JEDEC FILE STATUS: Final Version 1.95* @@ -16,6 +16,7 @@ NOTE PINS nRCAS : 52 : out* NOTE PINS nRRAS : 54 : out* NOTE PINS nRWE : 49 : out* NOTE PINS RCKE : 53 : out* +NOTE PINS RCLKout : 60 : out* NOTE PINS RCLK : 63 : in* NOTE PINS nRCS : 57 : out* NOTE PINS RD[7] : 43 : inout* @@ -37,7 +38,7 @@ NOTE PINS RA[3] : 71 : out* NOTE PINS RA[2] : 69 : out* NOTE PINS RA[1] : 67 : out* NOTE PINS RA[0] : 66 : out* -NOTE PINS RBA[1] : 60 : out* +NOTE PINS RBA[1] : 47 : out* NOTE PINS RBA[0] : 58 : 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+00000000010000000000000000000000000000001111111111111111111111111111111111111111111111111111111101011110000000000000000000000000 11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 * NOTE END CONFIG DATA* -L47744 +L47488 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 @@ -1425,10 +1426,10 @@ L171648 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 * -C374D* +C1984* NOTE FEATURE_ROW* E0000000000000000000000000000000000000000000000000000000000000000 0000010001100000* NOTE User Electronic Signature Data* UH00000000* -00B7 +0872 diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mrp b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mrp index 91dc51a..aca7916 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mrp +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mrp @@ -15,7 +15,7 @@ Target Vendor: LATTICE Target Device: LCMXO2-640HCTQFP100 Target Performance: 4 Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454 -Mapped on: 09/21/23 05:39:43 +Mapped on: 11/18/23 02:05:52 Design Summary -------------- @@ -27,12 +27,24 @@ Design Summary SLICEs as Logic/ROM: 120 out of 320 (38%) SLICEs as RAM: 0 out of 240 (0%) SLICEs as Carry: 10 out of 320 (3%) - Number of LUT4s: 237 out of 640 (37%) - Number used as logic LUTs: 217 + Number of LUT4s: 238 out of 640 (37%) + Number used as logic LUTs: 218 Number used as distributed RAM: 0 Number used as ripple logic: 20 Number used as shift registers: 0 - Number of PIO sites used: 63 + 4(JTAG) out of 79 (85%) + Number of PIO sites used: 64 + 4(JTAG) out of 79 (86%) + Number of IDDR/ODDR/TDDR cells used: 1 out of 237 (0%) + Number of IDDR cells: 0 + Number of ODDR cells: 1 + Number of TDDR cells: 0 + Number of PIO using at least one IDDR/ODDR/TDDR: 1 (0 differential) + Number of PIO using IDDR only: 0 (0 differential) + Number of PIO using ODDR only: 1 (0 differential) + Number of PIO using TDDR only: 0 (0 differential) + Number of PIO using IDDR/ODDR: 0 (0 differential) + Number of PIO using IDDR/TDDR: 0 (0 differential) + Number of PIO using ODDR/TDDR: 0 (0 differential) + Number of PIO using IDDR/ODDR/TDDR: 0 (0 differential) Number of block RAMs: 0 out of 2 (0%) Number of GSRs: 0 out of 1 (0%) EFB used : Yes @@ -48,29 +60,29 @@ Design Summary Number of DCMA: 0 out of 2 (0%) Notes:- 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of - distributed RAMs) + 2*(Number of ripple logic) - 2. Number of logic LUT4s does not include count of distributed RAM and - ripple logic. - Number of clocks: 4 - Net PHI2_c: 20 loads, 9 rising, 11 falling (Driver: PIO PHI2 ) - Net RCLK_c: 47 loads, 47 rising, 0 falling (Driver: PIO RCLK ) - Net nCRAS_c: 9 loads, 0 rising, 9 falling (Driver: PIO nCRAS ) - Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS ) - Number of Clock Enables: 5 - Net N_178: 1 loads, 1 LSLICEs - Net XOR8MEG18: 5 loads, 5 LSLICEs - Net N_360_i: 2 loads, 2 LSLICEs Page 1 -Design: RAM2GS Date: 09/21/23 05:39:43 +Design: RAM2GS Date: 11/18/23 02:05:52 Design Summary (cont) --------------------- - Net un1_wb_rst14_i_0: 9 loads, 9 LSLICEs + distributed RAMs) + 2*(Number of ripple logic) + 2. Number of logic LUT4s does not include count of distributed RAM and + ripple logic. + Number of clocks: 4 + Net PHI2_c: 20 loads, 9 rising, 11 falling (Driver: PIO PHI2 ) + Net RCLK_c: 48 loads, 48 rising, 0 falling (Driver: PIO RCLK ) + Net nCRAS_c: 9 loads, 0 rising, 9 falling (Driver: PIO nCRAS ) + Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS ) + Number of Clock Enables: 5 + Net wb_cyc_stb_2_sqmuxa_i_0_0: 1 loads, 1 LSLICEs + Net XOR8MEG18: 5 loads, 5 LSLICEs + Net N_126_i: 9 loads, 9 LSLICEs + Net N_261_i: 2 loads, 2 LSLICEs Net CmdUFMData_1_sqmuxa: 1 loads, 1 LSLICEs Number of LSRs: 5 Net RA10s_i: 1 loads, 0 LSLICEs @@ -80,16 +92,16 @@ Design Summary (cont) Net RASr2: 2 loads, 2 LSLICEs Number of nets driven by tri-state buffers: 0 Top 10 highest fanout non-clock nets: - Net InitReady: 41 loads - Net FS[11]: 23 loads + Net InitReady: 40 loads Net FS[13]: 22 loads - Net FS[10]: 21 loads - Net FS[12]: 21 loads - Net FS[9]: 20 loads - Net FS[14]: 18 loads - Net CO0: 15 loads + Net FS[11]: 21 loads + Net FS[12]: 19 loads + Net FS[14]: 19 loads + Net FS[10]: 18 loads + Net FS[9]: 17 loads + Net Ready: 14 loads Net Ready_fast: 14 loads - Net N_214: 13 loads + Net CO0: 12 loads @@ -114,6 +126,16 @@ IO (PIO) Attributes +---------------------+-----------+-----------+------------+ | IO Name | Direction | Levelmode | IO | | | | IO_TYPE | Register | + + Page 2 + + + + +Design: RAM2GS Date: 11/18/23 02:05:52 + +IO (PIO) Attributes (cont) +-------------------------- +---------------------+-----------+-----------+------------+ | RD[0] | BIDIR | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ @@ -126,16 +148,6 @@ IO (PIO) Attributes | RDQMH | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | nRCAS | OUTPUT | LVCMOS33 | OUT | - - Page 2 - - - - -Design: RAM2GS Date: 09/21/23 05:39:43 - -IO (PIO) Attributes (cont) --------------------------- +---------------------+-----------+-----------+------------+ | nRRAS | OUTPUT | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ @@ -143,6 +155,8 @@ IO (PIO) Attributes (cont) +---------------------+-----------+-----------+------------+ | RCKE | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ +| RCLKout | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ | RCLK | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | nRCS | OUTPUT | LVCMOS33 | OUT | @@ -178,6 +192,16 @@ IO (PIO) Attributes (cont) | RA[4] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | RA[3] | OUTPUT | LVCMOS33 | | + + Page 3 + + + + +Design: RAM2GS Date: 11/18/23 02:05:52 + +IO (PIO) Attributes (cont) +-------------------------- +---------------------+-----------+-----------+------------+ | RA[2] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ @@ -192,16 +216,6 @@ IO (PIO) Attributes (cont) | LED | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | nFWE | INPUT | LVCMOS33 | | - - Page 3 - - - - -Design: RAM2GS Date: 09/21/23 05:39:43 - -IO (PIO) Attributes (cont) --------------------------- +---------------------+-----------+-----------+------------+ | nCRAS | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ @@ -244,6 +258,16 @@ IO (PIO) Attributes (cont) | MAin[9] | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | MAin[8] | INPUT | LVCMOS33 | | + + Page 4 + + + + +Design: RAM2GS Date: 11/18/23 02:05:52 + +IO (PIO) Attributes (cont) +-------------------------- +---------------------+-----------+-----------+------------+ | MAin[7] | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ @@ -258,16 +282,6 @@ IO (PIO) Attributes (cont) | MAin[2] | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | MAin[1] | INPUT | LVCMOS33 | | - - Page 4 - - - - -Design: RAM2GS Date: 09/21/23 05:39:43 - -IO (PIO) Attributes (cont) --------------------------- +---------------------+-----------+-----------+------------+ | MAin[0] | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ @@ -279,7 +293,6 @@ Block GSR_INST undriven or does not drive anything - clipped. Signal nCRAS_c_i was merged into signal nCRAS_c Signal RASr2_i was merged into signal RASr2 Signal XOR8MEG.CN was merged into signal PHI2_c -Signal GND undriven or does not drive anything - clipped. Signal ufmefb/VCC undriven or does not drive anything - clipped. Signal ufmefb/GND undriven or does not drive anything - clipped. Signal FS_s_0_S1[17] undriven or does not drive anything - clipped. @@ -311,6 +324,16 @@ Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped. Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped. Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped. Signal ufmefb/I2C2SCLO undriven or does not drive anything - clipped. + + Page 5 + + + + +Design: RAM2GS Date: 11/18/23 02:05:52 + +Removed logic (cont) +-------------------- Signal ufmefb/I2C1SDAOEN undriven or does not drive anything - clipped. Signal ufmefb/I2C1SDAO undriven or does not drive anything - clipped. Signal ufmefb/I2C1SCLOEN undriven or does not drive anything - clipped. @@ -324,16 +347,6 @@ Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped. Signal ufmefb/PLLDATO6 undriven or does not drive anything - clipped. Signal ufmefb/PLLDATO7 undriven or does not drive anything - clipped. Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped. - - Page 5 - - - - -Design: RAM2GS Date: 09/21/23 05:39:43 - -Removed logic (cont) --------------------- Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped. Signal ufmefb/PLLADRO2 undriven or does not drive anything - clipped. Signal ufmefb/PLLADRO3 undriven or does not drive anything - clipped. @@ -354,7 +367,6 @@ Signal N_1 undriven or does not drive anything - clipped. Block nCRAS_pad_RNIBPVB was optimized away. Block RASr2_RNIAFR1 was optimized away. Block XOR8MEG.CN was optimized away. -Block GND was optimized away. Block ufmefb/VCC was optimized away. Block ufmefb/GND was optimized away. @@ -378,6 +390,16 @@ Embedded Functional Block Connection Summary I2C Function Summary: -------------------- None + + Page 6 + + + + +Design: RAM2GS Date: 11/18/23 02:05:52 + +Embedded Functional Block Connection Summary (cont) +--------------------------------------------------- SPI Function Summary: -------------------- None @@ -391,16 +413,6 @@ Embedded Functional Block Connection Summary Available General Purpose Flash Memory: 191 Pages (191*128 Bits) - Page 6 - - - - -Design: RAM2GS Date: 09/21/23 05:39:43 - -Embedded Functional Block Connection Summary (cont) ---------------------------------------------------- - EBR Blocks with Unique Initialization Data: 0 @@ -436,18 +448,6 @@ Run Time and Memory Usage - - - - - - - - - - - - diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.pad b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.pad index 01e7c43..287e0b8 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.pad +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.pad @@ -6,7 +6,7 @@ Performance Grade: 4 PACKAGE: TQFP100 Package Status: Final Version 1.39 -Thu Sep 21 05:39:54 2023 +Sat Nov 18 02:06:05 2023 Pinout by Port Name: +-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ @@ -55,9 +55,10 @@ Pinout by Port Name: | RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW | | RA[9] | 62/1 | LVCMOS33_OUT | PR5D | | | DRIVE:4mA SLEW:SLOW | | RBA[0] | 58/1 | LVCMOS33_OUT | PR6C | | | DRIVE:4mA SLEW:SLOW | -| RBA[1] | 60/1 | LVCMOS33_OUT | PR6A | | | DRIVE:4mA SLEW:SLOW | +| RBA[1] | 47/2 | LVCMOS33_OUT | PB14B | | | DRIVE:4mA SLEW:SLOW | | RCKE | 53/1 | LVCMOS33_OUT | PR7B | | | DRIVE:4mA SLEW:SLOW | | RCLK | 63/1 | LVCMOS33_IN | PR5C | | | CLAMP:ON HYSTERESIS:SMALL | +| RCLKout | 60/1 | LVCMOS33_OUT | PR6A | | | DRIVE:24mA SLEW:FAST | | RDQMH | 51/1 | LVCMOS33_OUT | PR7D | | | DRIVE:4mA SLEW:SLOW | | RDQML | 48/2 | LVCMOS33_OUT | PB14C | | | DRIVE:4mA SLEW:SLOW | | RD[0] | 36/2 | LVCMOS33_BIDI | PB10A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | @@ -134,7 +135,7 @@ Pinout by Pin Number: | 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB12C | | | | | 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB12D | | | | | 45/2 | unused, PULL:DOWN | | | PB14A | | | | -| 47/2 | unused, PULL:DOWN | | | PB14B | | | | +| 47/2 | RBA[1] | LOCATED | LVCMOS33_OUT | PB14B | | | | | 48/2 | RDQML | LOCATED | LVCMOS33_OUT | PB14C | SN | | | | 49/2 | nRWE | LOCATED | LVCMOS33_OUT | PB14D | SI/SISPI | | | | 51/1 | RDQMH | LOCATED | LVCMOS33_OUT | PR7D | | | | @@ -144,7 +145,7 @@ Pinout by Pin Number: | 57/1 | nRCS | LOCATED | LVCMOS33_OUT | PR6D | | | | | 58/1 | RBA[0] | LOCATED | LVCMOS33_OUT | PR6C | | | | | 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR6B | | | | -| 60/1 | RBA[1] | LOCATED | LVCMOS33_OUT | PR6A | | | | +| 60/1 | RCLKout | LOCATED | LVCMOS33_OUT | PR6A | | | | | 62/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5D | PCLKC1_0 | | | | 63/1 | RCLK | LOCATED | LVCMOS33_IN | PR5C | PCLKT1_0 | | | | 64/1 | RA[10] | LOCATED | LVCMOS33_OUT | PR5B | | | | @@ -238,9 +239,10 @@ LOCATE COMP "RA[7]" SITE "75"; LOCATE COMP "RA[8]" SITE "65"; LOCATE COMP "RA[9]" SITE "62"; LOCATE COMP "RBA[0]" SITE "58"; -LOCATE COMP "RBA[1]" SITE "60"; +LOCATE COMP "RBA[1]" SITE "47"; LOCATE COMP "RCKE" SITE "53"; LOCATE COMP "RCLK" SITE "63"; +LOCATE COMP "RCLKout" SITE "60"; LOCATE COMP "RDQMH" SITE "51"; LOCATE COMP "RDQML" SITE "48"; LOCATE COMP "RD[0]" SITE "36"; @@ -269,5 +271,5 @@ Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Thu Sep 21 05:39:58 2023 +Sat Nov 18 02:06:08 2023 diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.prf b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.prf index 3a2cc62..cc2a9db 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.prf +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.prf @@ -1,5 +1,5 @@ SCHEMATIC START ; -# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Thu Sep 21 05:39:44 2023 +# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Sat Nov 18 02:05:53 2023 SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ; LOCATE COMP "RD[0]" SITE "36" ; @@ -11,6 +11,7 @@ LOCATE COMP "nRCAS" SITE "52" ; LOCATE COMP "nRRAS" SITE "54" ; LOCATE COMP "nRWE" SITE "49" ; LOCATE COMP "RCKE" SITE "53" ; +LOCATE COMP "RCLKout" SITE "60" ; LOCATE COMP "RCLK" SITE "63" ; LOCATE COMP "nRCS" SITE "57" ; LOCATE COMP "RD[7]" SITE "43" ; @@ -32,7 +33,7 @@ LOCATE COMP "RA[3]" SITE "71" ; LOCATE COMP "RA[2]" SITE "69" ; LOCATE COMP "RA[1]" SITE "67" ; LOCATE COMP "RA[0]" SITE "66" ; -LOCATE COMP "RBA[1]" SITE "60" ; +LOCATE COMP "RBA[1]" SITE "47" ; LOCATE COMP "RBA[0]" SITE "58" ; LOCATE COMP "LED" SITE "34" ; LOCATE COMP "nFWE" SITE "15" ; @@ -110,4 +111,5 @@ OUTPUT PORT "RD[4]" LOAD 9.000000 pF ; OUTPUT PORT "RD[5]" LOAD 9.000000 pF ; OUTPUT PORT "RD[6]" LOAD 9.000000 pF ; OUTPUT PORT "RD[7]" LOAD 9.000000 pF ; +OUTPUT PORT "RCLKout" LOAD 5.000000 pF ; COMMERCIAL ; diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.srr b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.srr index 1652b0c..c8551f9 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.srr +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.srr @@ -3,7 +3,7 @@ #OS: Windows 8 6.2 #Hostname: ZANEMACWIN11 -# Thu Sep 21 05:39:33 2023 +# Sat Nov 18 02:05:39 2023 #Implementation: impl1 @@ -51,13 +51,17 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202 @I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v" (library work) @I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-640HC\REFB.v" (library work) Verilog syntax check successful! +File \\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v changed - recompiling Selecting top level module RAM2GS +@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1601:7:1601:12|Synthesizing module ODDRXE in library work. +Running optimization stage 1 on ODDRXE ....... +Finished optimization stage 1 on ODDRXE (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB) @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work. Running optimization stage 1 on VHI ....... -Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 98MB) +Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB) @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work. Running optimization stage 1 on VLO ....... -Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB) +Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB) @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work. Running optimization stage 1 on EFB ....... Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB) @@ -77,13 +81,15 @@ Running optimization stage 2 on VLO ....... Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) Running optimization stage 2 on VHI ....... Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) +Running optimization stage 2 on ODDRXE ....... +Finished optimization stage 2 on ODDRXE (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) -At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB) +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Sep 21 05:39:33 2023 +# Sat Nov 18 02:05:40 2023 ###########################################################] ###########################################################[ @@ -110,7 +116,7 @@ At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Sep 21 05:39:34 2023 +# Sat Nov 18 02:05:40 2023 ###########################################################] @@ -120,12 +126,12 @@ For a summary of runtime and memory usage for all design units, please see file: @END -At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB) +At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Sep 21 05:39:34 2023 +# Sat Nov 18 02:05:40 2023 ###########################################################] ###########################################################[ @@ -146,18 +152,17 @@ Implementation : impl1 Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ @N|Running in 64-bit mode +File \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Sep 21 05:39:35 2023 +# Sat Nov 18 02:05:42 2023 ###########################################################] -Premap Report - -# Thu Sep 21 05:39:35 2023 +# Sat Nov 18 02:05:42 2023 Copyright (C) 1994-2021 Synopsys, Inc. @@ -176,10 +181,10 @@ Implementation : impl1 Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @ -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB) +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB) -Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 140MB) +Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 140MB) Reading constraint file: \\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc @L: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1_scck.rpt @@ -203,7 +208,6 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h @W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. @N: FX493 |Applying initial value "0" on instance Ready. @N: FX493 |Applying initial value "0" on instance RCKE. -@N: FX493 |Applying initial value "0" on instance LEDEN. @N: FX493 |Applying initial value "0" on instance n8MEGEN. @N: FX493 |Applying initial value "1" on instance nRCAS. @N: FX493 |Applying initial value "0" on instance CmdLEDEN. @@ -229,11 +233,11 @@ Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapse Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB) -Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) +Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB) @N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS -Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB) @@ -317,12 +321,10 @@ Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 103MB peak: 185MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu Sep 21 05:39:37 2023 +# Sat Nov 18 02:05:43 2023 ###########################################################] -Map & Optimize Report - -# Thu Sep 21 05:39:37 2023 +# Sat Nov 18 02:05:44 2023 Copyright (C) 1994-2021 Synopsys, Inc. @@ -341,22 +343,22 @@ Implementation : impl1 Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @ -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB) +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB) @N: MF916 |Option synthesis_strategy=base is enabled. @N: MF248 |Running in 64-bit mode. @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 139MB) +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB) -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 139MB) +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB) -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB) +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB) @@ -365,8 +367,8 @@ Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapse Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB) -@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":163:4:163:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] -@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":150:4:150:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] +@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":166:4:166:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] +@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":153:4:153:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] @N: FX493 |Applying initial value "0" on instance IS[0]. @W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. @N: FX493 |Applying initial value "0" on instance IS[1]. @@ -376,7 +378,7 @@ Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00 Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 185MB peak: 185MB) -Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 187MB) +Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB) Available hyper_sources - for debug and ip models @@ -389,7 +391,7 @@ Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CP Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 187MB) -Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 187MB) +Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB) @@ -398,16 +400,16 @@ Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CP Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB) -Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 197MB peak: 197MB) +Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 196MB peak: 196MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ - 1 0h:00m:01s -2.98ns 201 / 106 - 2 0h:00m:01s -2.98ns 217 / 106 + 1 0h:00m:01s -2.98ns 202 / 106 + 2 0h:00m:01s -2.98ns 215 / 106 3 0h:00m:01s -2.76ns 215 / 106 -@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":121:4:121:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing. -@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":304:4:304:9|Replicating instance CmdValid (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing. -@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":163:4:163:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 11 loads 1 time to improve timing. +@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":124:4:124:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing. +@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":307:4:307:9|Replicating instance CmdValid (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing. +@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":166:4:166:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing. Timing driven replication report Added 3 Registers via timing driven replication Added 1 LUTs via timing driven replication @@ -421,10 +423,10 @@ Finished technology timing optimizations and critical path resynthesis (Real Tim @N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. -Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 198MB peak: 198MB) +Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 197MB peak: 197MB) -Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 160MB peak: 198MB) +Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 198MB) Writing Analyst data base \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_m.srm @@ -434,14 +436,15 @@ Writing EDIF Netlist and constraint files @N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.edi @N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF -Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 203MB peak: 203MB) +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 202MB peak: 202MB) -Finished Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 203MB peak: 203MB) +Finished Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 202MB peak: 203MB) Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 201MB peak: 203MB) +@W: MT246 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":43:11:43:19|Blackbox ODDRXE is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W: MT246 :"\\mac\icloud\repos\ram2gs\cpld\lcmxo2-640hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @N: MT615 |Found clock RCLK with period 16.00ns @N: MT615 |Found clock PHI2 with period 350.00ns @@ -450,7 +453,7 @@ Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:0 ##### START OF TIMING REPORT #####[ -# Timing report written on Thu Sep 21 05:39:41 2023 +# Timing report written on Sat Nov 18 02:05:48 2023 # @@ -501,7 +504,7 @@ Starting Ending | constraint slack | constraint slack | constraint --------------------------------------------------------------------------------------------------------------- System RCLK | 16.000 12.918 | No paths - | No paths - | No paths - RCLK System | 16.000 14.956 | No paths - | No paths - | No paths - -RCLK RCLK | 16.000 9.040 | No paths - | No paths - | No paths - +RCLK RCLK | 16.000 9.237 | No paths - | No paths - | No paths - RCLK PHI2 | 2.000 0.216 | No paths - | 1.000 -0.676 | No paths - RCLK nCRAS | No paths - | No paths - | 1.000 -0.784 | No paths - PHI2 RCLK | No paths - | No paths - | No paths - | 1.000 -1.828 @@ -540,30 +543,30 @@ CmdLEDEN PHI2 FD1P3AX Q CmdLEDEN 1.044 Cmdn8MEGEN PHI2 FD1P3AX Q Cmdn8MEGEN 1.044 -1.589 CmdUFMWrite PHI2 FD1P3AX Q CmdUFMWrite 1.044 -0.572 CmdUFMData PHI2 FD1P3AX Q CmdUFMData 0.972 -0.500 -Bank_0io[0] PHI2 IFS1P3DX Q Bank[0] 0.972 169.081 Bank_0io[1] PHI2 IFS1P3DX Q Bank[1] 0.972 169.081 Bank_0io[2] PHI2 IFS1P3DX Q Bank[2] 0.972 169.081 +Bank_0io[3] PHI2 IFS1P3DX Q Bank[3] 0.972 169.081 ========================================================================================== Ending Points with Worst Slack ****************************** - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------------ -wb_adr[0] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828 -wb_adr[1] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828 -wb_adr[2] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828 -wb_adr[3] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828 -wb_adr[4] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828 -wb_adr[5] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828 -wb_adr[6] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828 -wb_adr[7] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828 -wb_dati[0] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828 -wb_dati[1] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828 -========================================================================================= + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------- +wb_adr[0] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +wb_adr[1] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +wb_adr[2] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +wb_adr[3] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +wb_adr[4] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +wb_adr[5] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +wb_adr[6] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +wb_adr[7] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +wb_dati[0] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +wb_dati[1] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +================================================================================ @@ -594,7 +597,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r - CmdUFMShift Net - - - - 2 CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r - CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r - -un1_wb_rst14_i_0 Net - - - - 17 +N_126_i Net - - - - 17 wb_adr[0] FD1P3AX SP In 0.000 2.357 r - ========================================================================================= @@ -622,7 +625,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r - CmdUFMShift Net - - - - 2 CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r - CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r - -un1_wb_rst14_i_0 Net - - - - 17 +N_126_i Net - - - - 17 wb_adr[7] FD1P3AX SP In 0.000 2.357 r - ========================================================================================= @@ -650,7 +653,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r - CmdUFMShift Net - - - - 2 CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r - CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r - -un1_wb_rst14_i_0 Net - - - - 17 +N_126_i Net - - - - 17 wb_adr[6] FD1P3AX SP In 0.000 2.357 r - ========================================================================================= @@ -678,7 +681,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r - CmdUFMShift Net - - - - 2 CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r - CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r - -un1_wb_rst14_i_0 Net - - - - 17 +N_126_i Net - - - - 17 wb_adr[5] FD1P3AX SP In 0.000 2.357 r - ========================================================================================= @@ -706,7 +709,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r - CmdUFMShift Net - - - - 2 CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r - CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r - -un1_wb_rst14_i_0 Net - - - - 17 +N_126_i Net - - - - 17 wb_adr[4] FD1P3AX SP In 0.000 2.357 r - ========================================================================================= @@ -729,13 +732,13 @@ Instance Reference Type Pin Net Time Slac Ready_fast RCLK FD1S3AX Q Ready_fast 1.256 -0.784 LEDEN RCLK FD1S3AX Q LEDEN 1.148 -0.676 n8MEGEN RCLK FD1S3AX Q n8MEGEN 1.108 -0.636 -IS[1] RCLK FD1P3AX Q IS[1] 1.204 9.040 -IS[2] RCLK FD1P3AX Q IS[2] 1.188 9.056 -IS[3] RCLK FD1P3AX Q IS[3] 1.148 9.096 -InitReady RCLK FD1S3AX Q InitReady 1.339 9.228 -FS[15] RCLK FD1S3AX Q FS[15] 1.228 9.339 -FS[16] RCLK FD1S3AX Q FS[16] 1.188 9.379 -FS[17] RCLK FD1S3AX Q FS[17] 1.188 9.379 +InitReady RCLK FD1S3AX Q InitReady 1.337 9.237 +FS[16] RCLK FD1S3AX Q FS[16] 1.204 9.371 +FS[17] RCLK FD1S3AX Q FS[17] 1.204 9.371 +FS[15] RCLK FD1S3AX Q FS[15] 1.188 9.387 +S[0] RCLK FD1S3IX Q CO0 1.244 9.873 +S[1] RCLK FD1S3IX Q S[1] 1.236 9.881 +RASr2 RCLK FD1S3AX Q RASr2 1.228 9.889 ================================================================================== @@ -832,7 +835,35 @@ Path information for path number 3: Number of logic level(s): 1 Starting point: Ready_fast / Q - Ending point: RowA[0] / D + Ending point: RBA_0io[1] / D + The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK + The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin SCLK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------- +Ready_fast FD1S3AX Q Out 1.256 1.256 r - +Ready_fast Net - - - - 14 +RBAd[1] ORCALUT4 B In 0.000 1.256 r - +RBAd[1] ORCALUT4 Z Out 0.617 1.873 r - +RBAd_0[1] Net - - - - 1 +RBA_0io[1] OFS1P3DX D In 0.000 1.873 r - +================================================================================= + + +Path information for path number 4: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 1.873 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -0.784 + + Number of logic level(s): 1 + Starting point: Ready_fast / Q + Ending point: RowA[1] / D The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK @@ -841,14 +872,14 @@ Name Type Name Dir Delay Time Fan Out(s --------------------------------------------------------------------------------- Ready_fast FD1S3AX Q Out 1.256 1.256 r - Ready_fast Net - - - - 14 -RowAd[0] ORCALUT4 B In 0.000 1.256 r - -RowAd[0] ORCALUT4 Z Out 0.617 1.873 r - -RowAd_0[0] Net - - - - 1 -RowA[0] FD1S3AX D In 0.000 1.873 r - +RowAd[1] ORCALUT4 B In 0.000 1.256 r - +RowAd[1] ORCALUT4 Z Out 0.617 1.873 r - +RowAd_0[1] Net - - - - 1 +RowA[1] FD1S3AX D In 0.000 1.873 r - ================================================================================= -Path information for path number 4: +Path information for path number 5: Requested Period: 1.000 - Setup time: -0.089 + Clock delay at ending point: 0.000 (ideal) @@ -876,34 +907,6 @@ RowA[5] FD1S3AX D In 0.000 1.873 f - ================================================================================= -Path information for path number 5: - Requested Period: 1.000 - - Setup time: -0.089 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 1.089 - - - Propagation time: 1.873 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : -0.784 - - Number of logic level(s): 1 - Starting point: Ready_fast / Q - Ending point: RowA[8] / D - The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK - The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------- -Ready_fast FD1S3AX Q Out 1.256 1.256 r - -Ready_fast Net - - - - 14 -RowAd[8] ORCALUT4 B In 0.000 1.256 r - -RowAd[8] ORCALUT4 Z Out 0.617 1.873 r - -RowAd_0[8] Net - - - - 1 -RowA[8] FD1S3AX D In 0.000 1.873 r - -================================================================================= - - ==================================== @@ -928,16 +931,16 @@ FWEr nCRAS FD1S3AX Q FWEr 1.180 -1.797 Ending Points with Worst Slack ****************************** - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------------- -nRCAS_0io nCRAS OFS1P3BX D N_248_i 1.089 -2.605 -nRCS_0io nCRAS OFS1P3BX D N_247_i 1.089 -1.797 -nRWE_0io nCRAS OFS1P3BX D N_49_i 1.089 -1.797 -nRowColSel nCRAS FD1S3IX D nRowColSel_0_0_0 1.089 -1.797 -RCKEEN nCRAS FD1S3AX D RCKEEN_8 1.089 -1.725 -========================================================================================== + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +---------------------------------------------------------------------------------------- +nRCAS_0io nCRAS OFS1P3BX D N_251_i 1.089 -2.605 +nRCS_0io nCRAS OFS1P3BX D N_37_i 1.089 -1.797 +nRWE_0io nCRAS OFS1P3BX D N_252_i 1.089 -1.797 +nRowColSel nCRAS FD1S3IX D nRowColSel_0_0 1.089 -1.797 +RCKEEN nCRAS FD1S3AX D RCKEEN_8 1.089 -1.725 +======================================================================================== @@ -971,10 +974,10 @@ CBR_fast_RNIQ31K1 ORCALUT4 Z Out 1.089 2.061 r - nRCAS_0_sqmuxa_1 Net - - - - 2 nRCAS_0io_RNO_0 ORCALUT4 B In 0.000 2.061 r - nRCAS_0io_RNO_0 ORCALUT4 Z Out 1.017 3.077 r - -N_248_i_sx Net - - - - 1 -nRCAS_0io_RNO ORCALUT4 D In 0.000 3.077 r - +N_251_i_sx Net - - - - 1 +nRCAS_0io_RNO ORCALUT4 C In 0.000 3.077 r - nRCAS_0io_RNO ORCALUT4 Z Out 0.617 3.694 f - -N_248_i Net - - - - 1 +N_251_i Net - - - - 1 nRCAS_0io OFS1P3BX D In 0.000 3.694 f - ==================================================================================== @@ -995,19 +998,19 @@ Path information for path number 2: The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------- -CBR FD1S3AX Q Out 1.180 1.180 r - -CBR Net - - - - 5 -RCKEEN_8_u_0_0_a2_2 ORCALUT4 A In 0.000 1.180 r - -RCKEEN_8_u_0_0_a2_2 ORCALUT4 Z Out 1.089 2.269 f - -N_590 Net - - - - 2 -nRCS_0io_RNO ORCALUT4 C In 0.000 2.269 f - -nRCS_0io_RNO ORCALUT4 Z Out 0.617 2.885 r - -N_247_i Net - - - - 1 -nRCS_0io OFS1P3BX D In 0.000 2.885 r - -====================================================================================== +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +------------------------------------------------------------------------------------ +CBR FD1S3AX Q Out 1.180 1.180 r - +CBR Net - - - - 5 +RCKEEN_8_u_0_a2_2 ORCALUT4 A In 0.000 1.180 r - +RCKEEN_8_u_0_a2_2 ORCALUT4 Z Out 1.089 2.269 f - +N_141 Net - - - - 2 +nRCS_0io_RNO ORCALUT4 A In 0.000 2.269 f - +nRCS_0io_RNO ORCALUT4 Z Out 0.617 2.885 r - +N_37_i Net - - - - 1 +nRCS_0io OFS1P3BX D In 0.000 2.885 r - +==================================================================================== Path information for path number 3: @@ -1026,19 +1029,19 @@ Path information for path number 3: The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------- -FWEr FD1S3AX Q Out 1.180 1.180 r - -FWEr Net - - - - 5 -nRCAS_r_i_0_a2 ORCALUT4 B In 0.000 1.180 r - -nRCAS_r_i_0_a2 ORCALUT4 Z Out 1.089 2.269 f - -N_248_i_1_0 Net - - - - 2 -nRCAS_0io_RNO ORCALUT4 C In 0.000 2.269 f - -nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.885 r - -N_248_i Net - - - - 1 -nRCAS_0io OFS1P3BX D In 0.000 2.885 r - -================================================================================= +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +---------------------------------------------------------------------------------- +FWEr FD1S3AX Q Out 1.180 1.180 r - +FWEr Net - - - - 5 +nRCS_9_u_i_a2_0 ORCALUT4 B In 0.000 1.180 r - +nRCS_9_u_i_a2_0 ORCALUT4 Z Out 1.089 2.269 f - +N_251_i_1 Net - - - - 2 +nRCAS_0io_RNO ORCALUT4 A In 0.000 2.269 f - +nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.885 r - +N_251_i Net - - - - 1 +nRCAS_0io OFS1P3BX D In 0.000 2.885 r - +================================================================================== Path information for path number 4: @@ -1057,19 +1060,19 @@ Path information for path number 4: The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------- -CBR FD1S3AX Q Out 1.180 1.180 r - -CBR Net - - - - 5 -RCKEEN_8_u_0_0_a2_2 ORCALUT4 A In 0.000 1.180 r - -RCKEEN_8_u_0_0_a2_2 ORCALUT4 Z Out 1.089 2.269 f - -N_590 Net - - - - 2 -nRWE_0io_RNO ORCALUT4 B In 0.000 2.269 f - -nRWE_0io_RNO ORCALUT4 Z Out 0.617 2.885 r - -N_49_i Net - - - - 1 -nRWE_0io OFS1P3BX D In 0.000 2.885 r - -====================================================================================== +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +------------------------------------------------------------------------------------ +CBR FD1S3AX Q Out 1.180 1.180 r - +CBR Net - - - - 5 +RCKEEN_8_u_0_a2_2 ORCALUT4 A In 0.000 1.180 r - +RCKEEN_8_u_0_a2_2 ORCALUT4 Z Out 1.089 2.269 f - +N_141 Net - - - - 2 +nRWE_0io_RNO ORCALUT4 B In 0.000 2.269 f - +nRWE_0io_RNO ORCALUT4 Z Out 0.617 2.885 r - +N_252_i Net - - - - 1 +nRWE_0io OFS1P3BX D In 0.000 2.885 r - +==================================================================================== Path information for path number 5: @@ -1093,12 +1096,12 @@ Name Type Name Dir Delay Time Fan -------------------------------------------------------------------------------------- FWEr FD1S3AX Q Out 1.180 1.180 r - FWEr Net - - - - 5 -nRowColSel_0_0_0_a2 ORCALUT4 B In 0.000 1.180 r - -nRowColSel_0_0_0_a2 ORCALUT4 Z Out 1.089 2.269 r - -N_248_i_1_1 Net - - - - 2 +nRowColSel_0_0_a2_1 ORCALUT4 B In 0.000 1.180 r - +nRowColSel_0_0_a2_1 ORCALUT4 Z Out 1.089 2.269 r - +N_251_i_1_0 Net - - - - 2 nRCAS_0io_RNO ORCALUT4 B In 0.000 2.269 r - nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.885 f - -N_248_i Net - - - - 1 +N_251_i Net - - - - 1 nRCAS_0io OFS1P3BX D In 0.000 2.885 f - ====================================================================================== @@ -1127,14 +1130,14 @@ ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 Ending Points with Worst Slack ****************************** - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------ -LEDEN System FD1S3AX D LEDENe_0 16.089 12.918 -n8MEGEN System FD1S3AX D n8MEGENe_0 16.089 12.918 -wb_cyc_stb System FD1P3IX SP N_178 15.528 14.912 -=================================================================================== + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------------------------- +LEDEN System FD1S3AX D LEDENe_0 16.089 12.918 +n8MEGEN System FD1S3AX D n8MEGENe_0 16.089 12.918 +wb_cyc_stb System FD1P3IX SP wb_cyc_stb_2_sqmuxa_i_0_0 15.528 14.912 +================================================================================================== @@ -1172,8 +1175,8 @@ ufmefb.EFBInst_0_RNISI191 ORCALUT4 Z Out 0.449 1.466 r N_4 Net - - - - 1 CmdValid_RNIOOBE2 ORCALUT4 C In 0.000 1.466 r - CmdValid_RNIOOBE2 ORCALUT4 Z Out 1.089 2.554 r - -CmdValid_RNIOOBE2 Net - - - - 2 -LEDENe ORCALUT4 B In 0.000 2.554 r - +un1_FS_38_i Net - - - - 2 +LEDENe ORCALUT4 C In 0.000 2.554 r - LEDENe ORCALUT4 Z Out 0.617 3.171 r - LEDENe_0 Net - - - - 1 LEDEN FD1S3AX D In 0.000 3.171 r - @@ -1196,7 +1199,7 @@ Part: lcmxo2_640hc-4 Register bits: 109 of 640 (17%) PIC Latch: 0 -I/O cells: 63 +I/O cells: 64 Details: @@ -1211,12 +1214,13 @@ GSR: 1 IB: 25 IFS1P3DX: 9 INV: 7 -OB: 30 +OB: 31 +ODDRXE: 1 OFS1P3BX: 4 OFS1P3DX: 11 OFS1P3JX: 1 -ORCALUT4: 213 -PFUMX: 1 +ORCALUT4: 212 +PFUMX: 2 PUR: 1 VHI: 2 VLO: 2 @@ -1225,6 +1229,6 @@ Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 78MB peak: 203MB) Process took 0h:00m:04s realtime, 0h:00m:04s cputime -# Thu Sep 21 05:39:42 2023 +# Sat Nov 18 02:05:48 2023 ###########################################################] diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.tw1 b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.tw1 index e0c1312..8eb34fc 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.tw1 +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.tw1 @@ -13,7 +13,7 @@ Setup and Hold Report -------------------------------------------------------------------------------- Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 -Thu Sep 21 05:39:45 2023 +Sat Nov 18 02:05:54 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -46,28 +46,28 @@ Passed: The following path meets requirements by 163.025ns (weighted slack = 326 Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_0io[0] (from PHI2_c +) + Source: FF Q Bank_0io[1] (from PHI2_c +) Destination: FF Data in CmdEnable (to PHI2_c -) Delay: 9.223ns (33.1% logic, 66.9% route), 6 logic levels. Constraint Details: - 9.223ns physical path delay Din[0]_MGIOL to SLICE_17 meets + 9.223ns physical path delay Din[1]_MGIOL to SLICE_17 meets 172.414ns delay constraint less 0.166ns DIN_SET requirement (totaling 172.248ns) by 163.025ns Physical Path Details: - Data path Din[0]_MGIOL to SLICE_17: + Data path Din[1]_MGIOL to SLICE_17: Name Fanout Delay (ns) Site Resource -C2INP_DEL --- 0.577 *[0]_MGIOL.CLK to *n[0]_MGIOL.IN Din[0]_MGIOL (from PHI2_c) -ROUTE 1 e 1.234 *n[0]_MGIOL.IN to SLICE_93.A0 Bank[0] -CTOF_DEL --- 0.495 SLICE_93.A0 to SLICE_93.F0 SLICE_93 -ROUTE 1 e 1.234 SLICE_93.F0 to SLICE_84.C0 un1_CmdEnable20_0_0_o3_10 -CTOF_DEL --- 0.495 SLICE_84.C0 to SLICE_84.F0 SLICE_84 -ROUTE 6 e 1.234 SLICE_84.F0 to SLICE_11.C1 un1_CmdEnable20_0_0_o3 +C2INP_DEL --- 0.577 *[1]_MGIOL.CLK to *n[1]_MGIOL.IN Din[1]_MGIOL (from PHI2_c) +ROUTE 1 e 1.234 *n[1]_MGIOL.IN to SLICE_90.A0 Bank[1] +CTOF_DEL --- 0.495 SLICE_90.A0 to SLICE_90.F0 SLICE_90 +ROUTE 1 e 1.234 SLICE_90.F0 to SLICE_80.C0 un1_CmdEnable20_0_0_o2_10 +CTOF_DEL --- 0.495 SLICE_80.C0 to SLICE_80.F0 SLICE_80 +ROUTE 6 e 1.234 SLICE_80.F0 to SLICE_11.C1 N_367 CTOF_DEL --- 0.495 SLICE_11.C1 to SLICE_11.F1 SLICE_11 ROUTE 3 e 1.234 SLICE_11.F1 to SLICE_33.B0 CmdEnable16 CTOF_DEL --- 0.495 SLICE_33.B0 to SLICE_33.F0 SLICE_33 @@ -118,48 +118,46 @@ Report: 150.150MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; - 878 items scored, 0 timing errors detected. + 891 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- -Passed: The following path meets requirements by 6.049ns +Passed: The following path meets requirements by 5.516ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q IS[1] (from RCLK_c +) - Destination: FF Data in nRCAS_0io (to RCLK_c +) + Source: FF Q S[0] (from RCLK_c +) + Destination: FF Data in nRWE_0io (to RCLK_c +) - Delay: 9.798ns (34.9% logic, 65.1% route), 7 logic levels. + Delay: 10.331ns (28.3% logic, 71.7% route), 6 logic levels. Constraint Details: - 9.798ns physical path delay SLICE_27 to nRCAS_MGIOL meets + 10.331ns physical path delay SLICE_16 to nRWE_MGIOL meets 16.000ns delay constraint less - 0.153ns DO_SET requirement (totaling 15.847ns) by 6.049ns + 0.153ns DO_SET requirement (totaling 15.847ns) by 5.516ns Physical Path Details: - Data path SLICE_27 to nRCAS_MGIOL: + Data path SLICE_16 to nRWE_MGIOL: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 SLICE_27.CLK to SLICE_27.Q0 SLICE_27 (from RCLK_c) -ROUTE 7 e 1.234 SLICE_27.Q0 to SLICE_74.A1 IS[1] -CTOF_DEL --- 0.495 SLICE_74.A1 to SLICE_74.F1 SLICE_74 -ROUTE 2 e 0.480 SLICE_74.F1 to SLICE_74.B0 un1_nRCAS_6_sqmuxa_i_0_0_o2_0 -CTOF_DEL --- 0.495 SLICE_74.B0 to SLICE_74.F0 SLICE_74 -ROUTE 2 e 1.234 SLICE_74.F0 to SLICE_61.B1 N_408 -CTOF_DEL --- 0.495 SLICE_61.B1 to SLICE_61.F1 SLICE_61 -ROUTE 1 e 0.480 SLICE_61.F1 to SLICE_61.A0 un1_nRCAS_6_sqmuxa_i_0_0 -CTOF_DEL --- 0.495 SLICE_61.A0 to SLICE_61.F0 SLICE_61 -ROUTE 1 e 1.234 SLICE_61.F0 to SLICE_94.D0 nRCAS_r_i_0_o2_0_0 -CTOF_DEL --- 0.495 SLICE_94.D0 to SLICE_94.F0 SLICE_94 -ROUTE 1 e 0.480 SLICE_94.F0 to SLICE_94.A1 N_248_i_1 -CTOF_DEL --- 0.495 SLICE_94.A1 to SLICE_94.F1 SLICE_94 -ROUTE 1 e 1.234 SLICE_94.F1 to *AS_MGIOL.OPOS N_248_i (to RCLK_c) +REG_DEL --- 0.452 SLICE_16.CLK to SLICE_16.Q0 SLICE_16 (from RCLK_c) +ROUTE 12 e 1.234 SLICE_16.Q0 to SLICE_62.D1 CO0 +CTOF_DEL --- 0.495 SLICE_62.D1 to SLICE_62.F1 SLICE_62 +ROUTE 6 e 1.234 SLICE_62.F1 to SLICE_79.A1 IS_0_sqmuxa_0_o2 +CTOF_DEL --- 0.495 SLICE_79.A1 to SLICE_79.F1 SLICE_79 +ROUTE 2 e 1.234 SLICE_79.F1 to SLICE_28.D1 IS_0_sqmuxa_0_o3 +CTOF_DEL --- 0.495 SLICE_28.D1 to SLICE_28.F1 SLICE_28 +ROUTE 1 e 1.234 SLICE_28.F1 to SLICE_68.D1 nRWE_s_i_a2_1_0 +CTOF_DEL --- 0.495 SLICE_68.D1 to SLICE_68.F1 SLICE_68 +ROUTE 1 e 1.234 SLICE_68.F1 to SLICE_75.D0 nRWE_s_i_tz_0 +CTOF_DEL --- 0.495 SLICE_75.D0 to SLICE_75.F0 SLICE_75 +ROUTE 1 e 1.234 SLICE_75.F0 to *WE_MGIOL.OPOS N_252_i (to RCLK_c) -------- - 9.798 (34.9% logic, 65.1% route), 7 logic levels. + 10.331 (28.3% logic, 71.7% route), 6 logic levels. -Report: 100.492MHz is the maximum frequency for this preference. +Report: 95.383MHz is the maximum frequency for this preference. Report Summary -------------- @@ -173,7 +171,7 @@ FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0 | | | FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0 | | | -FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 100.492 MHz| 7 +FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 95.383 MHz| 6 | | | ---------------------------------------------------------------------------- @@ -198,7 +196,7 @@ Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11 Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10 No transfer within this clock domain is found -Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47 +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 48 Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ; Data transfers from: @@ -228,11 +226,11 @@ Timing summary (Setup): Timing errors: 0 Score: 0 Cumulative negative slack: 0 -Constraints cover 1025 paths, 4 nets, and 741 connections (72.86% coverage) +Constraints cover 1038 paths, 4 nets, and 732 connections (72.40% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 -Thu Sep 21 05:39:45 2023 +Sat Nov 18 02:05:54 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -303,7 +301,7 @@ Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ; ================================================================================ Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; - 878 items scored, 0 timing errors detected. + 891 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- @@ -369,7 +367,7 @@ Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11 Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10 No transfer within this clock domain is found -Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47 +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 48 Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ; Data transfers from: @@ -399,7 +397,7 @@ Timing summary (Hold): Timing errors: 0 Score: 0 Cumulative negative slack: 0 -Constraints cover 1025 paths, 4 nets, and 741 connections (72.86% coverage) +Constraints cover 1038 paths, 4 nets, and 732 connections (72.40% coverage) diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.twr b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.twr index 2c710d7..6052b77 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.twr +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.twr @@ -13,7 +13,7 @@ Setup and Hold Report -------------------------------------------------------------------------------- Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 -Thu Sep 21 05:40:01 2023 +Sat Nov 18 02:06:11 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -42,90 +42,247 @@ Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ; -------------------------------------------------------------------------------- -Passed: The following path meets requirements by 162.971ns (weighted slack = 325.942ns) +Passed: The following path meets requirements by 161.791ns (weighted slack = 323.582ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_0io[0] (from PHI2_c +) + Source: FF Q Bank_0io[7] (from PHI2_c +) Destination: FF Data in CmdUFMData (to PHI2_c -) - Delay: 8.963ns (28.5% logic, 71.5% route), 5 logic levels. + Delay: 10.143ns (25.2% logic, 74.8% route), 5 logic levels. Constraint Details: - 8.963ns physical path delay Din[0]_MGIOL to SLICE_82 meets + 10.143ns physical path delay Din[7]_MGIOL to SLICE_19 meets 172.414ns delay constraint less 0.173ns skew and - 0.307ns CE_SET requirement (totaling 171.934ns) by 162.971ns + 0.307ns CE_SET requirement (totaling 171.934ns) by 161.791ns Physical Path Details: - Data path Din[0]_MGIOL to SLICE_82: + Data path Din[7]_MGIOL to SLICE_19: Name Fanout Delay (ns) Site Resource -C2INP_DEL --- 0.577 IOL_L2C.CLK to IOL_L2C.IN Din[0]_MGIOL (from PHI2_c) -ROUTE 1 1.802 IOL_L2C.IN to R3C8A.D0 Bank[0] -CTOF_DEL --- 0.495 R3C8A.D0 to R3C8A.F0 SLICE_93 -ROUTE 1 0.958 R3C8A.F0 to R2C6B.D0 un1_CmdEnable20_0_0_o3_10 -CTOF_DEL --- 0.495 R2C6B.D0 to R2C6B.F0 SLICE_84 -ROUTE 6 1.506 R2C6B.F0 to R3C9D.A1 un1_CmdEnable20_0_0_o3 -CTOF_DEL --- 0.495 R3C9D.A1 to R3C9D.F1 SLICE_23 -ROUTE 8 1.487 R3C9D.F1 to R4C9C.B0 XOR8MEG18 -CTOF_DEL --- 0.495 R4C9C.B0 to R4C9C.F0 SLICE_82 -ROUTE 1 0.653 R4C9C.F0 to R4C9C.CE CmdUFMData_1_sqmuxa (to PHI2_c) +C2INP_DEL --- 0.577 IOL_L2A.CLK to IOL_L2A.IN Din[7]_MGIOL (from PHI2_c) +ROUTE 1 1.995 IOL_L2A.IN to R5C6A.C0 Bank[7] +CTOF_DEL --- 0.495 R5C6A.C0 to R5C6A.F0 SLICE_90 +ROUTE 1 1.299 R5C6A.F0 to R2C6C.A0 un1_CmdEnable20_0_0_o2_10 +CTOF_DEL --- 0.495 R2C6C.A0 to R2C6C.F0 SLICE_80 +ROUTE 6 1.993 R2C6C.F0 to R4C8A.B1 N_367 +CTOF_DEL --- 0.495 R4C8A.B1 to R4C8A.F1 SLICE_23 +ROUTE 8 1.230 R4C8A.F1 to R5C9A.C0 XOR8MEG18 +CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_77 +ROUTE 1 1.069 R5C9A.F0 to R5C10B.CE CmdUFMData_1_sqmuxa (to PHI2_c) -------- - 8.963 (28.5% logic, 71.5% route), 5 logic levels. + 10.143 (25.2% logic, 74.8% route), 5 logic levels. Clock Skew Details: - Source Clock Path PHI2 to Din[0]_MGIOL: + Source Clock Path PHI2 to Din[7]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 21 3.712 8.PADDI to IOL_L2C.CLK PHI2_c +ROUTE 21 3.712 8.PADDI to IOL_L2A.CLK PHI2_c -------- 3.712 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_82: + Destination Clock Path PHI2 to SLICE_19: Name Fanout Delay (ns) Site Resource -ROUTE 21 3.539 8.PADDI to R4C9C.CLK PHI2_c +ROUTE 21 3.539 8.PADDI to R5C10B.CLK PHI2_c -------- 3.539 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 163.277ns (weighted slack = 326.554ns) +Passed: The following path meets requirements by 162.140ns (weighted slack = 324.280ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_0io[7] (from PHI2_c +) + Destination: FF Data in CmdEnable (to PHI2_c -) + + Delay: 9.935ns (30.7% logic, 69.3% route), 6 logic levels. + + Constraint Details: + + 9.935ns physical path delay Din[7]_MGIOL to SLICE_17 meets + 172.414ns delay constraint less + 0.173ns skew and + 0.166ns DIN_SET requirement (totaling 172.075ns) by 162.140ns + + Physical Path Details: + + Data path Din[7]_MGIOL to SLICE_17: + + Name Fanout Delay (ns) Site Resource +C2INP_DEL --- 0.577 IOL_L2A.CLK to IOL_L2A.IN Din[7]_MGIOL (from PHI2_c) +ROUTE 1 1.995 IOL_L2A.IN to R5C6A.C0 Bank[7] +CTOF_DEL --- 0.495 R5C6A.C0 to R5C6A.F0 SLICE_90 +ROUTE 1 1.299 R5C6A.F0 to R2C6C.A0 un1_CmdEnable20_0_0_o2_10 +CTOF_DEL --- 0.495 R2C6C.A0 to R2C6C.F0 SLICE_80 +ROUTE 6 1.188 R2C6C.F0 to R5C8D.D1 N_367 +CTOF_DEL --- 0.495 R5C8D.D1 to R5C8D.F1 SLICE_11 +ROUTE 3 1.102 R5C8D.F1 to R5C5D.C0 CmdEnable16 +CTOF_DEL --- 0.495 R5C5D.C0 to R5C5D.F0 SLICE_33 +ROUTE 1 1.299 R5C5D.F0 to R5C8C.A0 CmdEnable_0_sqmuxa +CTOF_DEL --- 0.495 R5C8C.A0 to R5C8C.F0 SLICE_17 +ROUTE 1 0.000 R5C8C.F0 to R5C8C.DI0 CmdEnable_s (to PHI2_c) + -------- + 9.935 (30.7% logic, 69.3% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to Din[7]_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 3.712 8.PADDI to IOL_L2A.CLK PHI2_c + -------- + 3.712 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_17: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 3.539 8.PADDI to R5C8C.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.411ns (weighted slack = 324.822ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_0io[1] (from PHI2_c +) + Destination: FF Data in CmdUFMData (to PHI2_c -) + + Delay: 9.523ns (26.9% logic, 73.1% route), 5 logic levels. + + Constraint Details: + + 9.523ns physical path delay Din[1]_MGIOL to SLICE_19 meets + 172.414ns delay constraint less + 0.173ns skew and + 0.307ns CE_SET requirement (totaling 171.934ns) by 162.411ns + + Physical Path Details: + + Data path Din[1]_MGIOL to SLICE_19: + + Name Fanout Delay (ns) Site Resource +C2INP_DEL --- 0.577 IOL_T6D.CLK to IOL_T6D.IN Din[1]_MGIOL (from PHI2_c) +ROUTE 1 1.375 IOL_T6D.IN to R5C6A.D0 Bank[1] +CTOF_DEL --- 0.495 R5C6A.D0 to R5C6A.F0 SLICE_90 +ROUTE 1 1.299 R5C6A.F0 to R2C6C.A0 un1_CmdEnable20_0_0_o2_10 +CTOF_DEL --- 0.495 R2C6C.A0 to R2C6C.F0 SLICE_80 +ROUTE 6 1.993 R2C6C.F0 to R4C8A.B1 N_367 +CTOF_DEL --- 0.495 R4C8A.B1 to R4C8A.F1 SLICE_23 +ROUTE 8 1.230 R4C8A.F1 to R5C9A.C0 XOR8MEG18 +CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_77 +ROUTE 1 1.069 R5C9A.F0 to R5C10B.CE CmdUFMData_1_sqmuxa (to PHI2_c) + -------- + 9.523 (26.9% logic, 73.1% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to Din[1]_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 3.712 8.PADDI to IOL_T6D.CLK PHI2_c + -------- + 3.712 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 3.539 8.PADDI to R5C10B.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.760ns (weighted slack = 325.520ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_0io[1] (from PHI2_c +) + Destination: FF Data in CmdEnable (to PHI2_c -) + + Delay: 9.315ns (32.8% logic, 67.2% route), 6 logic levels. + + Constraint Details: + + 9.315ns physical path delay Din[1]_MGIOL to SLICE_17 meets + 172.414ns delay constraint less + 0.173ns skew and + 0.166ns DIN_SET requirement (totaling 172.075ns) by 162.760ns + + Physical Path Details: + + Data path Din[1]_MGIOL to SLICE_17: + + Name Fanout Delay (ns) Site Resource +C2INP_DEL --- 0.577 IOL_T6D.CLK to IOL_T6D.IN Din[1]_MGIOL (from PHI2_c) +ROUTE 1 1.375 IOL_T6D.IN to R5C6A.D0 Bank[1] +CTOF_DEL --- 0.495 R5C6A.D0 to R5C6A.F0 SLICE_90 +ROUTE 1 1.299 R5C6A.F0 to R2C6C.A0 un1_CmdEnable20_0_0_o2_10 +CTOF_DEL --- 0.495 R2C6C.A0 to R2C6C.F0 SLICE_80 +ROUTE 6 1.188 R2C6C.F0 to R5C8D.D1 N_367 +CTOF_DEL --- 0.495 R5C8D.D1 to R5C8D.F1 SLICE_11 +ROUTE 3 1.102 R5C8D.F1 to R5C5D.C0 CmdEnable16 +CTOF_DEL --- 0.495 R5C5D.C0 to R5C5D.F0 SLICE_33 +ROUTE 1 1.299 R5C5D.F0 to R5C8C.A0 CmdEnable_0_sqmuxa +CTOF_DEL --- 0.495 R5C8C.A0 to R5C8C.F0 SLICE_17 +ROUTE 1 0.000 R5C8C.F0 to R5C8C.DI0 CmdEnable_s (to PHI2_c) + -------- + 9.315 (32.8% logic, 67.2% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to Din[1]_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 3.712 8.PADDI to IOL_T6D.CLK PHI2_c + -------- + 3.712 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_17: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 3.539 8.PADDI to R5C8C.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.896ns (weighted slack = 325.792ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Bank_0io[2] (from PHI2_c +) Destination: FF Data in CmdUFMData (to PHI2_c -) - Delay: 8.657ns (29.5% logic, 70.5% route), 5 logic levels. + Delay: 9.038ns (28.3% logic, 71.7% route), 5 logic levels. Constraint Details: - 8.657ns physical path delay Din[2]_MGIOL to SLICE_82 meets + 9.038ns physical path delay Din[2]_MGIOL to SLICE_19 meets 172.414ns delay constraint less 0.173ns skew and - 0.307ns CE_SET requirement (totaling 171.934ns) by 163.277ns + 0.307ns CE_SET requirement (totaling 171.934ns) by 162.896ns Physical Path Details: - Data path Din[2]_MGIOL to SLICE_82: + Data path Din[2]_MGIOL to SLICE_19: Name Fanout Delay (ns) Site Resource C2INP_DEL --- 0.577 IOL_T9A.CLK to IOL_T9A.IN Din[2]_MGIOL (from PHI2_c) -ROUTE 1 1.496 IOL_T9A.IN to R3C8A.C0 Bank[2] -CTOF_DEL --- 0.495 R3C8A.C0 to R3C8A.F0 SLICE_93 -ROUTE 1 0.958 R3C8A.F0 to R2C6B.D0 un1_CmdEnable20_0_0_o3_10 -CTOF_DEL --- 0.495 R2C6B.D0 to R2C6B.F0 SLICE_84 -ROUTE 6 1.506 R2C6B.F0 to R3C9D.A1 un1_CmdEnable20_0_0_o3 -CTOF_DEL --- 0.495 R3C9D.A1 to R3C9D.F1 SLICE_23 -ROUTE 8 1.487 R3C9D.F1 to R4C9C.B0 XOR8MEG18 -CTOF_DEL --- 0.495 R4C9C.B0 to R4C9C.F0 SLICE_82 -ROUTE 1 0.653 R4C9C.F0 to R4C9C.CE CmdUFMData_1_sqmuxa (to PHI2_c) +ROUTE 1 1.753 IOL_T9A.IN to R2C6C.B1 Bank[2] +CTOF_DEL --- 0.495 R2C6C.B1 to R2C6C.F1 SLICE_80 +ROUTE 1 0.436 R2C6C.F1 to R2C6C.C0 un1_CmdEnable20_0_0_o2_11 +CTOF_DEL --- 0.495 R2C6C.C0 to R2C6C.F0 SLICE_80 +ROUTE 6 1.993 R2C6C.F0 to R4C8A.B1 N_367 +CTOF_DEL --- 0.495 R4C8A.B1 to R4C8A.F1 SLICE_23 +ROUTE 8 1.230 R4C8A.F1 to R5C9A.C0 XOR8MEG18 +CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_77 +ROUTE 1 1.069 R5C9A.F0 to R5C10B.CE CmdUFMData_1_sqmuxa (to PHI2_c) -------- - 8.657 (29.5% logic, 70.5% route), 5 logic levels. + 9.038 (28.3% logic, 71.7% route), 5 logic levels. Clock Skew Details: @@ -136,209 +293,209 @@ ROUTE 21 3.712 8.PADDI to IOL_T9A.CLK PHI2_c -------- 3.712 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_82: + Destination Clock Path PHI2 to SLICE_19: Name Fanout Delay (ns) Site Resource -ROUTE 21 3.539 8.PADDI to R4C9C.CLK PHI2_c +ROUTE 21 3.539 8.PADDI to R5C10B.CLK PHI2_c -------- 3.539 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 163.351ns (weighted slack = 326.702ns) +Passed: The following path meets requirements by 163.153ns (weighted slack = 326.306ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_0io[5] (from PHI2_c +) + Source: FF Q Bank_0io[6] (from PHI2_c +) Destination: FF Data in CmdUFMData (to PHI2_c -) - Delay: 8.583ns (29.8% logic, 70.2% route), 5 logic levels. + Delay: 8.781ns (29.1% logic, 70.9% route), 5 logic levels. Constraint Details: - 8.583ns physical path delay Din[5]_MGIOL to SLICE_82 meets + 8.781ns physical path delay Din[6]_MGIOL to SLICE_19 meets 172.414ns delay constraint less 0.173ns skew and - 0.307ns CE_SET requirement (totaling 171.934ns) by 163.351ns + 0.307ns CE_SET requirement (totaling 171.934ns) by 163.153ns Physical Path Details: - Data path Din[5]_MGIOL to SLICE_82: + Data path Din[6]_MGIOL to SLICE_19: Name Fanout Delay (ns) Site Resource -C2INP_DEL --- 0.577 IOL_T6B.CLK to IOL_T6B.IN Din[5]_MGIOL (from PHI2_c) -ROUTE 1 1.944 IOL_T6B.IN to R2C6B.A1 Bank[5] -CTOF_DEL --- 0.495 R2C6B.A1 to R2C6B.F1 SLICE_84 -ROUTE 1 0.436 R2C6B.F1 to R2C6B.C0 un1_CmdEnable20_0_0_o3_11 -CTOF_DEL --- 0.495 R2C6B.C0 to R2C6B.F0 SLICE_84 -ROUTE 6 1.506 R2C6B.F0 to R3C9D.A1 un1_CmdEnable20_0_0_o3 -CTOF_DEL --- 0.495 R3C9D.A1 to R3C9D.F1 SLICE_23 -ROUTE 8 1.487 R3C9D.F1 to R4C9C.B0 XOR8MEG18 -CTOF_DEL --- 0.495 R4C9C.B0 to R4C9C.F0 SLICE_82 -ROUTE 1 0.653 R4C9C.F0 to R4C9C.CE CmdUFMData_1_sqmuxa (to PHI2_c) +C2INP_DEL --- 0.577 IOL_L2B.CLK to IOL_L2B.IN Din[6]_MGIOL (from PHI2_c) +ROUTE 1 1.496 IOL_L2B.IN to R2C6C.C1 Bank[6] +CTOF_DEL --- 0.495 R2C6C.C1 to R2C6C.F1 SLICE_80 +ROUTE 1 0.436 R2C6C.F1 to R2C6C.C0 un1_CmdEnable20_0_0_o2_11 +CTOF_DEL --- 0.495 R2C6C.C0 to R2C6C.F0 SLICE_80 +ROUTE 6 1.993 R2C6C.F0 to R4C8A.B1 N_367 +CTOF_DEL --- 0.495 R4C8A.B1 to R4C8A.F1 SLICE_23 +ROUTE 8 1.230 R4C8A.F1 to R5C9A.C0 XOR8MEG18 +CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_77 +ROUTE 1 1.069 R5C9A.F0 to R5C10B.CE CmdUFMData_1_sqmuxa (to PHI2_c) -------- - 8.583 (29.8% logic, 70.2% route), 5 logic levels. + 8.781 (29.1% logic, 70.9% route), 5 logic levels. Clock Skew Details: - Source Clock Path PHI2 to Din[5]_MGIOL: + Source Clock Path PHI2 to Din[6]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 21 3.712 8.PADDI to IOL_T6B.CLK PHI2_c +ROUTE 21 3.712 8.PADDI to IOL_L2B.CLK PHI2_c -------- 3.712 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_82: + Destination Clock Path PHI2 to SLICE_19: Name Fanout Delay (ns) Site Resource -ROUTE 21 3.539 8.PADDI to R4C9C.CLK PHI2_c +ROUTE 21 3.539 8.PADDI to R5C10B.CLK PHI2_c -------- 3.539 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 163.564ns (weighted slack = 327.128ns) +Passed: The following path meets requirements by 163.245ns (weighted slack = 326.490ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_0io[0] (from PHI2_c +) + Source: FF Q Bank_0io[2] (from PHI2_c +) Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 8.511ns (35.9% logic, 64.1% route), 6 logic levels. + Delay: 8.830ns (34.6% logic, 65.4% route), 6 logic levels. Constraint Details: - 8.511ns physical path delay Din[0]_MGIOL to SLICE_17 meets + 8.830ns physical path delay Din[2]_MGIOL to SLICE_17 meets 172.414ns delay constraint less 0.173ns skew and - 0.166ns DIN_SET requirement (totaling 172.075ns) by 163.564ns + 0.166ns DIN_SET requirement (totaling 172.075ns) by 163.245ns Physical Path Details: - Data path Din[0]_MGIOL to SLICE_17: + Data path Din[2]_MGIOL to SLICE_17: Name Fanout Delay (ns) Site Resource -C2INP_DEL --- 0.577 IOL_L2C.CLK to IOL_L2C.IN Din[0]_MGIOL (from PHI2_c) -ROUTE 1 1.802 IOL_L2C.IN to R3C8A.D0 Bank[0] -CTOF_DEL --- 0.495 R3C8A.D0 to R3C8A.F0 SLICE_93 -ROUTE 1 0.958 R3C8A.F0 to R2C6B.D0 un1_CmdEnable20_0_0_o3_10 -CTOF_DEL --- 0.495 R2C6B.D0 to R2C6B.F0 SLICE_84 -ROUTE 6 1.617 R2C6B.F0 to R4C11D.D1 un1_CmdEnable20_0_0_o3 -CTOF_DEL --- 0.495 R4C11D.D1 to R4C11D.F1 SLICE_11 -ROUTE 3 0.767 R4C11D.F1 to R3C11D.C0 CmdEnable16 -CTOF_DEL --- 0.495 R3C11D.C0 to R3C11D.F0 SLICE_33 -ROUTE 1 0.315 R3C11D.F0 to R3C11C.D0 CmdEnable_0_sqmuxa -CTOF_DEL --- 0.495 R3C11C.D0 to R3C11C.F0 SLICE_17 -ROUTE 1 0.000 R3C11C.F0 to R3C11C.DI0 CmdEnable_s (to PHI2_c) +C2INP_DEL --- 0.577 IOL_T9A.CLK to IOL_T9A.IN Din[2]_MGIOL (from PHI2_c) +ROUTE 1 1.753 IOL_T9A.IN to R2C6C.B1 Bank[2] +CTOF_DEL --- 0.495 R2C6C.B1 to R2C6C.F1 SLICE_80 +ROUTE 1 0.436 R2C6C.F1 to R2C6C.C0 un1_CmdEnable20_0_0_o2_11 +CTOF_DEL --- 0.495 R2C6C.C0 to R2C6C.F0 SLICE_80 +ROUTE 6 1.188 R2C6C.F0 to R5C8D.D1 N_367 +CTOF_DEL --- 0.495 R5C8D.D1 to R5C8D.F1 SLICE_11 +ROUTE 3 1.102 R5C8D.F1 to R5C5D.C0 CmdEnable16 +CTOF_DEL --- 0.495 R5C5D.C0 to R5C5D.F0 SLICE_33 +ROUTE 1 1.299 R5C5D.F0 to R5C8C.A0 CmdEnable_0_sqmuxa +CTOF_DEL --- 0.495 R5C8C.A0 to R5C8C.F0 SLICE_17 +ROUTE 1 0.000 R5C8C.F0 to R5C8C.DI0 CmdEnable_s (to PHI2_c) -------- - 8.511 (35.9% logic, 64.1% route), 6 logic levels. + 8.830 (34.6% logic, 65.4% route), 6 logic levels. Clock Skew Details: - Source Clock Path PHI2 to Din[0]_MGIOL: + Source Clock Path PHI2 to Din[2]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 21 3.712 8.PADDI to IOL_L2C.CLK PHI2_c +ROUTE 21 3.712 8.PADDI to IOL_T9A.CLK PHI2_c -------- 3.712 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_17: Name Fanout Delay (ns) Site Resource -ROUTE 21 3.539 8.PADDI to R3C11C.CLK PHI2_c +ROUTE 21 3.539 8.PADDI to R5C8C.CLK PHI2_c -------- 3.539 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 163.740ns (weighted slack = 327.480ns) +Passed: The following path meets requirements by 163.389ns (weighted slack = 326.778ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_0io[0] (from PHI2_c +) - Destination: FF Data in CmdEnable (to PHI2_c -) + Source: FF Q Bank_0io[3] (from PHI2_c +) + Destination: FF Data in CmdUFMData (to PHI2_c -) - Delay: 8.335ns (30.7% logic, 69.3% route), 5 logic levels. + Delay: 8.545ns (29.9% logic, 70.1% route), 5 logic levels. Constraint Details: - 8.335ns physical path delay Din[0]_MGIOL to SLICE_17 meets + 8.545ns physical path delay Din[3]_MGIOL to SLICE_19 meets 172.414ns delay constraint less 0.173ns skew and - 0.166ns DIN_SET requirement (totaling 172.075ns) by 163.740ns + 0.307ns CE_SET requirement (totaling 171.934ns) by 163.389ns Physical Path Details: - Data path Din[0]_MGIOL to SLICE_17: + Data path Din[3]_MGIOL to SLICE_19: Name Fanout Delay (ns) Site Resource -C2INP_DEL --- 0.577 IOL_L2C.CLK to IOL_L2C.IN Din[0]_MGIOL (from PHI2_c) -ROUTE 1 1.802 IOL_L2C.IN to R3C8A.D0 Bank[0] -CTOF_DEL --- 0.495 R3C8A.D0 to R3C8A.F0 SLICE_93 -ROUTE 1 0.958 R3C8A.F0 to R2C6B.D0 un1_CmdEnable20_0_0_o3_10 -CTOF_DEL --- 0.495 R2C6B.D0 to R2C6B.F0 SLICE_84 -ROUTE 6 1.995 R2C6B.F0 to R4C11B.B0 un1_CmdEnable20_0_0_o3 -CTOF_DEL --- 0.495 R4C11B.B0 to R4C11B.F0 SLICE_80 -ROUTE 1 1.023 R4C11B.F0 to R3C11C.B0 un1_CmdEnable20_i -CTOF_DEL --- 0.495 R3C11C.B0 to R3C11C.F0 SLICE_17 -ROUTE 1 0.000 R3C11C.F0 to R3C11C.DI0 CmdEnable_s (to PHI2_c) +C2INP_DEL --- 0.577 IOL_T6C.CLK to IOL_T6C.IN Din[3]_MGIOL (from PHI2_c) +ROUTE 1 1.260 IOL_T6C.IN to R2C6C.D1 Bank[3] +CTOF_DEL --- 0.495 R2C6C.D1 to R2C6C.F1 SLICE_80 +ROUTE 1 0.436 R2C6C.F1 to R2C6C.C0 un1_CmdEnable20_0_0_o2_11 +CTOF_DEL --- 0.495 R2C6C.C0 to R2C6C.F0 SLICE_80 +ROUTE 6 1.993 R2C6C.F0 to R4C8A.B1 N_367 +CTOF_DEL --- 0.495 R4C8A.B1 to R4C8A.F1 SLICE_23 +ROUTE 8 1.230 R4C8A.F1 to R5C9A.C0 XOR8MEG18 +CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_77 +ROUTE 1 1.069 R5C9A.F0 to R5C10B.CE CmdUFMData_1_sqmuxa (to PHI2_c) -------- - 8.335 (30.7% logic, 69.3% route), 5 logic levels. + 8.545 (29.9% logic, 70.1% route), 5 logic levels. Clock Skew Details: - Source Clock Path PHI2 to Din[0]_MGIOL: + Source Clock Path PHI2 to Din[3]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 21 3.712 8.PADDI to IOL_L2C.CLK PHI2_c +ROUTE 21 3.712 8.PADDI to IOL_T6C.CLK PHI2_c -------- 3.712 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_17: + Destination Clock Path PHI2 to SLICE_19: Name Fanout Delay (ns) Site Resource -ROUTE 21 3.539 8.PADDI to R3C11C.CLK PHI2_c +ROUTE 21 3.539 8.PADDI to R5C10B.CLK PHI2_c -------- 3.539 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 163.802ns (weighted slack = 327.604ns) +Passed: The following path meets requirements by 163.435ns (weighted slack = 326.870ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_0io[0] (from PHI2_c +) + Source: FF Q Bank_0io[7] (from PHI2_c +) Destination: FF Data in CmdValid (to PHI2_c -) - Delay: 8.273ns (30.9% logic, 69.1% route), 5 logic levels. + Delay: 8.640ns (29.6% logic, 70.4% route), 5 logic levels. Constraint Details: - 8.273ns physical path delay Din[0]_MGIOL to SLICE_22 meets + 8.640ns physical path delay Din[7]_MGIOL to SLICE_22 meets 172.414ns delay constraint less 0.173ns skew and - 0.166ns DIN_SET requirement (totaling 172.075ns) by 163.802ns + 0.166ns DIN_SET requirement (totaling 172.075ns) by 163.435ns Physical Path Details: - Data path Din[0]_MGIOL to SLICE_22: + Data path Din[7]_MGIOL to SLICE_22: Name Fanout Delay (ns) Site Resource -C2INP_DEL --- 0.577 IOL_L2C.CLK to IOL_L2C.IN Din[0]_MGIOL (from PHI2_c) -ROUTE 1 1.802 IOL_L2C.IN to R3C8A.D0 Bank[0] -CTOF_DEL --- 0.495 R3C8A.D0 to R3C8A.F0 SLICE_93 -ROUTE 1 0.958 R3C8A.F0 to R2C6B.D0 un1_CmdEnable20_0_0_o3_10 -CTOF_DEL --- 0.495 R2C6B.D0 to R2C6B.F0 SLICE_84 -ROUTE 6 1.506 R2C6B.F0 to R3C9D.A1 un1_CmdEnable20_0_0_o3 -CTOF_DEL --- 0.495 R3C9D.A1 to R3C9D.F1 SLICE_23 -ROUTE 8 1.450 R3C9D.F1 to R4C9D.A0 XOR8MEG18 -CTOF_DEL --- 0.495 R4C9D.A0 to R4C9D.F0 SLICE_22 +C2INP_DEL --- 0.577 IOL_L2A.CLK to IOL_L2A.IN Din[7]_MGIOL (from PHI2_c) +ROUTE 1 1.995 IOL_L2A.IN to R5C6A.C0 Bank[7] +CTOF_DEL --- 0.495 R5C6A.C0 to R5C6A.F0 SLICE_90 +ROUTE 1 1.299 R5C6A.F0 to R2C6C.A0 un1_CmdEnable20_0_0_o2_10 +CTOF_DEL --- 0.495 R2C6C.A0 to R2C6C.F0 SLICE_80 +ROUTE 6 1.993 R2C6C.F0 to R4C8A.B1 N_367 +CTOF_DEL --- 0.495 R4C8A.B1 to R4C8A.F1 SLICE_23 +ROUTE 8 0.796 R4C8A.F1 to R4C9D.C0 XOR8MEG18 +CTOF_DEL --- 0.495 R4C9D.C0 to R4C9D.F0 SLICE_22 ROUTE 1 0.000 R4C9D.F0 to R4C9D.DI0 CmdValid_r (to PHI2_c) -------- - 8.273 (30.9% logic, 69.1% route), 5 logic levels. + 8.640 (29.6% logic, 70.4% route), 5 logic levels. Clock Skew Details: - Source Clock Path PHI2 to Din[0]_MGIOL: + Source Clock Path PHI2 to Din[7]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 21 3.712 8.PADDI to IOL_L2C.CLK PHI2_c +ROUTE 21 3.712 8.PADDI to IOL_L2A.CLK PHI2_c -------- 3.712 (0.0% logic, 100.0% route), 0 logic levels. @@ -350,94 +507,39 @@ ROUTE 21 3.539 8.PADDI to R4C9D.CLK PHI2_c 3.539 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 163.870ns (weighted slack = 327.740ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_0io[2] (from PHI2_c +) - Destination: FF Data in CmdEnable (to PHI2_c -) - - Delay: 8.205ns (37.2% logic, 62.8% route), 6 logic levels. - - Constraint Details: - - 8.205ns physical path delay Din[2]_MGIOL to SLICE_17 meets - 172.414ns delay constraint less - 0.173ns skew and - 0.166ns DIN_SET requirement (totaling 172.075ns) by 163.870ns - - Physical Path Details: - - Data path Din[2]_MGIOL to SLICE_17: - - Name Fanout Delay (ns) Site Resource -C2INP_DEL --- 0.577 IOL_T9A.CLK to IOL_T9A.IN Din[2]_MGIOL (from PHI2_c) -ROUTE 1 1.496 IOL_T9A.IN to R3C8A.C0 Bank[2] -CTOF_DEL --- 0.495 R3C8A.C0 to R3C8A.F0 SLICE_93 -ROUTE 1 0.958 R3C8A.F0 to R2C6B.D0 un1_CmdEnable20_0_0_o3_10 -CTOF_DEL --- 0.495 R2C6B.D0 to R2C6B.F0 SLICE_84 -ROUTE 6 1.617 R2C6B.F0 to R4C11D.D1 un1_CmdEnable20_0_0_o3 -CTOF_DEL --- 0.495 R4C11D.D1 to R4C11D.F1 SLICE_11 -ROUTE 3 0.767 R4C11D.F1 to R3C11D.C0 CmdEnable16 -CTOF_DEL --- 0.495 R3C11D.C0 to R3C11D.F0 SLICE_33 -ROUTE 1 0.315 R3C11D.F0 to R3C11C.D0 CmdEnable_0_sqmuxa -CTOF_DEL --- 0.495 R3C11C.D0 to R3C11C.F0 SLICE_17 -ROUTE 1 0.000 R3C11C.F0 to R3C11C.DI0 CmdEnable_s (to PHI2_c) - -------- - 8.205 (37.2% logic, 62.8% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to Din[2]_MGIOL: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 3.712 8.PADDI to IOL_T9A.CLK PHI2_c - -------- - 3.712 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_17: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 3.539 8.PADDI to R3C11C.CLK PHI2_c - -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 163.944ns (weighted slack = 327.888ns) +Passed: The following path meets requirements by 163.445ns (weighted slack = 326.890ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Bank_0io[5] (from PHI2_c +) - Destination: FF Data in CmdEnable (to PHI2_c -) + Destination: FF Data in CmdUFMData (to PHI2_c -) - Delay: 8.131ns (37.5% logic, 62.5% route), 6 logic levels. + Delay: 8.489ns (30.1% logic, 69.9% route), 5 logic levels. Constraint Details: - 8.131ns physical path delay Din[5]_MGIOL to SLICE_17 meets + 8.489ns physical path delay Din[5]_MGIOL to SLICE_19 meets 172.414ns delay constraint less 0.173ns skew and - 0.166ns DIN_SET requirement (totaling 172.075ns) by 163.944ns + 0.307ns CE_SET requirement (totaling 171.934ns) by 163.445ns Physical Path Details: - Data path Din[5]_MGIOL to SLICE_17: + Data path Din[5]_MGIOL to SLICE_19: Name Fanout Delay (ns) Site Resource C2INP_DEL --- 0.577 IOL_T6B.CLK to IOL_T6B.IN Din[5]_MGIOL (from PHI2_c) -ROUTE 1 1.944 IOL_T6B.IN to R2C6B.A1 Bank[5] -CTOF_DEL --- 0.495 R2C6B.A1 to R2C6B.F1 SLICE_84 -ROUTE 1 0.436 R2C6B.F1 to R2C6B.C0 un1_CmdEnable20_0_0_o3_11 -CTOF_DEL --- 0.495 R2C6B.C0 to R2C6B.F0 SLICE_84 -ROUTE 6 1.617 R2C6B.F0 to R4C11D.D1 un1_CmdEnable20_0_0_o3 -CTOF_DEL --- 0.495 R4C11D.D1 to R4C11D.F1 SLICE_11 -ROUTE 3 0.767 R4C11D.F1 to R3C11D.C0 CmdEnable16 -CTOF_DEL --- 0.495 R3C11D.C0 to R3C11D.F0 SLICE_33 -ROUTE 1 0.315 R3C11D.F0 to R3C11C.D0 CmdEnable_0_sqmuxa -CTOF_DEL --- 0.495 R3C11C.D0 to R3C11C.F0 SLICE_17 -ROUTE 1 0.000 R3C11C.F0 to R3C11C.DI0 CmdEnable_s (to PHI2_c) +ROUTE 1 1.204 IOL_T6B.IN to R2C6C.A1 Bank[5] +CTOF_DEL --- 0.495 R2C6C.A1 to R2C6C.F1 SLICE_80 +ROUTE 1 0.436 R2C6C.F1 to R2C6C.C0 un1_CmdEnable20_0_0_o2_11 +CTOF_DEL --- 0.495 R2C6C.C0 to R2C6C.F0 SLICE_80 +ROUTE 6 1.993 R2C6C.F0 to R4C8A.B1 N_367 +CTOF_DEL --- 0.495 R4C8A.B1 to R4C8A.F1 SLICE_23 +ROUTE 8 1.230 R4C8A.F1 to R5C9A.C0 XOR8MEG18 +CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_77 +ROUTE 1 1.069 R5C9A.F0 to R5C10B.CE CmdUFMData_1_sqmuxa (to PHI2_c) -------- - 8.131 (37.5% logic, 62.5% route), 6 logic levels. + 8.489 (30.1% logic, 69.9% route), 5 logic levels. Clock Skew Details: @@ -448,116 +550,14 @@ ROUTE 21 3.712 8.PADDI to IOL_T6B.CLK PHI2_c -------- 3.712 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_17: + Destination Clock Path PHI2 to SLICE_19: Name Fanout Delay (ns) Site Resource -ROUTE 21 3.539 8.PADDI to R3C11C.CLK PHI2_c +ROUTE 21 3.539 8.PADDI to R5C10B.CLK PHI2_c -------- 3.539 (0.0% logic, 100.0% route), 0 logic levels. - -Passed: The following path meets requirements by 164.035ns (weighted slack = 328.070ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_0io[1] (from PHI2_c +) - Destination: FF Data in CmdUFMData (to PHI2_c -) - - Delay: 7.899ns (32.4% logic, 67.6% route), 5 logic levels. - - Constraint Details: - - 7.899ns physical path delay Din[1]_MGIOL to SLICE_82 meets - 172.414ns delay constraint less - 0.173ns skew and - 0.307ns CE_SET requirement (totaling 171.934ns) by 164.035ns - - Physical Path Details: - - Data path Din[1]_MGIOL to SLICE_82: - - Name Fanout Delay (ns) Site Resource -C2INP_DEL --- 0.577 IOL_T6D.CLK to IOL_T6D.IN Din[1]_MGIOL (from PHI2_c) -ROUTE 1 1.260 IOL_T6D.IN to R2C6B.D1 Bank[1] -CTOF_DEL --- 0.495 R2C6B.D1 to R2C6B.F1 SLICE_84 -ROUTE 1 0.436 R2C6B.F1 to R2C6B.C0 un1_CmdEnable20_0_0_o3_11 -CTOF_DEL --- 0.495 R2C6B.C0 to R2C6B.F0 SLICE_84 -ROUTE 6 1.506 R2C6B.F0 to R3C9D.A1 un1_CmdEnable20_0_0_o3 -CTOF_DEL --- 0.495 R3C9D.A1 to R3C9D.F1 SLICE_23 -ROUTE 8 1.487 R3C9D.F1 to R4C9C.B0 XOR8MEG18 -CTOF_DEL --- 0.495 R4C9C.B0 to R4C9C.F0 SLICE_82 -ROUTE 1 0.653 R4C9C.F0 to R4C9C.CE CmdUFMData_1_sqmuxa (to PHI2_c) - -------- - 7.899 (32.4% logic, 67.6% route), 5 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to Din[1]_MGIOL: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 3.712 8.PADDI to IOL_T6D.CLK PHI2_c - -------- - 3.712 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_82: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 3.539 8.PADDI to R4C9C.CLK PHI2_c - -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 164.044ns (weighted slack = 328.088ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_0io[0] (from PHI2_c +) - Destination: FF Data in ADSubmitted (to PHI2_c -) - - Delay: 8.031ns (31.8% logic, 68.2% route), 5 logic levels. - - Constraint Details: - - 8.031ns physical path delay Din[0]_MGIOL to SLICE_10 meets - 172.414ns delay constraint less - 0.173ns skew and - 0.166ns DIN_SET requirement (totaling 172.075ns) by 164.044ns - - Physical Path Details: - - Data path Din[0]_MGIOL to SLICE_10: - - Name Fanout Delay (ns) Site Resource -C2INP_DEL --- 0.577 IOL_L2C.CLK to IOL_L2C.IN Din[0]_MGIOL (from PHI2_c) -ROUTE 1 1.802 IOL_L2C.IN to R3C8A.D0 Bank[0] -CTOF_DEL --- 0.495 R3C8A.D0 to R3C8A.F0 SLICE_93 -ROUTE 1 0.958 R3C8A.F0 to R2C6B.D0 un1_CmdEnable20_0_0_o3_10 -CTOF_DEL --- 0.495 R2C6B.D0 to R2C6B.F0 SLICE_84 -ROUTE 6 1.958 R2C6B.F0 to R3C11C.A1 un1_CmdEnable20_0_0_o3 -CTOF_DEL --- 0.495 R3C11C.A1 to R3C11C.F1 SLICE_17 -ROUTE 2 0.756 R3C11C.F1 to R3C11A.C0 CmdEnable17 -CTOF_DEL --- 0.495 R3C11A.C0 to R3C11A.F0 SLICE_10 -ROUTE 1 0.000 R3C11A.F0 to R3C11A.DI0 ADSubmitted_r_0_0 (to PHI2_c) - -------- - 8.031 (31.8% logic, 68.2% route), 5 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to Din[0]_MGIOL: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 3.712 8.PADDI to IOL_L2C.CLK PHI2_c - -------- - 3.712 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_10: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 3.539 8.PADDI to R3C11A.CLK PHI2_c - -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. - -Report: 52.949MHz is the maximum frequency for this preference. +Report: 47.068MHz is the maximum frequency for this preference. ================================================================================ @@ -598,25 +598,88 @@ Report: 150.150MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; - 878 items scored, 0 timing errors detected. + 891 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- -Passed: The following path meets requirements by 5.772ns +Passed: The following path meets requirements by 6.226ns + The internal maximum frequency of the following component is 102.312 MHz + + Logical Details: Cell type Pin name Component name + + Destination: EFB WBCLKI ufmefb/EFBInst_0 + + Delay: 9.774ns -- based on Minimum Pulse Width + + +Passed: The following path meets requirements by 6.245ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[14] (from RCLK_c +) + Destination: FF Data in wb_dati[1] (to RCLK_c +) + + Delay: 9.589ns (30.5% logic, 69.5% route), 6 logic levels. + + Constraint Details: + + 9.589ns physical path delay SLICE_3 to SLICE_52 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 15.834ns) by 6.245ns + + Physical Path Details: + + Data path SLICE_3 to SLICE_52: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R6C3D.CLK to R6C3D.Q1 SLICE_3 (from RCLK_c) +ROUTE 19 2.021 R6C3D.Q1 to R3C4C.D1 FS[14] +CTOF_DEL --- 0.495 R3C4C.D1 to R3C4C.F1 SLICE_118 +ROUTE 2 1.392 R3C4C.F1 to R4C4C.A0 wb_dati_5_1_iv_0_a2_7[4] +CTOF_DEL --- 0.495 R4C4C.A0 to R4C4C.F0 SLICE_97 +ROUTE 1 0.967 R4C4C.F0 to R4C4A.A0 wb_dati_5_1_iv_0_a2_0_2[1] +CTOF_DEL --- 0.495 R4C4A.A0 to R4C4A.F0 SLICE_64 +ROUTE 1 1.535 R4C4A.F0 to R2C4B.B0 wb_dati_5_1_iv_0_0[1] +CTOF_DEL --- 0.495 R2C4B.B0 to R2C4B.F0 SLICE_85 +ROUTE 1 0.747 R2C4B.F0 to R2C4C.C1 wb_dati_5_1_iv_0_1[1] +CTOF_DEL --- 0.495 R2C4C.C1 to R2C4C.F1 SLICE_52 +ROUTE 1 0.000 R2C4C.F1 to R2C4C.DI1 wb_dati_5[1] (to RCLK_c) + -------- + 9.589 (30.5% logic, 69.5% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.019 63.PADDI to R6C3D.CLK RCLK_c + -------- + 2.019 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_52: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.019 63.PADDI to R2C4C.CLK RCLK_c + -------- + 2.019 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 6.252ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: EFB Port ufmefb/EFBInst_0(ASIC) (from RCLK_c +) Destination: FF Data in n8MEGEN (to RCLK_c +) - Delay: 9.889ns (73.5% logic, 26.5% route), 3 logic levels. + Delay: 9.409ns (77.2% logic, 22.8% route), 3 logic levels. Constraint Details: - 9.889ns physical path delay ufmefb/EFBInst_0 to SLICE_45 meets + 9.409ns physical path delay ufmefb/EFBInst_0 to SLICE_45 meets 16.000ns delay constraint less 0.173ns skew and - 0.166ns DIN_SET requirement (totaling 15.661ns) by 5.772ns + 0.166ns DIN_SET requirement (totaling 15.661ns) by 6.252ns Physical Path Details: @@ -624,46 +687,99 @@ Passed: The following path meets requirements by 5.772ns Name Fanout Delay (ns) Site Resource WCLKI2WBDA --- 6.278 EFB.WBCLKI to EFB.WBDATO0 ufmefb/EFBInst_0 (from RCLK_c) -ROUTE 1 1.995 EFB.WBDATO0 to R4C8D.C1 wb_dato[0] -CTOF_DEL --- 0.495 R4C8D.C1 to R4C8D.F1 SLICE_122 -ROUTE 1 0.626 R4C8D.F1 to R4C8C.D0 n8MEGENe_1_0 -CTOF_DEL --- 0.495 R4C8C.D0 to R4C8C.F0 SLICE_45 -ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 n8MEGENe_0 (to RCLK_c) +ROUTE 1 0.984 EFB.WBDATO0 to R3C3A.C1 wb_dato[0] +CTOF_DEL --- 0.495 R3C3A.C1 to R3C3A.F1 SLICE_111 +ROUTE 1 1.157 R3C3A.F1 to R4C6D.D0 n8MEGENe_1_0 +CTOF_DEL --- 0.495 R4C6D.D0 to R4C6D.F0 SLICE_45 +ROUTE 1 0.000 R4C6D.F0 to R4C6D.DI0 n8MEGENe_0 (to RCLK_c) -------- - 9.889 (73.5% logic, 26.5% route), 3 logic levels. + 9.409 (77.2% logic, 22.8% route), 3 logic levels. Clock Skew Details: Source Clock Path RCLK to ufmefb/EFBInst_0: Name Fanout Delay (ns) Site Resource -ROUTE 47 2.192 63.PADDI to EFB.WBCLKI RCLK_c +ROUTE 48 2.192 63.PADDI to EFB.WBCLKI RCLK_c -------- 2.192 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_45: Name Fanout Delay (ns) Site Resource -ROUTE 47 2.019 63.PADDI to R4C8C.CLK RCLK_c +ROUTE 48 2.019 63.PADDI to R4C6D.CLK RCLK_c -------- 2.019 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 6.522ns +Passed: The following path meets requirements by 6.570ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[12] (from RCLK_c +) + Destination: FF Data in wb_dati[1] (to RCLK_c +) + + Delay: 9.264ns (31.6% logic, 68.4% route), 6 logic levels. + + Constraint Details: + + 9.264ns physical path delay SLICE_4 to SLICE_52 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 15.834ns) by 6.570ns + + Physical Path Details: + + Data path SLICE_4 to SLICE_52: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R6C3C.CLK to R6C3C.Q1 SLICE_4 (from RCLK_c) +ROUTE 19 1.696 R6C3C.Q1 to R3C4C.C1 FS[12] +CTOF_DEL --- 0.495 R3C4C.C1 to R3C4C.F1 SLICE_118 +ROUTE 2 1.392 R3C4C.F1 to R4C4C.A0 wb_dati_5_1_iv_0_a2_7[4] +CTOF_DEL --- 0.495 R4C4C.A0 to R4C4C.F0 SLICE_97 +ROUTE 1 0.967 R4C4C.F0 to R4C4A.A0 wb_dati_5_1_iv_0_a2_0_2[1] +CTOF_DEL --- 0.495 R4C4A.A0 to R4C4A.F0 SLICE_64 +ROUTE 1 1.535 R4C4A.F0 to R2C4B.B0 wb_dati_5_1_iv_0_0[1] +CTOF_DEL --- 0.495 R2C4B.B0 to R2C4B.F0 SLICE_85 +ROUTE 1 0.747 R2C4B.F0 to R2C4C.C1 wb_dati_5_1_iv_0_1[1] +CTOF_DEL --- 0.495 R2C4C.C1 to R2C4C.F1 SLICE_52 +ROUTE 1 0.000 R2C4C.F1 to R2C4C.DI1 wb_dati_5[1] (to RCLK_c) + -------- + 9.264 (31.6% logic, 68.4% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_4: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.019 63.PADDI to R6C3C.CLK RCLK_c + -------- + 2.019 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_52: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.019 63.PADDI to R2C4C.CLK RCLK_c + -------- + 2.019 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 6.779ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: EFB Port ufmefb/EFBInst_0(ASIC) (from RCLK_c +) Destination: FF Data in LEDEN (to RCLK_c +) - Delay: 9.139ns (70.6% logic, 29.4% route), 3 logic levels. + Delay: 8.882ns (72.6% logic, 27.4% route), 3 logic levels. Constraint Details: - 9.139ns physical path delay ufmefb/EFBInst_0 to SLICE_30 meets + 8.882ns physical path delay ufmefb/EFBInst_0 to SLICE_30 meets 16.000ns delay constraint less 0.173ns skew and - 0.166ns DIN_SET requirement (totaling 15.661ns) by 6.522ns + 0.166ns DIN_SET requirement (totaling 15.661ns) by 6.779ns Physical Path Details: @@ -671,46 +787,258 @@ Passed: The following path meets requirements by 6.522ns Name Fanout Delay (ns) Site Resource WCLKI2WBDA --- 5.461 EFB.WBCLKI to EFB.WBDATO1 ufmefb/EFBInst_0 (from RCLK_c) -ROUTE 1 1.995 EFB.WBDATO1 to R4C8A.C1 wb_dato[1] -CTOF_DEL --- 0.495 R4C8A.C1 to R4C8A.F1 SLICE_30 -ROUTE 1 0.693 R4C8A.F1 to R4C8A.B0 LEDEN_6_i_m2_i_m2 -CTOF_DEL --- 0.495 R4C8A.B0 to R4C8A.F0 SLICE_30 -ROUTE 1 0.000 R4C8A.F0 to R4C8A.DI0 LEDENe_0 (to RCLK_c) +ROUTE 1 1.995 EFB.WBDATO1 to R4C6B.C1 wb_dato[1] +CTOF_DEL --- 0.495 R4C6B.C1 to R4C6B.F1 SLICE_30 +ROUTE 1 0.436 R4C6B.F1 to R4C6B.C0 LEDEN_6 +CTOF_DEL --- 0.495 R4C6B.C0 to R4C6B.F0 SLICE_30 +ROUTE 1 0.000 R4C6B.F0 to R4C6B.DI0 LEDENe_0 (to RCLK_c) -------- - 9.139 (70.6% logic, 29.4% route), 3 logic levels. + 8.882 (72.6% logic, 27.4% route), 3 logic levels. Clock Skew Details: Source Clock Path RCLK to ufmefb/EFBInst_0: Name Fanout Delay (ns) Site Resource -ROUTE 47 2.192 63.PADDI to EFB.WBCLKI RCLK_c +ROUTE 48 2.192 63.PADDI to EFB.WBCLKI RCLK_c -------- 2.192 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_30: Name Fanout Delay (ns) Site Resource -ROUTE 47 2.019 63.PADDI to R4C8A.CLK RCLK_c +ROUTE 48 2.019 63.PADDI to R4C6B.CLK RCLK_c -------- 2.019 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 6.683ns +Passed: The following path meets requirements by 6.810ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[17] (from RCLK_c +) + Destination: FF Data in wb_dati[6] (to RCLK_c +) + + Delay: 9.024ns (32.4% logic, 67.6% route), 6 logic levels. + + Constraint Details: + + 9.024ns physical path delay SLICE_1 to SLICE_55 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 15.834ns) by 6.810ns + + Physical Path Details: + + Data path SLICE_1 to SLICE_55: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R6C4B.CLK to R6C4B.Q0 SLICE_1 (from RCLK_c) +ROUTE 7 1.729 R6C4B.Q0 to R4C4A.C1 FS[17] +CTOF_DEL --- 0.495 R4C4A.C1 to R4C4A.F1 SLICE_64 +ROUTE 12 1.800 R4C4A.F1 to R3C4A.A1 FS_RNIHVJI[15] +CTOF_DEL --- 0.495 R3C4A.A1 to R3C4A.F1 SLICE_84 +ROUTE 4 0.643 R3C4A.F1 to R3C4A.D0 wb_dati_5_1_iv_0_a2_13[3] +CTOF_DEL --- 0.495 R3C4A.D0 to R3C4A.F0 SLICE_84 +ROUTE 1 0.626 R3C4A.F0 to R3C4D.D0 wb_dati_5_1_iv_0_0_a2[6] +CTOF_DEL --- 0.495 R3C4D.D0 to R3C4D.F0 SLICE_81 +ROUTE 1 1.299 R3C4D.F0 to R2C5B.A0 wb_dati_5_1_iv_0_0_1[6] +CTOF_DEL --- 0.495 R2C5B.A0 to R2C5B.F0 SLICE_55 +ROUTE 1 0.000 R2C5B.F0 to R2C5B.DI0 wb_dati_5[6] (to RCLK_c) + -------- + 9.024 (32.4% logic, 67.6% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_1: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.019 63.PADDI to R6C4B.CLK RCLK_c + -------- + 2.019 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_55: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.019 63.PADDI to R2C5B.CLK RCLK_c + -------- + 2.019 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 7.148ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[9] (from RCLK_c +) + Destination: FF Data in wb_dati[1] (to RCLK_c +) + + Delay: 8.686ns (33.7% logic, 66.3% route), 6 logic levels. + + Constraint Details: + + 8.686ns physical path delay SLICE_5 to SLICE_52 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.148ns + + Physical Path Details: + + Data path SLICE_5 to SLICE_52: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R6C3B.CLK to R6C3B.Q0 SLICE_5 (from RCLK_c) +ROUTE 17 1.867 R6C3B.Q0 to R4C4C.B1 FS[9] +CTOF_DEL --- 0.495 R4C4C.B1 to R4C4C.F1 SLICE_97 +ROUTE 3 0.643 R4C4C.F1 to R4C4C.D0 wb_dati_5_1_iv_0_o2_0[7] +CTOF_DEL --- 0.495 R4C4C.D0 to R4C4C.F0 SLICE_97 +ROUTE 1 0.967 R4C4C.F0 to R4C4A.A0 wb_dati_5_1_iv_0_a2_0_2[1] +CTOF_DEL --- 0.495 R4C4A.A0 to R4C4A.F0 SLICE_64 +ROUTE 1 1.535 R4C4A.F0 to R2C4B.B0 wb_dati_5_1_iv_0_0[1] +CTOF_DEL --- 0.495 R2C4B.B0 to R2C4B.F0 SLICE_85 +ROUTE 1 0.747 R2C4B.F0 to R2C4C.C1 wb_dati_5_1_iv_0_1[1] +CTOF_DEL --- 0.495 R2C4C.C1 to R2C4C.F1 SLICE_52 +ROUTE 1 0.000 R2C4C.F1 to R2C4C.DI1 wb_dati_5[1] (to RCLK_c) + -------- + 8.686 (33.7% logic, 66.3% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_5: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.019 63.PADDI to R6C3B.CLK RCLK_c + -------- + 2.019 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_52: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.019 63.PADDI to R2C4C.CLK RCLK_c + -------- + 2.019 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 7.149ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[15] (from RCLK_c +) + Destination: FF Data in wb_dati[6] (to RCLK_c +) + + Delay: 8.685ns (33.7% logic, 66.3% route), 6 logic levels. + + Constraint Details: + + 8.685ns physical path delay SLICE_2 to SLICE_55 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.149ns + + Physical Path Details: + + Data path SLICE_2 to SLICE_55: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R6C4A.CLK to R6C4A.Q0 SLICE_2 (from RCLK_c) +ROUTE 6 1.390 R6C4A.Q0 to R4C4A.B1 FS[15] +CTOF_DEL --- 0.495 R4C4A.B1 to R4C4A.F1 SLICE_64 +ROUTE 12 1.800 R4C4A.F1 to R3C4A.A1 FS_RNIHVJI[15] +CTOF_DEL --- 0.495 R3C4A.A1 to R3C4A.F1 SLICE_84 +ROUTE 4 0.643 R3C4A.F1 to R3C4A.D0 wb_dati_5_1_iv_0_a2_13[3] +CTOF_DEL --- 0.495 R3C4A.D0 to R3C4A.F0 SLICE_84 +ROUTE 1 0.626 R3C4A.F0 to R3C4D.D0 wb_dati_5_1_iv_0_0_a2[6] +CTOF_DEL --- 0.495 R3C4D.D0 to R3C4D.F0 SLICE_81 +ROUTE 1 1.299 R3C4D.F0 to R2C5B.A0 wb_dati_5_1_iv_0_0_1[6] +CTOF_DEL --- 0.495 R2C5B.A0 to R2C5B.F0 SLICE_55 +ROUTE 1 0.000 R2C5B.F0 to R2C5B.DI0 wb_dati_5[6] (to RCLK_c) + -------- + 8.685 (33.7% logic, 66.3% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_2: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.019 63.PADDI to R6C4A.CLK RCLK_c + -------- + 2.019 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_55: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.019 63.PADDI to R2C5B.CLK RCLK_c + -------- + 2.019 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 7.154ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[17] (from RCLK_c +) + Destination: FF Data in wb_dati[4] (to RCLK_c +) + + Delay: 8.680ns (33.7% logic, 66.3% route), 6 logic levels. + + Constraint Details: + + 8.680ns physical path delay SLICE_1 to SLICE_54 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.154ns + + Physical Path Details: + + Data path SLICE_1 to SLICE_54: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R6C4B.CLK to R6C4B.Q0 SLICE_1 (from RCLK_c) +ROUTE 7 1.729 R6C4B.Q0 to R4C4A.C1 FS[17] +CTOF_DEL --- 0.495 R4C4A.C1 to R4C4A.F1 SLICE_64 +ROUTE 12 1.019 R4C4A.F1 to R2C3B.D1 FS_RNIHVJI[15] +CTOF_DEL --- 0.495 R2C3B.D1 to R2C3B.F1 SLICE_87 +ROUTE 4 0.994 R2C3B.F1 to R3C4D.D1 wb_dati_5_1_iv_0_a2_12[3] +CTOF_DEL --- 0.495 R3C4D.D1 to R3C4D.F1 SLICE_81 +ROUTE 2 1.010 R3C4D.F1 to R3C3A.B0 wb_dati_5_1_iv_0_a2_2[4] +CTOF_DEL --- 0.495 R3C3A.B0 to R3C3A.F0 SLICE_111 +ROUTE 1 1.001 R3C3A.F0 to R2C3D.B0 wb_dati_5_1_iv_0_0_1[4] +CTOF_DEL --- 0.495 R2C3D.B0 to R2C3D.F0 SLICE_54 +ROUTE 1 0.000 R2C3D.F0 to R2C3D.DI0 wb_dati_5[4] (to RCLK_c) + -------- + 8.680 (33.7% logic, 66.3% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_1: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.019 63.PADDI to R6C4B.CLK RCLK_c + -------- + 2.019 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_54: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.019 63.PADDI to R2C3D.CLK RCLK_c + -------- + 2.019 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 7.228ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: EFB Port ufmefb/EFBInst_0(ASIC) (from RCLK_c +) Destination: FF Data in LEDEN (to RCLK_c +) - Delay: 8.978ns (48.2% logic, 51.8% route), 5 logic levels. + Delay: 8.433ns (51.3% logic, 48.7% route), 5 logic levels. Constraint Details: - 8.978ns physical path delay ufmefb/EFBInst_0 to SLICE_30 meets + 8.433ns physical path delay ufmefb/EFBInst_0 to SLICE_30 meets 16.000ns delay constraint less 0.173ns skew and - 0.166ns DIN_SET requirement (totaling 15.661ns) by 6.683ns + 0.166ns DIN_SET requirement (totaling 15.661ns) by 7.228ns Physical Path Details: @@ -718,410 +1046,88 @@ Passed: The following path meets requirements by 6.683ns Name Fanout Delay (ns) Site Resource WCLKI2WBAC --- 2.343 EFB.WBCLKI to EFB.WBACKO ufmefb/EFBInst_0 (from RCLK_c) -ROUTE 2 2.309 EFB.WBACKO to R4C7B.D0 wb_ack -CTOF_DEL --- 0.495 R4C7B.D0 to R4C7B.F0 SLICE_104 -ROUTE 1 0.626 R4C7B.F0 to R4C7D.D0 ufmefb/g0_0_a3_2 -CTOF_DEL --- 0.495 R4C7D.D0 to R4C7D.F0 SLICE_68 -ROUTE 1 0.744 R4C7D.F0 to R4C8C.C1 N_4 -CTOF_DEL --- 0.495 R4C8C.C1 to R4C8C.F1 SLICE_45 -ROUTE 2 0.976 R4C8C.F1 to R4C8A.A0 CmdValid_RNIOOBE2 -CTOF_DEL --- 0.495 R4C8A.A0 to R4C8A.F0 SLICE_30 -ROUTE 1 0.000 R4C8A.F0 to R4C8A.DI0 LEDENe_0 (to RCLK_c) +ROUTE 2 1.504 EFB.WBACKO to R3C5C.C0 wb_ack +CTOF_DEL --- 0.495 R3C5C.C0 to R3C5C.F0 SLICE_102 +ROUTE 1 0.315 R3C5C.F0 to R3C5B.D0 ufmefb/g0_0_a3_2 +CTOF_DEL --- 0.495 R3C5B.D0 to R3C5B.F0 SLICE_66 +ROUTE 1 1.278 R3C5B.F0 to R4C6D.C1 N_4 +CTOF_DEL --- 0.495 R4C6D.C1 to R4C6D.F1 SLICE_45 +ROUTE 2 1.013 R4C6D.F1 to R4C6B.B0 un1_FS_38_i +CTOF_DEL --- 0.495 R4C6B.B0 to R4C6B.F0 SLICE_30 +ROUTE 1 0.000 R4C6B.F0 to R4C6B.DI0 LEDENe_0 (to RCLK_c) -------- - 8.978 (48.2% logic, 51.8% route), 5 logic levels. + 8.433 (51.3% logic, 48.7% route), 5 logic levels. Clock Skew Details: Source Clock Path RCLK to ufmefb/EFBInst_0: Name Fanout Delay (ns) Site Resource -ROUTE 47 2.192 63.PADDI to EFB.WBCLKI RCLK_c +ROUTE 48 2.192 63.PADDI to EFB.WBCLKI RCLK_c -------- 2.192 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_30: Name Fanout Delay (ns) Site Resource -ROUTE 47 2.019 63.PADDI to R4C8A.CLK RCLK_c +ROUTE 48 2.019 63.PADDI to R4C6B.CLK RCLK_c -------- 2.019 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 6.738ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS[3] (from RCLK_c +) - Destination: FF Data in nRCAS_0io (to RCLK_c +) - - Delay: 9.282ns (36.9% logic, 63.1% route), 7 logic levels. - - Constraint Details: - - 9.282ns physical path delay SLICE_28 to nRCAS_MGIOL meets - 16.000ns delay constraint less - -0.173ns skew and - 0.153ns DO_SET requirement (totaling 16.020ns) by 6.738ns - - Physical Path Details: - - Data path SLICE_28 to nRCAS_MGIOL: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R4C15D.CLK to R4C15D.Q0 SLICE_28 (from RCLK_c) -ROUTE 4 1.183 R4C15D.Q0 to R4C14B.C1 IS[3] -CTOF_DEL --- 0.495 R4C14B.C1 to R4C14B.F1 SLICE_74 -ROUTE 2 0.445 R4C14B.F1 to R4C14B.C0 un1_nRCAS_6_sqmuxa_i_0_0_o2_0 -CTOF_DEL --- 0.495 R4C14B.C0 to R4C14B.F0 SLICE_74 -ROUTE 2 0.758 R4C14B.F0 to R4C13A.C1 N_408 -CTOF_DEL --- 0.495 R4C13A.C1 to R4C13A.F1 SLICE_61 -ROUTE 1 0.626 R4C13A.F1 to R4C13A.D0 un1_nRCAS_6_sqmuxa_i_0_0 -CTOF_DEL --- 0.495 R4C13A.D0 to R4C13A.F0 SLICE_61 -ROUTE 1 0.623 R4C13A.F0 to R5C13A.D0 nRCAS_r_i_0_o2_0_0 -CTOF_DEL --- 0.495 R5C13A.D0 to R5C13A.F0 SLICE_94 -ROUTE 1 0.626 R5C13A.F0 to R5C13A.D1 N_248_i_1 -CTOF_DEL --- 0.495 R5C13A.D1 to R5C13A.F1 SLICE_94 -ROUTE 1 1.599 R5C13A.F1 to IOL_R7C.OPOS N_248_i (to RCLK_c) - -------- - 9.282 (36.9% logic, 63.1% route), 7 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_28: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 2.019 63.PADDI to R4C15D.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to nRCAS_MGIOL: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 2.192 63.PADDI to IOL_R7C.CLK RCLK_c - -------- - 2.192 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 6.917ns +Passed: The following path meets requirements by 7.241ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q IS[1] (from RCLK_c +) Destination: FF Data in nRCAS_0io (to RCLK_c +) - Delay: 9.103ns (37.6% logic, 62.4% route), 7 logic levels. + Delay: 8.779ns (33.3% logic, 66.7% route), 6 logic levels. Constraint Details: - 9.103ns physical path delay SLICE_27 to nRCAS_MGIOL meets + 8.779ns physical path delay SLICE_27 to nRCAS_MGIOL meets 16.000ns delay constraint less -0.173ns skew and - 0.153ns DO_SET requirement (totaling 16.020ns) by 6.917ns + 0.153ns DO_SET requirement (totaling 16.020ns) by 7.241ns Physical Path Details: Data path SLICE_27 to nRCAS_MGIOL: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R4C15A.CLK to R4C15A.Q0 SLICE_27 (from RCLK_c) -ROUTE 7 1.004 R4C15A.Q0 to R4C14B.A1 IS[1] -CTOF_DEL --- 0.495 R4C14B.A1 to R4C14B.F1 SLICE_74 -ROUTE 2 0.445 R4C14B.F1 to R4C14B.C0 un1_nRCAS_6_sqmuxa_i_0_0_o2_0 -CTOF_DEL --- 0.495 R4C14B.C0 to R4C14B.F0 SLICE_74 -ROUTE 2 0.758 R4C14B.F0 to R4C13A.C1 N_408 -CTOF_DEL --- 0.495 R4C13A.C1 to R4C13A.F1 SLICE_61 -ROUTE 1 0.626 R4C13A.F1 to R4C13A.D0 un1_nRCAS_6_sqmuxa_i_0_0 -CTOF_DEL --- 0.495 R4C13A.D0 to R4C13A.F0 SLICE_61 -ROUTE 1 0.623 R4C13A.F0 to R5C13A.D0 nRCAS_r_i_0_o2_0_0 -CTOF_DEL --- 0.495 R5C13A.D0 to R5C13A.F0 SLICE_94 -ROUTE 1 0.626 R5C13A.F0 to R5C13A.D1 N_248_i_1 -CTOF_DEL --- 0.495 R5C13A.D1 to R5C13A.F1 SLICE_94 -ROUTE 1 1.599 R5C13A.F1 to IOL_R7C.OPOS N_248_i (to RCLK_c) +REG_DEL --- 0.452 R4C14D.CLK to R4C14D.Q0 SLICE_27 (from RCLK_c) +ROUTE 7 1.433 R4C14D.Q0 to R5C14C.B1 IS[1] +CTOF_DEL --- 0.495 R5C14C.B1 to R5C14C.F1 SLICE_83 +ROUTE 3 0.673 R5C14C.F1 to R5C14D.A0 un1_nRCAS_6_sqmuxa_i_o2 +CTOF_DEL --- 0.495 R5C14D.A0 to R5C14D.F0 SLICE_62 +ROUTE 2 0.967 R5C14D.F0 to R6C13C.D0 N_48 +CTOF_DEL --- 0.495 R6C13C.D0 to R6C13C.F0 SLICE_69 +ROUTE 1 0.436 R6C13C.F0 to R6C13C.C1 nRCS_9_u_i_o3_0_0 +CTOF_DEL --- 0.495 R6C13C.C1 to R6C13C.F1 SLICE_69 +ROUTE 1 0.744 R6C13C.F1 to R6C14C.C1 nRCS_9_u_i_o3_0_2 +CTOF_DEL --- 0.495 R6C14C.C1 to R6C14C.F1 SLICE_101 +ROUTE 1 1.599 R6C14C.F1 to IOL_R7C.OPOS N_251_i (to RCLK_c) -------- - 9.103 (37.6% logic, 62.4% route), 7 logic levels. + 8.779 (33.3% logic, 66.7% route), 6 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_27: Name Fanout Delay (ns) Site Resource -ROUTE 47 2.019 63.PADDI to R4C15A.CLK RCLK_c +ROUTE 48 2.019 63.PADDI to R4C14D.CLK RCLK_c -------- 2.019 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to nRCAS_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 47 2.192 63.PADDI to IOL_R7C.CLK RCLK_c +ROUTE 48 2.192 63.PADDI to IOL_R7C.CLK RCLK_c -------- 2.192 (0.0% logic, 100.0% route), 0 logic levels. - -Passed: The following path meets requirements by 7.044ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q InitReady (from RCLK_c +) - Destination: FF Data in wb_dati[4] (to RCLK_c +) - - Delay: 8.790ns (33.3% logic, 66.7% route), 6 logic levels. - - Constraint Details: - - 8.790ns physical path delay SLICE_29 to SLICE_54 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.044ns - - Physical Path Details: - - Data path SLICE_29 to SLICE_54: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R4C7C.CLK to R4C7C.Q0 SLICE_29 (from RCLK_c) -ROUTE 41 1.468 R4C7C.Q0 to R2C5D.D1 InitReady -CTOF_DEL --- 0.495 R2C5D.D1 to R2C5D.F1 SLICE_66 -ROUTE 13 1.119 R2C5D.F1 to R3C6C.C0 N_214 -CTOF_DEL --- 0.495 R3C6C.C0 to R3C6C.F0 SLICE_113 -ROUTE 2 0.967 R3C6C.F0 to R2C4A.D1 N_576 -CTOF_DEL --- 0.495 R2C4A.D1 to R2C4A.F1 SLICE_85 -ROUTE 2 1.308 R2C4A.F1 to R3C5A.A0 N_473 -CTOF_DEL --- 0.495 R3C5A.A0 to R3C5A.F0 SLICE_86 -ROUTE 1 1.001 R3C5A.F0 to R3C4C.B0 wb_dati_5_1_iv_0_1[4] -CTOF_DEL --- 0.495 R3C4C.B0 to R3C4C.F0 SLICE_54 -ROUTE 1 0.000 R3C4C.F0 to R3C4C.DI0 wb_dati_5[4] (to RCLK_c) - -------- - 8.790 (33.3% logic, 66.7% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_29: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 2.019 63.PADDI to R4C7C.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_54: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 2.019 63.PADDI to R3C4C.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 7.047ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q InitReady (from RCLK_c +) - Destination: FF Data in wb_dati[6] (to RCLK_c +) - - Delay: 8.787ns (33.3% logic, 66.7% route), 6 logic levels. - - Constraint Details: - - 8.787ns physical path delay SLICE_29 to SLICE_55 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.047ns - - Physical Path Details: - - Data path SLICE_29 to SLICE_55: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R4C7C.CLK to R4C7C.Q0 SLICE_29 (from RCLK_c) -ROUTE 41 1.468 R4C7C.Q0 to R2C5D.D1 InitReady -CTOF_DEL --- 0.495 R2C5D.D1 to R2C5D.F1 SLICE_66 -ROUTE 13 0.656 R2C5D.F1 to R3C5C.D1 N_214 -CTOF_DEL --- 0.495 R3C5C.D1 to R3C5C.F1 SLICE_87 -ROUTE 4 1.473 R3C5C.F1 to R4C4D.B0 N_579 -CTOF_DEL --- 0.495 R4C4D.B0 to R4C4D.F0 SLICE_89 -ROUTE 1 1.299 R4C4D.F0 to R2C4A.A0 N_472 -CTOF_DEL --- 0.495 R2C4A.A0 to R2C4A.F0 SLICE_85 -ROUTE 1 0.964 R2C4A.F0 to R2C5B.A0 wb_dati_5_1_iv_0_1[6] -CTOF_DEL --- 0.495 R2C5B.A0 to R2C5B.F0 SLICE_55 -ROUTE 1 0.000 R2C5B.F0 to R2C5B.DI0 wb_dati_5[6] (to RCLK_c) - -------- - 8.787 (33.3% logic, 66.7% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_29: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 2.019 63.PADDI to R4C7C.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_55: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 2.019 63.PADDI to R2C5B.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 7.048ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[17] (from RCLK_c +) - Destination: FF Data in wb_dati[4] (to RCLK_c +) - - Delay: 8.786ns (33.3% logic, 66.7% route), 6 logic levels. - - Constraint Details: - - 8.786ns physical path delay SLICE_1 to SLICE_54 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.048ns - - Physical Path Details: - - Data path SLICE_1 to SLICE_54: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R2C9B.CLK to R2C9B.Q0 SLICE_1 (from RCLK_c) -ROUTE 6 1.464 R2C9B.Q0 to R2C5D.B1 FS[17] -CTOF_DEL --- 0.495 R2C5D.B1 to R2C5D.F1 SLICE_66 -ROUTE 13 1.119 R2C5D.F1 to R3C6C.C0 N_214 -CTOF_DEL --- 0.495 R3C6C.C0 to R3C6C.F0 SLICE_113 -ROUTE 2 0.967 R3C6C.F0 to R2C4A.D1 N_576 -CTOF_DEL --- 0.495 R2C4A.D1 to R2C4A.F1 SLICE_85 -ROUTE 2 1.308 R2C4A.F1 to R3C5A.A0 N_473 -CTOF_DEL --- 0.495 R3C5A.A0 to R3C5A.F0 SLICE_86 -ROUTE 1 1.001 R3C5A.F0 to R3C4C.B0 wb_dati_5_1_iv_0_1[4] -CTOF_DEL --- 0.495 R3C4C.B0 to R3C4C.F0 SLICE_54 -ROUTE 1 0.000 R3C4C.F0 to R3C4C.DI0 wb_dati_5[4] (to RCLK_c) - -------- - 8.786 (33.3% logic, 66.7% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_1: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 2.019 63.PADDI to R2C9B.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_54: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 2.019 63.PADDI to R3C4C.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 7.051ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[17] (from RCLK_c +) - Destination: FF Data in wb_dati[6] (to RCLK_c +) - - Delay: 8.783ns (33.3% logic, 66.7% route), 6 logic levels. - - Constraint Details: - - 8.783ns physical path delay SLICE_1 to SLICE_55 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.051ns - - Physical Path Details: - - Data path SLICE_1 to SLICE_55: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R2C9B.CLK to R2C9B.Q0 SLICE_1 (from RCLK_c) -ROUTE 6 1.464 R2C9B.Q0 to R2C5D.B1 FS[17] -CTOF_DEL --- 0.495 R2C5D.B1 to R2C5D.F1 SLICE_66 -ROUTE 13 0.656 R2C5D.F1 to R3C5C.D1 N_214 -CTOF_DEL --- 0.495 R3C5C.D1 to R3C5C.F1 SLICE_87 -ROUTE 4 1.473 R3C5C.F1 to R4C4D.B0 N_579 -CTOF_DEL --- 0.495 R4C4D.B0 to R4C4D.F0 SLICE_89 -ROUTE 1 1.299 R4C4D.F0 to R2C4A.A0 N_472 -CTOF_DEL --- 0.495 R2C4A.A0 to R2C4A.F0 SLICE_85 -ROUTE 1 0.964 R2C4A.F0 to R2C5B.A0 wb_dati_5_1_iv_0_1[6] -CTOF_DEL --- 0.495 R2C5B.A0 to R2C5B.F0 SLICE_55 -ROUTE 1 0.000 R2C5B.F0 to R2C5B.DI0 wb_dati_5[6] (to RCLK_c) - -------- - 8.783 (33.3% logic, 66.7% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_1: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 2.019 63.PADDI to R2C9B.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_55: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 2.019 63.PADDI to R2C5B.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 7.085ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[16] (from RCLK_c +) - Destination: FF Data in wb_dati[4] (to RCLK_c +) - - Delay: 8.749ns (33.5% logic, 66.5% route), 6 logic levels. - - Constraint Details: - - 8.749ns physical path delay SLICE_2 to SLICE_54 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.085ns - - Physical Path Details: - - Data path SLICE_2 to SLICE_54: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R2C9A.CLK to R2C9A.Q1 SLICE_2 (from RCLK_c) -ROUTE 6 1.427 R2C9A.Q1 to R2C5D.A1 FS[16] -CTOF_DEL --- 0.495 R2C5D.A1 to R2C5D.F1 SLICE_66 -ROUTE 13 1.119 R2C5D.F1 to R3C6C.C0 N_214 -CTOF_DEL --- 0.495 R3C6C.C0 to R3C6C.F0 SLICE_113 -ROUTE 2 0.967 R3C6C.F0 to R2C4A.D1 N_576 -CTOF_DEL --- 0.495 R2C4A.D1 to R2C4A.F1 SLICE_85 -ROUTE 2 1.308 R2C4A.F1 to R3C5A.A0 N_473 -CTOF_DEL --- 0.495 R3C5A.A0 to R3C5A.F0 SLICE_86 -ROUTE 1 1.001 R3C5A.F0 to R3C4C.B0 wb_dati_5_1_iv_0_1[4] -CTOF_DEL --- 0.495 R3C4C.B0 to R3C4C.F0 SLICE_54 -ROUTE 1 0.000 R3C4C.F0 to R3C4C.DI0 wb_dati_5[4] (to RCLK_c) - -------- - 8.749 (33.5% logic, 66.5% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_2: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 2.019 63.PADDI to R2C9A.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_54: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 2.019 63.PADDI to R3C4C.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - -Report: 97.771MHz is the maximum frequency for this preference. +Report: 102.312MHz is the maximum frequency for this preference. Report Summary -------------- @@ -1129,13 +1135,13 @@ Report Summary Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | -FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 52.949 MHz| 5 +FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 47.068 MHz| 5 | | | FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0 | | | FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0 | | | -FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 97.771 MHz| 3 +FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 102.312 MHz| 0 | | | ---------------------------------------------------------------------------- @@ -1160,7 +1166,7 @@ Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11 Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10 No transfer within this clock domain is found -Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47 +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 48 Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ; Data transfers from: @@ -1190,11 +1196,11 @@ Timing summary (Setup): Timing errors: 0 Score: 0 Cumulative negative slack: 0 -Constraints cover 1025 paths, 4 nets, and 758 connections (74.53% coverage) +Constraints cover 1038 paths, 4 nets, and 750 connections (74.18% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 -Thu Sep 21 05:40:01 2023 +Sat Nov 18 02:06:11 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -1244,10 +1250,10 @@ Passed: The following path meets requirements by 0.379ns Data path SLICE_11 to SLICE_11: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R4C11D.CLK to R4C11D.Q0 SLICE_11 (from PHI2_c) -ROUTE 2 0.132 R4C11D.Q0 to R4C11D.A0 C1Submitted -CTOF_DEL --- 0.101 R4C11D.A0 to R4C11D.F0 SLICE_11 -ROUTE 1 0.000 R4C11D.F0 to R4C11D.DI0 C1Submitted_RNO (to PHI2_c) +REG_DEL --- 0.133 R5C8D.CLK to R5C8D.Q0 SLICE_11 (from PHI2_c) +ROUTE 2 0.132 R5C8D.Q0 to R5C8D.A0 C1Submitted +CTOF_DEL --- 0.101 R5C8D.A0 to R5C8D.F0 SLICE_11 +ROUTE 1 0.000 R5C8D.F0 to R5C8D.DI0 C1Submitted_RNO (to PHI2_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. @@ -1256,59 +1262,14 @@ ROUTE 1 0.000 R4C11D.F0 to R4C11D.DI0 C1Submitted_RNO (to P Source Clock Path PHI2 to SLICE_11: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R4C11D.CLK PHI2_c +ROUTE 21 1.240 8.PADDI to R5C8D.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_11: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R4C11D.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.379ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CmdEnable (from PHI2_c -) - Destination: FF Data in CmdEnable (to PHI2_c -) - - Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. - - Constraint Details: - - 0.366ns physical path delay SLICE_17 to SLICE_17 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.379ns - - Physical Path Details: - - Data path SLICE_17 to SLICE_17: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C11C.CLK to R3C11C.Q0 SLICE_17 (from PHI2_c) -ROUTE 2 0.132 R3C11C.Q0 to R3C11C.A0 CmdEnable -CTOF_DEL --- 0.101 R3C11C.A0 to R3C11C.F0 SLICE_17 -ROUTE 1 0.000 R3C11C.F0 to R3C11C.DI0 CmdEnable_s (to PHI2_c) - -------- - 0.366 (63.9% logic, 36.1% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_17: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R3C11C.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_17: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R3C11C.CLK PHI2_c +ROUTE 21 1.240 8.PADDI to R5C8D.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. @@ -1334,10 +1295,10 @@ Passed: The following path meets requirements by 0.379ns Data path SLICE_20 to SLICE_20: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C9B.CLK to R3C9B.Q0 SLICE_20 (from PHI2_c) -ROUTE 2 0.132 R3C9B.Q0 to R3C9B.A0 CmdUFMShift -CTOF_DEL --- 0.101 R3C9B.A0 to R3C9B.F0 SLICE_20 -ROUTE 1 0.000 R3C9B.F0 to R3C9B.DI0 CmdUFMShift_3 (to PHI2_c) +REG_DEL --- 0.133 R4C9A.CLK to R4C9A.Q0 SLICE_20 (from PHI2_c) +ROUTE 2 0.132 R4C9A.Q0 to R4C9A.A0 CmdUFMShift +CTOF_DEL --- 0.101 R4C9A.A0 to R4C9A.F0 SLICE_20 +ROUTE 1 0.000 R4C9A.F0 to R4C9A.DI0 CmdUFMShift_3 (to PHI2_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. @@ -1346,337 +1307,384 @@ ROUTE 1 0.000 R3C9B.F0 to R3C9B.DI0 CmdUFMShift_3 (to PHI Source Clock Path PHI2 to SLICE_20: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R3C9B.CLK PHI2_c +ROUTE 21 1.240 8.PADDI to R4C9A.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_20: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R3C9B.CLK PHI2_c +ROUTE 21 1.240 8.PADDI to R4C9A.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 0.385ns +Passed: The following path meets requirements by 0.382ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ADSubmitted (from PHI2_c -) Destination: FF Data in ADSubmitted (to PHI2_c -) - Delay: 0.372ns (62.9% logic, 37.1% route), 2 logic levels. + Delay: 0.369ns (63.4% logic, 36.6% route), 2 logic levels. Constraint Details: - 0.372ns physical path delay SLICE_10 to SLICE_10 meets + 0.369ns physical path delay SLICE_10 to SLICE_10 meets -0.013ns DIN_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.385ns + 0.000ns skew requirement (totaling -0.013ns) by 0.382ns Physical Path Details: Data path SLICE_10 to SLICE_10: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C11A.CLK to R3C11A.Q0 SLICE_10 (from PHI2_c) -ROUTE 2 0.138 R3C11A.Q0 to R3C11A.D0 ADSubmitted -CTOF_DEL --- 0.101 R3C11A.D0 to R3C11A.F0 SLICE_10 -ROUTE 1 0.000 R3C11A.F0 to R3C11A.DI0 ADSubmitted_r_0_0 (to PHI2_c) +REG_DEL --- 0.133 R5C7C.CLK to R5C7C.Q0 SLICE_10 (from PHI2_c) +ROUTE 2 0.135 R5C7C.Q0 to R5C7C.D0 ADSubmitted +CTOF_DEL --- 0.101 R5C7C.D0 to R5C7C.F0 SLICE_10 +ROUTE 1 0.000 R5C7C.F0 to R5C7C.DI0 ADSubmitted_r_0_0 (to PHI2_c) -------- - 0.372 (62.9% logic, 37.1% route), 2 logic levels. + 0.369 (63.4% logic, 36.6% route), 2 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_10: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R3C11A.CLK PHI2_c +ROUTE 21 1.240 8.PADDI to R5C7C.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_10: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R3C11A.CLK PHI2_c +ROUTE 21 1.240 8.PADDI to R5C7C.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 0.616ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q ADSubmitted (from PHI2_c -) - Destination: FF Data in CmdEnable (to PHI2_c -) - - Delay: 0.603ns (55.6% logic, 44.4% route), 3 logic levels. - - Constraint Details: - - 0.603ns physical path delay SLICE_10 to SLICE_17 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.616ns - - Physical Path Details: - - Data path SLICE_10 to SLICE_17: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C11A.CLK to R3C11A.Q0 SLICE_10 (from PHI2_c) -ROUTE 2 0.215 R3C11A.Q0 to R3C11D.A0 ADSubmitted -CTOF_DEL --- 0.101 R3C11D.A0 to R3C11D.F0 SLICE_33 -ROUTE 1 0.053 R3C11D.F0 to R3C11C.D0 CmdEnable_0_sqmuxa -CTOF_DEL --- 0.101 R3C11C.D0 to R3C11C.F0 SLICE_17 -ROUTE 1 0.000 R3C11C.F0 to R3C11C.DI0 CmdEnable_s (to PHI2_c) - -------- - 0.603 (55.6% logic, 44.4% route), 3 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_10: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R3C11A.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_17: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R3C11C.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.616ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CmdUFMWrite (from PHI2_c -) - Destination: FF Data in CmdUFMWrite (to PHI2_c -) - - Delay: 0.603ns (55.6% logic, 44.4% route), 3 logic levels. - - Constraint Details: - - 0.603ns physical path delay SLICE_21 to SLICE_21 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.616ns - - Physical Path Details: - - Data path SLICE_21 to SLICE_21: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C9C.CLK to R3C9C.Q0 SLICE_21 (from PHI2_c) -ROUTE 2 0.212 R3C9C.Q0 to R3C9C.A1 CmdUFMWrite -CTOF_DEL --- 0.101 R3C9C.A1 to R3C9C.F1 SLICE_21 -ROUTE 1 0.056 R3C9C.F1 to R3C9C.C0 N_462 -CTOF_DEL --- 0.101 R3C9C.C0 to R3C9C.F0 SLICE_21 -ROUTE 1 0.000 R3C9C.F0 to R3C9C.DI0 CmdUFMWrite_3 (to PHI2_c) - -------- - 0.603 (55.6% logic, 44.4% route), 3 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_21: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R3C9C.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_21: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R3C9C.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.627ns +Passed: The following path meets requirements by 0.471ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CmdEnable (from PHI2_c -) - Destination: FF Data in CmdValid_fast (to PHI2_c -) + Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 0.614ns (54.6% logic, 45.4% route), 3 logic levels. + Delay: 0.458ns (51.1% logic, 48.9% route), 2 logic levels. Constraint Details: - 0.614ns physical path delay SLICE_17 to SLICE_23 meets + 0.458ns physical path delay SLICE_17 to SLICE_17 meets -0.013ns DIN_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.627ns + 0.000ns skew requirement (totaling -0.013ns) by 0.471ns Physical Path Details: - Data path SLICE_17 to SLICE_23: + Data path SLICE_17 to SLICE_17: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C11C.CLK to R3C11C.Q0 SLICE_17 (from PHI2_c) -ROUTE 2 0.220 R3C11C.Q0 to R3C9D.D1 CmdEnable -CTOF_DEL --- 0.101 R3C9D.D1 to R3C9D.F1 SLICE_23 -ROUTE 8 0.059 R3C9D.F1 to R3C9D.C0 XOR8MEG18 -CTOF_DEL --- 0.101 R3C9D.C0 to R3C9D.F0 SLICE_23 -ROUTE 1 0.000 R3C9D.F0 to R3C9D.DI0 N_36_fast (to PHI2_c) +REG_DEL --- 0.133 R5C8C.CLK to R5C8C.Q0 SLICE_17 (from PHI2_c) +ROUTE 2 0.224 R5C8C.Q0 to R5C8C.B0 CmdEnable +CTOF_DEL --- 0.101 R5C8C.B0 to R5C8C.F0 SLICE_17 +ROUTE 1 0.000 R5C8C.F0 to R5C8C.DI0 CmdEnable_s (to PHI2_c) -------- - 0.614 (54.6% logic, 45.4% route), 3 logic levels. + 0.458 (51.1% logic, 48.9% route), 2 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_17: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R3C11C.CLK PHI2_c +ROUTE 21 1.240 8.PADDI to R5C8C.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_23: + Destination Clock Path PHI2 to SLICE_17: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R3C9D.CLK PHI2_c +ROUTE 21 1.240 8.PADDI to R5C8C.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.613ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q C1Submitted (from PHI2_c -) + Destination: FF Data in CmdEnable (to PHI2_c -) + + Delay: 0.600ns (55.8% logic, 44.2% route), 3 logic levels. + + Constraint Details: + + 0.600ns physical path delay SLICE_11 to SLICE_17 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.613ns + + Physical Path Details: + + Data path SLICE_11 to SLICE_17: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C8D.CLK to R5C8D.Q0 SLICE_11 (from PHI2_c) +ROUTE 2 0.212 R5C8D.Q0 to R5C8B.A0 C1Submitted +CTOF_DEL --- 0.101 R5C8B.A0 to R5C8B.F0 SLICE_76 +ROUTE 1 0.053 R5C8B.F0 to R5C8C.D0 un1_CmdEnable20_i +CTOF_DEL --- 0.101 R5C8C.D0 to R5C8C.F0 SLICE_17 +ROUTE 1 0.000 R5C8C.F0 to R5C8C.DI0 CmdEnable_s (to PHI2_c) + -------- + 0.600 (55.8% logic, 44.2% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_11: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 1.240 8.PADDI to R5C8D.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_17: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 1.240 8.PADDI to R5C8C.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.616ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdLEDEN (from PHI2_c -) + Destination: FF Data in CmdLEDEN (to PHI2_c -) + + Delay: 0.603ns (55.6% logic, 44.4% route), 3 logic levels. + + Constraint Details: + + 0.603ns physical path delay SLICE_18 to SLICE_18 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.616ns + + Physical Path Details: + + Data path SLICE_18 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R4C8C.CLK to R4C8C.Q0 SLICE_18 (from PHI2_c) +ROUTE 2 0.212 R4C8C.Q0 to R4C8C.A1 CmdLEDEN +CTOF_DEL --- 0.101 R4C8C.A1 to R4C8C.F1 SLICE_18 +ROUTE 1 0.056 R4C8C.F1 to R4C8C.C0 CmdLEDEN_4_u_i_m2_i_0 +CTOF_DEL --- 0.101 R4C8C.C0 to R4C8C.F0 SLICE_18 +ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 N_17_i (to PHI2_c) + -------- + 0.603 (55.6% logic, 44.4% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 1.240 8.PADDI to R4C8C.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 1.240 8.PADDI to R4C8C.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.616ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Cmdn8MEGEN (from PHI2_c -) + Destination: FF Data in Cmdn8MEGEN (to PHI2_c -) + + Delay: 0.603ns (55.6% logic, 44.4% route), 3 logic levels. + + Constraint Details: + + 0.603ns physical path delay SLICE_24 to SLICE_24 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.616ns + + Physical Path Details: + + Data path SLICE_24 to SLICE_24: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R4C8D.CLK to R4C8D.Q0 SLICE_24 (from PHI2_c) +ROUTE 2 0.212 R4C8D.Q0 to R4C8D.A1 Cmdn8MEGEN +CTOF_DEL --- 0.101 R4C8D.A1 to R4C8D.F1 SLICE_24 +ROUTE 1 0.056 R4C8D.F1 to R4C8D.C0 Cmdn8MEGEN_4_u_i_m2_i_0 +CTOF_DEL --- 0.101 R4C8D.C0 to R4C8D.F0 SLICE_24 +ROUTE 1 0.000 R4C8D.F0 to R4C8D.DI0 N_15_i (to PHI2_c) + -------- + 0.603 (55.6% logic, 44.4% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_24: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 1.240 8.PADDI to R4C8D.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_24: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 1.240 8.PADDI to R4C8D.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.616ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q XOR8MEG (from PHI2_c -) + Destination: FF Data in XOR8MEG (to PHI2_c -) + + Delay: 0.603ns (55.6% logic, 44.4% route), 3 logic levels. + + Constraint Details: + + 0.603ns physical path delay SLICE_44 to SLICE_44 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.616ns + + Physical Path Details: + + Data path SLICE_44 to SLICE_44: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C9C.CLK to R5C9C.Q0 SLICE_44 (from PHI2_c) +ROUTE 2 0.212 R5C9C.Q0 to R5C9C.A1 XOR8MEG +CTOF_DEL --- 0.101 R5C9C.A1 to R5C9C.F1 SLICE_44 +ROUTE 1 0.056 R5C9C.F1 to R5C9C.C0 N_411 +CTOF_DEL --- 0.101 R5C9C.C0 to R5C9C.F0 SLICE_44 +ROUTE 1 0.000 R5C9C.F0 to R5C9C.DI0 XOR8MEG_3 (to PHI2_c) + -------- + 0.603 (55.6% logic, 44.4% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_44: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 1.240 8.PADDI to R5C9C.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_44: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 1.240 8.PADDI to R5C9C.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.628ns - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Cmdn8MEGEN (from PHI2_c -) - Destination: FF Data in Cmdn8MEGEN (to PHI2_c -) - - Delay: 0.615ns (54.5% logic, 45.5% route), 3 logic levels. - - Constraint Details: - - 0.615ns physical path delay SLICE_24 to SLICE_24 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.628ns - - Physical Path Details: - - Data path SLICE_24 to SLICE_24: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R4C9B.CLK to R4C9B.Q0 SLICE_24 (from PHI2_c) -ROUTE 2 0.224 R4C9B.Q0 to R4C9B.B1 Cmdn8MEGEN -CTOF_DEL --- 0.101 R4C9B.B1 to R4C9B.F1 SLICE_24 -ROUTE 1 0.056 R4C9B.F1 to R4C9B.C0 Cmdn8MEGEN_4_u_i_0_0 -CTOF_DEL --- 0.101 R4C9B.C0 to R4C9B.F0 SLICE_24 -ROUTE 1 0.000 R4C9B.F0 to R4C9B.DI0 N_38_i (to PHI2_c) - -------- - 0.615 (54.5% logic, 45.5% route), 3 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_24: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R4C9B.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_24: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R4C9B.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.633ns - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CmdEnable (from PHI2_c -) Destination: FF Data in CmdUFMShift (to PHI2_c -) - Delay: 0.605ns (38.7% logic, 61.3% route), 2 logic levels. + Delay: 0.600ns (39.0% logic, 61.0% route), 2 logic levels. Constraint Details: - 0.605ns physical path delay SLICE_17 to SLICE_20 meets + 0.600ns physical path delay SLICE_17 to SLICE_20 meets -0.028ns CE_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.028ns) by 0.633ns + 0.000ns skew requirement (totaling -0.028ns) by 0.628ns Physical Path Details: Data path SLICE_17 to SLICE_20: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C11C.CLK to R3C11C.Q0 SLICE_17 (from PHI2_c) -ROUTE 2 0.220 R3C11C.Q0 to R3C9D.D1 CmdEnable -CTOF_DEL --- 0.101 R3C9D.D1 to R3C9D.F1 SLICE_23 -ROUTE 8 0.151 R3C9D.F1 to R3C9B.CE XOR8MEG18 (to PHI2_c) +REG_DEL --- 0.133 R5C8C.CLK to R5C8C.Q0 SLICE_17 (from PHI2_c) +ROUTE 2 0.213 R5C8C.Q0 to R4C8A.A1 CmdEnable +CTOF_DEL --- 0.101 R4C8A.A1 to R4C8A.F1 SLICE_23 +ROUTE 8 0.153 R4C8A.F1 to R4C9A.CE XOR8MEG18 (to PHI2_c) -------- - 0.605 (38.7% logic, 61.3% route), 2 logic levels. + 0.600 (39.0% logic, 61.0% route), 2 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_17: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R3C11C.CLK PHI2_c +ROUTE 21 1.240 8.PADDI to R5C8C.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_20: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R3C9B.CLK PHI2_c +ROUTE 21 1.240 8.PADDI to R4C9A.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 0.633ns +Passed: The following path meets requirements by 0.628ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q CmdEnable (from PHI2_c -) + Source: FF Q CmdUFMWrite (from PHI2_c -) Destination: FF Data in CmdUFMWrite (to PHI2_c -) - Delay: 0.605ns (38.7% logic, 61.3% route), 2 logic levels. + Delay: 0.615ns (54.5% logic, 45.5% route), 3 logic levels. Constraint Details: - 0.605ns physical path delay SLICE_17 to SLICE_21 meets - -0.028ns CE_HLD and + 0.615ns physical path delay SLICE_21 to SLICE_21 meets + -0.013ns DIN_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.028ns) by 0.633ns + 0.000ns skew requirement (totaling -0.013ns) by 0.628ns Physical Path Details: - Data path SLICE_17 to SLICE_21: + Data path SLICE_21 to SLICE_21: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C11C.CLK to R3C11C.Q0 SLICE_17 (from PHI2_c) -ROUTE 2 0.220 R3C11C.Q0 to R3C9D.D1 CmdEnable -CTOF_DEL --- 0.101 R3C9D.D1 to R3C9D.F1 SLICE_23 -ROUTE 8 0.151 R3C9D.F1 to R3C9C.CE XOR8MEG18 (to PHI2_c) +REG_DEL --- 0.133 R4C8B.CLK to R4C8B.Q0 SLICE_21 (from PHI2_c) +ROUTE 2 0.224 R4C8B.Q0 to R4C8B.B1 CmdUFMWrite +CTOF_DEL --- 0.101 R4C8B.B1 to R4C8B.F1 SLICE_21 +ROUTE 1 0.056 R4C8B.F1 to R4C8B.C0 N_415 +CTOF_DEL --- 0.101 R4C8B.C0 to R4C8B.F0 SLICE_21 +ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 CmdUFMWrite_3 (to PHI2_c) -------- - 0.605 (38.7% logic, 61.3% route), 2 logic levels. + 0.615 (54.5% logic, 45.5% route), 3 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_17: + Source Clock Path PHI2 to SLICE_21: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R3C11C.CLK PHI2_c +ROUTE 21 1.240 8.PADDI to R4C8B.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_21: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R3C9C.CLK PHI2_c +ROUTE 21 1.240 8.PADDI to R4C8B.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. @@ -1695,7 +1703,7 @@ Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ; ================================================================================ Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; - 878 items scored, 0 timing errors detected. + 891 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- @@ -1720,8 +1728,8 @@ Passed: The following path meets requirements by 0.304ns Data path SLICE_12 to SLICE_12: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R4C11C.CLK to R4C11C.Q0 SLICE_12 (from RCLK_c) -ROUTE 1 0.152 R4C11C.Q0 to R4C11C.M1 CASr (to RCLK_c) +REG_DEL --- 0.133 R6C8B.CLK to R6C8B.Q0 SLICE_12 (from RCLK_c) +ROUTE 1 0.152 R6C8B.Q0 to R6C8B.M1 CASr (to RCLK_c) -------- 0.285 (46.7% logic, 53.3% route), 1 logic levels. @@ -1730,57 +1738,14 @@ ROUTE 1 0.152 R4C11C.Q0 to R4C11C.M1 CASr (to RCLK_c) Source Clock Path RCLK to SLICE_12: Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R4C11C.CLK RCLK_c +ROUTE 48 0.651 63.PADDI to R6C8B.CLK RCLK_c -------- 0.651 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_12: Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R4C11C.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.306ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q PHI2r2 (from RCLK_c +) - Destination: FF Data in PHI2r3 (to RCLK_c +) - - Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. - - Constraint Details: - - 0.287ns physical path delay SLICE_31 to SLICE_31 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.306ns - - Physical Path Details: - - Data path SLICE_31 to SLICE_31: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C10C.CLK to R3C10C.Q0 SLICE_31 (from RCLK_c) -ROUTE 5 0.154 R3C10C.Q0 to R3C10C.M1 PHI2r2 (to RCLK_c) - -------- - 0.287 (46.3% logic, 53.7% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_31: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R3C10C.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_31: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R3C10C.CLK RCLK_c +ROUTE 48 0.651 63.PADDI to R6C8B.CLK RCLK_c -------- 0.651 (0.0% logic, 100.0% route), 0 logic levels. @@ -1806,8 +1771,8 @@ Passed: The following path meets requirements by 0.306ns Data path SLICE_32 to SLICE_32: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C11A.CLK to R5C11A.Q0 SLICE_32 (from RCLK_c) -ROUTE 2 0.154 R5C11A.Q0 to R5C11A.M1 RASr (to RCLK_c) +REG_DEL --- 0.133 R5C13C.CLK to R5C13C.Q0 SLICE_32 (from RCLK_c) +ROUTE 2 0.154 R5C13C.Q0 to R5C13C.M1 RASr (to RCLK_c) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. @@ -1816,18 +1781,319 @@ ROUTE 2 0.154 R5C11A.Q0 to R5C11A.M1 RASr (to RCLK_c) Source Clock Path RCLK to SLICE_32: Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R5C11A.CLK RCLK_c +ROUTE 48 0.651 63.PADDI to R5C13C.CLK RCLK_c -------- 0.651 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_32: Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R5C11A.CLK RCLK_c +ROUTE 48 0.651 63.PADDI to R5C13C.CLK RCLK_c -------- 0.651 (0.0% logic, 100.0% route), 0 logic levels. +Passed: The following path meets requirements by 0.311ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q PHI2r2 (from RCLK_c +) + Destination: FF Data in PHI2r3 (to RCLK_c +) + + Delay: 0.292ns (45.5% logic, 54.5% route), 1 logic levels. + + Constraint Details: + + 0.292ns physical path delay SLICE_31 to SLICE_31 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.311ns + + Physical Path Details: + + Data path SLICE_31 to SLICE_31: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R4C7D.CLK to R4C7D.Q0 SLICE_31 (from RCLK_c) +ROUTE 5 0.159 R4C7D.Q0 to R4C7D.M1 PHI2r2 (to RCLK_c) + -------- + 0.292 (45.5% logic, 54.5% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_31: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 0.651 63.PADDI to R4C7D.CLK RCLK_c + -------- + 0.651 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_31: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 0.651 63.PADDI to R4C7D.CLK RCLK_c + -------- + 0.651 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.318ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q wb_adr[7] (from RCLK_c +) + Destination: EFB Port ufmefb/EFBInst_0(ASIC) (to RCLK_c +) + + Delay: 0.304ns (43.8% logic, 56.3% route), 1 logic levels. + + Constraint Details: + + 0.304ns physical path delay SLICE_50 to ufmefb/EFBInst_0 meets + -0.068ns WBADRI_HLD and + 0.000ns delay constraint less + -0.054ns skew requirement (totaling -0.014ns) by 0.318ns + + Physical Path Details: + + Data path SLICE_50 to ufmefb/EFBInst_0: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R2C2B.CLK to R2C2B.Q1 SLICE_50 (from RCLK_c) +ROUTE 1 0.171 R2C2B.Q1 to EFB.WBADRI7 wb_adr[7] (to RCLK_c) + -------- + 0.304 (43.8% logic, 56.3% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_50: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 0.651 63.PADDI to R2C2B.CLK RCLK_c + -------- + 0.651 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to ufmefb/EFBInst_0: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 0.705 63.PADDI to EFB.WBCLKI RCLK_c + -------- + 0.705 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.333ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q wb_adr[2] (from RCLK_c +) + Destination: EFB Port ufmefb/EFBInst_0(ASIC) (to RCLK_c +) + + Delay: 0.306ns (43.5% logic, 56.5% route), 1 logic levels. + + Constraint Details: + + 0.306ns physical path delay SLICE_48 to ufmefb/EFBInst_0 meets + -0.081ns WBADRI_HLD and + 0.000ns delay constraint less + -0.054ns skew requirement (totaling -0.027ns) by 0.333ns + + Physical Path Details: + + Data path SLICE_48 to ufmefb/EFBInst_0: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R2C2C.CLK to R2C2C.Q0 SLICE_48 (from RCLK_c) +ROUTE 2 0.173 R2C2C.Q0 to EFB.WBADRI2 wb_adr[2] (to RCLK_c) + -------- + 0.306 (43.5% logic, 56.5% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_48: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 0.651 63.PADDI to R2C2C.CLK RCLK_c + -------- + 0.651 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to ufmefb/EFBInst_0: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 0.705 63.PADDI to EFB.WBCLKI RCLK_c + -------- + 0.705 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.347ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q wb_dati[3] (from RCLK_c +) + Destination: EFB Port ufmefb/EFBInst_0(ASIC) (to RCLK_c +) + + Delay: 0.306ns (43.5% logic, 56.5% route), 1 logic levels. + + Constraint Details: + + 0.306ns physical path delay SLICE_53 to ufmefb/EFBInst_0 meets + -0.095ns WBDATI_HLD and + 0.000ns delay constraint less + -0.054ns skew requirement (totaling -0.041ns) by 0.347ns + + Physical Path Details: + + Data path SLICE_53 to ufmefb/EFBInst_0: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R2C3C.CLK to R2C3C.Q1 SLICE_53 (from RCLK_c) +ROUTE 2 0.173 R2C3C.Q1 to EFB.WBDATI3 wb_dati[3] (to RCLK_c) + -------- + 0.306 (43.5% logic, 56.5% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_53: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 0.651 63.PADDI to R2C3C.CLK RCLK_c + -------- + 0.651 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to ufmefb/EFBInst_0: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 0.705 63.PADDI to EFB.WBCLKI RCLK_c + -------- + 0.705 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.350ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q wb_dati[4] (from RCLK_c +) + Destination: EFB Port ufmefb/EFBInst_0(ASIC) (to RCLK_c +) + + Delay: 0.307ns (43.3% logic, 56.7% route), 1 logic levels. + + Constraint Details: + + 0.307ns physical path delay SLICE_54 to ufmefb/EFBInst_0 meets + -0.097ns WBDATI_HLD and + 0.000ns delay constraint less + -0.054ns skew requirement (totaling -0.043ns) by 0.350ns + + Physical Path Details: + + Data path SLICE_54 to ufmefb/EFBInst_0: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R2C3D.CLK to R2C3D.Q0 SLICE_54 (from RCLK_c) +ROUTE 2 0.174 R2C3D.Q0 to EFB.WBDATI4 wb_dati[4] (to RCLK_c) + -------- + 0.307 (43.3% logic, 56.7% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_54: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 0.651 63.PADDI to R2C3D.CLK RCLK_c + -------- + 0.651 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to ufmefb/EFBInst_0: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 0.705 63.PADDI to EFB.WBCLKI RCLK_c + -------- + 0.705 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.355ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RASr2 (from RCLK_c +) + Destination: FF Data in S[1] (to RCLK_c +) + + Delay: 0.298ns (44.6% logic, 55.4% route), 1 logic levels. + + Constraint Details: + + 0.298ns physical path delay SLICE_32 to SLICE_43 meets + -0.057ns LSR_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.057ns) by 0.355ns + + Physical Path Details: + + Data path SLICE_32 to SLICE_43: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C13C.CLK to R5C13C.Q1 SLICE_32 (from RCLK_c) +ROUTE 10 0.165 R5C13C.Q1 to R5C13B.LSR RASr2 (to RCLK_c) + -------- + 0.298 (44.6% logic, 55.4% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_32: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 0.651 63.PADDI to R5C13C.CLK RCLK_c + -------- + 0.651 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_43: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 0.651 63.PADDI to R5C13B.CLK RCLK_c + -------- + 0.651 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.358ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q wb_adr[3] (from RCLK_c +) + Destination: EFB Port ufmefb/EFBInst_0(ASIC) (to RCLK_c +) + + Delay: 0.307ns (43.3% logic, 56.7% route), 1 logic levels. + + Constraint Details: + + 0.307ns physical path delay SLICE_48 to ufmefb/EFBInst_0 meets + -0.105ns WBADRI_HLD and + 0.000ns delay constraint less + -0.054ns skew requirement (totaling -0.051ns) by 0.358ns + + Physical Path Details: + + Data path SLICE_48 to ufmefb/EFBInst_0: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R2C2C.CLK to R2C2C.Q1 SLICE_48 (from RCLK_c) +ROUTE 2 0.174 R2C2C.Q1 to EFB.WBADRI3 wb_adr[3] (to RCLK_c) + -------- + 0.307 (43.3% logic, 56.7% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_48: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 0.651 63.PADDI to R2C2C.CLK RCLK_c + -------- + 0.651 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to ufmefb/EFBInst_0: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 0.705 63.PADDI to EFB.WBCLKI RCLK_c + -------- + 0.705 (0.0% logic, 100.0% route), 0 logic levels. + + Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) @@ -1849,10 +2115,10 @@ Passed: The following path meets requirements by 0.379ns Data path SLICE_0 to SLICE_0: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R2C7A.CLK to R2C7A.Q1 SLICE_0 (from RCLK_c) -ROUTE 3 0.132 R2C7A.Q1 to R2C7A.A1 FS[0] -CTOF_DEL --- 0.101 R2C7A.A1 to R2C7A.F1 SLICE_0 -ROUTE 1 0.000 R2C7A.F1 to R2C7A.DI1 FS_s[0] (to RCLK_c) +REG_DEL --- 0.133 R6C2A.CLK to R6C2A.Q1 SLICE_0 (from RCLK_c) +ROUTE 3 0.132 R6C2A.Q1 to R6C2A.A1 FS[0] +CTOF_DEL --- 0.101 R6C2A.A1 to R6C2A.F1 SLICE_0 +ROUTE 1 0.000 R6C2A.F1 to R6C2A.DI1 FS_s[0] (to RCLK_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. @@ -1861,284 +2127,14 @@ ROUTE 1 0.000 R2C7A.F1 to R2C7A.DI1 FS_s[0] (to RCLK_c) Source Clock Path RCLK to SLICE_0: Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R2C7A.CLK RCLK_c +ROUTE 48 0.651 63.PADDI to R6C2A.CLK RCLK_c -------- 0.651 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_0: Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R2C7A.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.379ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[17] (from RCLK_c +) - Destination: FF Data in FS[17] (to RCLK_c +) - - Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. - - Constraint Details: - - 0.366ns physical path delay SLICE_1 to SLICE_1 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.379ns - - Physical Path Details: - - Data path SLICE_1 to SLICE_1: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R2C9B.CLK to R2C9B.Q0 SLICE_1 (from RCLK_c) -ROUTE 6 0.132 R2C9B.Q0 to R2C9B.A0 FS[17] -CTOF_DEL --- 0.101 R2C9B.A0 to R2C9B.F0 SLICE_1 -ROUTE 1 0.000 R2C9B.F0 to R2C9B.DI0 FS_s[17] (to RCLK_c) - -------- - 0.366 (63.9% logic, 36.1% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_1: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R2C9B.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_1: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R2C9B.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.379ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[16] (from RCLK_c +) - Destination: FF Data in FS[16] (to RCLK_c +) - - Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. - - Constraint Details: - - 0.366ns physical path delay SLICE_2 to SLICE_2 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.379ns - - Physical Path Details: - - Data path SLICE_2 to SLICE_2: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R2C9A.CLK to R2C9A.Q1 SLICE_2 (from RCLK_c) -ROUTE 6 0.132 R2C9A.Q1 to R2C9A.A1 FS[16] -CTOF_DEL --- 0.101 R2C9A.A1 to R2C9A.F1 SLICE_2 -ROUTE 1 0.000 R2C9A.F1 to R2C9A.DI1 FS_s[16] (to RCLK_c) - -------- - 0.366 (63.9% logic, 36.1% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_2: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R2C9A.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_2: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R2C9A.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.379ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q n8MEGEN (from RCLK_c +) - Destination: FF Data in n8MEGEN (to RCLK_c +) - - Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. - - Constraint Details: - - 0.366ns physical path delay SLICE_45 to SLICE_45 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.379ns - - Physical Path Details: - - Data path SLICE_45 to SLICE_45: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R4C8C.CLK to R4C8C.Q0 SLICE_45 (from RCLK_c) -ROUTE 3 0.132 R4C8C.Q0 to R4C8C.A0 n8MEGEN -CTOF_DEL --- 0.101 R4C8C.A0 to R4C8C.F0 SLICE_45 -ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 n8MEGENe_0 (to RCLK_c) - -------- - 0.366 (63.9% logic, 36.1% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_45: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R4C8C.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_45: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R4C8C.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.379ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[10] (from RCLK_c +) - Destination: FF Data in FS[10] (to RCLK_c +) - - Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. - - Constraint Details: - - 0.366ns physical path delay SLICE_5 to SLICE_5 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.379ns - - Physical Path Details: - - Data path SLICE_5 to SLICE_5: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R2C8B.CLK to R2C8B.Q1 SLICE_5 (from RCLK_c) -ROUTE 21 0.132 R2C8B.Q1 to R2C8B.A1 FS[10] -CTOF_DEL --- 0.101 R2C8B.A1 to R2C8B.F1 SLICE_5 -ROUTE 1 0.000 R2C8B.F1 to R2C8B.DI1 FS_s[10] (to RCLK_c) - -------- - 0.366 (63.9% logic, 36.1% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_5: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R2C8B.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_5: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R2C8B.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.379ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q wb_req (from RCLK_c +) - Destination: FF Data in wb_req (to RCLK_c +) - - Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. - - Constraint Details: - - 0.366ns physical path delay SLICE_56 to SLICE_56 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.379ns - - Physical Path Details: - - Data path SLICE_56 to SLICE_56: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R4C7A.CLK to R4C7A.Q0 SLICE_56 (from RCLK_c) -ROUTE 3 0.132 R4C7A.Q0 to R4C7A.A0 wb_req -CTOF_DEL --- 0.101 R4C7A.A0 to R4C7A.F0 SLICE_56 -ROUTE 1 0.000 R4C7A.F0 to R4C7A.DI0 wb_reqe_0 (to RCLK_c) - -------- - 0.366 (63.9% logic, 36.1% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_56: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R4C7A.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_56: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R4C7A.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.379ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q wb_rst (from RCLK_c +) - Destination: FF Data in wb_rst (to RCLK_c +) - - Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. - - Constraint Details: - - 0.366ns physical path delay SLICE_57 to SLICE_57 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.379ns - - Physical Path Details: - - Data path SLICE_57 to SLICE_57: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R4C6B.CLK to R4C6B.Q0 SLICE_57 (from RCLK_c) -ROUTE 2 0.132 R4C6B.Q0 to R4C6B.A0 wb_rst -CTOF_DEL --- 0.101 R4C6B.A0 to R4C6B.F0 SLICE_57 -ROUTE 1 0.000 R4C6B.F0 to R4C6B.DI0 wb_rste_0 (to RCLK_c) - -------- - 0.366 (63.9% logic, 36.1% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_57: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R4C6B.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_57: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R4C6B.CLK RCLK_c +ROUTE 48 0.651 63.PADDI to R6C2A.CLK RCLK_c -------- 0.651 (0.0% logic, 100.0% route), 0 logic levels. @@ -2179,7 +2175,7 @@ Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11 Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10 No transfer within this clock domain is found -Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47 +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 48 Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ; Data transfers from: @@ -2209,7 +2205,7 @@ Timing summary (Hold): Timing errors: 0 Score: 0 Cumulative negative slack: 0 -Constraints cover 1025 paths, 4 nets, and 758 connections (74.53% coverage) +Constraints cover 1038 paths, 4 nets, and 750 connections (74.18% coverage) diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_bgn.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_bgn.html index 87150fd..4eaaad7 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_bgn.html +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_bgn.html @@ -12,10 +12,10 @@ Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Thu Sep 21 05:40:10 2023 +Sat Nov 18 02:06:26 2023 -Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC -w -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf +Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC -w -jedec -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf Loading design for application Bitgen from file RAM2GS_LCMXO2_640HC_impl1.ncd. Design name: RAM2GS @@ -80,10 +80,20 @@ Creating bit map... Bitstream Status: Final Version 1.95. -Saving bit stream in "RAM2GS_LCMXO2_640HC_impl1.bit". +Saving bit stream in "RAM2GS_LCMXO2_640HC_impl1.jed". + +=========== +UFM Summary. +=========== +UFM Size: 191 Pages (128*191 Bits). +UFM Utilization: General Purpose Flash Memory. + +Available General Purpose Flash Memory: 191 Pages (Page 0 to Page 190). +Initialized UFM Pages: 1 Page (Page 190). + Total CPU Time: 4 secs -Total REAL Time: 5 secs -Peak Memory Usage: 266 MB +Total REAL Time: 4 secs +Peak Memory Usage: 267 MB diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_cck.rpt b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_cck.rpt index df40c34..7423f95 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_cck.rpt +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_cck.rpt @@ -13,7 +13,7 @@ Hostname: ZANEMACWIN11 Implementation : impl1 -# Written on Thu Sep 21 05:39:36 2023 +# Written on Sat Nov 18 02:05:43 2023 ##### DESIGN INFO ####################################################### @@ -103,6 +103,7 @@ p:RA[11] p:RBA[0] p:RBA[1] p:RCKE +p:RCLKout p:RDQMH p:RDQML p:RD[0] (bidir end point) diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_iotiming.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_iotiming.html index ec67e92..a5e0e97 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_iotiming.html +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_iotiming.html @@ -38,7 +38,7 @@ Performance Hardware Data Status: Final Version 34.4. // Package: TQFP100 // ncd File: ram2gs_lcmxo2_640hc_impl1.ncd // Version: Diamond (64-bit) 3.12.1.454 -// Written on Thu Sep 21 05:40:03 2023 +// Written on Sat Nov 18 02:06:14 2023 // M: Minimum Performance Grade // iotiming RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml @@ -50,95 +50,96 @@ Worst Case Results across Performance Grades (M, 6, 5, 4): Port Clock Edge Setup Performance_Grade Hold Performance_Grade ---------------------------------------------------------------------- -CROW[0] nCRAS F 2.429 4 -0.163 M -CROW[1] nCRAS F 1.927 4 -0.005 M -Din[0] PHI2 F 5.424 4 3.636 4 -Din[0] nCCAS F 1.913 4 -0.130 M -Din[1] PHI2 F 5.162 4 3.516 4 -Din[1] nCCAS F 2.007 4 -0.156 M -Din[2] PHI2 F 5.078 4 3.516 4 -Din[2] nCCAS F 0.876 4 0.346 4 -Din[3] PHI2 F 6.152 4 3.516 4 -Din[3] nCCAS F 0.245 4 0.869 4 -Din[4] PHI2 F 5.240 4 3.516 4 -Din[4] nCCAS F 0.714 4 0.460 4 -Din[5] PHI2 F 6.035 4 3.516 4 -Din[5] nCCAS F 0.751 4 0.419 4 -Din[6] PHI2 F 4.496 4 3.636 4 -Din[6] nCCAS F 1.518 4 -0.020 M -Din[7] PHI2 F 4.936 4 3.636 4 -Din[7] nCCAS F 1.852 4 -0.081 M -MAin[0] PHI2 F 5.207 4 0.531 4 -MAin[0] nCRAS F 1.658 4 0.036 M -MAin[1] PHI2 F 3.450 4 0.460 4 -MAin[1] nCRAS F 2.014 4 -0.043 M -MAin[2] PHI2 F 7.941 4 -0.604 M -MAin[2] nCRAS F 1.001 4 0.498 4 -MAin[3] PHI2 F 8.770 4 -0.865 M -MAin[3] nCRAS F 2.190 4 -0.151 M -MAin[4] PHI2 F 9.575 4 -1.072 M -MAin[4] nCRAS F 1.331 4 0.186 4 -MAin[5] PHI2 F 9.093 4 -0.925 M -MAin[5] nCRAS F 1.329 4 0.186 4 -MAin[6] PHI2 F 9.450 4 -1.036 M -MAin[6] nCRAS F 1.323 4 0.191 4 -MAin[7] PHI2 F 8.247 4 -0.706 M -MAin[7] nCRAS F 1.258 4 0.267 4 -MAin[8] nCRAS F 0.994 4 0.504 4 -MAin[9] nCRAS F 0.614 4 0.830 4 +CROW[0] nCRAS F 2.058 4 -0.092 M +CROW[1] nCRAS F 2.269 4 -0.117 M +Din[0] PHI2 F 7.415 4 3.636 4 +Din[0] nCCAS F 2.760 4 -0.330 M +Din[1] PHI2 F 6.384 4 3.516 4 +Din[1] nCCAS F 1.112 4 0.128 4 +Din[2] PHI2 F 6.717 4 3.516 4 +Din[2] nCCAS F 0.113 4 0.982 4 +Din[3] PHI2 F 5.806 4 3.516 4 +Din[3] nCCAS F 1.105 4 0.134 4 +Din[4] PHI2 F 6.853 4 3.516 4 +Din[4] nCCAS F 1.538 4 -0.010 M +Din[5] PHI2 F 7.478 4 3.516 4 +Din[5] nCCAS F 0.714 4 0.460 4 +Din[6] PHI2 F 5.667 4 3.636 4 +Din[6] nCCAS F 1.504 4 -0.015 M +Din[7] PHI2 F 5.567 4 3.636 4 +Din[7] nCCAS F 1.063 4 0.194 4 +MAin[0] PHI2 F 4.483 4 0.742 4 +MAin[0] nCRAS F 1.204 4 0.334 4 +MAin[1] PHI2 F 4.440 4 0.520 4 +MAin[1] nCRAS F 1.245 4 0.313 4 +MAin[2] PHI2 F 9.497 4 -0.729 M +MAin[2] nCRAS F 0.758 4 0.714 4 +MAin[3] PHI2 F 9.534 4 -0.752 M +MAin[3] nCRAS F 0.454 4 0.874 4 +MAin[4] PHI2 F 7.882 4 -0.326 M +MAin[4] nCRAS F 0.832 4 0.632 4 +MAin[5] PHI2 F 10.136 4 -0.894 M +MAin[5] nCRAS F 0.830 4 0.632 4 +MAin[6] PHI2 F 8.759 4 -0.555 M +MAin[6] nCRAS F 1.259 4 0.268 4 +MAin[7] PHI2 F 8.430 4 -0.434 M +MAin[7] nCRAS F 0.881 4 0.510 4 +MAin[8] nCRAS F 1.066 4 0.422 4 +MAin[9] nCRAS F 0.723 4 0.746 4 PHI2 RCLK R -0.005 M 2.116 4 -nCCAS RCLK R 3.191 4 -0.531 M -nCCAS nCRAS F 3.195 4 -0.341 M -nCRAS RCLK R 2.797 4 -0.402 M -nFWE PHI2 F 8.238 4 -0.666 M -nFWE nCRAS F 1.140 4 0.400 4 +nCCAS RCLK R 3.614 4 -0.637 M +nCCAS nCRAS F 3.629 4 -0.447 M +nCRAS RCLK R 3.040 4 -0.485 M +nFWE PHI2 F 8.830 4 -0.567 M +nFWE nCRAS F 0.454 4 0.874 4 // Clock to Output Delay -Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade +Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade ------------------------------------------------------------------------ -LED RCLK R 10.962 4 3.218 M -LED nCRAS F 10.815 4 3.159 M -RA[0] RCLK R 10.143 4 3.128 M -RA[0] nCRAS F 11.178 4 3.358 M -RA[10] RCLK R 7.578 4 2.578 M -RA[11] PHI2 R 9.098 4 3.021 M -RA[1] RCLK R 10.676 4 3.248 M -RA[1] nCRAS F 11.215 4 3.370 M -RA[2] RCLK R 11.199 4 3.402 M -RA[2] nCRAS F 11.518 4 3.451 M -RA[3] RCLK R 10.446 4 3.209 M -RA[3] nCRAS F 11.264 4 3.364 M -RA[4] RCLK R 10.446 4 3.209 M -RA[4] nCRAS F 11.484 4 3.438 M -RA[5] RCLK R 11.199 4 3.402 M -RA[5] nCRAS F 11.264 4 3.364 M -RA[6] RCLK R 11.424 4 3.444 M -RA[6] nCRAS F 11.388 4 3.388 M -RA[7] RCLK R 11.112 4 3.370 M -RA[7] nCRAS F 11.608 4 3.487 M -RA[8] RCLK R 10.916 4 3.308 M -RA[8] nCRAS F 11.380 4 3.415 M -RA[9] RCLK R 11.115 4 3.362 M -RA[9] nCRAS F 11.201 4 3.380 M -RBA[0] nCRAS F 8.645 4 2.828 M -RBA[1] nCRAS F 8.645 4 2.828 M -RCKE RCLK R 8.593 4 2.793 M -RDQMH RCLK R 10.909 4 3.327 M -RDQML RCLK R 10.348 4 3.207 M -RD[0] nCCAS F 8.761 4 2.984 M -RD[1] nCCAS F 8.761 4 2.984 M -RD[2] nCCAS F 8.761 4 2.984 M -RD[3] nCCAS F 8.761 4 2.984 M -RD[4] nCCAS F 8.761 4 2.984 M -RD[5] nCCAS F 8.761 4 2.984 M -RD[6] nCCAS F 8.761 4 2.984 M -RD[7] nCCAS F 8.761 4 2.984 M -nRCAS RCLK R 7.578 4 2.578 M -nRCS RCLK R 7.578 4 2.578 M -nRRAS RCLK R 7.578 4 2.578 M -nRWE RCLK R 7.558 4 2.585 M +LED RCLK R 11.284 4 2.893 M +LED nCRAS F 11.111 4 3.244 M +RA[0] RCLK R 10.888 4 3.313 M +RA[0] nCRAS F 11.968 4 3.554 M +RA[10] RCLK R 7.578 4 2.578 M +RA[11] PHI2 R 9.098 4 3.021 M +RA[1] RCLK R 11.272 4 3.408 M +RA[1] nCRAS F 11.484 4 3.438 M +RA[2] RCLK R 11.749 4 3.528 M +RA[2] nCRAS F 11.267 4 3.385 M +RA[3] RCLK R 11.291 4 3.431 M +RA[3] nCRAS F 11.596 4 3.449 M +RA[4] RCLK R 10.696 4 3.276 M +RA[4] nCRAS F 11.720 4 3.503 M +RA[5] RCLK R 11.228 4 3.401 M +RA[5] nCRAS F 11.364 4 3.427 M +RA[6] RCLK R 10.132 4 3.112 M +RA[6] nCRAS F 10.958 4 3.284 M +RA[7] RCLK R 11.404 4 3.446 M +RA[7] nCRAS F 11.918 4 3.561 M +RA[8] RCLK R 10.488 4 3.236 M +RA[8] nCRAS F 11.512 4 3.463 M +RA[9] RCLK R 10.941 4 3.329 M +RA[9] nCRAS F 11.074 4 3.356 M +RBA[0] nCRAS F 8.645 4 2.828 M +RBA[1] nCRAS F 8.625 4 2.835 M +RCKE RCLK R 9.454 4 3.006 M +RCLKout RCLK R 6.857 4 1.980 M +RDQMH RCLK R 9.846 4 3.033 M +RDQML RCLK R 9.741 4 3.008 M +RD[0] nCCAS F 8.761 4 2.984 M +RD[1] nCCAS F 8.761 4 2.984 M +RD[2] nCCAS F 8.761 4 2.984 M +RD[3] nCCAS F 8.761 4 2.984 M +RD[4] nCCAS F 8.761 4 2.984 M +RD[5] nCCAS F 8.761 4 2.984 M +RD[6] nCCAS F 8.761 4 2.984 M +RD[7] nCCAS F 8.761 4 2.984 M +nRCAS RCLK R 7.578 4 2.578 M +nRCS RCLK R 7.578 4 2.578 M +nRRAS RCLK R 7.578 4 2.578 M +nRWE RCLK R 7.558 4 2.585 M WARNING: you must also run trce with hold speed: 4 WARNING: you must also run trce with setup speed: M diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvo.sdf b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvo.sdf index c1ced42..c7d445b 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvo.sdf +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvo.sdf @@ -1,7 +1,7 @@ (DELAYFILE (SDFVERSION "3.0") (DESIGN "RAM2GS") - (DATE "Thu Sep 21 05:39:46 2023") + (DATE "Sat Nov 18 02:05:56 2023") (VENDOR "Lattice") (PROGRAM "ldbanno") (VERSION "Diamond (64-bit) 3.12.1.454") @@ -324,6 +324,8 @@ (INSTANCE SLICE_16) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) @@ -390,6 +392,24 @@ (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) ) ) + (CELL + (CELLTYPE "SLICE_19") + (INSTANCE SLICE_19) + (DELAY + (ABSOLUTE + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) (CELL (CELLTYPE "SLICE_20") (INSTANCE SLICE_20) @@ -526,8 +546,11 @@ (INSTANCE SLICE_26) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) @@ -570,6 +593,9 @@ (INSTANCE SLICE_28) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) @@ -1048,11 +1074,9 @@ (INSTANCE SLICE_49) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -1077,7 +1101,6 @@ (ABSOLUTE (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -1264,7 +1287,6 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -1284,7 +1306,6 @@ (INSTANCE SLICE_58) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) @@ -1308,8 +1329,8 @@ ) ) (CELL - (CELLTYPE "wb_dati_5_1_iv_0_o3_5__SLICE_59") - (INSTANCE wb_dati_5_1_iv_0_o3\[5\]\/SLICE_59) + (CELLTYPE "wb_dati_5_1_iv_0_0_o2_5__SLICE_59") + (INSTANCE wb_dati_5_1_iv_0_0_o2\[5\]\/SLICE_59) (DELAY (ABSOLUTE (IOPATH D1 OFX0 (457:589:721)(457:589:721)) @@ -1325,18 +1346,18 @@ ) ) (CELL - (CELLTYPE "SLICE_60") - (INSTANCE SLICE_60) + (CELLTYPE "wb_adr_5_i_0_1_0__SLICE_60") + (INSTANCE wb_adr_5_i_0_1\[0\]\/SLICE_60) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH C1 OFX0 (457:589:721)(457:589:721)) + (IOPATH B1 OFX0 (457:589:721)(457:589:721)) + (IOPATH A1 OFX0 (457:589:721)(457:589:721)) + (IOPATH D0 OFX0 (457:589:721)(457:589:721)) + (IOPATH C0 OFX0 (457:589:721)(457:589:721)) + (IOPATH B0 OFX0 (457:589:721)(457:589:721)) + (IOPATH A0 OFX0 (457:589:721)(457:589:721)) + (IOPATH M0 OFX0 (322:349:376)(322:349:376)) ) ) ) @@ -1349,6 +1370,7 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -1364,6 +1386,7 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -1411,7 +1434,6 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -1423,11 +1445,9 @@ (INSTANCE SLICE_66) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -1454,6 +1474,7 @@ (INSTANCE SLICE_68) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) @@ -1472,7 +1493,6 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -1488,6 +1508,7 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -1499,10 +1520,9 @@ (INSTANCE SLICE_71) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -1514,10 +1534,10 @@ (INSTANCE SLICE_72) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -1529,7 +1549,6 @@ (INSTANCE SLICE_73) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) @@ -1545,6 +1564,7 @@ (INSTANCE SLICE_74) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) @@ -1560,6 +1580,8 @@ (INSTANCE SLICE_75) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) @@ -1574,7 +1596,6 @@ (INSTANCE SLICE_76) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) @@ -1582,8 +1603,18 @@ (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) ) ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + ) ) (CELL (CELLTYPE "SLICE_77") @@ -1594,20 +1625,24 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) ) ) + (TIMINGCHECK + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) ) (CELL (CELLTYPE "SLICE_78") (INSTANCE SLICE_78) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) @@ -1636,6 +1671,7 @@ (INSTANCE SLICE_80) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) @@ -1643,24 +1679,15 @@ (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) ) ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) - (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) - ) ) (CELL (CELLTYPE "SLICE_81") (INSTANCE SLICE_81) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) @@ -1680,25 +1707,19 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) ) ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) - (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) - ) ) (CELL (CELLTYPE "SLICE_83") (INSTANCE SLICE_83) (DELAY (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) @@ -1713,7 +1734,6 @@ (INSTANCE SLICE_84) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) @@ -1749,7 +1769,6 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -1761,7 +1780,6 @@ (INSTANCE SLICE_87) (DELAY (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) @@ -1776,8 +1794,6 @@ (INSTANCE SLICE_88) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) @@ -1792,6 +1808,7 @@ (INSTANCE SLICE_89) (DELAY (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) @@ -1822,7 +1839,6 @@ (INSTANCE SLICE_91) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) @@ -1838,7 +1854,6 @@ (INSTANCE SLICE_92) (DELAY (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) @@ -1869,8 +1884,6 @@ (INSTANCE SLICE_94) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) @@ -1941,6 +1954,8 @@ (INSTANCE SLICE_99) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) @@ -1969,9 +1984,10 @@ (INSTANCE SLICE_101) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -1983,6 +1999,8 @@ (INSTANCE SLICE_102) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) @@ -1997,6 +2015,8 @@ (INSTANCE SLICE_103) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) @@ -2011,10 +2031,10 @@ (INSTANCE SLICE_104) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -2026,10 +2046,9 @@ (INSTANCE SLICE_105) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -2041,10 +2060,10 @@ (INSTANCE SLICE_106) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -2056,35 +2075,22 @@ (INSTANCE SLICE_107) (DELAY (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) ) ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) ) (CELL (CELLTYPE "SLICE_108") (INSTANCE SLICE_108) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) ) @@ -2099,7 +2105,6 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) ) @@ -2110,11 +2115,8 @@ (INSTANCE SLICE_110) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -2126,8 +2128,11 @@ (INSTANCE SLICE_111) (DELAY (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) ) @@ -2138,10 +2143,10 @@ (INSTANCE SLICE_112) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) ) @@ -2152,8 +2157,10 @@ (INSTANCE SLICE_113) (DELAY (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) ) @@ -2206,10 +2213,8 @@ (INSTANCE SLICE_117) (DELAY (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) ) @@ -2220,10 +2225,8 @@ (INSTANCE SLICE_118) (DELAY (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) ) @@ -2283,19 +2286,6 @@ ) ) ) - (CELL - (CELLTYPE "SLICE_123") - (INSTANCE SLICE_123) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) (CELL (CELLTYPE "RD_0_") (INSTANCE RD\[0\]_I) @@ -2468,6 +2458,32 @@ ) ) ) + (CELL + (CELLTYPE "RCLKout") + (INSTANCE RCLKout_I) + (DELAY + (ABSOLUTE + (IOPATH IOLDO RCLKout (1847:1987:2127)(1847:1987:2127)) + ) + ) + ) + (CELL + (CELLTYPE "RCLKout_MGIOL") + (INSTANCE RCLKout_MGIOL) + (DELAY + (ABSOLUTE + (IOPATH CLK IOLDO (1172:1208:1244)(1172:1208:1244)) + ) + ) + (TIMINGCHECK + (SETUPHOLD ONEG (posedge CLK) (72:72:72)(-52:-52:-52)) + (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (4807:4807:4807)) + (WIDTH (negedge CLK) (4807:4807:4807)) + ) + ) (CELL (CELLTYPE "RCLK") (INSTANCE RCLK_I) @@ -3463,7 +3479,7 @@ (DELAY (ABSOLUTE (INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_0/Q1 SLICE_92/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_89/A1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_0/Q1 SLICE_121/A1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_0/F1 SLICE_0/DI1 (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_0/CLK (0:0:0)(0:0:0)) @@ -3505,218 +3521,209 @@ (INTERCONNECT RCLK_I/PADDI SLICE_56/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_57/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_58/CLK (0:0:0)(0:0:0)) - (INTERCONNECT RCLK_I/PADDI SLICE_107/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_77/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI PHI2_MGIOL/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI nRCAS_MGIOL/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI nRRAS_MGIOL/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI nRWE_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI RCLKout_MGIOL/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI nRCS_MGIOL/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI RA\[10\]_MGIOL/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBCLKIin (0:0:0)(0:0:0)) (INTERCONNECT SLICE_0/FCO SLICE_9/FCI (0:0:0)(0:0:0)) (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q0 SLICE_56/C1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q0 SLICE_57/C1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q0 SLICE_66/C1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q0 SLICE_97/B1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q0 SLICE_123/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_29/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_58/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_64/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_91/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_94/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_99/D0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_1/F0 SLICE_1/DI0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_2/FCO SLICE_1/FCI (0:0:0)(0:0:0)) (INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q1 SLICE_56/D1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q1 SLICE_57/D1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q1 SLICE_66/D1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q1 SLICE_97/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q1 SLICE_123/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_29/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_58/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_64/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_91/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_94/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_99/C0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q0 SLICE_49/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q0 SLICE_49/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q0 SLICE_50/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q0 SLICE_57/B1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q0 SLICE_58/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q0 SLICE_66/B1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q0 SLICE_97/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q0 SLICE_123/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_29/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_64/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_91/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_94/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_99/B0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_2/F1 SLICE_2/DI1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_2/F0 SLICE_2/DI0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_3/FCO SLICE_2/FCI (0:0:0)(0:0:0)) (INTERCONNECT SLICE_3/Q1 SLICE_3/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q1 SLICE_62/C0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q1 SLICE_69/B1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q1 SLICE_70/C0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q1 SLICE_75/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q1 SLICE_76/D1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q1 SLICE_77/C1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q1 SLICE_87/C1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q1 SLICE_96/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q1 SLICE_101/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_56/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_61/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_61/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_67/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_73/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_74/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_84/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_85/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_88/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_94/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_98/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_99/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_102/C1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_3/Q1 SLICE_102/C0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q1 SLICE_104/C1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q1 SLICE_104/C0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q1 SLICE_105/B1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_3/Q1 SLICE_105/C0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q1 SLICE_106/C1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q1 SLICE_110/D0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q1 SLICE_113/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_107/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_107/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_118/B1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_3/Q0 SLICE_3/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q0 wb_dati_5_1_iv_0_o3\[5\]\/SLICE_59/D0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q0 SLICE_63/B0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q0 SLICE_67/C0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q0 SLICE_69/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q0 SLICE_70/B1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q0 SLICE_76/C1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q0 SLICE_77/B1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q0 SLICE_87/C0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q0 SLICE_89/B0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q0 SLICE_91/B1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q0 SLICE_95/B1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q0 SLICE_96/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_56/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 wb_dati_5_1_iv_0_0_o2\[5\]\/SLICE_59/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 wb_adr_5_i_0_1\[0\]\/SLICE_60/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_61/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_65/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_72/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_74/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_84/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_85/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_87/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_93/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_97/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_98/B1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_3/Q0 SLICE_102/B1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q0 SLICE_104/B1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q0 SLICE_104/B0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q0 SLICE_105/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q0 SLICE_105/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q0 SLICE_106/B1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q0 SLICE_106/B0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q0 SLICE_109/D1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q0 SLICE_110/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_102/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_104/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_104/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_105/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_105/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_107/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_118/B0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_3/F1 SLICE_3/DI1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_3/F0 SLICE_3/DI0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_4/FCO SLICE_3/FCI (0:0:0)(0:0:0)) (INTERCONNECT SLICE_4/Q1 SLICE_4/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/Q1 wb_dati_5_1_iv_0_o3\[5\]\/SLICE_59/D1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/Q1 SLICE_63/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/Q1 SLICE_63/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/Q1 SLICE_69/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/Q1 SLICE_70/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/Q1 SLICE_73/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/Q1 SLICE_75/D0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/Q1 SLICE_76/B0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/Q1 SLICE_77/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/Q1 SLICE_87/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/Q1 SLICE_95/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/Q1 SLICE_96/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/Q1 SLICE_101/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/Q1 SLICE_102/B0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/Q1 SLICE_104/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/Q1 SLICE_104/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/Q1 SLICE_106/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/Q1 SLICE_106/C0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/Q1 SLICE_110/B1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/Q1 SLICE_110/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q1 SLICE_56/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q1 wb_dati_5_1_iv_0_0_o2\[5\]\/SLICE_59/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q1 SLICE_67/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q1 SLICE_71/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q1 SLICE_72/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q1 SLICE_73/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q1 SLICE_74/A1 (0:0:0)(0:0:0)) + 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(0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_63/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_76/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_114/A0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_11/F1 SLICE_10/D0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_11/F1 SLICE_11/A0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_11/F1 SLICE_33/B0 (0:0:0)(0:0:0)) @@ -3730,13 +3737,13 @@ (INTERCONNECT PHI2_I/PADDI SLICE_11/CLK (0:0:0)(0:0:0)) (INTERCONNECT PHI2_I/PADDI SLICE_17/CLK (0:0:0)(0:0:0)) (INTERCONNECT PHI2_I/PADDI SLICE_18/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_19/CLK (0:0:0)(0:0:0)) (INTERCONNECT PHI2_I/PADDI SLICE_20/CLK (0:0:0)(0:0:0)) (INTERCONNECT PHI2_I/PADDI SLICE_21/CLK (0:0:0)(0:0:0)) (INTERCONNECT PHI2_I/PADDI SLICE_22/CLK (0:0:0)(0:0:0)) (INTERCONNECT PHI2_I/PADDI SLICE_23/CLK (0:0:0)(0:0:0)) (INTERCONNECT PHI2_I/PADDI SLICE_24/CLK (0:0:0)(0:0:0)) (INTERCONNECT PHI2_I/PADDI SLICE_44/CLK (0:0:0)(0:0:0)) - (INTERCONNECT PHI2_I/PADDI SLICE_82/CLK (0:0:0)(0:0:0)) (INTERCONNECT PHI2_I/PADDI PHI2_MGIOL/DI (0:0:0)(0:0:0)) (INTERCONNECT PHI2_I/PADDI RA\[11\]_MGIOL/CLK (0:0:0)(0:0:0)) (INTERCONNECT PHI2_I/PADDI Din\[7\]_MGIOL/CLK (0:0:0)(0:0:0)) @@ -3747,14 +3754,14 @@ (INTERCONNECT PHI2_I/PADDI Din\[2\]_MGIOL/CLK (0:0:0)(0:0:0)) (INTERCONNECT PHI2_I/PADDI Din\[1\]_MGIOL/CLK (0:0:0)(0:0:0)) (INTERCONNECT PHI2_I/PADDI Din\[0\]_MGIOL/CLK (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_112/F1 SLICE_11/B1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_112/F1 SLICE_17/B1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_112/F1 SLICE_64/C0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_112/F1 SLICE_80/B1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_64/F1 SLICE_11/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_64/F1 SLICE_64/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_109/F1 SLICE_11/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_109/F1 SLICE_17/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_109/F1 SLICE_63/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_109/F1 SLICE_76/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63/F1 SLICE_11/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63/F1 SLICE_63/D0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_11/Q0 SLICE_11/B0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_11/Q0 SLICE_80/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_11/Q0 SLICE_76/A0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_11/F0 SLICE_11/DI0 (0:0:0)(0:0:0)) (INTERCONNECT nCCAS_I/PADDI SLICE_12/A0 (0:0:0)(0:0:0)) (INTERCONNECT nCCAS_I/PADDI SLICE_25/A1 (0:0:0)(0:0:0)) @@ -3767,59 +3774,58 @@ (INTERCONNECT nCCAS_I/PADDI RD\[2\]_MGIOL/CLK (0:0:0)(0:0:0)) (INTERCONNECT nCCAS_I/PADDI RD\[1\]_MGIOL/CLK (0:0:0)(0:0:0)) (INTERCONNECT SLICE_12/F0 SLICE_12/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_12/F0 SLICE_80/M0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_12/F0 SLICE_80/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_12/F0 SLICE_76/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_12/F0 SLICE_76/M1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_12/Q0 SLICE_12/M1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_12/Q1 SLICE_26/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_12/Q1 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SLICE_43/Q0 SLICE_79/B0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_43/Q0 SLICE_81/C1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_43/Q0 SLICE_88/C1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_43/Q0 SLICE_108/D1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_16/Q0 SLICE_16/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_16/Q0 SLICE_16/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_16/Q0 SLICE_26/B1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_16/Q0 SLICE_43/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_16/Q0 SLICE_43/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_16/Q0 SLICE_60/B1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_16/Q0 SLICE_60/D0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_16/Q0 SLICE_61/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_16/Q0 SLICE_61/B0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_16/Q0 SLICE_72/C0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_16/Q0 SLICE_79/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_16/Q0 SLICE_83/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_16/Q0 SLICE_88/D1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_16/Q0 SLICE_108/B1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_16/Q0 SLICE_108/C0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_16/F0 SLICE_16/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_43/Q0 SLICE_62/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_43/Q0 SLICE_62/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_43/Q0 SLICE_68/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_43/Q0 SLICE_101/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_43/Q0 SLICE_103/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_43/Q0 SLICE_106/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_43/Q0 SLICE_117/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32/Q1 SLICE_16/C1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_32/Q1 SLICE_16/LSR (0:0:0)(0:0:0)) (INTERCONNECT SLICE_32/Q1 SLICE_33/M0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_32/Q1 SLICE_34/B1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_32/Q1 SLICE_35/A1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_32/Q1 SLICE_35/B0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_32/Q1 SLICE_43/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32/Q1 SLICE_43/B1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_32/Q1 SLICE_43/LSR (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_32/Q1 SLICE_72/B1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_32/Q1 SLICE_74/C0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_32/Q1 SLICE_78/C0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_32/Q1 SLICE_79/B1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_32/Q1 SLICE_90/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_16/F1 SLICE_46/C0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_99/F0 SLICE_17/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_99/F0 SLICE_80/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32/Q1 SLICE_62/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32/Q1 SLICE_68/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_28/Q0 SLICE_16/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_28/Q0 SLICE_28/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_28/Q0 SLICE_79/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_28/Q0 SLICE_83/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/Q0 SLICE_16/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/Q0 SLICE_16/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/Q0 SLICE_43/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/Q0 SLICE_62/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/Q0 SLICE_68/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/Q0 SLICE_69/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/Q0 SLICE_75/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/Q0 SLICE_78/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/Q0 SLICE_103/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/Q0 SLICE_103/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/Q0 SLICE_117/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/Q0 SLICE_117/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/F0 SLICE_16/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/F1 SLICE_36/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/F1 SLICE_37/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F0 SLICE_17/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F0 SLICE_76/C1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_33/F0 SLICE_17/D0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_80/F0 SLICE_17/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/F0 SLICE_17/C0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_17/Q0 SLICE_17/A0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_17/Q0 SLICE_23/A1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_17/F0 SLICE_17/DI0 (0:0:0)(0:0:0)) @@ -3833,22 +3839,22 @@ (INTERCONNECT Din\[1\]_I/PADDI SLICE_20/B0 (0:0:0)(0:0:0)) (INTERCONNECT Din\[1\]_I/PADDI SLICE_21/B0 (0:0:0)(0:0:0)) (INTERCONNECT Din\[1\]_I/PADDI SLICE_44/A0 (0:0:0)(0:0:0)) - (INTERCONNECT Din\[1\]_I/PADDI SLICE_112/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_109/B1 (0:0:0)(0:0:0)) (INTERCONNECT Din\[1\]_I/PADDI RD\[1\]_MGIOL/OPOS (0:0:0)(0:0:0)) (INTERCONNECT Din\[1\]_I/PADDI Din\[1\]_MGIOL/DI (0:0:0)(0:0:0)) (INTERCONNECT SLICE_119/F1 SLICE_18/B1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_119/F1 SLICE_24/A1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_18/Q0 SLICE_18/A1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_18/Q0 SLICE_30/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_82/F1 SLICE_18/C0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_82/F1 SLICE_20/D0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_82/F1 SLICE_21/D0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_82/F1 SLICE_24/B0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_82/F1 SLICE_82/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/F1 SLICE_18/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/F1 SLICE_20/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/F1 SLICE_21/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/F1 SLICE_24/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/F1 SLICE_77/A0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_30/Q0 SLICE_18/B0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_30/Q0 SLICE_30/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_30/Q0 SLICE_32/B1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_30/Q0 SLICE_44/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q0 SLICE_106/B0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_18/F1 SLICE_18/A0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_18/F0 SLICE_18/DI0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_23/F1 SLICE_18/CE (0:0:0)(0:0:0)) @@ -3858,87 +3864,100 @@ (INTERCONNECT SLICE_23/F1 SLICE_23/A0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_23/F1 SLICE_24/CE (0:0:0)(0:0:0)) (INTERCONNECT SLICE_23/F1 SLICE_44/CE (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_23/F1 SLICE_82/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23/F1 SLICE_77/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_19/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_26/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_26/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_27/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_27/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_28/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_28/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_36/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_83/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_19/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_21/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_24/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_109/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_109/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI RD\[0\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI Din\[0\]_MGIOL/DI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/F0 SLICE_19/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19/F0 RA\[10\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19/Q0 SLICE_58/A0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_20/Q0 SLICE_20/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_20/Q0 SLICE_103/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_20/Q0 SLICE_100/A0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_20/F0 SLICE_20/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_20/F1 RCLKout_MGIOL/OPOS (0:0:0)(0:0:0)) (INTERCONNECT SLICE_21/Q0 SLICE_21/A1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_21/Q0 SLICE_51/A0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_21/F1 SLICE_21/C0 (0:0:0)(0:0:0)) - (INTERCONNECT Din\[0\]_I/PADDI SLICE_21/A0 (0:0:0)(0:0:0)) - (INTERCONNECT Din\[0\]_I/PADDI SLICE_24/C1 (0:0:0)(0:0:0)) - (INTERCONNECT Din\[0\]_I/PADDI SLICE_82/M0 (0:0:0)(0:0:0)) - (INTERCONNECT Din\[0\]_I/PADDI SLICE_112/D1 (0:0:0)(0:0:0)) - (INTERCONNECT Din\[0\]_I/PADDI SLICE_112/A0 (0:0:0)(0:0:0)) - (INTERCONNECT Din\[0\]_I/PADDI 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(0:0:0)(0:0:0)) - (INTERCONNECT SLICE_85/F1 SLICE_86/B0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_89/F0 SLICE_85/B0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_88/F0 RA\[10\]_MGIOL/LSR (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_90/F1 SLICE_90/D0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_92/F1 SLICE_92/D0 (0:0:0)(0:0:0)) - (INTERCONNECT ufmefb\/EFBInst_0/WBACKO SLICE_92/C0 (0:0:0)(0:0:0)) - (INTERCONNECT ufmefb\/EFBInst_0/WBACKO SLICE_104/D0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_93/F1 SLICE_93/D0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_114/F0 SLICE_93/C0 (0:0:0)(0:0:0)) - (INTERCONNECT Din\[2\]_MGIOL/IN SLICE_93/B0 (0:0:0)(0:0:0)) - (INTERCONNECT Din\[0\]_MGIOL/IN SLICE_93/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_94/F0 SLICE_94/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_94/F1 nRCAS_MGIOL/OPOS (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_96/F1 SLICE_96/D0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_109/F0 SLICE_96/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/F0 SLICE_80/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_MGIOL/IN SLICE_80/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_MGIOL/IN SLICE_80/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_118/F1 SLICE_81/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_118/F1 SLICE_97/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/F1 SLICE_81/B1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_98/F1 SLICE_98/D0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_99/F1 SLICE_99/D0 (0:0:0)(0:0:0)) - (INTERCONNECT Din\[2\]_I/PADDI SLICE_99/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/F0 SLICE_81/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/F1 SLICE_81/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/F1 SLICE_111/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102/F1 SLICE_82/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/F1 SLICE_82/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/F1 SLICE_86/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/F0 SLICE_87/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/F1 SLICE_89/D0 (0:0:0)(0:0:0)) + (INTERCONNECT ufmefb\/EFBInst_0/WBACKO SLICE_89/C0 (0:0:0)(0:0:0)) + (INTERCONNECT ufmefb\/EFBInst_0/WBACKO SLICE_102/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/F1 SLICE_90/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_112/F0 SLICE_90/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_MGIOL/IN SLICE_90/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_MGIOL/IN SLICE_90/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F1 SLICE_92/D0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_92/A0 (0:0:0)(0:0:0)) (INTERCONNECT Din\[2\]_I/PADDI SLICE_119/A0 (0:0:0)(0:0:0)) (INTERCONNECT Din\[2\]_I/PADDI RD\[2\]_MGIOL/OPOS (0:0:0)(0:0:0)) (INTERCONNECT Din\[2\]_I/PADDI Din\[2\]_MGIOL/DI (0:0:0)(0:0:0)) - (INTERCONNECT Din\[7\]_I/PADDI SLICE_100/B1 (0:0:0)(0:0:0)) - (INTERCONNECT Din\[7\]_I/PADDI SLICE_112/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93/F0 SLICE_93/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95/F1 SLICE_95/D0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_96/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_109/A1 (0:0:0)(0:0:0)) (INTERCONNECT Din\[7\]_I/PADDI SLICE_119/C1 (0:0:0)(0:0:0)) (INTERCONNECT Din\[7\]_I/PADDI RD\[7\]_MGIOL/OPOS (0:0:0)(0:0:0)) (INTERCONNECT Din\[7\]_I/PADDI Din\[7\]_MGIOL/DI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_112/F0 SLICE_100/C0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_103/F1 SLICE_103/C0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_111/F0 RDQMH_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_111/F1 RDQML_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_114/F1 RA\[6\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_115/F0 RA\[8\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_109/F0 SLICE_96/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99/F0 SLICE_99/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F1 SLICE_100/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/F0 SLICE_101/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/F1 nRCAS_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_106/F0 LED_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_108/F0 RDQMH_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_108/F1 RDQML_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT ufmefb\/EFBInst_0/WBDATO0 SLICE_111/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_112/F1 RA\[2\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_113/F0 RA\[0\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_113/F1 RA\[8\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_114/F0 RA\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_114/F1 RA\[3\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_115/F0 RA\[4\]_I/PADDO (0:0:0)(0:0:0)) (INTERCONNECT SLICE_115/F1 RA\[9\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_116/F0 RA\[0\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_116/F0 RA\[5\]_I/PADDO (0:0:0)(0:0:0)) (INTERCONNECT SLICE_116/F1 RA\[7\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_117/F0 RA\[1\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_117/F1 RA\[5\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_118/F0 RA\[2\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_118/F1 RA\[4\]_I/PADDO (0:0:0)(0:0:0)) (INTERCONNECT CROW\[1\]_I/PADDI SLICE_120/A1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_120/F0 RA\[11\]_MGIOL/OPOS (0:0:0)(0:0:0)) (INTERCONNECT SLICE_120/F1 RBA\[1\]_MGIOL/OPOS (0:0:0)(0:0:0)) - (INTERCONNECT ufmefb\/EFBInst_0/WBDATO0 SLICE_122/C1 (0:0:0)(0:0:0)) (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_I/PADDO (0:0:0)(0:0:0)) (INTERCONNECT RD\[0\]_MGIOL/IOLDO RD\[0\]_I/IOLDO (0:0:0)(0:0:0)) (INTERCONNECT nRCAS_MGIOL/IOLDO nRCAS_I/IOLDO (0:0:0)(0:0:0)) (INTERCONNECT nRRAS_MGIOL/IOLDO nRRAS_I/IOLDO (0:0:0)(0:0:0)) (INTERCONNECT nRWE_MGIOL/IOLDO nRWE_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RCLKout_MGIOL/IOLDO RCLKout_I/IOLDO (0:0:0)(0:0:0)) (INTERCONNECT nRCS_MGIOL/IOLDO nRCS_I/IOLDO (0:0:0)(0:0:0)) (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_I/PADDO (0:0:0)(0:0:0)) (INTERCONNECT RD\[7\]_MGIOL/IOLDO RD\[7\]_I/IOLDO (0:0:0)(0:0:0)) diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvo.vo b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvo.vo index 8200fb7..be4a7a8 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvo.vo +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvo.vo @@ -2,8 +2,8 @@ // Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454 // ldbanno -n Verilog -o RAM2GS_LCMXO2_640HC_impl1_mapvo.vo -w -neg -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd -// Netlist created on Thu Sep 21 05:39:43 2023 -// Netlist written on Thu Sep 21 05:39:46 2023 +// Netlist created on Sat Nov 18 02:05:52 2023 +// Netlist written on Sat Nov 18 02:05:56 2023 // Design is for device LCMXO2-640HC // Design is for package TQFP100 // Design is for performance grade 4 @@ -11,7 +11,8 @@ `timescale 1 ns / 1 ps module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, - RD, nRCS, RCLK, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML ); + RD, nRCS, RCLK, RCLKout, RCKE, nRWE, nRRAS, nRCAS, RDQMH, + RDQML ); input PHI2; input [9:0] MAin; input [1:0] CROW; @@ -21,7 +22,7 @@ module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, output LED; output [1:0] RBA; output [11:0] RA; - output nRCS, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML; + output nRCS, RCLKout, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML; inout [7:0] RD; wire \FS[0] , \FS_s[0] , RCLK_c, \FS_cry[0] , \FS[17] , \FS_s[17] , \FS_cry[16] , \FS[16] , \FS[15] , \FS_s[16] , \FS_s[15] , @@ -30,73 +31,85 @@ module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, \FS_cry[10] , \FS[10] , \FS[9] , \FS_s[10] , \FS_s[9] , \FS_cry[8] , \FS[8] , \FS[7] , \FS_s[8] , \FS_s[7] , \FS_cry[6] , \FS[6] , \FS[5] , \FS_s[6] , \FS_s[5] , \FS_cry[4] , \FS[4] , \FS[3] , \FS_s[4] , - \FS_s[3] , \FS_cry[2] , \FS[2] , \FS[1] , \FS_s[2] , \FS_s[1] , - un1_CmdEnable20_0_0_o3, \MAin_c[1] , CmdEnable16, CmdEnable17, N_524, - ADSubmitted, ADSubmitted_r_0_0, PHI2_c, N_518, N_594, C1Submitted, - C1Submitted_RNO, nCCAS_c, nCCAS_c_i, CASr, CASr2, \S[1] , CO0, - N_123_i, RASr2, N_345_i, N_593, CmdEnable_0_sqmuxa, un1_CmdEnable20_i, - CmdEnable, CmdEnable_s, CmdValid_2_i_o2_1_o3, \Din_c[1] , - CmdLEDEN_4_u_i_0_a3_0_0, CmdLEDEN, N_531, LEDEN, CmdLEDEN_4_u_i_0_0, - N_40_i, XOR8MEG18, CmdUFMShift, CmdUFMShift_3, CmdUFMWrite, N_462, - \Din_c[0] , CmdUFMWrite_3, N_213, \Din_c[5] , \Din_c[4] , \Din_c[3] , - CmdValid_r, CmdValid, \MAin_c[0] , N_36_fast, CmdValid_fast, - Cmdn8MEGEN, n8MEGEN, Cmdn8MEGEN_4_u_i_0_0, N_38_i, nFWE_c, nFWE_c_i, - nCRAS_c, FWEr, RD_1_i, nRCS_9_u_i_0_o2_1_RNIL2K71, \IS[0] , N_351_i_i, - N_267, \IS[2] , \IS[1] , N_348_i_i, N_344_i, N_360_i, \IS[3] , - N_350_i_i, \IS_i[0] , N_581, InitReady3_0_a3_1, InitReady, InitReady3, - N_757_0, \wb_dato[1] , LEDEN_6_i_m2_i_m2, CmdValid_RNIOOBE2, LEDENe_0, - Ready_fast, \CROW_c[0] , PHI2r2, PHI2r, \RBAd_0[0] , PHI2r3, CBR, - nCRAS_c_i_0, RASr, LED_c, nRowColSel, \RowA[3] , \MAin_c[3] , RASr3, - \RA_c[3] , N_216, Ready, RCKEEN_8_u_0_1_0, RCKEEN_8_u_0_0_0, RCKEEN_8, - RCKEEN, RCKE_2, RCKE_c, m3_0_a2_0, N_347, Ready_0_sqmuxa_0_a2_4_a3_2, - N_758_0, Ready_0_sqmuxa, N_759_0, \RowAd_0[1] , \RowAd_0[0] , - \RowA[0] , \RowA[1] , \MAin_c[2] , \RowAd_0[3] , \RowAd_0[2] , - \RowA[2] , \MAin_c[5] , \MAin_c[4] , \RowAd_0[5] , \RowAd_0[4] , - \RowA[4] , \RowA[5] , \MAin_c[7] , \MAin_c[6] , \RowAd_0[7] , - \RowAd_0[6] , \RowA[6] , \RowA[7] , \MAin_c[9] , \MAin_c[8] , - \RowAd_0[9] , \RowAd_0[8] , \RowA[8] , \RowA[9] , XOR8MEG, - XOR8MEG_3_u_0_0_a3_0_2, N_441, XOR8MEG_3, g1_0, N_4, n8MEGENe_1_0, - n8MEGENe_0, CASr3, N_248_i_1_1, nRowColSel_0_0_0, nRRAS_0_sqmuxa, - \wb_adr_5_i_0_0[1] , N_417, N_416, N_382, \wb_adr_5_i_0_3[0] , - \wb_adr_5_i_0_0[0] , N_423, N_383, N_229_i, N_230_i, un1_wb_rst14_i_0, - \wb_adr[0] , \wb_adr[1] , \wb_adr[2] , \wb_adr_5[3] , \wb_adr_5[2] , - \wb_adr[3] , \wb_adr[4] , N_210, N_385, N_384, \wb_adr[5] , - \wb_adr[6] , \wb_adr_5[7] , N_386, \wb_adr[7] , - wb_cyc_stb_4_iv_0_a3_0_0, N_471_3, N_471_2, N_214, un1_PHI2r3, N_471, - wb_cyc_stb_4, N_178, wb_rst10, wb_cyc_stb, \wb_dati_5_1_iv_0_1[1] , - N_578, N_207, wb_we, \wb_dati_5_0_iv_0_a3_1[0] , N_576, - \wb_dati_5[1] , \wb_dati_5[0] , \wb_dati[0] , \wb_dati[1] , - \wb_dati_5_1_iv_i_i_a3_1[3] , \wb_dati_5_1_iv_i_i_1[3] , - \wb_dati_5_1_iv_i_i_0[3] , N_579, N_361, \wb_dati_5_1_iv_i_i[3] , - \wb_dati_5[2] , \wb_dati[2] , \wb_dati[3] , \wb_dati[4] , - \wb_dati_5_1_iv_0_1[4] , \wb_dati_5_1_iv_0_0[4] , \wb_dati_5[5] , - \wb_dati_5[4] , \wb_dati[5] , \wb_dati_5_1_iv_0_0[7] , N_488, N_486, - N_484, \wb_dati_5_1_iv_0_1[6] , \wb_dati_5[7] , \wb_dati_5[6] , - \wb_dati[6] , \wb_dati[7] , wb_req, N_92_i, N_31_i, wb_reqe_0, wb_rst, - N_515, wb_rste_0, wb_we_0_i_0_1, CmdUFMData, N_231_i, N_217, N_479, - N_209, CBR_fast, N_408, nRCAS_0_sqmuxa_1, N_248_i_sx, - un1_nRCAS_6_sqmuxa_i_0_0, nRCAS_r_i_0_o2_0_0, N_599, N_407, - wb_we_0_i_0_a3_0_0, N_427, wb_we_0_i_0_0, N_539, \Din_c[6] , - un1_CmdEnable20_0_0_0, \wb_adr_5_i_0_a3_0_1[0] , N_424, - \wb_adr_5_i_0_1[0] , N_542, N_208, \wb_dati_5_1_iv_0_a3_0_1[7] , - \ufmefb/g0_0_a3_2 , N_226, \wb_dati_5_1_iv_0_a3_0_1[1] , N_477, N_236, - N_596, N_536, N_502, N_412, N_522, nRCS_9_u_i_0_o3, - \wb_dati_5_1_iv_i_i_a3_3_0[3] , un1_nRCAS_6_sqmuxa_i_0_0_o2_0, N_221, - N_246_i, un1_CmdEnable20_0_0_a3_1_1, nRWE_s_i_0_tz_0, N_595, N_590, - N_49_i, CmdUFMData_1_sqmuxa, N_248_i_1_0, N_247_i, \Bank[5] , - \Bank[4] , \Bank[3] , \Bank[1] , un1_CmdEnable20_0_0_o3_11, - un1_CmdEnable20_0_0_o3_10, \Bank[7] , \Bank[6] , N_537, N_514, N_473, - N_472, RA10s_i, nRWE_s_i_0_a3_1_0, wb_cyc_stb_2_sqmuxa_i_a3_0, wb_ack, - un1_CmdEnable20_0_0_o3_4, un1_CmdEnable20_0_0_o3_3, \Bank[2] , - \Bank[0] , N_248_i_1, N_248_i, N_511, N_404, - wb_cyc_stb_4_iv_0_a3_0_2_0, N_505, \Din_c[2] , \Din_c[7] , - XOR8MEG_3_u_0_0_0_a2, G_4_0_a3_0, RDQMH_c, RDQML_c, \RA_c[6] , - \RA_c[8] , \RA_c[9] , \RA_c[0] , \RA_c[7] , \RA_c[1] , \RA_c[5] , - \RA_c[2] , \RA_c[4] , \CROW_c[1] , RA11d_0, \RBAd_0[1] , \wb_dato[0] , - \RD_in[0] , \WRD[0] , nRCAS_c, nRRAS_c, nRWE_c, nRCS_c, \RD_in[7] , - \WRD[7] , \RD_in[6] , \WRD[6] , \RD_in[5] , \WRD[5] , \RD_in[4] , - \WRD[4] , \RD_in[3] , \WRD[3] , \RD_in[2] , \WRD[2] , \RD_in[1] , - \WRD[1] , \RA_c[11] , \RA_c[10] , \RBA_c[1] , \RBA_c[0] , VCCI; + \FS_s[3] , \FS_cry[2] , \FS[2] , \FS[1] , \FS_s[2] , \FS_s[1] , N_367, + \MAin_c[1] , CmdEnable16, CmdEnable17, N_293_i, ADSubmitted, + ADSubmitted_r_0_0, PHI2_c, N_457, N_483, C1Submitted, C1Submitted_RNO, + nCCAS_c, nCCAS_c_i, CASr, CASr2, \S[1] , RASr2, \IS[3] , CO0, N_279_i, + Ready_0_sqmuxa_0_a2_2, N_482, CmdEnable_0_sqmuxa, un1_CmdEnable20_i, + CmdEnable, CmdEnable_s, N_260, \Din_c[1] , CmdLEDEN_4_u_i_m2_i_a2_0_0, + CmdLEDEN, N_461, LEDEN, CmdLEDEN_4_u_i_m2_i_0, N_17_i, XOR8MEG18, + \IS[0] , \Din_c[0] , CmdUFMData_1_sqmuxa, \IS_i[0] , CmdUFMData, + CmdUFMShift, CmdUFMShift_3, GND, CmdUFMWrite, N_415, CmdUFMWrite_3, + N_353, \Din_c[5] , \Din_c[4] , \Din_c[3] , CmdValid_r, CmdValid, + \MAin_c[0] , N_34_fast, CmdValid_fast, Cmdn8MEGEN, n8MEGEN, + Cmdn8MEGEN_4_u_i_m2_i_0, N_15_i, nFWE_c, nFWE_c_i, nCRAS_c, FWEr, + RD_1_i, IS_0_sqmuxa_0_o2, un1_nRCAS_6_sqmuxa_i_o2, nRCS_9_u_i_0_0, + Ready, N_76_i_i, N_32_i, \IS[2] , \IS[1] , N_73_i_i, N_69_i, N_261_i, + IS_0_sqmuxa_0_o3, N_74_i_i, nRWE_s_i_a2_1_0, InitReady, InitReady3, + N_705_0, wb_rst10, \wb_dato[1] , un1_FS_38_i, LEDEN_6, LEDENe_0, + Ready_fast, \CROW_c[0] , PHI2r2, PHI2r, \RBAd_0[0] , VCC, PHI2r3, + nRowColSel, \RowA[6] , \MAin_c[6] , nCRAS_c_i_0, RASr, \RA_c[6] , + RASr3, \wb_adr_5_i_0_o2[0] , \S_0_i_o3[1] , RCKEEN_8_u_1, + RCKEEN_8_u_0_0, CBR, RCKEEN_8, RCKEEN, RCKE_2, RCKE_c, m3_0_a2_0, + Ready_0_sqmuxa_0_o2, N_706_0, Ready_0_sqmuxa, N_707_0, \RowAd_0[1] , + \RowAd_0[0] , \RowA[0] , \RowA[1] , \MAin_c[3] , \MAin_c[2] , + \RowAd_0[3] , \RowAd_0[2] , \RowA[2] , \RowA[3] , \MAin_c[5] , + \MAin_c[4] , \RowAd_0[5] , \RowAd_0[4] , \RowA[4] , \RowA[5] , + \MAin_c[7] , \RowAd_0[7] , \RowAd_0[6] , \RowA[7] , \MAin_c[9] , + \MAin_c[8] , \RowAd_0[9] , \RowAd_0[8] , \RowA[8] , \RowA[9] , + XOR8MEG, XOR8MEG_3_u_0_0_a2_0_2, N_411, XOR8MEG_3, g1_0, N_4, + n8MEGENe_1_0, n8MEGENe_0, CASr3, N_251_i_1_0, N_70_i, nRowColSel_0_0, + nRRAS_0_sqmuxa, \wb_adr_5_i_3_0_0[1] , \wb_adr_5_i_3_0_a2_0[1] , + \wb_adr_5_i_3_0_a2[1] , N_216, \wb_adr_5_i_0_3[0] , + \wb_adr_5_i_0_2[0] , \FS_RNIOVGI[9] , \wb_dati_5_1_iv_0_a2_11[3] , + N_45_i, N_47_i, N_126_i, \wb_adr[0] , \wb_adr[1] , \wb_adr[2] , + \wb_adr_5[3] , \wb_adr_5[2] , \wb_adr[3] , \wb_adr[4] , + \FS_RNI82PA[15] , \wb_adr_5[5] , \wb_adr_5[4] , \wb_adr[5] , + \wb_adr[6] , \wb_adr_5[7] , \wb_adr_5[6] , \wb_adr[7] , + wb_cyc_stb_4_iv_0_0_a2_0_0, \FS_RNIHVJI[15] , N_99_2, N_99_1, + un1_PHI2r3_i_li, wb_cyc_stb_4_iv_0_0_a2_0, wb_cyc_stb_4, + wb_cyc_stb_2_sqmuxa_i_0_0, wb_cyc_stb, \wb_dati_5_1_iv_0_1[1] , + \FS_RNIGOCT[12] , \FS_RNIS637[9] , wb_we, \wb_dati_5_0_iv_0_a2_1[0] , + \wb_dati_5_1_iv_0_a2_12[3] , \wb_dati_5[1] , \wb_dati_5[0] , + \wb_dati[0] , \wb_dati[1] , \wb_dati_5_1_iv_0_0_a2_1[3] , + \wb_dati_5_1_iv_0_0_1[3] , \wb_dati_5_1_iv_0_0_0[3] , + \wb_dati_5_1_iv_0_a2_13[3] , \wb_dati_5_1_iv_0_0_o2[5] , + \wb_dati_5[3] , \wb_dati_5[2] , \wb_dati[2] , \wb_dati[3] , + \wb_dati[4] , \wb_dati_5_1_iv_0_1_0[4] , \wb_dati_5_1_iv_0_0_1[4] , + \wb_dati_5[5] , \wb_dati_5[4] , \wb_dati[5] , \wb_dati_5_1_iv_0_1[7] , + \wb_dati_5_1_iv_0_a2_5[7] , \wb_dati_5_1_iv_0_RNO[7] , + \wb_dati_5_1_iv_0_0_1[6] , \wb_dati_5[7] , \wb_dati_5[6] , + \wb_dati[6] , \wb_dati[7] , un1_wb_rst14_2_0_o2, wb_req, + un1_wb_rst14_2_i, N_122_i, wb_reqe_0, wb_rst_3, wb_rst, wb_rste_0, + wb_we_0_0_i_1, N_346_i, \wb_dati_5_1_iv_0_o2[7] , + \wb_dati_5_1_iv_0_o2_0_RNIMDJC1[4] , \wb_dati_5_1_iv_0_0_o2[3] , + \wb_dati_5_1_iv_0_o2_0[7] , \FS_RNIJO0F[12] , \FS_RNI9Q57[12] , + \wb_adr_5_i_0_1[0] , N_313, \wb_adr_5_i_0_0[0] , N_48, N_466, + \Din_c[6] , un1_CmdEnable20_0_0_0, \wb_dati_5_1_iv_0_a2_0_2[1] , + \wb_dati_5_1_iv_0_0[1] , \wb_dati_5_1_iv_0_0_o2[4] , + \ufmefb/g0_0_a3_2 , \FS_RNIF2MA[9] , nRWE_s_i_tz_0, nRCS_9_u_i_o3_0_0, + RCKEEN_8_u_0_o3, nRCS_9_u_i_o3_0_2, wb_we_0_0_i_1_1, + \wb_adr_5_i_0_a2_6[0] , \wb_adr_5_i_3_0_a2_3[1] , + \wb_dati_5_1_iv_0_o2_0[4] , \FS_RNI7U6M[14] , + \wb_dati_5_1_iv_0_1_RNO[7] , CBR_fast, N_142, N_141, nRCAS_0_sqmuxa_1, + N_252_i, un1_CmdEnable20_0_0_a2_1_1, nRCS_9_u_i_0, N_251_i_1, N_37_i, + RA10s_i, \Bank[6] , \Bank[5] , \Bank[3] , \Bank[2] , + un1_CmdEnable20_0_0_o2_11, un1_CmdEnable20_0_0_o2_10, \Bank[4] , + \Bank[0] , \wb_dati_5_1_iv_0_a2_7[4] , \wb_dati_5_1_iv_0_a2_6[4] , + \wb_dati_5_1_iv_0_0_a2[6] , \wb_dati_5_1_iv_0_a2_2[4] , + \wb_dati_5_1_iv_0_a2_0_0[7] , \wb_dati_5_1_iv_0_a2_0[7] , + \wb_dati_5_1_iv_0_a2_7[3] , \wb_dati_5_1_iv_0_a2_5[3] , + wb_cyc_stb_2_sqmuxa_i_0_0_a2_0, wb_ack, un1_CmdEnable20_0_0_o2_4, + un1_CmdEnable20_0_0_o2_3, \Bank[7] , \Bank[1] , N_442, \Din_c[2] , + wb_we_0_0_i_a2_0, wb_cyc_stb_2_sqmuxa_i_a2_2_0, \Din_c[7] , N_452, + InitReady3_0_a2_1_0, G_4_0_a3_0, N_251_i_sx, N_251_i, LED_c, RDQMH_c, + RDQML_c, \wb_dato[0] , \RA_c[2] , \RA_c[0] , \RA_c[8] , \RA_c[1] , + \RA_c[3] , \RA_c[4] , \RA_c[9] , \RA_c[5] , \RA_c[7] , \CROW_c[1] , + RA11d_0, \RBAd_0[1] , \RD_in[0] , \WRD[0] , nRCAS_c, nRRAS_c, nRWE_c, + RCLKout_c, nRCS_c, \RD_in[7] , \WRD[7] , \RD_in[6] , \WRD[6] , + \RD_in[5] , \WRD[5] , \RD_in[4] , \WRD[4] , \RD_in[3] , \WRD[3] , + \RD_in[2] , \WRD[2] , \RD_in[1] , \WRD[1] , \RA_c[11] , \RA_c[10] , + \RBA_c[1] , \RBA_c[0] , VCCI; SLICE_0 SLICE_0( .A1(\FS[0] ), .DI1(\FS_s[0] ), .CLK(RCLK_c), .F1(\FS_s[0] ), .Q1(\FS[0] ), .FCO(\FS_cry[0] )); @@ -126,84 +139,87 @@ module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, SLICE_9 SLICE_9( .A1(\FS[2] ), .A0(\FS[1] ), .DI1(\FS_s[2] ), .DI0(\FS_s[1] ), .CLK(RCLK_c), .FCI(\FS_cry[0] ), .F0(\FS_s[1] ), .Q0(\FS[1] ), .F1(\FS_s[2] ), .Q1(\FS[2] ), .FCO(\FS_cry[2] )); - SLICE_10 SLICE_10( .B1(un1_CmdEnable20_0_0_o3), .A1(\MAin_c[1] ), - .D0(CmdEnable16), .C0(CmdEnable17), .B0(N_524), .A0(ADSubmitted), - .DI0(ADSubmitted_r_0_0), .CLK(PHI2_c), .F0(ADSubmitted_r_0_0), - .Q0(ADSubmitted), .F1(N_524)); - SLICE_11 SLICE_11( .D1(\MAin_c[1] ), .C1(un1_CmdEnable20_0_0_o3), .B1(N_518), - .A1(N_594), .D0(\MAin_c[1] ), .C0(un1_CmdEnable20_0_0_o3), - .B0(C1Submitted), .A0(CmdEnable16), .DI0(C1Submitted_RNO), .CLK(PHI2_c), - .F0(C1Submitted_RNO), .Q0(C1Submitted), .F1(CmdEnable16)); + SLICE_10 SLICE_10( .B1(N_367), .A1(\MAin_c[1] ), .D0(CmdEnable16), + .C0(CmdEnable17), .B0(N_293_i), .A0(ADSubmitted), .DI0(ADSubmitted_r_0_0), + .CLK(PHI2_c), .F0(ADSubmitted_r_0_0), .Q0(ADSubmitted), .F1(N_293_i)); + SLICE_11 SLICE_11( .D1(\MAin_c[1] ), .C1(N_367), .B1(N_457), .A1(N_483), + .D0(\MAin_c[1] ), .C0(N_367), .B0(C1Submitted), .A0(CmdEnable16), + .DI0(C1Submitted_RNO), .CLK(PHI2_c), .F0(C1Submitted_RNO), + .Q0(C1Submitted), .F1(CmdEnable16)); SLICE_12 SLICE_12( .A0(nCCAS_c), .DI0(nCCAS_c_i), .M1(CASr), .CLK(RCLK_c), .F0(nCCAS_c_i), .Q0(CASr), .Q1(CASr2)); - SLICE_16 SLICE_16( .B1(\S[1] ), .A1(CO0), .B0(\S[1] ), .A0(CO0), - .DI0(N_123_i), .LSR(RASr2), .CLK(RCLK_c), .F0(N_123_i), .Q0(CO0), - .F1(N_345_i)); - SLICE_17 SLICE_17( .D1(\MAin_c[1] ), .C1(un1_CmdEnable20_0_0_o3), .B1(N_518), - .A1(N_593), .D0(CmdEnable_0_sqmuxa), .C0(un1_CmdEnable20_i), - .B0(CmdEnable17), .A0(CmdEnable), .DI0(CmdEnable_s), .CLK(PHI2_c), - .F0(CmdEnable_s), .Q0(CmdEnable), .F1(CmdEnable17)); - SLICE_18 SLICE_18( .D1(CmdValid_2_i_o2_1_o3), .C1(\Din_c[1] ), - .B1(CmdLEDEN_4_u_i_0_a3_0_0), .A1(CmdLEDEN), .C0(N_531), .B0(LEDEN), - .A0(CmdLEDEN_4_u_i_0_0), .DI0(N_40_i), .CE(XOR8MEG18), .CLK(PHI2_c), - .F0(N_40_i), .Q0(CmdLEDEN), .F1(CmdLEDEN_4_u_i_0_0)); - SLICE_20 SLICE_20( .D0(N_531), .C0(CmdValid_2_i_o2_1_o3), .B0(\Din_c[1] ), - .A0(CmdUFMShift), .DI0(CmdUFMShift_3), .CE(XOR8MEG18), .CLK(PHI2_c), - .F0(CmdUFMShift_3), .Q0(CmdUFMShift)); - SLICE_21 SLICE_21( .B1(CmdValid_2_i_o2_1_o3), .A1(CmdUFMWrite), .D0(N_531), - .C0(N_462), .B0(\Din_c[1] ), .A0(\Din_c[0] ), .DI0(CmdUFMWrite_3), - .CE(XOR8MEG18), .CLK(PHI2_c), .F0(CmdUFMWrite_3), .Q0(CmdUFMWrite), - .F1(N_462)); - SLICE_22 SLICE_22( .D1(N_213), .C1(\Din_c[5] ), .B1(\Din_c[4] ), - .A1(\Din_c[3] ), .B0(CmdValid_2_i_o2_1_o3), .A0(XOR8MEG18), - .DI0(CmdValid_r), .CLK(PHI2_c), .F0(CmdValid_r), .Q0(CmdValid), - .F1(CmdValid_2_i_o2_1_o3)); - SLICE_23 SLICE_23( .D1(un1_CmdEnable20_0_0_o3), .C1(\MAin_c[1] ), - .B1(\MAin_c[0] ), .A1(CmdEnable), .B0(CmdValid_2_i_o2_1_o3), - .A0(XOR8MEG18), .DI0(N_36_fast), .CLK(PHI2_c), .F0(N_36_fast), - .Q0(CmdValid_fast), .F1(XOR8MEG18)); - SLICE_24 SLICE_24( .D1(CmdValid_2_i_o2_1_o3), .C1(\Din_c[0] ), - .B1(Cmdn8MEGEN), .A1(CmdLEDEN_4_u_i_0_a3_0_0), .C0(n8MEGEN), .B0(N_531), - .A0(Cmdn8MEGEN_4_u_i_0_0), .DI0(N_38_i), .CE(XOR8MEG18), .CLK(PHI2_c), - .F0(N_38_i), .Q0(Cmdn8MEGEN), .F1(Cmdn8MEGEN_4_u_i_0_0)); + SLICE_16 SLICE_16( .D1(\S[1] ), .C1(RASr2), .B1(\IS[3] ), .A1(CO0), + .B0(\S[1] ), .A0(CO0), .DI0(N_279_i), .LSR(RASr2), .CLK(RCLK_c), + .F0(N_279_i), .Q0(CO0), .F1(Ready_0_sqmuxa_0_a2_2)); + SLICE_17 SLICE_17( .D1(\MAin_c[1] ), .C1(N_367), .B1(N_457), .A1(N_482), + .D0(CmdEnable_0_sqmuxa), .C0(un1_CmdEnable20_i), .B0(CmdEnable17), + .A0(CmdEnable), .DI0(CmdEnable_s), .CLK(PHI2_c), .F0(CmdEnable_s), + .Q0(CmdEnable), .F1(CmdEnable17)); + SLICE_18 SLICE_18( .D1(N_260), .C1(\Din_c[1] ), + .B1(CmdLEDEN_4_u_i_m2_i_a2_0_0), .A1(CmdLEDEN), .C0(N_461), .B0(LEDEN), + .A0(CmdLEDEN_4_u_i_m2_i_0), .DI0(N_17_i), .CE(XOR8MEG18), .CLK(PHI2_c), + .F0(N_17_i), .Q0(CmdLEDEN), .F1(CmdLEDEN_4_u_i_m2_i_0)); + SLICE_19 SLICE_19( .A0(\IS[0] ), .M0(\Din_c[0] ), .CE(CmdUFMData_1_sqmuxa), + .CLK(PHI2_c), .F0(\IS_i[0] ), .Q0(CmdUFMData)); + SLICE_20 SLICE_20( .D0(N_461), .C0(N_260), .B0(\Din_c[1] ), .A0(CmdUFMShift), + .DI0(CmdUFMShift_3), .CE(XOR8MEG18), .CLK(PHI2_c), .F0(CmdUFMShift_3), + .Q0(CmdUFMShift), .F1(GND)); + SLICE_21 SLICE_21( .B1(N_260), .A1(CmdUFMWrite), .D0(N_461), .C0(N_415), + .B0(\Din_c[1] ), .A0(\Din_c[0] ), .DI0(CmdUFMWrite_3), .CE(XOR8MEG18), + .CLK(PHI2_c), .F0(CmdUFMWrite_3), .Q0(CmdUFMWrite), .F1(N_415)); + SLICE_22 SLICE_22( .D1(N_353), .C1(\Din_c[5] ), .B1(\Din_c[4] ), + .A1(\Din_c[3] ), .B0(N_260), .A0(XOR8MEG18), .DI0(CmdValid_r), + .CLK(PHI2_c), .F0(CmdValid_r), .Q0(CmdValid), .F1(N_260)); + SLICE_23 SLICE_23( .D1(N_367), .C1(\MAin_c[1] ), .B1(\MAin_c[0] ), + .A1(CmdEnable), .B0(N_260), .A0(XOR8MEG18), .DI0(N_34_fast), .CLK(PHI2_c), + .F0(N_34_fast), .Q0(CmdValid_fast), .F1(XOR8MEG18)); + SLICE_24 SLICE_24( .D1(N_260), .C1(\Din_c[0] ), .B1(Cmdn8MEGEN), + .A1(CmdLEDEN_4_u_i_m2_i_a2_0_0), .C0(n8MEGEN), .B0(N_461), + .A0(Cmdn8MEGEN_4_u_i_m2_i_0), .DI0(N_15_i), .CE(XOR8MEG18), .CLK(PHI2_c), + .F0(N_15_i), .Q0(Cmdn8MEGEN), .F1(Cmdn8MEGEN_4_u_i_m2_i_0)); SLICE_25 SLICE_25( .B1(nFWE_c), .A1(nCCAS_c), .A0(nFWE_c), .DI0(nFWE_c_i), .CLK(nCRAS_c), .F0(nFWE_c_i), .Q0(FWEr), .F1(RD_1_i)); - SLICE_26 SLICE_26( .B1(CO0), .A1(CASr2), .B0(nRCS_9_u_i_0_o2_1_RNIL2K71), - .A0(\IS[0] ), .DI0(N_351_i_i), .CLK(RCLK_c), .F0(N_351_i_i), .Q0(\IS[0] ), - .F1(N_267)); + SLICE_26 SLICE_26( .D1(\IS[0] ), .C1(IS_0_sqmuxa_0_o2), + .B1(un1_nRCAS_6_sqmuxa_i_o2), .A1(nRCS_9_u_i_0_0), .C0(IS_0_sqmuxa_0_o2), + .B0(Ready), .A0(\IS[0] ), .DI0(N_76_i_i), .CLK(RCLK_c), .F0(N_76_i_i), + .Q0(\IS[0] ), .F1(N_32_i)); SLICE_27 SLICE_27( .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), .B0(\IS[1] ), - .A0(\IS[0] ), .DI1(N_348_i_i), .DI0(N_344_i), .CE(N_360_i), .CLK(RCLK_c), - .F0(N_344_i), .Q0(\IS[1] ), .F1(N_348_i_i), .Q1(\IS[2] )); - SLICE_28 SLICE_28( .A1(\IS[0] ), .D0(\IS[0] ), .C0(\IS[1] ), .B0(\IS[2] ), - .A0(\IS[3] ), .DI0(N_350_i_i), .CE(N_360_i), .CLK(RCLK_c), .F0(N_350_i_i), - .Q0(\IS[3] ), .F1(\IS_i[0] )); - SLICE_29 SLICE_29( .D1(N_581), .C1(InitReady3_0_a3_1), .B1(\FS[11] ), - .A1(\FS[10] ), .B0(InitReady), .A0(InitReady3), .DI0(N_757_0), - .CLK(RCLK_c), .F0(N_757_0), .Q0(InitReady), .F1(InitReady3)); + .A0(\IS[0] ), .DI1(N_73_i_i), .DI0(N_69_i), .CE(N_261_i), .CLK(RCLK_c), + .F0(N_69_i), .Q0(\IS[1] ), .F1(N_73_i_i), .Q1(\IS[2] )); + SLICE_28 SLICE_28( .D1(IS_0_sqmuxa_0_o3), .C1(\IS[2] ), .B1(\IS[1] ), + .A1(\IS[0] ), .D0(\IS[0] ), .C0(\IS[1] ), .B0(\IS[2] ), .A0(\IS[3] ), + .DI0(N_74_i_i), .CE(N_261_i), .CLK(RCLK_c), .F0(N_74_i_i), .Q0(\IS[3] ), + .F1(nRWE_s_i_a2_1_0)); + SLICE_29 SLICE_29( .D1(\FS[16] ), .C1(\FS[17] ), .B1(InitReady), + .A1(\FS[15] ), .B0(InitReady), .A0(InitReady3), .DI0(N_705_0), + .CLK(RCLK_c), .F0(N_705_0), .Q0(InitReady), .F1(wb_rst10)); SLICE_30 SLICE_30( .C1(\wb_dato[1] ), .B1(InitReady), .A1(CmdLEDEN), - .C0(LEDEN_6_i_m2_i_m2), .B0(CmdValid_RNIOOBE2), .A0(LEDEN), .DI0(LEDENe_0), - .CLK(RCLK_c), .F0(LEDENe_0), .Q0(LEDEN), .F1(LEDEN_6_i_m2_i_m2)); + .C0(un1_FS_38_i), .B0(LEDEN_6), .A0(LEDEN), .DI0(LEDENe_0), .CLK(RCLK_c), + .F0(LEDENe_0), .Q0(LEDEN), .F1(LEDEN_6)); SLICE_31 SLICE_31( .B0(Ready_fast), .A0(\CROW_c[0] ), .M1(PHI2r2), - .M0(PHI2r), .CLK(RCLK_c), .F0(\RBAd_0[0] ), .Q0(PHI2r2), .Q1(PHI2r3)); - SLICE_32 SLICE_32( .C1(nCRAS_c), .B1(LEDEN), .A1(CBR), .A0(nCRAS_c), - .DI0(nCRAS_c_i_0), .M1(RASr), .CLK(RCLK_c), .F0(nCRAS_c_i_0), .Q0(RASr), - .F1(LED_c), .Q1(RASr2)); - SLICE_33 SLICE_33( .C1(nRowColSel), .B1(\RowA[3] ), .A1(\MAin_c[3] ), + .M0(PHI2r), .CLK(RCLK_c), .F0(\RBAd_0[0] ), .Q0(PHI2r2), .F1(VCC), + .Q1(PHI2r3)); + SLICE_32 SLICE_32( .C1(nRowColSel), .B1(\RowA[6] ), .A1(\MAin_c[6] ), + .A0(nCRAS_c), .DI0(nCRAS_c_i_0), .M1(RASr), .CLK(RCLK_c), .F0(nCRAS_c_i_0), + .Q0(RASr), .F1(\RA_c[6] ), .Q1(RASr2)); + SLICE_33 SLICE_33( .C1(\FS[11] ), .B1(\FS[10] ), .A1(\FS[9] ), .B0(CmdEnable16), .A0(ADSubmitted), .M0(RASr2), .CLK(RCLK_c), - .F0(CmdEnable_0_sqmuxa), .Q0(RASr3), .F1(\RA_c[3] )); - SLICE_34 SLICE_34( .D1(N_216), .C1(InitReady), .B1(RASr2), .A1(Ready), - .D0(Ready), .C0(RCKEEN_8_u_0_1_0), .B0(RCKEEN_8_u_0_0_0), .A0(CBR), + .F0(CmdEnable_0_sqmuxa), .Q0(RASr3), .F1(\wb_adr_5_i_0_o2[0] )); + SLICE_34 SLICE_34( .D1(\S_0_i_o3[1] ), .C1(InitReady), .B1(RASr2), + .A1(Ready), .D0(Ready), .C0(RCKEEN_8_u_1), .B0(RCKEEN_8_u_0_0), .A0(CBR), .DI0(RCKEEN_8), .CLK(RCLK_c), .F0(RCKEEN_8), .Q0(RCKEEN), - .F1(RCKEEN_8_u_0_0_0)); + .F1(RCKEEN_8_u_0_0)); SLICE_35 SLICE_35( .B1(\S[1] ), .A1(RASr2), .D0(RCKEEN), .C0(RASr3), .B0(RASr2), .A0(RASr), .DI0(RCKE_2), .CLK(RCLK_c), .F0(RCKE_2), .Q0(RCKE_c), .F1(m3_0_a2_0)); SLICE_36 SLICE_36( .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), .D0(InitReady), - .C0(N_347), .B0(Ready_0_sqmuxa_0_a2_4_a3_2), .A0(Ready), .DI0(N_758_0), - .CLK(RCLK_c), .F0(N_758_0), .Q0(Ready), .F1(N_347)); - SLICE_37 SLICE_37( .D1(Ready_0_sqmuxa_0_a2_4_a3_2), .C1(Ready), .B1(N_347), - .A1(InitReady), .B0(Ready_fast), .A0(Ready_0_sqmuxa), .DI0(N_759_0), - .CLK(RCLK_c), .F0(N_759_0), .Q0(Ready_fast), .F1(Ready_0_sqmuxa)); + .C0(Ready_0_sqmuxa_0_o2), .B0(Ready_0_sqmuxa_0_a2_2), .A0(Ready), + .DI0(N_706_0), .CLK(RCLK_c), .F0(N_706_0), .Q0(Ready), + .F1(Ready_0_sqmuxa_0_o2)); + SLICE_37 SLICE_37( .D1(Ready_0_sqmuxa_0_a2_2), .C1(Ready), + .B1(Ready_0_sqmuxa_0_o2), .A1(InitReady), .B0(Ready_fast), + .A0(Ready_0_sqmuxa), .DI0(N_707_0), .CLK(RCLK_c), .F0(N_707_0), + .Q0(Ready_fast), .F1(Ready_0_sqmuxa)); SLICE_38 SLICE_38( .B1(Ready_fast), .A1(\MAin_c[1] ), .B0(Ready_fast), .A0(\MAin_c[0] ), .DI1(\RowAd_0[1] ), .DI0(\RowAd_0[0] ), .CLK(nCRAS_c), .F0(\RowAd_0[0] ), .Q0(\RowA[0] ), .F1(\RowAd_0[1] ), .Q1(\RowA[1] )); @@ -219,252 +235,288 @@ module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, SLICE_42 SLICE_42( .B1(Ready_fast), .A1(\MAin_c[9] ), .B0(Ready_fast), .A0(\MAin_c[8] ), .DI1(\RowAd_0[9] ), .DI0(\RowAd_0[8] ), .CLK(nCRAS_c), .F0(\RowAd_0[8] ), .Q0(\RowA[8] ), .F1(\RowAd_0[9] ), .Q1(\RowA[9] )); - SLICE_43 SLICE_43( .D1(\S[1] ), .C1(RASr2), .B1(\IS[3] ), .A1(CO0), - .B0(\S[1] ), .A0(CO0), .DI0(N_216), .LSR(RASr2), .CLK(RCLK_c), .F0(N_216), - .Q0(\S[1] ), .F1(Ready_0_sqmuxa_0_a2_4_a3_2)); - SLICE_44 SLICE_44( .D1(XOR8MEG), .C1(N_213), .B1(\Din_c[5] ), - .A1(\Din_c[4] ), .D0(XOR8MEG_3_u_0_0_a3_0_2), .C0(N_441), .B0(LEDEN), + SLICE_43 SLICE_43( .D1(Ready), .C1(RCKE_c), .B1(RASr2), .A1(\S_0_i_o3[1] ), + .B0(\S[1] ), .A0(CO0), .DI0(\S_0_i_o3[1] ), .LSR(RASr2), .CLK(RCLK_c), + .F0(\S_0_i_o3[1] ), .Q0(\S[1] ), .F1(nRCS_9_u_i_0_0)); + SLICE_44 SLICE_44( .D1(XOR8MEG), .C1(N_353), .B1(\Din_c[5] ), + .A1(\Din_c[4] ), .D0(XOR8MEG_3_u_0_0_a2_0_2), .C0(N_411), .B0(LEDEN), .A0(\Din_c[1] ), .DI0(XOR8MEG_3), .CE(XOR8MEG18), .CLK(PHI2_c), - .F0(XOR8MEG_3), .Q0(XOR8MEG), .F1(N_441)); + .F0(XOR8MEG_3), .Q0(XOR8MEG), .F1(N_411)); SLICE_45 SLICE_45( .D1(g1_0), .C1(N_4), .B1(InitReady), .A1(CmdValid), - .C0(n8MEGENe_1_0), .B0(n8MEGEN), .A0(CmdValid_RNIOOBE2), .DI0(n8MEGENe_0), - .CLK(RCLK_c), .F0(n8MEGENe_0), .Q0(n8MEGEN), .F1(CmdValid_RNIOOBE2)); - SLICE_46 SLICE_46( .B1(FWEr), .A1(CASr3), .D0(Ready), .C0(N_345_i), - .B0(N_248_i_1_1), .A0(CBR), .DI0(nRowColSel_0_0_0), .LSR(nRRAS_0_sqmuxa), - .CLK(RCLK_c), .F0(nRowColSel_0_0_0), .Q0(nRowColSel), .F1(N_248_i_1_1)); - SLICE_47 SLICE_47( .D1(\wb_adr_5_i_0_0[1] ), .C1(N_417), .B1(N_416), - .A1(N_382), .D0(\wb_adr_5_i_0_3[0] ), .C0(\wb_adr_5_i_0_0[0] ), .B0(N_423), - .A0(N_383), .DI1(N_229_i), .DI0(N_230_i), .CE(un1_wb_rst14_i_0), - .CLK(RCLK_c), .F0(N_230_i), .Q0(\wb_adr[0] ), .F1(N_229_i), - .Q1(\wb_adr[1] )); + .C0(un1_FS_38_i), .B0(n8MEGENe_1_0), .A0(n8MEGEN), .DI0(n8MEGENe_0), + .CLK(RCLK_c), .F0(n8MEGENe_0), .Q0(n8MEGEN), .F1(un1_FS_38_i)); + SLICE_46 SLICE_46( .B1(FWEr), .A1(CASr3), .D0(Ready), .C0(N_251_i_1_0), + .B0(N_70_i), .A0(CBR), .DI0(nRowColSel_0_0), .LSR(nRRAS_0_sqmuxa), + .CLK(RCLK_c), .F0(nRowColSel_0_0), .Q0(nRowColSel), .F1(N_251_i_1_0)); + SLICE_47 SLICE_47( .D1(\wb_adr_5_i_3_0_0[1] ), .C1(\wb_adr_5_i_3_0_a2_0[1] ), + .B1(\wb_adr_5_i_3_0_a2[1] ), .A1(N_216), .D0(\wb_adr_5_i_0_3[0] ), + .C0(\wb_adr_5_i_0_2[0] ), .B0(\FS_RNIOVGI[9] ), + .A0(\wb_dati_5_1_iv_0_a2_11[3] ), .DI1(N_45_i), .DI0(N_47_i), .CE(N_126_i), + .CLK(RCLK_c), .F0(N_47_i), .Q0(\wb_adr[0] ), .F1(N_45_i), .Q1(\wb_adr[1] )); SLICE_48 SLICE_48( .B1(\wb_adr[2] ), .A1(InitReady), .B0(\wb_adr[1] ), - .A0(InitReady), .DI1(\wb_adr_5[3] ), .DI0(\wb_adr_5[2] ), - .CE(un1_wb_rst14_i_0), .CLK(RCLK_c), .F0(\wb_adr_5[2] ), .Q0(\wb_adr[2] ), - .F1(\wb_adr_5[3] ), .Q1(\wb_adr[3] )); - SLICE_49 SLICE_49( .D1(\wb_adr[4] ), .C1(N_210), .B1(InitReady), - .A1(\FS[15] ), .D0(\wb_adr[3] ), .C0(N_210), .B0(InitReady), .A0(\FS[15] ), - .DI1(N_385), .DI0(N_384), .CE(un1_wb_rst14_i_0), .CLK(RCLK_c), .F0(N_384), - .Q0(\wb_adr[4] ), .F1(N_385), .Q1(\wb_adr[5] )); - SLICE_50 SLICE_50( .B1(\wb_adr[6] ), .A1(InitReady), .D0(\wb_adr[5] ), - .C0(N_210), .B0(InitReady), .A0(\FS[15] ), .DI1(\wb_adr_5[7] ), - .DI0(N_386), .CE(un1_wb_rst14_i_0), .CLK(RCLK_c), .F0(N_386), + .A0(InitReady), .DI1(\wb_adr_5[3] ), .DI0(\wb_adr_5[2] ), .CE(N_126_i), + .CLK(RCLK_c), .F0(\wb_adr_5[2] ), .Q0(\wb_adr[2] ), .F1(\wb_adr_5[3] ), + .Q1(\wb_adr[3] )); + SLICE_49 SLICE_49( .C1(\wb_adr[4] ), .B1(\FS_RNI82PA[15] ), .A1(InitReady), + .C0(\wb_adr[3] ), .B0(\FS_RNI82PA[15] ), .A0(InitReady), + .DI1(\wb_adr_5[5] ), .DI0(\wb_adr_5[4] ), .CE(N_126_i), .CLK(RCLK_c), + .F0(\wb_adr_5[4] ), .Q0(\wb_adr[4] ), .F1(\wb_adr_5[5] ), .Q1(\wb_adr[5] )); + SLICE_50 SLICE_50( .B1(\wb_adr[6] ), .A1(InitReady), .C0(\wb_adr[5] ), + .B0(\FS_RNI82PA[15] ), .A0(InitReady), .DI1(\wb_adr_5[7] ), + .DI0(\wb_adr_5[6] ), .CE(N_126_i), .CLK(RCLK_c), .F0(\wb_adr_5[6] ), .Q0(\wb_adr[6] ), .F1(\wb_adr_5[7] ), .Q1(\wb_adr[7] )); - SLICE_51 SLICE_51( .D1(wb_cyc_stb_4_iv_0_a3_0_0), .C1(N_471_3), .B1(N_471_2), - .A1(N_214), .D0(un1_PHI2r3), .C0(N_471), .B0(InitReady), .A0(CmdUFMWrite), - .DI0(wb_cyc_stb_4), .CE(N_178), .LSR(wb_rst10), .CLK(RCLK_c), - .F0(wb_cyc_stb_4), .Q0(wb_cyc_stb), .F1(N_471)); - SLICE_52 SLICE_52( .D1(\wb_dati_5_1_iv_0_1[1] ), .C1(N_578), .B1(N_207), - .A1(\FS[11] ), .D0(wb_we), .C0(\wb_dati_5_0_iv_0_a3_1[0] ), .B0(N_576), - .A0(InitReady), .DI1(\wb_dati_5[1] ), .DI0(\wb_dati_5[0] ), - .CE(un1_wb_rst14_i_0), .CLK(RCLK_c), .F0(\wb_dati_5[0] ), - .Q0(\wb_dati[0] ), .F1(\wb_dati_5[1] ), .Q1(\wb_dati[1] )); - SLICE_53 SLICE_53( .D1(\wb_dati_5_1_iv_i_i_a3_1[3] ), - .C1(\wb_dati_5_1_iv_i_i_1[3] ), .B1(\wb_dati_5_1_iv_i_i_0[3] ), .A1(N_579), - .C0(\wb_dati[1] ), .B0(N_361), .A0(InitReady), - .DI1(\wb_dati_5_1_iv_i_i[3] ), .DI0(\wb_dati_5[2] ), .CE(un1_wb_rst14_i_0), - .CLK(RCLK_c), .F0(\wb_dati_5[2] ), .Q0(\wb_dati[2] ), - .F1(\wb_dati_5_1_iv_i_i[3] ), .Q1(\wb_dati[3] )); - SLICE_54 SLICE_54( .C1(\wb_dati[4] ), .B1(N_361), .A1(InitReady), - .D0(\wb_dati_5_1_iv_0_1[4] ), .C0(\wb_dati_5_1_iv_0_0[4] ), .B0(N_578), - .A0(\FS[9] ), .DI1(\wb_dati_5[5] ), .DI0(\wb_dati_5[4] ), - .CE(un1_wb_rst14_i_0), .CLK(RCLK_c), .F0(\wb_dati_5[4] ), - .Q0(\wb_dati[4] ), .F1(\wb_dati_5[5] ), .Q1(\wb_dati[5] )); - SLICE_55 SLICE_55( .D1(\wb_dati_5_1_iv_0_0[7] ), .C1(N_488), .B1(N_486), - .A1(N_484), .D0(\wb_dati_5_1_iv_0_1[6] ), .C0(N_578), .B0(N_207), - .A0(\FS[11] ), .DI1(\wb_dati_5[7] ), .DI0(\wb_dati_5[6] ), - .CE(un1_wb_rst14_i_0), .CLK(RCLK_c), .F0(\wb_dati_5[6] ), - .Q0(\wb_dati[6] ), .F1(\wb_dati_5[7] ), .Q1(\wb_dati[7] )); - SLICE_56 SLICE_56( .D1(\FS[16] ), .C1(\FS[17] ), .B1(InitReady), .A1(N_581), - .C0(wb_req), .B0(N_92_i), .A0(N_31_i), .DI0(wb_reqe_0), .LSR(wb_rst10), - .CLK(RCLK_c), .F0(wb_reqe_0), .Q0(wb_req), .F1(N_31_i)); - SLICE_57 SLICE_57( .D1(\FS[16] ), .C1(\FS[17] ), .B1(\FS[15] ), - .A1(InitReady), .D0(wb_rst10), .C0(wb_rst), .B0(N_515), .A0(N_92_i), - .DI0(wb_rste_0), .CLK(RCLK_c), .F0(wb_rste_0), .Q0(wb_rst), .F1(wb_rst10)); - SLICE_58 SLICE_58( .D1(\wb_adr[0] ), .C1(N_210), .B1(InitReady), - .A1(\FS[15] ), .D0(wb_we_0_i_0_1), .C0(N_210), .B0(InitReady), - .A0(CmdUFMData), .DI0(N_231_i), .CE(un1_wb_rst14_i_0), .LSR(wb_rst10), - .CLK(RCLK_c), .F0(N_231_i), .Q0(wb_we), .F1(N_382)); - wb_dati_5_1_iv_0_o3_5__SLICE_59 \wb_dati_5_1_iv_0_o3[5]/SLICE_59 ( - .D1(\FS[12] ), .C1(N_217), .B1(N_214), .A1(N_479), .D0(\FS[13] ), - .C0(N_209), .B0(N_214), .A0(N_479), .M0(\FS[9] ), .OFX0(N_361)); - SLICE_60 SLICE_60( .D1(m3_0_a2_0), .C1(Ready), .B1(CO0), .A1(CBR_fast), - .D0(CO0), .C0(N_408), .B0(nRCAS_0_sqmuxa_1), .A0(\S[1] ), .F0(N_248_i_sx), - .F1(nRCAS_0_sqmuxa_1)); - SLICE_61 SLICE_61( .D1(\S[1] ), .C1(Ready), .B1(N_408), .A1(CO0), .C0(CASr2), - .B0(CO0), .A0(un1_nRCAS_6_sqmuxa_i_0_0), .F0(nRCAS_r_i_0_o2_0_0), - .F1(un1_nRCAS_6_sqmuxa_i_0_0)); - SLICE_62 SLICE_62( .D1(\FS[11] ), .C1(\FS[10] ), .B1(\FS[9] ), - .A1(InitReady), .C0(\FS[14] ), .B0(InitReady), .A0(N_599), .F0(N_407), - .F1(N_599)); - SLICE_63 SLICE_63( .D1(wb_we_0_i_0_a3_0_0), .C1(N_427), .B1(N_207), - .A1(\FS[12] ), .D0(wb_we_0_i_0_0), .C0(N_407), .B0(\FS[13] ), - .A0(\FS[12] ), .F0(wb_we_0_i_0_1), .F1(wb_we_0_i_0_0)); - SLICE_64 SLICE_64( .D1(N_539), .C1(\MAin_c[0] ), .B1(\Din_c[6] ), - .A1(\Din_c[3] ), .D0(N_594), .C0(N_518), .B0(\MAin_c[1] ), - .A0(\MAin_c[0] ), .F0(un1_CmdEnable20_0_0_0), .F1(N_594)); - SLICE_65 SLICE_65( .D1(\wb_adr_5_i_0_a3_0_1[0] ), .C1(N_424), .B1(\FS[10] ), - .A1(\FS[9] ), .D0(\wb_adr_5_i_0_1[0] ), .C0(N_542), .B0(N_208), - .A0(\FS[9] ), .F0(\wb_adr_5_i_0_3[0] ), .F1(\wb_adr_5_i_0_1[0] )); - SLICE_66 SLICE_66( .D1(\FS[16] ), .C1(\FS[17] ), .B1(\FS[15] ), - .A1(InitReady), .D0(\wb_dati_5_1_iv_0_a3_0_1[7] ), .C0(\wb_dati[6] ), - .B0(N_214), .A0(InitReady), .F0(\wb_dati_5_1_iv_0_0[7] ), .F1(N_214)); - SLICE_67 SLICE_67( .D1(N_579), .C1(N_208), .B1(\FS[10] ), .A1(\FS[9] ), - .C0(\FS[13] ), .B0(\FS[11] ), .A0(\FS[10] ), .F0(N_208), - .F1(\wb_dati_5_1_iv_0_0[4] )); - SLICE_68 SLICE_68( .C1(\FS[9] ), .B1(\FS[10] ), .A1(\FS[11] ), - .C0(\ufmefb/g0_0_a3_2 ), .B0(N_226), .A0(N_214), .F0(N_4), .F1(N_226)); - SLICE_69 SLICE_69( .D1(\wb_dati_5_1_iv_0_a3_0_1[1] ), .C1(N_214), - .B1(\FS[14] ), .A1(\FS[12] ), .D0(\FS[9] ), .C0(\FS[10] ), .B0(\FS[11] ), - .A0(\FS[13] ), .F0(\wb_dati_5_1_iv_0_a3_0_1[1] ), .F1(N_477)); - SLICE_70 SLICE_70( .D1(N_542), .C1(N_236), .B1(\FS[13] ), .A1(\FS[11] ), - .C0(\FS[14] ), .B0(InitReady), .A0(\FS[12] ), .F0(N_542), .F1(N_424)); - SLICE_71 SLICE_71( .D1(N_596), .C1(N_536), .B1(N_502), .A1(N_412), - .C0(\FS[9] ), .B0(\FS[10] ), .A0(\FS[11] ), .F0(N_596), - .F1(\wb_dati_5_1_iv_i_i_1[3] )); - SLICE_72 SLICE_72( .D1(nRRAS_0_sqmuxa), .C1(RCKE_c), .B1(RASr2), .A1(N_522), - .C0(CO0), .B0(\S[1] ), .A0(Ready), .F0(nRRAS_0_sqmuxa), - .F1(nRCS_9_u_i_0_o3)); - SLICE_73 SLICE_73( .D1(\wb_dati_5_1_iv_i_i_a3_3_0[3] ), .C1(\wb_dati[2] ), - .B1(N_502), .A1(InitReady), .D0(\FS[9] ), .C0(\FS[10] ), .B0(\FS[11] ), - .A0(\FS[12] ), .F0(\wb_dati_5_1_iv_i_i_a3_3_0[3] ), - .F1(\wb_dati_5_1_iv_i_i_0[3] )); - SLICE_74 SLICE_74( .C1(\IS[3] ), .B1(\IS[2] ), .A1(\IS[1] ), .D0(InitReady), - .C0(RASr2), .B0(un1_nRCAS_6_sqmuxa_i_0_0_o2_0), .A0(Ready), .F0(N_408), - .F1(un1_nRCAS_6_sqmuxa_i_0_0_o2_0)); - SLICE_75 SLICE_75( .B1(InitReady), .A1(\FS[14] ), .D0(\FS[12] ), - .C0(\FS[11] ), .B0(N_207), .A0(N_515), .F0(\wb_adr_5_i_0_0[1] ), - .F1(N_515)); - SLICE_76 SLICE_76( .D1(\FS[14] ), .C1(\FS[13] ), .B1(\FS[11] ), - .A1(\FS[10] ), .D0(\FS[9] ), .C0(N_214), .B0(\FS[12] ), .A0(N_217), - .F0(N_486), .F1(N_217)); - SLICE_77 SLICE_77( .D1(N_214), .C1(\FS[14] ), .B1(\FS[13] ), .A1(\FS[12] ), - .D0(\FS[9] ), .C0(\FS[10] ), .B0(\FS[11] ), .A0(N_578), .F0(N_484), - .F1(N_578)); - SLICE_78 SLICE_78( .D1(un1_nRCAS_6_sqmuxa_i_0_0_o2_0), .C1(N_221), - .B1(N_216), .A1(\IS[0] ), .D0(N_522), .C0(RASr2), .B0(RCKE_c), - .A0(nRRAS_0_sqmuxa), .F0(N_246_i), .F1(N_522)); - SLICE_79 SLICE_79( .B1(RASr2), .A1(InitReady), .D0(Ready), .C0(N_221), - .B0(\S[1] ), .A0(CO0), .F0(N_360_i), .F1(N_221)); - SLICE_80 SLICE_80( .C1(N_593), .B1(N_518), .A1(\MAin_c[1] ), - .D0(un1_CmdEnable20_0_0_a3_1_1), .C0(un1_CmdEnable20_0_0_0), - .B0(un1_CmdEnable20_0_0_o3), .A0(C1Submitted), .M1(nCCAS_c_i), - .M0(nCCAS_c_i), .CLK(nCRAS_c), .F0(un1_CmdEnable20_i), .Q0(CBR), - .F1(un1_CmdEnable20_0_0_a3_1_1), .Q1(CBR_fast)); - SLICE_81 SLICE_81( .C1(\S[1] ), .B1(Ready), .A1(CBR), .D0(nRWE_s_i_0_tz_0), - .C0(N_595), .B0(N_590), .A0(nRCAS_0_sqmuxa_1), .F0(N_49_i), .F1(N_590)); - SLICE_82 SLICE_82( .D1(\Din_c[3] ), .C1(\Din_c[5] ), .B1(\Din_c[4] ), - .A1(N_213), .B0(XOR8MEG18), .A0(N_531), .M0(\Din_c[0] ), - .CE(CmdUFMData_1_sqmuxa), .CLK(PHI2_c), .F0(CmdUFMData_1_sqmuxa), - .Q0(CmdUFMData), .F1(N_531)); - SLICE_83 SLICE_83( .B1(FWEr), .A1(CO0), .D0(N_595), .C0(N_590), - .B0(N_248_i_1_0), .A0(nRCS_9_u_i_0_o3), .F0(N_247_i), .F1(N_248_i_1_0)); - SLICE_84 SLICE_84( .D1(\Bank[5] ), .C1(\Bank[4] ), .B1(\Bank[3] ), - .A1(\Bank[1] ), .D0(un1_CmdEnable20_0_0_o3_11), - .C0(un1_CmdEnable20_0_0_o3_10), .B0(\Bank[7] ), .A0(\Bank[6] ), - .F0(un1_CmdEnable20_0_0_o3), .F1(un1_CmdEnable20_0_0_o3_11)); - SLICE_85 SLICE_85( .D1(N_576), .C1(N_537), .B1(N_514), .A1(\FS[10] ), - .D0(\wb_dati[5] ), .C0(N_473), .B0(N_472), .A0(InitReady), - .F0(\wb_dati_5_1_iv_0_1[6] ), .F1(N_473)); - SLICE_86 SLICE_86( .D1(N_536), .C1(N_502), .B1(N_207), .A1(\FS[11] ), - .D0(\wb_dati[3] ), .C0(N_479), .B0(N_473), .A0(InitReady), - .F0(\wb_dati_5_1_iv_0_1[4] ), .F1(N_479)); - SLICE_87 SLICE_87( .C1(\FS[14] ), .B1(N_214), .A1(\FS[12] ), .D0(N_579), - .C0(\FS[13] ), .B0(\FS[11] ), .A0(\FS[10] ), .F0(N_488), .F1(N_579)); - SLICE_88 SLICE_88( .D1(CO0), .C1(\S[1] ), .B1(N_221), .A1(Ready), - .D0(nRCS_9_u_i_0_o2_1_RNIL2K71), .C0(\IS[3] ), .B0(\IS[2] ), .A0(\IS[1] ), - .F0(RA10s_i), .F1(nRCS_9_u_i_0_o2_1_RNIL2K71)); - SLICE_89 SLICE_89( .B1(\FS[10] ), .A1(\FS[9] ), .D0(N_579), .C0(N_236), - .B0(\FS[13] ), .A0(\FS[11] ), .F0(N_472), .F1(N_236)); - SLICE_90 SLICE_90( .D1(nRCS_9_u_i_0_o2_1_RNIL2K71), .C1(\IS[2] ), - .B1(\IS[1] ), .A1(\IS[0] ), .D0(nRWE_s_i_0_a3_1_0), .C0(nRRAS_0_sqmuxa), - .B0(RCKE_c), .A0(RASr2), .F0(nRWE_s_i_0_tz_0), .F1(nRWE_s_i_0_a3_1_0)); - SLICE_91 SLICE_91( .D1(\FS[9] ), .C1(N_214), .B1(\FS[13] ), .A1(N_209), - .D0(\wb_dati[0] ), .C0(N_477), .B0(N_412), .A0(InitReady), - .F0(\wb_dati_5_1_iv_0_1[1] ), .F1(N_412)); - SLICE_92 SLICE_92( .C1(wb_req), .B1(N_471_3), .A1(\FS[0] ), - .D0(wb_cyc_stb_2_sqmuxa_i_a3_0), .C0(wb_ack), .B0(N_471_2), .A0(N_214), - .F0(N_178), .F1(wb_cyc_stb_2_sqmuxa_i_a3_0)); - SLICE_93 SLICE_93( .D1(\MAin_c[7] ), .C1(\MAin_c[5] ), .B1(\MAin_c[3] ), - .A1(\MAin_c[2] ), .D0(un1_CmdEnable20_0_0_o3_4), - .C0(un1_CmdEnable20_0_0_o3_3), .B0(\Bank[2] ), .A0(\Bank[0] ), - .F0(un1_CmdEnable20_0_0_o3_10), .F1(un1_CmdEnable20_0_0_o3_4)); - SLICE_94 SLICE_94( .D1(N_248_i_sx), .C1(N_248_i_1_0), .B1(N_248_i_1_1), - .A1(N_248_i_1), .D0(nRCAS_r_i_0_o2_0_0), .C0(N_267), .B0(FWEr), .A0(CBR), - .F0(N_248_i_1), .F1(N_248_i)); - SLICE_95 SLICE_95( .B1(\FS[13] ), .A1(\FS[12] ), .D0(N_536), .C0(N_207), - .B0(InitReady), .A0(\FS[11] ), .F0(N_427), .F1(N_536)); - SLICE_96 SLICE_96( .B1(InitReady), .A1(\FS[14] ), .D0(N_511), .C0(N_404), - .B0(\FS[13] ), .A0(\FS[12] ), .F0(\wb_adr_5_i_0_0[0] ), .F1(N_511)); - SLICE_97 SLICE_97( .B1(\FS[17] ), .A1(\FS[16] ), .D0(\wb_dati[7] ), - .C0(N_210), .B0(InitReady), .A0(\FS[15] ), .F0(N_383), .F1(N_210)); - SLICE_98 SLICE_98( .B1(\FS[4] ), .A1(\FS[3] ), - .D0(wb_cyc_stb_4_iv_0_a3_0_2_0), .C0(\FS[7] ), .B0(\FS[6] ), .A0(\FS[2] ), - .F0(N_471_2), .F1(wb_cyc_stb_4_iv_0_a3_0_2_0)); - SLICE_99 SLICE_99( .B1(\Din_c[5] ), .A1(\Din_c[3] ), .D0(N_505), - .C0(\MAin_c[0] ), .B0(\Din_c[6] ), .A0(\Din_c[2] ), .F0(N_593), .F1(N_505)); - SLICE_100 SLICE_100( .B1(\Din_c[7] ), .A1(\Din_c[6] ), .D0(N_539), - .C0(XOR8MEG_3_u_0_0_0_a2), .B0(N_213), .A0(\Din_c[3] ), - .F0(XOR8MEG_3_u_0_0_a3_0_2), .F1(N_213)); - SLICE_101 SLICE_101( .B1(\FS[14] ), .A1(\FS[12] ), .D0(N_537), .C0(N_514), - .B0(\FS[10] ), .A0(\FS[9] ), .F0(\wb_dati_5_1_iv_0_a3_0_1[7] ), .F1(N_537)); - SLICE_102 SLICE_102( .B1(\FS[13] ), .A1(\FS[11] ), .D0(N_514), .C0(\FS[14] ), - .B0(\FS[12] ), .A0(\FS[10] ), .F0(\wb_dati_5_0_iv_0_a3_1[0] ), .F1(N_514)); - SLICE_103 SLICE_103( .B1(PHI2r3), .A1(PHI2r2), .D0(InitReady), - .C0(G_4_0_a3_0), .B0(CmdValid_fast), .A0(CmdUFMShift), - .F0(un1_wb_rst14_i_0), .F1(G_4_0_a3_0)); - SLICE_104 SLICE_104( .C1(\FS[14] ), .B1(\FS[13] ), .A1(\FS[12] ), - .D0(wb_ack), .C0(\FS[14] ), .B0(\FS[13] ), .A0(\FS[12] ), - .F0(\ufmefb/g0_0_a3_2 ), .F1(N_581)); - SLICE_105 SLICE_105( .D1(N_226), .C1(InitReady), .B1(\FS[14] ), - .A1(\FS[13] ), .C0(\FS[14] ), .B0(InitReady), .A0(\FS[13] ), - .F0(wb_we_0_i_0_a3_0_0), .F1(N_417)); - SLICE_106 SLICE_106( .D1(N_599), .C1(\FS[14] ), .B1(\FS[13] ), .A1(\FS[12] ), - .C0(\FS[12] ), .B0(\FS[13] ), .A0(N_599), .F0(N_423), .F1(N_416)); - SLICE_107 SLICE_107( .C1(PHI2r3), .B1(PHI2r2), .A1(CmdValid), .D0(PHI2r3), - .C0(PHI2r2), .B0(InitReady), .A0(CmdValid), .M0(CASr2), .CLK(RCLK_c), - .F0(N_92_i), .Q0(CASr3), .F1(un1_PHI2r3)); - SLICE_108 SLICE_108( .D1(\S[1] ), .C1(FWEr), .B1(CO0), .A1(CASr2), .D0(FWEr), - .C0(CO0), .B0(CASr3), .A0(CASr2), .F0(N_595), .F1(RCKEEN_8_u_0_1_0)); - SLICE_109 SLICE_109( .D1(\FS[13] ), .C1(\FS[11] ), .B1(\FS[10] ), - .A1(\FS[9] ), .C0(\FS[11] ), .B0(\FS[10] ), .A0(\FS[9] ), .F0(N_404), - .F1(\wb_dati_5_1_iv_i_i_a3_1[3] )); - SLICE_110 SLICE_110( .D1(InitReady), .C1(\FS[13] ), .B1(\FS[12] ), - .A1(\FS[11] ), .D0(\FS[14] ), .C0(\FS[12] ), .B0(\FS[11] ), .A0(\FS[10] ), - .F0(N_209), .F1(\wb_adr_5_i_0_a3_0_1[0] )); - SLICE_111 SLICE_111( .B1(nRowColSel), .A1(\MAin_c[9] ), .B0(nRowColSel), + SLICE_51 SLICE_51( .D1(wb_cyc_stb_4_iv_0_0_a2_0_0), .C1(\FS_RNIHVJI[15] ), + .B1(N_99_2), .A1(N_99_1), .D0(un1_PHI2r3_i_li), + .C0(wb_cyc_stb_4_iv_0_0_a2_0), .B0(InitReady), .A0(CmdUFMWrite), + .DI0(wb_cyc_stb_4), .CE(wb_cyc_stb_2_sqmuxa_i_0_0), .LSR(wb_rst10), + .CLK(RCLK_c), .F0(wb_cyc_stb_4), .Q0(wb_cyc_stb), + .F1(wb_cyc_stb_4_iv_0_0_a2_0)); + SLICE_52 SLICE_52( .D1(\wb_dati_5_1_iv_0_1[1] ), .C1(\FS_RNIGOCT[12] ), + .B1(\FS_RNIS637[9] ), .A1(\FS[11] ), .D0(wb_we), + .C0(\wb_dati_5_0_iv_0_a2_1[0] ), .B0(\wb_dati_5_1_iv_0_a2_12[3] ), + .A0(InitReady), .DI1(\wb_dati_5[1] ), .DI0(\wb_dati_5[0] ), .CE(N_126_i), + .CLK(RCLK_c), .F0(\wb_dati_5[0] ), .Q0(\wb_dati[0] ), .F1(\wb_dati_5[1] ), + .Q1(\wb_dati[1] )); + SLICE_53 SLICE_53( .D1(\wb_dati_5_1_iv_0_0_a2_1[3] ), + .C1(\wb_dati_5_1_iv_0_0_1[3] ), .B1(\wb_dati_5_1_iv_0_0_0[3] ), + .A1(\wb_dati_5_1_iv_0_a2_13[3] ), .C0(\wb_dati[1] ), + .B0(\wb_dati_5_1_iv_0_0_o2[5] ), .A0(InitReady), .DI1(\wb_dati_5[3] ), + .DI0(\wb_dati_5[2] ), .CE(N_126_i), .CLK(RCLK_c), .F0(\wb_dati_5[2] ), + .Q0(\wb_dati[2] ), .F1(\wb_dati_5[3] ), .Q1(\wb_dati[3] )); + SLICE_54 SLICE_54( .C1(\wb_dati[4] ), .B1(\wb_dati_5_1_iv_0_0_o2[5] ), + .A1(InitReady), .D0(\wb_dati_5_1_iv_0_1_0[4] ), + .C0(\wb_dati_5_1_iv_0_0_1[4] ), .B0(\FS_RNIGOCT[12] ), .A0(\FS[9] ), + .DI1(\wb_dati_5[5] ), .DI0(\wb_dati_5[4] ), .CE(N_126_i), .CLK(RCLK_c), + .F0(\wb_dati_5[4] ), .Q0(\wb_dati[4] ), .F1(\wb_dati_5[5] ), + .Q1(\wb_dati[5] )); + SLICE_55 SLICE_55( .D1(\wb_dati_5_1_iv_0_1[7] ), + .C1(\wb_dati_5_1_iv_0_a2_5[7] ), .B1(\wb_dati_5_1_iv_0_a2_13[3] ), + .A1(\wb_dati_5_1_iv_0_RNO[7] ), .D0(\wb_dati_5_1_iv_0_0_1[6] ), + .C0(\FS_RNIGOCT[12] ), .B0(\FS_RNIS637[9] ), .A0(\FS[11] ), + .DI1(\wb_dati_5[7] ), .DI0(\wb_dati_5[6] ), .CE(N_126_i), .CLK(RCLK_c), + .F0(\wb_dati_5[6] ), .Q0(\wb_dati[6] ), .F1(\wb_dati_5[7] ), + .Q1(\wb_dati[7] )); + SLICE_56 SLICE_56( .D1(\FS[12] ), .C1(\FS[13] ), .B1(\FS[14] ), + .A1(un1_wb_rst14_2_0_o2), .C0(wb_req), .B0(un1_wb_rst14_2_i), .A0(N_122_i), + .DI0(wb_reqe_0), .LSR(wb_rst10), .CLK(RCLK_c), .F0(wb_reqe_0), .Q0(wb_req), + .F1(un1_wb_rst14_2_i)); + SLICE_57 SLICE_57( .D1(PHI2r3), .C1(PHI2r2), .B1(InitReady), .A1(CmdValid), + .C0(wb_rst_3), .B0(wb_rst), .A0(N_122_i), .DI0(wb_rste_0), .CLK(RCLK_c), + .F0(wb_rste_0), .Q0(wb_rst), .F1(N_122_i)); + SLICE_58 SLICE_58( .C1(InitReady), .B1(\FS[17] ), .A1(\FS[16] ), + .D0(wb_we_0_0_i_1), .C0(un1_wb_rst14_2_0_o2), .B0(InitReady), + .A0(CmdUFMData), .DI0(N_346_i), .CE(N_126_i), .LSR(wb_rst10), .CLK(RCLK_c), + .F0(N_346_i), .Q0(wb_we), .F1(un1_wb_rst14_2_0_o2)); + wb_dati_5_1_iv_0_0_o2_5__SLICE_59 \wb_dati_5_1_iv_0_0_o2[5]/SLICE_59 ( + .D1(\FS[12] ), .C1(\wb_dati_5_1_iv_0_o2[7] ), .B1(\FS_RNIHVJI[15] ), + .A1(\wb_dati_5_1_iv_0_o2_0_RNIMDJC1[4] ), .D0(\FS[13] ), + .C0(\wb_dati_5_1_iv_0_0_o2[3] ), .B0(\FS_RNIHVJI[15] ), + .A0(\wb_dati_5_1_iv_0_o2_0_RNIMDJC1[4] ), .M0(\FS[9] ), + .OFX0(\wb_dati_5_1_iv_0_0_o2[5] )); + wb_adr_5_i_0_1_0__SLICE_60 \wb_adr_5_i_0_1[0]/SLICE_60 ( .C1(\FS[13] ), + .B1(\wb_dati_5_1_iv_0_o2_0[7] ), .A1(\FS_RNIJO0F[12] ), .D0(InitReady), + .C0(\FS_RNI9Q57[12] ), .B0(\FS[9] ), .A0(\FS[10] ), .M0(\FS[11] ), + .OFX0(\wb_adr_5_i_0_1[0] )); + SLICE_61 SLICE_61( .D1(\FS[14] ), .C1(InitReady), .B1(N_313), + .A1(\FS_RNI9Q57[12] ), .D0(\FS[14] ), .C0(InitReady), .B0(\FS[13] ), + .A0(\wb_adr_5_i_0_o2[0] ), .F0(N_313), .F1(\wb_adr_5_i_0_0[0] )); + SLICE_62 SLICE_62( .D1(CO0), .C1(\S[1] ), .B1(InitReady), .A1(RASr2), + .D0(\S[1] ), .C0(Ready), .B0(un1_nRCAS_6_sqmuxa_i_o2), + .A0(IS_0_sqmuxa_0_o2), .F0(N_48), .F1(IS_0_sqmuxa_0_o2)); + SLICE_63 SLICE_63( .D1(N_466), .C1(\MAin_c[0] ), .B1(\Din_c[6] ), + .A1(\Din_c[3] ), .D0(N_483), .C0(N_457), .B0(\MAin_c[1] ), + .A0(\MAin_c[0] ), .F0(un1_CmdEnable20_0_0_0), .F1(N_483)); + SLICE_64 SLICE_64( .D1(InitReady), .C1(\FS[17] ), .B1(\FS[16] ), + .A1(\FS[15] ), .D0(\wb_dati_5_1_iv_0_a2_0_2[1] ), .C0(\wb_dati[0] ), + .B0(\FS_RNIHVJI[15] ), .A0(InitReady), .F0(\wb_dati_5_1_iv_0_0[1] ), + .F1(\FS_RNIHVJI[15] )); + SLICE_65 SLICE_65( .D1(\wb_dati_5_1_iv_0_a2_13[3] ), + .C1(\wb_dati_5_1_iv_0_0_o2[4] ), .B1(\FS[10] ), .A1(\FS[9] ), + .C0(\FS[13] ), .B0(\FS[11] ), .A0(\FS[10] ), + .F0(\wb_dati_5_1_iv_0_0_o2[4] ), .F1(\wb_dati_5_1_iv_0_1_0[4] )); + SLICE_66 SLICE_66( .C1(\FS[11] ), .B1(\FS[10] ), .A1(\FS[9] ), + .C0(\ufmefb/g0_0_a3_2 ), .B0(\FS_RNIF2MA[9] ), .A0(\FS_RNIHVJI[15] ), + .F0(N_4), .F1(\FS_RNIF2MA[9] )); + SLICE_67 SLICE_67( .D1(\wb_adr_5_i_0_1[0] ), .C1(\FS_RNIJO0F[12] ), + .B1(\wb_dati_5_1_iv_0_0_o2[4] ), .A1(\FS[9] ), .C0(\FS[14] ), + .B0(InitReady), .A0(\FS[12] ), .F0(\FS_RNIJO0F[12] ), + .F1(\wb_adr_5_i_0_3[0] )); + SLICE_68 SLICE_68( .D1(nRWE_s_i_a2_1_0), .C1(nRRAS_0_sqmuxa), .B1(RCKE_c), + .A1(RASr2), .C0(CO0), .B0(\S[1] ), .A0(Ready), .F0(nRRAS_0_sqmuxa), + .F1(nRWE_s_i_tz_0)); + SLICE_69 SLICE_69( .D1(nRCS_9_u_i_o3_0_0), .C1(RCKEEN_8_u_0_o3), .B1(FWEr), + .A1(CBR), .C0(CASr2), .B0(CO0), .A0(N_48), .F0(nRCS_9_u_i_o3_0_0), + .F1(nRCS_9_u_i_o3_0_2)); + SLICE_70 SLICE_70( .D1(wb_we_0_0_i_1_1), .C1(\FS_RNIOVGI[9] ), + .B1(\wb_adr_5_i_0_a2_6[0] ), .A1(\FS_RNI9Q57[12] ), .D0(\FS[9] ), + .C0(\FS[10] ), .B0(\FS[11] ), .A0(InitReady), .F0(\FS_RNIOVGI[9] ), + .F1(wb_we_0_0_i_1)); + SLICE_71 SLICE_71( .B1(\FS[10] ), .A1(\FS[9] ), .D0(\FS[12] ), .C0(\FS[11] ), + .B0(\FS_RNIS637[9] ), .A0(\wb_adr_5_i_3_0_a2_3[1] ), + .F0(\wb_adr_5_i_3_0_0[1] ), .F1(\FS_RNIS637[9] )); + SLICE_72 SLICE_72( .C1(\FS[9] ), .B1(\FS[10] ), .A1(\FS[11] ), .D0(\FS[12] ), + .C0(\FS[13] ), .B0(\wb_dati_5_1_iv_0_o2_0[4] ), .A0(\FS_RNI7U6M[14] ), + .F0(\wb_dati_5_1_iv_0_o2_0_RNIMDJC1[4] ), .F1(\wb_dati_5_1_iv_0_o2_0[4] )); + SLICE_73 SLICE_73( .C1(\wb_dati_5_1_iv_0_a2_5[7] ), + .B1(\wb_dati_5_1_iv_0_0_o2[4] ), .A1(\FS[14] ), .D0(\FS[9] ), + .C0(\FS_RNIHVJI[15] ), .B0(\FS[12] ), .A0(\wb_dati_5_1_iv_0_o2[7] ), + .F0(\wb_dati_5_1_iv_0_1_RNO[7] ), .F1(\wb_dati_5_1_iv_0_o2[7] )); + SLICE_74 SLICE_74( .D1(\FS_RNIHVJI[15] ), .C1(\FS[14] ), .B1(\FS[13] ), + .A1(\FS[12] ), .D0(\FS[9] ), .C0(\FS[10] ), .B0(\FS[11] ), + .A0(\FS_RNIGOCT[12] ), .F0(\wb_dati_5_1_iv_0_RNO[7] ), + .F1(\FS_RNIGOCT[12] )); + SLICE_75 SLICE_75( .D1(m3_0_a2_0), .C1(Ready), .B1(CO0), .A1(CBR_fast), + .D0(nRWE_s_i_tz_0), .C0(N_142), .B0(N_141), .A0(nRCAS_0_sqmuxa_1), + .F0(N_252_i), .F1(nRCAS_0_sqmuxa_1)); + SLICE_76 SLICE_76( .C1(N_482), .B1(N_457), .A1(\MAin_c[1] ), + .D0(un1_CmdEnable20_0_0_a2_1_1), .C0(un1_CmdEnable20_0_0_0), .B0(N_367), + .A0(C1Submitted), .M1(nCCAS_c_i), .M0(nCCAS_c_i), .CLK(nCRAS_c), + .F0(un1_CmdEnable20_i), .Q0(CBR), .F1(un1_CmdEnable20_0_0_a2_1_1), + .Q1(CBR_fast)); + SLICE_77 SLICE_77( .D1(\Din_c[3] ), .C1(\Din_c[5] ), .B1(\Din_c[4] ), + .A1(N_353), .B0(XOR8MEG18), .A0(N_461), .M0(CASr2), .CLK(RCLK_c), + .F0(CmdUFMData_1_sqmuxa), .Q0(CASr3), .F1(N_461)); + SLICE_78 SLICE_78( .B1(FWEr), .A1(CO0), .D0(nRCS_9_u_i_0), .C0(N_251_i_1), + .B0(N_142), .A0(N_141), .F0(N_37_i), .F1(N_251_i_1)); + SLICE_79 SLICE_79( .B1(Ready), .A1(IS_0_sqmuxa_0_o2), .D0(IS_0_sqmuxa_0_o3), + .C0(\IS[3] ), .B0(\IS[2] ), .A0(\IS[1] ), .F0(RA10s_i), + .F1(IS_0_sqmuxa_0_o3)); + SLICE_80 SLICE_80( .D1(\Bank[6] ), .C1(\Bank[5] ), .B1(\Bank[3] ), + .A1(\Bank[2] ), .D0(un1_CmdEnable20_0_0_o2_11), + .C0(un1_CmdEnable20_0_0_o2_10), .B0(\Bank[4] ), .A0(\Bank[0] ), .F0(N_367), + .F1(un1_CmdEnable20_0_0_o2_11)); + SLICE_81 SLICE_81( .D1(\wb_dati_5_1_iv_0_a2_12[3] ), + .C1(\wb_dati_5_1_iv_0_a2_7[4] ), .B1(\wb_dati_5_1_iv_0_a2_6[4] ), + .A1(\FS[10] ), .D0(\wb_dati[5] ), .C0(\wb_dati_5_1_iv_0_0_a2[6] ), + .B0(\wb_dati_5_1_iv_0_a2_2[4] ), .A0(InitReady), + .F0(\wb_dati_5_1_iv_0_0_1[6] ), .F1(\wb_dati_5_1_iv_0_a2_2[4] )); + SLICE_82 SLICE_82( .D1(\wb_dati_5_1_iv_0_a2_0_0[7] ), .C1(\FS_RNIHVJI[15] ), + .B1(\FS[10] ), .A1(\FS[9] ), .D0(\wb_dati[6] ), + .C0(\wb_dati_5_1_iv_0_1_RNO[7] ), .B0(\wb_dati_5_1_iv_0_a2_0[7] ), + .A0(InitReady), .F0(\wb_dati_5_1_iv_0_1[7] ), + .F1(\wb_dati_5_1_iv_0_a2_0[7] )); + SLICE_83 SLICE_83( .C1(\IS[3] ), .B1(\IS[2] ), .A1(\IS[1] ), + .D0(nRCS_9_u_i_0_0), .C0(un1_nRCAS_6_sqmuxa_i_o2), .B0(IS_0_sqmuxa_0_o2), + .A0(\IS[0] ), .F0(nRCS_9_u_i_0), .F1(un1_nRCAS_6_sqmuxa_i_o2)); + SLICE_84 SLICE_84( .C1(\FS[14] ), .B1(\FS_RNIHVJI[15] ), .A1(\FS[12] ), + .D0(\wb_dati_5_1_iv_0_a2_13[3] ), .C0(\wb_dati_5_1_iv_0_o2_0[7] ), + .B0(\FS[13] ), .A0(\FS[11] ), .F0(\wb_dati_5_1_iv_0_0_a2[6] ), + .F1(\wb_dati_5_1_iv_0_a2_13[3] )); + SLICE_85 SLICE_85( .D1(\FS[14] ), .C1(\FS[12] ), .B1(\FS[11] ), + .A1(\FS[10] ), .D0(\wb_dati_5_1_iv_0_0[1] ), + .C0(\wb_dati_5_1_iv_0_a2_12[3] ), .B0(\wb_dati_5_1_iv_0_0_o2[3] ), + .A0(\FS[13] ), .F0(\wb_dati_5_1_iv_0_1[1] ), + .F1(\wb_dati_5_1_iv_0_0_o2[3] )); + SLICE_86 SLICE_86( .D1(\FS_RNI7U6M[14] ), .C1(\FS_RNIS637[9] ), + .B1(\FS[12] ), .A1(\FS[11] ), .C0(\wb_dati[2] ), + .B0(\wb_dati_5_1_iv_0_a2_7[3] ), .A0(InitReady), + .F0(\wb_dati_5_1_iv_0_0_0[3] ), .F1(\wb_dati_5_1_iv_0_a2_7[3] )); + SLICE_87 SLICE_87( .B1(\FS_RNIHVJI[15] ), .A1(\FS[9] ), + .D0(\wb_dati_5_1_iv_0_a2_12[3] ), .C0(\wb_dati_5_1_iv_0_a2_5[3] ), + .B0(\wb_dati_5_1_iv_0_0_o2[3] ), .A0(\FS[13] ), + .F0(\wb_dati_5_1_iv_0_0_1[3] ), .F1(\wb_dati_5_1_iv_0_a2_12[3] )); + SLICE_88 SLICE_88( .B1(\FS_RNIHVJI[15] ), .A1(\FS[14] ), + .D0(\wb_dati_5_1_iv_0_a2_11[3] ), .C0(\FS_RNI7U6M[14] ), + .B0(\FS_RNIS637[9] ), .A0(\FS[11] ), .F0(\wb_dati_5_1_iv_0_a2_5[3] ), + .F1(\FS_RNI7U6M[14] )); + SLICE_89 SLICE_89( .C1(wb_req), .B1(N_99_1), .A1(\FS[0] ), + .D0(wb_cyc_stb_2_sqmuxa_i_0_0_a2_0), .C0(wb_ack), .B0(\FS_RNIHVJI[15] ), + .A0(N_99_2), .F0(wb_cyc_stb_2_sqmuxa_i_0_0), + .F1(wb_cyc_stb_2_sqmuxa_i_0_0_a2_0)); + SLICE_90 SLICE_90( .D1(nFWE_c), .C1(\MAin_c[7] ), .B1(\MAin_c[6] ), + .A1(\MAin_c[4] ), .D0(un1_CmdEnable20_0_0_o2_4), + .C0(un1_CmdEnable20_0_0_o2_3), .B0(\Bank[7] ), .A0(\Bank[1] ), + .F0(un1_CmdEnable20_0_0_o2_10), .F1(un1_CmdEnable20_0_0_o2_4)); + SLICE_91 SLICE_91( .C1(\FS[17] ), .B1(\FS[16] ), .A1(\FS[15] ), + .D0(\wb_dati[7] ), .C0(\wb_adr_5_i_0_0[0] ), .B0(\FS_RNI82PA[15] ), + .A0(InitReady), .F0(\wb_adr_5_i_0_2[0] ), .F1(\FS_RNI82PA[15] )); + SLICE_92 SLICE_92( .B1(\Din_c[5] ), .A1(\Din_c[3] ), .D0(N_442), + .C0(\MAin_c[0] ), .B0(\Din_c[6] ), .A0(\Din_c[2] ), .F0(N_482), .F1(N_442)); + SLICE_93 SLICE_93( .D1(\wb_dati_5_1_iv_0_a2_11[3] ), .C1(wb_we_0_0_i_a2_0), + .B1(\wb_dati_5_1_iv_0_o2_0[4] ), .A1(InitReady), + .D0(\wb_adr_5_i_0_a2_6[0] ), .C0(\FS_RNIS637[9] ), .B0(\FS[13] ), + .A0(\FS[12] ), .F0(wb_we_0_0_i_a2_0), .F1(wb_we_0_0_i_1_1)); + SLICE_94 SLICE_94( .B1(InitReady), .A1(\FS[14] ), + .D0(\wb_adr_5_i_3_0_a2_3[1] ), .C0(\FS[17] ), .B0(\FS[16] ), .A0(\FS[15] ), + .F0(wb_rst_3), .F1(\wb_adr_5_i_3_0_a2_3[1] )); + SLICE_95 SLICE_95( .B1(\FS[7] ), .A1(\FS[1] ), + .D0(wb_cyc_stb_2_sqmuxa_i_a2_2_0), .C0(\FS[5] ), .B0(\FS[4] ), + .A0(\FS[2] ), .F0(N_99_2), .F1(wb_cyc_stb_2_sqmuxa_i_a2_2_0)); + SLICE_96 SLICE_96( .B1(\Din_c[7] ), .A1(\Din_c[6] ), .D0(N_466), .C0(N_452), + .B0(N_353), .A0(\Din_c[3] ), .F0(XOR8MEG_3_u_0_0_a2_0_2), .F1(N_353)); + SLICE_97 SLICE_97( .B1(\FS[10] ), .A1(\FS[9] ), + .D0(\wb_dati_5_1_iv_0_a2_7[4] ), .C0(\wb_dati_5_1_iv_0_o2_0[7] ), + .B0(\FS[13] ), .A0(\FS[11] ), .F0(\wb_dati_5_1_iv_0_a2_0_2[1] ), + .F1(\wb_dati_5_1_iv_0_o2_0[7] )); + SLICE_98 SLICE_98( .B1(\FS[13] ), .A1(\FS[11] ), + .D0(\wb_dati_5_1_iv_0_a2_6[4] ), .C0(\FS[14] ), .B0(\FS[12] ), + .A0(\FS[10] ), .F0(\wb_dati_5_0_iv_0_a2_1[0] ), + .F1(\wb_dati_5_1_iv_0_a2_6[4] )); + SLICE_99 SLICE_99( .D1(\FS_RNI9Q57[12] ), .C1(InitReady3_0_a2_1_0), + .B1(\FS[14] ), .A1(\FS[11] ), .D0(\FS[17] ), .C0(\FS[16] ), .B0(\FS[15] ), + .A0(\FS[10] ), .F0(InitReady3_0_a2_1_0), .F1(InitReady3)); + SLICE_100 SLICE_100( .B1(PHI2r3), .A1(PHI2r2), .D0(InitReady), + .C0(G_4_0_a3_0), .B0(CmdValid_fast), .A0(CmdUFMShift), .F0(N_126_i), + .F1(G_4_0_a3_0)); + SLICE_101 SLICE_101( .D1(nRCS_9_u_i_o3_0_2), .C1(N_251_i_sx), + .B1(N_251_i_1_0), .A1(N_251_i_1), .C0(\S[1] ), .B0(nRCAS_0_sqmuxa_1), + .A0(N_48), .F0(N_251_i_sx), .F1(N_251_i)); + SLICE_102 SLICE_102( .D1(\FS[12] ), .C1(\FS[14] ), .B1(\FS[13] ), + .A1(\FS[11] ), .D0(wb_ack), .C0(\FS[14] ), .B0(\FS[13] ), .A0(\FS[12] ), + .F0(\ufmefb/g0_0_a3_2 ), .F1(\wb_dati_5_1_iv_0_a2_0_0[7] )); + SLICE_103 SLICE_103( .D1(\S[1] ), .C1(FWEr), .B1(CO0), .A1(CASr2), .D0(FWEr), + .C0(CO0), .B0(CASr3), .A0(CASr2), .F0(N_142), .F1(RCKEEN_8_u_1)); + SLICE_104 SLICE_104( .D1(\FS[13] ), .C1(\FS[11] ), .B1(\FS[10] ), + .A1(\FS[9] ), .C0(\FS[13] ), .B0(\FS[11] ), .A0(\FS[10] ), + .F0(\wb_dati_5_1_iv_0_a2_5[7] ), .F1(\wb_dati_5_1_iv_0_0_a2_1[3] )); + SLICE_105 SLICE_105( .B1(\FS[13] ), .A1(\FS[12] ), .D0(\FS_RNIOVGI[9] ), + .C0(\FS[14] ), .B0(\FS[13] ), .A0(\FS[12] ), .F0(\wb_adr_5_i_3_0_a2[1] ), + .F1(\FS_RNI9Q57[12] )); + SLICE_106 SLICE_106( .C1(\S[1] ), .B1(Ready), .A1(CBR), .D0(nCRAS_c), + .C0(Ready), .B0(LEDEN), .A0(CBR), .F0(LED_c), .F1(N_141)); + SLICE_107 SLICE_107( .B1(InitReady), .A1(\FS[14] ), .D0(\FS_RNIF2MA[9] ), + .C0(InitReady), .B0(\FS[14] ), .A0(\FS[13] ), + .F0(\wb_adr_5_i_3_0_a2_0[1] ), .F1(\wb_adr_5_i_0_a2_6[0] )); + SLICE_108 SLICE_108( .B1(nRowColSel), .A1(\MAin_c[9] ), .B0(nRowColSel), .A0(\MAin_c[9] ), .F0(RDQMH_c), .F1(RDQML_c)); - SLICE_112 SLICE_112( .D1(\Din_c[0] ), .C1(\Din_c[4] ), .B1(\Din_c[1] ), - .A1(\Din_c[7] ), .B0(\Din_c[4] ), .A0(\Din_c[0] ), - .F0(XOR8MEG_3_u_0_0_0_a2), .F1(N_518)); - SLICE_113 SLICE_113( .B1(N_214), .A1(\FS[14] ), .B0(N_214), .A0(\FS[9] ), - .F0(N_576), .F1(N_502)); - SLICE_114 SLICE_114( .C1(nRowColSel), .B1(\RowA[6] ), .A1(\MAin_c[6] ), - .C0(nFWE_c), .B0(\MAin_c[6] ), .A0(\MAin_c[4] ), - .F0(un1_CmdEnable20_0_0_o3_3), .F1(\RA_c[6] )); + SLICE_109 SLICE_109( .D1(\Din_c[0] ), .C1(\Din_c[4] ), .B1(\Din_c[1] ), + .A1(\Din_c[7] ), .B0(\Din_c[4] ), .A0(\Din_c[0] ), .F0(N_452), .F1(N_457)); + SLICE_110 SLICE_110( .B1(PHI2r3), .A1(PHI2r2), .C0(PHI2r3), .B0(PHI2r2), + .A0(CmdValid), .F0(un1_PHI2r3_i_li), .F1(g1_0)); + SLICE_111 SLICE_111( .C1(\wb_dato[0] ), .B1(InitReady), .A1(Cmdn8MEGEN), + .D0(\wb_dati[3] ), .C0(\wb_dati_5_1_iv_0_a2_2[4] ), + .B0(\wb_dati_5_1_iv_0_o2_0_RNIMDJC1[4] ), .A0(InitReady), + .F0(\wb_dati_5_1_iv_0_0_1[4] ), .F1(n8MEGENe_1_0)); + SLICE_112 SLICE_112( .C1(nRowColSel), .B1(\RowA[2] ), .A1(\MAin_c[2] ), + .C0(\MAin_c[5] ), .B0(\MAin_c[3] ), .A0(\MAin_c[2] ), + .F0(un1_CmdEnable20_0_0_o2_3), .F1(\RA_c[2] )); + SLICE_113 SLICE_113( .C1(nRowColSel), .B1(\RowA[8] ), .A1(\MAin_c[8] ), + .C0(nRowColSel), .B0(\RowA[0] ), .A0(\MAin_c[0] ), .F0(\RA_c[0] ), + .F1(\RA_c[8] )); + SLICE_114 SLICE_114( .C1(nRowColSel), .B1(\RowA[3] ), .A1(\MAin_c[3] ), + .C0(nRowColSel), .B0(\RowA[1] ), .A0(\MAin_c[1] ), .F0(\RA_c[1] ), + .F1(\RA_c[3] )); SLICE_115 SLICE_115( .C1(nRowColSel), .B1(\RowA[9] ), .A1(\MAin_c[9] ), - .C0(nRowColSel), .B0(\RowA[8] ), .A0(\MAin_c[8] ), .F0(\RA_c[8] ), + .C0(nRowColSel), .B0(\RowA[4] ), .A0(\MAin_c[4] ), .F0(\RA_c[4] ), .F1(\RA_c[9] )); SLICE_116 SLICE_116( .C1(nRowColSel), .B1(\RowA[7] ), .A1(\MAin_c[7] ), - .C0(nRowColSel), .B0(\RowA[0] ), .A0(\MAin_c[0] ), .F0(\RA_c[0] ), + .C0(nRowColSel), .B0(\RowA[5] ), .A0(\MAin_c[5] ), .F0(\RA_c[5] ), .F1(\RA_c[7] )); - SLICE_117 SLICE_117( .C1(nRowColSel), .B1(\RowA[5] ), .A1(\MAin_c[5] ), - .C0(nRowColSel), .B0(\RowA[1] ), .A0(\MAin_c[1] ), .F0(\RA_c[1] ), - .F1(\RA_c[5] )); - SLICE_118 SLICE_118( .C1(nRowColSel), .B1(\RowA[4] ), .A1(\MAin_c[4] ), - .C0(nRowColSel), .B0(\RowA[2] ), .A0(\MAin_c[2] ), .F0(\RA_c[2] ), - .F1(\RA_c[4] )); + SLICE_117 SLICE_117( .B1(\S[1] ), .A1(CO0), .B0(CO0), .A0(CASr2), + .F0(RCKEEN_8_u_0_o3), .F1(N_70_i)); + SLICE_118 SLICE_118( .B1(\FS[14] ), .A1(\FS[12] ), .B0(\FS[13] ), + .A0(\FS[12] ), .F0(\wb_dati_5_1_iv_0_a2_11[3] ), + .F1(\wb_dati_5_1_iv_0_a2_7[4] )); SLICE_119 SLICE_119( .D1(\Din_c[6] ), .C1(\Din_c[7] ), .B1(\Din_c[4] ), - .A1(\Din_c[5] ), .B0(\Din_c[5] ), .A0(\Din_c[2] ), .F0(N_539), - .F1(CmdLEDEN_4_u_i_0_a3_0_0)); + .A1(\Din_c[5] ), .B0(\Din_c[5] ), .A0(\Din_c[2] ), .F0(N_466), + .F1(CmdLEDEN_4_u_i_m2_i_a2_0_0)); SLICE_120 SLICE_120( .B1(Ready_fast), .A1(\CROW_c[1] ), .D0(n8MEGEN), .C0(XOR8MEG), .B0(Ready_fast), .A0(\Din_c[6] ), .F0(RA11d_0), .F1(\RBAd_0[1] )); - SLICE_121 SLICE_121( .B1(wb_req), .A1(\FS[0] ), .C0(\FS[8] ), .B0(\FS[5] ), - .A0(\FS[1] ), .F0(N_471_3), .F1(wb_cyc_stb_4_iv_0_a3_0_0)); - SLICE_122 SLICE_122( .C1(\wb_dato[0] ), .B1(InitReady), .A1(Cmdn8MEGEN), - .B0(PHI2r3), .A0(PHI2r2), .F0(g1_0), .F1(n8MEGENe_1_0)); - SLICE_123 SLICE_123( .B1(\FS[10] ), .A1(\FS[9] ), .C0(\FS[17] ), - .B0(\FS[16] ), .A0(\FS[15] ), .F0(InitReady3_0_a3_1), .F1(N_207)); + SLICE_121 SLICE_121( .B1(wb_req), .A1(\FS[0] ), .C0(\FS[8] ), .B0(\FS[6] ), + .A0(\FS[3] ), .F0(N_99_1), .F1(wb_cyc_stb_4_iv_0_0_a2_0_0)); + SLICE_122 SLICE_122( .C1(\wb_adr[0] ), .B1(\FS_RNI82PA[15] ), .A1(InitReady), + .B0(IS_0_sqmuxa_0_o2), .A0(Ready), .F0(N_261_i), .F1(N_216)); RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .IOLDO(\WRD[0] ), .PADDT(RD_1_i), .RD0(RD[0])); RD_0__MGIOL \RD[0]_MGIOL ( .IOLDO(\WRD[0] ), .OPOS(\Din_c[0] ), @@ -475,15 +527,18 @@ module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, RDQML RDQML_I( .PADDO(RDQML_c), .RDQML(RDQML)); RDQMH RDQMH_I( .PADDO(RDQMH_c), .RDQMH(RDQMH)); nRCAS nRCAS_I( .IOLDO(nRCAS_c), .nRCAS(nRCAS)); - nRCAS_MGIOL nRCAS_MGIOL( .IOLDO(nRCAS_c), .OPOS(N_248_i), .CLK(RCLK_c)); + nRCAS_MGIOL nRCAS_MGIOL( .IOLDO(nRCAS_c), .OPOS(N_251_i), .CLK(RCLK_c)); nRRAS nRRAS_I( .IOLDO(nRRAS_c), .nRRAS(nRRAS)); - nRRAS_MGIOL nRRAS_MGIOL( .IOLDO(nRRAS_c), .OPOS(N_246_i), .CLK(RCLK_c)); + nRRAS_MGIOL nRRAS_MGIOL( .IOLDO(nRRAS_c), .OPOS(N_32_i), .CLK(RCLK_c)); nRWE nRWE_I( .IOLDO(nRWE_c), .nRWE(nRWE)); - nRWE_MGIOL nRWE_MGIOL( .IOLDO(nRWE_c), .OPOS(N_49_i), .CLK(RCLK_c)); + nRWE_MGIOL nRWE_MGIOL( .IOLDO(nRWE_c), .OPOS(N_252_i), .CLK(RCLK_c)); RCKE RCKE_I( .PADDO(RCKE_c), .RCKE(RCKE)); + RCLKout RCLKout_I( .IOLDO(RCLKout_c), .RCLKout(RCLKout)); + RCLKout_MGIOL RCLKout_MGIOL( .IOLDO(RCLKout_c), .ONEG(VCC), .OPOS(GND), + .CLK(RCLK_c)); RCLK RCLK_I( .PADDI(RCLK_c), .RCLK(RCLK)); nRCS nRCS_I( .IOLDO(nRCS_c), .nRCS(nRCS)); - nRCS_MGIOL nRCS_MGIOL( .IOLDO(nRCS_c), .OPOS(N_247_i), .CLK(RCLK_c)); + nRCS_MGIOL nRCS_MGIOL( .IOLDO(nRCS_c), .OPOS(N_37_i), .CLK(RCLK_c)); RD_7_ \RD[7]_I ( .PADDI(\RD_in[7] ), .IOLDO(\WRD[7] ), .PADDT(RD_1_i), .RD7(RD[7])); RD_7__MGIOL \RD[7]_MGIOL ( .IOLDO(\WRD[7] ), .OPOS(\Din_c[7] ), @@ -1031,18 +1086,21 @@ module lut40006 ( input A, B, C, D, output Z ); ROM16X1A #(16'h5555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_16 ( input B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); +module SLICE_16 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, + F1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; - lut40007 nRowColSel_0_0_0_x2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40004 Ready_0_sqmuxa_0_a2_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40007 \S_RNO[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40008 \S_RNO[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre0009 \S[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + vmuxregsre0008 \S[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); @@ -1060,15 +1118,10 @@ endmodule module lut40007 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h6666) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40008 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module vmuxregsre0009 ( input D0, D1, SD, SP, CK, LSR, output Q ); +module vmuxregsre0008 ( input D0, D1, SD, SP, CK, LSR, output Q ); FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); defparam INST01.GSR = "DISABLED"; @@ -1078,9 +1131,9 @@ module SLICE_17 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly; - lut40004 un1_CmdEnable20_0_0_a2_0_RNI00E51( .A(A1), .B(B1), .C(C1), .D(D1), + lut40004 un1_CmdEnable20_0_0_a2_3_RNIJ3N91( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40010 CmdEnable_s( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40009 CmdEnable_s( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre CmdEnable( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1104,7 +1157,7 @@ module SLICE_17 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, endmodule -module lut40010 ( input A, B, C, D, output Z ); +module lut40009 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFFCA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule @@ -1113,8 +1166,8 @@ module SLICE_18 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; - lut40011 CmdLEDEN_4_u_i_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40012 CmdLEDEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40010 CmdLEDEN_4_u_i_m2_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40011 CmdLEDEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre CmdLEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); @@ -1138,25 +1191,47 @@ module SLICE_18 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, endmodule -module lut40011 ( input A, B, C, D, output Z ); +module lut40010 ( input A, B, C, D, output Z ); ROM16X1A #(16'h5D0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40012 ( input A, B, C, D, output Z ); +module lut40011 ( input A, B, C, D, output Z ); ROM16X1A #(16'h4545) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_20 ( input D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0 ); - wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly; +module SLICE_19 ( input A0, M0, CE, CLK, output F0, Q0 ); + wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; + lut40006 RA10_0io_RNO( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CmdUFMData( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_20 ( input D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; + + lut40012 GND( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); lut40013 CmdUFMShift_3_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre CmdUFMShift( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); specify (D0 => F0) = (0:0:0,0:0:0); @@ -1172,6 +1247,11 @@ module SLICE_20 ( input D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0 ); endmodule +module lut40012 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + module lut40013 ( input A, B, C, D, output Z ); ROM16X1A #(16'hB3A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); @@ -1181,7 +1261,7 @@ module SLICE_21 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; - lut40014 CmdUFMWrite_3_u_0_0_0_a3( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + lut40014 CmdUFMWrite_3_u_0_0_0_a2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40015 CmdUFMWrite_3_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); @@ -1219,7 +1299,7 @@ endmodule module SLICE_22 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly; - lut40016 CmdValid_2_i_o2_1_o3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40016 CmdValid_2_i_o2_0_o2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut4 CmdValid_r( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre CmdValid( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), @@ -1250,7 +1330,7 @@ endmodule module SLICE_23 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly; - lut40017 CmdUFMData_1_sqmuxa_0_a3_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40017 CmdUFMData_1_sqmuxa_0_a2_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut4 CmdValid_r_fast( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre CmdValid_fast( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), @@ -1282,7 +1362,7 @@ module SLICE_24 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; - lut40013 Cmdn8MEGEN_4_u_i_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40013 Cmdn8MEGEN_4_u_i_m2_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40018 Cmdn8MEGEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre Cmdn8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), @@ -1340,19 +1420,23 @@ module lut40019 ( input A, B, C, D, output Z ); ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_26 ( input B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); +module SLICE_26 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, + F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly; - lut40020 RCKEEN_8_u_0_0_o2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40020 nRRAS_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40021 \IS_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40021 \IS_RNO[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre \IS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); @@ -1365,12 +1449,12 @@ endmodule module lut40020 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h5051) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40021 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h9999) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hA9A9) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_27 ( input C1, B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, @@ -1379,7 +1463,7 @@ module SLICE_27 ( input C1, B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, lut40022 \IS_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40007 IS_n1_0_x2_0_x2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40023 IS_n1_0_x2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre \IS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1408,17 +1492,26 @@ module lut40022 ( input A, B, C, D, output Z ); ROM16X1A #(16'h7878) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_28 ( input A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; +module lut40023 ( input A, B, C, D, output Z ); - lut40006 RA10_0io_RNO( .A(A1), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40023 \IS_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + ROM16X1A #(16'h6666) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_28 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40024 nRWE_s_i_a2_1_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40025 \IS_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \IS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); @@ -1433,7 +1526,12 @@ module SLICE_28 ( input A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); endmodule -module lut40023 ( input A, B, C, D, output Z ); +module lut40024 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40025 ( input A, B, C, D, output Z ); ROM16X1A #(16'h6AAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule @@ -1441,7 +1539,7 @@ endmodule module SLICE_29 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly; - lut40024 InitReady3_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40026 \FS_RNIHVJI_0[15] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40019 InitReady_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre InitReady( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), @@ -1463,17 +1561,17 @@ module SLICE_29 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); endmodule -module lut40024 ( input A, B, C, D, output Z ); +module lut40026 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_30 ( input C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly; - lut40025 LEDEN_6_i_m2_i_m2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40027 LEDEN_6_i_m2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40026 LEDENe( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40028 LEDENe( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre LEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1493,21 +1591,22 @@ module SLICE_30 ( input C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); endmodule -module lut40025 ( input A, B, C, D, output Z ); +module lut40027 ( input A, B, C, D, output Z ); ROM16X1A #(16'hB8B8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40026 ( input A, B, C, D, output Z ); +module lut40028 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hE2E2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hCACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_31 ( input B0, A0, M1, M0, CLK, output F0, Q0, Q1 ); +module SLICE_31 ( input B0, A0, M1, M0, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; - lut40014 \RBAd[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40029 VCC( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); + lut40014 \RBAd[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre PHI2r3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1527,10 +1626,15 @@ module SLICE_31 ( input B0, A0, M1, M0, CLK, output F0, Q0, Q1 ); endmodule +module lut40029 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + module SLICE_32 ( input C1, B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; - lut40027 LED_pad_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40030 \un9_RA_i_m2_i_m2[6] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40006 RASr_RNO( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre RASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), @@ -1554,17 +1658,17 @@ module SLICE_32 ( input C1, B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); endmodule -module lut40027 ( input A, B, C, D, output Z ); +module lut40030 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFBFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hACAC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_33 ( input C1, B1, A1, B0, A0, M0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, M0_dly, CLK_dly; - lut40028 \un9_RA_i_m2_i_m2[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40031 \wb_adr_5_i_0_o2[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40014 CmdEnable_0_sqmuxa_0_a3_0_a3( .A(A0), .B(B0), .C(GNDI), .D(GNDI), + lut40014 CmdEnable_0_sqmuxa_0_a2_0_a2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre RASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); @@ -1584,17 +1688,17 @@ module SLICE_33 ( input C1, B1, A1, B0, A0, M0, CLK, output F0, Q0, F1 ); endmodule -module lut40028 ( input A, B, C, D, output Z ); +module lut40031 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hACAC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hB1B1) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_34 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire VCCI, GNDI, DI0_dly, CLK_dly; - lut40029 RCKEEN_8_u_0_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40030 RCKEEN_8_u_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40032 RCKEEN_8_u_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40033 RCKEEN_8_u( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre RCKEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1617,12 +1721,12 @@ module SLICE_34 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, endmodule -module lut40029 ( input A, B, C, D, output Z ); +module lut40032 ( input A, B, C, D, output Z ); ROM16X1A #(16'h5072) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40030 ( input A, B, C, D, output Z ); +module lut40033 ( input A, B, C, D, output Z ); ROM16X1A #(16'hDCCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule @@ -1632,7 +1736,7 @@ module SLICE_35 ( input B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); lut4 RASr2_RNI6PUF( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40031 RCKE_2_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40034 RCKE_2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre RCKE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1652,7 +1756,7 @@ module SLICE_35 ( input B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); endmodule -module lut40031 ( input A, B, C, D, output Z ); +module lut40034 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFE30) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule @@ -1661,9 +1765,9 @@ module SLICE_36 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly; - lut40032 Ready_0_sqmuxa_0_a2_4_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40035 Ready_0_sqmuxa_0_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40033 Ready_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40036 Ready_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre Ready( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1684,12 +1788,12 @@ module SLICE_36 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, endmodule -module lut40032 ( input A, B, C, D, output Z ); +module lut40035 ( input A, B, C, D, output Z ); ROM16X1A #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40033 ( input A, B, C, D, output Z ); +module lut40036 ( input A, B, C, D, output Z ); ROM16X1A #(16'hAEAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule @@ -1697,7 +1801,7 @@ endmodule module SLICE_37 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly; - lut40034 Ready_0_sqmuxa_0_a2_4_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40037 Ready_0_sqmuxa_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40019 Ready_fast_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre Ready_fast( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), @@ -1719,7 +1823,7 @@ module SLICE_37 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); endmodule -module lut40034 ( input A, B, C, D, output Z ); +module lut40037 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule @@ -1783,7 +1887,7 @@ endmodule module SLICE_40 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly; - lut40035 \RowAd[5] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40038 \RowAd[5] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40014 \RowAd[4] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre \RowA[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), @@ -1808,7 +1912,7 @@ module SLICE_40 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); endmodule -module lut40035 ( input A, B, C, D, output Z ); +module lut40038 ( input A, B, C, D, output Z ); ROM16X1A #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule @@ -1844,7 +1948,7 @@ endmodule module SLICE_42 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly; - lut40035 \RowAd[9] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40038 \RowAd[9] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40014 \RowAd[8] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre \RowA[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), @@ -1873,10 +1977,10 @@ module SLICE_43 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; - lut40004 Ready_0_sqmuxa_0_a2_4_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40019 \S_0_i_o2_i_o2[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40039 nRCS_9_u_i_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40019 \S_0_i_o3[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0009 \S[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + vmuxregsre0008 \S[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); @@ -1899,12 +2003,17 @@ module SLICE_43 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, endmodule +module lut40039 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + module SLICE_44 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly; - lut40036 XOR8MEG_3_u_0_0_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40037 XOR8MEG_3_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40040 XOR8MEG_3_u_0_0_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40041 XOR8MEG_3_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre XOR8MEG( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1929,12 +2038,12 @@ module SLICE_44 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output endmodule -module lut40036 ( input A, B, C, D, output Z ); +module lut40040 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFE00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40037 ( input A, B, C, D, output Z ); +module lut40041 ( input A, B, C, D, output Z ); ROM16X1A #(16'hF7F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule @@ -1943,8 +2052,8 @@ module SLICE_45 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly; - lut40038 CmdValid_RNIOOBE2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40039 n8MEGEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40042 CmdValid_RNIOOBE2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40043 n8MEGEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre n8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); @@ -1966,24 +2075,24 @@ module SLICE_45 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, endmodule -module lut40038 ( input A, B, C, D, output Z ); +module lut40042 ( input A, B, C, D, output Z ); ROM16X1A #(16'hF8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40039 ( input A, B, C, D, output Z ); +module lut40043 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h4E4E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h3A3A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_46 ( input B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; - lut40040 nRowColSel_0_0_0_a2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40044 nRowColSel_0_0_a2_1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40041 nRowColSel_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0009 nRowColSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + lut40045 nRowColSel_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0008 nRowColSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -2005,22 +2114,22 @@ module SLICE_46 ( input B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, endmodule -module lut40040 ( input A, B, C, D, output Z ); +module lut40044 ( input A, B, C, D, output Z ); ROM16X1A #(16'h4444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40041 ( input A, B, C, D, output Z ); +module lut40045 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hF400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hDC00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_47 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40042 \wb_adr_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40042 \wb_adr_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40024 \wb_adr_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40046 \wb_adr_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \wb_adr[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -2048,9 +2157,9 @@ module SLICE_47 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, endmodule -module lut40042 ( input A, B, C, D, output Z ); +module lut40046 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0007) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_48 ( input B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, @@ -2082,25 +2191,23 @@ module SLICE_48 ( input B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, endmodule -module SLICE_49 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; +module SLICE_49 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40043 \wb_adr_5_i_m2_i_m2[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40043 \wb_adr_5_i_m2_i_m2[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40031 \wb_adr_5_i_m2[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40031 \wb_adr_5_i_m2[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \wb_adr[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \wb_adr[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); @@ -2115,18 +2222,13 @@ module SLICE_49 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, endmodule -module lut40043 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCE02) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_50 ( input B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, - Q0, F1, Q1 ); +module SLICE_50 ( input B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, + F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40014 \wb_adr_5[7] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40043 \wb_adr_5_i_m2_i_m2[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40031 \wb_adr_5_i_m2[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \wb_adr[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -2136,7 +2238,6 @@ module SLICE_50 ( input B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); @@ -2155,9 +2256,9 @@ module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); wire VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; - lut40044 wb_cyc_stb_4_iv_0_a3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40038 wb_cyc_stb_4_iv_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0009 wb_cyc_stb( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + lut40004 wb_cyc_stb_4_iv_0_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40042 wb_cyc_stb_4_iv_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0008 wb_cyc_stb( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -2182,17 +2283,12 @@ module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, endmodule -module lut40044 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40045 \wb_dati_5_1_iv_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40046 \wb_dati_5_0_iv_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40047 \wb_dati_5_1_iv_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40048 \wb_dati_5_0_iv_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \wb_dati[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -2220,12 +2316,12 @@ module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, endmodule -module lut40045 ( input A, B, C, D, output Z ); +module lut40047 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFF10) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40046 ( input A, B, C, D, output Z ); +module lut40048 ( input A, B, C, D, output Z ); ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule @@ -2234,8 +2330,8 @@ module SLICE_53 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40047 \wb_dati_5_1_iv_i_i[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40048 \wb_dati_5_1_iv_0[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40049 \wb_dati_5_1_iv_0_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40050 \wb_dati_5_1_iv_0_0[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \wb_dati[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); @@ -2262,12 +2358,12 @@ module SLICE_53 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output endmodule -module lut40047 ( input A, B, C, D, output Z ); +module lut40049 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFEFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40048 ( input A, B, C, D, output Z ); +module lut40050 ( input A, B, C, D, output Z ); ROM16X1A #(16'hECEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule @@ -2276,9 +2372,9 @@ module SLICE_54 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40048 \wb_dati_5_1_iv_0[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40050 \wb_dati_5_1_iv_0_0[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40049 \wb_dati_5_1_iv_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40051 \wb_dati_5_1_iv_0_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \wb_dati[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -2304,17 +2400,17 @@ module SLICE_54 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output endmodule -module lut40049 ( input A, B, C, D, output Z ); +module lut40051 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFF4A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hF4FA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_55 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40050 \wb_dati_5_1_iv_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40045 \wb_dati_5_1_iv_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40052 \wb_dati_5_1_iv_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40047 \wb_dati_5_1_iv_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \wb_dati[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -2342,19 +2438,19 @@ module SLICE_55 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, endmodule -module lut40050 ( input A, B, C, D, output Z ); +module lut40052 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFFEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_56 ( input D1, C1, B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; - lut40051 wb_reqe_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40025 wb_reqe( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40053 wb_reqe_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40054 wb_reqe( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0009 wb_req( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + vmuxregsre0008 wb_req( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -2377,28 +2473,32 @@ module SLICE_56 ( input D1, C1, B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, endmodule -module lut40051 ( input A, B, C, D, output Z ); +module lut40053 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h1555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, - Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly; +module lut40054 ( input A, B, C, D, output Z ); - lut40051 \FS_RNIHVJI_0[16] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40052 wb_rste( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + ROM16X1A #(16'hD8D8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_57 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly; + + lut40055 un1_InitReady_4_i_0_a2_i( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40056 wb_rste( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre wb_rst( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); @@ -2410,23 +2510,28 @@ module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, endmodule -module lut40052 ( input A, B, C, D, output Z ); +module lut40055 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hD850) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h3B33) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_58 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, - output F0, Q0, F1 ); - wire VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; +module lut40056 ( input A, B, C, D, output Z ); - lut40043 \wb_adr_5_i_0_m2[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40053 wb_we_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0009 wb_we( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + ROM16X1A #(16'hE4E4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_58 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output + F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40057 un1_wb_rst14_2_0_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40058 wb_we_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0008 wb_we( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -2446,26 +2551,33 @@ module SLICE_58 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, endmodule -module lut40053 ( input A, B, C, D, output Z ); +module lut40057 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h008B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module wb_dati_5_1_iv_0_o3_5__SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, - M0, output OFX0 ); - wire - \wb_dati_5_1_iv_0_o3[5]/SLICE_59/wb_dati_5_1_iv_0_o3[5]/SLICE_59_K1_H1 , - \wb_dati_5_1_iv_0_o3[5]/SLICE_59/wb_dati_5_1_iv_0_o3[5]/GATE_H0 ; +module lut40058 ( input A, B, C, D, output Z ); - lut40054 \wb_dati_5_1_iv_0_o3[5]/SLICE_59_K1 ( .A(A1), .B(B1), .C(C1), + ROM16X1A #(16'h008F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module wb_dati_5_1_iv_0_0_o2_5__SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, + A0, M0, output OFX0 ); + wire + \wb_dati_5_1_iv_0_0_o2[5]/SLICE_59/wb_dati_5_1_iv_0_0_o2[5]/SLICE_59_K1_H1 + , + \wb_dati_5_1_iv_0_0_o2[5]/SLICE_59/wb_dati_5_1_iv_0_0_o2[5]/GATE_H0 ; + + lut40059 \wb_dati_5_1_iv_0_0_o2[5]/SLICE_59_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(\wb_dati_5_1_iv_0_o3[5]/SLICE_59/wb_dati_5_1_iv_0_o3[5]/SLICE_59_K1_H1 )); - lut40055 \wb_dati_5_1_iv_0_o3[5]/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(\wb_dati_5_1_iv_0_o3[5]/SLICE_59/wb_dati_5_1_iv_0_o3[5]/GATE_H0 )); - selmux2 \wb_dati_5_1_iv_0_o3[5]/SLICE_59_K0K1MUX ( - .D0(\wb_dati_5_1_iv_0_o3[5]/SLICE_59/wb_dati_5_1_iv_0_o3[5]/GATE_H0 ), - .D1(\wb_dati_5_1_iv_0_o3[5]/SLICE_59/wb_dati_5_1_iv_0_o3[5]/SLICE_59_K1_H1 ), - .SD(M0), .Z(OFX0)); + .Z(\wb_dati_5_1_iv_0_0_o2[5]/SLICE_59/wb_dati_5_1_iv_0_0_o2[5]/SLICE_59_K1_H1 ) + ); + lut40060 \wb_dati_5_1_iv_0_0_o2[5]/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\wb_dati_5_1_iv_0_0_o2[5]/SLICE_59/wb_dati_5_1_iv_0_0_o2[5]/GATE_H0 )); + selmux2 \wb_dati_5_1_iv_0_0_o2[5]/SLICE_59_K0K1MUX ( + .D0(\wb_dati_5_1_iv_0_0_o2[5]/SLICE_59/wb_dati_5_1_iv_0_0_o2[5]/GATE_H0 ), + .D1(\wb_dati_5_1_iv_0_0_o2[5]/SLICE_59/wb_dati_5_1_iv_0_0_o2[5]/SLICE_59_K1_H1 ) + , .SD(M0), .Z(OFX0)); specify (D1 => OFX0) = (0:0:0,0:0:0); @@ -2481,12 +2593,12 @@ module wb_dati_5_1_iv_0_o3_5__SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, endmodule -module lut40054 ( input A, B, C, D, output Z ); +module lut40059 ( input A, B, C, D, output Z ); ROM16X1A #(16'hAABA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40055 ( input A, B, C, D, output Z ); +module lut40060 ( input A, B, C, D, output Z ); ROM16X1A #(16'hBAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule @@ -2496,114 +2608,48 @@ module selmux2 ( input D0, D1, SD, output Z ); MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z)); endmodule -module SLICE_60 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module wb_adr_5_i_0_1_0__SLICE_60 ( input C1, B1, A1, D0, C0, B0, A0, M0, + output OFX0 ); + wire GNDI, \wb_adr_5_i_0_1[0]/SLICE_60/wb_adr_5_i_0_1[0]/SLICE_60_K1_H1 , + \wb_adr_5_i_0_1[0]/SLICE_60/wb_adr_5_i_0_1[0]/GATE_H0 ; - lut40056 CBR_fast_RNIQ31K1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40057 nRCAS_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40056 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40057 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCCCD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_61 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40058 un1_nRCAS_6_sqmuxa_i_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40018 nRCAS_r_i_0_o2_0_2_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40061 \wb_adr_5_i_0_1[0]/SLICE_60_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(\wb_adr_5_i_0_1[0]/SLICE_60/wb_adr_5_i_0_1[0]/SLICE_60_K1_H1 )); gnd DRIVEGND( .PWR0(GNDI)); + lut40062 \wb_adr_5_i_0_1[0]/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\wb_adr_5_i_0_1[0]/SLICE_60/wb_adr_5_i_0_1[0]/GATE_H0 )); + selmux2 \wb_adr_5_i_0_1[0]/SLICE_60_K0K1MUX ( + .D0(\wb_adr_5_i_0_1[0]/SLICE_60/wb_adr_5_i_0_1[0]/GATE_H0 ), + .D1(\wb_adr_5_i_0_1[0]/SLICE_60/wb_adr_5_i_0_1[0]/SLICE_60_K1_H1 ), + .SD(M0), .Z(OFX0)); specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule -module lut40058 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0FEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_62 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40044 \wb_adr_5_i_0_a2_1[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40059 wb_we_0_i_0_1_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40059 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hBABA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40060 wb_we_0_i_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40061 wb_we_0_i_0_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40060 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFDF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40061 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFF80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_64 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module lut40062 ( input A, B, C, D, output Z ); - lut40062 un1_CmdEnable20_0_0_a2_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40063 un1_CmdEnable20_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + ROM16X1A #(16'h0060) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_61 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40063 \wb_adr_5_i_0_2_RNO[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40004 \wb_adr_5_i_0_2_RNO_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -2618,20 +2664,15 @@ module SLICE_64 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); endmodule -module lut40062 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40063 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hF111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hCECC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40064 \wb_adr_5_i_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40065 \wb_adr_5_i_0_3[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40064 IS_0_sqmuxa_0_o2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40065 un1_nRCAS_6_sqmuxa_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -2648,18 +2689,18 @@ endmodule module lut40064 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hF6F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40065 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFF40) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0BFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_66 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40066 \FS_RNIHVJI[16] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40013 \wb_dati_5_1_iv_0_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40066 un1_CmdEnable20_0_0_a2_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40067 un1_CmdEnable20_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -2676,67 +2717,18 @@ endmodule module lut40066 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_67 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40067 \wb_dati_5_1_iv_0_0[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40068 \wb_adr_5_i_0_o2[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - + ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40067 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h1BBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hF111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40068 ( input A, B, C, D, output Z ); +module SLICE_64 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - ROM16X1A #(16'h1919) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_68 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40032 \FS_RNIF2MA[9] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40069 \ufmefb/EFBInst_0_RNISI191 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40069 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40070 \wb_dati_5_1_iv_0_a3_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40034 \wb_dati_5_1_iv_0_a3_0_RNO[1] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); + lut40068 \FS_RNIHVJI[15] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40013 \wb_dati_5_1_iv_0_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -2751,16 +2743,17 @@ module SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); endmodule -module lut40070 ( input A, B, C, D, output Z ); +module lut40068 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFFFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_70 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); +module SLICE_65 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40034 \wb_adr_5_i_0_a3_4[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40071 \FS_RNIJO0F[14] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40069 \wb_dati_5_1_iv_0_1_0[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40070 \wb_dati_5_1_iv_0_0_o2[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -2775,17 +2768,45 @@ module SLICE_70 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); endmodule -module lut40071 ( input A, B, C, D, output Z ); +module lut40069 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h1BBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_71 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); +module lut40070 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1919) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_66 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40072 \wb_dati_5_1_iv_i_i_1[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40073 \wb_dati_5_1_iv_i_i_1_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + lut40035 \FS_RNIF2MA[9] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 \ufmefb/EFBInst_0_RNISI191 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40071 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_67 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40072 \wb_adr_5_i_0_3[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40073 \FS_RNIJO0F[12] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -2802,19 +2823,19 @@ endmodule module lut40072 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hEAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFF40) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40073 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h2A2A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_72 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); +module SLICE_68 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40074 nRCS_9_u_i_0_o3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40075 Ready_RNICVV51( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40072 nRWE_s_i_tz_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40074 \S_RNICVV51[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -2831,19 +2852,37 @@ endmodule module lut40074 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFEAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_69 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40075 nRCAS_0io_RNO_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40018 nRCAS_0io_RNO_2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + endmodule module lut40075 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h1500) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_70 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40076 \wb_dati_5_1_iv_i_i_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40056 \wb_dati_5_1_iv_i_i_0_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); + lut40076 wb_we_0_0_i_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40077 \FS_RNIOVGI[9] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -2860,17 +2899,50 @@ endmodule module lut40076 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hA8FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_74 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module lut40077 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_71 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40077 un1_nRCAS_6_sqmuxa_i_0_0_o2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), + lut40078 \FS_RNIS637[9] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40079 \wb_adr_RNO_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40078 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40079 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h08AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_72 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40080 \wb_dati_5_1_iv_0_o2_0[4] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40078 un1_nRCAS_6_sqmuxa_i_0_0_o2_0_RNIQVER( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); + lut40004 \wb_dati_5_1_iv_0_o2_0_RNIMDJC1[4] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -2884,51 +2956,19 @@ module SLICE_74 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); endmodule -module lut40077 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40078 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hBFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_75 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40079 \wb_adr_5_i_0_a2_0[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40080 \wb_adr_RNO_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40079 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40080 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h08AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h6A6A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_76 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_73 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; - lut40081 \wb_dati_5_1_iv_0_o2[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40042 \wb_dati_5_1_iv_0_RNO_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40081 \wb_dati_5_1_iv_0_o2[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40024 \wb_dati_5_1_iv_0_1_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -2942,12 +2982,12 @@ endmodule module lut40081 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h1019) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hF4F4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_77 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_74 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40017 \FS_RNIGOCT[14] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40017 \FS_RNIGOCT[12] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40082 \wb_dati_5_1_iv_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify @@ -2968,10 +3008,10 @@ module lut40082 ( input A, B, C, D, output Z ); ROM16X1A #(16'h2022) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_78 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_75 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40083 nRCS_9_u_i_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40084 nRRAS_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40083 CBR_fast_RNIQ31K1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40084 nRWE_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -2988,38 +3028,19 @@ endmodule module lut40083 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0302) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40084 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0057) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hAABF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_79 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40020 nRCS_9_u_i_0_o2_1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40051 nRCS_9_u_i_0_o2_1_RNIL2K71_0( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module SLICE_80 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, +module SLICE_76 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; - lut40085 un1_CmdEnable20_0_0_a3_1_1( .A(A1), .B(B1), .C(C1), .D(GNDI), + lut40085 un1_CmdEnable20_0_0_a2_1_1( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40086 CmdEnable_s_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); @@ -3058,15 +3079,40 @@ module lut40086 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0203) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_81 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; +module SLICE_77 ( input D1, C1, B1, A1, B0, A0, M0, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, M0_dly, CLK_dly; - lut40087 RCKEEN_8_u_0_0_a2_2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40077 Cmdn8MEGEN_4_u_i_m2_i_a2_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40014 CmdUFMData_1_sqmuxa_0_a2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), + .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40088 nRWE_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_78 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40087 nRCS_9_u_i_a2_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40088 nRCS_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); @@ -3079,48 +3125,20 @@ endmodule module lut40087 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40088 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hAABF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0057) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_82 ( input D1, C1, B1, A1, B0, A0, M0, CE, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; - - lut40044 CmdLEDEN_4_u_i_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40014 CmdUFMData_1_sqmuxa_0_a3( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre CmdUFMData( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - endspecify - -endmodule - -module SLICE_83 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_79 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40079 nRCAS_r_i_0_a2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40019 IS_0_sqmuxa_0_o3( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40089 nRCS_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40089 RA10_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (B1 => F1) = (0:0:0,0:0:0); @@ -3135,13 +3153,13 @@ endmodule module lut40089 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0515) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFFEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_80 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40090 un1_CmdEnable20_0_0_o3_11( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40091 un1_CmdEnable20_0_0_o3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40090 un1_CmdEnable20_0_0_o2_11( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40064 un1_CmdEnable20_0_0_o2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -3158,18 +3176,13 @@ endmodule module lut40090 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h7FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hBFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40091 ( input A, B, C, D, output Z ); +module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - ROM16X1A #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40024 \wb_dati_5_1_iv_0_a3_0[6] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40047 \wb_dati_5_1_iv_0_1[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40091 \wb_dati_5_1_iv_0_a2_2[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40049 \wb_dati_5_1_iv_0_0_1[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -3184,10 +3197,15 @@ module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); endmodule -module SLICE_86 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module lut40091 ( input A, B, C, D, output Z ); - lut40092 \wb_dati_5_1_iv_0_a3[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40047 \wb_dati_5_1_iv_0_1[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_82 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40092 \wb_dati_5_1_iv_0_a2_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40049 \wb_dati_5_1_iv_0_1[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -3204,16 +3222,15 @@ endmodule module lut40092 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h9000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0600) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_87 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_83 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40071 \wb_dati_5_1_iv_i_i_a2_4[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); + lut40057 un1_nRCAS_6_sqmuxa_i_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40093 \wb_dati_5_1_iv_0_a3_3[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40093 nRCS_9_u_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -3229,16 +3246,18 @@ endmodule module lut40093 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFF32) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_88 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_84 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; - lut40050 nRCS_9_u_i_0_o2_1_RNIL2K71( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40094 RA10_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40073 \wb_dati_5_1_iv_0_a2_13[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40094 \wb_dati_5_1_iv_0_0_a2[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -3252,18 +3271,17 @@ endmodule module lut40094 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0900) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_89 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; +module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40008 \wb_dati_5_1_iv_0_o2_0[7] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40095 \wb_dati_5_1_iv_0_a3[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40095 \wb_dati_5_1_iv_0_0_o2[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40096 \wb_dati_5_1_iv_0_1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); @@ -3276,80 +3294,99 @@ endmodule module lut40095 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0900) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_90 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40042 nRWE_s_i_0_a3_1_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40065 nRWE_s_i_0_tz_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module SLICE_91 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40017 \wb_dati_5_1_iv_i_i_a3_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40047 \wb_dati_5_1_iv_0_1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module SLICE_92 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40096 wb_cyc_stb_2_sqmuxa_i_a3_0( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40097 wb_cyc_stb_2_sqmuxa_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - + ROM16X1A #(16'h0810) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40096 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hC4C4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFF80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_86 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40066 \wb_dati_5_1_iv_0_a2_7[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40050 \wb_dati_5_1_iv_0_0_0[3] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_87 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40087 \wb_dati_5_1_iv_0_a2_12[3] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \wb_dati_5_1_iv_0_0_1[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_88 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40087 \FS_RNI7U6M[14] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40091 \wb_dati_5_1_iv_0_a2_5[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_89 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40097 wb_cyc_stb_2_sqmuxa_i_0_0_a2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40049 wb_cyc_stb_2_sqmuxa_i_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + endmodule module lut40097 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFEFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hC4C4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_93 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_90 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40090 un1_CmdEnable20_0_0_o3_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40098 un1_CmdEnable20_0_0_o3_10( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40098 un1_CmdEnable20_0_0_o2_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40064 un1_CmdEnable20_0_0_o2_10( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -3366,13 +3403,61 @@ endmodule module lut40098 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFF7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_94 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_91 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; - lut40084 nRCAS_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40099 nRCAS_r_i_0_o2_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40099 \FS_RNI82PA[15] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40100 \wb_adr_5_i_0_2[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40099 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFDFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40100 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF4FE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_92 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40014 Cmdn8MEGEN_4_u_i_m2_i_a2_3( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40083 un1_CmdEnable20_0_0_a2_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_93 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40101 wb_we_0_0_i_1_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40102 wb_we_0_0_i_a2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -3387,18 +3472,47 @@ module SLICE_94 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); endmodule -module lut40099 ( input A, B, C, D, output Z ); +module lut40101 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h1500) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0B0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40102 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_94 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40087 \wb_adr_5_i_3_0_a2_3[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40103 wb_rst_3_0_a2_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40103 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_95 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; - lut4 \wb_dati_5_1_iv_i_i_a2_2[3] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + lut40087 wb_cyc_stb_2_sqmuxa_i_a2_2_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40100 wb_we_0_i_0_a3_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40103 wb_cyc_stb_2_sqmuxa_i_a2_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (B1 => F1) = (0:0:0,0:0:0); @@ -3411,17 +3525,12 @@ module SLICE_95 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); endmodule -module lut40100 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module SLICE_96 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; - lut4 \wb_adr_5_i_0_a2_1[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40019 XOR8MEG_3_u_0_0_o2_1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40101 \wb_adr_5_i_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40083 XOR8MEG_3_u_0_0_a2_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (B1 => F1) = (0:0:0,0:0:0); @@ -3434,17 +3543,14 @@ module SLICE_96 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); endmodule -module lut40101 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hC800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module SLICE_97 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40019 \FS_RNIH267[16] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40007 \wb_dati_5_1_iv_0_o2_0[7] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40043 \wb_adr_5_i_0_m2[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40066 \wb_dati_5_1_iv_0_a2_0_2[1] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); specify (B1 => F1) = (0:0:0,0:0:0); @@ -3460,95 +3566,10 @@ endmodule module SLICE_98 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40079 wb_cyc_stb_4_iv_0_a3_0_2_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + lut40014 \wb_dati_5_1_iv_0_a2_6[4] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40102 wb_cyc_stb_4_iv_0_a3_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40102 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_99 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40014 CmdLEDEN_4_u_i_0_a2_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40056 un1_CmdEnable20_0_0_a2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module SLICE_100 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40019 XOR8MEG_3_u_0_0_o2_1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40056 XOR8MEG_3_u_0_0_a3_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module SLICE_101 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40040 \wb_dati_5_1_iv_0_a2[6] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40103 \wb_dati_5_1_iv_0_a3_0_1[7] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40103 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h6000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_102 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40014 \wb_dati_5_0_iv_0_a2[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40104 \wb_dati_5_0_iv_0_a3_1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40104 \wb_dati_5_0_iv_0_a2_1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (B1 => F1) = (0:0:0,0:0:0); @@ -3566,14 +3587,14 @@ module lut40104 ( input A, B, C, D, output Z ); ROM16X1A #(16'h2800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_103 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; +module SLICE_99 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40040 PHI2r3_RNIFT0I_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40105 CmdValid_fast_RNI3K0H1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40004 InitReady3_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40105 InitReady3_0_a2_1_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); @@ -3586,18 +3607,17 @@ endmodule module lut40105 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h80FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h7FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_104 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_100 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40085 \FS_RNIVOOA[14] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40044 PHI2r3_RNIFT0I_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40004 \ufmefb/EFBInst_0_RNISGNB ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40106 CmdValid_fast_RNI3K0H1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify - (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); @@ -3608,35 +3628,16 @@ module SLICE_104 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); endmodule -module SLICE_105 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40106 \wb_adr_5_i_0_a3_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40069 wb_we_0_i_0_0_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - module lut40106 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0A08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h80FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_106 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); +module SLICE_101 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40107 \wb_adr_5_i_0_a3[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40108 \wb_adr_RNO_0[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40107 nRCAS_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40108 nRCAS_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -3653,26 +3654,22 @@ endmodule module lut40107 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hA300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h010F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40108 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hCDCD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_107 ( input C1, B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0, - F1 ); - wire GNDI, VCCI, M0_dly, CLK_dly; +module SLICE_102 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40108 wb_cyc_stb_4_iv_0_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40109 CmdValid_RNIS5A51( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre CASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); + lut40109 \wb_dati_5_1_iv_0_a2_0_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40004 \ufmefb/EFBInst_0_RNISGNB ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -3680,23 +3677,19 @@ module SLICE_107 ( input C1, B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0, (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); endspecify endmodule module lut40109 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h3B33) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_108 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_103 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40110 RCKEEN_8_u_0_1_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40056 nRWE_s_i_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40110 RCKEEN_8_u_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40083 nRWE_s_i_a2_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -3716,12 +3709,13 @@ module lut40110 ( input A, B, C, D, output Z ); ROM16X1A #(16'h70CF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_109 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); +module SLICE_104 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40111 \wb_dati_5_1_iv_i_i_a3_1_1[3] ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40111 \wb_dati_5_1_iv_0_0_a2_1[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40112 \wb_adr_5_i_0_o2_0[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40071 \wb_dati_5_1_iv_0_a2_5[7] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -3741,18 +3735,37 @@ module lut40111 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0084) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40112 ( input A, B, C, D, output Z ); +module SLICE_105 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; - ROM16X1A #(16'hB1B1) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_110 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40113 \wb_adr_5_i_0_a3_0_2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40114 \wb_dati_5_1_iv_i_i_o2[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40014 \FS_RNI9Q57[12] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40112 \wb_adr_5_i_3_0_a2[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40112 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_106 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40113 RCKEEN_8_u_0_a2_2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40114 LED_pad_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -3766,20 +3779,43 @@ endmodule module lut40113 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40114 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0810) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFFBF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_111 ( input B1, A1, B0, A0, output F0, F1 ); +module SLICE_107 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40020 RDQML_0_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut4 \wb_adr_5_i_0_a2_6[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40035 RDQMH_pad_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40115 \wb_adr_5_i_3_0_a2_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40115 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0A08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_108 ( input B1, A1, B0, A0, output F0, F1 ); + wire GNDI; + + lut40078 RDQML_0_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40038 RDQMH_pad_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); specify (B1 => F1) = (0:0:0,0:0:0); @@ -3790,11 +3826,11 @@ module SLICE_111 ( input B1, A1, B0, A0, output F0, F1 ); endmodule -module SLICE_112 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); +module SLICE_109 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); wire GNDI; - lut40034 un1_CmdEnable20_0_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut4 XOR8MEG_3_u_0_0_0_a2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40037 un1_CmdEnable20_0_0_a2_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut4 XOR8MEG_3_u_0_0_a2_1( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -3808,29 +3844,58 @@ module SLICE_112 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); endmodule -module SLICE_113 ( input B1, A1, B0, A0, output F0, F1 ); +module SLICE_110 ( input B1, A1, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40079 \FS_RNI7U6M[14] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40044 PHI2r3_RNIFT0I( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40079 \wb_dati_5_1_iv_i_i_a2_3[3] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); + lut40116 wb_cyc_stb_4_iv_0_0_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule -module SLICE_114 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); +module lut40116 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_111 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40028 \un9_RA_i_m2_i_m2[6] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40117 n8MEGEN_RNO_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40115 un1_CmdEnable20_0_0_o3_3( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40049 \wb_dati_5_1_iv_0_0_1[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40117 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4747) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_112 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40030 \un9_RA_i_m2_i_m2[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40035 un1_CmdEnable20_0_0_o2_3( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -3843,17 +3908,48 @@ module SLICE_114 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); endmodule -module lut40115 ( input A, B, C, D, output Z ); +module SLICE_113 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40030 \un9_RA[8] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40030 \un9_RA_i_m2_i_m2[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_114 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40030 \un9_RA_i_m2_i_m2[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40030 \un9_RA_i_m2_i_m2[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify - ROM16X1A #(16'hF7F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_115 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40028 \un9_RA_i_m2_i_m2[9] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40030 \un9_RA_i_m2_i_m2[9] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40028 \un9_RA[8] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40030 \un9_RA_i_m2_i_m2[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -3869,9 +3965,9 @@ endmodule module SLICE_116 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40028 \un9_RA_i_m2_i_m2[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40030 \un9_RA_i_m2_i_m2[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40028 \un9_RA_i_m2_i_m2[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40030 \un9_RA_i_m2_i_m2[5] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -3884,36 +3980,33 @@ module SLICE_116 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); endmodule -module SLICE_117 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); +module SLICE_117 ( input B1, A1, B0, A0, output F0, F1 ); wire GNDI; - lut40028 \un9_RA_i_m2_i_m2[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40023 nRowColSel_0_0_x2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40028 \un9_RA_i_m2_i_m2[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40078 RCKEEN_8_u_0_o3( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); specify - (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule -module SLICE_118 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); +module SLICE_118 ( input B1, A1, B0, A0, output F0, F1 ); wire GNDI; - lut40028 \un9_RA_i_m2_i_m2[4] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40044 \wb_dati_5_1_iv_0_a2_7[4] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40028 \un9_RA_i_m2_i_m2[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut4 \wb_dati_5_1_iv_0_a2_11[3] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); specify - (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); endspecify @@ -3923,8 +4016,8 @@ endmodule module SLICE_119 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); wire GNDI; - lut40116 CmdLEDEN_4_u_i_0_a3_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40079 XOR8MEG_3_u_0_0_a2_0( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40118 CmdLEDEN_4_u_i_m2_i_a2_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40087 XOR8MEG_3_u_0_0_a2_2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -3938,7 +4031,7 @@ module SLICE_119 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); endmodule -module lut40116 ( input A, B, C, D, output Z ); +module lut40118 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule @@ -3948,7 +4041,7 @@ module SLICE_120 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); lut40014 \RBAd[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40117 RA11d( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40119 RA11d( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (B1 => F1) = (0:0:0,0:0:0); @@ -3961,7 +4054,7 @@ module SLICE_120 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); endmodule -module lut40117 ( input A, B, C, D, output Z ); +module lut40119 ( input A, B, C, D, output Z ); ROM16X1A #(16'hC048) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule @@ -3969,10 +4062,11 @@ endmodule module SLICE_121 ( input B1, A1, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40014 wb_cyc_stb_4_iv_0_a3_0_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + lut40014 wb_cyc_stb_4_iv_0_0_a2_0_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 wb_cyc_stb_4_iv_0_a3_0_3( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40073 wb_cyc_stb_2_sqmuxa_i_a2_1( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); specify (B1 => F1) = (0:0:0,0:0:0); @@ -3987,9 +4081,10 @@ endmodule module SLICE_122 ( input C1, B1, A1, B0, A0, output F0, F1 ); wire GNDI; - lut40118 n8MEGEN_RNO_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40031 \wb_adr_5_i_3_0_m2[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40040 PHI2r3_RNIFT0I( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40087 IS_0_sqmuxa_0_o2_RNIDJQJ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), + .Z(F0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -4001,28 +4096,6 @@ module SLICE_122 ( input C1, B1, A1, B0, A0, output F0, F1 ); endmodule -module lut40118 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4747) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_123 ( input B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40020 \wb_adr_5_i_0_o2[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40085 InitReady3_0_a3_1( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - module RD_0_ ( output PADDI, input IOLDO, PADDT, inout RD0 ); xo2iobuf \RD_pad[0] ( .I(IOLDO), .T(PADDT), .Z(PADDI), .PAD(RD0), .PADI(RD0)); @@ -4069,7 +4142,7 @@ endmodule module Dout_0_ ( input PADDO, output Dout0 ); - xo2iobuf0119 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0)); + xo2iobuf0120 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0)); specify (PADDO => Dout0) = (0:0:0,0:0:0); @@ -4077,14 +4150,14 @@ module Dout_0_ ( input PADDO, output Dout0 ); endmodule -module xo2iobuf0119 ( input I, output PAD ); +module xo2iobuf0120 ( input I, output PAD ); OB INST5( .I(I), .O(PAD)); endmodule module PHI2 ( output PADDI, input PHI2 ); - xo2iobuf0120 PHI2_pad( .Z(PADDI), .PAD(PHI2)); + xo2iobuf0121 PHI2_pad( .Z(PADDI), .PAD(PHI2)); specify (PHI2 => PADDI) = (0:0:0,0:0:0); @@ -4094,7 +4167,7 @@ module PHI2 ( output PADDI, input PHI2 ); endmodule -module xo2iobuf0120 ( output Z, input PAD ); +module xo2iobuf0121 ( output Z, input PAD ); IB INST1( .I(PAD), .O(Z)); endmodule @@ -4124,7 +4197,7 @@ endmodule module RDQML ( input PADDO, output RDQML ); - xo2iobuf0121 RDQML_pad( .I(PADDO), .PAD(RDQML)); + xo2iobuf0122 RDQML_pad( .I(PADDO), .PAD(RDQML)); specify (PADDO => RDQML) = (0:0:0,0:0:0); @@ -4132,14 +4205,14 @@ module RDQML ( input PADDO, output RDQML ); endmodule -module xo2iobuf0121 ( input I, output PAD ); +module xo2iobuf0122 ( input I, output PAD ); OB INST5( .I(I), .O(PAD)); endmodule module RDQMH ( input PADDO, output RDQMH ); - xo2iobuf0121 RDQMH_pad( .I(PADDO), .PAD(RDQMH)); + xo2iobuf0122 RDQMH_pad( .I(PADDO), .PAD(RDQMH)); specify (PADDO => RDQMH) = (0:0:0,0:0:0); @@ -4149,7 +4222,7 @@ endmodule module nRCAS ( input IOLDO, output nRCAS ); - xo2iobuf0121 nRCAS_pad( .I(IOLDO), .PAD(nRCAS)); + xo2iobuf0122 nRCAS_pad( .I(IOLDO), .PAD(nRCAS)); specify (IOLDO => nRCAS) = (0:0:0,0:0:0); @@ -4160,7 +4233,7 @@ endmodule module nRCAS_MGIOL ( output IOLDO, input OPOS, CLK ); wire VCCI, GNDI, OPOS_dly, CLK_dly; - mfflsre0122 nRCAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + mfflsre0123 nRCAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); @@ -4174,7 +4247,7 @@ module nRCAS_MGIOL ( output IOLDO, input OPOS, CLK ); endmodule -module mfflsre0122 ( input D0, SP, CK, LSR, output Q ); +module mfflsre0123 ( input D0, SP, CK, LSR, output Q ); FD1P3BX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q)); defparam INST01.GSR = "DISABLED"; @@ -4182,7 +4255,7 @@ endmodule module nRRAS ( input IOLDO, output nRRAS ); - xo2iobuf0121 nRRAS_pad( .I(IOLDO), .PAD(nRRAS)); + xo2iobuf0122 nRRAS_pad( .I(IOLDO), .PAD(nRRAS)); specify (IOLDO => nRRAS) = (0:0:0,0:0:0); @@ -4193,7 +4266,7 @@ endmodule module nRRAS_MGIOL ( output IOLDO, input OPOS, CLK ); wire VCCI, GNDI, OPOS_dly, CLK_dly; - mfflsre0122 nRRAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + mfflsre0123 nRRAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); @@ -4209,7 +4282,7 @@ endmodule module nRWE ( input IOLDO, output nRWE ); - xo2iobuf0121 nRWE_pad( .I(IOLDO), .PAD(nRWE)); + xo2iobuf0122 nRWE_pad( .I(IOLDO), .PAD(nRWE)); specify (IOLDO => nRWE) = (0:0:0,0:0:0); @@ -4220,7 +4293,7 @@ endmodule module nRWE_MGIOL ( output IOLDO, input OPOS, CLK ); wire VCCI, GNDI, OPOS_dly, CLK_dly; - mfflsre0122 nRWE_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + mfflsre0123 nRWE_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); @@ -4236,7 +4309,7 @@ endmodule module RCKE ( input PADDO, output RCKE ); - xo2iobuf0121 RCKE_pad( .I(PADDO), .PAD(RCKE)); + xo2iobuf0122 RCKE_pad( .I(PADDO), .PAD(RCKE)); specify (PADDO => RCKE) = (0:0:0,0:0:0); @@ -4244,9 +4317,47 @@ module RCKE ( input PADDO, output RCKE ); endmodule +module RCLKout ( input IOLDO, output RCLKout ); + + xo2iobuf0124 RCLKout_pad( .I(IOLDO), .PAD(RCLKout)); + + specify + (IOLDO => RCLKout) = (0:0:0,0:0:0); + endspecify + +endmodule + +module xo2iobuf0124 ( input I, output PAD ); + + OB INST5( .I(I), .O(PAD)); +endmodule + +module RCLKout_MGIOL ( output IOLDO, input ONEG, OPOS, CLK ); + wire GNDI, ONEG_dly, CLK_dly, OPOS_dly; + + xo2oddr rclk_oddr( .D0(OPOS_dly), .D1(ONEG_dly), .SCLK(CLK_dly), .RST(GNDI), + .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, ONEG, 0:0:0, 0:0:0,,,, CLK_dly, ONEG_dly); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module xo2oddr ( input D0, D1, SCLK, RST, output Q ); + + ODDRXE INST1( .D0(D0), .D1(D1), .SCLK(SCLK), .RST(RST), .Q(Q)); + defparam INST1.GSR = "DISABLED"; +endmodule + module RCLK ( output PADDI, input RCLK ); - xo2iobuf0120 RCLK_pad( .Z(PADDI), .PAD(RCLK)); + xo2iobuf0121 RCLK_pad( .Z(PADDI), .PAD(RCLK)); specify (RCLK => PADDI) = (0:0:0,0:0:0); @@ -4258,7 +4369,7 @@ endmodule module nRCS ( input IOLDO, output nRCS ); - xo2iobuf0121 nRCS_pad( .I(IOLDO), .PAD(nRCS)); + xo2iobuf0122 nRCS_pad( .I(IOLDO), .PAD(nRCS)); specify (IOLDO => nRCS) = (0:0:0,0:0:0); @@ -4269,7 +4380,7 @@ endmodule module nRCS_MGIOL ( output IOLDO, input OPOS, CLK ); wire VCCI, GNDI, OPOS_dly, CLK_dly; - mfflsre0122 nRCS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + mfflsre0123 nRCS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); @@ -4509,7 +4620,7 @@ endmodule module RA_11_ ( input IOLDO, output RA11 ); - xo2iobuf0121 \RA_pad[11] ( .I(IOLDO), .PAD(RA11)); + xo2iobuf0122 \RA_pad[11] ( .I(IOLDO), .PAD(RA11)); specify (IOLDO => RA11) = (0:0:0,0:0:0); @@ -4536,7 +4647,7 @@ endmodule module RA_10_ ( input IOLDO, output RA10 ); - xo2iobuf0121 \RA_pad[10] ( .I(IOLDO), .PAD(RA10)); + xo2iobuf0122 \RA_pad[10] ( .I(IOLDO), .PAD(RA10)); specify (IOLDO => RA10) = (0:0:0,0:0:0); @@ -4547,7 +4658,7 @@ endmodule module RA_10__MGIOL ( output IOLDO, input OPOS, LSR, CLK ); wire VCCI, OPOS_dly, CLK_dly, LSR_dly; - mfflsre0123 RA10_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), + mfflsre0125 RA10_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -4561,7 +4672,7 @@ module RA_10__MGIOL ( output IOLDO, input OPOS, LSR, CLK ); endmodule -module mfflsre0123 ( input D0, SP, CK, LSR, output Q ); +module mfflsre0125 ( input D0, SP, CK, LSR, output Q ); FD1P3JX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q)); defparam INST01.GSR = "DISABLED"; @@ -4569,7 +4680,7 @@ endmodule module RA_9_ ( input PADDO, output RA9 ); - xo2iobuf0121 \RA_pad[9] ( .I(PADDO), .PAD(RA9)); + xo2iobuf0122 \RA_pad[9] ( .I(PADDO), .PAD(RA9)); specify (PADDO => RA9) = (0:0:0,0:0:0); @@ -4579,7 +4690,7 @@ endmodule module RA_8_ ( input PADDO, output RA8 ); - xo2iobuf0121 \RA_pad[8] ( .I(PADDO), .PAD(RA8)); + xo2iobuf0122 \RA_pad[8] ( .I(PADDO), .PAD(RA8)); specify (PADDO => RA8) = (0:0:0,0:0:0); @@ -4589,7 +4700,7 @@ endmodule module RA_7_ ( input PADDO, output RA7 ); - xo2iobuf0121 \RA_pad[7] ( .I(PADDO), .PAD(RA7)); + xo2iobuf0122 \RA_pad[7] ( .I(PADDO), .PAD(RA7)); specify (PADDO => RA7) = (0:0:0,0:0:0); @@ -4599,7 +4710,7 @@ endmodule module RA_6_ ( input PADDO, output RA6 ); - xo2iobuf0121 \RA_pad[6] ( .I(PADDO), .PAD(RA6)); + xo2iobuf0122 \RA_pad[6] ( .I(PADDO), .PAD(RA6)); specify (PADDO => RA6) = (0:0:0,0:0:0); @@ -4609,7 +4720,7 @@ endmodule module RA_5_ ( input PADDO, output RA5 ); - xo2iobuf0121 \RA_pad[5] ( .I(PADDO), .PAD(RA5)); + xo2iobuf0122 \RA_pad[5] ( .I(PADDO), .PAD(RA5)); specify (PADDO => RA5) = (0:0:0,0:0:0); @@ -4619,7 +4730,7 @@ endmodule module RA_4_ ( input PADDO, output RA4 ); - xo2iobuf0121 \RA_pad[4] ( .I(PADDO), .PAD(RA4)); + xo2iobuf0122 \RA_pad[4] ( .I(PADDO), .PAD(RA4)); specify (PADDO => RA4) = (0:0:0,0:0:0); @@ -4629,7 +4740,7 @@ endmodule module RA_3_ ( input PADDO, output RA3 ); - xo2iobuf0121 \RA_pad[3] ( .I(PADDO), .PAD(RA3)); + xo2iobuf0122 \RA_pad[3] ( .I(PADDO), .PAD(RA3)); specify (PADDO => RA3) = (0:0:0,0:0:0); @@ -4639,7 +4750,7 @@ endmodule module RA_2_ ( input PADDO, output RA2 ); - xo2iobuf0121 \RA_pad[2] ( .I(PADDO), .PAD(RA2)); + xo2iobuf0122 \RA_pad[2] ( .I(PADDO), .PAD(RA2)); specify (PADDO => RA2) = (0:0:0,0:0:0); @@ -4649,7 +4760,7 @@ endmodule module RA_1_ ( input PADDO, output RA1 ); - xo2iobuf0121 \RA_pad[1] ( .I(PADDO), .PAD(RA1)); + xo2iobuf0122 \RA_pad[1] ( .I(PADDO), .PAD(RA1)); specify (PADDO => RA1) = (0:0:0,0:0:0); @@ -4659,7 +4770,7 @@ endmodule module RA_0_ ( input PADDO, output RA0 ); - xo2iobuf0121 \RA_pad[0] ( .I(PADDO), .PAD(RA0)); + xo2iobuf0122 \RA_pad[0] ( .I(PADDO), .PAD(RA0)); specify (PADDO => RA0) = (0:0:0,0:0:0); @@ -4669,7 +4780,7 @@ endmodule module RBA_1_ ( input IOLDO, output RBA1 ); - xo2iobuf0121 \RBA_pad[1] ( .I(IOLDO), .PAD(RBA1)); + xo2iobuf0122 \RBA_pad[1] ( .I(IOLDO), .PAD(RBA1)); specify (IOLDO => RBA1) = (0:0:0,0:0:0); @@ -4697,7 +4808,7 @@ endmodule module RBA_0_ ( input IOLDO, output RBA0 ); - xo2iobuf0121 \RBA_pad[0] ( .I(IOLDO), .PAD(RBA0)); + xo2iobuf0122 \RBA_pad[0] ( .I(IOLDO), .PAD(RBA0)); specify (IOLDO => RBA0) = (0:0:0,0:0:0); @@ -4725,7 +4836,7 @@ endmodule module LED ( input PADDO, output LED ); - xo2iobuf0124 LED_pad( .I(PADDO), .PAD(LED)); + xo2iobuf0126 LED_pad( .I(PADDO), .PAD(LED)); specify (PADDO => LED) = (0:0:0,0:0:0); @@ -4733,14 +4844,14 @@ module LED ( input PADDO, output LED ); endmodule -module xo2iobuf0124 ( input I, output PAD ); +module xo2iobuf0126 ( input I, output PAD ); OB INST5( .I(I), .O(PAD)); endmodule module nFWE ( output PADDI, input nFWE ); - xo2iobuf0120 nFWE_pad( .Z(PADDI), .PAD(nFWE)); + xo2iobuf0121 nFWE_pad( .Z(PADDI), .PAD(nFWE)); specify (nFWE => PADDI) = (0:0:0,0:0:0); @@ -4752,7 +4863,7 @@ endmodule module nCRAS ( output PADDI, input nCRAS ); - xo2iobuf0120 nCRAS_pad( .Z(PADDI), .PAD(nCRAS)); + xo2iobuf0121 nCRAS_pad( .Z(PADDI), .PAD(nCRAS)); specify (nCRAS => PADDI) = (0:0:0,0:0:0); @@ -4764,7 +4875,7 @@ endmodule module nCCAS ( output PADDI, input nCCAS ); - xo2iobuf0120 nCCAS_pad( .Z(PADDI), .PAD(nCCAS)); + xo2iobuf0121 nCCAS_pad( .Z(PADDI), .PAD(nCCAS)); specify (nCCAS => PADDI) = (0:0:0,0:0:0); @@ -4776,7 +4887,7 @@ endmodule module Dout_7_ ( input PADDO, output Dout7 ); - xo2iobuf0119 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7)); + xo2iobuf0120 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7)); specify (PADDO => Dout7) = (0:0:0,0:0:0); @@ -4786,7 +4897,7 @@ endmodule module Dout_6_ ( input PADDO, output Dout6 ); - xo2iobuf0119 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6)); + xo2iobuf0120 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6)); specify (PADDO => Dout6) = (0:0:0,0:0:0); @@ -4796,7 +4907,7 @@ endmodule module Dout_5_ ( input PADDO, output Dout5 ); - xo2iobuf0119 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5)); + xo2iobuf0120 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5)); specify (PADDO => Dout5) = (0:0:0,0:0:0); @@ -4806,7 +4917,7 @@ endmodule module Dout_4_ ( input PADDO, output Dout4 ); - xo2iobuf0119 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4)); + xo2iobuf0120 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4)); specify (PADDO => Dout4) = (0:0:0,0:0:0); @@ -4816,7 +4927,7 @@ endmodule module Dout_3_ ( input PADDO, output Dout3 ); - xo2iobuf0119 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3)); + xo2iobuf0120 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3)); specify (PADDO => Dout3) = (0:0:0,0:0:0); @@ -4826,7 +4937,7 @@ endmodule module Dout_2_ ( input PADDO, output Dout2 ); - xo2iobuf0119 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2)); + xo2iobuf0120 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2)); specify (PADDO => Dout2) = (0:0:0,0:0:0); @@ -4836,7 +4947,7 @@ endmodule module Dout_1_ ( input PADDO, output Dout1 ); - xo2iobuf0119 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1)); + xo2iobuf0120 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1)); specify (PADDO => Dout1) = (0:0:0,0:0:0); @@ -4846,7 +4957,7 @@ endmodule module Din_7_ ( output PADDI, input Din7 ); - xo2iobuf0120 \Din_pad[7] ( .Z(PADDI), .PAD(Din7)); + xo2iobuf0121 \Din_pad[7] ( .Z(PADDI), .PAD(Din7)); specify (Din7 => PADDI) = (0:0:0,0:0:0); @@ -4875,7 +4986,7 @@ endmodule module Din_6_ ( output PADDI, input Din6 ); - xo2iobuf0120 \Din_pad[6] ( .Z(PADDI), .PAD(Din6)); + xo2iobuf0121 \Din_pad[6] ( .Z(PADDI), .PAD(Din6)); specify (Din6 => PADDI) = (0:0:0,0:0:0); @@ -4904,7 +5015,7 @@ endmodule module Din_5_ ( output PADDI, input Din5 ); - xo2iobuf0120 \Din_pad[5] ( .Z(PADDI), .PAD(Din5)); + xo2iobuf0121 \Din_pad[5] ( .Z(PADDI), .PAD(Din5)); specify (Din5 => PADDI) = (0:0:0,0:0:0); @@ -4933,7 +5044,7 @@ endmodule module Din_4_ ( output PADDI, input Din4 ); - xo2iobuf0120 \Din_pad[4] ( .Z(PADDI), .PAD(Din4)); + xo2iobuf0121 \Din_pad[4] ( .Z(PADDI), .PAD(Din4)); specify (Din4 => PADDI) = (0:0:0,0:0:0); @@ -4962,7 +5073,7 @@ endmodule module Din_3_ ( output PADDI, input Din3 ); - xo2iobuf0120 \Din_pad[3] ( .Z(PADDI), .PAD(Din3)); + xo2iobuf0121 \Din_pad[3] ( .Z(PADDI), .PAD(Din3)); specify (Din3 => PADDI) = (0:0:0,0:0:0); @@ -4991,7 +5102,7 @@ endmodule module Din_2_ ( output PADDI, input Din2 ); - xo2iobuf0120 \Din_pad[2] ( .Z(PADDI), .PAD(Din2)); + xo2iobuf0121 \Din_pad[2] ( .Z(PADDI), .PAD(Din2)); specify (Din2 => PADDI) = (0:0:0,0:0:0); @@ -5020,7 +5131,7 @@ endmodule module Din_1_ ( output PADDI, input Din1 ); - xo2iobuf0120 \Din_pad[1] ( .Z(PADDI), .PAD(Din1)); + xo2iobuf0121 \Din_pad[1] ( .Z(PADDI), .PAD(Din1)); specify (Din1 => PADDI) = (0:0:0,0:0:0); @@ -5049,7 +5160,7 @@ endmodule module Din_0_ ( output PADDI, input Din0 ); - xo2iobuf0120 \Din_pad[0] ( .Z(PADDI), .PAD(Din0)); + xo2iobuf0121 \Din_pad[0] ( .Z(PADDI), .PAD(Din0)); specify (Din0 => PADDI) = (0:0:0,0:0:0); @@ -5078,7 +5189,7 @@ endmodule module CROW_1_ ( output PADDI, input CROW1 ); - xo2iobuf0120 \CROW_pad[1] ( .Z(PADDI), .PAD(CROW1)); + xo2iobuf0121 \CROW_pad[1] ( .Z(PADDI), .PAD(CROW1)); specify (CROW1 => PADDI) = (0:0:0,0:0:0); @@ -5090,7 +5201,7 @@ endmodule module CROW_0_ ( output PADDI, input CROW0 ); - xo2iobuf0120 \CROW_pad[0] ( .Z(PADDI), .PAD(CROW0)); + xo2iobuf0121 \CROW_pad[0] ( .Z(PADDI), .PAD(CROW0)); specify (CROW0 => PADDI) = (0:0:0,0:0:0); @@ -5102,7 +5213,7 @@ endmodule module MAin_9_ ( output PADDI, input MAin9 ); - xo2iobuf0120 \MAin_pad[9] ( .Z(PADDI), .PAD(MAin9)); + xo2iobuf0121 \MAin_pad[9] ( .Z(PADDI), .PAD(MAin9)); specify (MAin9 => PADDI) = (0:0:0,0:0:0); @@ -5114,7 +5225,7 @@ endmodule module MAin_8_ ( output PADDI, input MAin8 ); - xo2iobuf0120 \MAin_pad[8] ( .Z(PADDI), .PAD(MAin8)); + xo2iobuf0121 \MAin_pad[8] ( .Z(PADDI), .PAD(MAin8)); specify (MAin8 => PADDI) = (0:0:0,0:0:0); @@ -5126,7 +5237,7 @@ endmodule module MAin_7_ ( output PADDI, input MAin7 ); - xo2iobuf0120 \MAin_pad[7] ( .Z(PADDI), .PAD(MAin7)); + xo2iobuf0121 \MAin_pad[7] ( .Z(PADDI), .PAD(MAin7)); specify (MAin7 => PADDI) = (0:0:0,0:0:0); @@ -5138,7 +5249,7 @@ endmodule module MAin_6_ ( output PADDI, input MAin6 ); - xo2iobuf0120 \MAin_pad[6] ( .Z(PADDI), .PAD(MAin6)); + xo2iobuf0121 \MAin_pad[6] ( .Z(PADDI), .PAD(MAin6)); specify (MAin6 => PADDI) = (0:0:0,0:0:0); @@ -5150,7 +5261,7 @@ endmodule module MAin_5_ ( output PADDI, input MAin5 ); - xo2iobuf0120 \MAin_pad[5] ( .Z(PADDI), .PAD(MAin5)); + xo2iobuf0121 \MAin_pad[5] ( .Z(PADDI), .PAD(MAin5)); specify (MAin5 => PADDI) = (0:0:0,0:0:0); @@ -5162,7 +5273,7 @@ endmodule module MAin_4_ ( output PADDI, input MAin4 ); - xo2iobuf0120 \MAin_pad[4] ( .Z(PADDI), .PAD(MAin4)); + xo2iobuf0121 \MAin_pad[4] ( .Z(PADDI), .PAD(MAin4)); specify (MAin4 => PADDI) = (0:0:0,0:0:0); @@ -5174,7 +5285,7 @@ endmodule module MAin_3_ ( output PADDI, input MAin3 ); - xo2iobuf0120 \MAin_pad[3] ( .Z(PADDI), .PAD(MAin3)); + xo2iobuf0121 \MAin_pad[3] ( .Z(PADDI), .PAD(MAin3)); specify (MAin3 => PADDI) = (0:0:0,0:0:0); @@ -5186,7 +5297,7 @@ endmodule module MAin_2_ ( output PADDI, input MAin2 ); - xo2iobuf0120 \MAin_pad[2] ( .Z(PADDI), .PAD(MAin2)); + xo2iobuf0121 \MAin_pad[2] ( .Z(PADDI), .PAD(MAin2)); specify (MAin2 => PADDI) = (0:0:0,0:0:0); @@ -5198,7 +5309,7 @@ endmodule module MAin_1_ ( output PADDI, input MAin1 ); - xo2iobuf0120 \MAin_pad[1] ( .Z(PADDI), .PAD(MAin1)); + xo2iobuf0121 \MAin_pad[1] ( .Z(PADDI), .PAD(MAin1)); specify (MAin1 => PADDI) = (0:0:0,0:0:0); @@ -5210,7 +5321,7 @@ endmodule module MAin_0_ ( output PADDI, input MAin0 ); - xo2iobuf0120 \MAin_pad[0] ( .Z(PADDI), .PAD(MAin0)); + xo2iobuf0121 \MAin_pad[0] ( .Z(PADDI), .PAD(MAin0)); specify (MAin0 => PADDI) = (0:0:0,0:0:0); diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mrp.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mrp.html index a74211f..8af07cf 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mrp.html +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mrp.html @@ -23,7 +23,7 @@ Target Vendor: LATTICE Target Device: LCMXO2-640HCTQFP100 Target Performance: 4 Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454 -Mapped on: 09/21/23 05:39:43 +Mapped on: 11/18/23 02:05:52 Design Summary @@ -34,12 +34,24 @@ Mapped on: 09/21/23 05:39:43 SLICEs as Logic/ROM: 120 out of 320 (38%) SLICEs as RAM: 0 out of 240 (0%) SLICEs as Carry: 10 out of 320 (3%) - Number of LUT4s: 237 out of 640 (37%) - Number used as logic LUTs: 217 + Number of LUT4s: 238 out of 640 (37%) + Number used as logic LUTs: 218 Number used as distributed RAM: 0 Number used as ripple logic: 20 Number used as shift registers: 0 - Number of PIO sites used: 63 + 4(JTAG) out of 79 (85%) + Number of PIO sites used: 64 + 4(JTAG) out of 79 (86%) + Number of IDDR/ODDR/TDDR cells used: 1 out of 237 (0%) + Number of IDDR cells: 0 + Number of ODDR cells: 1 + Number of TDDR cells: 0 + Number of PIO using at least one IDDR/ODDR/TDDR: 1 (0 differential) + Number of PIO using IDDR only: 0 (0 differential) + Number of PIO using ODDR only: 1 (0 differential) + Number of PIO using TDDR only: 0 (0 differential) + Number of PIO using IDDR/ODDR: 0 (0 differential) + Number of PIO using IDDR/TDDR: 0 (0 differential) + Number of PIO using ODDR/TDDR: 0 (0 differential) + Number of PIO using IDDR/ODDR/TDDR: 0 (0 differential) Number of block RAMs: 0 out of 2 (0%) Number of GSRs: 0 out of 1 (0%) EFB used : Yes @@ -55,20 +67,20 @@ Mapped on: 09/21/23 05:39:43 Number of DCMA: 0 out of 2 (0%) Notes:- 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of + distributed RAMs) + 2*(Number of ripple logic) 2. Number of logic LUT4s does not include count of distributed RAM and ripple logic. Number of clocks: 4 Net PHI2_c: 20 loads, 9 rising, 11 falling (Driver: PIO PHI2 ) - Net RCLK_c: 47 loads, 47 rising, 0 falling (Driver: PIO RCLK ) + Net RCLK_c: 48 loads, 48 rising, 0 falling (Driver: PIO RCLK ) Net nCRAS_c: 9 loads, 0 rising, 9 falling (Driver: PIO nCRAS ) Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS ) Number of Clock Enables: 5 - Net N_178: 1 loads, 1 LSLICEs + Net wb_cyc_stb_2_sqmuxa_i_0_0: 1 loads, 1 LSLICEs Net XOR8MEG18: 5 loads, 5 LSLICEs - Net N_360_i: 2 loads, 2 LSLICEs - - Net un1_wb_rst14_i_0: 9 loads, 9 LSLICEs + Net N_126_i: 9 loads, 9 LSLICEs + Net N_261_i: 2 loads, 2 LSLICEs Net CmdUFMData_1_sqmuxa: 1 loads, 1 LSLICEs Number of LSRs: 5 Net RA10s_i: 1 loads, 0 LSLICEs @@ -78,16 +90,16 @@ Mapped on: 09/21/23 05:39:43 Net RASr2: 2 loads, 2 LSLICEs Number of nets driven by tri-state buffers: 0 Top 10 highest fanout non-clock nets: - Net InitReady: 41 loads - Net FS[11]: 23 loads + Net InitReady: 40 loads Net FS[13]: 22 loads - Net FS[10]: 21 loads - Net FS[12]: 21 loads - Net FS[9]: 20 loads - Net FS[14]: 18 loads - Net CO0: 15 loads + Net FS[11]: 21 loads + Net FS[12]: 19 loads + Net FS[14]: 19 loads + Net FS[10]: 18 loads + Net FS[9]: 17 loads + Net Ready: 14 loads Net Ready_fast: 14 loads - Net N_214: 13 loads + Net CO0: 12 loads @@ -115,6 +127,7 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will +---------------------+-----------+-----------+------------+ | IO Name | Direction | Levelmode | IO | | | | IO_TYPE | Register | + +---------------------+-----------+-----------+------------+ | RD[0] | BIDIR | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ @@ -127,7 +140,6 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will | RDQMH | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | nRCAS | OUTPUT | LVCMOS33 | OUT | - +---------------------+-----------+-----------+------------+ | nRRAS | OUTPUT | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ @@ -135,6 +147,8 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will +---------------------+-----------+-----------+------------+ | RCKE | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ +| RCLKout | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ | RCLK | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | nRCS | OUTPUT | LVCMOS33 | OUT | @@ -170,6 +184,7 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will | RA[4] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | RA[3] | OUTPUT | LVCMOS33 | | + +---------------------+-----------+-----------+------------+ | RA[2] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ @@ -184,7 +199,6 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will | LED | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | nFWE | INPUT | LVCMOS33 | | - +---------------------+-----------+-----------+------------+ | nCRAS | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ @@ -227,6 +241,7 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will | MAin[9] | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | MAin[8] | INPUT | LVCMOS33 | | + +---------------------+-----------+-----------+------------+ | MAin[7] | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ @@ -241,7 +256,6 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will | MAin[2] | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | MAin[1] | INPUT | LVCMOS33 | | - +---------------------+-----------+-----------+------------+ | MAin[0] | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ @@ -254,7 +268,6 @@ Block GSR_INST undriven or does not drive anything - clipped. Signal nCRAS_c_i was merged into signal nCRAS_c Signal RASr2_i was merged into signal RASr2 Signal XOR8MEG.CN was merged into signal PHI2_c -Signal GND undriven or does not drive anything - clipped. Signal ufmefb/VCC undriven or does not drive anything - clipped. Signal ufmefb/GND undriven or does not drive anything - clipped. Signal FS_s_0_S1[17] undriven or does not drive anything - clipped. @@ -286,6 +299,7 @@ Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped. Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped. Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped. Signal ufmefb/I2C2SCLO undriven or does not drive anything - clipped. + Signal ufmefb/I2C1SDAOEN undriven or does not drive anything - clipped. Signal ufmefb/I2C1SDAO undriven or does not drive anything - clipped. Signal ufmefb/I2C1SCLOEN undriven or does not drive anything - clipped. @@ -299,7 +313,6 @@ Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped. Signal ufmefb/PLLDATO6 undriven or does not drive anything - clipped. Signal ufmefb/PLLDATO7 undriven or does not drive anything - clipped. Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped. - Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped. Signal ufmefb/PLLADRO2 undriven or does not drive anything - clipped. Signal ufmefb/PLLADRO3 undriven or does not drive anything - clipped. @@ -320,7 +333,6 @@ Signal N_1 undriven or does not drive anything - clipped. Block nCRAS_pad_RNIBPVB was optimized away. Block RASr2_RNIAFR1 was optimized away. Block XOR8MEG.CN was optimized away. -Block GND was optimized away. Block ufmefb/VCC was optimized away. Block ufmefb/GND was optimized away. @@ -345,6 +357,7 @@ Block ufmefb/GND was optimized away. I2C Function Summary: -------------------- None + SPI Function Summary: -------------------- None @@ -358,7 +371,6 @@ Block ufmefb/GND was optimized away. Available General Purpose Flash Memory: 191 Pages (191*128 Bits) - EBR Blocks with Unique Initialization Data: 0 @@ -400,18 +412,6 @@ Instance Name: ufmefb/EFBInst_0 - - - - - - - - - - - - diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_pad.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_pad.html index 922c9bf..d93f9ce 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_pad.html +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_pad.html @@ -14,7 +14,7 @@ Performance Grade: 4 PACKAGE: TQFP100 Package Status: Final Version 1.39 -Thu Sep 21 05:39:54 2023 +Sat Nov 18 02:06:05 2023 Pinout by Port Name: +-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ @@ -63,9 +63,10 @@ Pinout by Port Name: | RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW | | RA[9] | 62/1 | LVCMOS33_OUT | PR5D | | | DRIVE:4mA SLEW:SLOW | | RBA[0] | 58/1 | LVCMOS33_OUT | PR6C | | | DRIVE:4mA SLEW:SLOW | -| RBA[1] | 60/1 | LVCMOS33_OUT | PR6A | | | DRIVE:4mA SLEW:SLOW | +| RBA[1] | 47/2 | LVCMOS33_OUT | PB14B | | | DRIVE:4mA SLEW:SLOW | | RCKE | 53/1 | LVCMOS33_OUT | PR7B | | | DRIVE:4mA SLEW:SLOW | | RCLK | 63/1 | LVCMOS33_IN | PR5C | | | CLAMP:ON HYSTERESIS:SMALL | +| RCLKout | 60/1 | LVCMOS33_OUT | PR6A | | | DRIVE:24mA SLEW:FAST | | RDQMH | 51/1 | LVCMOS33_OUT | PR7D | | | DRIVE:4mA SLEW:SLOW | | RDQML | 48/2 | LVCMOS33_OUT | PB14C | | | DRIVE:4mA SLEW:SLOW | | RD[0] | 36/2 | LVCMOS33_BIDI | PB10A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | @@ -143,7 +144,7 @@ Vccio by Bank: | 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB12C | | | | | 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB12D | | | | | 45/2 | unused, PULL:DOWN | | | PB14A | | | | -| 47/2 | unused, PULL:DOWN | | | PB14B | | | | +| 47/2 | RBA[1] | LOCATED | LVCMOS33_OUT | PB14B | | | | | 48/2 | RDQML | LOCATED | LVCMOS33_OUT | PB14C | SN | | | | 49/2 | nRWE | LOCATED | LVCMOS33_OUT | PB14D | SI/SISPI | | | | 51/1 | RDQMH | LOCATED | LVCMOS33_OUT | PR7D | | | | @@ -153,7 +154,7 @@ Vccio by Bank: | 57/1 | nRCS | LOCATED | LVCMOS33_OUT | PR6D | | | | | 58/1 | RBA[0] | LOCATED | LVCMOS33_OUT | PR6C | | | | | 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR6B | | | | -| 60/1 | RBA[1] | LOCATED | LVCMOS33_OUT | PR6A | | | | +| 60/1 | RCLKout | LOCATED | LVCMOS33_OUT | PR6A | | | | | 62/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5D | PCLKC1_0 | | | | 63/1 | RCLK | LOCATED | LVCMOS33_IN | PR5C | PCLKT1_0 | | | | 64/1 | RA[10] | LOCATED | LVCMOS33_OUT | PR5B | | | | @@ -247,9 +248,10 @@ LOCATE COMP "RA[7]" SITE "75"; LOCATE COMP "RA[8]" SITE "65"; LOCATE COMP "RA[9]" SITE "62"; LOCATE COMP "RBA[0]" SITE "58"; -LOCATE COMP "RBA[1]" SITE "60"; +LOCATE COMP "RBA[1]" SITE "47"; LOCATE COMP "RCKE" SITE "53"; LOCATE COMP "RCLK" SITE "63"; +LOCATE COMP "RCLKout" SITE "60"; LOCATE COMP "RDQMH" SITE "51"; LOCATE COMP "RDQML" SITE "48"; LOCATE COMP "RD[0]" SITE "36"; @@ -278,7 +280,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Thu Sep 21 05:39:58 2023 +Sat Nov 18 02:06:08 2023 diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_par.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_par.html index 300bb39..029ad73 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_par.html +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_par.html @@ -12,7 +12,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Thu Sep 21 05:39:47 2023 +Sat Nov 18 02:05:56 2023 C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_640HC_impl1.p2t RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir @@ -26,17 +26,17 @@ Preference file: RAM2GS_LCMXO2_640HC_impl1.prf. Level/ Number Worst Timing Worst Timing Run NCD Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status ---------- -------- ----- ------ ----------- ----------- ---- ------ -5_1 * 0 5.772 0 0.304 0 13 Completed +5_1 * 0 6.245 0 0.304 0 15 Completed * : Design saved. -Total (real) run time for 1-seed: 13 secs +Total (real) run time for 1-seed: 15 secs par done! Note: user must run 'Trace' for timing closure signoff. Lattice Place and Route Report for Design "RAM2GS_LCMXO2_640HC_impl1_map.ncd" -Thu Sep 21 05:39:47 2023 +Sat Nov 18 02:05:56 2023 Best Par Run @@ -63,23 +63,23 @@ Ignore Preference Error(s): True Device utilization summary: - PIO (prelim) 63+4(JTAG)/80 84% used - 63+4(JTAG)/79 85% bonded - IOLOGIC 25/80 31% used + PIO (prelim) 64+4(JTAG)/80 85% used + 64+4(JTAG)/79 86% bonded + IOLOGIC 26/80 32% used SLICE 120/320 37% used EFB 1/1 100% used -Number of Signals: 388 -Number of Connections: 1017 +Number of Signals: 389 +Number of Connections: 1011 Pin Constraint Summary: - 63 out of 63 pins locked (100% locked). + 64 out of 64 pins locked (100% locked). The following 2 signals are selected to use the primary clock routing resources: - RCLK_c (driver: RCLK, clk load #: 47) + RCLK_c (driver: RCLK, clk load #: 48) PHI2_c (driver: PHI2, clk load #: 20) WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. @@ -92,18 +92,18 @@ WARNING - par: Signal "nCRAS_c" is selected to use Secondary clock res WARNING - par: Signal "nCCAS_c" is selected to use Secondary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. No signal is selected as Global Set/Reset. Starting Placer Phase 0. -............ -Finished Placer Phase 0. REAL time: 0 secs +........... +Finished Placer Phase 0. REAL time: 2 secs Starting Placer Phase 1. .................... -Placer score = 57011. -Finished Placer Phase 1. REAL time: 7 secs +Placer score = 59875. +Finished Placer Phase 1. REAL time: 9 secs Starting Placer Phase 2. . -Placer score = 56576 -Finished Placer Phase 2. REAL time: 7 secs +Placer score = 59374 +Finished Placer Phase 2. REAL time: 9 secs @@ -116,7 +116,7 @@ Global Clock Resources: DCC : 0 out of 8 (0%) Global Clocks: - PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "63 (PR5C)", clk load = 47 + PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "63 (PR5C)", clk load = 48 PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 20 SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 9, ce load = 0, sr load = 0 SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 8, ce load = 0, sr load = 0 @@ -128,9 +128,9 @@ Global Clocks: I/O Usage Summary (final): - 63 + 4(JTAG) out of 80 (83.8%) PIO sites used. - 63 + 4(JTAG) out of 79 (84.8%) bonded PIO sites used. - Number of PIO comps: 63; differential: 0. + 64 + 4(JTAG) out of 80 (85.0%) PIO sites used. + 64 + 4(JTAG) out of 79 (86.1%) bonded PIO sites used. + Number of PIO comps: 64; differential: 0. Number of Vref pins used: 0. I/O Bank Usage Summary: @@ -139,20 +139,20 @@ I/O Bank Usage Summary: +----------+----------------+------------+-----------+ | 0 | 13 / 19 ( 68%) | 3.3V | - | | 1 | 20 / 20 (100%) | 3.3V | - | -| 2 | 12 / 20 ( 60%) | 3.3V | - | +| 2 | 13 / 20 ( 65%) | 3.3V | - | | 3 | 18 / 20 ( 90%) | 3.3V | - | +----------+----------------+------------+-----------+ -Total placer CPU time: 7 secs +Total placer CPU time: 8 secs Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd. -0 connections routed; 1017 unrouted. +0 connections routed; 1011 unrouted. Starting router resource preassignment -Completed router resource preassignment. Real time: 11 secs +Completed router resource preassignment. Real time: 13 secs -Start NBR router at 05:39:58 09/21/23 +Start NBR router at 02:06:09 11/18/23 ***************************************************************** Info: NBR allows conflicts(one node used by more than one signal) @@ -167,50 +167,41 @@ Note: NBR uses a different method to calculate timing slacks. The your design. ***************************************************************** -Start NBR special constraint process at 05:39:58 09/21/23 +Start NBR special constraint process at 02:06:09 11/18/23 -Start NBR section for initial routing at 05:39:58 09/21/23 +Start NBR section for initial routing at 02:06:09 11/18/23 Level 1, iteration 1 -2(0.00%) conflicts; 816(80.24%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 6.163ns/0.000ns; real time: 11 secs +0(0.00%) conflict; 814(80.51%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack<setup>: 6.075ns/0.000ns; real time: 13 secs Level 2, iteration 1 -0(0.00%) conflict; 815(80.14%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 5.772ns/0.000ns; real time: 11 secs +0(0.00%) conflict; 808(79.92%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack<setup>: 6.252ns/0.000ns; real time: 13 secs Level 3, iteration 1 -0(0.00%) conflict; 815(80.14%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 5.772ns/0.000ns; real time: 11 secs +0(0.00%) conflict; 808(79.92%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack<setup>: 6.252ns/0.000ns; real time: 13 secs Level 4, iteration 1 -8(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 5.772ns/0.000ns; real time: 12 secs +6(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack<setup>: 6.245ns/0.000ns; real time: 14 secs Info: Initial congestion level at 75% usage is 0 Info: Initial congestion area at 75% usage is 0 (0.00%) -Start NBR section for normal routing at 05:39:59 09/21/23 +Start NBR section for normal routing at 02:06:10 11/18/23 Level 4, iteration 1 -4(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 5.772ns/0.000ns; real time: 12 secs +1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack<setup>: 6.245ns/0.000ns; real time: 14 secs Level 4, iteration 2 -2(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 5.772ns/0.000ns; real time: 12 secs -Level 4, iteration 3 -1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 5.772ns/0.000ns; real time: 12 secs -Level 4, iteration 4 -1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 5.772ns/0.000ns; real time: 12 secs -Level 4, iteration 5 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 5.772ns/0.000ns; real time: 12 secs +Estimated worst slack/total negative slack<setup>: 6.245ns/0.000ns; real time: 14 secs -Start NBR section for setup/hold timing optimization with effort level 3 at 05:39:59 09/21/23 +Start NBR section for setup/hold timing optimization with effort level 3 at 02:06:10 11/18/23 -Start NBR section for re-routing at 05:39:59 09/21/23 +Start NBR section for re-routing at 02:06:10 11/18/23 Level 4, iteration 1 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 5.772ns/0.000ns; real time: 12 secs +Estimated worst slack/total negative slack<setup>: 6.245ns/0.000ns; real time: 14 secs -Start NBR section for post-routing at 05:39:59 09/21/23 +Start NBR section for post-routing at 02:06:10 11/18/23 End NBR router with 0 unrouted connection @@ -218,17 +209,17 @@ NBR Summary ----------- Number of unrouted connections : 0 (0.00%) Number of connections with timing violations : 0 (0.00%) - Estimated worst slack<setup> : 5.772ns + Estimated worst slack<setup> : 6.245ns Timing score<setup> : 0 ----------- Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. -Total CPU time 12 secs -Total REAL time: 13 secs +Total CPU time 13 secs +Total REAL time: 15 secs Completely routed. -End of route. 1017 routed (100.00%); 0 unrouted. +End of route. 1011 routed (100.00%); 0 unrouted. Hold time timing score: 0, hold timing errors: 0 @@ -242,14 +233,14 @@ All signals are completely routed. PAR_SUMMARY::Run status = Completed PAR_SUMMARY::Number of unrouted conns = 0 -PAR_SUMMARY::Worst slack<setup/<ns>> = 5.772 +PAR_SUMMARY::Worst slack<setup/<ns>> = 6.245 PAR_SUMMARY::Timing score<setup/<ns>> = 0.000 PAR_SUMMARY::Worst slack<hold /<ns>> = 0.304 PAR_SUMMARY::Timing score<hold /<ns>> = 0.000 PAR_SUMMARY::Number of errors = 0 Total CPU time to completion: 13 secs -Total REAL time to completion: 13 secs +Total REAL time to completion: 15 secs par done! diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_scck.rpt b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_scck.rpt index 231cc15..afd58a3 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_scck.rpt +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_scck.rpt @@ -13,7 +13,7 @@ Hostname: ZANEMACWIN11 Implementation : impl1 -# Written on Thu Sep 21 05:39:36 2023 +# Written on Sat Nov 18 02:05:42 2023 ##### FILES SYNTAX CHECKED ############################################## Constraint File(s): "\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc" diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_summary.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_summary.html index 130dc47..b23aa77 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_summary.html +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_summary.html @@ -24,9 +24,9 @@ Last Process: -JEDEC File + State: -Passed + Target Device: @@ -62,7 +62,7 @@ Updated: -2023/09/21 05:40:18 +2023/11/18 02:59:48 Implementation Location: diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_synplify.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_synplify.html index 59b9948..14f534a 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_synplify.html +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_synplify.html @@ -12,7 +12,7 @@ #OS: Windows 8 6.2 #Hostname: ZANEMACWIN11 -# Thu Sep 21 05:39:33 2023 +# Sat Nov 18 02:05:39 2023 #Implementation: impl1 @@ -60,13 +60,17 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202 @I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v" (library work) @I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-640HC\REFB.v" (library work) Verilog syntax check successful! +File \\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v changed - recompiling Selecting top level module RAM2GS +@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1601:7:1601:12|Synthesizing module ODDRXE in library work. +Running optimization stage 1 on ODDRXE ....... +Finished optimization stage 1 on ODDRXE (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB) @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work. Running optimization stage 1 on VHI ....... -Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 98MB) +Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB) @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work. Running optimization stage 1 on VLO ....... -Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB) +Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB) @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work. Running optimization stage 1 on EFB ....... Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB) @@ -86,13 +90,15 @@ Running optimization stage 2 on VLO ....... Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) Running optimization stage 2 on VHI ....... Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) +Running optimization stage 2 on ODDRXE ....... +Finished optimization stage 2 on ODDRXE (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) -At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB) +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Sep 21 05:39:33 2023 +# Sat Nov 18 02:05:40 2023 ###########################################################] ###########################################################[ @@ -119,7 +125,7 @@ At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Sep 21 05:39:34 2023 +# Sat Nov 18 02:05:40 2023 ###########################################################] @@ -129,12 +135,12 @@ For a summary of runtime and memory usage for all design units, please see file: @END -At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB) +At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Sep 21 05:39:34 2023 +# Sat Nov 18 02:05:40 2023 ###########################################################] ###########################################################[ @@ -155,18 +161,17 @@ Implementation : impl1 Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ @N|Running in 64-bit mode +File \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Sep 21 05:39:35 2023 +# Sat Nov 18 02:05:42 2023 ###########################################################] -Premap Report - -# Thu Sep 21 05:39:35 2023 +# Sat Nov 18 02:05:42 2023 Copyright (C) 1994-2021 Synopsys, Inc. @@ -185,10 +190,10 @@ Implementation : impl1 Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @ -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB) +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB) -Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 140MB) +Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 140MB) Reading constraint file: \\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc @L: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1_scck.rpt @@ -212,7 +217,6 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h @W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. @N: FX493 |Applying initial value "0" on instance Ready. @N: FX493 |Applying initial value "0" on instance RCKE. -@N: FX493 |Applying initial value "0" on instance LEDEN. @N: FX493 |Applying initial value "0" on instance n8MEGEN. @N: FX493 |Applying initial value "1" on instance nRCAS. @N: FX493 |Applying initial value "0" on instance CmdLEDEN. @@ -238,11 +242,11 @@ Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapse Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB) -Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) +Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB) @N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS -Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB) @@ -326,12 +330,10 @@ Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 103MB peak: 185MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu Sep 21 05:39:37 2023 +# Sat Nov 18 02:05:43 2023 ###########################################################] -Map & Optimize Report - -# Thu Sep 21 05:39:37 2023 +# Sat Nov 18 02:05:44 2023 Copyright (C) 1994-2021 Synopsys, Inc. @@ -350,22 +352,22 @@ Implementation : impl1 Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @ -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB) +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB) @N: MF916 |Option synthesis_strategy=base is enabled. @N: MF248 |Running in 64-bit mode. @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 139MB) +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB) -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 139MB) +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB) -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB) +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB) @@ -374,8 +376,8 @@ Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapse Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB) -@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":163:4:163:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] -@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":150:4:150:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] +@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":166:4:166:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] +@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":153:4:153:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] @N: FX493 |Applying initial value "0" on instance IS[0]. @W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. @N: FX493 |Applying initial value "0" on instance IS[1]. @@ -385,7 +387,7 @@ Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00 Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 185MB peak: 185MB) -Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 187MB) +Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB) Available hyper_sources - for debug and ip models @@ -398,7 +400,7 @@ Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CP Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 187MB) -Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 187MB) +Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB) @@ -407,16 +409,16 @@ Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CP Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB) -Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 197MB peak: 197MB) +Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 196MB peak: 196MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ - 1 0h:00m:01s -2.98ns 201 / 106 - 2 0h:00m:01s -2.98ns 217 / 106 + 1 0h:00m:01s -2.98ns 202 / 106 + 2 0h:00m:01s -2.98ns 215 / 106 3 0h:00m:01s -2.76ns 215 / 106 -@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":121:4:121:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing. -@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":304:4:304:9|Replicating instance CmdValid (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing. -@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":163:4:163:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 11 loads 1 time to improve timing. +@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":124:4:124:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing. +@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":307:4:307:9|Replicating instance CmdValid (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing. +@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":166:4:166:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing. Timing driven replication report Added 3 Registers via timing driven replication Added 1 LUTs via timing driven replication @@ -430,10 +432,10 @@ Finished technology timing optimizations and critical path resynthesis (Real Tim @N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. -Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 198MB peak: 198MB) +Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 197MB peak: 197MB) -Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 160MB peak: 198MB) +Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 198MB) Writing Analyst data base \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_m.srm @@ -443,14 +445,15 @@ Writing EDIF Netlist and constraint files @N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.edi @N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF -Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 203MB peak: 203MB) +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 202MB peak: 202MB) -Finished Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 203MB peak: 203MB) +Finished Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 202MB peak: 203MB) Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 201MB peak: 203MB) +@W: MT246 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":43:11:43:19|Blackbox ODDRXE is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W: MT246 :"\\mac\icloud\repos\ram2gs\cpld\lcmxo2-640hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @N: MT615 |Found clock RCLK with period 16.00ns @N: MT615 |Found clock PHI2 with period 350.00ns @@ -459,7 +462,7 @@ Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:0 ##### START OF TIMING REPORT #####[ -# Timing report written on Thu Sep 21 05:39:41 2023 +# Timing report written on Sat Nov 18 02:05:48 2023 # @@ -510,7 +513,7 @@ Starting Ending | constraint slack | constraint slack | constraint --------------------------------------------------------------------------------------------------------------- System RCLK | 16.000 12.918 | No paths - | No paths - | No paths - RCLK System | 16.000 14.956 | No paths - | No paths - | No paths - -RCLK RCLK | 16.000 9.040 | No paths - | No paths - | No paths - +RCLK RCLK | 16.000 9.237 | No paths - | No paths - | No paths - RCLK PHI2 | 2.000 0.216 | No paths - | 1.000 -0.676 | No paths - RCLK nCRAS | No paths - | No paths - | 1.000 -0.784 | No paths - PHI2 RCLK | No paths - | No paths - | No paths - | 1.000 -1.828 @@ -549,30 +552,30 @@ CmdLEDEN PHI2 FD1P3AX Q CmdLEDEN 1.044 Cmdn8MEGEN PHI2 FD1P3AX Q Cmdn8MEGEN 1.044 -1.589 CmdUFMWrite PHI2 FD1P3AX Q CmdUFMWrite 1.044 -0.572 CmdUFMData PHI2 FD1P3AX Q CmdUFMData 0.972 -0.500 -Bank_0io[0] PHI2 IFS1P3DX Q Bank[0] 0.972 169.081 Bank_0io[1] PHI2 IFS1P3DX Q Bank[1] 0.972 169.081 Bank_0io[2] PHI2 IFS1P3DX Q Bank[2] 0.972 169.081 +Bank_0io[3] PHI2 IFS1P3DX Q Bank[3] 0.972 169.081 ========================================================================================== Ending Points with Worst Slack ****************************** - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------------ -wb_adr[0] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828 -wb_adr[1] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828 -wb_adr[2] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828 -wb_adr[3] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828 -wb_adr[4] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828 -wb_adr[5] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828 -wb_adr[6] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828 -wb_adr[7] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828 -wb_dati[0] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828 -wb_dati[1] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828 -========================================================================================= + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------- +wb_adr[0] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +wb_adr[1] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +wb_adr[2] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +wb_adr[3] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +wb_adr[4] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +wb_adr[5] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +wb_adr[6] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +wb_adr[7] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +wb_dati[0] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +wb_dati[1] PHI2 FD1P3AX SP N_126_i 0.528 -1.828 +================================================================================ @@ -603,7 +606,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r - CmdUFMShift Net - - - - 2 CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r - CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r - -un1_wb_rst14_i_0 Net - - - - 17 +N_126_i Net - - - - 17 wb_adr[0] FD1P3AX SP In 0.000 2.357 r - ========================================================================================= @@ -631,7 +634,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r - CmdUFMShift Net - - - - 2 CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r - CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r - -un1_wb_rst14_i_0 Net - - - - 17 +N_126_i Net - - - - 17 wb_adr[7] FD1P3AX SP In 0.000 2.357 r - ========================================================================================= @@ -659,7 +662,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r - CmdUFMShift Net - - - - 2 CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r - CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r - -un1_wb_rst14_i_0 Net - - - - 17 +N_126_i Net - - - - 17 wb_adr[6] FD1P3AX SP In 0.000 2.357 r - ========================================================================================= @@ -687,7 +690,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r - CmdUFMShift Net - - - - 2 CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r - CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r - -un1_wb_rst14_i_0 Net - - - - 17 +N_126_i Net - - - - 17 wb_adr[5] FD1P3AX SP In 0.000 2.357 r - ========================================================================================= @@ -715,7 +718,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r - CmdUFMShift Net - - - - 2 CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r - CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r - -un1_wb_rst14_i_0 Net - - - - 17 +N_126_i Net - - - - 17 wb_adr[4] FD1P3AX SP In 0.000 2.357 r - ========================================================================================= @@ -738,13 +741,13 @@ Instance Reference Type Pin Net Time Slac Ready_fast RCLK FD1S3AX Q Ready_fast 1.256 -0.784 LEDEN RCLK FD1S3AX Q LEDEN 1.148 -0.676 n8MEGEN RCLK FD1S3AX Q n8MEGEN 1.108 -0.636 -IS[1] RCLK FD1P3AX Q IS[1] 1.204 9.040 -IS[2] RCLK FD1P3AX Q IS[2] 1.188 9.056 -IS[3] RCLK FD1P3AX Q IS[3] 1.148 9.096 -InitReady RCLK FD1S3AX Q InitReady 1.339 9.228 -FS[15] RCLK FD1S3AX Q FS[15] 1.228 9.339 -FS[16] RCLK FD1S3AX Q FS[16] 1.188 9.379 -FS[17] RCLK FD1S3AX Q FS[17] 1.188 9.379 +InitReady RCLK FD1S3AX Q InitReady 1.337 9.237 +FS[16] RCLK FD1S3AX Q FS[16] 1.204 9.371 +FS[17] RCLK FD1S3AX Q FS[17] 1.204 9.371 +FS[15] RCLK FD1S3AX Q FS[15] 1.188 9.387 +S[0] RCLK FD1S3IX Q CO0 1.244 9.873 +S[1] RCLK FD1S3IX Q S[1] 1.236 9.881 +RASr2 RCLK FD1S3AX Q RASr2 1.228 9.889 ================================================================================== @@ -841,7 +844,35 @@ Path information for path number 3: Number of logic level(s): 1 Starting point: Ready_fast / Q - Ending point: RowA[0] / D + Ending point: RBA_0io[1] / D + The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK + The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin SCLK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------- +Ready_fast FD1S3AX Q Out 1.256 1.256 r - +Ready_fast Net - - - - 14 +RBAd[1] ORCALUT4 B In 0.000 1.256 r - +RBAd[1] ORCALUT4 Z Out 0.617 1.873 r - +RBAd_0[1] Net - - - - 1 +RBA_0io[1] OFS1P3DX D In 0.000 1.873 r - +================================================================================= + + +Path information for path number 4: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 1.873 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -0.784 + + Number of logic level(s): 1 + Starting point: Ready_fast / Q + Ending point: RowA[1] / D The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK @@ -850,14 +881,14 @@ Name Type Name Dir Delay Time Fan Out(s --------------------------------------------------------------------------------- Ready_fast FD1S3AX Q Out 1.256 1.256 r - Ready_fast Net - - - - 14 -RowAd[0] ORCALUT4 B In 0.000 1.256 r - -RowAd[0] ORCALUT4 Z Out 0.617 1.873 r - -RowAd_0[0] Net - - - - 1 -RowA[0] FD1S3AX D In 0.000 1.873 r - +RowAd[1] ORCALUT4 B In 0.000 1.256 r - +RowAd[1] ORCALUT4 Z Out 0.617 1.873 r - +RowAd_0[1] Net - - - - 1 +RowA[1] FD1S3AX D In 0.000 1.873 r - ================================================================================= -Path information for path number 4: +Path information for path number 5: Requested Period: 1.000 - Setup time: -0.089 + Clock delay at ending point: 0.000 (ideal) @@ -885,34 +916,6 @@ RowA[5] FD1S3AX D In 0.000 1.873 f - ================================================================================= -Path information for path number 5: - Requested Period: 1.000 - - Setup time: -0.089 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 1.089 - - - Propagation time: 1.873 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : -0.784 - - Number of logic level(s): 1 - Starting point: Ready_fast / Q - Ending point: RowA[8] / D - The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK - The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------- -Ready_fast FD1S3AX Q Out 1.256 1.256 r - -Ready_fast Net - - - - 14 -RowAd[8] ORCALUT4 B In 0.000 1.256 r - -RowAd[8] ORCALUT4 Z Out 0.617 1.873 r - -RowAd_0[8] Net - - - - 1 -RowA[8] FD1S3AX D In 0.000 1.873 r - -================================================================================= - - ==================================== @@ -937,16 +940,16 @@ FWEr nCRAS FD1S3AX Q FWEr 1.180 -1.797 Ending Points with Worst Slack ****************************** - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------------- -nRCAS_0io nCRAS OFS1P3BX D N_248_i 1.089 -2.605 -nRCS_0io nCRAS OFS1P3BX D N_247_i 1.089 -1.797 -nRWE_0io nCRAS OFS1P3BX D N_49_i 1.089 -1.797 -nRowColSel nCRAS FD1S3IX D nRowColSel_0_0_0 1.089 -1.797 -RCKEEN nCRAS FD1S3AX D RCKEEN_8 1.089 -1.725 -========================================================================================== + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +---------------------------------------------------------------------------------------- +nRCAS_0io nCRAS OFS1P3BX D N_251_i 1.089 -2.605 +nRCS_0io nCRAS OFS1P3BX D N_37_i 1.089 -1.797 +nRWE_0io nCRAS OFS1P3BX D N_252_i 1.089 -1.797 +nRowColSel nCRAS FD1S3IX D nRowColSel_0_0 1.089 -1.797 +RCKEEN nCRAS FD1S3AX D RCKEEN_8 1.089 -1.725 +======================================================================================== @@ -980,10 +983,10 @@ CBR_fast_RNIQ31K1 ORCALUT4 Z Out 1.089 2.061 r - nRCAS_0_sqmuxa_1 Net - - - - 2 nRCAS_0io_RNO_0 ORCALUT4 B In 0.000 2.061 r - nRCAS_0io_RNO_0 ORCALUT4 Z Out 1.017 3.077 r - -N_248_i_sx Net - - - - 1 -nRCAS_0io_RNO ORCALUT4 D In 0.000 3.077 r - +N_251_i_sx Net - - - - 1 +nRCAS_0io_RNO ORCALUT4 C In 0.000 3.077 r - nRCAS_0io_RNO ORCALUT4 Z Out 0.617 3.694 f - -N_248_i Net - - - - 1 +N_251_i Net - - - - 1 nRCAS_0io OFS1P3BX D In 0.000 3.694 f - ==================================================================================== @@ -1004,19 +1007,19 @@ Path information for path number 2: The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------- -CBR FD1S3AX Q Out 1.180 1.180 r - -CBR Net - - - - 5 -RCKEEN_8_u_0_0_a2_2 ORCALUT4 A In 0.000 1.180 r - -RCKEEN_8_u_0_0_a2_2 ORCALUT4 Z Out 1.089 2.269 f - -N_590 Net - - - - 2 -nRCS_0io_RNO ORCALUT4 C In 0.000 2.269 f - -nRCS_0io_RNO ORCALUT4 Z Out 0.617 2.885 r - -N_247_i Net - - - - 1 -nRCS_0io OFS1P3BX D In 0.000 2.885 r - -====================================================================================== +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +------------------------------------------------------------------------------------ +CBR FD1S3AX Q Out 1.180 1.180 r - +CBR Net - - - - 5 +RCKEEN_8_u_0_a2_2 ORCALUT4 A In 0.000 1.180 r - +RCKEEN_8_u_0_a2_2 ORCALUT4 Z Out 1.089 2.269 f - +N_141 Net - - - - 2 +nRCS_0io_RNO ORCALUT4 A In 0.000 2.269 f - +nRCS_0io_RNO ORCALUT4 Z Out 0.617 2.885 r - +N_37_i Net - - - - 1 +nRCS_0io OFS1P3BX D In 0.000 2.885 r - +==================================================================================== Path information for path number 3: @@ -1035,19 +1038,19 @@ Path information for path number 3: The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------- -FWEr FD1S3AX Q Out 1.180 1.180 r - -FWEr Net - - - - 5 -nRCAS_r_i_0_a2 ORCALUT4 B In 0.000 1.180 r - -nRCAS_r_i_0_a2 ORCALUT4 Z Out 1.089 2.269 f - -N_248_i_1_0 Net - - - - 2 -nRCAS_0io_RNO ORCALUT4 C In 0.000 2.269 f - -nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.885 r - -N_248_i Net - - - - 1 -nRCAS_0io OFS1P3BX D In 0.000 2.885 r - -================================================================================= +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +---------------------------------------------------------------------------------- +FWEr FD1S3AX Q Out 1.180 1.180 r - +FWEr Net - - - - 5 +nRCS_9_u_i_a2_0 ORCALUT4 B In 0.000 1.180 r - +nRCS_9_u_i_a2_0 ORCALUT4 Z Out 1.089 2.269 f - +N_251_i_1 Net - - - - 2 +nRCAS_0io_RNO ORCALUT4 A In 0.000 2.269 f - +nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.885 r - +N_251_i Net - - - - 1 +nRCAS_0io OFS1P3BX D In 0.000 2.885 r - +================================================================================== Path information for path number 4: @@ -1066,19 +1069,19 @@ Path information for path number 4: The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------- -CBR FD1S3AX Q Out 1.180 1.180 r - -CBR Net - - - - 5 -RCKEEN_8_u_0_0_a2_2 ORCALUT4 A In 0.000 1.180 r - -RCKEEN_8_u_0_0_a2_2 ORCALUT4 Z Out 1.089 2.269 f - -N_590 Net - - - - 2 -nRWE_0io_RNO ORCALUT4 B In 0.000 2.269 f - -nRWE_0io_RNO ORCALUT4 Z Out 0.617 2.885 r - -N_49_i Net - - - - 1 -nRWE_0io OFS1P3BX D In 0.000 2.885 r - -====================================================================================== +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +------------------------------------------------------------------------------------ +CBR FD1S3AX Q Out 1.180 1.180 r - +CBR Net - - - - 5 +RCKEEN_8_u_0_a2_2 ORCALUT4 A In 0.000 1.180 r - +RCKEEN_8_u_0_a2_2 ORCALUT4 Z Out 1.089 2.269 f - +N_141 Net - - - - 2 +nRWE_0io_RNO ORCALUT4 B In 0.000 2.269 f - +nRWE_0io_RNO ORCALUT4 Z Out 0.617 2.885 r - +N_252_i Net - - - - 1 +nRWE_0io OFS1P3BX D In 0.000 2.885 r - +==================================================================================== Path information for path number 5: @@ -1102,12 +1105,12 @@ Name Type Name Dir Delay Time Fan -------------------------------------------------------------------------------------- FWEr FD1S3AX Q Out 1.180 1.180 r - FWEr Net - - - - 5 -nRowColSel_0_0_0_a2 ORCALUT4 B In 0.000 1.180 r - -nRowColSel_0_0_0_a2 ORCALUT4 Z Out 1.089 2.269 r - -N_248_i_1_1 Net - - - - 2 +nRowColSel_0_0_a2_1 ORCALUT4 B In 0.000 1.180 r - +nRowColSel_0_0_a2_1 ORCALUT4 Z Out 1.089 2.269 r - +N_251_i_1_0 Net - - - - 2 nRCAS_0io_RNO ORCALUT4 B In 0.000 2.269 r - nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.885 f - -N_248_i Net - - - - 1 +N_251_i Net - - - - 1 nRCAS_0io OFS1P3BX D In 0.000 2.885 f - ====================================================================================== @@ -1136,14 +1139,14 @@ ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 Ending Points with Worst Slack ****************************** - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------ -LEDEN System FD1S3AX D LEDENe_0 16.089 12.918 -n8MEGEN System FD1S3AX D n8MEGENe_0 16.089 12.918 -wb_cyc_stb System FD1P3IX SP N_178 15.528 14.912 -=================================================================================== + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------------------------- +LEDEN System FD1S3AX D LEDENe_0 16.089 12.918 +n8MEGEN System FD1S3AX D n8MEGENe_0 16.089 12.918 +wb_cyc_stb System FD1P3IX SP wb_cyc_stb_2_sqmuxa_i_0_0 15.528 14.912 +================================================================================================== @@ -1181,8 +1184,8 @@ ufmefb.EFBInst_0_RNISI191 ORCALUT4 Z Out 0.449 1.466 r N_4 Net - - - - 1 CmdValid_RNIOOBE2 ORCALUT4 C In 0.000 1.466 r - CmdValid_RNIOOBE2 ORCALUT4 Z Out 1.089 2.554 r - -CmdValid_RNIOOBE2 Net - - - - 2 -LEDENe ORCALUT4 B In 0.000 2.554 r - +un1_FS_38_i Net - - - - 2 +LEDENe ORCALUT4 C In 0.000 2.554 r - LEDENe ORCALUT4 Z Out 0.617 3.171 r - LEDENe_0 Net - - - - 1 LEDEN FD1S3AX D In 0.000 3.171 r - @@ -1205,7 +1208,7 @@ Part: lcmxo2_640hc-4 Register bits: 109 of 640 (17%) PIC Latch: 0 -I/O cells: 63 +I/O cells: 64 Details: @@ -1220,12 +1223,13 @@ GSR: 1 IB: 25 IFS1P3DX: 9 INV: 7 -OB: 30 +OB: 31 +ODDRXE: 1 OFS1P3BX: 4 OFS1P3DX: 11 OFS1P3JX: 1 -ORCALUT4: 213 -PFUMX: 1 +ORCALUT4: 212 +PFUMX: 2 PUR: 1 VHI: 2 VLO: 2 @@ -1234,7 +1238,7 @@ Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 78MB peak: 203MB) Process took 0h:00m:04s realtime, 0h:00m:04s cputime -# Thu Sep 21 05:39:42 2023 +# Sat Nov 18 02:05:48 2023 ###########################################################] diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_tw1.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_tw1.html index 4853e80..56a12ef 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_tw1.html +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_tw1.html @@ -22,7 +22,7 @@ Setup and Hold Report -------------------------------------------------------------------------------- Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 -Thu Sep 21 05:39:45 2023 +Sat Nov 18 02:05:54 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -50,8 +50,8 @@ Report: 150.150MHz is the maximum frequency for this preference.
  • FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)
    • 0 items scored, 0 timing errors detected. Report: 150.150MHz is the maximum frequency for this preference. -
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    • 878 items scored, 0 timing errors detected. -Report: 100.492MHz is the maximum frequency for this preference. +
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    • 891 items scored, 0 timing errors detected. +Report: 95.383MHz is the maximum frequency for this preference. BLOCK ASYNCPATHS BLOCK RESETPATHS @@ -69,28 +69,28 @@ Passed: The following path meets requirements by 163.025ns (weighted slack = 326 Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_0io[0] (from PHI2_c +) + Source: FF Q Bank_0io[1] (from PHI2_c +) Destination: FF Data in CmdEnable (to PHI2_c -) Delay: 9.223ns (33.1% logic, 66.9% route), 6 logic levels. Constraint Details: - 9.223ns physical path delay Din[0]_MGIOL to SLICE_17 meets + 9.223ns physical path delay Din[1]_MGIOL to SLICE_17 meets 172.414ns delay constraint less 0.166ns DIN_SET requirement (totaling 172.248ns) by 163.025ns Physical Path Details: - Data path Din[0]_MGIOL to SLICE_17: + Data path Din[1]_MGIOL to SLICE_17: Name Fanout Delay (ns) Site Resource -C2INP_DEL --- 0.577 *[0]_MGIOL.CLK to *n[0]_MGIOL.IN Din[0]_MGIOL (from PHI2_c) -ROUTE 1 e 1.234 *n[0]_MGIOL.IN to SLICE_93.A0 Bank[0] -CTOF_DEL --- 0.495 SLICE_93.A0 to SLICE_93.F0 SLICE_93 -ROUTE 1 e 1.234 SLICE_93.F0 to SLICE_84.C0 un1_CmdEnable20_0_0_o3_10 -CTOF_DEL --- 0.495 SLICE_84.C0 to SLICE_84.F0 SLICE_84 -ROUTE 6 e 1.234 SLICE_84.F0 to SLICE_11.C1 un1_CmdEnable20_0_0_o3 +C2INP_DEL --- 0.577 *[1]_MGIOL.CLK to *n[1]_MGIOL.IN Din[1]_MGIOL (from PHI2_c) +ROUTE 1 e 1.234 *n[1]_MGIOL.IN to SLICE_90.A0 Bank[1] +CTOF_DEL --- 0.495 SLICE_90.A0 to SLICE_90.F0 SLICE_90 +ROUTE 1 e 1.234 SLICE_90.F0 to SLICE_80.C0 un1_CmdEnable20_0_0_o2_10 +CTOF_DEL --- 0.495 SLICE_80.C0 to SLICE_80.F0 SLICE_80 +ROUTE 6 e 1.234 SLICE_80.F0 to SLICE_11.C1 N_367 CTOF_DEL --- 0.495 SLICE_11.C1 to SLICE_11.F1 SLICE_11 ROUTE 3 e 1.234 SLICE_11.F1 to SLICE_33.B0 CmdEnable16 CTOF_DEL --- 0.495 SLICE_33.B0 to SLICE_33.F0 SLICE_33 @@ -141,48 +141,46 @@ Report: 150.150MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; - 878 items scored, 0 timing errors detected. + 891 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- -Passed: The following path meets requirements by 6.049ns +Passed: The following path meets requirements by 5.516ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q IS[1] (from RCLK_c +) - Destination: FF Data in nRCAS_0io (to RCLK_c +) + Source: FF Q S[0] (from RCLK_c +) + Destination: FF Data in nRWE_0io (to RCLK_c +) - Delay: 9.798ns (34.9% logic, 65.1% route), 7 logic levels. + Delay: 10.331ns (28.3% logic, 71.7% route), 6 logic levels. Constraint Details: - 9.798ns physical path delay SLICE_27 to nRCAS_MGIOL meets + 10.331ns physical path delay SLICE_16 to nRWE_MGIOL meets 16.000ns delay constraint less - 0.153ns DO_SET requirement (totaling 15.847ns) by 6.049ns + 0.153ns DO_SET requirement (totaling 15.847ns) by 5.516ns Physical Path Details: - Data path SLICE_27 to nRCAS_MGIOL: + Data path SLICE_16 to nRWE_MGIOL: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 SLICE_27.CLK to SLICE_27.Q0 SLICE_27 (from RCLK_c) -ROUTE 7 e 1.234 SLICE_27.Q0 to SLICE_74.A1 IS[1] -CTOF_DEL --- 0.495 SLICE_74.A1 to SLICE_74.F1 SLICE_74 -ROUTE 2 e 0.480 SLICE_74.F1 to SLICE_74.B0 un1_nRCAS_6_sqmuxa_i_0_0_o2_0 -CTOF_DEL --- 0.495 SLICE_74.B0 to SLICE_74.F0 SLICE_74 -ROUTE 2 e 1.234 SLICE_74.F0 to SLICE_61.B1 N_408 -CTOF_DEL --- 0.495 SLICE_61.B1 to SLICE_61.F1 SLICE_61 -ROUTE 1 e 0.480 SLICE_61.F1 to SLICE_61.A0 un1_nRCAS_6_sqmuxa_i_0_0 -CTOF_DEL --- 0.495 SLICE_61.A0 to SLICE_61.F0 SLICE_61 -ROUTE 1 e 1.234 SLICE_61.F0 to SLICE_94.D0 nRCAS_r_i_0_o2_0_0 -CTOF_DEL --- 0.495 SLICE_94.D0 to SLICE_94.F0 SLICE_94 -ROUTE 1 e 0.480 SLICE_94.F0 to SLICE_94.A1 N_248_i_1 -CTOF_DEL --- 0.495 SLICE_94.A1 to SLICE_94.F1 SLICE_94 -ROUTE 1 e 1.234 SLICE_94.F1 to *AS_MGIOL.OPOS N_248_i (to RCLK_c) +REG_DEL --- 0.452 SLICE_16.CLK to SLICE_16.Q0 SLICE_16 (from RCLK_c) +ROUTE 12 e 1.234 SLICE_16.Q0 to SLICE_62.D1 CO0 +CTOF_DEL --- 0.495 SLICE_62.D1 to SLICE_62.F1 SLICE_62 +ROUTE 6 e 1.234 SLICE_62.F1 to SLICE_79.A1 IS_0_sqmuxa_0_o2 +CTOF_DEL --- 0.495 SLICE_79.A1 to SLICE_79.F1 SLICE_79 +ROUTE 2 e 1.234 SLICE_79.F1 to SLICE_28.D1 IS_0_sqmuxa_0_o3 +CTOF_DEL --- 0.495 SLICE_28.D1 to SLICE_28.F1 SLICE_28 +ROUTE 1 e 1.234 SLICE_28.F1 to SLICE_68.D1 nRWE_s_i_a2_1_0 +CTOF_DEL --- 0.495 SLICE_68.D1 to SLICE_68.F1 SLICE_68 +ROUTE 1 e 1.234 SLICE_68.F1 to SLICE_75.D0 nRWE_s_i_tz_0 +CTOF_DEL --- 0.495 SLICE_75.D0 to SLICE_75.F0 SLICE_75 +ROUTE 1 e 1.234 SLICE_75.F0 to *WE_MGIOL.OPOS N_252_i (to RCLK_c) -------- - 9.798 (34.9% logic, 65.1% route), 7 logic levels. + 10.331 (28.3% logic, 71.7% route), 6 logic levels. -Report: 100.492MHz is the maximum frequency for this preference. +Report: 95.383MHz is the maximum frequency for this preference. Report Summary -------------- @@ -196,7 +194,7 @@ FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0 | | | FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0 | | | -FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 100.492 MHz| 7 +FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 95.383 MHz| 6 | | | ---------------------------------------------------------------------------- @@ -221,7 +219,7 @@ Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11 Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10 No transfer within this clock domain is found -Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47 +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 48 Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ; Data transfers from: @@ -251,11 +249,11 @@ Clock Domain: PHI2_c Source: PHI2.PAD Loads: 21 Timing errors: 0 Score: 0 Cumulative negative slack: 0 -Constraints cover 1025 paths, 4 nets, and 741 connections (72.86% coverage) +Constraints cover 1038 paths, 4 nets, and 732 connections (72.40% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 -Thu Sep 21 05:39:45 2023 +Sat Nov 18 02:05:54 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -280,7 +278,7 @@ Report level: verbose report, limited to 1 item per preference
  • FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)
    • 0 items scored, 0 timing errors detected. -
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    • 878 items scored, 0 timing errors detected. +
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    • 891 items scored, 0 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS @@ -336,7 +334,7 @@ ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r_0_0 (to ================================================================================ Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; - 878 items scored, 0 timing errors detected. + 891 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- @@ -402,7 +400,7 @@ Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11 Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10 No transfer within this clock domain is found -Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47 +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 48 Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ; Data transfers from: @@ -432,7 +430,7 @@ Clock Domain: PHI2_c Source: PHI2.PAD Loads: 21 Timing errors: 0 Score: 0 Cumulative negative slack: 0 -Constraints cover 1025 paths, 4 nets, and 741 connections (72.86% coverage) +Constraints cover 1038 paths, 4 nets, and 732 connections (72.40% coverage) diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_twr.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_twr.html index ebf44d8..8925379 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_twr.html +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_twr.html @@ -22,7 +22,7 @@ Setup and Hold Report -------------------------------------------------------------------------------- Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 -Thu Sep 21 05:40:01 2023 +Sat Nov 18 02:06:11 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -42,7 +42,7 @@ Report level: verbose report, limited to 10 items per preference Preference Summary
  • FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)
    • 147 items scored, 0 timing errors detected. -Report: 52.949MHz is the maximum frequency for this preference. +Report: 47.068MHz is the maximum frequency for this preference.
  • FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)
    • 0 items scored, 0 timing errors detected. Report: 150.150MHz is the maximum frequency for this preference. @@ -50,8 +50,8 @@ Report: 150.150MHz is the maximum frequency for this preference.
  • FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)
    • 0 items scored, 0 timing errors detected. Report: 150.150MHz is the maximum frequency for this preference. -
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    • 878 items scored, 0 timing errors detected. -Report: 97.771MHz is the maximum frequency for this preference. +
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    • 891 items scored, 0 timing errors detected. +Report: 102.312MHz is the maximum frequency for this preference. BLOCK ASYNCPATHS BLOCK RESETPATHS @@ -65,90 +65,247 @@ BLOCK RESETPATHS -------------------------------------------------------------------------------- -Passed: The following path meets requirements by 162.971ns (weighted slack = 325.942ns) +Passed: The following path meets requirements by 161.791ns (weighted slack = 323.582ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_0io[0] (from PHI2_c +) + Source: FF Q Bank_0io[7] (from PHI2_c +) Destination: FF Data in CmdUFMData (to PHI2_c -) - Delay: 8.963ns (28.5% logic, 71.5% route), 5 logic levels. + Delay: 10.143ns (25.2% logic, 74.8% route), 5 logic levels. Constraint Details: - 8.963ns physical path delay Din[0]_MGIOL to SLICE_82 meets + 10.143ns physical path delay Din[7]_MGIOL to SLICE_19 meets 172.414ns delay constraint less 0.173ns skew and - 0.307ns CE_SET requirement (totaling 171.934ns) by 162.971ns + 0.307ns CE_SET requirement (totaling 171.934ns) by 161.791ns Physical Path Details: - Data path Din[0]_MGIOL to SLICE_82: + Data path Din[7]_MGIOL to SLICE_19: Name Fanout Delay (ns) Site Resource -C2INP_DEL --- 0.577 IOL_L2C.CLK to IOL_L2C.IN Din[0]_MGIOL (from PHI2_c) -ROUTE 1 1.802 IOL_L2C.IN to R3C8A.D0 Bank[0] -CTOF_DEL --- 0.495 R3C8A.D0 to R3C8A.F0 SLICE_93 -ROUTE 1 0.958 R3C8A.F0 to R2C6B.D0 un1_CmdEnable20_0_0_o3_10 -CTOF_DEL --- 0.495 R2C6B.D0 to R2C6B.F0 SLICE_84 -ROUTE 6 1.506 R2C6B.F0 to R3C9D.A1 un1_CmdEnable20_0_0_o3 -CTOF_DEL --- 0.495 R3C9D.A1 to R3C9D.F1 SLICE_23 -ROUTE 8 1.487 R3C9D.F1 to R4C9C.B0 XOR8MEG18 -CTOF_DEL --- 0.495 R4C9C.B0 to R4C9C.F0 SLICE_82 -ROUTE 1 0.653 R4C9C.F0 to R4C9C.CE CmdUFMData_1_sqmuxa (to PHI2_c) +C2INP_DEL --- 0.577 IOL_L2A.CLK to IOL_L2A.IN Din[7]_MGIOL (from PHI2_c) +ROUTE 1 1.995 IOL_L2A.IN to R5C6A.C0 Bank[7] +CTOF_DEL --- 0.495 R5C6A.C0 to R5C6A.F0 SLICE_90 +ROUTE 1 1.299 R5C6A.F0 to R2C6C.A0 un1_CmdEnable20_0_0_o2_10 +CTOF_DEL --- 0.495 R2C6C.A0 to R2C6C.F0 SLICE_80 +ROUTE 6 1.993 R2C6C.F0 to R4C8A.B1 N_367 +CTOF_DEL --- 0.495 R4C8A.B1 to R4C8A.F1 SLICE_23 +ROUTE 8 1.230 R4C8A.F1 to R5C9A.C0 XOR8MEG18 +CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_77 +ROUTE 1 1.069 R5C9A.F0 to R5C10B.CE CmdUFMData_1_sqmuxa (to PHI2_c) -------- - 8.963 (28.5% logic, 71.5% route), 5 logic levels. + 10.143 (25.2% logic, 74.8% route), 5 logic levels. Clock Skew Details: - Source Clock Path PHI2 to Din[0]_MGIOL: + Source Clock Path PHI2 to Din[7]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 21 3.712 8.PADDI to IOL_L2C.CLK PHI2_c +ROUTE 21 3.712 8.PADDI to IOL_L2A.CLK PHI2_c -------- 3.712 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_82: + Destination Clock Path PHI2 to SLICE_19: Name Fanout Delay (ns) Site Resource -ROUTE 21 3.539 8.PADDI to R4C9C.CLK PHI2_c +ROUTE 21 3.539 8.PADDI to R5C10B.CLK PHI2_c -------- 3.539 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 163.277ns (weighted slack = 326.554ns) +Passed: The following path meets requirements by 162.140ns (weighted slack = 324.280ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_0io[7] (from PHI2_c +) + Destination: FF Data in CmdEnable (to PHI2_c -) + + Delay: 9.935ns (30.7% logic, 69.3% route), 6 logic levels. + + Constraint Details: + + 9.935ns physical path delay Din[7]_MGIOL to SLICE_17 meets + 172.414ns delay constraint less + 0.173ns skew and + 0.166ns DIN_SET requirement (totaling 172.075ns) by 162.140ns + + Physical Path Details: + + Data path Din[7]_MGIOL to SLICE_17: + + Name Fanout Delay (ns) Site Resource +C2INP_DEL --- 0.577 IOL_L2A.CLK to IOL_L2A.IN Din[7]_MGIOL (from PHI2_c) +ROUTE 1 1.995 IOL_L2A.IN to R5C6A.C0 Bank[7] +CTOF_DEL --- 0.495 R5C6A.C0 to R5C6A.F0 SLICE_90 +ROUTE 1 1.299 R5C6A.F0 to R2C6C.A0 un1_CmdEnable20_0_0_o2_10 +CTOF_DEL --- 0.495 R2C6C.A0 to R2C6C.F0 SLICE_80 +ROUTE 6 1.188 R2C6C.F0 to R5C8D.D1 N_367 +CTOF_DEL --- 0.495 R5C8D.D1 to R5C8D.F1 SLICE_11 +ROUTE 3 1.102 R5C8D.F1 to R5C5D.C0 CmdEnable16 +CTOF_DEL --- 0.495 R5C5D.C0 to R5C5D.F0 SLICE_33 +ROUTE 1 1.299 R5C5D.F0 to R5C8C.A0 CmdEnable_0_sqmuxa +CTOF_DEL --- 0.495 R5C8C.A0 to R5C8C.F0 SLICE_17 +ROUTE 1 0.000 R5C8C.F0 to R5C8C.DI0 CmdEnable_s (to PHI2_c) + -------- + 9.935 (30.7% logic, 69.3% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to Din[7]_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 3.712 8.PADDI to IOL_L2A.CLK PHI2_c + -------- + 3.712 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_17: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 3.539 8.PADDI to R5C8C.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.411ns (weighted slack = 324.822ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_0io[1] (from PHI2_c +) + Destination: FF Data in CmdUFMData (to PHI2_c -) + + Delay: 9.523ns (26.9% logic, 73.1% route), 5 logic levels. + + Constraint Details: + + 9.523ns physical path delay Din[1]_MGIOL to SLICE_19 meets + 172.414ns delay constraint less + 0.173ns skew and + 0.307ns CE_SET requirement (totaling 171.934ns) by 162.411ns + + Physical Path Details: + + Data path Din[1]_MGIOL to SLICE_19: + + Name Fanout Delay (ns) Site Resource +C2INP_DEL --- 0.577 IOL_T6D.CLK to IOL_T6D.IN Din[1]_MGIOL (from PHI2_c) +ROUTE 1 1.375 IOL_T6D.IN to R5C6A.D0 Bank[1] +CTOF_DEL --- 0.495 R5C6A.D0 to R5C6A.F0 SLICE_90 +ROUTE 1 1.299 R5C6A.F0 to R2C6C.A0 un1_CmdEnable20_0_0_o2_10 +CTOF_DEL --- 0.495 R2C6C.A0 to R2C6C.F0 SLICE_80 +ROUTE 6 1.993 R2C6C.F0 to R4C8A.B1 N_367 +CTOF_DEL --- 0.495 R4C8A.B1 to R4C8A.F1 SLICE_23 +ROUTE 8 1.230 R4C8A.F1 to R5C9A.C0 XOR8MEG18 +CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_77 +ROUTE 1 1.069 R5C9A.F0 to R5C10B.CE CmdUFMData_1_sqmuxa (to PHI2_c) + -------- + 9.523 (26.9% logic, 73.1% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to Din[1]_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 3.712 8.PADDI to IOL_T6D.CLK PHI2_c + -------- + 3.712 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 3.539 8.PADDI to R5C10B.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.760ns (weighted slack = 325.520ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_0io[1] (from PHI2_c +) + Destination: FF Data in CmdEnable (to PHI2_c -) + + Delay: 9.315ns (32.8% logic, 67.2% route), 6 logic levels. + + Constraint Details: + + 9.315ns physical path delay Din[1]_MGIOL to SLICE_17 meets + 172.414ns delay constraint less + 0.173ns skew and + 0.166ns DIN_SET requirement (totaling 172.075ns) by 162.760ns + + Physical Path Details: + + Data path Din[1]_MGIOL to SLICE_17: + + Name Fanout Delay (ns) Site Resource +C2INP_DEL --- 0.577 IOL_T6D.CLK to IOL_T6D.IN Din[1]_MGIOL (from PHI2_c) +ROUTE 1 1.375 IOL_T6D.IN to R5C6A.D0 Bank[1] +CTOF_DEL --- 0.495 R5C6A.D0 to R5C6A.F0 SLICE_90 +ROUTE 1 1.299 R5C6A.F0 to R2C6C.A0 un1_CmdEnable20_0_0_o2_10 +CTOF_DEL --- 0.495 R2C6C.A0 to R2C6C.F0 SLICE_80 +ROUTE 6 1.188 R2C6C.F0 to R5C8D.D1 N_367 +CTOF_DEL --- 0.495 R5C8D.D1 to R5C8D.F1 SLICE_11 +ROUTE 3 1.102 R5C8D.F1 to R5C5D.C0 CmdEnable16 +CTOF_DEL --- 0.495 R5C5D.C0 to R5C5D.F0 SLICE_33 +ROUTE 1 1.299 R5C5D.F0 to R5C8C.A0 CmdEnable_0_sqmuxa +CTOF_DEL --- 0.495 R5C8C.A0 to R5C8C.F0 SLICE_17 +ROUTE 1 0.000 R5C8C.F0 to R5C8C.DI0 CmdEnable_s (to PHI2_c) + -------- + 9.315 (32.8% logic, 67.2% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to Din[1]_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 3.712 8.PADDI to IOL_T6D.CLK PHI2_c + -------- + 3.712 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_17: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 3.539 8.PADDI to R5C8C.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.896ns (weighted slack = 325.792ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Bank_0io[2] (from PHI2_c +) Destination: FF Data in CmdUFMData (to PHI2_c -) - Delay: 8.657ns (29.5% logic, 70.5% route), 5 logic levels. + Delay: 9.038ns (28.3% logic, 71.7% route), 5 logic levels. Constraint Details: - 8.657ns physical path delay Din[2]_MGIOL to SLICE_82 meets + 9.038ns physical path delay Din[2]_MGIOL to SLICE_19 meets 172.414ns delay constraint less 0.173ns skew and - 0.307ns CE_SET requirement (totaling 171.934ns) by 163.277ns + 0.307ns CE_SET requirement (totaling 171.934ns) by 162.896ns Physical Path Details: - Data path Din[2]_MGIOL to SLICE_82: + Data path Din[2]_MGIOL to SLICE_19: Name Fanout Delay (ns) Site Resource C2INP_DEL --- 0.577 IOL_T9A.CLK to IOL_T9A.IN Din[2]_MGIOL (from PHI2_c) -ROUTE 1 1.496 IOL_T9A.IN to R3C8A.C0 Bank[2] -CTOF_DEL --- 0.495 R3C8A.C0 to R3C8A.F0 SLICE_93 -ROUTE 1 0.958 R3C8A.F0 to R2C6B.D0 un1_CmdEnable20_0_0_o3_10 -CTOF_DEL --- 0.495 R2C6B.D0 to R2C6B.F0 SLICE_84 -ROUTE 6 1.506 R2C6B.F0 to R3C9D.A1 un1_CmdEnable20_0_0_o3 -CTOF_DEL --- 0.495 R3C9D.A1 to R3C9D.F1 SLICE_23 -ROUTE 8 1.487 R3C9D.F1 to R4C9C.B0 XOR8MEG18 -CTOF_DEL --- 0.495 R4C9C.B0 to R4C9C.F0 SLICE_82 -ROUTE 1 0.653 R4C9C.F0 to R4C9C.CE CmdUFMData_1_sqmuxa (to PHI2_c) +ROUTE 1 1.753 IOL_T9A.IN to R2C6C.B1 Bank[2] +CTOF_DEL --- 0.495 R2C6C.B1 to R2C6C.F1 SLICE_80 +ROUTE 1 0.436 R2C6C.F1 to R2C6C.C0 un1_CmdEnable20_0_0_o2_11 +CTOF_DEL --- 0.495 R2C6C.C0 to R2C6C.F0 SLICE_80 +ROUTE 6 1.993 R2C6C.F0 to R4C8A.B1 N_367 +CTOF_DEL --- 0.495 R4C8A.B1 to R4C8A.F1 SLICE_23 +ROUTE 8 1.230 R4C8A.F1 to R5C9A.C0 XOR8MEG18 +CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_77 +ROUTE 1 1.069 R5C9A.F0 to R5C10B.CE CmdUFMData_1_sqmuxa (to PHI2_c) -------- - 8.657 (29.5% logic, 70.5% route), 5 logic levels. + 9.038 (28.3% logic, 71.7% route), 5 logic levels. Clock Skew Details: @@ -159,209 +316,209 @@ ROUTE 21 3.712 8.PADDI to IOL_T9A.CLK PHI2_c -------- 3.712 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_82: + Destination Clock Path PHI2 to SLICE_19: Name Fanout Delay (ns) Site Resource -ROUTE 21 3.539 8.PADDI to R4C9C.CLK PHI2_c +ROUTE 21 3.539 8.PADDI to R5C10B.CLK PHI2_c -------- 3.539 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 163.351ns (weighted slack = 326.702ns) +Passed: The following path meets requirements by 163.153ns (weighted slack = 326.306ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_0io[5] (from PHI2_c +) + Source: FF Q Bank_0io[6] (from PHI2_c +) Destination: FF Data in CmdUFMData (to PHI2_c -) - Delay: 8.583ns (29.8% logic, 70.2% route), 5 logic levels. + Delay: 8.781ns (29.1% logic, 70.9% route), 5 logic levels. Constraint Details: - 8.583ns physical path delay Din[5]_MGIOL to SLICE_82 meets + 8.781ns physical path delay Din[6]_MGIOL to SLICE_19 meets 172.414ns delay constraint less 0.173ns skew and - 0.307ns CE_SET requirement (totaling 171.934ns) by 163.351ns + 0.307ns CE_SET requirement (totaling 171.934ns) by 163.153ns Physical Path Details: - Data path Din[5]_MGIOL to SLICE_82: + Data path Din[6]_MGIOL to SLICE_19: Name Fanout Delay (ns) Site Resource -C2INP_DEL --- 0.577 IOL_T6B.CLK to IOL_T6B.IN Din[5]_MGIOL (from PHI2_c) -ROUTE 1 1.944 IOL_T6B.IN to R2C6B.A1 Bank[5] -CTOF_DEL --- 0.495 R2C6B.A1 to R2C6B.F1 SLICE_84 -ROUTE 1 0.436 R2C6B.F1 to R2C6B.C0 un1_CmdEnable20_0_0_o3_11 -CTOF_DEL --- 0.495 R2C6B.C0 to R2C6B.F0 SLICE_84 -ROUTE 6 1.506 R2C6B.F0 to R3C9D.A1 un1_CmdEnable20_0_0_o3 -CTOF_DEL --- 0.495 R3C9D.A1 to R3C9D.F1 SLICE_23 -ROUTE 8 1.487 R3C9D.F1 to R4C9C.B0 XOR8MEG18 -CTOF_DEL --- 0.495 R4C9C.B0 to R4C9C.F0 SLICE_82 -ROUTE 1 0.653 R4C9C.F0 to R4C9C.CE CmdUFMData_1_sqmuxa (to PHI2_c) +C2INP_DEL --- 0.577 IOL_L2B.CLK to IOL_L2B.IN Din[6]_MGIOL (from PHI2_c) +ROUTE 1 1.496 IOL_L2B.IN to R2C6C.C1 Bank[6] +CTOF_DEL --- 0.495 R2C6C.C1 to R2C6C.F1 SLICE_80 +ROUTE 1 0.436 R2C6C.F1 to R2C6C.C0 un1_CmdEnable20_0_0_o2_11 +CTOF_DEL --- 0.495 R2C6C.C0 to R2C6C.F0 SLICE_80 +ROUTE 6 1.993 R2C6C.F0 to R4C8A.B1 N_367 +CTOF_DEL --- 0.495 R4C8A.B1 to R4C8A.F1 SLICE_23 +ROUTE 8 1.230 R4C8A.F1 to R5C9A.C0 XOR8MEG18 +CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_77 +ROUTE 1 1.069 R5C9A.F0 to R5C10B.CE CmdUFMData_1_sqmuxa (to PHI2_c) -------- - 8.583 (29.8% logic, 70.2% route), 5 logic levels. + 8.781 (29.1% logic, 70.9% route), 5 logic levels. Clock Skew Details: - Source Clock Path PHI2 to Din[5]_MGIOL: + Source Clock Path PHI2 to Din[6]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 21 3.712 8.PADDI to IOL_T6B.CLK PHI2_c +ROUTE 21 3.712 8.PADDI to IOL_L2B.CLK PHI2_c -------- 3.712 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_82: + Destination Clock Path PHI2 to SLICE_19: Name Fanout Delay (ns) Site Resource -ROUTE 21 3.539 8.PADDI to R4C9C.CLK PHI2_c +ROUTE 21 3.539 8.PADDI to R5C10B.CLK PHI2_c -------- 3.539 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 163.564ns (weighted slack = 327.128ns) +Passed: The following path meets requirements by 163.245ns (weighted slack = 326.490ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_0io[0] (from PHI2_c +) + Source: FF Q Bank_0io[2] (from PHI2_c +) Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 8.511ns (35.9% logic, 64.1% route), 6 logic levels. + Delay: 8.830ns (34.6% logic, 65.4% route), 6 logic levels. Constraint Details: - 8.511ns physical path delay Din[0]_MGIOL to SLICE_17 meets + 8.830ns physical path delay Din[2]_MGIOL to SLICE_17 meets 172.414ns delay constraint less 0.173ns skew and - 0.166ns DIN_SET requirement (totaling 172.075ns) by 163.564ns + 0.166ns DIN_SET requirement (totaling 172.075ns) by 163.245ns Physical Path Details: - Data path Din[0]_MGIOL to SLICE_17: + Data path Din[2]_MGIOL to SLICE_17: Name Fanout Delay (ns) Site Resource -C2INP_DEL --- 0.577 IOL_L2C.CLK to IOL_L2C.IN Din[0]_MGIOL (from PHI2_c) -ROUTE 1 1.802 IOL_L2C.IN to R3C8A.D0 Bank[0] -CTOF_DEL --- 0.495 R3C8A.D0 to R3C8A.F0 SLICE_93 -ROUTE 1 0.958 R3C8A.F0 to R2C6B.D0 un1_CmdEnable20_0_0_o3_10 -CTOF_DEL --- 0.495 R2C6B.D0 to R2C6B.F0 SLICE_84 -ROUTE 6 1.617 R2C6B.F0 to R4C11D.D1 un1_CmdEnable20_0_0_o3 -CTOF_DEL --- 0.495 R4C11D.D1 to R4C11D.F1 SLICE_11 -ROUTE 3 0.767 R4C11D.F1 to R3C11D.C0 CmdEnable16 -CTOF_DEL --- 0.495 R3C11D.C0 to R3C11D.F0 SLICE_33 -ROUTE 1 0.315 R3C11D.F0 to R3C11C.D0 CmdEnable_0_sqmuxa -CTOF_DEL --- 0.495 R3C11C.D0 to R3C11C.F0 SLICE_17 -ROUTE 1 0.000 R3C11C.F0 to R3C11C.DI0 CmdEnable_s (to PHI2_c) +C2INP_DEL --- 0.577 IOL_T9A.CLK to IOL_T9A.IN Din[2]_MGIOL (from PHI2_c) +ROUTE 1 1.753 IOL_T9A.IN to R2C6C.B1 Bank[2] +CTOF_DEL --- 0.495 R2C6C.B1 to R2C6C.F1 SLICE_80 +ROUTE 1 0.436 R2C6C.F1 to R2C6C.C0 un1_CmdEnable20_0_0_o2_11 +CTOF_DEL --- 0.495 R2C6C.C0 to R2C6C.F0 SLICE_80 +ROUTE 6 1.188 R2C6C.F0 to R5C8D.D1 N_367 +CTOF_DEL --- 0.495 R5C8D.D1 to R5C8D.F1 SLICE_11 +ROUTE 3 1.102 R5C8D.F1 to R5C5D.C0 CmdEnable16 +CTOF_DEL --- 0.495 R5C5D.C0 to R5C5D.F0 SLICE_33 +ROUTE 1 1.299 R5C5D.F0 to R5C8C.A0 CmdEnable_0_sqmuxa +CTOF_DEL --- 0.495 R5C8C.A0 to R5C8C.F0 SLICE_17 +ROUTE 1 0.000 R5C8C.F0 to R5C8C.DI0 CmdEnable_s (to PHI2_c) -------- - 8.511 (35.9% logic, 64.1% route), 6 logic levels. + 8.830 (34.6% logic, 65.4% route), 6 logic levels. Clock Skew Details: - Source Clock Path PHI2 to Din[0]_MGIOL: + Source Clock Path PHI2 to Din[2]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 21 3.712 8.PADDI to IOL_L2C.CLK PHI2_c +ROUTE 21 3.712 8.PADDI to IOL_T9A.CLK PHI2_c -------- 3.712 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_17: Name Fanout Delay (ns) Site Resource -ROUTE 21 3.539 8.PADDI to R3C11C.CLK PHI2_c +ROUTE 21 3.539 8.PADDI to R5C8C.CLK PHI2_c -------- 3.539 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 163.740ns (weighted slack = 327.480ns) +Passed: The following path meets requirements by 163.389ns (weighted slack = 326.778ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_0io[0] (from PHI2_c +) - Destination: FF Data in CmdEnable (to PHI2_c -) + Source: FF Q Bank_0io[3] (from PHI2_c +) + Destination: FF Data in CmdUFMData (to PHI2_c -) - Delay: 8.335ns (30.7% logic, 69.3% route), 5 logic levels. + Delay: 8.545ns (29.9% logic, 70.1% route), 5 logic levels. Constraint Details: - 8.335ns physical path delay Din[0]_MGIOL to SLICE_17 meets + 8.545ns physical path delay Din[3]_MGIOL to SLICE_19 meets 172.414ns delay constraint less 0.173ns skew and - 0.166ns DIN_SET requirement (totaling 172.075ns) by 163.740ns + 0.307ns CE_SET requirement (totaling 171.934ns) by 163.389ns Physical Path Details: - Data path Din[0]_MGIOL to SLICE_17: + Data path Din[3]_MGIOL to SLICE_19: Name Fanout Delay (ns) Site Resource -C2INP_DEL --- 0.577 IOL_L2C.CLK to IOL_L2C.IN Din[0]_MGIOL (from PHI2_c) -ROUTE 1 1.802 IOL_L2C.IN to R3C8A.D0 Bank[0] -CTOF_DEL --- 0.495 R3C8A.D0 to R3C8A.F0 SLICE_93 -ROUTE 1 0.958 R3C8A.F0 to R2C6B.D0 un1_CmdEnable20_0_0_o3_10 -CTOF_DEL --- 0.495 R2C6B.D0 to R2C6B.F0 SLICE_84 -ROUTE 6 1.995 R2C6B.F0 to R4C11B.B0 un1_CmdEnable20_0_0_o3 -CTOF_DEL --- 0.495 R4C11B.B0 to R4C11B.F0 SLICE_80 -ROUTE 1 1.023 R4C11B.F0 to R3C11C.B0 un1_CmdEnable20_i -CTOF_DEL --- 0.495 R3C11C.B0 to R3C11C.F0 SLICE_17 -ROUTE 1 0.000 R3C11C.F0 to R3C11C.DI0 CmdEnable_s (to PHI2_c) +C2INP_DEL --- 0.577 IOL_T6C.CLK to IOL_T6C.IN Din[3]_MGIOL (from PHI2_c) +ROUTE 1 1.260 IOL_T6C.IN to R2C6C.D1 Bank[3] +CTOF_DEL --- 0.495 R2C6C.D1 to R2C6C.F1 SLICE_80 +ROUTE 1 0.436 R2C6C.F1 to R2C6C.C0 un1_CmdEnable20_0_0_o2_11 +CTOF_DEL --- 0.495 R2C6C.C0 to R2C6C.F0 SLICE_80 +ROUTE 6 1.993 R2C6C.F0 to R4C8A.B1 N_367 +CTOF_DEL --- 0.495 R4C8A.B1 to R4C8A.F1 SLICE_23 +ROUTE 8 1.230 R4C8A.F1 to R5C9A.C0 XOR8MEG18 +CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_77 +ROUTE 1 1.069 R5C9A.F0 to R5C10B.CE CmdUFMData_1_sqmuxa (to PHI2_c) -------- - 8.335 (30.7% logic, 69.3% route), 5 logic levels. + 8.545 (29.9% logic, 70.1% route), 5 logic levels. Clock Skew Details: - Source Clock Path PHI2 to Din[0]_MGIOL: + Source Clock Path PHI2 to Din[3]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 21 3.712 8.PADDI to IOL_L2C.CLK PHI2_c +ROUTE 21 3.712 8.PADDI to IOL_T6C.CLK PHI2_c -------- 3.712 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_17: + Destination Clock Path PHI2 to SLICE_19: Name Fanout Delay (ns) Site Resource -ROUTE 21 3.539 8.PADDI to R3C11C.CLK PHI2_c +ROUTE 21 3.539 8.PADDI to R5C10B.CLK PHI2_c -------- 3.539 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 163.802ns (weighted slack = 327.604ns) +Passed: The following path meets requirements by 163.435ns (weighted slack = 326.870ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_0io[0] (from PHI2_c +) + Source: FF Q Bank_0io[7] (from PHI2_c +) Destination: FF Data in CmdValid (to PHI2_c -) - Delay: 8.273ns (30.9% logic, 69.1% route), 5 logic levels. + Delay: 8.640ns (29.6% logic, 70.4% route), 5 logic levels. Constraint Details: - 8.273ns physical path delay Din[0]_MGIOL to SLICE_22 meets + 8.640ns physical path delay Din[7]_MGIOL to SLICE_22 meets 172.414ns delay constraint less 0.173ns skew and - 0.166ns DIN_SET requirement (totaling 172.075ns) by 163.802ns + 0.166ns DIN_SET requirement (totaling 172.075ns) by 163.435ns Physical Path Details: - Data path Din[0]_MGIOL to SLICE_22: + Data path Din[7]_MGIOL to SLICE_22: Name Fanout Delay (ns) Site Resource -C2INP_DEL --- 0.577 IOL_L2C.CLK to IOL_L2C.IN Din[0]_MGIOL (from PHI2_c) -ROUTE 1 1.802 IOL_L2C.IN to R3C8A.D0 Bank[0] -CTOF_DEL --- 0.495 R3C8A.D0 to R3C8A.F0 SLICE_93 -ROUTE 1 0.958 R3C8A.F0 to R2C6B.D0 un1_CmdEnable20_0_0_o3_10 -CTOF_DEL --- 0.495 R2C6B.D0 to R2C6B.F0 SLICE_84 -ROUTE 6 1.506 R2C6B.F0 to R3C9D.A1 un1_CmdEnable20_0_0_o3 -CTOF_DEL --- 0.495 R3C9D.A1 to R3C9D.F1 SLICE_23 -ROUTE 8 1.450 R3C9D.F1 to R4C9D.A0 XOR8MEG18 -CTOF_DEL --- 0.495 R4C9D.A0 to R4C9D.F0 SLICE_22 +C2INP_DEL --- 0.577 IOL_L2A.CLK to IOL_L2A.IN Din[7]_MGIOL (from PHI2_c) +ROUTE 1 1.995 IOL_L2A.IN to R5C6A.C0 Bank[7] +CTOF_DEL --- 0.495 R5C6A.C0 to R5C6A.F0 SLICE_90 +ROUTE 1 1.299 R5C6A.F0 to R2C6C.A0 un1_CmdEnable20_0_0_o2_10 +CTOF_DEL --- 0.495 R2C6C.A0 to R2C6C.F0 SLICE_80 +ROUTE 6 1.993 R2C6C.F0 to R4C8A.B1 N_367 +CTOF_DEL --- 0.495 R4C8A.B1 to R4C8A.F1 SLICE_23 +ROUTE 8 0.796 R4C8A.F1 to R4C9D.C0 XOR8MEG18 +CTOF_DEL --- 0.495 R4C9D.C0 to R4C9D.F0 SLICE_22 ROUTE 1 0.000 R4C9D.F0 to R4C9D.DI0 CmdValid_r (to PHI2_c) -------- - 8.273 (30.9% logic, 69.1% route), 5 logic levels. + 8.640 (29.6% logic, 70.4% route), 5 logic levels. Clock Skew Details: - Source Clock Path PHI2 to Din[0]_MGIOL: + Source Clock Path PHI2 to Din[7]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 21 3.712 8.PADDI to IOL_L2C.CLK PHI2_c +ROUTE 21 3.712 8.PADDI to IOL_L2A.CLK PHI2_c -------- 3.712 (0.0% logic, 100.0% route), 0 logic levels. @@ -373,94 +530,39 @@ ROUTE 21 3.539 8.PADDI to R4C9D.CLK PHI2_c 3.539 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 163.870ns (weighted slack = 327.740ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_0io[2] (from PHI2_c +) - Destination: FF Data in CmdEnable (to PHI2_c -) - - Delay: 8.205ns (37.2% logic, 62.8% route), 6 logic levels. - - Constraint Details: - - 8.205ns physical path delay Din[2]_MGIOL to SLICE_17 meets - 172.414ns delay constraint less - 0.173ns skew and - 0.166ns DIN_SET requirement (totaling 172.075ns) by 163.870ns - - Physical Path Details: - - Data path Din[2]_MGIOL to SLICE_17: - - Name Fanout Delay (ns) Site Resource -C2INP_DEL --- 0.577 IOL_T9A.CLK to IOL_T9A.IN Din[2]_MGIOL (from PHI2_c) -ROUTE 1 1.496 IOL_T9A.IN to R3C8A.C0 Bank[2] -CTOF_DEL --- 0.495 R3C8A.C0 to R3C8A.F0 SLICE_93 -ROUTE 1 0.958 R3C8A.F0 to R2C6B.D0 un1_CmdEnable20_0_0_o3_10 -CTOF_DEL --- 0.495 R2C6B.D0 to R2C6B.F0 SLICE_84 -ROUTE 6 1.617 R2C6B.F0 to R4C11D.D1 un1_CmdEnable20_0_0_o3 -CTOF_DEL --- 0.495 R4C11D.D1 to R4C11D.F1 SLICE_11 -ROUTE 3 0.767 R4C11D.F1 to R3C11D.C0 CmdEnable16 -CTOF_DEL --- 0.495 R3C11D.C0 to R3C11D.F0 SLICE_33 -ROUTE 1 0.315 R3C11D.F0 to R3C11C.D0 CmdEnable_0_sqmuxa -CTOF_DEL --- 0.495 R3C11C.D0 to R3C11C.F0 SLICE_17 -ROUTE 1 0.000 R3C11C.F0 to R3C11C.DI0 CmdEnable_s (to PHI2_c) - -------- - 8.205 (37.2% logic, 62.8% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to Din[2]_MGIOL: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 3.712 8.PADDI to IOL_T9A.CLK PHI2_c - -------- - 3.712 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_17: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 3.539 8.PADDI to R3C11C.CLK PHI2_c - -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 163.944ns (weighted slack = 327.888ns) +Passed: The following path meets requirements by 163.445ns (weighted slack = 326.890ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Bank_0io[5] (from PHI2_c +) - Destination: FF Data in CmdEnable (to PHI2_c -) + Destination: FF Data in CmdUFMData (to PHI2_c -) - Delay: 8.131ns (37.5% logic, 62.5% route), 6 logic levels. + Delay: 8.489ns (30.1% logic, 69.9% route), 5 logic levels. Constraint Details: - 8.131ns physical path delay Din[5]_MGIOL to SLICE_17 meets + 8.489ns physical path delay Din[5]_MGIOL to SLICE_19 meets 172.414ns delay constraint less 0.173ns skew and - 0.166ns DIN_SET requirement (totaling 172.075ns) by 163.944ns + 0.307ns CE_SET requirement (totaling 171.934ns) by 163.445ns Physical Path Details: - Data path Din[5]_MGIOL to SLICE_17: + Data path Din[5]_MGIOL to SLICE_19: Name Fanout Delay (ns) Site Resource C2INP_DEL --- 0.577 IOL_T6B.CLK to IOL_T6B.IN Din[5]_MGIOL (from PHI2_c) -ROUTE 1 1.944 IOL_T6B.IN to R2C6B.A1 Bank[5] -CTOF_DEL --- 0.495 R2C6B.A1 to R2C6B.F1 SLICE_84 -ROUTE 1 0.436 R2C6B.F1 to R2C6B.C0 un1_CmdEnable20_0_0_o3_11 -CTOF_DEL --- 0.495 R2C6B.C0 to R2C6B.F0 SLICE_84 -ROUTE 6 1.617 R2C6B.F0 to R4C11D.D1 un1_CmdEnable20_0_0_o3 -CTOF_DEL --- 0.495 R4C11D.D1 to R4C11D.F1 SLICE_11 -ROUTE 3 0.767 R4C11D.F1 to R3C11D.C0 CmdEnable16 -CTOF_DEL --- 0.495 R3C11D.C0 to R3C11D.F0 SLICE_33 -ROUTE 1 0.315 R3C11D.F0 to R3C11C.D0 CmdEnable_0_sqmuxa -CTOF_DEL --- 0.495 R3C11C.D0 to R3C11C.F0 SLICE_17 -ROUTE 1 0.000 R3C11C.F0 to R3C11C.DI0 CmdEnable_s (to PHI2_c) +ROUTE 1 1.204 IOL_T6B.IN to R2C6C.A1 Bank[5] +CTOF_DEL --- 0.495 R2C6C.A1 to R2C6C.F1 SLICE_80 +ROUTE 1 0.436 R2C6C.F1 to R2C6C.C0 un1_CmdEnable20_0_0_o2_11 +CTOF_DEL --- 0.495 R2C6C.C0 to R2C6C.F0 SLICE_80 +ROUTE 6 1.993 R2C6C.F0 to R4C8A.B1 N_367 +CTOF_DEL --- 0.495 R4C8A.B1 to R4C8A.F1 SLICE_23 +ROUTE 8 1.230 R4C8A.F1 to R5C9A.C0 XOR8MEG18 +CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_77 +ROUTE 1 1.069 R5C9A.F0 to R5C10B.CE CmdUFMData_1_sqmuxa (to PHI2_c) -------- - 8.131 (37.5% logic, 62.5% route), 6 logic levels. + 8.489 (30.1% logic, 69.9% route), 5 logic levels. Clock Skew Details: @@ -471,116 +573,14 @@ ROUTE 21 3.712 8.PADDI to IOL_T6B.CLK PHI2_c -------- 3.712 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_17: + Destination Clock Path PHI2 to SLICE_19: Name Fanout Delay (ns) Site Resource -ROUTE 21 3.539 8.PADDI to R3C11C.CLK PHI2_c +ROUTE 21 3.539 8.PADDI to R5C10B.CLK PHI2_c -------- 3.539 (0.0% logic, 100.0% route), 0 logic levels. - -Passed: The following path meets requirements by 164.035ns (weighted slack = 328.070ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_0io[1] (from PHI2_c +) - Destination: FF Data in CmdUFMData (to PHI2_c -) - - Delay: 7.899ns (32.4% logic, 67.6% route), 5 logic levels. - - Constraint Details: - - 7.899ns physical path delay Din[1]_MGIOL to SLICE_82 meets - 172.414ns delay constraint less - 0.173ns skew and - 0.307ns CE_SET requirement (totaling 171.934ns) by 164.035ns - - Physical Path Details: - - Data path Din[1]_MGIOL to SLICE_82: - - Name Fanout Delay (ns) Site Resource -C2INP_DEL --- 0.577 IOL_T6D.CLK to IOL_T6D.IN Din[1]_MGIOL (from PHI2_c) -ROUTE 1 1.260 IOL_T6D.IN to R2C6B.D1 Bank[1] -CTOF_DEL --- 0.495 R2C6B.D1 to R2C6B.F1 SLICE_84 -ROUTE 1 0.436 R2C6B.F1 to R2C6B.C0 un1_CmdEnable20_0_0_o3_11 -CTOF_DEL --- 0.495 R2C6B.C0 to R2C6B.F0 SLICE_84 -ROUTE 6 1.506 R2C6B.F0 to R3C9D.A1 un1_CmdEnable20_0_0_o3 -CTOF_DEL --- 0.495 R3C9D.A1 to R3C9D.F1 SLICE_23 -ROUTE 8 1.487 R3C9D.F1 to R4C9C.B0 XOR8MEG18 -CTOF_DEL --- 0.495 R4C9C.B0 to R4C9C.F0 SLICE_82 -ROUTE 1 0.653 R4C9C.F0 to R4C9C.CE CmdUFMData_1_sqmuxa (to PHI2_c) - -------- - 7.899 (32.4% logic, 67.6% route), 5 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to Din[1]_MGIOL: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 3.712 8.PADDI to IOL_T6D.CLK PHI2_c - -------- - 3.712 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_82: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 3.539 8.PADDI to R4C9C.CLK PHI2_c - -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 164.044ns (weighted slack = 328.088ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_0io[0] (from PHI2_c +) - Destination: FF Data in ADSubmitted (to PHI2_c -) - - Delay: 8.031ns (31.8% logic, 68.2% route), 5 logic levels. - - Constraint Details: - - 8.031ns physical path delay Din[0]_MGIOL to SLICE_10 meets - 172.414ns delay constraint less - 0.173ns skew and - 0.166ns DIN_SET requirement (totaling 172.075ns) by 164.044ns - - Physical Path Details: - - Data path Din[0]_MGIOL to SLICE_10: - - Name Fanout Delay (ns) Site Resource -C2INP_DEL --- 0.577 IOL_L2C.CLK to IOL_L2C.IN Din[0]_MGIOL (from PHI2_c) -ROUTE 1 1.802 IOL_L2C.IN to R3C8A.D0 Bank[0] -CTOF_DEL --- 0.495 R3C8A.D0 to R3C8A.F0 SLICE_93 -ROUTE 1 0.958 R3C8A.F0 to R2C6B.D0 un1_CmdEnable20_0_0_o3_10 -CTOF_DEL --- 0.495 R2C6B.D0 to R2C6B.F0 SLICE_84 -ROUTE 6 1.958 R2C6B.F0 to R3C11C.A1 un1_CmdEnable20_0_0_o3 -CTOF_DEL --- 0.495 R3C11C.A1 to R3C11C.F1 SLICE_17 -ROUTE 2 0.756 R3C11C.F1 to R3C11A.C0 CmdEnable17 -CTOF_DEL --- 0.495 R3C11A.C0 to R3C11A.F0 SLICE_10 -ROUTE 1 0.000 R3C11A.F0 to R3C11A.DI0 ADSubmitted_r_0_0 (to PHI2_c) - -------- - 8.031 (31.8% logic, 68.2% route), 5 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to Din[0]_MGIOL: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 3.712 8.PADDI to IOL_L2C.CLK PHI2_c - -------- - 3.712 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_10: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 3.539 8.PADDI to R3C11A.CLK PHI2_c - -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. - -Report: 52.949MHz is the maximum frequency for this preference. +Report: 47.068MHz is the maximum frequency for this preference. ================================================================================ @@ -621,25 +621,88 @@ Report: 150.150MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; - 878 items scored, 0 timing errors detected. + 891 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- -Passed: The following path meets requirements by 5.772ns +Passed: The following path meets requirements by 6.226ns + The internal maximum frequency of the following component is 102.312 MHz + + Logical Details: Cell type Pin name Component name + + Destination: EFB WBCLKI ufmefb/EFBInst_0 + + Delay: 9.774ns -- based on Minimum Pulse Width + + +Passed: The following path meets requirements by 6.245ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[14] (from RCLK_c +) + Destination: FF Data in wb_dati[1] (to RCLK_c +) + + Delay: 9.589ns (30.5% logic, 69.5% route), 6 logic levels. + + Constraint Details: + + 9.589ns physical path delay SLICE_3 to SLICE_52 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 15.834ns) by 6.245ns + + Physical Path Details: + + Data path SLICE_3 to SLICE_52: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R6C3D.CLK to R6C3D.Q1 SLICE_3 (from RCLK_c) +ROUTE 19 2.021 R6C3D.Q1 to R3C4C.D1 FS[14] +CTOF_DEL --- 0.495 R3C4C.D1 to R3C4C.F1 SLICE_118 +ROUTE 2 1.392 R3C4C.F1 to R4C4C.A0 wb_dati_5_1_iv_0_a2_7[4] +CTOF_DEL --- 0.495 R4C4C.A0 to R4C4C.F0 SLICE_97 +ROUTE 1 0.967 R4C4C.F0 to R4C4A.A0 wb_dati_5_1_iv_0_a2_0_2[1] +CTOF_DEL --- 0.495 R4C4A.A0 to R4C4A.F0 SLICE_64 +ROUTE 1 1.535 R4C4A.F0 to R2C4B.B0 wb_dati_5_1_iv_0_0[1] +CTOF_DEL --- 0.495 R2C4B.B0 to R2C4B.F0 SLICE_85 +ROUTE 1 0.747 R2C4B.F0 to R2C4C.C1 wb_dati_5_1_iv_0_1[1] +CTOF_DEL --- 0.495 R2C4C.C1 to R2C4C.F1 SLICE_52 +ROUTE 1 0.000 R2C4C.F1 to R2C4C.DI1 wb_dati_5[1] (to RCLK_c) + -------- + 9.589 (30.5% logic, 69.5% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.019 63.PADDI to R6C3D.CLK RCLK_c + -------- + 2.019 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_52: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.019 63.PADDI to R2C4C.CLK RCLK_c + -------- + 2.019 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 6.252ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: EFB Port ufmefb/EFBInst_0(ASIC) (from RCLK_c +) Destination: FF Data in n8MEGEN (to RCLK_c +) - Delay: 9.889ns (73.5% logic, 26.5% route), 3 logic levels. + Delay: 9.409ns (77.2% logic, 22.8% route), 3 logic levels. Constraint Details: - 9.889ns physical path delay ufmefb/EFBInst_0 to SLICE_45 meets + 9.409ns physical path delay ufmefb/EFBInst_0 to SLICE_45 meets 16.000ns delay constraint less 0.173ns skew and - 0.166ns DIN_SET requirement (totaling 15.661ns) by 5.772ns + 0.166ns DIN_SET requirement (totaling 15.661ns) by 6.252ns Physical Path Details: @@ -647,46 +710,99 @@ Passed: The following path meets requirements by 5.772ns Name Fanout Delay (ns) Site Resource WCLKI2WBDA --- 6.278 EFB.WBCLKI to EFB.WBDATO0 ufmefb/EFBInst_0 (from RCLK_c) -ROUTE 1 1.995 EFB.WBDATO0 to R4C8D.C1 wb_dato[0] -CTOF_DEL --- 0.495 R4C8D.C1 to R4C8D.F1 SLICE_122 -ROUTE 1 0.626 R4C8D.F1 to R4C8C.D0 n8MEGENe_1_0 -CTOF_DEL --- 0.495 R4C8C.D0 to R4C8C.F0 SLICE_45 -ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 n8MEGENe_0 (to RCLK_c) +ROUTE 1 0.984 EFB.WBDATO0 to R3C3A.C1 wb_dato[0] +CTOF_DEL --- 0.495 R3C3A.C1 to R3C3A.F1 SLICE_111 +ROUTE 1 1.157 R3C3A.F1 to R4C6D.D0 n8MEGENe_1_0 +CTOF_DEL --- 0.495 R4C6D.D0 to R4C6D.F0 SLICE_45 +ROUTE 1 0.000 R4C6D.F0 to R4C6D.DI0 n8MEGENe_0 (to RCLK_c) -------- - 9.889 (73.5% logic, 26.5% route), 3 logic levels. + 9.409 (77.2% logic, 22.8% route), 3 logic levels. Clock Skew Details: Source Clock Path RCLK to ufmefb/EFBInst_0: Name Fanout Delay (ns) Site Resource -ROUTE 47 2.192 63.PADDI to EFB.WBCLKI RCLK_c +ROUTE 48 2.192 63.PADDI to EFB.WBCLKI RCLK_c -------- 2.192 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_45: Name Fanout Delay (ns) Site Resource -ROUTE 47 2.019 63.PADDI to R4C8C.CLK RCLK_c +ROUTE 48 2.019 63.PADDI to R4C6D.CLK RCLK_c -------- 2.019 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 6.522ns +Passed: The following path meets requirements by 6.570ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[12] (from RCLK_c +) + Destination: FF Data in wb_dati[1] (to RCLK_c +) + + Delay: 9.264ns (31.6% logic, 68.4% route), 6 logic levels. + + Constraint Details: + + 9.264ns physical path delay SLICE_4 to SLICE_52 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 15.834ns) by 6.570ns + + Physical Path Details: + + Data path SLICE_4 to SLICE_52: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R6C3C.CLK to R6C3C.Q1 SLICE_4 (from RCLK_c) +ROUTE 19 1.696 R6C3C.Q1 to R3C4C.C1 FS[12] +CTOF_DEL --- 0.495 R3C4C.C1 to R3C4C.F1 SLICE_118 +ROUTE 2 1.392 R3C4C.F1 to R4C4C.A0 wb_dati_5_1_iv_0_a2_7[4] +CTOF_DEL --- 0.495 R4C4C.A0 to R4C4C.F0 SLICE_97 +ROUTE 1 0.967 R4C4C.F0 to R4C4A.A0 wb_dati_5_1_iv_0_a2_0_2[1] +CTOF_DEL --- 0.495 R4C4A.A0 to R4C4A.F0 SLICE_64 +ROUTE 1 1.535 R4C4A.F0 to R2C4B.B0 wb_dati_5_1_iv_0_0[1] +CTOF_DEL --- 0.495 R2C4B.B0 to R2C4B.F0 SLICE_85 +ROUTE 1 0.747 R2C4B.F0 to R2C4C.C1 wb_dati_5_1_iv_0_1[1] +CTOF_DEL --- 0.495 R2C4C.C1 to R2C4C.F1 SLICE_52 +ROUTE 1 0.000 R2C4C.F1 to R2C4C.DI1 wb_dati_5[1] (to RCLK_c) + -------- + 9.264 (31.6% logic, 68.4% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_4: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.019 63.PADDI to R6C3C.CLK RCLK_c + -------- + 2.019 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_52: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.019 63.PADDI to R2C4C.CLK RCLK_c + -------- + 2.019 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 6.779ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: EFB Port ufmefb/EFBInst_0(ASIC) (from RCLK_c +) Destination: FF Data in LEDEN (to RCLK_c +) - Delay: 9.139ns (70.6% logic, 29.4% route), 3 logic levels. + Delay: 8.882ns (72.6% logic, 27.4% route), 3 logic levels. Constraint Details: - 9.139ns physical path delay ufmefb/EFBInst_0 to SLICE_30 meets + 8.882ns physical path delay ufmefb/EFBInst_0 to SLICE_30 meets 16.000ns delay constraint less 0.173ns skew and - 0.166ns DIN_SET requirement (totaling 15.661ns) by 6.522ns + 0.166ns DIN_SET requirement (totaling 15.661ns) by 6.779ns Physical Path Details: @@ -694,46 +810,258 @@ Passed: The following path meets requirements by 6.522ns Name Fanout Delay (ns) Site Resource WCLKI2WBDA --- 5.461 EFB.WBCLKI to EFB.WBDATO1 ufmefb/EFBInst_0 (from RCLK_c) -ROUTE 1 1.995 EFB.WBDATO1 to R4C8A.C1 wb_dato[1] -CTOF_DEL --- 0.495 R4C8A.C1 to R4C8A.F1 SLICE_30 -ROUTE 1 0.693 R4C8A.F1 to R4C8A.B0 LEDEN_6_i_m2_i_m2 -CTOF_DEL --- 0.495 R4C8A.B0 to R4C8A.F0 SLICE_30 -ROUTE 1 0.000 R4C8A.F0 to R4C8A.DI0 LEDENe_0 (to RCLK_c) +ROUTE 1 1.995 EFB.WBDATO1 to R4C6B.C1 wb_dato[1] +CTOF_DEL --- 0.495 R4C6B.C1 to R4C6B.F1 SLICE_30 +ROUTE 1 0.436 R4C6B.F1 to R4C6B.C0 LEDEN_6 +CTOF_DEL --- 0.495 R4C6B.C0 to R4C6B.F0 SLICE_30 +ROUTE 1 0.000 R4C6B.F0 to R4C6B.DI0 LEDENe_0 (to RCLK_c) -------- - 9.139 (70.6% logic, 29.4% route), 3 logic levels. + 8.882 (72.6% logic, 27.4% route), 3 logic levels. Clock Skew Details: Source Clock Path RCLK to ufmefb/EFBInst_0: Name Fanout Delay (ns) Site Resource -ROUTE 47 2.192 63.PADDI to EFB.WBCLKI RCLK_c +ROUTE 48 2.192 63.PADDI to EFB.WBCLKI RCLK_c -------- 2.192 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_30: Name Fanout Delay (ns) Site Resource -ROUTE 47 2.019 63.PADDI to R4C8A.CLK RCLK_c +ROUTE 48 2.019 63.PADDI to R4C6B.CLK RCLK_c -------- 2.019 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 6.683ns +Passed: The following path meets requirements by 6.810ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[17] (from RCLK_c +) + Destination: FF Data in wb_dati[6] (to RCLK_c +) + + Delay: 9.024ns (32.4% logic, 67.6% route), 6 logic levels. + + Constraint Details: + + 9.024ns physical path delay SLICE_1 to SLICE_55 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 15.834ns) by 6.810ns + + Physical Path Details: + + Data path SLICE_1 to SLICE_55: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R6C4B.CLK to R6C4B.Q0 SLICE_1 (from RCLK_c) +ROUTE 7 1.729 R6C4B.Q0 to R4C4A.C1 FS[17] +CTOF_DEL --- 0.495 R4C4A.C1 to R4C4A.F1 SLICE_64 +ROUTE 12 1.800 R4C4A.F1 to R3C4A.A1 FS_RNIHVJI[15] +CTOF_DEL --- 0.495 R3C4A.A1 to R3C4A.F1 SLICE_84 +ROUTE 4 0.643 R3C4A.F1 to R3C4A.D0 wb_dati_5_1_iv_0_a2_13[3] +CTOF_DEL --- 0.495 R3C4A.D0 to R3C4A.F0 SLICE_84 +ROUTE 1 0.626 R3C4A.F0 to R3C4D.D0 wb_dati_5_1_iv_0_0_a2[6] +CTOF_DEL --- 0.495 R3C4D.D0 to R3C4D.F0 SLICE_81 +ROUTE 1 1.299 R3C4D.F0 to R2C5B.A0 wb_dati_5_1_iv_0_0_1[6] +CTOF_DEL --- 0.495 R2C5B.A0 to R2C5B.F0 SLICE_55 +ROUTE 1 0.000 R2C5B.F0 to R2C5B.DI0 wb_dati_5[6] (to RCLK_c) + -------- + 9.024 (32.4% logic, 67.6% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_1: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.019 63.PADDI to R6C4B.CLK RCLK_c + -------- + 2.019 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_55: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.019 63.PADDI to R2C5B.CLK RCLK_c + -------- + 2.019 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 7.148ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[9] (from RCLK_c +) + Destination: FF Data in wb_dati[1] (to RCLK_c +) + + Delay: 8.686ns (33.7% logic, 66.3% route), 6 logic levels. + + Constraint Details: + + 8.686ns physical path delay SLICE_5 to SLICE_52 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.148ns + + Physical Path Details: + + Data path SLICE_5 to SLICE_52: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R6C3B.CLK to R6C3B.Q0 SLICE_5 (from RCLK_c) +ROUTE 17 1.867 R6C3B.Q0 to R4C4C.B1 FS[9] +CTOF_DEL --- 0.495 R4C4C.B1 to R4C4C.F1 SLICE_97 +ROUTE 3 0.643 R4C4C.F1 to R4C4C.D0 wb_dati_5_1_iv_0_o2_0[7] +CTOF_DEL --- 0.495 R4C4C.D0 to R4C4C.F0 SLICE_97 +ROUTE 1 0.967 R4C4C.F0 to R4C4A.A0 wb_dati_5_1_iv_0_a2_0_2[1] +CTOF_DEL --- 0.495 R4C4A.A0 to R4C4A.F0 SLICE_64 +ROUTE 1 1.535 R4C4A.F0 to R2C4B.B0 wb_dati_5_1_iv_0_0[1] +CTOF_DEL --- 0.495 R2C4B.B0 to R2C4B.F0 SLICE_85 +ROUTE 1 0.747 R2C4B.F0 to R2C4C.C1 wb_dati_5_1_iv_0_1[1] +CTOF_DEL --- 0.495 R2C4C.C1 to R2C4C.F1 SLICE_52 +ROUTE 1 0.000 R2C4C.F1 to R2C4C.DI1 wb_dati_5[1] (to RCLK_c) + -------- + 8.686 (33.7% logic, 66.3% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_5: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.019 63.PADDI to R6C3B.CLK RCLK_c + -------- + 2.019 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_52: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.019 63.PADDI to R2C4C.CLK RCLK_c + -------- + 2.019 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 7.149ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[15] (from RCLK_c +) + Destination: FF Data in wb_dati[6] (to RCLK_c +) + + Delay: 8.685ns (33.7% logic, 66.3% route), 6 logic levels. + + Constraint Details: + + 8.685ns physical path delay SLICE_2 to SLICE_55 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.149ns + + Physical Path Details: + + Data path SLICE_2 to SLICE_55: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R6C4A.CLK to R6C4A.Q0 SLICE_2 (from RCLK_c) +ROUTE 6 1.390 R6C4A.Q0 to R4C4A.B1 FS[15] +CTOF_DEL --- 0.495 R4C4A.B1 to R4C4A.F1 SLICE_64 +ROUTE 12 1.800 R4C4A.F1 to R3C4A.A1 FS_RNIHVJI[15] +CTOF_DEL --- 0.495 R3C4A.A1 to R3C4A.F1 SLICE_84 +ROUTE 4 0.643 R3C4A.F1 to R3C4A.D0 wb_dati_5_1_iv_0_a2_13[3] +CTOF_DEL --- 0.495 R3C4A.D0 to R3C4A.F0 SLICE_84 +ROUTE 1 0.626 R3C4A.F0 to R3C4D.D0 wb_dati_5_1_iv_0_0_a2[6] +CTOF_DEL --- 0.495 R3C4D.D0 to R3C4D.F0 SLICE_81 +ROUTE 1 1.299 R3C4D.F0 to R2C5B.A0 wb_dati_5_1_iv_0_0_1[6] +CTOF_DEL --- 0.495 R2C5B.A0 to R2C5B.F0 SLICE_55 +ROUTE 1 0.000 R2C5B.F0 to R2C5B.DI0 wb_dati_5[6] (to RCLK_c) + -------- + 8.685 (33.7% logic, 66.3% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_2: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.019 63.PADDI to R6C4A.CLK RCLK_c + -------- + 2.019 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_55: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.019 63.PADDI to R2C5B.CLK RCLK_c + -------- + 2.019 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 7.154ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[17] (from RCLK_c +) + Destination: FF Data in wb_dati[4] (to RCLK_c +) + + Delay: 8.680ns (33.7% logic, 66.3% route), 6 logic levels. + + Constraint Details: + + 8.680ns physical path delay SLICE_1 to SLICE_54 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.154ns + + Physical Path Details: + + Data path SLICE_1 to SLICE_54: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R6C4B.CLK to R6C4B.Q0 SLICE_1 (from RCLK_c) +ROUTE 7 1.729 R6C4B.Q0 to R4C4A.C1 FS[17] +CTOF_DEL --- 0.495 R4C4A.C1 to R4C4A.F1 SLICE_64 +ROUTE 12 1.019 R4C4A.F1 to R2C3B.D1 FS_RNIHVJI[15] +CTOF_DEL --- 0.495 R2C3B.D1 to R2C3B.F1 SLICE_87 +ROUTE 4 0.994 R2C3B.F1 to R3C4D.D1 wb_dati_5_1_iv_0_a2_12[3] +CTOF_DEL --- 0.495 R3C4D.D1 to R3C4D.F1 SLICE_81 +ROUTE 2 1.010 R3C4D.F1 to R3C3A.B0 wb_dati_5_1_iv_0_a2_2[4] +CTOF_DEL --- 0.495 R3C3A.B0 to R3C3A.F0 SLICE_111 +ROUTE 1 1.001 R3C3A.F0 to R2C3D.B0 wb_dati_5_1_iv_0_0_1[4] +CTOF_DEL --- 0.495 R2C3D.B0 to R2C3D.F0 SLICE_54 +ROUTE 1 0.000 R2C3D.F0 to R2C3D.DI0 wb_dati_5[4] (to RCLK_c) + -------- + 8.680 (33.7% logic, 66.3% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_1: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.019 63.PADDI to R6C4B.CLK RCLK_c + -------- + 2.019 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_54: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 2.019 63.PADDI to R2C3D.CLK RCLK_c + -------- + 2.019 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 7.228ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: EFB Port ufmefb/EFBInst_0(ASIC) (from RCLK_c +) Destination: FF Data in LEDEN (to RCLK_c +) - Delay: 8.978ns (48.2% logic, 51.8% route), 5 logic levels. + Delay: 8.433ns (51.3% logic, 48.7% route), 5 logic levels. Constraint Details: - 8.978ns physical path delay ufmefb/EFBInst_0 to SLICE_30 meets + 8.433ns physical path delay ufmefb/EFBInst_0 to SLICE_30 meets 16.000ns delay constraint less 0.173ns skew and - 0.166ns DIN_SET requirement (totaling 15.661ns) by 6.683ns + 0.166ns DIN_SET requirement (totaling 15.661ns) by 7.228ns Physical Path Details: @@ -741,410 +1069,88 @@ Passed: The following path meets requirements by 6.683ns Name Fanout Delay (ns) Site Resource WCLKI2WBAC --- 2.343 EFB.WBCLKI to EFB.WBACKO ufmefb/EFBInst_0 (from RCLK_c) -ROUTE 2 2.309 EFB.WBACKO to R4C7B.D0 wb_ack -CTOF_DEL --- 0.495 R4C7B.D0 to R4C7B.F0 SLICE_104 -ROUTE 1 0.626 R4C7B.F0 to R4C7D.D0 ufmefb/g0_0_a3_2 -CTOF_DEL --- 0.495 R4C7D.D0 to R4C7D.F0 SLICE_68 -ROUTE 1 0.744 R4C7D.F0 to R4C8C.C1 N_4 -CTOF_DEL --- 0.495 R4C8C.C1 to R4C8C.F1 SLICE_45 -ROUTE 2 0.976 R4C8C.F1 to R4C8A.A0 CmdValid_RNIOOBE2 -CTOF_DEL --- 0.495 R4C8A.A0 to R4C8A.F0 SLICE_30 -ROUTE 1 0.000 R4C8A.F0 to R4C8A.DI0 LEDENe_0 (to RCLK_c) +ROUTE 2 1.504 EFB.WBACKO to R3C5C.C0 wb_ack +CTOF_DEL --- 0.495 R3C5C.C0 to R3C5C.F0 SLICE_102 +ROUTE 1 0.315 R3C5C.F0 to R3C5B.D0 ufmefb/g0_0_a3_2 +CTOF_DEL --- 0.495 R3C5B.D0 to R3C5B.F0 SLICE_66 +ROUTE 1 1.278 R3C5B.F0 to R4C6D.C1 N_4 +CTOF_DEL --- 0.495 R4C6D.C1 to R4C6D.F1 SLICE_45 +ROUTE 2 1.013 R4C6D.F1 to R4C6B.B0 un1_FS_38_i +CTOF_DEL --- 0.495 R4C6B.B0 to R4C6B.F0 SLICE_30 +ROUTE 1 0.000 R4C6B.F0 to R4C6B.DI0 LEDENe_0 (to RCLK_c) -------- - 8.978 (48.2% logic, 51.8% route), 5 logic levels. + 8.433 (51.3% logic, 48.7% route), 5 logic levels. Clock Skew Details: Source Clock Path RCLK to ufmefb/EFBInst_0: Name Fanout Delay (ns) Site Resource -ROUTE 47 2.192 63.PADDI to EFB.WBCLKI RCLK_c +ROUTE 48 2.192 63.PADDI to EFB.WBCLKI RCLK_c -------- 2.192 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_30: Name Fanout Delay (ns) Site Resource -ROUTE 47 2.019 63.PADDI to R4C8A.CLK RCLK_c +ROUTE 48 2.019 63.PADDI to R4C6B.CLK RCLK_c -------- 2.019 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 6.738ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS[3] (from RCLK_c +) - Destination: FF Data in nRCAS_0io (to RCLK_c +) - - Delay: 9.282ns (36.9% logic, 63.1% route), 7 logic levels. - - Constraint Details: - - 9.282ns physical path delay SLICE_28 to nRCAS_MGIOL meets - 16.000ns delay constraint less - -0.173ns skew and - 0.153ns DO_SET requirement (totaling 16.020ns) by 6.738ns - - Physical Path Details: - - Data path SLICE_28 to nRCAS_MGIOL: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R4C15D.CLK to R4C15D.Q0 SLICE_28 (from RCLK_c) -ROUTE 4 1.183 R4C15D.Q0 to R4C14B.C1 IS[3] -CTOF_DEL --- 0.495 R4C14B.C1 to R4C14B.F1 SLICE_74 -ROUTE 2 0.445 R4C14B.F1 to R4C14B.C0 un1_nRCAS_6_sqmuxa_i_0_0_o2_0 -CTOF_DEL --- 0.495 R4C14B.C0 to R4C14B.F0 SLICE_74 -ROUTE 2 0.758 R4C14B.F0 to R4C13A.C1 N_408 -CTOF_DEL --- 0.495 R4C13A.C1 to R4C13A.F1 SLICE_61 -ROUTE 1 0.626 R4C13A.F1 to R4C13A.D0 un1_nRCAS_6_sqmuxa_i_0_0 -CTOF_DEL --- 0.495 R4C13A.D0 to R4C13A.F0 SLICE_61 -ROUTE 1 0.623 R4C13A.F0 to R5C13A.D0 nRCAS_r_i_0_o2_0_0 -CTOF_DEL --- 0.495 R5C13A.D0 to R5C13A.F0 SLICE_94 -ROUTE 1 0.626 R5C13A.F0 to R5C13A.D1 N_248_i_1 -CTOF_DEL --- 0.495 R5C13A.D1 to R5C13A.F1 SLICE_94 -ROUTE 1 1.599 R5C13A.F1 to IOL_R7C.OPOS N_248_i (to RCLK_c) - -------- - 9.282 (36.9% logic, 63.1% route), 7 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_28: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 2.019 63.PADDI to R4C15D.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to nRCAS_MGIOL: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 2.192 63.PADDI to IOL_R7C.CLK RCLK_c - -------- - 2.192 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 6.917ns +Passed: The following path meets requirements by 7.241ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q IS[1] (from RCLK_c +) Destination: FF Data in nRCAS_0io (to RCLK_c +) - Delay: 9.103ns (37.6% logic, 62.4% route), 7 logic levels. + Delay: 8.779ns (33.3% logic, 66.7% route), 6 logic levels. Constraint Details: - 9.103ns physical path delay SLICE_27 to nRCAS_MGIOL meets + 8.779ns physical path delay SLICE_27 to nRCAS_MGIOL meets 16.000ns delay constraint less -0.173ns skew and - 0.153ns DO_SET requirement (totaling 16.020ns) by 6.917ns + 0.153ns DO_SET requirement (totaling 16.020ns) by 7.241ns Physical Path Details: Data path SLICE_27 to nRCAS_MGIOL: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R4C15A.CLK to R4C15A.Q0 SLICE_27 (from RCLK_c) -ROUTE 7 1.004 R4C15A.Q0 to R4C14B.A1 IS[1] -CTOF_DEL --- 0.495 R4C14B.A1 to R4C14B.F1 SLICE_74 -ROUTE 2 0.445 R4C14B.F1 to R4C14B.C0 un1_nRCAS_6_sqmuxa_i_0_0_o2_0 -CTOF_DEL --- 0.495 R4C14B.C0 to R4C14B.F0 SLICE_74 -ROUTE 2 0.758 R4C14B.F0 to R4C13A.C1 N_408 -CTOF_DEL --- 0.495 R4C13A.C1 to R4C13A.F1 SLICE_61 -ROUTE 1 0.626 R4C13A.F1 to R4C13A.D0 un1_nRCAS_6_sqmuxa_i_0_0 -CTOF_DEL --- 0.495 R4C13A.D0 to R4C13A.F0 SLICE_61 -ROUTE 1 0.623 R4C13A.F0 to R5C13A.D0 nRCAS_r_i_0_o2_0_0 -CTOF_DEL --- 0.495 R5C13A.D0 to R5C13A.F0 SLICE_94 -ROUTE 1 0.626 R5C13A.F0 to R5C13A.D1 N_248_i_1 -CTOF_DEL --- 0.495 R5C13A.D1 to R5C13A.F1 SLICE_94 -ROUTE 1 1.599 R5C13A.F1 to IOL_R7C.OPOS N_248_i (to RCLK_c) +REG_DEL --- 0.452 R4C14D.CLK to R4C14D.Q0 SLICE_27 (from RCLK_c) +ROUTE 7 1.433 R4C14D.Q0 to R5C14C.B1 IS[1] +CTOF_DEL --- 0.495 R5C14C.B1 to R5C14C.F1 SLICE_83 +ROUTE 3 0.673 R5C14C.F1 to R5C14D.A0 un1_nRCAS_6_sqmuxa_i_o2 +CTOF_DEL --- 0.495 R5C14D.A0 to R5C14D.F0 SLICE_62 +ROUTE 2 0.967 R5C14D.F0 to R6C13C.D0 N_48 +CTOF_DEL --- 0.495 R6C13C.D0 to R6C13C.F0 SLICE_69 +ROUTE 1 0.436 R6C13C.F0 to R6C13C.C1 nRCS_9_u_i_o3_0_0 +CTOF_DEL --- 0.495 R6C13C.C1 to R6C13C.F1 SLICE_69 +ROUTE 1 0.744 R6C13C.F1 to R6C14C.C1 nRCS_9_u_i_o3_0_2 +CTOF_DEL --- 0.495 R6C14C.C1 to R6C14C.F1 SLICE_101 +ROUTE 1 1.599 R6C14C.F1 to IOL_R7C.OPOS N_251_i (to RCLK_c) -------- - 9.103 (37.6% logic, 62.4% route), 7 logic levels. + 8.779 (33.3% logic, 66.7% route), 6 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_27: Name Fanout Delay (ns) Site Resource -ROUTE 47 2.019 63.PADDI to R4C15A.CLK RCLK_c +ROUTE 48 2.019 63.PADDI to R4C14D.CLK RCLK_c -------- 2.019 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to nRCAS_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 47 2.192 63.PADDI to IOL_R7C.CLK RCLK_c +ROUTE 48 2.192 63.PADDI to IOL_R7C.CLK RCLK_c -------- 2.192 (0.0% logic, 100.0% route), 0 logic levels. - -Passed: The following path meets requirements by 7.044ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q InitReady (from RCLK_c +) - Destination: FF Data in wb_dati[4] (to RCLK_c +) - - Delay: 8.790ns (33.3% logic, 66.7% route), 6 logic levels. - - Constraint Details: - - 8.790ns physical path delay SLICE_29 to SLICE_54 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.044ns - - Physical Path Details: - - Data path SLICE_29 to SLICE_54: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R4C7C.CLK to R4C7C.Q0 SLICE_29 (from RCLK_c) -ROUTE 41 1.468 R4C7C.Q0 to R2C5D.D1 InitReady -CTOF_DEL --- 0.495 R2C5D.D1 to R2C5D.F1 SLICE_66 -ROUTE 13 1.119 R2C5D.F1 to R3C6C.C0 N_214 -CTOF_DEL --- 0.495 R3C6C.C0 to R3C6C.F0 SLICE_113 -ROUTE 2 0.967 R3C6C.F0 to R2C4A.D1 N_576 -CTOF_DEL --- 0.495 R2C4A.D1 to R2C4A.F1 SLICE_85 -ROUTE 2 1.308 R2C4A.F1 to R3C5A.A0 N_473 -CTOF_DEL --- 0.495 R3C5A.A0 to R3C5A.F0 SLICE_86 -ROUTE 1 1.001 R3C5A.F0 to R3C4C.B0 wb_dati_5_1_iv_0_1[4] -CTOF_DEL --- 0.495 R3C4C.B0 to R3C4C.F0 SLICE_54 -ROUTE 1 0.000 R3C4C.F0 to R3C4C.DI0 wb_dati_5[4] (to RCLK_c) - -------- - 8.790 (33.3% logic, 66.7% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_29: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 2.019 63.PADDI to R4C7C.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_54: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 2.019 63.PADDI to R3C4C.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 7.047ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q InitReady (from RCLK_c +) - Destination: FF Data in wb_dati[6] (to RCLK_c +) - - Delay: 8.787ns (33.3% logic, 66.7% route), 6 logic levels. - - Constraint Details: - - 8.787ns physical path delay SLICE_29 to SLICE_55 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.047ns - - Physical Path Details: - - Data path SLICE_29 to SLICE_55: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R4C7C.CLK to R4C7C.Q0 SLICE_29 (from RCLK_c) -ROUTE 41 1.468 R4C7C.Q0 to R2C5D.D1 InitReady -CTOF_DEL --- 0.495 R2C5D.D1 to R2C5D.F1 SLICE_66 -ROUTE 13 0.656 R2C5D.F1 to R3C5C.D1 N_214 -CTOF_DEL --- 0.495 R3C5C.D1 to R3C5C.F1 SLICE_87 -ROUTE 4 1.473 R3C5C.F1 to R4C4D.B0 N_579 -CTOF_DEL --- 0.495 R4C4D.B0 to R4C4D.F0 SLICE_89 -ROUTE 1 1.299 R4C4D.F0 to R2C4A.A0 N_472 -CTOF_DEL --- 0.495 R2C4A.A0 to R2C4A.F0 SLICE_85 -ROUTE 1 0.964 R2C4A.F0 to R2C5B.A0 wb_dati_5_1_iv_0_1[6] -CTOF_DEL --- 0.495 R2C5B.A0 to R2C5B.F0 SLICE_55 -ROUTE 1 0.000 R2C5B.F0 to R2C5B.DI0 wb_dati_5[6] (to RCLK_c) - -------- - 8.787 (33.3% logic, 66.7% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_29: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 2.019 63.PADDI to R4C7C.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_55: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 2.019 63.PADDI to R2C5B.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 7.048ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[17] (from RCLK_c +) - Destination: FF Data in wb_dati[4] (to RCLK_c +) - - Delay: 8.786ns (33.3% logic, 66.7% route), 6 logic levels. - - Constraint Details: - - 8.786ns physical path delay SLICE_1 to SLICE_54 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.048ns - - Physical Path Details: - - Data path SLICE_1 to SLICE_54: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R2C9B.CLK to R2C9B.Q0 SLICE_1 (from RCLK_c) -ROUTE 6 1.464 R2C9B.Q0 to R2C5D.B1 FS[17] -CTOF_DEL --- 0.495 R2C5D.B1 to R2C5D.F1 SLICE_66 -ROUTE 13 1.119 R2C5D.F1 to R3C6C.C0 N_214 -CTOF_DEL --- 0.495 R3C6C.C0 to R3C6C.F0 SLICE_113 -ROUTE 2 0.967 R3C6C.F0 to R2C4A.D1 N_576 -CTOF_DEL --- 0.495 R2C4A.D1 to R2C4A.F1 SLICE_85 -ROUTE 2 1.308 R2C4A.F1 to R3C5A.A0 N_473 -CTOF_DEL --- 0.495 R3C5A.A0 to R3C5A.F0 SLICE_86 -ROUTE 1 1.001 R3C5A.F0 to R3C4C.B0 wb_dati_5_1_iv_0_1[4] -CTOF_DEL --- 0.495 R3C4C.B0 to R3C4C.F0 SLICE_54 -ROUTE 1 0.000 R3C4C.F0 to R3C4C.DI0 wb_dati_5[4] (to RCLK_c) - -------- - 8.786 (33.3% logic, 66.7% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_1: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 2.019 63.PADDI to R2C9B.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_54: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 2.019 63.PADDI to R3C4C.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 7.051ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[17] (from RCLK_c +) - Destination: FF Data in wb_dati[6] (to RCLK_c +) - - Delay: 8.783ns (33.3% logic, 66.7% route), 6 logic levels. - - Constraint Details: - - 8.783ns physical path delay SLICE_1 to SLICE_55 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.051ns - - Physical Path Details: - - Data path SLICE_1 to SLICE_55: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R2C9B.CLK to R2C9B.Q0 SLICE_1 (from RCLK_c) -ROUTE 6 1.464 R2C9B.Q0 to R2C5D.B1 FS[17] -CTOF_DEL --- 0.495 R2C5D.B1 to R2C5D.F1 SLICE_66 -ROUTE 13 0.656 R2C5D.F1 to R3C5C.D1 N_214 -CTOF_DEL --- 0.495 R3C5C.D1 to R3C5C.F1 SLICE_87 -ROUTE 4 1.473 R3C5C.F1 to R4C4D.B0 N_579 -CTOF_DEL --- 0.495 R4C4D.B0 to R4C4D.F0 SLICE_89 -ROUTE 1 1.299 R4C4D.F0 to R2C4A.A0 N_472 -CTOF_DEL --- 0.495 R2C4A.A0 to R2C4A.F0 SLICE_85 -ROUTE 1 0.964 R2C4A.F0 to R2C5B.A0 wb_dati_5_1_iv_0_1[6] -CTOF_DEL --- 0.495 R2C5B.A0 to R2C5B.F0 SLICE_55 -ROUTE 1 0.000 R2C5B.F0 to R2C5B.DI0 wb_dati_5[6] (to RCLK_c) - -------- - 8.783 (33.3% logic, 66.7% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_1: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 2.019 63.PADDI to R2C9B.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_55: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 2.019 63.PADDI to R2C5B.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 7.085ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[16] (from RCLK_c +) - Destination: FF Data in wb_dati[4] (to RCLK_c +) - - Delay: 8.749ns (33.5% logic, 66.5% route), 6 logic levels. - - Constraint Details: - - 8.749ns physical path delay SLICE_2 to SLICE_54 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 15.834ns) by 7.085ns - - Physical Path Details: - - Data path SLICE_2 to SLICE_54: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R2C9A.CLK to R2C9A.Q1 SLICE_2 (from RCLK_c) -ROUTE 6 1.427 R2C9A.Q1 to R2C5D.A1 FS[16] -CTOF_DEL --- 0.495 R2C5D.A1 to R2C5D.F1 SLICE_66 -ROUTE 13 1.119 R2C5D.F1 to R3C6C.C0 N_214 -CTOF_DEL --- 0.495 R3C6C.C0 to R3C6C.F0 SLICE_113 -ROUTE 2 0.967 R3C6C.F0 to R2C4A.D1 N_576 -CTOF_DEL --- 0.495 R2C4A.D1 to R2C4A.F1 SLICE_85 -ROUTE 2 1.308 R2C4A.F1 to R3C5A.A0 N_473 -CTOF_DEL --- 0.495 R3C5A.A0 to R3C5A.F0 SLICE_86 -ROUTE 1 1.001 R3C5A.F0 to R3C4C.B0 wb_dati_5_1_iv_0_1[4] -CTOF_DEL --- 0.495 R3C4C.B0 to R3C4C.F0 SLICE_54 -ROUTE 1 0.000 R3C4C.F0 to R3C4C.DI0 wb_dati_5[4] (to RCLK_c) - -------- - 8.749 (33.5% logic, 66.5% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_2: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 2.019 63.PADDI to R2C9A.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_54: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 2.019 63.PADDI to R3C4C.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - -Report: 97.771MHz is the maximum frequency for this preference. +Report: 102.312MHz is the maximum frequency for this preference. Report Summary -------------- @@ -1152,13 +1158,13 @@ Report: 97.771MHz is the maximum frequency for this preference. Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | -FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 52.949 MHz| 5 +FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 47.068 MHz| 5 | | | FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0 | | | FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0 | | | -FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 97.771 MHz| 3 +FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 102.312 MHz| 0 | | | ---------------------------------------------------------------------------- @@ -1183,7 +1189,7 @@ Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11 Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10 No transfer within this clock domain is found -Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47 +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 48 Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ; Data transfers from: @@ -1213,11 +1219,11 @@ Clock Domain: PHI2_c Source: PHI2.PAD Loads: 21 Timing errors: 0 Score: 0 Cumulative negative slack: 0 -Constraints cover 1025 paths, 4 nets, and 758 connections (74.53% coverage) +Constraints cover 1038 paths, 4 nets, and 750 connections (74.18% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 -Thu Sep 21 05:40:01 2023 +Sat Nov 18 02:06:11 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -1242,7 +1248,7 @@ Report level: verbose report, limited to 10 items per preference
  • FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)
    • 0 items scored, 0 timing errors detected. -
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    • 878 items scored, 0 timing errors detected. +
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    • 891 items scored, 0 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS @@ -1277,10 +1283,10 @@ Passed: The following path meets requirements by 0.379ns Data path SLICE_11 to SLICE_11: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R4C11D.CLK to R4C11D.Q0 SLICE_11 (from PHI2_c) -ROUTE 2 0.132 R4C11D.Q0 to R4C11D.A0 C1Submitted -CTOF_DEL --- 0.101 R4C11D.A0 to R4C11D.F0 SLICE_11 -ROUTE 1 0.000 R4C11D.F0 to R4C11D.DI0 C1Submitted_RNO (to PHI2_c) +REG_DEL --- 0.133 R5C8D.CLK to R5C8D.Q0 SLICE_11 (from PHI2_c) +ROUTE 2 0.132 R5C8D.Q0 to R5C8D.A0 C1Submitted +CTOF_DEL --- 0.101 R5C8D.A0 to R5C8D.F0 SLICE_11 +ROUTE 1 0.000 R5C8D.F0 to R5C8D.DI0 C1Submitted_RNO (to PHI2_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. @@ -1289,59 +1295,14 @@ ROUTE 1 0.000 R4C11D.F0 to R4C11D.DI0 C1Submitted_RNO (to P Source Clock Path PHI2 to SLICE_11: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R4C11D.CLK PHI2_c +ROUTE 21 1.240 8.PADDI to R5C8D.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_11: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R4C11D.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.379ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CmdEnable (from PHI2_c -) - Destination: FF Data in CmdEnable (to PHI2_c -) - - Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. - - Constraint Details: - - 0.366ns physical path delay SLICE_17 to SLICE_17 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.379ns - - Physical Path Details: - - Data path SLICE_17 to SLICE_17: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C11C.CLK to R3C11C.Q0 SLICE_17 (from PHI2_c) -ROUTE 2 0.132 R3C11C.Q0 to R3C11C.A0 CmdEnable -CTOF_DEL --- 0.101 R3C11C.A0 to R3C11C.F0 SLICE_17 -ROUTE 1 0.000 R3C11C.F0 to R3C11C.DI0 CmdEnable_s (to PHI2_c) - -------- - 0.366 (63.9% logic, 36.1% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_17: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R3C11C.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_17: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R3C11C.CLK PHI2_c +ROUTE 21 1.240 8.PADDI to R5C8D.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. @@ -1367,10 +1328,10 @@ Passed: The following path meets requirements by 0.379ns Data path SLICE_20 to SLICE_20: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C9B.CLK to R3C9B.Q0 SLICE_20 (from PHI2_c) -ROUTE 2 0.132 R3C9B.Q0 to R3C9B.A0 CmdUFMShift -CTOF_DEL --- 0.101 R3C9B.A0 to R3C9B.F0 SLICE_20 -ROUTE 1 0.000 R3C9B.F0 to R3C9B.DI0 CmdUFMShift_3 (to PHI2_c) +REG_DEL --- 0.133 R4C9A.CLK to R4C9A.Q0 SLICE_20 (from PHI2_c) +ROUTE 2 0.132 R4C9A.Q0 to R4C9A.A0 CmdUFMShift +CTOF_DEL --- 0.101 R4C9A.A0 to R4C9A.F0 SLICE_20 +ROUTE 1 0.000 R4C9A.F0 to R4C9A.DI0 CmdUFMShift_3 (to PHI2_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. @@ -1379,337 +1340,384 @@ ROUTE 1 0.000 R3C9B.F0 to R3C9B.DI0 CmdUFMShift_3 (to PHI Source Clock Path PHI2 to SLICE_20: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R3C9B.CLK PHI2_c +ROUTE 21 1.240 8.PADDI to R4C9A.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_20: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R3C9B.CLK PHI2_c +ROUTE 21 1.240 8.PADDI to R4C9A.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 0.385ns +Passed: The following path meets requirements by 0.382ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ADSubmitted (from PHI2_c -) Destination: FF Data in ADSubmitted (to PHI2_c -) - Delay: 0.372ns (62.9% logic, 37.1% route), 2 logic levels. + Delay: 0.369ns (63.4% logic, 36.6% route), 2 logic levels. Constraint Details: - 0.372ns physical path delay SLICE_10 to SLICE_10 meets + 0.369ns physical path delay SLICE_10 to SLICE_10 meets -0.013ns DIN_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.385ns + 0.000ns skew requirement (totaling -0.013ns) by 0.382ns Physical Path Details: Data path SLICE_10 to SLICE_10: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C11A.CLK to R3C11A.Q0 SLICE_10 (from PHI2_c) -ROUTE 2 0.138 R3C11A.Q0 to R3C11A.D0 ADSubmitted -CTOF_DEL --- 0.101 R3C11A.D0 to R3C11A.F0 SLICE_10 -ROUTE 1 0.000 R3C11A.F0 to R3C11A.DI0 ADSubmitted_r_0_0 (to PHI2_c) +REG_DEL --- 0.133 R5C7C.CLK to R5C7C.Q0 SLICE_10 (from PHI2_c) +ROUTE 2 0.135 R5C7C.Q0 to R5C7C.D0 ADSubmitted +CTOF_DEL --- 0.101 R5C7C.D0 to R5C7C.F0 SLICE_10 +ROUTE 1 0.000 R5C7C.F0 to R5C7C.DI0 ADSubmitted_r_0_0 (to PHI2_c) -------- - 0.372 (62.9% logic, 37.1% route), 2 logic levels. + 0.369 (63.4% logic, 36.6% route), 2 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_10: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R3C11A.CLK PHI2_c +ROUTE 21 1.240 8.PADDI to R5C7C.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_10: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R3C11A.CLK PHI2_c +ROUTE 21 1.240 8.PADDI to R5C7C.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 0.616ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q ADSubmitted (from PHI2_c -) - Destination: FF Data in CmdEnable (to PHI2_c -) - - Delay: 0.603ns (55.6% logic, 44.4% route), 3 logic levels. - - Constraint Details: - - 0.603ns physical path delay SLICE_10 to SLICE_17 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.616ns - - Physical Path Details: - - Data path SLICE_10 to SLICE_17: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C11A.CLK to R3C11A.Q0 SLICE_10 (from PHI2_c) -ROUTE 2 0.215 R3C11A.Q0 to R3C11D.A0 ADSubmitted -CTOF_DEL --- 0.101 R3C11D.A0 to R3C11D.F0 SLICE_33 -ROUTE 1 0.053 R3C11D.F0 to R3C11C.D0 CmdEnable_0_sqmuxa -CTOF_DEL --- 0.101 R3C11C.D0 to R3C11C.F0 SLICE_17 -ROUTE 1 0.000 R3C11C.F0 to R3C11C.DI0 CmdEnable_s (to PHI2_c) - -------- - 0.603 (55.6% logic, 44.4% route), 3 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_10: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R3C11A.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_17: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R3C11C.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.616ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CmdUFMWrite (from PHI2_c -) - Destination: FF Data in CmdUFMWrite (to PHI2_c -) - - Delay: 0.603ns (55.6% logic, 44.4% route), 3 logic levels. - - Constraint Details: - - 0.603ns physical path delay SLICE_21 to SLICE_21 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.616ns - - Physical Path Details: - - Data path SLICE_21 to SLICE_21: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C9C.CLK to R3C9C.Q0 SLICE_21 (from PHI2_c) -ROUTE 2 0.212 R3C9C.Q0 to R3C9C.A1 CmdUFMWrite -CTOF_DEL --- 0.101 R3C9C.A1 to R3C9C.F1 SLICE_21 -ROUTE 1 0.056 R3C9C.F1 to R3C9C.C0 N_462 -CTOF_DEL --- 0.101 R3C9C.C0 to R3C9C.F0 SLICE_21 -ROUTE 1 0.000 R3C9C.F0 to R3C9C.DI0 CmdUFMWrite_3 (to PHI2_c) - -------- - 0.603 (55.6% logic, 44.4% route), 3 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_21: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R3C9C.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_21: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R3C9C.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.627ns +Passed: The following path meets requirements by 0.471ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CmdEnable (from PHI2_c -) - Destination: FF Data in CmdValid_fast (to PHI2_c -) + Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 0.614ns (54.6% logic, 45.4% route), 3 logic levels. + Delay: 0.458ns (51.1% logic, 48.9% route), 2 logic levels. Constraint Details: - 0.614ns physical path delay SLICE_17 to SLICE_23 meets + 0.458ns physical path delay SLICE_17 to SLICE_17 meets -0.013ns DIN_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.627ns + 0.000ns skew requirement (totaling -0.013ns) by 0.471ns Physical Path Details: - Data path SLICE_17 to SLICE_23: + Data path SLICE_17 to SLICE_17: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C11C.CLK to R3C11C.Q0 SLICE_17 (from PHI2_c) -ROUTE 2 0.220 R3C11C.Q0 to R3C9D.D1 CmdEnable -CTOF_DEL --- 0.101 R3C9D.D1 to R3C9D.F1 SLICE_23 -ROUTE 8 0.059 R3C9D.F1 to R3C9D.C0 XOR8MEG18 -CTOF_DEL --- 0.101 R3C9D.C0 to R3C9D.F0 SLICE_23 -ROUTE 1 0.000 R3C9D.F0 to R3C9D.DI0 N_36_fast (to PHI2_c) +REG_DEL --- 0.133 R5C8C.CLK to R5C8C.Q0 SLICE_17 (from PHI2_c) +ROUTE 2 0.224 R5C8C.Q0 to R5C8C.B0 CmdEnable +CTOF_DEL --- 0.101 R5C8C.B0 to R5C8C.F0 SLICE_17 +ROUTE 1 0.000 R5C8C.F0 to R5C8C.DI0 CmdEnable_s (to PHI2_c) -------- - 0.614 (54.6% logic, 45.4% route), 3 logic levels. + 0.458 (51.1% logic, 48.9% route), 2 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_17: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R3C11C.CLK PHI2_c +ROUTE 21 1.240 8.PADDI to R5C8C.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_23: + Destination Clock Path PHI2 to SLICE_17: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R3C9D.CLK PHI2_c +ROUTE 21 1.240 8.PADDI to R5C8C.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.613ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q C1Submitted (from PHI2_c -) + Destination: FF Data in CmdEnable (to PHI2_c -) + + Delay: 0.600ns (55.8% logic, 44.2% route), 3 logic levels. + + Constraint Details: + + 0.600ns physical path delay SLICE_11 to SLICE_17 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.613ns + + Physical Path Details: + + Data path SLICE_11 to SLICE_17: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C8D.CLK to R5C8D.Q0 SLICE_11 (from PHI2_c) +ROUTE 2 0.212 R5C8D.Q0 to R5C8B.A0 C1Submitted +CTOF_DEL --- 0.101 R5C8B.A0 to R5C8B.F0 SLICE_76 +ROUTE 1 0.053 R5C8B.F0 to R5C8C.D0 un1_CmdEnable20_i +CTOF_DEL --- 0.101 R5C8C.D0 to R5C8C.F0 SLICE_17 +ROUTE 1 0.000 R5C8C.F0 to R5C8C.DI0 CmdEnable_s (to PHI2_c) + -------- + 0.600 (55.8% logic, 44.2% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_11: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 1.240 8.PADDI to R5C8D.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_17: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 1.240 8.PADDI to R5C8C.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.616ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdLEDEN (from PHI2_c -) + Destination: FF Data in CmdLEDEN (to PHI2_c -) + + Delay: 0.603ns (55.6% logic, 44.4% route), 3 logic levels. + + Constraint Details: + + 0.603ns physical path delay SLICE_18 to SLICE_18 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.616ns + + Physical Path Details: + + Data path SLICE_18 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R4C8C.CLK to R4C8C.Q0 SLICE_18 (from PHI2_c) +ROUTE 2 0.212 R4C8C.Q0 to R4C8C.A1 CmdLEDEN +CTOF_DEL --- 0.101 R4C8C.A1 to R4C8C.F1 SLICE_18 +ROUTE 1 0.056 R4C8C.F1 to R4C8C.C0 CmdLEDEN_4_u_i_m2_i_0 +CTOF_DEL --- 0.101 R4C8C.C0 to R4C8C.F0 SLICE_18 +ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 N_17_i (to PHI2_c) + -------- + 0.603 (55.6% logic, 44.4% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 1.240 8.PADDI to R4C8C.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 1.240 8.PADDI to R4C8C.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.616ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Cmdn8MEGEN (from PHI2_c -) + Destination: FF Data in Cmdn8MEGEN (to PHI2_c -) + + Delay: 0.603ns (55.6% logic, 44.4% route), 3 logic levels. + + Constraint Details: + + 0.603ns physical path delay SLICE_24 to SLICE_24 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.616ns + + Physical Path Details: + + Data path SLICE_24 to SLICE_24: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R4C8D.CLK to R4C8D.Q0 SLICE_24 (from PHI2_c) +ROUTE 2 0.212 R4C8D.Q0 to R4C8D.A1 Cmdn8MEGEN +CTOF_DEL --- 0.101 R4C8D.A1 to R4C8D.F1 SLICE_24 +ROUTE 1 0.056 R4C8D.F1 to R4C8D.C0 Cmdn8MEGEN_4_u_i_m2_i_0 +CTOF_DEL --- 0.101 R4C8D.C0 to R4C8D.F0 SLICE_24 +ROUTE 1 0.000 R4C8D.F0 to R4C8D.DI0 N_15_i (to PHI2_c) + -------- + 0.603 (55.6% logic, 44.4% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_24: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 1.240 8.PADDI to R4C8D.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_24: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 1.240 8.PADDI to R4C8D.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.616ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q XOR8MEG (from PHI2_c -) + Destination: FF Data in XOR8MEG (to PHI2_c -) + + Delay: 0.603ns (55.6% logic, 44.4% route), 3 logic levels. + + Constraint Details: + + 0.603ns physical path delay SLICE_44 to SLICE_44 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.616ns + + Physical Path Details: + + Data path SLICE_44 to SLICE_44: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C9C.CLK to R5C9C.Q0 SLICE_44 (from PHI2_c) +ROUTE 2 0.212 R5C9C.Q0 to R5C9C.A1 XOR8MEG +CTOF_DEL --- 0.101 R5C9C.A1 to R5C9C.F1 SLICE_44 +ROUTE 1 0.056 R5C9C.F1 to R5C9C.C0 N_411 +CTOF_DEL --- 0.101 R5C9C.C0 to R5C9C.F0 SLICE_44 +ROUTE 1 0.000 R5C9C.F0 to R5C9C.DI0 XOR8MEG_3 (to PHI2_c) + -------- + 0.603 (55.6% logic, 44.4% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_44: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 1.240 8.PADDI to R5C9C.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_44: + + Name Fanout Delay (ns) Site Resource +ROUTE 21 1.240 8.PADDI to R5C9C.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.628ns - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Cmdn8MEGEN (from PHI2_c -) - Destination: FF Data in Cmdn8MEGEN (to PHI2_c -) - - Delay: 0.615ns (54.5% logic, 45.5% route), 3 logic levels. - - Constraint Details: - - 0.615ns physical path delay SLICE_24 to SLICE_24 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.628ns - - Physical Path Details: - - Data path SLICE_24 to SLICE_24: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R4C9B.CLK to R4C9B.Q0 SLICE_24 (from PHI2_c) -ROUTE 2 0.224 R4C9B.Q0 to R4C9B.B1 Cmdn8MEGEN -CTOF_DEL --- 0.101 R4C9B.B1 to R4C9B.F1 SLICE_24 -ROUTE 1 0.056 R4C9B.F1 to R4C9B.C0 Cmdn8MEGEN_4_u_i_0_0 -CTOF_DEL --- 0.101 R4C9B.C0 to R4C9B.F0 SLICE_24 -ROUTE 1 0.000 R4C9B.F0 to R4C9B.DI0 N_38_i (to PHI2_c) - -------- - 0.615 (54.5% logic, 45.5% route), 3 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_24: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R4C9B.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_24: - - Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R4C9B.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.633ns - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CmdEnable (from PHI2_c -) Destination: FF Data in CmdUFMShift (to PHI2_c -) - Delay: 0.605ns (38.7% logic, 61.3% route), 2 logic levels. + Delay: 0.600ns (39.0% logic, 61.0% route), 2 logic levels. Constraint Details: - 0.605ns physical path delay SLICE_17 to SLICE_20 meets + 0.600ns physical path delay SLICE_17 to SLICE_20 meets -0.028ns CE_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.028ns) by 0.633ns + 0.000ns skew requirement (totaling -0.028ns) by 0.628ns Physical Path Details: Data path SLICE_17 to SLICE_20: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C11C.CLK to R3C11C.Q0 SLICE_17 (from PHI2_c) -ROUTE 2 0.220 R3C11C.Q0 to R3C9D.D1 CmdEnable -CTOF_DEL --- 0.101 R3C9D.D1 to R3C9D.F1 SLICE_23 -ROUTE 8 0.151 R3C9D.F1 to R3C9B.CE XOR8MEG18 (to PHI2_c) +REG_DEL --- 0.133 R5C8C.CLK to R5C8C.Q0 SLICE_17 (from PHI2_c) +ROUTE 2 0.213 R5C8C.Q0 to R4C8A.A1 CmdEnable +CTOF_DEL --- 0.101 R4C8A.A1 to R4C8A.F1 SLICE_23 +ROUTE 8 0.153 R4C8A.F1 to R4C9A.CE XOR8MEG18 (to PHI2_c) -------- - 0.605 (38.7% logic, 61.3% route), 2 logic levels. + 0.600 (39.0% logic, 61.0% route), 2 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_17: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R3C11C.CLK PHI2_c +ROUTE 21 1.240 8.PADDI to R5C8C.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_20: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R3C9B.CLK PHI2_c +ROUTE 21 1.240 8.PADDI to R4C9A.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 0.633ns +Passed: The following path meets requirements by 0.628ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q CmdEnable (from PHI2_c -) + Source: FF Q CmdUFMWrite (from PHI2_c -) Destination: FF Data in CmdUFMWrite (to PHI2_c -) - Delay: 0.605ns (38.7% logic, 61.3% route), 2 logic levels. + Delay: 0.615ns (54.5% logic, 45.5% route), 3 logic levels. Constraint Details: - 0.605ns physical path delay SLICE_17 to SLICE_21 meets - -0.028ns CE_HLD and + 0.615ns physical path delay SLICE_21 to SLICE_21 meets + -0.013ns DIN_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.028ns) by 0.633ns + 0.000ns skew requirement (totaling -0.013ns) by 0.628ns Physical Path Details: - Data path SLICE_17 to SLICE_21: + Data path SLICE_21 to SLICE_21: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C11C.CLK to R3C11C.Q0 SLICE_17 (from PHI2_c) -ROUTE 2 0.220 R3C11C.Q0 to R3C9D.D1 CmdEnable -CTOF_DEL --- 0.101 R3C9D.D1 to R3C9D.F1 SLICE_23 -ROUTE 8 0.151 R3C9D.F1 to R3C9C.CE XOR8MEG18 (to PHI2_c) +REG_DEL --- 0.133 R4C8B.CLK to R4C8B.Q0 SLICE_21 (from PHI2_c) +ROUTE 2 0.224 R4C8B.Q0 to R4C8B.B1 CmdUFMWrite +CTOF_DEL --- 0.101 R4C8B.B1 to R4C8B.F1 SLICE_21 +ROUTE 1 0.056 R4C8B.F1 to R4C8B.C0 N_415 +CTOF_DEL --- 0.101 R4C8B.C0 to R4C8B.F0 SLICE_21 +ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 CmdUFMWrite_3 (to PHI2_c) -------- - 0.605 (38.7% logic, 61.3% route), 2 logic levels. + 0.615 (54.5% logic, 45.5% route), 3 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_17: + Source Clock Path PHI2 to SLICE_21: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R3C11C.CLK PHI2_c +ROUTE 21 1.240 8.PADDI to R4C8B.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_21: Name Fanout Delay (ns) Site Resource -ROUTE 21 1.240 8.PADDI to R3C9C.CLK PHI2_c +ROUTE 21 1.240 8.PADDI to R4C8B.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. @@ -1728,7 +1736,7 @@ ROUTE 21 1.240 8.PADDI to R3C9C.CLK PHI2_c ================================================================================ Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; - 878 items scored, 0 timing errors detected. + 891 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- @@ -1753,8 +1761,8 @@ Passed: The following path meets requirements by 0.304ns Data path SLICE_12 to SLICE_12: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R4C11C.CLK to R4C11C.Q0 SLICE_12 (from RCLK_c) -ROUTE 1 0.152 R4C11C.Q0 to R4C11C.M1 CASr (to RCLK_c) +REG_DEL --- 0.133 R6C8B.CLK to R6C8B.Q0 SLICE_12 (from RCLK_c) +ROUTE 1 0.152 R6C8B.Q0 to R6C8B.M1 CASr (to RCLK_c) -------- 0.285 (46.7% logic, 53.3% route), 1 logic levels. @@ -1763,57 +1771,14 @@ ROUTE 1 0.152 R4C11C.Q0 to R4C11C.M1 CASr (to RCLK_c) Source Clock Path RCLK to SLICE_12: Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R4C11C.CLK RCLK_c +ROUTE 48 0.651 63.PADDI to R6C8B.CLK RCLK_c -------- 0.651 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_12: Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R4C11C.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.306ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q PHI2r2 (from RCLK_c +) - Destination: FF Data in PHI2r3 (to RCLK_c +) - - Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. - - Constraint Details: - - 0.287ns physical path delay SLICE_31 to SLICE_31 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.306ns - - Physical Path Details: - - Data path SLICE_31 to SLICE_31: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C10C.CLK to R3C10C.Q0 SLICE_31 (from RCLK_c) -ROUTE 5 0.154 R3C10C.Q0 to R3C10C.M1 PHI2r2 (to RCLK_c) - -------- - 0.287 (46.3% logic, 53.7% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_31: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R3C10C.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_31: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R3C10C.CLK RCLK_c +ROUTE 48 0.651 63.PADDI to R6C8B.CLK RCLK_c -------- 0.651 (0.0% logic, 100.0% route), 0 logic levels. @@ -1839,8 +1804,8 @@ Passed: The following path meets requirements by 0.306ns Data path SLICE_32 to SLICE_32: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C11A.CLK to R5C11A.Q0 SLICE_32 (from RCLK_c) -ROUTE 2 0.154 R5C11A.Q0 to R5C11A.M1 RASr (to RCLK_c) +REG_DEL --- 0.133 R5C13C.CLK to R5C13C.Q0 SLICE_32 (from RCLK_c) +ROUTE 2 0.154 R5C13C.Q0 to R5C13C.M1 RASr (to RCLK_c) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. @@ -1849,18 +1814,319 @@ ROUTE 2 0.154 R5C11A.Q0 to R5C11A.M1 RASr (to RCLK_c) Source Clock Path RCLK to SLICE_32: Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R5C11A.CLK RCLK_c +ROUTE 48 0.651 63.PADDI to R5C13C.CLK RCLK_c -------- 0.651 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_32: Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R5C11A.CLK RCLK_c +ROUTE 48 0.651 63.PADDI to R5C13C.CLK RCLK_c -------- 0.651 (0.0% logic, 100.0% route), 0 logic levels. +Passed: The following path meets requirements by 0.311ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q PHI2r2 (from RCLK_c +) + Destination: FF Data in PHI2r3 (to RCLK_c +) + + Delay: 0.292ns (45.5% logic, 54.5% route), 1 logic levels. + + Constraint Details: + + 0.292ns physical path delay SLICE_31 to SLICE_31 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.311ns + + Physical Path Details: + + Data path SLICE_31 to SLICE_31: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R4C7D.CLK to R4C7D.Q0 SLICE_31 (from RCLK_c) +ROUTE 5 0.159 R4C7D.Q0 to R4C7D.M1 PHI2r2 (to RCLK_c) + -------- + 0.292 (45.5% logic, 54.5% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_31: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 0.651 63.PADDI to R4C7D.CLK RCLK_c + -------- + 0.651 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_31: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 0.651 63.PADDI to R4C7D.CLK RCLK_c + -------- + 0.651 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.318ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q wb_adr[7] (from RCLK_c +) + Destination: EFB Port ufmefb/EFBInst_0(ASIC) (to RCLK_c +) + + Delay: 0.304ns (43.8% logic, 56.3% route), 1 logic levels. + + Constraint Details: + + 0.304ns physical path delay SLICE_50 to ufmefb/EFBInst_0 meets + -0.068ns WBADRI_HLD and + 0.000ns delay constraint less + -0.054ns skew requirement (totaling -0.014ns) by 0.318ns + + Physical Path Details: + + Data path SLICE_50 to ufmefb/EFBInst_0: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R2C2B.CLK to R2C2B.Q1 SLICE_50 (from RCLK_c) +ROUTE 1 0.171 R2C2B.Q1 to EFB.WBADRI7 wb_adr[7] (to RCLK_c) + -------- + 0.304 (43.8% logic, 56.3% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_50: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 0.651 63.PADDI to R2C2B.CLK RCLK_c + -------- + 0.651 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to ufmefb/EFBInst_0: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 0.705 63.PADDI to EFB.WBCLKI RCLK_c + -------- + 0.705 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.333ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q wb_adr[2] (from RCLK_c +) + Destination: EFB Port ufmefb/EFBInst_0(ASIC) (to RCLK_c +) + + Delay: 0.306ns (43.5% logic, 56.5% route), 1 logic levels. + + Constraint Details: + + 0.306ns physical path delay SLICE_48 to ufmefb/EFBInst_0 meets + -0.081ns WBADRI_HLD and + 0.000ns delay constraint less + -0.054ns skew requirement (totaling -0.027ns) by 0.333ns + + Physical Path Details: + + Data path SLICE_48 to ufmefb/EFBInst_0: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R2C2C.CLK to R2C2C.Q0 SLICE_48 (from RCLK_c) +ROUTE 2 0.173 R2C2C.Q0 to EFB.WBADRI2 wb_adr[2] (to RCLK_c) + -------- + 0.306 (43.5% logic, 56.5% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_48: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 0.651 63.PADDI to R2C2C.CLK RCLK_c + -------- + 0.651 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to ufmefb/EFBInst_0: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 0.705 63.PADDI to EFB.WBCLKI RCLK_c + -------- + 0.705 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.347ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q wb_dati[3] (from RCLK_c +) + Destination: EFB Port ufmefb/EFBInst_0(ASIC) (to RCLK_c +) + + Delay: 0.306ns (43.5% logic, 56.5% route), 1 logic levels. + + Constraint Details: + + 0.306ns physical path delay SLICE_53 to ufmefb/EFBInst_0 meets + -0.095ns WBDATI_HLD and + 0.000ns delay constraint less + -0.054ns skew requirement (totaling -0.041ns) by 0.347ns + + Physical Path Details: + + Data path SLICE_53 to ufmefb/EFBInst_0: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R2C3C.CLK to R2C3C.Q1 SLICE_53 (from RCLK_c) +ROUTE 2 0.173 R2C3C.Q1 to EFB.WBDATI3 wb_dati[3] (to RCLK_c) + -------- + 0.306 (43.5% logic, 56.5% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_53: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 0.651 63.PADDI to R2C3C.CLK RCLK_c + -------- + 0.651 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to ufmefb/EFBInst_0: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 0.705 63.PADDI to EFB.WBCLKI RCLK_c + -------- + 0.705 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.350ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q wb_dati[4] (from RCLK_c +) + Destination: EFB Port ufmefb/EFBInst_0(ASIC) (to RCLK_c +) + + Delay: 0.307ns (43.3% logic, 56.7% route), 1 logic levels. + + Constraint Details: + + 0.307ns physical path delay SLICE_54 to ufmefb/EFBInst_0 meets + -0.097ns WBDATI_HLD and + 0.000ns delay constraint less + -0.054ns skew requirement (totaling -0.043ns) by 0.350ns + + Physical Path Details: + + Data path SLICE_54 to ufmefb/EFBInst_0: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R2C3D.CLK to R2C3D.Q0 SLICE_54 (from RCLK_c) +ROUTE 2 0.174 R2C3D.Q0 to EFB.WBDATI4 wb_dati[4] (to RCLK_c) + -------- + 0.307 (43.3% logic, 56.7% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_54: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 0.651 63.PADDI to R2C3D.CLK RCLK_c + -------- + 0.651 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to ufmefb/EFBInst_0: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 0.705 63.PADDI to EFB.WBCLKI RCLK_c + -------- + 0.705 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.355ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RASr2 (from RCLK_c +) + Destination: FF Data in S[1] (to RCLK_c +) + + Delay: 0.298ns (44.6% logic, 55.4% route), 1 logic levels. + + Constraint Details: + + 0.298ns physical path delay SLICE_32 to SLICE_43 meets + -0.057ns LSR_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.057ns) by 0.355ns + + Physical Path Details: + + Data path SLICE_32 to SLICE_43: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C13C.CLK to R5C13C.Q1 SLICE_32 (from RCLK_c) +ROUTE 10 0.165 R5C13C.Q1 to R5C13B.LSR RASr2 (to RCLK_c) + -------- + 0.298 (44.6% logic, 55.4% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_32: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 0.651 63.PADDI to R5C13C.CLK RCLK_c + -------- + 0.651 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_43: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 0.651 63.PADDI to R5C13B.CLK RCLK_c + -------- + 0.651 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.358ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q wb_adr[3] (from RCLK_c +) + Destination: EFB Port ufmefb/EFBInst_0(ASIC) (to RCLK_c +) + + Delay: 0.307ns (43.3% logic, 56.7% route), 1 logic levels. + + Constraint Details: + + 0.307ns physical path delay SLICE_48 to ufmefb/EFBInst_0 meets + -0.105ns WBADRI_HLD and + 0.000ns delay constraint less + -0.054ns skew requirement (totaling -0.051ns) by 0.358ns + + Physical Path Details: + + Data path SLICE_48 to ufmefb/EFBInst_0: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R2C2C.CLK to R2C2C.Q1 SLICE_48 (from RCLK_c) +ROUTE 2 0.174 R2C2C.Q1 to EFB.WBADRI3 wb_adr[3] (to RCLK_c) + -------- + 0.307 (43.3% logic, 56.7% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_48: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 0.651 63.PADDI to R2C2C.CLK RCLK_c + -------- + 0.651 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to ufmefb/EFBInst_0: + + Name Fanout Delay (ns) Site Resource +ROUTE 48 0.705 63.PADDI to EFB.WBCLKI RCLK_c + -------- + 0.705 (0.0% logic, 100.0% route), 0 logic levels. + + Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) @@ -1882,10 +2148,10 @@ Passed: The following path meets requirements by 0.379ns Data path SLICE_0 to SLICE_0: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R2C7A.CLK to R2C7A.Q1 SLICE_0 (from RCLK_c) -ROUTE 3 0.132 R2C7A.Q1 to R2C7A.A1 FS[0] -CTOF_DEL --- 0.101 R2C7A.A1 to R2C7A.F1 SLICE_0 -ROUTE 1 0.000 R2C7A.F1 to R2C7A.DI1 FS_s[0] (to RCLK_c) +REG_DEL --- 0.133 R6C2A.CLK to R6C2A.Q1 SLICE_0 (from RCLK_c) +ROUTE 3 0.132 R6C2A.Q1 to R6C2A.A1 FS[0] +CTOF_DEL --- 0.101 R6C2A.A1 to R6C2A.F1 SLICE_0 +ROUTE 1 0.000 R6C2A.F1 to R6C2A.DI1 FS_s[0] (to RCLK_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. @@ -1894,284 +2160,14 @@ ROUTE 1 0.000 R2C7A.F1 to R2C7A.DI1 FS_s[0] (to RCLK_c) Source Clock Path RCLK to SLICE_0: Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R2C7A.CLK RCLK_c +ROUTE 48 0.651 63.PADDI to R6C2A.CLK RCLK_c -------- 0.651 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_0: Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R2C7A.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.379ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[17] (from RCLK_c +) - Destination: FF Data in FS[17] (to RCLK_c +) - - Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. - - Constraint Details: - - 0.366ns physical path delay SLICE_1 to SLICE_1 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.379ns - - Physical Path Details: - - Data path SLICE_1 to SLICE_1: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R2C9B.CLK to R2C9B.Q0 SLICE_1 (from RCLK_c) -ROUTE 6 0.132 R2C9B.Q0 to R2C9B.A0 FS[17] -CTOF_DEL --- 0.101 R2C9B.A0 to R2C9B.F0 SLICE_1 -ROUTE 1 0.000 R2C9B.F0 to R2C9B.DI0 FS_s[17] (to RCLK_c) - -------- - 0.366 (63.9% logic, 36.1% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_1: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R2C9B.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_1: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R2C9B.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.379ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[16] (from RCLK_c +) - Destination: FF Data in FS[16] (to RCLK_c +) - - Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. - - Constraint Details: - - 0.366ns physical path delay SLICE_2 to SLICE_2 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.379ns - - Physical Path Details: - - Data path SLICE_2 to SLICE_2: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R2C9A.CLK to R2C9A.Q1 SLICE_2 (from RCLK_c) -ROUTE 6 0.132 R2C9A.Q1 to R2C9A.A1 FS[16] -CTOF_DEL --- 0.101 R2C9A.A1 to R2C9A.F1 SLICE_2 -ROUTE 1 0.000 R2C9A.F1 to R2C9A.DI1 FS_s[16] (to RCLK_c) - -------- - 0.366 (63.9% logic, 36.1% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_2: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R2C9A.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_2: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R2C9A.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.379ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q n8MEGEN (from RCLK_c +) - Destination: FF Data in n8MEGEN (to RCLK_c +) - - Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. - - Constraint Details: - - 0.366ns physical path delay SLICE_45 to SLICE_45 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.379ns - - Physical Path Details: - - Data path SLICE_45 to SLICE_45: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R4C8C.CLK to R4C8C.Q0 SLICE_45 (from RCLK_c) -ROUTE 3 0.132 R4C8C.Q0 to R4C8C.A0 n8MEGEN -CTOF_DEL --- 0.101 R4C8C.A0 to R4C8C.F0 SLICE_45 -ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 n8MEGENe_0 (to RCLK_c) - -------- - 0.366 (63.9% logic, 36.1% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_45: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R4C8C.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_45: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R4C8C.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.379ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[10] (from RCLK_c +) - Destination: FF Data in FS[10] (to RCLK_c +) - - Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. - - Constraint Details: - - 0.366ns physical path delay SLICE_5 to SLICE_5 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.379ns - - Physical Path Details: - - Data path SLICE_5 to SLICE_5: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R2C8B.CLK to R2C8B.Q1 SLICE_5 (from RCLK_c) -ROUTE 21 0.132 R2C8B.Q1 to R2C8B.A1 FS[10] -CTOF_DEL --- 0.101 R2C8B.A1 to R2C8B.F1 SLICE_5 -ROUTE 1 0.000 R2C8B.F1 to R2C8B.DI1 FS_s[10] (to RCLK_c) - -------- - 0.366 (63.9% logic, 36.1% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_5: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R2C8B.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_5: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R2C8B.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.379ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q wb_req (from RCLK_c +) - Destination: FF Data in wb_req (to RCLK_c +) - - Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. - - Constraint Details: - - 0.366ns physical path delay SLICE_56 to SLICE_56 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.379ns - - Physical Path Details: - - Data path SLICE_56 to SLICE_56: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R4C7A.CLK to R4C7A.Q0 SLICE_56 (from RCLK_c) -ROUTE 3 0.132 R4C7A.Q0 to R4C7A.A0 wb_req -CTOF_DEL --- 0.101 R4C7A.A0 to R4C7A.F0 SLICE_56 -ROUTE 1 0.000 R4C7A.F0 to R4C7A.DI0 wb_reqe_0 (to RCLK_c) - -------- - 0.366 (63.9% logic, 36.1% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_56: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R4C7A.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_56: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R4C7A.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.379ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q wb_rst (from RCLK_c +) - Destination: FF Data in wb_rst (to RCLK_c +) - - Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. - - Constraint Details: - - 0.366ns physical path delay SLICE_57 to SLICE_57 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.379ns - - Physical Path Details: - - Data path SLICE_57 to SLICE_57: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R4C6B.CLK to R4C6B.Q0 SLICE_57 (from RCLK_c) -ROUTE 2 0.132 R4C6B.Q0 to R4C6B.A0 wb_rst -CTOF_DEL --- 0.101 R4C6B.A0 to R4C6B.F0 SLICE_57 -ROUTE 1 0.000 R4C6B.F0 to R4C6B.DI0 wb_rste_0 (to RCLK_c) - -------- - 0.366 (63.9% logic, 36.1% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_57: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R4C6B.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_57: - - Name Fanout Delay (ns) Site Resource -ROUTE 47 0.651 63.PADDI to R4C6B.CLK RCLK_c +ROUTE 48 0.651 63.PADDI to R6C2A.CLK RCLK_c -------- 0.651 (0.0% logic, 100.0% route), 0 logic levels. @@ -2212,7 +2208,7 @@ Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11 Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10 No transfer within this clock domain is found -Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47 +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 48 Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ; Data transfers from: @@ -2242,7 +2238,7 @@ Clock Domain: PHI2_c Source: PHI2.PAD Loads: 21 Timing errors: 0 Score: 0 Cumulative negative slack: 0 -Constraints cover 1025 paths, 4 nets, and 758 connections (74.53% coverage) +Constraints cover 1038 paths, 4 nets, and 750 connections (74.18% coverage) diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_vo.sdf b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_vo.sdf index deea31f..2b8afa0 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_vo.sdf +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_vo.sdf @@ -1,7 +1,7 @@ (DELAYFILE (SDFVERSION "3.0") (DESIGN "RAM2GS") - (DATE "Thu Sep 21 05:40:09 2023") + (DATE "Sat Nov 18 02:06:21 2023") (VENDOR "Lattice") (PROGRAM "ldbanno") (VERSION "Diamond (64-bit) 3.12.1.454") @@ -305,7 +305,7 @@ (INSTANCE SLICE_12) (DELAY (ABSOLUTE - (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) (IOPATH CLK Q1 (392:422:452)(392:422:452)) ) @@ -324,9 +324,11 @@ (INSTANCE SLICE_16) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) ) @@ -390,6 +392,24 @@ (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) ) ) + (CELL + (CELLTYPE "SLICE_19") + (INSTANCE SLICE_19) + (DELAY + (ABSOLUTE + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) (CELL (CELLTYPE "SLICE_20") (INSTANCE SLICE_20) @@ -416,7 +436,7 @@ (INSTANCE SLICE_21) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) @@ -443,8 +463,8 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) ) ) @@ -489,7 +509,7 @@ (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) ) ) @@ -507,9 +527,9 @@ (INSTANCE SLICE_25) (DELAY (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) ) ) @@ -526,8 +546,11 @@ (INSTANCE SLICE_26) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) @@ -546,10 +569,10 @@ (INSTANCE SLICE_27) (DELAY (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) (IOPATH CLK Q1 (392:422:452)(392:422:452)) @@ -570,7 +593,10 @@ (INSTANCE SLICE_28) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) @@ -596,7 +622,7 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) ) @@ -617,7 +643,7 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) @@ -636,8 +662,8 @@ (INSTANCE SLICE_31) (DELAY (ABSOLUTE + (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) (IOPATH CLK Q1 (392:422:452)(392:422:452)) ) @@ -656,10 +682,10 @@ (INSTANCE SLICE_32) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) (IOPATH CLK Q1 (392:422:452)(392:422:452)) ) @@ -678,9 +704,9 @@ (INSTANCE SLICE_33) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) @@ -724,7 +750,7 @@ (DELAY (ABSOLUTE (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) @@ -746,8 +772,8 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) @@ -790,7 +816,7 @@ (INSTANCE SLICE_38) (DELAY (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -812,8 +838,8 @@ (INSTANCE SLICE_39) (DELAY (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) @@ -856,10 +882,10 @@ (INSTANCE SLICE_41) (DELAY (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) (IOPATH CLK Q1 (392:422:452)(392:422:452)) ) @@ -878,10 +904,10 @@ (INSTANCE SLICE_42) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) (IOPATH CLK Q1 (392:422:452)(392:422:452)) ) @@ -904,7 +930,7 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) ) @@ -974,7 +1000,7 @@ (DELAY (ABSOLUTE (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) @@ -1025,9 +1051,9 @@ (INSTANCE SLICE_48) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) (IOPATH CLK Q1 (392:422:452)(392:422:452)) @@ -1050,11 +1076,9 @@ (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) (IOPATH CLK Q1 (392:422:452)(392:422:452)) @@ -1075,9 +1099,8 @@ (INSTANCE SLICE_50) (DELAY (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -1160,7 +1183,7 @@ (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) (IOPATH CLK Q1 (392:422:452)(392:422:452)) @@ -1183,7 +1206,7 @@ (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) @@ -1238,8 +1261,8 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) ) @@ -1266,7 +1289,6 @@ (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) ) @@ -1284,7 +1306,6 @@ (INSTANCE SLICE_58) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) @@ -1308,8 +1329,8 @@ ) ) (CELL - (CELLTYPE "wb_dati_5_1_iv_0_o3_5__SLICE_59") - (INSTANCE wb_dati_5_1_iv_0_o3\[5\]\/SLICE_59) + (CELLTYPE "wb_dati_5_1_iv_0_0_o2_5__SLICE_59") + (INSTANCE wb_dati_5_1_iv_0_0_o2\[5\]\/SLICE_59) (DELAY (ABSOLUTE (IOPATH D1 OFX0 (457:589:721)(457:589:721)) @@ -1325,18 +1346,18 @@ ) ) (CELL - (CELLTYPE "SLICE_60") - (INSTANCE SLICE_60) + (CELLTYPE "wb_adr_5_i_0_1_0__SLICE_60") + (INSTANCE wb_adr_5_i_0_1\[0\]\/SLICE_60) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH D1 OFX0 (457:589:721)(457:589:721)) + (IOPATH C1 OFX0 (457:589:721)(457:589:721)) + (IOPATH A1 OFX0 (457:589:721)(457:589:721)) + (IOPATH D0 OFX0 (457:589:721)(457:589:721)) + (IOPATH C0 OFX0 (457:589:721)(457:589:721)) + (IOPATH B0 OFX0 (457:589:721)(457:589:721)) + (IOPATH A0 OFX0 (457:589:721)(457:589:721)) + (IOPATH M0 OFX0 (322:349:376)(322:349:376)) ) ) ) @@ -1352,6 +1373,7 @@ (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) ) ) ) @@ -1367,6 +1389,7 @@ (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) ) ) ) @@ -1414,7 +1437,6 @@ (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) ) ) ) @@ -1426,10 +1448,8 @@ (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) ) ) @@ -1456,10 +1476,11 @@ (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) ) ) ) @@ -1474,7 +1495,6 @@ (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) ) ) @@ -1491,6 +1511,7 @@ (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) ) ) ) @@ -1499,12 +1520,11 @@ (INSTANCE SLICE_71) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) ) ) @@ -1517,7 +1537,7 @@ (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -1531,7 +1551,6 @@ (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) @@ -1547,6 +1566,7 @@ (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) @@ -1561,7 +1581,9 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) @@ -1576,73 +1598,11 @@ (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "SLICE_77") - (INSTANCE SLICE_77) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "SLICE_78") - (INSTANCE SLICE_78) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "SLICE_79") - (INSTANCE SLICE_79) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "SLICE_80") - (INSTANCE SLICE_80) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) (IOPATH CLK Q1 (392:422:452)(392:422:452)) ) @@ -1656,6 +1616,72 @@ (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) ) ) + (CELL + (CELLTYPE "SLICE_77") + (INSTANCE SLICE_77) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_78") + (INSTANCE SLICE_78) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_79") + (INSTANCE SLICE_79) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_80") + (INSTANCE SLICE_80) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) (CELL (CELLTYPE "SLICE_81") (INSTANCE SLICE_81) @@ -1663,6 +1689,7 @@ (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) @@ -1680,19 +1707,12 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) ) ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) - (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) - ) ) (CELL (CELLTYPE "SLICE_83") @@ -1701,6 +1721,7 @@ (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) @@ -1715,7 +1736,6 @@ (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) @@ -1752,7 +1772,6 @@ (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) ) ) ) @@ -1762,8 +1781,7 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) @@ -1778,8 +1796,6 @@ (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) @@ -1792,6 +1808,7 @@ (INSTANCE SLICE_89) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) @@ -1824,7 +1841,6 @@ (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) @@ -1838,9 +1854,8 @@ (INSTANCE SLICE_92) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) @@ -1870,8 +1885,6 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) @@ -1886,7 +1899,7 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) @@ -1899,8 +1912,8 @@ (INSTANCE SLICE_96) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) @@ -1927,8 +1940,8 @@ (INSTANCE SLICE_98) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) @@ -1941,8 +1954,10 @@ (INSTANCE SLICE_99) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) @@ -1955,7 +1970,7 @@ (INSTANCE SLICE_100) (DELAY (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) @@ -1971,10 +1986,11 @@ (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) ) ) ) @@ -1984,6 +2000,8 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) @@ -1997,8 +2015,10 @@ (INSTANCE SLICE_103) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) @@ -2011,11 +2031,11 @@ (INSTANCE SLICE_104) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) ) @@ -2027,12 +2047,11 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) ) ) ) @@ -2044,10 +2063,10 @@ (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) ) ) ) @@ -2057,36 +2076,23 @@ (DELAY (ABSOLUTE (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) ) ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) ) (CELL (CELLTYPE "SLICE_108") (INSTANCE SLICE_108) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) ) ) ) @@ -2099,9 +2105,8 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) ) ) ) @@ -2112,11 +2117,8 @@ (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) ) ) @@ -2127,8 +2129,11 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) ) ) @@ -2139,10 +2144,10 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) ) ) @@ -2154,8 +2159,10 @@ (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) ) ) ) @@ -2166,7 +2173,7 @@ (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -2180,10 +2187,10 @@ (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) ) ) ) @@ -2192,11 +2199,11 @@ (INSTANCE SLICE_116) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) ) ) @@ -2207,11 +2214,9 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) ) ) ) @@ -2222,10 +2227,8 @@ (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) ) ) ) @@ -2238,8 +2241,8 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) ) ) ) @@ -2262,11 +2265,11 @@ (INSTANCE SLICE_121) (DELAY (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) ) ) ) @@ -2277,22 +2280,9 @@ (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "SLICE_123") - (INSTANCE SLICE_123) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) ) ) ) @@ -2468,6 +2458,32 @@ ) ) ) + (CELL + (CELLTYPE "RCLKout") + (INSTANCE RCLKout_I) + (DELAY + (ABSOLUTE + (IOPATH IOLDO RCLKout (1946:2086:2226)(1946:2086:2226)) + ) + ) + ) + (CELL + (CELLTYPE "RCLKout_MGIOL") + (INSTANCE RCLKout_MGIOL) + (DELAY + (ABSOLUTE + (IOPATH CLK IOLDO (1172:1208:1244)(1172:1208:1244)) + ) + ) + (TIMINGCHECK + (SETUPHOLD ONEG (posedge CLK) (72:72:72)(-52:-52:-52)) + (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (4807:4807:4807)) + (WIDTH (negedge CLK) (4807:4807:4807)) + ) + ) (CELL (CELLTYPE "RCLK") (INSTANCE RCLK_I) @@ -3463,8 +3479,8 @@ (DELAY (ABSOLUTE (INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_0/Q1 SLICE_92/C1 (984:1138:1292)(984:1138:1292)) - (INTERCONNECT SLICE_0/Q1 SLICE_121/A1 (1183:1347:1512)(1183:1347:1512)) + (INTERCONNECT SLICE_0/Q1 SLICE_89/C1 (1240:1417:1595)(1240:1417:1595)) + (INTERCONNECT SLICE_0/Q1 SLICE_121/D1 (1229:1351:1474)(1229:1351:1474)) (INTERCONNECT SLICE_0/F1 SLICE_0/DI1 (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_0/CLK (1833:1926:2019)(1833:1926:2019)) (INTERCONNECT RCLK_I/PADDI SLICE_1/CLK (1833:1926:2019)(1833:1926:2019)) @@ -3525,11 +3541,12 @@ (INTERCONNECT RCLK_I/PADDI SLICE_56/CLK (1833:1926:2019)(1833:1926:2019)) (INTERCONNECT RCLK_I/PADDI SLICE_57/CLK (1833:1926:2019)(1833:1926:2019)) (INTERCONNECT RCLK_I/PADDI SLICE_58/CLK (1833:1926:2019)(1833:1926:2019)) - (INTERCONNECT RCLK_I/PADDI SLICE_107/CLK (1833:1926:2019)(1833:1926:2019)) + (INTERCONNECT RCLK_I/PADDI SLICE_77/CLK (1833:1926:2019)(1833:1926:2019)) (INTERCONNECT RCLK_I/PADDI PHI2_MGIOL/CLK (1980:2086:2192)(1980:2086:2192)) (INTERCONNECT RCLK_I/PADDI nRCAS_MGIOL/CLK (1980:2086:2192)(1980:2086:2192)) (INTERCONNECT RCLK_I/PADDI nRRAS_MGIOL/CLK (1980:2086:2192)(1980:2086:2192)) (INTERCONNECT RCLK_I/PADDI nRWE_MGIOL/CLK (1980:2086:2192)(1980:2086:2192)) + (INTERCONNECT RCLK_I/PADDI RCLKout_MGIOL/CLK (1980:2086:2192)(1980:2086:2192)) (INTERCONNECT RCLK_I/PADDI nRCS_MGIOL/CLK (1980:2086:2192)(1980:2086:2192)) (INTERCONNECT RCLK_I/PADDI RA\[10\]_MGIOL/CLK (1980:2086:2192)(1980:2086:2192)) (INTERCONNECT RCLK_I/PADDI @@ -3537,230 +3554,224 @@ (1980:2086:2192)) (INTERCONNECT SLICE_0/FCO SLICE_9/FCI (0:0:0)(0:0:0)) (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_1/Q0 SLICE_56/D1 (909:1001:1093)(909:1001:1093)) - (INTERCONNECT SLICE_1/Q0 SLICE_57/B1 (1526:1718:1911)(1526:1718:1911)) - (INTERCONNECT SLICE_1/Q0 SLICE_66/B1 (1145:1304:1464)(1145:1304:1464)) - (INTERCONNECT SLICE_1/Q0 SLICE_97/B1 (1526:1718:1911)(1526:1718:1911)) - (INTERCONNECT SLICE_1/Q0 SLICE_123/B0 (1526:1718:1911)(1526:1718:1911)) + (INTERCONNECT SLICE_1/Q0 SLICE_29/A1 (1086:1247:1409)(1086:1247:1409)) + (INTERCONNECT SLICE_1/Q0 SLICE_58/B1 (1129:1295:1461)(1129:1295:1461)) + (INTERCONNECT SLICE_1/Q0 SLICE_64/C1 (1345:1537:1729)(1345:1537:1729)) + (INTERCONNECT SLICE_1/Q0 SLICE_91/D1 (887:985:1083)(887:985:1083)) + (INTERCONNECT SLICE_1/Q0 SLICE_94/C0 (1345:1537:1729)(1345:1537:1729)) + (INTERCONNECT SLICE_1/Q0 SLICE_99/B0 (791:920:1049)(791:920:1049)) (INTERCONNECT SLICE_1/F0 SLICE_1/DI0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_2/FCO SLICE_1/FCI (0:0:0)(0:0:0)) (INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_2/Q1 SLICE_56/C1 (920:1067:1214)(920:1067:1214)) - (INTERCONNECT SLICE_2/Q1 SLICE_57/C1 (1295:1474:1654)(1295:1474:1654)) - (INTERCONNECT SLICE_2/Q1 SLICE_66/A1 (1113:1270:1427)(1113:1270:1427)) - (INTERCONNECT SLICE_2/Q1 SLICE_97/C1 (1295:1474:1654)(1295:1474:1654)) - (INTERCONNECT SLICE_2/Q1 SLICE_123/C0 (1295:1474:1654)(1295:1474:1654)) - (INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (481:575:669)(481:575:669)) - (INTERCONNECT SLICE_2/Q0 SLICE_49/A1 (1451:1643:1835)(1451:1643:1835)) - (INTERCONNECT SLICE_2/Q0 SLICE_49/A0 (1451:1643:1835)(1451:1643:1835)) - (INTERCONNECT SLICE_2/Q0 SLICE_50/D0 (1568:1729:1891)(1568:1729:1891)) - (INTERCONNECT SLICE_2/Q0 SLICE_57/A1 (1820:2044:2268)(1820:2044:2268)) - (INTERCONNECT SLICE_2/Q0 SLICE_58/A1 (1820:2044:2268)(1820:2044:2268)) - (INTERCONNECT SLICE_2/Q0 SLICE_66/C1 (980:1135:1291)(980:1135:1291)) - (INTERCONNECT SLICE_2/Q0 SLICE_97/A0 (1820:2044:2268)(1820:2044:2268)) - (INTERCONNECT SLICE_2/Q0 SLICE_123/A0 (1820:2044:2268)(1820:2044:2268)) + (INTERCONNECT SLICE_2/Q1 SLICE_29/B1 (772:910:1048)(772:910:1048)) + (INTERCONNECT SLICE_2/Q1 SLICE_58/A1 (1017:1188:1359)(1017:1188:1359)) + (INTERCONNECT SLICE_2/Q1 SLICE_64/D1 (807:912:1018)(807:912:1018)) + (INTERCONNECT SLICE_2/Q1 SLICE_91/C1 (818:978:1139)(818:978:1139)) + (INTERCONNECT SLICE_2/Q1 SLICE_94/D0 (530:600:670)(530:600:670)) + (INTERCONNECT SLICE_2/Q1 SLICE_99/D0 (530:600:670)(530:600:670)) + (INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_2/Q0 SLICE_29/C1 (541:666:791)(541:666:791)) + (INTERCONNECT SLICE_2/Q0 SLICE_64/B1 (1044:1217:1390)(1044:1217:1390)) + (INTERCONNECT SLICE_2/Q0 SLICE_91/A1 (1012:1182:1353)(1012:1182:1353)) + (INTERCONNECT SLICE_2/Q0 SLICE_94/A0 (740:875:1011)(740:875:1011)) + (INTERCONNECT SLICE_2/Q0 SLICE_99/A0 (740:875:1011)(740:875:1011)) (INTERCONNECT SLICE_2/F1 SLICE_2/DI1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_2/F0 SLICE_2/DI0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_3/FCO SLICE_2/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q1 SLICE_3/A1 (481:575:669)(481:575:669)) - (INTERCONNECT SLICE_3/Q1 SLICE_62/D0 (1431:1561:1692)(1431:1561:1692)) - (INTERCONNECT SLICE_3/Q1 SLICE_69/C1 (879:1031:1183)(879:1031:1183)) - (INTERCONNECT SLICE_3/Q1 SLICE_70/D0 (1296:1423:1551)(1296:1423:1551)) - (INTERCONNECT SLICE_3/Q1 SLICE_75/D1 (1676:1836:1997)(1676:1836:1997)) - (INTERCONNECT SLICE_3/Q1 SLICE_76/B1 (2240:2503:2766)(2240:2503:2766)) - (INTERCONNECT SLICE_3/Q1 SLICE_77/B1 (1490:1688:1886)(1490:1688:1886)) - (INTERCONNECT SLICE_3/Q1 SLICE_87/C1 (1431:1614:1798)(1431:1614:1798)) - (INTERCONNECT SLICE_3/Q1 SLICE_96/D1 (1671:1831:1991)(1671:1831:1991)) - (INTERCONNECT SLICE_3/Q1 SLICE_101/D1 (921:1016:1111)(921:1016:1111)) - (INTERCONNECT SLICE_3/Q1 SLICE_102/B0 (1490:1688:1886)(1490:1688:1886)) - (INTERCONNECT SLICE_3/Q1 SLICE_104/C1 (2389:2673:2957)(2389:2673:2957)) - (INTERCONNECT SLICE_3/Q1 SLICE_104/C0 (2389:2673:2957)(2389:2673:2957)) - (INTERCONNECT SLICE_3/Q1 SLICE_105/D1 (1676:1836:1997)(1676:1836:1997)) - (INTERCONNECT SLICE_3/Q1 SLICE_105/D0 (1676:1836:1997)(1676:1836:1997)) - (INTERCONNECT SLICE_3/Q1 SLICE_106/A1 (1641:1837:2033)(1641:1837:2033)) - (INTERCONNECT SLICE_3/Q1 SLICE_110/C0 (1800:2016:2233)(1800:2016:2233)) - (INTERCONNECT SLICE_3/Q1 SLICE_113/D1 (1671:1831:1991)(1671:1831:1991)) - (INTERCONNECT SLICE_3/Q0 SLICE_3/A0 (481:575:669)(481:575:669)) - (INTERCONNECT SLICE_3/Q0 wb_dati_5_1_iv_0_o3\[5\]\/SLICE_59/A0 (1583:1787:1992) - (1583:1787:1992)) - (INTERCONNECT SLICE_3/Q0 SLICE_63/A0 (1968:2206:2444)(1968:2206:2444)) - (INTERCONNECT SLICE_3/Q0 SLICE_67/B0 (2364:2636:2908)(2364:2636:2908)) - (INTERCONNECT SLICE_3/Q0 SLICE_69/A0 (2285:2557:2829)(2285:2557:2829)) - (INTERCONNECT SLICE_3/Q0 SLICE_70/D1 (1352:1489:1626)(1352:1489:1626)) - (INTERCONNECT SLICE_3/Q0 SLICE_76/A1 (1568:1771:1974)(1568:1771:1974)) - (INTERCONNECT SLICE_3/Q0 SLICE_77/D1 (1373:1512:1651)(1373:1512:1651)) - (INTERCONNECT SLICE_3/Q0 SLICE_87/A0 (1895:2133:2371)(1895:2133:2371)) - (INTERCONNECT SLICE_3/Q0 SLICE_89/D0 (1352:1489:1626)(1352:1489:1626)) - (INTERCONNECT SLICE_3/Q0 SLICE_91/C1 (2086:2347:2609)(2086:2347:2609)) - (INTERCONNECT SLICE_3/Q0 SLICE_95/A1 (1638:1835:2032)(1638:1835:2032)) - (INTERCONNECT SLICE_3/Q0 SLICE_96/A0 (2328:2597:2866)(2328:2597:2866)) - (INTERCONNECT SLICE_3/Q0 SLICE_102/A1 (1192:1362:1533)(1192:1362:1533)) - (INTERCONNECT SLICE_3/Q0 SLICE_104/B1 (1411:1600:1789)(1411:1600:1789)) - (INTERCONNECT SLICE_3/Q0 SLICE_104/B0 (1411:1600:1789)(1411:1600:1789)) - (INTERCONNECT SLICE_3/Q0 SLICE_105/A1 (2328:2597:2866)(2328:2597:2866)) - (INTERCONNECT SLICE_3/Q0 SLICE_105/B0 (1411:1600:1789)(1411:1600:1789)) - (INTERCONNECT SLICE_3/Q0 SLICE_106/C1 (1769:1996:2224)(1769:1996:2224)) - (INTERCONNECT SLICE_3/Q0 SLICE_106/C0 (1769:1996:2224)(1769:1996:2224)) - (INTERCONNECT SLICE_3/Q0 SLICE_109/B1 (1979:2217:2456)(1979:2217:2456)) - (INTERCONNECT SLICE_3/Q0 SLICE_110/D1 (2085:2292:2500)(2085:2292:2500)) + (INTERCONNECT SLICE_3/Q1 SLICE_3/A1 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_3/Q1 SLICE_56/D1 (871:966:1062)(871:966:1062)) + (INTERCONNECT SLICE_3/Q1 SLICE_61/B1 (1509:1708:1907)(1509:1708:1907)) + (INTERCONNECT SLICE_3/Q1 SLICE_61/B0 (1509:1708:1907)(1509:1708:1907)) + (INTERCONNECT SLICE_3/Q1 SLICE_67/D0 (929:1023:1117)(929:1023:1117)) + (INTERCONNECT SLICE_3/Q1 SLICE_73/D1 (1699:1860:2021)(1699:1860:2021)) + (INTERCONNECT SLICE_3/Q1 SLICE_74/B1 (1941:2170:2399)(1941:2170:2399)) + (INTERCONNECT SLICE_3/Q1 SLICE_84/D1 (1699:1860:2021)(1699:1860:2021)) + (INTERCONNECT SLICE_3/Q1 SLICE_85/B1 (2305:2565:2826)(2305:2565:2826)) + (INTERCONNECT SLICE_3/Q1 SLICE_88/D1 (908:1000:1092)(908:1000:1092)) + (INTERCONNECT SLICE_3/Q1 SLICE_94/D1 (929:1023:1117)(929:1023:1117)) + (INTERCONNECT SLICE_3/Q1 SLICE_98/D0 (1699:1860:2021)(1699:1860:2021)) + (INTERCONNECT SLICE_3/Q1 SLICE_99/C1 (1267:1451:1635)(1267:1451:1635)) + (INTERCONNECT SLICE_3/Q1 SLICE_102/C1 (2114:2373:2632)(2114:2373:2632)) + (INTERCONNECT SLICE_3/Q1 SLICE_102/D0 (1324:1452:1581)(1324:1452:1581)) + (INTERCONNECT SLICE_3/Q1 SLICE_105/C0 (1662:1880:2099)(1662:1880:2099)) + (INTERCONNECT SLICE_3/Q1 SLICE_107/C1 (1335:1518:1702)(1335:1518:1702)) + (INTERCONNECT SLICE_3/Q1 SLICE_107/A0 (1861:2090:2319)(1861:2090:2319)) + (INTERCONNECT SLICE_3/Q1 SLICE_118/D1 (1699:1860:2021)(1699:1860:2021)) + (INTERCONNECT SLICE_3/Q0 SLICE_3/A0 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_3/Q0 SLICE_56/C1 (560:676:792)(560:676:792)) + (INTERCONNECT SLICE_3/Q0 wb_dati_5_1_iv_0_0_o2\[5\]\/SLICE_59/D0 (929:1023:1117) + (929:1023:1117)) + (INTERCONNECT SLICE_3/Q0 wb_adr_5_i_0_1\[0\]\/SLICE_60/D1 (924:1017:1111) + (924:1017:1111)) + (INTERCONNECT SLICE_3/Q0 SLICE_61/D0 (924:1017:1111)(924:1017:1111)) + (INTERCONNECT SLICE_3/Q0 SLICE_65/C0 (1310:1491:1672)(1310:1491:1672)) + (INTERCONNECT SLICE_3/Q0 SLICE_72/B0 (1498:1695:1892)(1498:1695:1892)) + (INTERCONNECT SLICE_3/Q0 SLICE_74/D1 (1669:1827:1985)(1669:1827:1985)) + (INTERCONNECT SLICE_3/Q0 SLICE_84/B0 (1566:1762:1959)(1566:1762:1959)) + (INTERCONNECT SLICE_3/Q0 SLICE_85/D0 (2039:2229:2419)(2039:2229:2419)) + (INTERCONNECT SLICE_3/Q0 SLICE_87/A0 (2576:2866:3157)(2576:2866:3157)) + (INTERCONNECT SLICE_3/Q0 SLICE_93/A0 (1861:2090:2319)(1861:2090:2319)) + (INTERCONNECT SLICE_3/Q0 SLICE_97/B0 (1930:2158:2386)(1930:2158:2386)) + (INTERCONNECT SLICE_3/Q0 SLICE_98/B1 (1566:1762:1959)(1566:1762:1959)) + (INTERCONNECT SLICE_3/Q0 SLICE_102/B1 (1566:1762:1959)(1566:1762:1959)) + (INTERCONNECT SLICE_3/Q0 SLICE_102/B0 (1566:1762:1959)(1566:1762:1959)) + (INTERCONNECT SLICE_3/Q0 SLICE_104/D1 (1631:1793:1956)(1631:1793:1956)) + (INTERCONNECT SLICE_3/Q0 SLICE_104/D0 (1631:1793:1956)(1631:1793:1956)) + (INTERCONNECT SLICE_3/Q0 SLICE_105/D1 (919:1012:1105)(919:1012:1105)) + (INTERCONNECT SLICE_3/Q0 SLICE_105/B0 (1541:1735:1929)(1541:1735:1929)) + (INTERCONNECT SLICE_3/Q0 SLICE_107/D0 (919:1012:1105)(919:1012:1105)) + (INTERCONNECT SLICE_3/Q0 SLICE_118/B0 (1566:1762:1959)(1566:1762:1959)) (INTERCONNECT SLICE_3/F1 SLICE_3/DI1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_3/F0 SLICE_3/DI0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_4/FCO SLICE_3/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/Q1 SLICE_4/A1 (481:575:669)(481:575:669)) - (INTERCONNECT SLICE_4/Q1 wb_dati_5_1_iv_0_o3\[5\]\/SLICE_59/C1 (1020:1181:1343) - (1020:1181:1343)) - (INTERCONNECT SLICE_4/Q1 SLICE_63/B1 (1979:2226:2474)(1979:2226:2474)) - (INTERCONNECT SLICE_4/Q1 SLICE_63/B0 (1979:2226:2474)(1979:2226:2474)) - (INTERCONNECT SLICE_4/Q1 SLICE_69/A1 (756:884:1012)(756:884:1012)) - (INTERCONNECT SLICE_4/Q1 SLICE_70/C0 (1353:1543:1733)(1353:1543:1733)) - (INTERCONNECT SLICE_4/Q1 SLICE_73/D0 (1342:1477:1612)(1342:1477:1612)) - (INTERCONNECT SLICE_4/Q1 SLICE_75/D0 (1373:1511:1649)(1373:1511:1649)) - (INTERCONNECT SLICE_4/Q1 SLICE_76/A0 (1219:1391:1563)(1219:1391:1563)) - (INTERCONNECT SLICE_4/Q1 SLICE_77/C1 (932:1082:1232)(932:1082:1232)) - (INTERCONNECT SLICE_4/Q1 SLICE_87/A1 (1546:1753:1960)(1546:1753:1960)) - (INTERCONNECT SLICE_4/Q1 SLICE_95/D1 (1379:1517:1656)(1379:1517:1656)) - (INTERCONNECT SLICE_4/Q1 SLICE_96/B0 (1158:1320:1483)(1158:1320:1483)) - (INTERCONNECT SLICE_4/Q1 SLICE_101/C1 (932:1082:1232)(932:1082:1232)) - (INTERCONNECT SLICE_4/Q1 SLICE_102/C0 (932:1082:1232)(932:1082:1232)) - (INTERCONNECT SLICE_4/Q1 SLICE_104/A1 (1496:1688:1880)(1496:1688:1880)) - (INTERCONNECT SLICE_4/Q1 SLICE_104/A0 (1496:1688:1880)(1496:1688:1880)) - (INTERCONNECT SLICE_4/Q1 SLICE_106/D1 (1737:1916:2096)(1737:1916:2096)) - (INTERCONNECT SLICE_4/Q1 SLICE_106/D0 (1737:1916:2096)(1737:1916:2096)) - (INTERCONNECT SLICE_4/Q1 SLICE_110/B1 (1578:1787:1997)(1578:1787:1997)) - (INTERCONNECT SLICE_4/Q1 SLICE_110/A0 (1219:1391:1563)(1219:1391:1563)) + (INTERCONNECT SLICE_4/Q1 SLICE_4/A1 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_4/Q1 SLICE_56/B1 (786:914:1043)(786:914:1043)) + (INTERCONNECT SLICE_4/Q1 wb_dati_5_1_iv_0_0_o2\[5\]\/SLICE_59/D1 (1256:1385:1514) + (1256:1385:1514)) + (INTERCONNECT SLICE_4/Q1 SLICE_67/A0 (1129:1287:1446)(1129:1287:1446)) + (INTERCONNECT SLICE_4/Q1 SLICE_71/B0 (1488:1684:1880)(1488:1684:1880)) + (INTERCONNECT SLICE_4/Q1 SLICE_72/D0 (929:1023:1117)(929:1023:1117)) + (INTERCONNECT SLICE_4/Q1 SLICE_73/D0 (1631:1792:1954)(1631:1792:1954)) + (INTERCONNECT SLICE_4/Q1 SLICE_74/C1 (1315:1496:1678)(1315:1496:1678)) + (INTERCONNECT SLICE_4/Q1 SLICE_84/C1 (1330:1513:1696)(1330:1513:1696)) + (INTERCONNECT SLICE_4/Q1 SLICE_85/C1 (1315:1496:1678)(1315:1496:1678)) + (INTERCONNECT SLICE_4/Q1 SLICE_86/C1 (1267:1451:1635)(1267:1451:1635)) + (INTERCONNECT SLICE_4/Q1 SLICE_93/C0 (1330:1513:1696)(1330:1513:1696)) + (INTERCONNECT SLICE_4/Q1 SLICE_98/C0 (1330:1513:1696)(1330:1513:1696)) + (INTERCONNECT SLICE_4/Q1 SLICE_102/A1 (1867:2097:2328)(1867:2097:2328)) + (INTERCONNECT SLICE_4/Q1 SLICE_102/A0 (1867:2097:2328)(1867:2097:2328)) + (INTERCONNECT SLICE_4/Q1 SLICE_105/A1 (1499:1689:1880)(1499:1689:1880)) + (INTERCONNECT SLICE_4/Q1 SLICE_105/A0 (1499:1689:1880)(1499:1689:1880)) + (INTERCONNECT SLICE_4/Q1 SLICE_118/C1 (1330:1513:1696)(1330:1513:1696)) + (INTERCONNECT SLICE_4/Q1 SLICE_118/C0 (1330:1513:1696)(1330:1513:1696)) (INTERCONNECT SLICE_4/Q0 SLICE_4/A0 (481:575:669)(481:575:669)) - (INTERCONNECT SLICE_4/Q0 SLICE_29/A1 (1130:1290:1451)(1130:1290:1451)) - (INTERCONNECT SLICE_4/Q0 SLICE_52/B1 (1064:1229:1394)(1064:1229:1394)) - (INTERCONNECT SLICE_4/Q0 SLICE_55/B0 (1064:1229:1394)(1064:1229:1394)) - (INTERCONNECT SLICE_4/Q0 SLICE_62/B1 (1475:1673:1872)(1475:1673:1872)) - (INTERCONNECT SLICE_4/Q0 SLICE_67/A0 (1515:1709:1903)(1515:1709:1903)) - (INTERCONNECT SLICE_4/Q0 SLICE_68/A1 (1130:1290:1451)(1130:1290:1451)) - (INTERCONNECT SLICE_4/Q0 SLICE_69/D0 (1149:1281:1413)(1149:1281:1413)) - (INTERCONNECT SLICE_4/Q0 SLICE_70/A1 (1515:1709:1903)(1515:1709:1903)) - (INTERCONNECT SLICE_4/Q0 SLICE_71/A0 (1500:1692:1885)(1500:1692:1885)) - (INTERCONNECT SLICE_4/Q0 SLICE_73/A0 (1879:2104:2330)(1879:2104:2330)) - (INTERCONNECT SLICE_4/Q0 SLICE_75/A0 (1130:1290:1451)(1130:1290:1451)) - (INTERCONNECT SLICE_4/Q0 SLICE_76/C1 (1213:1398:1583)(1213:1398:1583)) - (INTERCONNECT SLICE_4/Q0 SLICE_77/A0 (1359:1556:1754)(1359:1556:1754)) - (INTERCONNECT SLICE_4/Q0 SLICE_86/D1 (1202:1332:1462)(1202:1332:1462)) - (INTERCONNECT SLICE_4/Q0 SLICE_87/B0 (1444:1642:1840)(1444:1642:1840)) - (INTERCONNECT SLICE_4/Q0 SLICE_89/A0 (1515:1709:1903)(1515:1709:1903)) - (INTERCONNECT SLICE_4/Q0 SLICE_95/A0 (1770:2001:2232)(1770:2001:2232)) - (INTERCONNECT SLICE_4/Q0 SLICE_102/D1 (1186:1314:1443)(1186:1314:1443)) - (INTERCONNECT SLICE_4/Q0 SLICE_109/A1 (1838:2067:2297)(1838:2067:2297)) - (INTERCONNECT SLICE_4/Q0 SLICE_109/A0 (1838:2067:2297)(1838:2067:2297)) - (INTERCONNECT SLICE_4/Q0 SLICE_110/C1 (1213:1398:1583)(1213:1398:1583)) - (INTERCONNECT SLICE_4/Q0 SLICE_110/B0 (1874:2105:2337)(1874:2105:2337)) + (INTERCONNECT SLICE_4/Q0 SLICE_33/B1 (1167:1330:1494)(1167:1330:1494)) + (INTERCONNECT SLICE_4/Q0 SLICE_52/A1 (1880:2105:2331)(1880:2105:2331)) + (INTERCONNECT SLICE_4/Q0 SLICE_55/D0 (1295:1422:1550)(1295:1422:1550)) + (INTERCONNECT SLICE_4/Q0 wb_adr_5_i_0_1\[0\]\/SLICE_60/M0 (1217:1336:1455) + (1217:1336:1455)) + (INTERCONNECT SLICE_4/Q0 SLICE_65/D0 (1300:1428:1556)(1300:1428:1556)) + (INTERCONNECT SLICE_4/Q0 SLICE_66/C1 (1638:1856:2074)(1638:1856:2074)) + (INTERCONNECT SLICE_4/Q0 SLICE_70/D0 (1252:1382:1513)(1252:1382:1513)) + (INTERCONNECT SLICE_4/Q0 SLICE_71/A0 (1505:1698:1891)(1505:1698:1891)) + (INTERCONNECT SLICE_4/Q0 SLICE_72/B1 (1222:1392:1563)(1222:1392:1563)) + (INTERCONNECT SLICE_4/Q0 SLICE_74/B0 (1869:2100:2331)(1869:2100:2331)) + (INTERCONNECT SLICE_4/Q0 SLICE_84/A0 (2250:2507:2765)(2250:2507:2765)) + (INTERCONNECT SLICE_4/Q0 SLICE_85/A1 (1880:2105:2331)(1880:2105:2331)) + (INTERCONNECT SLICE_4/Q0 SLICE_86/A1 (1528:1733:1938)(1528:1733:1938)) + (INTERCONNECT SLICE_4/Q0 SLICE_88/D0 (1318:1457:1597)(1318:1457:1597)) + (INTERCONNECT SLICE_4/Q0 SLICE_97/C0 (2051:2298:2545)(2051:2298:2545)) + (INTERCONNECT SLICE_4/Q0 SLICE_98/D1 (985:1088:1191)(985:1088:1191)) + (INTERCONNECT SLICE_4/Q0 SLICE_99/A1 (1505:1698:1891)(1505:1698:1891)) + (INTERCONNECT SLICE_4/Q0 SLICE_102/D1 (985:1088:1191)(985:1088:1191)) + (INTERCONNECT SLICE_4/Q0 SLICE_104/B1 (1597:1800:2003)(1597:1800:2003)) + (INTERCONNECT SLICE_4/Q0 SLICE_104/B0 (1597:1800:2003)(1597:1800:2003)) (INTERCONNECT SLICE_4/F1 SLICE_4/DI1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_4/F0 SLICE_4/DI0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_5/FCO SLICE_4/FCI (0:0:0)(0:0:0)) (INTERCONNECT SLICE_5/Q1 SLICE_5/A1 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_5/Q1 SLICE_29/D1 (810:904:998)(810:904:998)) - (INTERCONNECT SLICE_5/Q1 SLICE_62/D1 (1585:1746:1908)(1585:1746:1908)) - (INTERCONNECT SLICE_5/Q1 SLICE_65/D1 (1965:2159:2354)(1965:2159:2354)) - (INTERCONNECT SLICE_5/Q1 SLICE_67/A1 (2502:2797:3092)(2502:2797:3092)) - (INTERCONNECT SLICE_5/Q1 SLICE_67/D0 (1965:2159:2354)(1965:2159:2354)) - (INTERCONNECT SLICE_5/Q1 SLICE_68/C1 (821:970:1119)(821:970:1119)) - (INTERCONNECT SLICE_5/Q1 SLICE_69/C0 (1590:1806:2022)(1590:1806:2022)) - (INTERCONNECT SLICE_5/Q1 SLICE_71/D0 (1215:1344:1474)(1215:1344:1474)) - (INTERCONNECT SLICE_5/Q1 SLICE_73/B0 (1821:2050:2279)(1821:2050:2279)) - (INTERCONNECT SLICE_5/Q1 SLICE_76/D1 (1215:1344:1474)(1215:1344:1474)) - (INTERCONNECT SLICE_5/Q1 SLICE_77/B0 (1821:2050:2279)(1821:2050:2279)) - (INTERCONNECT SLICE_5/Q1 SLICE_85/B1 (2582:2877:3172)(2582:2877:3172)) - (INTERCONNECT SLICE_5/Q1 SLICE_87/D0 (1215:1344:1474)(1215:1344:1474)) - (INTERCONNECT SLICE_5/Q1 SLICE_89/B1 (1467:1663:1859)(1467:1663:1859)) - (INTERCONNECT SLICE_5/Q1 SLICE_101/C0 (2351:2633:2915)(2351:2633:2915)) - (INTERCONNECT SLICE_5/Q1 SLICE_102/D0 (2340:2567:2794)(2340:2567:2794)) - (INTERCONNECT SLICE_5/Q1 SLICE_109/D1 (1215:1344:1474)(1215:1344:1474)) - (INTERCONNECT SLICE_5/Q1 SLICE_109/D0 (1215:1344:1474)(1215:1344:1474)) - (INTERCONNECT SLICE_5/Q1 SLICE_110/D0 (1180:1306:1432)(1180:1306:1432)) - (INTERCONNECT SLICE_5/Q1 SLICE_123/D1 (1180:1306:1432)(1180:1306:1432)) - (INTERCONNECT SLICE_5/Q0 SLICE_5/A0 (481:575:669)(481:575:669)) - (INTERCONNECT SLICE_5/Q0 SLICE_54/C0 (1381:1571:1762)(1381:1571:1762)) - (INTERCONNECT SLICE_5/Q0 wb_dati_5_1_iv_0_o3\[5\]\/SLICE_59/M0 (1292:1419:1546) - (1292:1419:1546)) - (INTERCONNECT SLICE_5/Q0 SLICE_62/A1 (1574:1774:1975)(1574:1774:1975)) - (INTERCONNECT SLICE_5/Q0 SLICE_65/C1 (1391:1582:1774)(1391:1582:1774)) - (INTERCONNECT SLICE_5/Q0 SLICE_65/C0 (1391:1582:1774)(1391:1582:1774)) - (INTERCONNECT SLICE_5/Q0 SLICE_67/C1 (1391:1582:1774)(1391:1582:1774)) - (INTERCONNECT SLICE_5/Q0 SLICE_68/D1 (1691:1861:2031)(1691:1861:2031)) - (INTERCONNECT SLICE_5/Q0 SLICE_69/B0 (793:924:1055)(793:924:1055)) - (INTERCONNECT SLICE_5/Q0 SLICE_71/C0 (1386:1577:1768)(1386:1577:1768)) - (INTERCONNECT SLICE_5/Q0 SLICE_73/C0 (1381:1571:1762)(1381:1571:1762)) - (INTERCONNECT SLICE_5/Q0 SLICE_76/B0 (1242:1413:1585)(1242:1413:1585)) - (INTERCONNECT SLICE_5/Q0 SLICE_77/D0 (1248:1378:1508)(1248:1378:1508)) - (INTERCONNECT SLICE_5/Q0 SLICE_89/C1 (1391:1582:1774)(1391:1582:1774)) - (INTERCONNECT SLICE_5/Q0 SLICE_91/B1 (793:924:1055)(793:924:1055)) - (INTERCONNECT SLICE_5/Q0 SLICE_101/B0 (1163:1326:1489)(1163:1326:1489)) - (INTERCONNECT SLICE_5/Q0 SLICE_109/C1 (1386:1577:1768)(1386:1577:1768)) - (INTERCONNECT SLICE_5/Q0 SLICE_109/C0 (1386:1577:1768)(1386:1577:1768)) - (INTERCONNECT SLICE_5/Q0 SLICE_113/B0 (1163:1326:1489)(1163:1326:1489)) - (INTERCONNECT SLICE_5/Q0 SLICE_123/B1 (1163:1326:1489)(1163:1326:1489)) + (INTERCONNECT SLICE_5/Q1 SLICE_33/A1 (1030:1190:1351)(1030:1190:1351)) + (INTERCONNECT SLICE_5/Q1 wb_adr_5_i_0_1\[0\]\/SLICE_60/A0 (1030:1190:1351) + (1030:1190:1351)) + (INTERCONNECT SLICE_5/Q1 SLICE_65/B1 (1452:1649:1846)(1452:1649:1846)) + (INTERCONNECT SLICE_5/Q1 SLICE_65/B0 (1452:1649:1846)(1452:1649:1846)) + (INTERCONNECT SLICE_5/Q1 SLICE_66/D1 (1210:1339:1468)(1210:1339:1468)) + (INTERCONNECT SLICE_5/Q1 SLICE_70/C0 (1221:1405:1589)(1221:1405:1589)) + (INTERCONNECT SLICE_5/Q1 SLICE_71/A1 (1030:1190:1351)(1030:1190:1351)) + (INTERCONNECT SLICE_5/Q1 SLICE_72/C1 (805:952:1100)(805:952:1100)) + (INTERCONNECT SLICE_5/Q1 SLICE_74/A0 (1790:2016:2243)(1790:2016:2243)) + (INTERCONNECT SLICE_5/Q1 SLICE_81/A1 (1790:2016:2243)(1790:2016:2243)) + (INTERCONNECT SLICE_5/Q1 SLICE_82/D1 (1580:1741:1902)(1580:1741:1902)) + (INTERCONNECT SLICE_5/Q1 SLICE_85/D1 (1565:1724:1884)(1565:1724:1884)) + (INTERCONNECT SLICE_5/Q1 SLICE_97/C1 (1201:1383:1565)(1201:1383:1565)) + (INTERCONNECT SLICE_5/Q1 SLICE_98/A0 (1790:2016:2243)(1790:2016:2243)) + (INTERCONNECT SLICE_5/Q1 SLICE_99/C0 (1158:1343:1528)(1158:1343:1528)) + (INTERCONNECT SLICE_5/Q1 SLICE_104/A1 (1775:2000:2225)(1775:2000:2225)) + (INTERCONNECT SLICE_5/Q1 SLICE_104/A0 (1775:2000:2225)(1775:2000:2225)) + (INTERCONNECT SLICE_5/Q0 SLICE_5/A0 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_5/Q0 SLICE_33/C1 (826:975:1125)(826:975:1125)) + (INTERCONNECT SLICE_5/Q0 SLICE_54/D0 (1251:1382:1514)(1251:1382:1514)) + (INTERCONNECT SLICE_5/Q0 wb_dati_5_1_iv_0_0_o2\[5\]\/SLICE_59/M0 (1216:1336:1456) + (1216:1336:1456)) + (INTERCONNECT SLICE_5/Q0 wb_adr_5_i_0_1\[0\]\/SLICE_60/C0 (826:975:1125) + (826:975:1125)) + (INTERCONNECT SLICE_5/Q0 SLICE_65/D1 (1190:1317:1444)(1190:1317:1444)) + (INTERCONNECT SLICE_5/Q0 SLICE_66/B1 (1432:1627:1822)(1432:1627:1822)) + (INTERCONNECT SLICE_5/Q0 SLICE_67/C1 (826:975:1125)(826:975:1125)) + (INTERCONNECT SLICE_5/Q0 SLICE_70/A0 (1400:1592:1785)(1400:1592:1785)) + (INTERCONNECT SLICE_5/Q0 SLICE_71/C1 (826:975:1125)(826:975:1125)) + (INTERCONNECT SLICE_5/Q0 SLICE_72/D1 (1251:1382:1514)(1251:1382:1514)) + (INTERCONNECT SLICE_5/Q0 SLICE_73/C0 (1642:1861:2081)(1642:1861:2081)) + (INTERCONNECT SLICE_5/Q0 SLICE_74/C0 (1642:1861:2081)(1642:1861:2081)) + (INTERCONNECT SLICE_5/Q0 SLICE_82/C1 (1642:1861:2081)(1642:1861:2081)) + (INTERCONNECT SLICE_5/Q0 SLICE_87/B1 (1493:1692:1892)(1493:1692:1892)) + (INTERCONNECT SLICE_5/Q0 SLICE_97/B1 (1472:1669:1867)(1472:1669:1867)) + (INTERCONNECT SLICE_5/Q0 SLICE_104/C1 (1642:1861:2081)(1642:1861:2081)) (INTERCONNECT SLICE_5/F1 SLICE_5/DI1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_5/F0 SLICE_5/DI0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_6/FCO SLICE_5/FCI (0:0:0)(0:0:0)) (INTERCONNECT SLICE_6/Q1 SLICE_6/A1 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_6/Q1 SLICE_121/C0 (908:1054:1200)(908:1054:1200)) + (INTERCONNECT SLICE_6/Q1 SLICE_121/B0 (775:902:1030)(775:902:1030)) (INTERCONNECT SLICE_6/Q0 SLICE_6/A0 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_6/Q0 SLICE_98/C0 (908:1054:1200)(908:1054:1200)) + (INTERCONNECT SLICE_6/Q0 SLICE_95/D1 (792:878:965)(792:878:965)) (INTERCONNECT SLICE_6/F1 SLICE_6/DI1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_6/F0 SLICE_6/DI0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_7/FCO SLICE_6/FCI (0:0:0)(0:0:0)) (INTERCONNECT SLICE_7/Q1 SLICE_7/A1 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_7/Q1 SLICE_98/A0 (736:853:971)(736:853:971)) + (INTERCONNECT SLICE_7/Q1 SLICE_121/C0 (803:944:1086)(803:944:1086)) (INTERCONNECT SLICE_7/Q0 SLICE_7/A0 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_7/Q0 SLICE_121/B0 (1209:1375:1542)(1209:1375:1542)) + (INTERCONNECT SLICE_7/Q0 SLICE_95/D0 (860:954:1049)(860:954:1049)) (INTERCONNECT SLICE_7/F1 SLICE_7/DI1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_7/F0 SLICE_7/DI0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_8/FCO SLICE_7/FCI (0:0:0)(0:0:0)) (INTERCONNECT SLICE_8/Q1 SLICE_8/A1 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_8/Q1 SLICE_98/B1 (1209:1375:1542)(1209:1375:1542)) + (INTERCONNECT SLICE_8/Q1 SLICE_95/B0 (775:902:1030)(775:902:1030)) (INTERCONNECT SLICE_8/Q0 SLICE_8/A0 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_8/Q0 SLICE_98/A1 (743:868:993)(743:868:993)) + (INTERCONNECT SLICE_8/Q0 SLICE_121/D0 (897:988:1079)(897:988:1079)) (INTERCONNECT SLICE_8/F1 SLICE_8/DI1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_8/F0 SLICE_8/DI0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_9/FCO SLICE_8/FCI (0:0:0)(0:0:0)) (INTERCONNECT SLICE_9/Q1 SLICE_9/A1 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_9/Q1 SLICE_98/D0 (533:592:652)(533:592:652)) + (INTERCONNECT SLICE_9/Q1 SLICE_95/A0 (743:868:993)(743:868:993)) (INTERCONNECT SLICE_9/Q0 SLICE_9/A0 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_9/Q0 SLICE_121/A0 (1107:1263:1420)(1107:1263:1420)) + (INTERCONNECT SLICE_9/Q0 SLICE_95/B1 (768:888:1008)(768:888:1008)) (INTERCONNECT SLICE_9/F1 SLICE_9/DI1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_9/F0 SLICE_9/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT MAin\[1\]_I/PADDI SLICE_10/D1 (2232:2426:2620)(2232:2426:2620)) - (INTERCONNECT MAin\[1\]_I/PADDI SLICE_11/B1 (2832:3135:3438)(2832:3135:3438)) - (INTERCONNECT MAin\[1\]_I/PADDI SLICE_11/B0 (2832:3135:3438)(2832:3135:3438)) - (INTERCONNECT MAin\[1\]_I/PADDI SLICE_17/B1 (2474:2736:2998)(2474:2736:2998)) - (INTERCONNECT MAin\[1\]_I/PADDI SLICE_23/C1 (2190:2441:2692)(2190:2441:2692)) - (INTERCONNECT MAin\[1\]_I/PADDI SLICE_38/A1 (3176:3499:3822)(3176:3499:3822)) - (INTERCONNECT MAin\[1\]_I/PADDI SLICE_64/A0 (2800:3100:3401)(2800:3100:3401)) - (INTERCONNECT MAin\[1\]_I/PADDI SLICE_80/D1 (2590:2825:3060)(2590:2825:3060)) - (INTERCONNECT MAin\[1\]_I/PADDI SLICE_117/A0 (3139:3465:3792)(3139:3465:3792)) - (INTERCONNECT SLICE_84/F0 SLICE_10/C1 (1365:1551:1738)(1365:1551:1738)) - (INTERCONNECT SLICE_84/F0 SLICE_11/D1 (1354:1485:1617)(1354:1485:1617)) - (INTERCONNECT SLICE_84/F0 SLICE_11/D0 (1354:1485:1617)(1354:1485:1617)) - (INTERCONNECT SLICE_84/F0 SLICE_17/A1 (1564:1761:1958)(1564:1761:1958)) - (INTERCONNECT SLICE_84/F0 SLICE_23/A1 (1179:1342:1506)(1179:1342:1506)) - (INTERCONNECT SLICE_84/F0 SLICE_80/B0 (1596:1795:1995)(1596:1795:1995)) - (INTERCONNECT SLICE_10/Q0 SLICE_10/D0 (531:586:641)(531:586:641)) - (INTERCONNECT SLICE_10/Q0 SLICE_33/A0 (741:861:982)(741:861:982)) - (INTERCONNECT SLICE_17/F1 SLICE_10/C0 (534:645:756)(534:645:756)) - (INTERCONNECT SLICE_17/F1 SLICE_17/C0 (280:362:445)(280:362:445)) - (INTERCONNECT SLICE_10/F1 SLICE_10/B0 (508:600:693)(508:600:693)) - (INTERCONNECT SLICE_11/F1 SLICE_10/A0 (738:862:987)(738:862:987)) + (INTERCONNECT SLICE_80/F0 SLICE_10/D1 (990:1089:1188)(990:1089:1188)) + (INTERCONNECT SLICE_80/F0 SLICE_11/D1 (990:1089:1188)(990:1089:1188)) + (INTERCONNECT SLICE_80/F0 SLICE_11/D0 (990:1089:1188)(990:1089:1188)) + (INTERCONNECT SLICE_80/F0 SLICE_17/D1 (990:1089:1188)(990:1089:1188)) + (INTERCONNECT SLICE_80/F0 SLICE_23/B1 (1596:1794:1993)(1596:1794:1993)) + (INTERCONNECT SLICE_80/F0 SLICE_76/D0 (990:1089:1188)(990:1089:1188)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_10/C1 (1775:1977:2179)(1775:1977:2179)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_11/B1 (2766:3047:3328)(2766:3047:3328)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_11/B0 (2766:3047:3328)(2766:3047:3328)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_17/C1 (2535:2803:3071)(2535:2803:3071)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_23/D1 (2466:2680:2895)(2466:2680:2895)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_38/C1 (2520:2786:3053)(2520:2786:3053)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_63/A0 (2734:3012:3291)(2734:3012:3291)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_76/D1 (2524:2737:2950)(2524:2737:2950)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_114/C0 (2520:2786:3053)(2520:2786:3053)) + (INTERCONNECT SLICE_10/Q0 SLICE_10/D0 (523:578:633)(523:578:633)) + (INTERCONNECT SLICE_10/Q0 SLICE_33/A0 (743:868:993)(743:868:993)) + (INTERCONNECT SLICE_11/F1 SLICE_10/C0 (539:653:767)(539:653:767)) (INTERCONNECT SLICE_11/F1 SLICE_11/C0 (280:362:445)(280:362:445)) - (INTERCONNECT SLICE_11/F1 SLICE_33/C0 (539:653:767)(539:653:767)) + (INTERCONNECT SLICE_11/F1 SLICE_33/C0 (805:953:1102)(805:953:1102)) + (INTERCONNECT SLICE_17/F1 SLICE_10/B0 (768:889:1010)(768:889:1010)) + (INTERCONNECT SLICE_17/F1 SLICE_17/C0 (280:362:445)(280:362:445)) + (INTERCONNECT SLICE_10/F1 SLICE_10/A0 (730:848:967)(730:848:967)) (INTERCONNECT SLICE_10/F0 SLICE_10/DI0 (0:0:0)(0:0:0)) (INTERCONNECT PHI2_I/PADDI SLICE_10/CLK (3065:3302:3539)(3065:3302:3539)) (INTERCONNECT PHI2_I/PADDI SLICE_11/CLK (3065:3302:3539)(3065:3302:3539)) (INTERCONNECT PHI2_I/PADDI SLICE_17/CLK (3065:3302:3539)(3065:3302:3539)) (INTERCONNECT PHI2_I/PADDI SLICE_18/CLK (3065:3302:3539)(3065:3302:3539)) + (INTERCONNECT PHI2_I/PADDI SLICE_19/CLK (3065:3302:3539)(3065:3302:3539)) (INTERCONNECT PHI2_I/PADDI SLICE_20/CLK (3065:3302:3539)(3065:3302:3539)) (INTERCONNECT PHI2_I/PADDI SLICE_21/CLK (3065:3302:3539)(3065:3302:3539)) (INTERCONNECT PHI2_I/PADDI SLICE_22/CLK (3065:3302:3539)(3065:3302:3539)) (INTERCONNECT PHI2_I/PADDI SLICE_23/CLK (3065:3302:3539)(3065:3302:3539)) (INTERCONNECT PHI2_I/PADDI SLICE_24/CLK (3065:3302:3539)(3065:3302:3539)) (INTERCONNECT PHI2_I/PADDI SLICE_44/CLK (3065:3302:3539)(3065:3302:3539)) - (INTERCONNECT PHI2_I/PADDI SLICE_82/CLK (3065:3302:3539)(3065:3302:3539)) (INTERCONNECT PHI2_I/PADDI PHI2_MGIOL/DI (424:441:459)(424:441:459)) (INTERCONNECT PHI2_I/PADDI RA\[11\]_MGIOL/CLK (3212:3462:3712)(3212:3462:3712)) (INTERCONNECT PHI2_I/PADDI Din\[7\]_MGIOL/CLK (3212:3462:3712)(3212:3462:3712)) @@ -3771,17 +3782,17 @@ (INTERCONNECT PHI2_I/PADDI Din\[2\]_MGIOL/CLK (3212:3462:3712)(3212:3462:3712)) (INTERCONNECT PHI2_I/PADDI Din\[1\]_MGIOL/CLK (3212:3462:3712)(3212:3462:3712)) (INTERCONNECT PHI2_I/PADDI Din\[0\]_MGIOL/CLK (3212:3462:3712)(3212:3462:3712)) - (INTERCONNECT SLICE_112/F1 SLICE_11/C1 (895:1047:1199)(895:1047:1199)) - (INTERCONNECT SLICE_112/F1 SLICE_17/D1 (900:989:1079)(900:989:1079)) - (INTERCONNECT SLICE_112/F1 SLICE_64/C0 (895:1047:1199)(895:1047:1199)) - (INTERCONNECT SLICE_112/F1 SLICE_80/C1 (895:1047:1199)(895:1047:1199)) - (INTERCONNECT SLICE_64/F1 SLICE_11/A1 (741:861:982)(741:861:982)) - (INTERCONNECT SLICE_64/F1 SLICE_64/D0 (531:586:641)(531:586:641)) + (INTERCONNECT SLICE_109/F1 SLICE_11/C1 (882:1034:1187)(882:1034:1187)) + (INTERCONNECT SLICE_109/F1 SLICE_17/B1 (770:897:1024)(770:897:1024)) + (INTERCONNECT SLICE_109/F1 SLICE_63/B0 (770:897:1024)(770:897:1024)) + (INTERCONNECT SLICE_109/F1 SLICE_76/C1 (882:1034:1187)(882:1034:1187)) + (INTERCONNECT SLICE_63/F1 SLICE_11/A1 (741:861:982)(741:861:982)) + (INTERCONNECT SLICE_63/F1 SLICE_63/D0 (531:586:641)(531:586:641)) (INTERCONNECT SLICE_11/Q0 SLICE_11/A0 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_11/Q0 SLICE_80/A0 (733:853:974)(733:853:974)) + (INTERCONNECT SLICE_11/Q0 SLICE_76/A0 (733:853:974)(733:853:974)) (INTERCONNECT SLICE_11/F0 SLICE_11/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT nCCAS_I/PADDI SLICE_12/D0 (3559:3894:4229)(3559:3894:4229)) - (INTERCONNECT nCCAS_I/PADDI SLICE_25/A1 (3405:3774:4143)(3405:3774:4143)) + (INTERCONNECT nCCAS_I/PADDI SLICE_12/A0 (3832:4242:4652)(3832:4242:4652)) + (INTERCONNECT nCCAS_I/PADDI SLICE_25/A1 (3135:3475:3815)(3135:3475:3815)) (INTERCONNECT nCCAS_I/PADDI RD\[0\]_MGIOL/CLK (2547:2778:3010)(2547:2778:3010)) (INTERCONNECT nCCAS_I/PADDI RD\[7\]_MGIOL/CLK (2547:2778:3010)(2547:2778:3010)) (INTERCONNECT nCCAS_I/PADDI RD\[6\]_MGIOL/CLK (2547:2778:3010)(2547:2778:3010)) @@ -3791,165 +3802,176 @@ (INTERCONNECT nCCAS_I/PADDI RD\[2\]_MGIOL/CLK (2547:2778:3010)(2547:2778:3010)) (INTERCONNECT nCCAS_I/PADDI RD\[1\]_MGIOL/CLK (2547:2778:3010)(2547:2778:3010)) (INTERCONNECT SLICE_12/F0 SLICE_12/DI0 (3:6:9)(3:6:9)) - (INTERCONNECT SLICE_12/F0 SLICE_80/M0 (499:545:592)(499:545:592)) - (INTERCONNECT SLICE_12/F0 SLICE_80/M1 (499:545:592)(499:545:592)) + (INTERCONNECT SLICE_12/F0 SLICE_76/M0 (504:553:603)(504:553:603)) + (INTERCONNECT SLICE_12/F0 SLICE_76/M1 (504:553:603)(504:553:603)) (INTERCONNECT SLICE_12/Q0 SLICE_12/M1 (485:526:568)(485:526:568)) - (INTERCONNECT SLICE_12/Q1 SLICE_26/B1 (1050:1206:1362)(1050:1206:1362)) - (INTERCONNECT SLICE_12/Q1 SLICE_61/B0 (1050:1206:1362)(1050:1206:1362)) - (INTERCONNECT SLICE_12/Q1 SLICE_107/M0 (1084:1194:1304)(1084:1194:1304)) - (INTERCONNECT SLICE_12/Q1 SLICE_108/B1 (1050:1206:1362)(1050:1206:1362)) - (INTERCONNECT SLICE_12/Q1 SLICE_108/B0 (1050:1206:1362)(1050:1206:1362)) - (INTERCONNECT SLICE_16/Q0 SLICE_16/C1 (549:665:781)(549:665:781)) - (INTERCONNECT SLICE_16/Q0 SLICE_16/C0 (549:665:781)(549:665:781)) - (INTERCONNECT SLICE_16/Q0 SLICE_26/A1 (778:910:1042)(778:910:1042)) - (INTERCONNECT SLICE_16/Q0 SLICE_43/C1 (538:652:766)(538:652:766)) - (INTERCONNECT SLICE_16/Q0 SLICE_43/B0 (769:896:1023)(769:896:1023)) - (INTERCONNECT SLICE_16/Q0 SLICE_60/C1 (949:1102:1256)(949:1102:1256)) - (INTERCONNECT SLICE_16/Q0 SLICE_60/D0 (1265:1398:1532)(1265:1398:1532)) - (INTERCONNECT SLICE_16/Q0 SLICE_61/A1 (1496:1699:1902)(1496:1699:1902)) - (INTERCONNECT SLICE_16/Q0 SLICE_61/C0 (949:1102:1256)(949:1102:1256)) - (INTERCONNECT SLICE_16/Q0 SLICE_72/C0 (579:700:822)(579:700:822)) - (INTERCONNECT SLICE_16/Q0 SLICE_79/D0 (568:634:701)(568:634:701)) - (INTERCONNECT SLICE_16/Q0 SLICE_83/D1 (568:634:701)(568:634:701)) - (INTERCONNECT SLICE_16/Q0 SLICE_88/D1 (895:996:1098)(895:996:1098)) - (INTERCONNECT SLICE_16/Q0 SLICE_108/A1 (1496:1699:1902)(1496:1699:1902)) - (INTERCONNECT SLICE_16/Q0 SLICE_108/A0 (1496:1699:1902)(1496:1699:1902)) - (INTERCONNECT SLICE_43/Q0 SLICE_16/A1 (758:886:1015)(758:886:1015)) - (INTERCONNECT SLICE_43/Q0 SLICE_16/A0 (758:886:1015)(758:886:1015)) - (INTERCONNECT SLICE_43/Q0 SLICE_35/A1 (1027:1185:1343)(1027:1185:1343)) - (INTERCONNECT SLICE_43/Q0 SLICE_43/A1 (758:886:1015)(758:886:1015)) - (INTERCONNECT SLICE_43/Q0 SLICE_43/A0 (483:579:675)(483:579:675)) - (INTERCONNECT SLICE_43/Q0 SLICE_60/A0 (1354:1547:1740)(1354:1547:1740)) - (INTERCONNECT SLICE_43/Q0 SLICE_61/D1 (817:909:1002)(817:909:1002)) - (INTERCONNECT SLICE_43/Q0 SLICE_72/B0 (1423:1615:1807)(1423:1615:1807)) - (INTERCONNECT SLICE_43/Q0 SLICE_79/B0 (790:922:1055)(790:922:1055)) - (INTERCONNECT SLICE_43/Q0 SLICE_81/D1 (548:612:677)(548:612:677)) - (INTERCONNECT SLICE_43/Q0 SLICE_88/C1 (886:1040:1195)(886:1040:1195)) - (INTERCONNECT SLICE_43/Q0 SLICE_108/C1 (828:975:1123)(828:975:1123)) + (INTERCONNECT SLICE_12/Q1 SLICE_69/C0 (994:1149:1304)(994:1149:1304)) + (INTERCONNECT SLICE_12/Q1 SLICE_77/M0 (757:832:907)(757:832:907)) + (INTERCONNECT SLICE_12/Q1 SLICE_103/D1 (1310:1445:1580)(1310:1445:1580)) + (INTERCONNECT SLICE_12/Q1 SLICE_103/C0 (994:1149:1304)(994:1149:1304)) + (INTERCONNECT SLICE_12/Q1 SLICE_117/C0 (994:1149:1304)(994:1149:1304)) + (INTERCONNECT SLICE_28/Q0 SLICE_16/D1 (537:600:664)(537:600:664)) + (INTERCONNECT SLICE_28/Q0 SLICE_28/B0 (769:896:1023)(769:896:1023)) + (INTERCONNECT SLICE_28/Q0 SLICE_79/B0 (769:896:1023)(769:896:1023)) + (INTERCONNECT SLICE_28/Q0 SLICE_83/A1 (740:861:983)(740:861:983)) + (INTERCONNECT SLICE_32/Q1 SLICE_16/C1 (541:652:763)(541:652:763)) + (INTERCONNECT SLICE_32/Q1 SLICE_16/LSR (894:997:1101)(894:997:1101)) + (INTERCONNECT SLICE_32/Q1 SLICE_33/M0 (936:1027:1118)(936:1027:1118)) + (INTERCONNECT SLICE_32/Q1 SLICE_34/B1 (810:945:1080)(810:945:1080)) + (INTERCONNECT SLICE_32/Q1 SLICE_35/B1 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SLICE_46/B0 (1219:1385:1551)(1219:1385:1551)) - (INTERCONNECT SLICE_99/F0 SLICE_17/C1 (536:647:758)(536:647:758)) - (INTERCONNECT SLICE_99/F0 SLICE_80/B1 (1033:1191:1350)(1033:1191:1350)) - (INTERCONNECT SLICE_33/F0 SLICE_17/D0 (266:290:315)(266:290:315)) - (INTERCONNECT SLICE_80/F0 SLICE_17/B0 (772:897:1023)(772:897:1023)) - (INTERCONNECT SLICE_17/Q0 SLICE_17/A0 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_17/Q0 SLICE_23/D1 (792:878:965)(792:878:965)) + (INTERCONNECT SLICE_16/F1 SLICE_36/C0 (547:660:773)(547:660:773)) + (INTERCONNECT SLICE_16/F1 SLICE_37/C1 (911:1055:1200)(911:1055:1200)) + (INTERCONNECT SLICE_92/F0 SLICE_17/A1 (1180:1342:1505)(1180:1342:1505)) + (INTERCONNECT SLICE_92/F0 SLICE_76/A1 (1180:1342:1505)(1180:1342:1505)) + (INTERCONNECT SLICE_76/F0 SLICE_17/D0 (266:290:315)(266:290:315)) + (INTERCONNECT SLICE_17/Q0 SLICE_17/B0 (765:888:1011)(765:888:1011)) + (INTERCONNECT SLICE_17/Q0 SLICE_23/A1 (736:853:971)(736:853:971)) + (INTERCONNECT SLICE_33/F0 SLICE_17/A0 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RD\[1\]_MGIOL/OPOS (2921:3151:3381)(2921:3151:3381)) (INTERCONNECT Din\[1\]_I/PADDI Din\[1\]_MGIOL/DI (544:554:565)(544:554:565)) - (INTERCONNECT SLICE_119/F1 SLICE_18/C1 (536:647:758)(536:647:758)) - (INTERCONNECT SLICE_119/F1 SLICE_24/A1 (735:856:978)(735:856:978)) - (INTERCONNECT SLICE_22/F1 SLICE_18/B1 (769:899:1029)(769:899:1029)) - (INTERCONNECT SLICE_22/F1 SLICE_20/B0 (775:914:1053)(775:914:1053)) - (INTERCONNECT SLICE_22/F1 SLICE_21/D1 (533:604:675)(533:604:675)) - (INTERCONNECT SLICE_22/F1 SLICE_22/C0 (284:372:461)(284:372:461)) - (INTERCONNECT SLICE_22/F1 SLICE_23/B0 (775:914:1053)(775:914:1053)) - (INTERCONNECT SLICE_22/F1 SLICE_24/D1 (527:589:651)(527:589:651)) + (INTERCONNECT SLICE_22/F1 SLICE_18/C1 (544:670:796)(544:670:796)) + (INTERCONNECT SLICE_22/F1 SLICE_20/C0 (538:655:772)(538:655:772)) + (INTERCONNECT SLICE_22/F1 SLICE_21/A1 (743:879:1016)(743:879:1016)) + (INTERCONNECT SLICE_22/F1 SLICE_22/D0 (527:589:651)(527:589:651)) + (INTERCONNECT SLICE_22/F1 SLICE_23/C0 (544:670:796)(544:670:796)) + (INTERCONNECT SLICE_22/F1 SLICE_24/C1 (875:1031:1188)(875:1031:1188)) + (INTERCONNECT SLICE_119/F1 SLICE_18/B1 (767:891:1015)(767:891:1015)) + (INTERCONNECT SLICE_119/F1 SLICE_24/D1 (525:581:637)(525:581:637)) (INTERCONNECT SLICE_18/Q0 SLICE_18/A1 (733:853:974)(733:853:974)) - (INTERCONNECT SLICE_18/Q0 SLICE_30/A1 (1433:1620:1808)(1433:1620:1808)) - (INTERCONNECT SLICE_30/Q0 SLICE_18/C0 (540:659:778)(540:659:778)) - (INTERCONNECT SLICE_30/Q0 SLICE_30/D0 (523:578:633)(523:578:633)) - (INTERCONNECT SLICE_30/Q0 SLICE_32/B1 (1468:1670:1872)(1468:1670:1872)) - (INTERCONNECT SLICE_30/Q0 SLICE_44/C0 (806:959:1113)(806:959:1113)) - (INTERCONNECT SLICE_18/F1 SLICE_18/B0 (508:600:693)(508:600:693)) - (INTERCONNECT SLICE_82/F1 SLICE_18/A0 (737:864:992)(737:864:992)) - (INTERCONNECT SLICE_82/F1 SLICE_20/C0 (543:663:783)(543:663:783)) - (INTERCONNECT SLICE_82/F1 SLICE_21/A0 (742:872:1003)(742:872:1003)) - (INTERCONNECT SLICE_82/F1 SLICE_24/B0 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SLICE_26/Q0 SLICE_26/A1 (739:865:992)(739:865:992)) + (INTERCONNECT SLICE_26/Q0 SLICE_26/A0 (485:583:681)(485:583:681)) + (INTERCONNECT SLICE_26/Q0 SLICE_27/B1 (778:922:1066)(778:922:1066)) + (INTERCONNECT SLICE_26/Q0 SLICE_27/B0 (778:922:1066)(778:922:1066)) + (INTERCONNECT SLICE_26/Q0 SLICE_28/B1 (778:922:1066)(778:922:1066)) + (INTERCONNECT SLICE_26/Q0 SLICE_28/C0 (1250:1451:1653)(1250:1451:1653)) + (INTERCONNECT SLICE_26/Q0 SLICE_36/B1 (1808:2057:2307)(1808:2057:2307)) + (INTERCONNECT SLICE_26/Q0 SLICE_83/A0 (739:865:992)(739:865:992)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_19/M0 (2651:2880:3110)(2651:2880:3110)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_21/A0 (3673:4040:4407)(3673:4040:4407)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_24/B1 (4032:4436:4841)(4032:4436:4841)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_109/C1 (3844:4232:4621)(3844:4232:4621)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_109/C0 (3844:4232:4621)(3844:4232:4621)) + (INTERCONNECT Din\[0\]_I/PADDI RD\[0\]_MGIOL/OPOS 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(767:894:1021)(767:894:1021)) - (INTERCONNECT SLICE_100/F1 SLICE_82/B1 (772:902:1032)(772:902:1032)) - (INTERCONNECT SLICE_100/F1 SLICE_100/C0 (282:367:453)(282:367:453)) - (INTERCONNECT Din\[3\]_I/PADDI SLICE_22/C1 (2096:2309:2522)(2096:2309:2522)) - (INTERCONNECT Din\[3\]_I/PADDI SLICE_64/A1 (2659:2914:3169)(2659:2914:3169)) - (INTERCONNECT Din\[3\]_I/PADDI SLICE_82/A1 (2622:2880:3139)(2622:2880:3139)) - (INTERCONNECT Din\[3\]_I/PADDI SLICE_99/C1 (2460:2704:2949)(2460:2704:2949)) - (INTERCONNECT Din\[3\]_I/PADDI SLICE_100/A0 (2279:2501:2723)(2279:2501:2723)) - (INTERCONNECT Din\[3\]_I/PADDI RD\[3\]_MGIOL/OPOS (2180:2347:2514)(2180:2347:2514)) - (INTERCONNECT Din\[3\]_I/PADDI Din\[3\]_MGIOL/DI (544:554:565)(544:554:565)) - (INTERCONNECT Din\[4\]_I/PADDI SLICE_22/B1 (2316:2541:2766)(2316:2541:2766)) - (INTERCONNECT Din\[4\]_I/PADDI SLICE_44/C1 (2807:3091:3376)(2807:3091:3376)) - (INTERCONNECT Din\[4\]_I/PADDI SLICE_82/C1 (2085:2297:2509)(2085:2297:2509)) - (INTERCONNECT Din\[4\]_I/PADDI SLICE_112/C1 (2807:3091:3376)(2807:3091:3376)) - (INTERCONNECT Din\[4\]_I/PADDI SLICE_112/C0 (2807:3091:3376)(2807:3091:3376)) - (INTERCONNECT Din\[4\]_I/PADDI SLICE_119/C1 (2807:3091:3376)(2807:3091:3376)) - (INTERCONNECT Din\[4\]_I/PADDI RD\[4\]_MGIOL/OPOS (2589:2786:2983)(2589:2786:2983)) - (INTERCONNECT Din\[4\]_I/PADDI Din\[4\]_MGIOL/DI (544:554:565)(544:554:565)) - (INTERCONNECT Din\[5\]_I/PADDI SLICE_22/A1 (2370:2589:2808)(2370:2589:2808)) - (INTERCONNECT Din\[5\]_I/PADDI SLICE_44/D1 (2872:3096:3320)(2872:3096:3320)) - (INTERCONNECT Din\[5\]_I/PADDI SLICE_82/D1 (2487:2675:2864)(2487:2675:2864)) - (INTERCONNECT Din\[5\]_I/PADDI SLICE_99/B1 (2391:2611:2832)(2391:2611:2832)) - (INTERCONNECT Din\[5\]_I/PADDI SLICE_119/D1 (2872:3096:3320)(2872:3096:3320)) - (INTERCONNECT Din\[5\]_I/PADDI SLICE_119/D0 (2872:3096:3320)(2872:3096:3320)) - (INTERCONNECT Din\[5\]_I/PADDI RD\[5\]_MGIOL/OPOS (2630:2825:3020)(2630:2825:3020)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_22/D1 (2166:2319:2472)(2166:2319:2472)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_44/C1 (2515:2760:3005)(2515:2760:3005)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_77/A1 (2714:2969:3225)(2714:2969:3225)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_92/A1 (2376:2594:2813)(2376:2594:2813)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_119/B1 (2408:2629:2850)(2408:2629:2850)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_119/B0 (2408:2629:2850)(2408:2629:2850)) + (INTERCONNECT Din\[5\]_I/PADDI RD\[5\]_MGIOL/OPOS (2589:2786:2983)(2589:2786:2983)) (INTERCONNECT Din\[5\]_I/PADDI Din\[5\]_MGIOL/DI (544:554:565)(544:554:565)) + (INTERCONNECT SLICE_96/F1 SLICE_22/C1 (541:655:769)(541:655:769)) + (INTERCONNECT SLICE_96/F1 SLICE_44/D1 (273:306:340)(273:306:340)) + (INTERCONNECT SLICE_96/F1 SLICE_77/C1 (284:372:461)(284:372:461)) + (INTERCONNECT SLICE_96/F1 SLICE_96/B0 (769:899:1029)(769:899:1029)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_22/B1 (2322:2546:2771)(2322:2546:2771)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_63/D1 (2771:2994:3217)(2771:2994:3217)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_77/D1 (2397:2587:2778)(2397:2587:2778)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_92/C1 (2091:2302:2514)(2091:2302:2514)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_96/D0 (2080:2236:2393)(2080:2236:2393)) + (INTERCONNECT Din\[3\]_I/PADDI RD\[3\]_MGIOL/OPOS (2915:3144:3374)(2915:3144:3374)) + (INTERCONNECT Din\[3\]_I/PADDI Din\[3\]_MGIOL/DI (544:554:565)(544:554:565)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_22/A1 (2279:2500:2721)(2279:2500:2721)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_44/B1 (3403:3731:4059)(3403:3731:4059)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_77/B1 (3403:3731:4059)(3403:3731:4059)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_109/B1 (3403:3731:4059)(3403:3731:4059)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_109/B0 (3403:3731:4059)(3403:3731:4059)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_119/C1 (2407:2652:2898)(2407:2652:2898)) + (INTERCONNECT Din\[4\]_I/PADDI RD\[4\]_MGIOL/OPOS (3284:3545:3807)(3284:3545:3807)) + (INTERCONNECT Din\[4\]_I/PADDI Din\[4\]_MGIOL/DI (544:554:565)(544:554:565)) (INTERCONNECT SLICE_22/F0 SLICE_22/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_22/Q0 SLICE_45/D1 (536:594:652)(536:594:652)) - (INTERCONNECT SLICE_22/Q0 SLICE_107/C1 (885:1035:1185)(885:1035:1185)) - (INTERCONNECT SLICE_22/Q0 SLICE_107/C0 (885:1035:1185)(885:1035:1185)) - (INTERCONNECT MAin\[0\]_I/PADDI SLICE_23/B1 (2119:2342:2566)(2119:2342:2566)) - (INTERCONNECT MAin\[0\]_I/PADDI SLICE_38/A0 (2872:3169:3466)(2872:3169:3466)) - (INTERCONNECT MAin\[0\]_I/PADDI SLICE_64/B1 (3274:3605:3937)(3274:3605:3937)) - (INTERCONNECT MAin\[0\]_I/PADDI SLICE_64/B0 (3274:3605:3937)(3274:3605:3937)) - (INTERCONNECT MAin\[0\]_I/PADDI SLICE_99/D0 (2247:2434:2622)(2247:2434:2622)) - (INTERCONNECT MAin\[0\]_I/PADDI SLICE_116/B0 (2853:3140:3427)(2853:3140:3427)) + (INTERCONNECT SLICE_22/Q0 SLICE_45/D1 (1226:1346:1467)(1226:1346:1467)) + (INTERCONNECT SLICE_22/Q0 SLICE_57/A1 (1774:1997:2220)(1774:1997:2220)) + (INTERCONNECT SLICE_22/Q0 SLICE_110/A0 (1774:1997:2220)(1774:1997:2220)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_23/C1 (1898:2109:2321)(1898:2109:2321)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_38/B0 (2499:2755:3012)(2499:2755:3012)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_63/C1 (1534:1714:1894)(1534:1714:1894)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_63/C0 (1534:1714:1894)(1534:1714:1894)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_92/A0 (2097:2319:2541)(2097:2319:2541)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_113/A0 (2103:2325:2548)(2103:2325:2548)) (INTERCONNECT SLICE_23/F0 SLICE_23/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_23/Q0 SLICE_103/D0 (520:573:626)(520:573:626)) - (INTERCONNECT SLICE_24/Q0 SLICE_24/B1 (765:888:1011)(765:888:1011)) - (INTERCONNECT SLICE_24/Q0 SLICE_122/A1 (736:853:971)(736:853:971)) - (INTERCONNECT SLICE_45/Q0 SLICE_24/D0 (528:586:644)(528:586:644)) + (INTERCONNECT SLICE_23/Q0 SLICE_100/D0 (523:573:623)(523:573:623)) + (INTERCONNECT SLICE_24/Q0 SLICE_24/A1 (733:853:974)(733:853:974)) + (INTERCONNECT SLICE_24/Q0 SLICE_111/A1 (1623:1813:2004)(1623:1813:2004)) + (INTERCONNECT SLICE_45/Q0 SLICE_24/D0 (539:599:659)(539:599:659)) (INTERCONNECT SLICE_45/Q0 SLICE_45/A0 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_45/Q0 SLICE_120/A0 (1368:1557:1747)(1368:1557:1747)) + (INTERCONNECT SLICE_45/Q0 SLICE_120/D0 (1267:1390:1513)(1267:1390:1513)) (INTERCONNECT SLICE_24/F1 SLICE_24/C0 (277:356:436)(277:356:436)) (INTERCONNECT SLICE_24/F0 SLICE_24/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT nFWE_I/PADDI SLICE_25/B1 (2792:3087:3382)(2792:3087:3382)) - (INTERCONNECT nFWE_I/PADDI SLICE_25/A0 (2433:2690:2948)(2433:2690:2948)) - (INTERCONNECT nFWE_I/PADDI SLICE_114/C0 (1864:2079:2294)(1864:2079:2294)) + (INTERCONNECT nFWE_I/PADDI SLICE_25/D1 (1959:2110:2262)(1959:2110:2262)) + (INTERCONNECT nFWE_I/PADDI SLICE_25/D0 (1959:2110:2262)(1959:2110:2262)) + (INTERCONNECT nFWE_I/PADDI SLICE_90/A1 (2241:2472:2704)(2241:2472:2704)) (INTERCONNECT SLICE_25/F0 SLICE_25/DI0 (0:0:0)(0:0:0)) (INTERCONNECT nCRAS_I/PADDI SLICE_25/CLK (2594:2840:3086)(2594:2840:3086)) - (INTERCONNECT nCRAS_I/PADDI SLICE_32/C1 (3130:3487:3844)(3130:3487:3844)) - (INTERCONNECT nCRAS_I/PADDI SLICE_32/C0 (3130:3487:3844)(3130:3487:3844)) + (INTERCONNECT nCRAS_I/PADDI SLICE_32/B0 (3359:3723:4087)(3359:3723:4087)) (INTERCONNECT nCRAS_I/PADDI SLICE_38/CLK (2594:2840:3086)(2594:2840:3086)) (INTERCONNECT nCRAS_I/PADDI SLICE_38/CLK (2594:2840:3086)(2594:2840:3086)) (INTERCONNECT nCRAS_I/PADDI SLICE_39/CLK (2594:2840:3086)(2594:2840:3086)) @@ -3960,612 +3982,608 @@ (INTERCONNECT nCRAS_I/PADDI SLICE_41/CLK (2594:2840:3086)(2594:2840:3086)) (INTERCONNECT nCRAS_I/PADDI SLICE_42/CLK (2594:2840:3086)(2594:2840:3086)) (INTERCONNECT nCRAS_I/PADDI SLICE_42/CLK (2594:2840:3086)(2594:2840:3086)) - (INTERCONNECT nCRAS_I/PADDI SLICE_80/CLK (2594:2840:3086)(2594:2840:3086)) - (INTERCONNECT nCRAS_I/PADDI SLICE_80/CLK (2594:2840:3086)(2594:2840:3086)) + (INTERCONNECT nCRAS_I/PADDI SLICE_76/CLK (2594:2840:3086)(2594:2840:3086)) + (INTERCONNECT nCRAS_I/PADDI SLICE_76/CLK (2594:2840:3086)(2594:2840:3086)) + (INTERCONNECT nCRAS_I/PADDI SLICE_106/B0 (3625:4023:4422)(3625:4023:4422)) (INTERCONNECT nCRAS_I/PADDI RBA\[1\]_MGIOL/CLK (2741:3000:3259)(2741:3000:3259)) (INTERCONNECT nCRAS_I/PADDI RBA\[0\]_MGIOL/CLK (2741:3000:3259)(2741:3000:3259)) - (INTERCONNECT SLICE_25/Q0 SLICE_46/A1 (1006:1162:1318)(1006:1162:1318)) - (INTERCONNECT SLICE_25/Q0 SLICE_83/B1 (779:910:1042)(779:910:1042)) - (INTERCONNECT SLICE_25/Q0 SLICE_94/C0 (541:652:763)(541:652:763)) - (INTERCONNECT SLICE_25/Q0 SLICE_108/D1 (1246:1374:1502)(1246:1374:1502)) - (INTERCONNECT SLICE_25/Q0 SLICE_108/D0 (1246:1374:1502)(1246:1374:1502)) - (INTERCONNECT SLICE_25/F1 RD\[0\]_I/PADDT (1132:1253:1375)(1132:1253:1375)) - (INTERCONNECT SLICE_25/F1 RD\[7\]_I/PADDT (688:769:851)(688:769:851)) - (INTERCONNECT SLICE_25/F1 RD\[6\]_I/PADDT (688:769:851)(688:769:851)) - (INTERCONNECT SLICE_25/F1 RD\[5\]_I/PADDT (947:1055:1164)(947:1055:1164)) - (INTERCONNECT SLICE_25/F1 RD\[4\]_I/PADDT (947:1055:1164)(947:1055:1164)) - (INTERCONNECT SLICE_25/F1 RD\[3\]_I/PADDT (1132:1253:1375)(1132:1253:1375)) - (INTERCONNECT SLICE_25/F1 RD\[2\]_I/PADDT (1132:1253:1375)(1132:1253:1375)) - (INTERCONNECT SLICE_25/F1 RD\[1\]_I/PADDT (1132:1253:1375)(1132:1253:1375)) - (INTERCONNECT SLICE_88/F1 SLICE_26/B0 (513:611:710)(513:611:710)) - (INTERCONNECT SLICE_88/F1 SLICE_88/A0 (735:859:984)(735:859:984)) - (INTERCONNECT SLICE_88/F1 SLICE_90/C1 (546:664:783)(546:664:783)) - (INTERCONNECT SLICE_26/Q0 SLICE_26/A0 (481:575:669)(481:575:669)) - (INTERCONNECT SLICE_26/Q0 SLICE_27/C1 (900:1056:1212)(900:1056:1212)) - (INTERCONNECT SLICE_26/Q0 SLICE_27/C0 (900:1056:1212)(900:1056:1212)) - (INTERCONNECT SLICE_26/Q0 SLICE_28/B1 (1131:1300:1469)(1131:1300:1469)) - (INTERCONNECT SLICE_26/Q0 SLICE_28/B0 (1131:1300:1469)(1131:1300:1469)) - (INTERCONNECT SLICE_26/Q0 SLICE_36/C1 (539:648:757)(539:648:757)) - (INTERCONNECT SLICE_26/Q0 SLICE_78/C1 (900:1056:1212)(900:1056:1212)) - (INTERCONNECT SLICE_26/Q0 SLICE_90/B1 (1131:1300:1469)(1131:1300:1469)) + (INTERCONNECT SLICE_25/Q0 SLICE_46/B1 (772:910:1048)(772:910:1048)) + (INTERCONNECT SLICE_25/Q0 SLICE_69/B1 (772:910:1048)(772:910:1048)) + (INTERCONNECT SLICE_25/Q0 SLICE_78/A1 (1006:1176:1346)(1006:1176:1346)) + (INTERCONNECT SLICE_25/Q0 SLICE_103/A1 (736:853:971)(736:853:971)) + (INTERCONNECT SLICE_25/Q0 SLICE_103/D0 (530:600:670)(530:600:670)) + (INTERCONNECT SLICE_25/F1 RD\[0\]_I/PADDT (1073:1182:1292)(1073:1182:1292)) + (INTERCONNECT SLICE_25/F1 RD\[7\]_I/PADDT (1031:1144:1258)(1031:1144:1258)) + (INTERCONNECT SLICE_25/F1 RD\[6\]_I/PADDT (1031:1144:1258)(1031:1144:1258)) + (INTERCONNECT SLICE_25/F1 RD\[5\]_I/PADDT (693:769:846)(693:769:846)) + (INTERCONNECT SLICE_25/F1 RD\[4\]_I/PADDT (693:769:846)(693:769:846)) + (INTERCONNECT SLICE_25/F1 RD\[3\]_I/PADDT (1073:1182:1292)(1073:1182:1292)) + (INTERCONNECT SLICE_25/F1 RD\[2\]_I/PADDT (1073:1182:1292)(1073:1182:1292)) + (INTERCONNECT SLICE_25/F1 RD\[1\]_I/PADDT (1073:1182:1292)(1073:1182:1292)) + (INTERCONNECT SLICE_83/F1 SLICE_26/D1 (271:301:332)(271:301:332)) + (INTERCONNECT SLICE_83/F1 SLICE_62/A0 (481:577:673)(481:577:673)) + (INTERCONNECT SLICE_83/F1 SLICE_83/C0 (282:367:453)(282:367:453)) + (INTERCONNECT SLICE_62/F1 SLICE_26/C1 (549:668:787)(549:668:787)) + (INTERCONNECT SLICE_62/F1 SLICE_26/C0 (549:668:787)(549:668:787)) + (INTERCONNECT SLICE_62/F1 SLICE_62/C0 (284:372:461)(284:372:461)) + (INTERCONNECT SLICE_62/F1 SLICE_79/A1 (742:872:1003)(742:872:1003)) + (INTERCONNECT SLICE_62/F1 SLICE_83/B0 (515:616:718)(515:616:718)) + (INTERCONNECT SLICE_62/F1 SLICE_122/D0 (798:897:997)(798:897:997)) + (INTERCONNECT SLICE_43/F1 SLICE_26/B1 (778:904:1030)(778:904:1030)) + (INTERCONNECT SLICE_43/F1 SLICE_83/D0 (863:956:1049)(863:956:1049)) + (INTERCONNECT SLICE_36/Q0 SLICE_26/B0 (785:917:1049)(785:917:1049)) + (INTERCONNECT SLICE_36/Q0 SLICE_34/A1 (1851:2083:2316)(1851:2083:2316)) + (INTERCONNECT SLICE_36/Q0 SLICE_34/D0 (1303:1433:1563)(1303:1433:1563)) + (INTERCONNECT SLICE_36/Q0 SLICE_36/A0 (483:579:675)(483:579:675)) + (INTERCONNECT SLICE_36/Q0 SLICE_37/A1 (1513:1708:1904)(1513:1708:1904)) + (INTERCONNECT SLICE_36/Q0 SLICE_43/C1 (1652:1874:2096)(1652:1874:2096)) + (INTERCONNECT SLICE_36/Q0 SLICE_46/C0 (934:1086:1238)(934:1086:1238)) + (INTERCONNECT SLICE_36/Q0 SLICE_62/B0 (774:904:1034)(774:904:1034)) + (INTERCONNECT SLICE_36/Q0 SLICE_68/D0 (1136:1269:1403)(1136:1269:1403)) + (INTERCONNECT SLICE_36/Q0 SLICE_75/A1 (1346:1545:1744)(1346:1545:1744)) + (INTERCONNECT SLICE_36/Q0 SLICE_79/C1 (538:652:766)(538:652:766)) + (INTERCONNECT SLICE_36/Q0 SLICE_106/C1 (934:1086:1238)(934:1086:1238)) + (INTERCONNECT SLICE_36/Q0 SLICE_106/C0 (934:1086:1238)(934:1086:1238)) + (INTERCONNECT SLICE_36/Q0 SLICE_122/C0 (1678:1894:2111)(1678:1894:2111)) (INTERCONNECT SLICE_26/F0 SLICE_26/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_26/F1 SLICE_94/B0 (1031:1183:1336)(1031:1183:1336)) - (INTERCONNECT SLICE_27/Q0 SLICE_27/B1 (788:917:1046)(788:917:1046)) + (INTERCONNECT SLICE_26/F1 nRRAS_MGIOL/OPOS (1337:1468:1599)(1337:1468:1599)) + (INTERCONNECT SLICE_27/Q0 SLICE_27/D1 (566:631:696)(566:631:696)) (INTERCONNECT SLICE_27/Q0 SLICE_27/A0 (481:575:669)(481:575:669)) - (INTERCONNECT SLICE_27/Q0 SLICE_28/C0 (557:673:789)(557:673:789)) - (INTERCONNECT SLICE_27/Q0 SLICE_36/D1 (797:897:998)(797:897:998)) - (INTERCONNECT SLICE_27/Q0 SLICE_74/A1 (741:872:1004)(741:872:1004)) - (INTERCONNECT SLICE_27/Q0 SLICE_88/C0 (542:663:784)(542:663:784)) - (INTERCONNECT SLICE_27/Q0 SLICE_90/D1 (546:607:668)(546:607:668)) + (INTERCONNECT SLICE_27/Q0 SLICE_28/D1 (566:631:696)(566:631:696)) + (INTERCONNECT SLICE_27/Q0 SLICE_28/D0 (566:631:696)(566:631:696)) + (INTERCONNECT SLICE_27/Q0 SLICE_36/D1 (566:631:696)(566:631:696)) + (INTERCONNECT SLICE_27/Q0 SLICE_79/D0 (566:631:696)(566:631:696)) + (INTERCONNECT SLICE_27/Q0 SLICE_83/B1 (1104:1268:1433)(1104:1268:1433)) (INTERCONNECT SLICE_27/Q1 SLICE_27/A1 (481:575:669)(481:575:669)) - (INTERCONNECT SLICE_27/Q1 SLICE_28/D0 (536:595:654)(536:595:654)) - (INTERCONNECT SLICE_27/Q1 SLICE_36/B1 (1039:1207:1376)(1039:1207:1376)) - (INTERCONNECT SLICE_27/Q1 SLICE_74/D1 (531:597:663)(531:597:663)) - (INTERCONNECT SLICE_27/Q1 SLICE_88/B0 (773:907:1041)(773:907:1041)) - (INTERCONNECT SLICE_27/Q1 SLICE_90/A1 (746:870:995)(746:870:995)) + (INTERCONNECT SLICE_27/Q1 SLICE_28/A1 (766:894:1023)(766:894:1023)) + (INTERCONNECT SLICE_27/Q1 SLICE_28/A0 (766:894:1023)(766:894:1023)) + (INTERCONNECT SLICE_27/Q1 SLICE_36/A1 (766:894:1023)(766:894:1023)) + (INTERCONNECT SLICE_27/Q1 SLICE_79/A0 (766:894:1023)(766:894:1023)) + (INTERCONNECT SLICE_27/Q1 SLICE_83/D1 (535:596:658)(535:596:658)) (INTERCONNECT SLICE_27/F1 SLICE_27/DI1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_27/F0 SLICE_27/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_79/F0 SLICE_27/CE (887:985:1084)(887:985:1084)) - (INTERCONNECT SLICE_79/F0 SLICE_27/CE (887:985:1084)(887:985:1084)) - (INTERCONNECT SLICE_79/F0 SLICE_28/CE (887:985:1084)(887:985:1084)) - (INTERCONNECT SLICE_28/Q0 SLICE_28/A0 (481:575:669)(481:575:669)) - (INTERCONNECT SLICE_28/Q0 SLICE_43/B1 (1036:1192:1349)(1036:1192:1349)) - (INTERCONNECT SLICE_28/Q0 SLICE_74/C1 (879:1031:1183)(879:1031:1183)) - (INTERCONNECT SLICE_28/Q0 SLICE_88/D0 (541:603:665)(541:603:665)) + (INTERCONNECT SLICE_122/F0 SLICE_27/CE (887:985:1084)(887:985:1084)) + (INTERCONNECT SLICE_122/F0 SLICE_27/CE (887:985:1084)(887:985:1084)) + (INTERCONNECT SLICE_122/F0 SLICE_28/CE (887:985:1084)(887:985:1084)) + (INTERCONNECT SLICE_79/F1 SLICE_28/C1 (534:645:756)(534:645:756)) + (INTERCONNECT SLICE_79/F1 SLICE_79/C0 (280:362:445)(280:362:445)) (INTERCONNECT SLICE_28/F0 SLICE_28/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_28/F1 RA\[10\]_MGIOL/OPOS (1081:1188:1296)(1081:1188:1296)) - (INTERCONNECT SLICE_104/F1 SLICE_29/C1 (534:645:756)(534:645:756)) - (INTERCONNECT SLICE_104/F1 SLICE_56/B1 (765:889:1013)(765:889:1013)) - (INTERCONNECT SLICE_123/F0 SLICE_29/B1 (765:883:1001)(765:883:1001)) - (INTERCONNECT SLICE_29/F1 SLICE_29/C0 (277:356:436)(277:356:436)) - (INTERCONNECT SLICE_29/Q0 SLICE_29/A0 (489:591:693)(489:591:693)) - (INTERCONNECT SLICE_29/Q0 SLICE_30/B1 (782:930:1078)(782:930:1078)) - (INTERCONNECT SLICE_29/Q0 SLICE_34/B1 (1483:1689:1896)(1483:1689:1896)) - (INTERCONNECT SLICE_29/Q0 SLICE_36/B0 (1853:2091:2330)(1853:2091:2330)) - (INTERCONNECT SLICE_29/Q0 SLICE_37/B1 (1853:2091:2330)(1853:2091:2330)) - (INTERCONNECT SLICE_29/Q0 SLICE_45/B1 (782:930:1078)(782:930:1078)) - (INTERCONNECT SLICE_29/Q0 SLICE_48/A1 (1912:2146:2380)(1912:2146:2380)) - (INTERCONNECT SLICE_29/Q0 SLICE_48/A0 (1912:2146:2380)(1912:2146:2380)) - (INTERCONNECT SLICE_29/Q0 SLICE_49/D1 (2087:2289:2491)(2087:2289:2491)) - (INTERCONNECT SLICE_29/Q0 SLICE_49/D0 (2087:2289:2491)(2087:2289:2491)) - (INTERCONNECT SLICE_29/Q0 SLICE_50/A1 (2297:2564:2832)(2297:2564:2832)) - (INTERCONNECT SLICE_29/Q0 SLICE_50/A0 (2297:2564:2832)(2297:2564:2832)) - (INTERCONNECT SLICE_29/Q0 SLICE_51/A0 (749:888:1028)(749:888:1028)) - (INTERCONNECT SLICE_29/Q0 SLICE_52/D0 (2467:2702:2937)(2467:2702:2937)) - (INTERCONNECT SLICE_29/Q0 SLICE_53/A0 (3057:3390:3724)(3057:3390:3724)) - (INTERCONNECT SLICE_29/Q0 SLICE_54/D1 (2847:3115:3383)(2847:3115:3383)) - (INTERCONNECT SLICE_29/Q0 SLICE_56/A1 (743:873:1004)(743:873:1004)) - (INTERCONNECT SLICE_29/Q0 SLICE_57/D1 (538:606:674)(538:606:674)) - (INTERCONNECT SLICE_29/Q0 SLICE_58/D1 (3217:3517:3817)(3217:3517:3817)) - (INTERCONNECT SLICE_29/Q0 SLICE_58/D0 (3217:3517:3817)(3217:3517:3817)) - (INTERCONNECT SLICE_29/Q0 SLICE_62/C1 (1713:1936:2160)(1713:1936:2160)) - (INTERCONNECT SLICE_29/Q0 SLICE_62/C0 (1713:1936:2160)(1713:1936:2160)) - (INTERCONNECT SLICE_29/Q0 SLICE_66/D1 (1185:1326:1468)(1185:1326:1468)) - (INTERCONNECT SLICE_29/Q0 SLICE_66/D0 (2467:2702:2937)(2467:2702:2937)) - (INTERCONNECT SLICE_29/Q0 SLICE_70/B0 (1482:1689:1897)(1482:1689:1897)) - (INTERCONNECT SLICE_29/Q0 SLICE_73/B1 (3089:3425:3761)(3089:3425:3761)) - (INTERCONNECT SLICE_29/Q0 SLICE_74/D0 (983:1092:1201)(983:1092:1201)) - (INTERCONNECT SLICE_29/Q0 SLICE_75/B1 (780:916:1052)(780:916:1052)) - (INTERCONNECT SLICE_29/Q0 SLICE_79/D1 (983:1092:1201)(983:1092:1201)) - (INTERCONNECT SLICE_29/Q0 SLICE_85/D0 (2467:2702:2937)(2467:2702:2937)) - (INTERCONNECT SLICE_29/Q0 SLICE_86/B0 (1802:2044:2286)(1802:2044:2286)) - (INTERCONNECT SLICE_29/Q0 SLICE_91/D0 (1185:1326:1468)(1185:1326:1468)) - (INTERCONNECT SLICE_29/Q0 SLICE_95/C0 (1713:1936:2160)(1713:1936:2160)) - (INTERCONNECT SLICE_29/Q0 SLICE_96/C1 (1571:1800:2029)(1571:1800:2029)) - (INTERCONNECT SLICE_29/Q0 SLICE_97/B0 (1802:2044:2286)(1802:2044:2286)) - (INTERCONNECT SLICE_29/Q0 SLICE_103/A0 (1015:1189:1363)(1015:1189:1363)) - (INTERCONNECT SLICE_29/Q0 SLICE_105/C1 (1571:1800:2029)(1571:1800:2029)) - (INTERCONNECT SLICE_29/Q0 SLICE_105/C0 (1571:1800:2029)(1571:1800:2029)) - (INTERCONNECT SLICE_29/Q0 SLICE_107/D0 (540:620:700)(540:620:700)) - (INTERCONNECT SLICE_29/Q0 SLICE_110/A1 (1770:2009:2249)(1770:2009:2249)) - (INTERCONNECT SLICE_29/Q0 SLICE_122/D1 (540:620:700)(540:620:700)) + (INTERCONNECT SLICE_28/F1 SLICE_68/C1 (541:653:766)(541:653:766)) + (INTERCONNECT SLICE_29/Q0 SLICE_29/D1 (542:607:672)(542:607:672)) + (INTERCONNECT SLICE_29/Q0 SLICE_29/A0 (487:587:687)(487:587:687)) + (INTERCONNECT SLICE_29/Q0 SLICE_30/B1 (1698:1904:2111)(1698:1904:2111)) + (INTERCONNECT SLICE_29/Q0 SLICE_34/D1 (1359:1501:1643)(1359:1501:1643)) + (INTERCONNECT SLICE_29/Q0 SLICE_36/B0 (1971:2213:2455)(1971:2213:2455)) + (INTERCONNECT SLICE_29/Q0 SLICE_37/D1 (2099:2305:2511)(2099:2305:2511)) + (INTERCONNECT SLICE_29/Q0 SLICE_45/B1 (1698:1904:2111)(1698:1904:2111)) + (INTERCONNECT SLICE_29/Q0 SLICE_48/B1 (2513:2799:3086)(2513:2799:3086)) + (INTERCONNECT SLICE_29/Q0 SLICE_48/B0 (2513:2799:3086)(2513:2799:3086)) + (INTERCONNECT SLICE_29/Q0 SLICE_49/A1 (2481:2765:3049)(2481:2765:3049)) + (INTERCONNECT SLICE_29/Q0 SLICE_49/A0 (2481:2765:3049)(2481:2765:3049)) + (INTERCONNECT SLICE_29/Q0 SLICE_50/C1 (2282:2555:2829)(2282:2555:2829)) + (INTERCONNECT SLICE_29/Q0 SLICE_50/C0 (2282:2555:2829)(2282:2555:2829)) + (INTERCONNECT SLICE_29/Q0 SLICE_51/C0 (2267:2539:2811)(2267:2539:2811)) + (INTERCONNECT SLICE_29/Q0 SLICE_52/B0 (2898:3218:3538)(2898:3218:3538)) + (INTERCONNECT SLICE_29/Q0 SLICE_53/B0 (2898:3218:3538)(2898:3218:3538)) + (INTERCONNECT SLICE_29/Q0 SLICE_54/B1 (2898:3218:3538)(2898:3218:3538)) + (INTERCONNECT SLICE_29/Q0 SLICE_57/B1 (1698:1904:2111)(1698:1904:2111)) + (INTERCONNECT SLICE_29/Q0 SLICE_58/C1 (2267:2539:2811)(2267:2539:2811)) + (INTERCONNECT SLICE_29/Q0 SLICE_58/C0 (2267:2539:2811)(2267:2539:2811)) + (INTERCONNECT SLICE_29/Q0 wb_adr_5_i_0_1\[0\]\/SLICE_60/D0 (1826:1996:2167) + (1826:1996:2167)) + (INTERCONNECT SLICE_29/Q0 SLICE_61/C1 (1837:2062:2288)(1837:2062:2288)) + (INTERCONNECT SLICE_29/Q0 SLICE_61/A0 (744:869:995)(744:869:995)) + (INTERCONNECT SLICE_29/Q0 SLICE_62/D1 (1359:1501:1643)(1359:1501:1643)) + (INTERCONNECT SLICE_29/Q0 SLICE_64/A1 (748:891:1035)(748:891:1035)) + (INTERCONNECT SLICE_29/Q0 SLICE_64/C0 (2267:2539:2811)(2267:2539:2811)) + (INTERCONNECT SLICE_29/Q0 SLICE_67/B0 (776:904:1032)(776:904:1032)) + (INTERCONNECT SLICE_29/Q0 SLICE_70/B0 (1698:1904:2111)(1698:1904:2111)) + (INTERCONNECT SLICE_29/Q0 SLICE_81/B0 (1046:1226:1407)(1046:1226:1407)) + (INTERCONNECT SLICE_29/Q0 SLICE_82/D0 (3026:3310:3594)(3026:3310:3594)) + (INTERCONNECT SLICE_29/Q0 SLICE_86/C0 (3042:3381:3721)(3042:3381:3721)) + (INTERCONNECT SLICE_29/Q0 SLICE_91/C0 (549:682:815)(549:682:815)) + (INTERCONNECT SLICE_29/Q0 SLICE_93/B1 (3638:4022:4406)(3638:4022:4406)) + (INTERCONNECT SLICE_29/Q0 SLICE_94/A1 (752:882:1013)(752:882:1013)) + (INTERCONNECT SLICE_29/Q0 SLICE_100/C0 (995:1159:1324)(995:1159:1324)) + (INTERCONNECT SLICE_29/Q0 SLICE_107/A1 (1014:1192:1370)(1014:1192:1370)) + (INTERCONNECT SLICE_29/Q0 SLICE_107/C0 (3407:3778:4149)(3407:3778:4149)) + (INTERCONNECT SLICE_29/Q0 SLICE_111/D1 (3031:3315:3600)(3031:3315:3600)) + (INTERCONNECT SLICE_29/Q0 SLICE_111/D0 (3031:3315:3600)(3031:3315:3600)) + (INTERCONNECT SLICE_29/Q0 SLICE_122/D1 (2099:2305:2511)(2099:2305:2511)) + (INTERCONNECT SLICE_99/F1 SLICE_29/B0 (508:600:693)(508:600:693)) (INTERCONNECT SLICE_29/F0 SLICE_29/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_29/F1 SLICE_51/LSR (1152:1278:1404)(1152:1278:1404)) + (INTERCONNECT SLICE_29/F1 SLICE_56/LSR (1152:1278:1404)(1152:1278:1404)) + (INTERCONNECT SLICE_29/F1 SLICE_58/LSR (1505:1660:1816)(1505:1660:1816)) (INTERCONNECT ufmefb\/EFBInst_0/WBDATO1 SLICE_30/C1 (1607:1801:1995) (1607:1801:1995)) - (INTERCONNECT SLICE_30/F1 SLICE_30/B0 (508:600:693)(508:600:693)) - (INTERCONNECT SLICE_45/F1 SLICE_30/A0 (733:854:976)(733:854:976)) + (INTERCONNECT SLICE_30/F1 SLICE_30/C0 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_45/F1 SLICE_30/B0 (765:889:1013)(765:889:1013)) (INTERCONNECT SLICE_45/F1 SLICE_45/C0 (280:362:445)(280:362:445)) (INTERCONNECT SLICE_30/F0 SLICE_30/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_37/Q0 SLICE_31/B0 (1216:1386:1556)(1216:1386:1556)) + (INTERCONNECT CROW\[0\]_I/PADDI SLICE_31/D0 (1574:1704:1834)(1574:1704:1834)) + (INTERCONNECT SLICE_37/Q0 SLICE_31/B0 (1472:1665:1859)(1472:1665:1859)) (INTERCONNECT SLICE_37/Q0 SLICE_37/A0 (481:575:669)(481:575:669)) - (INTERCONNECT SLICE_37/Q0 SLICE_38/B1 (1677:1877:2077)(1677:1877:2077)) - (INTERCONNECT SLICE_37/Q0 SLICE_38/B0 (1677:1877:2077)(1677:1877:2077)) - (INTERCONNECT SLICE_37/Q0 SLICE_39/B1 (1682:1882:2083)(1682:1882:2083)) - (INTERCONNECT SLICE_37/Q0 SLICE_39/B0 (1682:1882:2083)(1682:1882:2083)) - (INTERCONNECT SLICE_37/Q0 SLICE_40/C1 (1821:2040:2260)(1821:2040:2260)) - (INTERCONNECT SLICE_37/Q0 SLICE_40/C0 (1821:2040:2260)(1821:2040:2260)) - (INTERCONNECT SLICE_37/Q0 SLICE_41/C1 (1451:1638:1826)(1451:1638:1826)) - (INTERCONNECT SLICE_37/Q0 SLICE_41/C0 (1451:1638:1826)(1451:1638:1826)) - (INTERCONNECT SLICE_37/Q0 SLICE_42/D1 (988:1090:1193)(988:1090:1193)) - (INTERCONNECT SLICE_37/Q0 SLICE_42/D0 (988:1090:1193)(988:1090:1193)) - (INTERCONNECT SLICE_37/Q0 SLICE_120/B1 (2052:2284:2517)(2052:2284:2517)) - (INTERCONNECT SLICE_37/Q0 SLICE_120/B0 (2052:2284:2517)(2052:2284:2517)) - (INTERCONNECT CROW\[0\]_I/PADDI SLICE_31/A0 (2148:2375:2602)(2148:2375:2602)) - (INTERCONNECT SLICE_31/Q0 SLICE_31/M1 (488:531:575)(488:531:575)) - (INTERCONNECT SLICE_31/Q0 SLICE_103/B1 (770:896:1022)(770:896:1022)) - (INTERCONNECT SLICE_31/Q0 SLICE_107/A1 (1446:1640:1835)(1446:1640:1835)) - (INTERCONNECT SLICE_31/Q0 SLICE_107/A0 (1446:1640:1835)(1446:1640:1835)) - (INTERCONNECT SLICE_31/Q0 SLICE_122/A0 (1446:1640:1835)(1446:1640:1835)) - (INTERCONNECT PHI2_MGIOL/IN SLICE_31/M0 (1479:1611:1744)(1479:1611:1744)) - (INTERCONNECT SLICE_31/F0 RBA\[0\]_MGIOL/OPOS (1527:1661:1795)(1527:1661:1795)) - (INTERCONNECT SLICE_31/Q1 SLICE_103/C1 (536:647:758)(536:647:758)) - (INTERCONNECT SLICE_31/Q1 SLICE_107/B1 (1475:1670:1865)(1475:1670:1865)) - (INTERCONNECT SLICE_31/Q1 SLICE_107/B0 (1475:1670:1865)(1475:1670:1865)) - (INTERCONNECT SLICE_31/Q1 SLICE_122/B0 (1475:1670:1865)(1475:1670:1865)) - (INTERCONNECT SLICE_80/Q0 SLICE_32/D1 (535:596:658)(535:596:658)) - (INTERCONNECT SLICE_80/Q0 SLICE_34/B0 (777:906:1036)(777:906:1036)) - (INTERCONNECT SLICE_80/Q0 SLICE_46/D0 (802:897:992)(802:897:992)) - (INTERCONNECT SLICE_80/Q0 SLICE_81/A1 (1376:1568:1760)(1376:1568:1760)) - (INTERCONNECT SLICE_80/Q0 SLICE_94/A0 (1437:1632:1828)(1437:1632:1828)) + (INTERCONNECT SLICE_37/Q0 SLICE_38/A1 (761:889:1018)(761:889:1018)) + (INTERCONNECT SLICE_37/Q0 SLICE_38/A0 (761:889:1018)(761:889:1018)) + (INTERCONNECT SLICE_37/Q0 SLICE_39/C1 (1698:1906:2114)(1698:1906:2114)) + (INTERCONNECT SLICE_37/Q0 SLICE_39/C0 (1698:1906:2114)(1698:1906:2114)) + (INTERCONNECT SLICE_37/Q0 SLICE_40/C1 (942:1093:1244)(942:1093:1244)) + (INTERCONNECT SLICE_37/Q0 SLICE_40/C0 (942:1093:1244)(942:1093:1244)) + (INTERCONNECT SLICE_37/Q0 SLICE_41/A1 (1141:1302:1464)(1141:1302:1464)) + (INTERCONNECT SLICE_37/Q0 SLICE_41/A0 (1141:1302:1464)(1141:1302:1464)) + (INTERCONNECT SLICE_37/Q0 SLICE_42/B1 (1163:1326:1489)(1163:1326:1489)) + (INTERCONNECT SLICE_37/Q0 SLICE_42/B0 (1163:1326:1489)(1163:1326:1489)) + (INTERCONNECT SLICE_37/Q0 SLICE_120/C1 (2068:2308:2548)(2068:2308:2548)) + (INTERCONNECT SLICE_37/Q0 SLICE_120/C0 (2068:2308:2548)(2068:2308:2548)) + (INTERCONNECT SLICE_31/Q0 SLICE_31/M1 (499:544:590)(499:544:590)) + (INTERCONNECT SLICE_31/Q0 SLICE_57/D1 (544:604:665)(544:604:665)) + (INTERCONNECT SLICE_31/Q0 SLICE_100/D1 (534:591:648)(534:591:648)) + (INTERCONNECT SLICE_31/Q0 SLICE_110/D1 (544:604:665)(544:604:665)) + (INTERCONNECT SLICE_31/Q0 SLICE_110/D0 (544:604:665)(544:604:665)) + (INTERCONNECT PHI2_MGIOL/IN SLICE_31/M0 (1442:1578:1714)(1442:1578:1714)) + (INTERCONNECT SLICE_31/F0 RBA\[0\]_MGIOL/OPOS (1854:2023:2192)(1854:2023:2192)) + (INTERCONNECT SLICE_31/F1 RCLKout_MGIOL/ONEG (1872:2042:2213)(1872:2042:2213)) + (INTERCONNECT SLICE_31/Q1 SLICE_57/C1 (540:659:778)(540:659:778)) + (INTERCONNECT SLICE_31/Q1 SLICE_100/A1 (733:853:974)(733:853:974)) + (INTERCONNECT SLICE_31/Q1 SLICE_110/C1 (540:659:778)(540:659:778)) + (INTERCONNECT SLICE_31/Q1 SLICE_110/C0 (540:659:778)(540:659:778)) + (INTERCONNECT SLICE_41/Q0 SLICE_32/C1 (534:639:744)(534:639:744)) + (INTERCONNECT MAin\[6\]_I/PADDI SLICE_32/B1 (2201:2420:2640)(2201:2420:2640)) + (INTERCONNECT MAin\[6\]_I/PADDI SLICE_41/B0 (2565:2816:3067)(2565:2816:3067)) + (INTERCONNECT MAin\[6\]_I/PADDI SLICE_90/B1 (2195:2414:2633)(2195:2414:2633)) + (INTERCONNECT SLICE_46/Q0 SLICE_32/A1 (738:861:985)(738:861:985)) + (INTERCONNECT SLICE_46/Q0 SLICE_108/C1 (539:652:765)(539:652:765)) + (INTERCONNECT SLICE_46/Q0 SLICE_108/C0 (539:652:765)(539:652:765)) + (INTERCONNECT SLICE_46/Q0 SLICE_112/A1 (1721:1948:2175)(1721:1948:2175)) + (INTERCONNECT SLICE_46/Q0 SLICE_113/D1 (820:915:1010)(820:915:1010)) + (INTERCONNECT SLICE_46/Q0 SLICE_113/D0 (820:915:1010)(820:915:1010)) + (INTERCONNECT SLICE_46/Q0 SLICE_114/D1 (1517:1679:1841)(1517:1679:1841)) + (INTERCONNECT SLICE_46/Q0 SLICE_114/B0 (1432:1627:1822)(1432:1627:1822)) + (INTERCONNECT SLICE_46/Q0 SLICE_115/C1 (1179:1368:1557)(1179:1368:1557)) + (INTERCONNECT SLICE_46/Q0 SLICE_115/D0 (820:915:1010)(820:915:1010)) + (INTERCONNECT SLICE_46/Q0 SLICE_116/C1 (1179:1368:1557)(1179:1368:1557)) + (INTERCONNECT SLICE_46/Q0 SLICE_116/C0 (1179:1368:1557)(1179:1368:1557)) (INTERCONNECT SLICE_32/F0 SLICE_32/DI0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_32/Q0 SLICE_32/M1 (488:531:575)(488:531:575)) - (INTERCONNECT SLICE_32/Q0 SLICE_35/A0 (1070:1230:1390)(1070:1230:1390)) - (INTERCONNECT SLICE_32/F1 LED_I/PADDO (1802:1982:2163)(1802:1982:2163)) - (INTERCONNECT SLICE_46/Q0 SLICE_33/D1 (818:907:996)(818:907:996)) - (INTERCONNECT SLICE_46/Q0 SLICE_111/D1 (1239:1362:1486)(1239:1362:1486)) - (INTERCONNECT SLICE_46/Q0 SLICE_111/D0 (1239:1362:1486)(1239:1362:1486)) - (INTERCONNECT SLICE_46/Q0 SLICE_114/D1 (1546:1698:1850)(1546:1698:1850)) - (INTERCONNECT SLICE_46/Q0 SLICE_115/C1 (1250:1428:1607)(1250:1428:1607)) - (INTERCONNECT SLICE_46/Q0 SLICE_115/C0 (1250:1428:1607)(1250:1428:1607)) - (INTERCONNECT SLICE_46/Q0 SLICE_116/C1 (1167:1348:1529)(1167:1348:1529)) - (INTERCONNECT SLICE_46/Q0 SLICE_116/D0 (818:907:996)(818:907:996)) - (INTERCONNECT SLICE_46/Q0 SLICE_117/A1 (1366:1557:1749)(1366:1557:1749)) - (INTERCONNECT SLICE_46/Q0 SLICE_117/C0 (1167:1348:1529)(1167:1348:1529)) - (INTERCONNECT SLICE_46/Q0 SLICE_118/D1 (818:907:996)(818:907:996)) - (INTERCONNECT SLICE_46/Q0 SLICE_118/A0 (1366:1557:1749)(1366:1557:1749)) - (INTERCONNECT SLICE_39/Q1 SLICE_33/C1 (531:639:747)(531:639:747)) - (INTERCONNECT MAin\[3\]_I/PADDI SLICE_33/B1 (3093:3365:3638)(3093:3365:3638)) - (INTERCONNECT MAin\[3\]_I/PADDI SLICE_39/A1 (3388:3693:3998)(3388:3693:3998)) - (INTERCONNECT MAin\[3\]_I/PADDI SLICE_93/B1 (3087:3359:3631)(3087:3359:3631)) - (INTERCONNECT SLICE_33/Q0 SLICE_35/C0 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(INTERCONNECT SLICE_40/Q1 SLICE_116/D0 (520:573:626)(520:573:626)) + (INTERCONNECT MAin\[7\]_I/PADDI SLICE_41/D1 (2323:2506:2689)(2323:2506:2689)) + (INTERCONNECT MAin\[7\]_I/PADDI SLICE_90/C1 (1882:2093:2304)(1882:2093:2304)) + (INTERCONNECT MAin\[7\]_I/PADDI SLICE_116/A1 (2533:2781:3030)(2533:2781:3030)) (INTERCONNECT SLICE_41/F1 SLICE_41/DI1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_41/F0 SLICE_41/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_41/Q0 SLICE_114/C1 (531:639:747)(531:639:747)) - (INTERCONNECT SLICE_41/Q1 SLICE_116/D1 (789:873:958)(789:873:958)) - (INTERCONNECT MAin\[9\]_I/PADDI SLICE_42/A1 (2003:2212:2422)(2003:2212:2422)) - (INTERCONNECT MAin\[9\]_I/PADDI SLICE_111/A1 (2003:2212:2422)(2003:2212:2422)) - (INTERCONNECT MAin\[9\]_I/PADDI SLICE_111/A0 (2003:2212:2422)(2003:2212:2422)) - (INTERCONNECT MAin\[9\]_I/PADDI SLICE_115/A1 (2003:2212:2422)(2003:2212:2422)) - (INTERCONNECT MAin\[8\]_I/PADDI SLICE_42/C0 (2329:2565:2802)(2329:2565:2802)) - (INTERCONNECT MAin\[8\]_I/PADDI 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(1582:1743:1905)(1582:1743:1905)) - (INTERCONNECT SLICE_103/F0 SLICE_49/CE (1963:2158:2354)(1963:2158:2354)) - (INTERCONNECT SLICE_103/F0 SLICE_49/CE (1963:2158:2354)(1963:2158:2354)) - (INTERCONNECT SLICE_103/F0 SLICE_50/CE (1963:2158:2354)(1963:2158:2354)) - (INTERCONNECT SLICE_103/F0 SLICE_50/CE (1963:2158:2354)(1963:2158:2354)) - (INTERCONNECT SLICE_103/F0 SLICE_52/CE (2327:2554:2781)(2327:2554:2781)) - (INTERCONNECT SLICE_103/F0 SLICE_52/CE (2327:2554:2781)(2327:2554:2781)) - (INTERCONNECT SLICE_103/F0 SLICE_53/CE (1593:1756:1920)(1593:1756:1920)) - (INTERCONNECT SLICE_103/F0 SLICE_53/CE (1593:1756:1920)(1593:1756:1920)) - (INTERCONNECT SLICE_103/F0 SLICE_54/CE (1593:1756:1920)(1593:1756:1920)) - (INTERCONNECT SLICE_103/F0 SLICE_54/CE (1593:1756:1920)(1593:1756:1920)) - (INTERCONNECT SLICE_103/F0 SLICE_55/CE (2327:2554:2781)(2327:2554:2781)) - (INTERCONNECT SLICE_103/F0 SLICE_55/CE (2327:2554:2781)(2327:2554:2781)) - (INTERCONNECT SLICE_103/F0 SLICE_58/CE (1582:1744:1907)(1582:1744:1907)) - (INTERCONNECT SLICE_47/Q0 SLICE_58/C1 (534:644:754)(534:644:754)) + (INTERCONNECT SLICE_100/F0 SLICE_47/CE (882:979:1076)(882:979:1076)) + (INTERCONNECT SLICE_100/F0 SLICE_47/CE (882:979:1076)(882:979:1076)) + (INTERCONNECT SLICE_100/F0 SLICE_48/CE (2012:2209:2406)(2012:2209:2406)) + (INTERCONNECT SLICE_100/F0 SLICE_48/CE (2012:2209:2406)(2012:2209:2406)) + (INTERCONNECT SLICE_100/F0 SLICE_49/CE (2012:2209:2406)(2012:2209:2406)) + (INTERCONNECT SLICE_100/F0 SLICE_49/CE (2012:2209:2406)(2012:2209:2406)) + (INTERCONNECT SLICE_100/F0 SLICE_50/CE (2012:2209:2406)(2012:2209:2406)) + (INTERCONNECT SLICE_100/F0 SLICE_50/CE (2012:2209:2406)(2012:2209:2406)) + (INTERCONNECT SLICE_100/F0 SLICE_52/CE (1627:1788:1950)(1627:1788:1950)) + (INTERCONNECT SLICE_100/F0 SLICE_52/CE (1627:1788:1950)(1627:1788:1950)) + (INTERCONNECT SLICE_100/F0 SLICE_53/CE (2090:2294:2498)(2090:2294:2498)) + (INTERCONNECT SLICE_100/F0 SLICE_53/CE (2090:2294:2498)(2090:2294:2498)) + (INTERCONNECT SLICE_100/F0 SLICE_54/CE (2090:2294:2498)(2090:2294:2498)) + (INTERCONNECT SLICE_100/F0 SLICE_54/CE (2090:2294:2498)(2090:2294:2498)) + (INTERCONNECT SLICE_100/F0 SLICE_55/CE (2084:2287:2491)(2084:2287:2491)) + (INTERCONNECT SLICE_100/F0 SLICE_55/CE (2084:2287:2491)(2084:2287:2491)) + (INTERCONNECT SLICE_100/F0 SLICE_58/CE (1252:1381:1510)(1252:1381:1510)) + (INTERCONNECT SLICE_47/Q0 SLICE_122/B1 (1209:1375:1542)(1209:1375:1542)) (INTERCONNECT SLICE_47/Q0 - ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI0in (1530:1666:1802) - (1530:1666:1802)) - (INTERCONNECT SLICE_47/Q1 SLICE_48/C0 (911:1055:1200)(911:1055:1200)) + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI0in (1786:1945:2105) + (1786:1945:2105)) + (INTERCONNECT SLICE_47/Q1 SLICE_48/A0 (1369:1551:1733)(1369:1551:1733)) (INTERCONNECT SLICE_47/Q1 - ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI1in (1745:1908:2072) - (1745:1908:2072)) - (INTERCONNECT SLICE_48/Q0 SLICE_48/D1 (523:578:633)(523:578:633)) + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI1in (1640:1799:1958) + (1640:1799:1958)) + (INTERCONNECT SLICE_48/Q0 SLICE_48/A1 (733:853:974)(733:853:974)) (INTERCONNECT SLICE_48/Q0 - ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI2in (1236:1368:1501) - (1236:1368:1501)) + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI2in (643:706:769) + (643:706:769)) (INTERCONNECT SLICE_48/F1 SLICE_48/DI1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_48/F0 SLICE_48/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_48/Q1 SLICE_49/C0 (980:1133:1286)(980:1133:1286)) + (INTERCONNECT SLICE_48/Q1 SLICE_49/D0 (523:578:633)(523:578:633)) (INTERCONNECT SLICE_48/Q1 - ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI3in (1086:1195:1304) - (1086:1195:1304)) - (INTERCONNECT SLICE_49/Q0 SLICE_49/C1 (534:644:754)(534:644:754)) + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI3in (650:720:791) + (650:720:791)) + (INTERCONNECT SLICE_49/Q0 SLICE_49/D1 (523:578:633)(523:578:633)) (INTERCONNECT SLICE_49/Q0 - ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI4in (909:1006:1104) - (909:1006:1104)) - (INTERCONNECT SLICE_97/F1 SLICE_49/B1 (1411:1602:1793)(1411:1602:1793)) - (INTERCONNECT SLICE_97/F1 SLICE_49/B0 (1411:1602:1793)(1411:1602:1793)) - (INTERCONNECT SLICE_97/F1 SLICE_50/B0 (1411:1602:1793)(1411:1602:1793)) - (INTERCONNECT SLICE_97/F1 SLICE_58/B1 (778:907:1036)(778:907:1036)) - (INTERCONNECT SLICE_97/F1 SLICE_58/B0 (513:611:710)(513:611:710)) - (INTERCONNECT SLICE_97/F1 SLICE_97/D0 (536:597:658)(536:597:658)) + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI4in (977:1082:1188) + (977:1082:1188)) + (INTERCONNECT SLICE_91/F1 SLICE_49/C1 (1180:1358:1536)(1180:1358:1536)) + (INTERCONNECT SLICE_91/F1 SLICE_49/C0 (1180:1358:1536)(1180:1358:1536)) + (INTERCONNECT SLICE_91/F1 SLICE_50/A0 (1379:1567:1756)(1379:1567:1756)) + (INTERCONNECT SLICE_91/F1 SLICE_91/A0 (735:859:984)(735:859:984)) + (INTERCONNECT SLICE_91/F1 SLICE_122/C1 (980:1137:1295)(980:1137:1295)) (INTERCONNECT SLICE_49/F1 SLICE_49/DI1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_49/F0 SLICE_49/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_49/Q1 SLICE_50/C0 (802:947:1093)(802:947:1093)) + (INTERCONNECT SLICE_49/Q1 SLICE_50/B0 (765:888:1011)(765:888:1011)) (INTERCONNECT SLICE_49/Q1 - ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI5in (908:1009:1111) - (908:1009:1111)) + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI5in (977:1082:1188) + (977:1082:1188)) (INTERCONNECT SLICE_50/Q0 SLICE_50/B1 (765:888:1011)(765:888:1011)) (INTERCONNECT SLICE_50/Q0 - ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI6in (909:1006:1104) - (909:1006:1104)) + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI6in (977:1082:1188) + (977:1082:1188)) (INTERCONNECT SLICE_50/F1 SLICE_50/DI1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_50/F0 SLICE_50/DI0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_50/Q1 - ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI7in (906:1001:1097) - (906:1001:1097)) - (INTERCONNECT SLICE_66/F1 SLICE_51/D1 (930:1033:1137)(930:1033:1137)) - (INTERCONNECT SLICE_66/F1 wb_dati_5_1_iv_0_o3\[5\]\/SLICE_59/D1 (1305:1441:1577) - (1305:1441:1577)) - (INTERCONNECT SLICE_66/F1 wb_dati_5_1_iv_0_o3\[5\]\/SLICE_59/D0 (1305:1441:1577) - (1305:1441:1577)) - (INTERCONNECT SLICE_66/F1 SLICE_66/C0 (286:377:469)(286:377:469)) - (INTERCONNECT SLICE_66/F1 SLICE_68/C0 (941:1099:1258)(941:1099:1258)) - (INTERCONNECT SLICE_66/F1 SLICE_69/D1 (550:620:691)(550:620:691)) - (INTERCONNECT SLICE_66/F1 SLICE_76/D0 (1305:1441:1577)(1305:1441:1577)) - (INTERCONNECT SLICE_66/F1 SLICE_77/A1 (739:869:1000)(739:869:1000)) - (INTERCONNECT SLICE_66/F1 SLICE_87/D1 (532:594:656)(532:594:656)) - (INTERCONNECT SLICE_66/F1 SLICE_91/D1 (550:620:691)(550:620:691)) - (INTERCONNECT SLICE_66/F1 SLICE_92/A0 (1140:1309:1478)(1140:1309:1478)) - (INTERCONNECT SLICE_66/F1 SLICE_113/C1 (815:967:1119)(815:967:1119)) - (INTERCONNECT SLICE_66/F1 SLICE_113/C0 (815:967:1119)(815:967:1119)) - (INTERCONNECT SLICE_121/F0 SLICE_51/C1 (280:362:445)(280:362:445)) - (INTERCONNECT SLICE_121/F0 SLICE_92/B1 (511:606:702)(511:606:702)) - (INTERCONNECT SLICE_121/F1 SLICE_51/B1 (762:883:1004)(762:883:1004)) - (INTERCONNECT SLICE_98/F0 SLICE_51/A1 (733:854:976)(733:854:976)) - (INTERCONNECT SLICE_98/F0 SLICE_92/D0 (269:296:324)(269:296:324)) - (INTERCONNECT SLICE_107/F1 SLICE_51/D0 (789:873:958)(789:873:958)) - (INTERCONNECT SLICE_51/F1 SLICE_51/C0 (277:356:436)(277:356:436)) + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI7in (640:701:762) + (640:701:762)) + (INTERCONNECT SLICE_121/F0 SLICE_51/D1 (523:579:635)(523:579:635)) + (INTERCONNECT SLICE_121/F0 SLICE_89/B1 (511:606:702)(511:606:702)) + (INTERCONNECT SLICE_121/F1 SLICE_51/C1 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_64/F1 SLICE_51/B1 (771:904:1037)(771:904:1037)) + (INTERCONNECT SLICE_64/F1 wb_dati_5_1_iv_0_0_o2\[5\]\/SLICE_59/B1 (1396:1602:1809) + (1396:1602:1809)) + (INTERCONNECT SLICE_64/F1 wb_dati_5_1_iv_0_0_o2\[5\]\/SLICE_59/B0 (1396:1602:1809) + (1396:1602:1809)) + (INTERCONNECT SLICE_64/F1 SLICE_64/B0 (511:606:702)(511:606:702)) + (INTERCONNECT SLICE_64/F1 SLICE_66/A0 (1401:1600:1800)(1401:1600:1800)) + (INTERCONNECT SLICE_64/F1 SLICE_73/A0 (1765:1996:2227)(1765:1996:2227)) + (INTERCONNECT SLICE_64/F1 SLICE_74/A1 (1396:1595:1794)(1396:1595:1794)) + (INTERCONNECT SLICE_64/F1 SLICE_82/A1 (1396:1595:1794)(1396:1595:1794)) + (INTERCONNECT SLICE_64/F1 SLICE_84/A1 (1401:1600:1800)(1401:1600:1800)) + (INTERCONNECT SLICE_64/F1 SLICE_87/D1 (816:917:1019)(816:917:1019)) + (INTERCONNECT SLICE_64/F1 SLICE_88/C1 (827:983:1140)(827:983:1140)) + (INTERCONNECT SLICE_64/F1 SLICE_89/B0 (771:904:1037)(771:904:1037)) + (INTERCONNECT SLICE_95/F0 SLICE_51/A1 (1005:1155:1306)(1005:1155:1306)) + (INTERCONNECT SLICE_95/F0 SLICE_89/C0 (1133:1308:1483)(1133:1308:1483)) + (INTERCONNECT SLICE_110/F0 SLICE_51/D0 (789:873:958)(789:873:958)) + (INTERCONNECT SLICE_51/F1 SLICE_51/B0 (508:600:693)(508:600:693)) (INTERCONNECT SLICE_51/F0 SLICE_51/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_92/F0 SLICE_51/CE (539:596:653)(539:596:653)) - (INTERCONNECT SLICE_57/F1 SLICE_51/LSR (1146:1276:1406)(1146:1276:1406)) - (INTERCONNECT SLICE_57/F1 SLICE_56/LSR (1510:1671:1833)(1510:1671:1833)) - (INTERCONNECT SLICE_57/F1 SLICE_57/D0 (525:584:643)(525:584:643)) - (INTERCONNECT SLICE_57/F1 SLICE_58/LSR (881:983:1086)(881:983:1086)) + (INTERCONNECT SLICE_89/F0 SLICE_51/CE (539:596:653)(539:596:653)) (INTERCONNECT SLICE_51/Q0 ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBCYCIin - (1533:1667:1802)(1533:1667:1802)) + (912:1008:1104)(912:1008:1104)) (INTERCONNECT SLICE_51/Q0 ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBSTBIin - (1879:2052:2226)(1879:2052:2226)) - (INTERCONNECT SLICE_123/F1 SLICE_52/D1 (1239:1374:1509)(1239:1374:1509)) - (INTERCONNECT SLICE_123/F1 SLICE_55/D0 (1239:1374:1509)(1239:1374:1509)) - (INTERCONNECT SLICE_123/F1 SLICE_63/C1 (813:962:1111)(813:962:1111)) - (INTERCONNECT SLICE_123/F1 SLICE_75/C0 (538:655:772)(538:655:772)) - (INTERCONNECT SLICE_123/F1 SLICE_86/B1 (1038:1199:1361)(1038:1199:1361)) - (INTERCONNECT SLICE_123/F1 SLICE_95/B0 (1044:1206:1368)(1044:1206:1368)) - (INTERCONNECT SLICE_91/F0 SLICE_52/C1 (534:639:744)(534:639:744)) - (INTERCONNECT SLICE_77/F1 SLICE_52/A1 (483:582:681)(483:582:681)) - (INTERCONNECT SLICE_77/F1 SLICE_54/A0 (1111:1274:1438)(1111:1274:1438)) - (INTERCONNECT SLICE_77/F1 SLICE_55/C0 (284:372:461)(284:372:461)) - (INTERCONNECT SLICE_77/F1 SLICE_77/C0 (538:655:772)(538:655:772)) - (INTERCONNECT SLICE_102/F0 SLICE_52/C0 (868:1015:1163)(868:1015:1163)) - (INTERCONNECT SLICE_58/Q0 SLICE_52/B0 (1468:1656:1845)(1468:1656:1845)) + (1258:1393:1528)(1258:1393:1528)) + (INTERCONNECT SLICE_74/F1 SLICE_52/D1 (978:1078:1179)(978:1078:1179)) + (INTERCONNECT SLICE_74/F1 SLICE_54/A0 (1515:1716:1917)(1515:1716:1917)) + (INTERCONNECT SLICE_74/F1 SLICE_55/C0 (534:645:756)(534:645:756)) + (INTERCONNECT SLICE_74/F1 SLICE_74/D0 (1342:1474:1606)(1342:1474:1606)) + (INTERCONNECT SLICE_85/F0 SLICE_52/C1 (531:639:747)(531:639:747)) + (INTERCONNECT SLICE_71/F1 SLICE_52/B1 (1050:1207:1364)(1050:1207:1364)) + (INTERCONNECT SLICE_71/F1 SLICE_55/B0 (1414:1602:1791)(1414:1602:1791)) + (INTERCONNECT SLICE_71/F1 SLICE_71/C0 (280:362:445)(280:362:445)) + (INTERCONNECT SLICE_71/F1 SLICE_86/B1 (1420:1609:1798)(1420:1609:1798)) + (INTERCONNECT SLICE_71/F1 SLICE_88/B0 (1420:1609:1798)(1420:1609:1798)) + (INTERCONNECT SLICE_71/F1 SLICE_93/B0 (1414:1602:1791)(1414:1602:1791)) + (INTERCONNECT SLICE_98/F0 SLICE_52/D0 (523:573:623)(523:573:623)) + (INTERCONNECT SLICE_87/F1 SLICE_52/C0 (540:660:780)(540:660:780)) + (INTERCONNECT SLICE_87/F1 SLICE_81/D1 (795:894:994)(795:894:994)) + (INTERCONNECT SLICE_87/F1 SLICE_85/A0 (739:869:1000)(739:869:1000)) + (INTERCONNECT SLICE_87/F1 SLICE_87/C0 (280:362:445)(280:362:445)) + (INTERCONNECT SLICE_58/Q0 SLICE_52/A0 (1073:1231:1390)(1073:1231:1390)) (INTERCONNECT SLICE_58/Q0 ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBWEIin - (2071:2265:2460)(2071:2265:2460)) - (INTERCONNECT SLICE_113/F0 SLICE_52/A0 (1002:1155:1308)(1002:1155:1308)) - (INTERCONNECT SLICE_113/F0 SLICE_85/D1 (792:879:967)(792:879:967)) + (1381:1513:1645)(1381:1513:1645)) (INTERCONNECT SLICE_52/F1 SLICE_52/DI1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_52/F0 SLICE_52/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_52/Q0 SLICE_91/C0 (537:644:751)(537:644:751)) + (INTERCONNECT SLICE_52/Q0 SLICE_64/D0 (792:878:965)(792:878:965)) (INTERCONNECT SLICE_52/Q0 - ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI0in (1014:1116:1218) - (1014:1116:1218)) - (INTERCONNECT SLICE_52/Q1 SLICE_53/C0 (802:947:1093)(802:947:1093)) + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI0in (1084:1193:1303) + (1084:1193:1303)) + (INTERCONNECT SLICE_52/Q1 SLICE_53/A0 (746:869:993)(746:869:993)) (INTERCONNECT SLICE_52/Q1 - ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI1in (1599:1767:1935) - (1599:1767:1935)) - (INTERCONNECT SLICE_73/F1 SLICE_53/D1 (266:290:315)(266:290:315)) - (INTERCONNECT SLICE_71/F1 SLICE_53/C1 (541:653:766)(541:653:766)) - (INTERCONNECT SLICE_109/F1 SLICE_53/B1 (772:897:1023)(772:897:1023)) - (INTERCONNECT SLICE_87/F1 SLICE_53/A1 (749:875:1002)(749:875:1002)) - (INTERCONNECT SLICE_87/F1 SLICE_67/D1 (909:1002:1095)(909:1002:1095)) - (INTERCONNECT SLICE_87/F1 SLICE_87/C0 (280:362:445)(280:362:445)) - (INTERCONNECT SLICE_87/F1 SLICE_89/B0 (1151:1312:1473)(1151:1312:1473)) - (INTERCONNECT wb_dati_5_1_iv_0_o3\[5\]\/SLICE_59/OFX0 SLICE_53/D0 (543:608:673) - (543:608:673)) - (INTERCONNECT wb_dati_5_1_iv_0_o3\[5\]\/SLICE_59/OFX0 SLICE_54/C1 (547:659:772) - (547:659:772)) + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI1in (1344:1479:1615) + (1344:1479:1615)) + (INTERCONNECT SLICE_104/F1 SLICE_53/D1 (1220:1340:1460)(1220:1340:1460)) + (INTERCONNECT SLICE_87/F0 SLICE_53/C1 (531:639:747)(531:639:747)) + (INTERCONNECT SLICE_86/F0 SLICE_53/B1 (772:897:1023)(772:897:1023)) + (INTERCONNECT SLICE_84/F1 SLICE_53/A1 (1004:1160:1316)(1004:1160:1316)) + (INTERCONNECT SLICE_84/F1 SLICE_55/C1 (807:958:1110)(807:958:1110)) + (INTERCONNECT SLICE_84/F1 SLICE_65/A1 (740:867:995)(740:867:995)) + (INTERCONNECT SLICE_84/F1 SLICE_84/D0 (525:584:643)(525:584:643)) + (INTERCONNECT wb_dati_5_1_iv_0_0_o2\[5\]\/SLICE_59/OFX0 SLICE_53/D0 (531:586:641) + (531:586:641)) + (INTERCONNECT wb_dati_5_1_iv_0_0_o2\[5\]\/SLICE_59/OFX0 SLICE_54/C1 (542:652:762) + (542:652:762)) (INTERCONNECT SLICE_53/F1 SLICE_53/DI1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_53/F0 SLICE_53/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_53/Q0 SLICE_73/D1 (523:578:633)(523:578:633)) + (INTERCONNECT SLICE_53/Q0 SLICE_86/D0 (533:592:652)(533:592:652)) (INTERCONNECT SLICE_53/Q0 - ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI2in (1084:1193:1303) - (1084:1193:1303)) - (INTERCONNECT SLICE_53/Q1 SLICE_86/C0 (537:644:751)(537:644:751)) - (INTERCONNECT SLICE_53/Q1 - ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI3in (1084:1193:1303) - (1084:1193:1303)) - (INTERCONNECT SLICE_54/Q0 SLICE_54/A1 (733:853:974)(733:853:974)) - (INTERCONNECT SLICE_54/Q0 - ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI4in (1236:1368:1501) + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI2in (1236:1368:1501) (1236:1368:1501)) - (INTERCONNECT SLICE_67/F1 SLICE_54/D0 (523:573:623)(523:573:623)) - (INTERCONNECT SLICE_86/F0 SLICE_54/B0 (765:883:1001)(765:883:1001)) + (INTERCONNECT SLICE_53/Q1 SLICE_111/A0 (743:868:993)(743:868:993)) + (INTERCONNECT SLICE_53/Q1 + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI3in (643:706:769) + (643:706:769)) + (INTERCONNECT SLICE_54/Q0 SLICE_54/D1 (523:578:633)(523:578:633)) + (INTERCONNECT SLICE_54/Q0 + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI4in (650:720:791) + (650:720:791)) + (INTERCONNECT SLICE_65/F1 SLICE_54/C0 (1127:1301:1476)(1127:1301:1476)) + (INTERCONNECT SLICE_111/F0 SLICE_54/B0 (765:883:1001)(765:883:1001)) (INTERCONNECT SLICE_54/F1 SLICE_54/DI1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_54/F0 SLICE_54/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_54/Q1 SLICE_85/C0 (1170:1341:1513)(1170:1341:1513)) + (INTERCONNECT SLICE_54/Q1 SLICE_81/A0 (1434:1625:1817)(1434:1625:1817)) (INTERCONNECT SLICE_54/Q1 - ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI5in (1603:1765:1928) - (1603:1765:1928)) - (INTERCONNECT SLICE_77/F0 SLICE_55/D1 (520:573:626)(520:573:626)) - (INTERCONNECT SLICE_76/F0 SLICE_55/C1 (534:639:744)(534:639:744)) - (INTERCONNECT SLICE_87/F0 SLICE_55/B1 (765:883:1001)(765:883:1001)) - (INTERCONNECT SLICE_66/F0 SLICE_55/A1 (1104:1258:1413)(1104:1258:1413)) - (INTERCONNECT SLICE_85/F0 SLICE_55/A0 (733:848:964)(733:848:964)) + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI5in (977:1082:1188) + (977:1082:1188)) + (INTERCONNECT SLICE_74/F0 SLICE_55/D1 (520:573:626)(520:573:626)) + (INTERCONNECT SLICE_82/F0 SLICE_55/B1 (508:600:693)(508:600:693)) + (INTERCONNECT SLICE_104/F0 SLICE_55/A1 (735:856:978)(735:856:978)) + (INTERCONNECT SLICE_104/F0 SLICE_73/C1 (536:647:758)(536:647:758)) + (INTERCONNECT SLICE_81/F0 SLICE_55/A0 (999:1149:1299)(999:1149:1299)) (INTERCONNECT SLICE_55/F1 SLICE_55/DI1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_55/F0 SLICE_55/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_55/Q0 SLICE_66/B0 (765:888:1011)(765:888:1011)) + (INTERCONNECT SLICE_55/Q0 SLICE_82/A0 (1110:1265:1420)(1110:1265:1420)) (INTERCONNECT SLICE_55/Q0 - ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI6in (1236:1368:1501) - (1236:1368:1501)) - (INTERCONNECT SLICE_55/Q1 SLICE_97/C0 (1129:1309:1490)(1129:1309:1490)) + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI6in (1344:1479:1615) + (1344:1479:1615)) + (INTERCONNECT SLICE_55/Q1 SLICE_91/B0 (1139:1298:1457)(1139:1298:1457)) (INTERCONNECT SLICE_55/Q1 - ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI7in (1339:1476:1613) - (1339:1476:1613)) - (INTERCONNECT SLICE_107/F0 SLICE_56/C0 (536:647:758)(536:647:758)) - (INTERCONNECT SLICE_107/F0 SLICE_57/B0 (1033:1191:1350)(1033:1191:1350)) - (INTERCONNECT SLICE_56/F1 SLICE_56/B0 (508:600:693)(508:600:693)) - (INTERCONNECT SLICE_56/Q0 SLICE_56/A0 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_56/Q0 SLICE_92/D1 (871:967:1064)(871:967:1064)) - (INTERCONNECT SLICE_56/Q0 SLICE_121/B1 (1113:1277:1442)(1113:1277:1442)) + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI7in (909:1006:1104) + (909:1006:1104)) + (INTERCONNECT SLICE_58/F1 SLICE_56/A1 (736:854:973)(736:854:973)) + (INTERCONNECT SLICE_58/F1 SLICE_58/B0 (765:889:1013)(765:889:1013)) + (INTERCONNECT SLICE_57/F1 SLICE_56/D0 (967:1066:1166)(967:1066:1166)) + (INTERCONNECT SLICE_57/F1 SLICE_57/C0 (280:362:445)(280:362:445)) + (INTERCONNECT SLICE_56/F1 SLICE_56/C0 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_56/Q0 SLICE_56/A0 (481:575:669)(481:575:669)) + (INTERCONNECT SLICE_56/Q0 SLICE_89/D1 (525:582:639)(525:582:639)) + (INTERCONNECT SLICE_56/Q0 SLICE_121/A1 (735:857:980)(735:857:980)) (INTERCONNECT SLICE_56/F0 SLICE_56/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_75/F1 SLICE_57/C0 (280:362:445)(280:362:445)) - (INTERCONNECT SLICE_75/F1 SLICE_75/B0 (511:606:702)(511:606:702)) - (INTERCONNECT SLICE_57/Q0 SLICE_57/A0 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_57/Q0 SLICE_57/D0 (523:578:633)(523:578:633)) (INTERCONNECT SLICE_57/Q0 ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBRSTIin - (1614:1765:1916)(1614:1765:1916)) + (1424:1572:1720)(1424:1572:1720)) + (INTERCONNECT SLICE_94/F0 SLICE_57/A0 (1104:1258:1413)(1104:1258:1413)) (INTERCONNECT SLICE_57/F0 SLICE_57/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_82/Q0 SLICE_58/C0 (905:1049:1193)(905:1049:1193)) - (INTERCONNECT SLICE_63/F0 SLICE_58/A0 (733:848:964)(733:848:964)) + (INTERCONNECT SLICE_70/F1 SLICE_58/D0 (523:573:623)(523:573:623)) (INTERCONNECT SLICE_58/F0 SLICE_58/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_86/F1 wb_dati_5_1_iv_0_o3\[5\]\/SLICE_59/B1 (776:902:1028) - (776:902:1028)) - (INTERCONNECT SLICE_86/F1 wb_dati_5_1_iv_0_o3\[5\]\/SLICE_59/B0 (776:902:1028) - (776:902:1028)) - (INTERCONNECT SLICE_86/F1 SLICE_86/D0 (523:579:635)(523:579:635)) - (INTERCONNECT SLICE_76/F1 wb_dati_5_1_iv_0_o3\[5\]\/SLICE_59/A1 (733:854:976) - (733:854:976)) - (INTERCONNECT SLICE_76/F1 SLICE_76/C0 (280:362:445)(280:362:445)) - (INTERCONNECT SLICE_110/F0 wb_dati_5_1_iv_0_o3\[5\]\/SLICE_59/C0 (536:647:758) - (536:647:758)) - (INTERCONNECT SLICE_110/F0 SLICE_91/A1 (1365:1552:1740)(1365:1552:1740)) - (INTERCONNECT SLICE_80/Q1 SLICE_60/A1 (1501:1698:1895)(1501:1698:1895)) - (INTERCONNECT SLICE_74/F0 SLICE_60/C0 (802:947:1093)(802:947:1093)) - (INTERCONNECT SLICE_74/F0 SLICE_61/C1 (536:647:758)(536:647:758)) - (INTERCONNECT SLICE_60/F1 SLICE_60/B0 (765:889:1013)(765:889:1013)) - (INTERCONNECT SLICE_60/F1 SLICE_81/A0 (736:854:973)(736:854:973)) - (INTERCONNECT SLICE_60/F0 SLICE_94/B1 (508:600:693)(508:600:693)) - (INTERCONNECT SLICE_61/F1 SLICE_61/D0 (520:573:626)(520:573:626)) - (INTERCONNECT SLICE_61/F0 SLICE_94/D0 (523:573:623)(523:573:623)) - (INTERCONNECT SLICE_62/F1 SLICE_62/B0 (776:902:1028)(776:902:1028)) - (INTERCONNECT SLICE_62/F1 SLICE_106/B1 (776:902:1028)(776:902:1028)) - (INTERCONNECT SLICE_62/F1 SLICE_106/B0 (511:606:702)(511:606:702)) - (INTERCONNECT SLICE_62/F0 SLICE_63/D0 (520:573:626)(520:573:626)) - (INTERCONNECT SLICE_95/F0 SLICE_63/D1 (520:573:626)(520:573:626)) - (INTERCONNECT SLICE_105/F0 SLICE_63/A1 (1174:1336:1498)(1174:1336:1498)) - (INTERCONNECT SLICE_63/F1 SLICE_63/C0 (277:356:436)(277:356:436)) - (INTERCONNECT Din\[6\]_I/PADDI SLICE_64/D1 (2389:2578:2768)(2389:2578:2768)) - (INTERCONNECT Din\[6\]_I/PADDI SLICE_99/C0 (2052:2266:2481)(2052:2266:2481)) - (INTERCONNECT Din\[6\]_I/PADDI SLICE_100/A1 (2251:2476:2701)(2251:2476:2701)) - (INTERCONNECT Din\[6\]_I/PADDI SLICE_119/B1 (2283:2510:2738)(2283:2510:2738)) - (INTERCONNECT Din\[6\]_I/PADDI SLICE_120/D0 (2411:2602:2794)(2411:2602:2794)) - (INTERCONNECT Din\[6\]_I/PADDI RD\[6\]_MGIOL/OPOS (3256:3521:3787)(3256:3521:3787)) + (INTERCONNECT SLICE_73/F1 wb_dati_5_1_iv_0_0_o2\[5\]\/SLICE_59/C1 (544:659:775) + (544:659:775)) + (INTERCONNECT SLICE_73/F1 SLICE_73/B0 (511:606:702)(511:606:702)) + (INTERCONNECT SLICE_72/F0 wb_dati_5_1_iv_0_0_o2\[5\]\/SLICE_59/A1 (738:862:987) + (738:862:987)) + (INTERCONNECT SLICE_72/F0 wb_dati_5_1_iv_0_0_o2\[5\]\/SLICE_59/A0 (738:862:987) + (738:862:987)) + (INTERCONNECT SLICE_72/F0 SLICE_111/C0 (534:645:756)(534:645:756)) + (INTERCONNECT SLICE_85/F1 wb_dati_5_1_iv_0_0_o2\[5\]\/SLICE_59/C0 (539:653:767) + (539:653:767)) + (INTERCONNECT SLICE_85/F1 SLICE_85/C0 (280:362:445)(280:362:445)) + (INTERCONNECT SLICE_85/F1 SLICE_87/B0 (1467:1664:1861)(1467:1664:1861)) + (INTERCONNECT SLICE_67/F0 wb_adr_5_i_0_1\[0\]\/SLICE_60/C1 (534:645:756) + (534:645:756)) + (INTERCONNECT SLICE_67/F0 SLICE_67/A1 (733:854:976)(733:854:976)) + (INTERCONNECT SLICE_97/F1 wb_adr_5_i_0_1\[0\]\/SLICE_60/A1 (1004:1160:1316) + (1004:1160:1316)) + (INTERCONNECT SLICE_97/F1 SLICE_84/C0 (1236:1417:1598)(1236:1417:1598)) + (INTERCONNECT SLICE_97/F1 SLICE_97/D0 (525:584:643)(525:584:643)) + (INTERCONNECT SLICE_105/F1 wb_adr_5_i_0_1\[0\]\/SLICE_60/B0 (1475:1670:1865) + (1475:1670:1865)) + (INTERCONNECT SLICE_105/F1 SLICE_61/A1 (1443:1635:1828)(1443:1635:1828)) + (INTERCONNECT SLICE_105/F1 SLICE_70/C1 (1233:1414:1595)(1233:1414:1595)) + (INTERCONNECT SLICE_105/F1 SLICE_99/D1 (1597:1755:1914)(1597:1755:1914)) + (INTERCONNECT wb_adr_5_i_0_1\[0\]\/SLICE_60/OFX0 SLICE_67/B1 (762:883:1004) + (762:883:1004)) + (INTERCONNECT SLICE_61/F0 SLICE_61/D1 (520:573:626)(520:573:626)) + (INTERCONNECT SLICE_61/F1 SLICE_91/D0 (789:873:958)(789:873:958)) + (INTERCONNECT SLICE_62/F0 SLICE_69/D0 (792:879:967)(792:879:967)) + (INTERCONNECT SLICE_62/F0 SLICE_101/D0 (533:593:654)(533:593:654)) + (INTERCONNECT SLICE_119/F0 SLICE_63/B1 (1209:1376:1544)(1209:1376:1544)) + (INTERCONNECT SLICE_119/F0 SLICE_96/A0 (1070:1231:1392)(1070:1231:1392)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_63/A1 (2563:2820:3078)(2563:2820:3078)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_92/D0 (3109:3367:3626)(3109:3367:3626)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_96/A1 (2611:2866:3121)(2611:2866:3121)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_119/A1 (3319:3643:3967)(3319:3643:3967)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_120/B0 (3792:4157:4522)(3792:4157:4522)) + (INTERCONNECT Din\[6\]_I/PADDI RD\[6\]_MGIOL/OPOS (3246:3509:3773)(3246:3509:3773)) (INTERCONNECT Din\[6\]_I/PADDI Din\[6\]_MGIOL/DI (424:441:459)(424:441:459)) - (INTERCONNECT SLICE_119/F0 SLICE_64/C1 (537:645:753)(537:645:753)) - (INTERCONNECT SLICE_119/F0 SLICE_100/B0 (765:889:1013)(765:889:1013)) - (INTERCONNECT SLICE_64/F0 SLICE_80/D0 (266:290:315)(266:290:315)) - (INTERCONNECT SLICE_110/F1 SLICE_65/B1 (765:883:1001)(765:883:1001)) - (INTERCONNECT SLICE_70/F1 SLICE_65/A1 (730:848:967)(730:848:967)) - (INTERCONNECT SLICE_70/F0 SLICE_65/D0 (523:579:635)(523:579:635)) - (INTERCONNECT SLICE_70/F0 SLICE_70/B1 (765:889:1013)(765:889:1013)) - (INTERCONNECT SLICE_65/F1 SLICE_65/B0 (508:600:693)(508:600:693)) - (INTERCONNECT SLICE_67/F0 SLICE_65/A0 (733:854:976)(733:854:976)) - (INTERCONNECT SLICE_67/F0 SLICE_67/B1 (765:889:1013)(765:889:1013)) - (INTERCONNECT SLICE_101/F0 SLICE_66/A0 (1174:1336:1498)(1174:1336:1498)) - (INTERCONNECT SLICE_104/F0 SLICE_68/D0 (520:573:626)(520:573:626)) - (INTERCONNECT SLICE_68/F1 SLICE_68/A0 (733:854:976)(733:854:976)) - (INTERCONNECT SLICE_68/F1 SLICE_105/B1 (1102:1265:1429)(1102:1265:1429)) - (INTERCONNECT SLICE_69/F0 SLICE_69/B1 (762:883:1004)(762:883:1004)) - (INTERCONNECT SLICE_69/F1 SLICE_91/A0 (999:1149:1299)(999:1149:1299)) - (INTERCONNECT SLICE_89/F1 SLICE_70/C1 (534:645:756)(534:645:756)) - (INTERCONNECT SLICE_89/F1 SLICE_89/C0 (280:362:445)(280:362:445)) - (INTERCONNECT SLICE_71/F0 SLICE_71/D1 (520:573:626)(520:573:626)) - (INTERCONNECT SLICE_91/F1 SLICE_71/C1 (544:659:775)(544:659:775)) - (INTERCONNECT SLICE_91/F1 SLICE_91/B0 (511:606:702)(511:606:702)) - (INTERCONNECT SLICE_95/F1 SLICE_71/B1 (1036:1194:1353)(1036:1194:1353)) - (INTERCONNECT SLICE_95/F1 SLICE_86/C1 (546:664:783)(546:664:783)) - (INTERCONNECT SLICE_95/F1 SLICE_95/D0 (525:584:643)(525:584:643)) - (INTERCONNECT SLICE_113/F1 SLICE_71/A1 (733:854:976)(733:854:976)) - (INTERCONNECT SLICE_113/F1 SLICE_73/A1 (749:875:1002)(749:875:1002)) - (INTERCONNECT SLICE_113/F1 SLICE_86/A1 (749:875:1002)(749:875:1002)) - (INTERCONNECT SLICE_78/F1 SLICE_72/B1 (1209:1376:1544)(1209:1376:1544)) - (INTERCONNECT SLICE_78/F1 SLICE_78/C0 (280:362:445)(280:362:445)) - (INTERCONNECT SLICE_72/F1 SLICE_83/C0 (531:639:747)(531:639:747)) - (INTERCONNECT SLICE_73/F0 SLICE_73/C1 (531:639:747)(531:639:747)) - (INTERCONNECT SLICE_74/F1 SLICE_74/C0 (280:362:445)(280:362:445)) - (INTERCONNECT SLICE_74/F1 SLICE_78/A1 (736:854:973)(736:854:973)) - (INTERCONNECT SLICE_79/F1 SLICE_78/D1 (528:584:640)(528:584:640)) - (INTERCONNECT SLICE_79/F1 SLICE_79/C0 (282:367:453)(282:367:453)) - (INTERCONNECT SLICE_79/F1 SLICE_88/A1 (735:859:984)(735:859:984)) - (INTERCONNECT SLICE_78/F0 nRRAS_MGIOL/OPOS (1445:1584:1723)(1445:1584:1723)) + (INTERCONNECT SLICE_63/F0 SLICE_76/B0 (762:883:1004)(762:883:1004)) + (INTERCONNECT SLICE_97/F0 SLICE_64/A0 (730:848:967)(730:848:967)) + (INTERCONNECT SLICE_64/F0 SLICE_85/B0 (1206:1370:1535)(1206:1370:1535)) + (INTERCONNECT SLICE_65/F0 SLICE_65/C1 (282:367:453)(282:367:453)) + (INTERCONNECT SLICE_65/F0 SLICE_67/D1 (535:598:662)(535:598:662)) + (INTERCONNECT SLICE_65/F0 SLICE_73/A1 (738:859:981)(738:859:981)) + (INTERCONNECT SLICE_102/F0 SLICE_66/D0 (266:290:315)(266:290:315)) + (INTERCONNECT SLICE_66/F1 SLICE_66/C0 (280:362:445)(280:362:445)) + (INTERCONNECT SLICE_66/F1 SLICE_107/B0 (1102:1265:1429)(1102:1265:1429)) + (INTERCONNECT SLICE_68/F1 SLICE_75/D0 (266:290:315)(266:290:315)) + (INTERCONNECT SLICE_69/F0 SLICE_69/C1 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_117/F0 SLICE_69/A1 (730:848:967)(730:848:967)) + (INTERCONNECT SLICE_69/F1 SLICE_101/C1 (534:639:744)(534:639:744)) + (INTERCONNECT SLICE_107/F1 SLICE_70/D1 (269:296:324)(269:296:324)) + (INTERCONNECT SLICE_107/F1 SLICE_93/D0 (526:579:632)(526:579:632)) + (INTERCONNECT SLICE_93/F1 SLICE_70/A1 (740:863:986)(740:863:986)) + (INTERCONNECT SLICE_94/F1 SLICE_71/D0 (523:579:635)(523:579:635)) + (INTERCONNECT SLICE_94/F1 SLICE_94/B0 (511:606:702)(511:606:702)) + (INTERCONNECT SLICE_72/F1 SLICE_72/C0 (280:362:445)(280:362:445)) + (INTERCONNECT SLICE_72/F1 SLICE_93/D1 (533:593:654)(533:593:654)) + (INTERCONNECT SLICE_88/F1 SLICE_72/A0 (481:577:673)(481:577:673)) + (INTERCONNECT SLICE_88/F1 SLICE_86/D1 (271:301:332)(271:301:332)) + (INTERCONNECT SLICE_88/F1 SLICE_88/C0 (282:367:453)(282:367:453)) + (INTERCONNECT SLICE_73/F0 SLICE_82/C0 (531:639:747)(531:639:747)) + (INTERCONNECT SLICE_76/Q1 SLICE_75/D1 (964:1060:1157)(964:1060:1157)) + (INTERCONNECT SLICE_103/F0 SLICE_75/C0 (879:1028:1178)(879:1028:1178)) + (INTERCONNECT SLICE_103/F0 SLICE_78/C0 (879:1028:1178)(879:1028:1178)) + (INTERCONNECT SLICE_75/F1 SLICE_75/B0 (511:606:702)(511:606:702)) + (INTERCONNECT SLICE_75/F1 SLICE_101/C0 (534:645:756)(534:645:756)) + (INTERCONNECT SLICE_106/F1 SLICE_75/A0 (1078:1238:1398)(1078:1238:1398)) + (INTERCONNECT SLICE_106/F1 SLICE_78/A0 (1078:1238:1398)(1078:1238:1398)) + (INTERCONNECT SLICE_75/F0 nRWE_MGIOL/OPOS (906:1001:1097)(906:1001:1097)) + (INTERCONNECT SLICE_76/F1 SLICE_76/C0 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_78/F1 SLICE_78/D0 (523:579:635)(523:579:635)) + (INTERCONNECT SLICE_78/F1 SLICE_101/D1 (269:296:324)(269:296:324)) + (INTERCONNECT SLICE_83/F0 SLICE_78/B0 (772:897:1023)(772:897:1023)) + (INTERCONNECT SLICE_78/F0 nRCS_MGIOL/OPOS (1081:1188:1296)(1081:1188:1296)) + (INTERCONNECT SLICE_79/F0 RA\[10\]_MGIOL/LSR (1356:1491:1626)(1356:1491:1626)) + (INTERCONNECT Din\[3\]_MGIOL/IN SLICE_80/D1 (1043:1151:1260)(1043:1151:1260)) + (INTERCONNECT Din\[6\]_MGIOL/IN SLICE_80/C1 (1161:1328:1496)(1161:1328:1496)) + (INTERCONNECT Din\[2\]_MGIOL/IN SLICE_80/B1 (1392:1572:1753)(1392:1572:1753)) + (INTERCONNECT Din\[5\]_MGIOL/IN SLICE_80/A1 (926:1065:1204)(926:1065:1204)) + (INTERCONNECT Din\[4\]_MGIOL/IN SLICE_80/D0 (709:775:841)(709:775:841)) (INTERCONNECT SLICE_80/F1 SLICE_80/C0 (277:356:436)(277:356:436)) - (INTERCONNECT SLICE_90/F0 SLICE_81/D0 (894:983:1072)(894:983:1072)) + (INTERCONNECT Din\[0\]_MGIOL/IN SLICE_80/B0 (1392:1572:1753)(1392:1572:1753)) + (INTERCONNECT SLICE_90/F0 SLICE_80/A0 (999:1149:1299)(999:1149:1299)) + (INTERCONNECT SLICE_98/F1 SLICE_81/C1 (280:362:445)(280:362:445)) + (INTERCONNECT SLICE_98/F1 SLICE_98/B0 (765:889:1013)(765:889:1013)) + (INTERCONNECT SLICE_118/F1 SLICE_81/B1 (511:606:702)(511:606:702)) + (INTERCONNECT SLICE_118/F1 SLICE_97/A0 (1070:1231:1392)(1070:1231:1392)) + (INTERCONNECT SLICE_84/F0 SLICE_81/D0 (520:573:626)(520:573:626)) (INTERCONNECT SLICE_81/F1 SLICE_81/C0 (280:362:445)(280:362:445)) - (INTERCONNECT SLICE_81/F1 SLICE_83/B0 (765:889:1013)(765:889:1013)) - (INTERCONNECT SLICE_108/F0 SLICE_81/B0 (1037:1190:1343)(1037:1190:1343)) - (INTERCONNECT SLICE_108/F0 SLICE_83/D0 (795:880:965)(795:880:965)) - (INTERCONNECT SLICE_81/F0 nRWE_MGIOL/OPOS (906:1001:1097)(906:1001:1097)) - (INTERCONNECT SLICE_82/F0 SLICE_82/CE (539:596:653)(539:596:653)) - (INTERCONNECT SLICE_83/F1 SLICE_83/A0 (733:854:976)(733:854:976)) - (INTERCONNECT SLICE_83/F1 SLICE_94/C1 (537:645:753)(537:645:753)) - (INTERCONNECT SLICE_83/F0 nRCS_MGIOL/OPOS (1375:1506:1638)(1375:1506:1638)) - (INTERCONNECT Din\[1\]_MGIOL/IN SLICE_84/D1 (1043:1151:1260)(1043:1151:1260)) - (INTERCONNECT Din\[3\]_MGIOL/IN SLICE_84/C1 (727:855:984)(727:855:984)) - (INTERCONNECT Din\[4\]_MGIOL/IN SLICE_84/B1 (958:1099:1241)(958:1099:1241)) - (INTERCONNECT Din\[5\]_MGIOL/IN SLICE_84/A1 (1549:1746:1944)(1549:1746:1944)) - (INTERCONNECT SLICE_93/F0 SLICE_84/D0 (789:873:958)(789:873:958)) - (INTERCONNECT SLICE_84/F1 SLICE_84/C0 (277:356:436)(277:356:436)) - (INTERCONNECT Din\[7\]_MGIOL/IN SLICE_84/B0 (1756:1968:2180)(1756:1968:2180)) - (INTERCONNECT Din\[6\]_MGIOL/IN SLICE_84/A0 (1549:1746:1944)(1549:1746:1944)) - (INTERCONNECT SLICE_101/F1 SLICE_85/C1 (534:645:756)(534:645:756)) - (INTERCONNECT SLICE_101/F1 SLICE_101/D0 (523:579:635)(523:579:635)) - (INTERCONNECT SLICE_102/F1 SLICE_85/A1 (744:867:991)(744:867:991)) - (INTERCONNECT SLICE_102/F1 SLICE_101/A0 (479:572:665)(479:572:665)) - (INTERCONNECT SLICE_102/F1 SLICE_102/A0 (744:867:991)(744:867:991)) - (INTERCONNECT SLICE_85/F1 SLICE_85/B0 (511:606:702)(511:606:702)) - (INTERCONNECT SLICE_85/F1 SLICE_86/A0 (1002:1155:1308)(1002:1155:1308)) - (INTERCONNECT SLICE_89/F0 SLICE_85/A0 (999:1149:1299)(999:1149:1299)) - (INTERCONNECT SLICE_88/F0 RA\[10\]_MGIOL/LSR (1791:1969:2147)(1791:1969:2147)) - (INTERCONNECT SLICE_90/F1 SLICE_90/C0 (277:356:436)(277:356:436)) - (INTERCONNECT ufmefb\/EFBInst_0/WBACKO SLICE_92/C0 (1612:1807:2003) - (1612:1807:2003)) - (INTERCONNECT ufmefb\/EFBInst_0/WBACKO SLICE_104/D0 (1965:2137:2309) - (1965:2137:2309)) - (INTERCONNECT SLICE_92/F1 SLICE_92/B0 (762:883:1004)(762:883:1004)) - (INTERCONNECT Din\[0\]_MGIOL/IN SLICE_93/D0 (1514:1658:1802)(1514:1658:1802)) - (INTERCONNECT Din\[2\]_MGIOL/IN SLICE_93/C0 (1161:1328:1496)(1161:1328:1496)) - (INTERCONNECT SLICE_93/F1 SLICE_93/B0 (508:600:693)(508:600:693)) - (INTERCONNECT SLICE_114/F0 SLICE_93/A0 (1174:1336:1498)(1174:1336:1498)) - (INTERCONNECT SLICE_94/F0 SLICE_94/D1 (520:573:626)(520:573:626)) - (INTERCONNECT SLICE_94/F1 nRCAS_MGIOL/OPOS (1337:1468:1599)(1337:1468:1599)) - (INTERCONNECT SLICE_96/F1 SLICE_96/D0 (520:573:626)(520:573:626)) - (INTERCONNECT SLICE_109/F0 SLICE_96/C0 (277:356:436)(277:356:436)) - (INTERCONNECT SLICE_98/F1 SLICE_98/B0 (508:600:693)(508:600:693)) - (INTERCONNECT SLICE_99/F1 SLICE_99/B0 (508:600:693)(508:600:693)) - (INTERCONNECT Din\[2\]_I/PADDI SLICE_99/A0 (1735:1912:2089)(1735:1912:2089)) - (INTERCONNECT Din\[2\]_I/PADDI SLICE_119/B0 (2137:2348:2560)(2137:2348:2560)) - (INTERCONNECT Din\[2\]_I/PADDI RD\[2\]_MGIOL/OPOS (2703:2924:3145)(2703:2924:3145)) + (INTERCONNECT SLICE_81/F1 SLICE_111/B0 (768:889:1010)(768:889:1010)) + (INTERCONNECT SLICE_102/F1 SLICE_82/B1 (772:897:1023)(772:897:1023)) + (INTERCONNECT SLICE_82/F1 SLICE_82/B0 (762:883:1004)(762:883:1004)) + (INTERCONNECT SLICE_86/F1 SLICE_86/B0 (762:883:1004)(762:883:1004)) + (INTERCONNECT SLICE_88/F0 SLICE_87/D0 (530:587:645)(530:587:645)) + (INTERCONNECT SLICE_89/F1 SLICE_89/D0 (520:573:626)(520:573:626)) + (INTERCONNECT ufmefb\/EFBInst_0/WBACKO SLICE_89/A0 (1365:1544:1724) + (1365:1544:1724)) + (INTERCONNECT ufmefb\/EFBInst_0/WBACKO SLICE_102/C0 (1166:1335:1504) + (1166:1335:1504)) + (INTERCONNECT Din\[1\]_MGIOL/IN SLICE_90/D0 (1150:1262:1375)(1150:1262:1375)) + (INTERCONNECT Din\[7\]_MGIOL/IN SLICE_90/C0 (1607:1801:1995)(1607:1801:1995)) + (INTERCONNECT SLICE_90/F1 SLICE_90/B0 (508:600:693)(508:600:693)) + (INTERCONNECT SLICE_112/F0 SLICE_90/A0 (1174:1336:1498)(1174:1336:1498)) + (INTERCONNECT SLICE_92/F1 SLICE_92/C0 (277:356:436)(277:356:436)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_92/B0 (2094:2308:2523)(2094:2308:2523)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_119/A0 (1735:1912:2089)(1735:1912:2089)) + (INTERCONNECT Din\[2\]_I/PADDI RD\[2\]_MGIOL/OPOS (2067:2224:2382)(2067:2224:2382)) (INTERCONNECT Din\[2\]_I/PADDI Din\[2\]_MGIOL/DI (544:554:565)(544:554:565)) - (INTERCONNECT Din\[7\]_I/PADDI SLICE_100/C1 (2299:2553:2808)(2299:2553:2808)) - (INTERCONNECT Din\[7\]_I/PADDI SLICE_112/B1 (2536:2804:3072)(2536:2804:3072)) - (INTERCONNECT Din\[7\]_I/PADDI SLICE_119/A1 (3966:4358:4750)(3966:4358:4750)) - (INTERCONNECT Din\[7\]_I/PADDI RD\[7\]_MGIOL/OPOS (3509:3815:4121)(3509:3815:4121)) + (INTERCONNECT SLICE_93/F0 SLICE_93/A1 (476:566:656)(476:566:656)) + (INTERCONNECT SLICE_95/F1 SLICE_95/C0 (277:356:436)(277:356:436)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_96/C1 (2385:2636:2887)(2385:2636:2887)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_109/D1 (2380:2576:2773)(2380:2576:2773)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_119/D1 (3071:3334:3597)(3071:3334:3597)) + (INTERCONNECT Din\[7\]_I/PADDI RD\[7\]_MGIOL/OPOS (2855:3093:3332)(2855:3093:3332)) (INTERCONNECT Din\[7\]_I/PADDI Din\[7\]_MGIOL/DI (424:441:459)(424:441:459)) - (INTERCONNECT SLICE_112/F0 SLICE_100/D0 (266:290:315)(266:290:315)) - (INTERCONNECT SLICE_103/F1 SLICE_103/B0 (508:600:693)(508:600:693)) - (INTERCONNECT SLICE_111/F0 RDQMH_I/PADDO (1384:1542:1701)(1384:1542:1701)) - (INTERCONNECT SLICE_111/F1 RDQML_I/PADDO (936:1038:1140)(936:1038:1140)) - (INTERCONNECT SLICE_114/F1 RA\[6\]_I/PADDO (1470:1661:1852)(1470:1661:1852)) - (INTERCONNECT SLICE_115/F0 RA\[8\]_I/PADDO (1279:1433:1587)(1279:1433:1587)) - (INTERCONNECT SLICE_115/F1 RA\[9\]_I/PADDO (1454:1620:1786)(1454:1620:1786)) - (INTERCONNECT SLICE_116/F0 RA\[0\]_I/PADDO (1106:1265:1425)(1106:1265:1425)) - (INTERCONNECT SLICE_116/F1 RA\[7\]_I/PADDO (1493:1677:1861)(1493:1677:1861)) - (INTERCONNECT SLICE_117/F0 RA\[1\]_I/PADDO (1106:1265:1425)(1106:1265:1425)) - (INTERCONNECT SLICE_117/F1 RA\[5\]_I/PADDO (1362:1545:1728)(1362:1545:1728)) - (INTERCONNECT SLICE_118/F0 RA\[2\]_I/PADDO (1362:1545:1728)(1362:1545:1728)) - (INTERCONNECT SLICE_118/F1 RA\[4\]_I/PADDO (1362:1545:1728)(1362:1545:1728)) - (INTERCONNECT CROW\[1\]_I/PADDI SLICE_120/C1 (1877:2086:2296)(1877:2086:2296)) - (INTERCONNECT SLICE_120/F0 RA\[11\]_MGIOL/OPOS (1408:1550:1693)(1408:1550:1693)) - (INTERCONNECT SLICE_120/F1 RBA\[1\]_MGIOL/OPOS (1337:1468:1599)(1337:1468:1599)) - (INTERCONNECT ufmefb\/EFBInst_0/WBDATO0 SLICE_122/C1 (1607:1801:1995) - (1607:1801:1995)) - (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_I/PADDO (2169:2344:2519)(2169:2344:2519)) + (INTERCONNECT SLICE_109/F0 SLICE_96/C0 (531:639:747)(531:639:747)) + (INTERCONNECT SLICE_99/F0 SLICE_99/B1 (762:883:1004)(762:883:1004)) + (INTERCONNECT SLICE_100/F1 SLICE_100/A0 (730:848:967)(730:848:967)) + (INTERCONNECT SLICE_101/F0 SLICE_101/A1 (730:848:967)(730:848:967)) + (INTERCONNECT SLICE_101/F1 nRCAS_MGIOL/OPOS (1337:1468:1599)(1337:1468:1599)) + (INTERCONNECT SLICE_106/F0 LED_I/PADDO (1367:1504:1642)(1367:1504:1642)) + (INTERCONNECT SLICE_108/F0 RDQMH_I/PADDO (1090:1224:1359)(1090:1224:1359)) + (INTERCONNECT SLICE_108/F1 RDQML_I/PADDO (1041:1147:1254)(1041:1147:1254)) + (INTERCONNECT ufmefb\/EFBInst_0/WBDATO0 SLICE_111/C1 (727:855:984)(727:855:984)) + (INTERCONNECT SLICE_112/F1 RA\[2\]_I/PADDO (1470:1661:1852)(1470:1661:1852)) + (INTERCONNECT SLICE_113/F0 RA\[0\]_I/PADDO (1710:1933:2156)(1710:1933:2156)) + (INTERCONNECT SLICE_113/F1 RA\[8\]_I/PADDO (1417:1586:1756)(1417:1586:1756)) + (INTERCONNECT SLICE_114/F0 RA\[1\]_I/PADDO (1362:1545:1728)(1362:1545:1728)) + (INTERCONNECT SLICE_114/F1 RA\[3\]_I/PADDO (1362:1545:1728)(1362:1545:1728)) + (INTERCONNECT SLICE_115/F0 RA\[4\]_I/PADDO (1578:1771:1964)(1578:1771:1964)) + (INTERCONNECT SLICE_115/F1 RA\[9\]_I/PADDO (1346:1504:1662)(1346:1504:1662)) + (INTERCONNECT SLICE_116/F0 RA\[5\]_I/PADDO (1574:1761:1949)(1574:1761:1949)) + (INTERCONNECT SLICE_116/F1 RA\[7\]_I/PADDO (1689:1907:2125)(1689:1907:2125)) + (INTERCONNECT CROW\[1\]_I/PADDI SLICE_120/B1 (1744:1935:2126)(1744:1935:2126)) + (INTERCONNECT SLICE_120/F0 RA\[11\]_MGIOL/OPOS (1445:1584:1723)(1445:1584:1723)) + (INTERCONNECT SLICE_120/F1 RBA\[1\]_MGIOL/OPOS (1753:1932:2111)(1753:1932:2111)) + (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_I/PADDO (2098:2261:2425)(2098:2261:2425)) (INTERCONNECT RD\[0\]_MGIOL/IOLDO RD\[0\]_I/IOLDO (30:36:43)(30:36:43)) (INTERCONNECT nRCAS_MGIOL/IOLDO nRCAS_I/IOLDO (9:36:63)(9:36:63)) (INTERCONNECT nRRAS_MGIOL/IOLDO nRRAS_I/IOLDO (9:36:63)(9:36:63)) (INTERCONNECT nRWE_MGIOL/IOLDO nRWE_I/IOLDO (30:36:43)(30:36:43)) + (INTERCONNECT RCLKout_MGIOL/IOLDO RCLKout_I/IOLDO (9:36:63)(9:36:63)) (INTERCONNECT nRCS_MGIOL/IOLDO nRCS_I/IOLDO (9:36:63)(9:36:63)) - (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_I/PADDO (2169:2344:2519)(2169:2344:2519)) + (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_I/PADDO (2632:2848:3064)(2632:2848:3064)) (INTERCONNECT RD\[7\]_MGIOL/IOLDO RD\[7\]_I/IOLDO (30:36:43)(30:36:43)) - (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_I/PADDO (2098:2261:2425)(2098:2261:2425)) + (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_I/PADDO (2169:2344:2519)(2169:2344:2519)) (INTERCONNECT RD\[6\]_MGIOL/IOLDO RD\[6\]_I/IOLDO (30:36:43)(30:36:43)) - (INTERCONNECT RD\[5\]_I/PADDI Dout\[5\]_I/PADDO (2693:2909:3126)(2693:2909:3126)) + (INTERCONNECT RD\[5\]_I/PADDI Dout\[5\]_I/PADDO (2098:2261:2425)(2098:2261:2425)) (INTERCONNECT RD\[5\]_MGIOL/IOLDO RD\[5\]_I/IOLDO (30:36:43)(30:36:43)) (INTERCONNECT RD\[4\]_I/PADDI Dout\[4\]_I/PADDO (2169:2344:2519)(2169:2344:2519)) (INTERCONNECT RD\[4\]_MGIOL/IOLDO RD\[4\]_I/IOLDO (30:36:43)(30:36:43)) - (INTERCONNECT RD\[3\]_I/PADDI Dout\[3\]_I/PADDO (2098:2261:2425)(2098:2261:2425)) + (INTERCONNECT RD\[3\]_I/PADDI Dout\[3\]_I/PADDO (2425:2623:2822)(2425:2623:2822)) (INTERCONNECT RD\[3\]_MGIOL/IOLDO RD\[3\]_I/IOLDO (30:36:43)(30:36:43)) - (INTERCONNECT RD\[2\]_I/PADDI Dout\[2\]_I/PADDO (2169:2344:2519)(2169:2344:2519)) + (INTERCONNECT RD\[2\]_I/PADDI Dout\[2\]_I/PADDO (2366:2547:2729)(2366:2547:2729)) (INTERCONNECT RD\[2\]_MGIOL/IOLDO RD\[2\]_I/IOLDO (30:36:43)(30:36:43)) (INTERCONNECT RD\[1\]_I/PADDI Dout\[1\]_I/PADDO (2098:2261:2425)(2098:2261:2425)) (INTERCONNECT RD\[1\]_MGIOL/IOLDO RD\[1\]_I/IOLDO (30:36:43)(30:36:43)) (INTERCONNECT RA\[11\]_MGIOL/IOLDO RA\[11\]_I/IOLDO (9:36:63)(9:36:63)) (INTERCONNECT RA\[10\]_MGIOL/IOLDO RA\[10\]_I/IOLDO (9:36:63)(9:36:63)) - (INTERCONNECT RBA\[1\]_MGIOL/IOLDO RBA\[1\]_I/IOLDO (9:36:63)(9:36:63)) + (INTERCONNECT RBA\[1\]_MGIOL/IOLDO RBA\[1\]_I/IOLDO (30:36:43)(30:36:43)) (INTERCONNECT RBA\[0\]_MGIOL/IOLDO RBA\[0\]_I/IOLDO (9:36:63)(9:36:63)) ) ) diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_vo.vo b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_vo.vo index e669911..879a0f0 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_vo.vo +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_vo.vo @@ -2,8 +2,8 @@ // Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454 // ldbanno -n Verilog -o RAM2GS_LCMXO2_640HC_impl1_vo.vo -w -neg -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd -// Netlist created on Thu Sep 21 05:39:43 2023 -// Netlist written on Thu Sep 21 05:40:09 2023 +// Netlist created on Sat Nov 18 02:05:52 2023 +// Netlist written on Sat Nov 18 02:06:21 2023 // Design is for device LCMXO2-640HC // Design is for package TQFP100 // Design is for performance grade 4 @@ -11,7 +11,8 @@ `timescale 1 ns / 1 ps module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, - RD, nRCS, RCLK, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML ); + RD, nRCS, RCLK, RCLKout, RCKE, nRWE, nRRAS, nRCAS, RDQMH, + RDQML ); input PHI2; input [9:0] MAin; input [1:0] CROW; @@ -21,7 +22,7 @@ module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, output LED; output [1:0] RBA; output [11:0] RA; - output nRCS, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML; + output nRCS, RCLKout, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML; inout [7:0] RD; wire \FS[0] , \FS_s[0] , RCLK_c, \FS_cry[0] , \FS[17] , \FS_s[17] , \FS_cry[16] , \FS[16] , \FS[15] , \FS_s[16] , \FS_s[15] , @@ -30,73 +31,85 @@ module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, \FS_cry[10] , \FS[10] , \FS[9] , \FS_s[10] , \FS_s[9] , \FS_cry[8] , \FS[8] , \FS[7] , \FS_s[8] , \FS_s[7] , \FS_cry[6] , \FS[6] , \FS[5] , \FS_s[6] , \FS_s[5] , \FS_cry[4] , \FS[4] , \FS[3] , \FS_s[4] , - \FS_s[3] , \FS_cry[2] , \FS[2] , \FS[1] , \FS_s[2] , \FS_s[1] , - \MAin_c[1] , un1_CmdEnable20_0_0_o3, ADSubmitted, CmdEnable17, N_524, - CmdEnable16, ADSubmitted_r_0_0, PHI2_c, N_518, N_594, C1Submitted, - C1Submitted_RNO, nCCAS_c, nCCAS_c_i, CASr, CASr2, CO0, \S[1] , - N_123_i, RASr2, N_345_i, N_593, CmdEnable_0_sqmuxa, un1_CmdEnable20_i, - CmdEnable, CmdEnable_s, \Din_c[1] , CmdLEDEN_4_u_i_0_a3_0_0, - CmdValid_2_i_o2_1_o3, CmdLEDEN, LEDEN, CmdLEDEN_4_u_i_0_0, N_531, - N_40_i, XOR8MEG18, CmdUFMShift, CmdUFMShift_3, CmdUFMWrite, - \Din_c[0] , N_462, CmdUFMWrite_3, N_213, \Din_c[3] , \Din_c[4] , - \Din_c[5] , CmdValid_r, CmdValid, \MAin_c[0] , N_36_fast, - CmdValid_fast, Cmdn8MEGEN, n8MEGEN, Cmdn8MEGEN_4_u_i_0_0, N_38_i, - nFWE_c, nFWE_c_i, nCRAS_c, FWEr, RD_1_i, nRCS_9_u_i_0_o2_1_RNIL2K71, - \IS[0] , N_351_i_i, N_267, \IS[1] , \IS[2] , N_348_i_i, N_344_i, - N_360_i, \IS[3] , N_350_i_i, \IS_i[0] , N_581, InitReady3_0_a3_1, - InitReady3, InitReady, N_757_0, \wb_dato[1] , LEDEN_6_i_m2_i_m2, - CmdValid_RNIOOBE2, LEDENe_0, Ready_fast, \CROW_c[0] , PHI2r2, PHI2r, - \RBAd_0[0] , PHI2r3, CBR, nCRAS_c_i_0, RASr, LED_c, nRowColSel, - \RowA[3] , \MAin_c[3] , RASr3, \RA_c[3] , N_216, Ready, - RCKEEN_8_u_0_1_0, RCKEEN_8_u_0_0_0, RCKEEN_8, RCKEEN, RCKE_2, RCKE_c, - m3_0_a2_0, Ready_0_sqmuxa_0_a2_4_a3_2, N_347, N_758_0, Ready_0_sqmuxa, - N_759_0, \RowAd_0[1] , \RowAd_0[0] , \RowA[0] , \RowA[1] , - \MAin_c[2] , \RowAd_0[3] , \RowAd_0[2] , \RowA[2] , \MAin_c[5] , - \MAin_c[4] , \RowAd_0[5] , \RowAd_0[4] , \RowA[4] , \RowA[5] , - \MAin_c[7] , \MAin_c[6] , \RowAd_0[7] , \RowAd_0[6] , \RowA[6] , - \RowA[7] , \MAin_c[9] , \MAin_c[8] , \RowAd_0[9] , \RowAd_0[8] , - \RowA[8] , \RowA[9] , XOR8MEG, N_441, XOR8MEG_3_u_0_0_a3_0_2, - XOR8MEG_3, N_4, g1_0, n8MEGENe_1_0, n8MEGENe_0, CASr3, N_248_i_1_1, - nRowColSel_0_0_0, nRRAS_0_sqmuxa, N_417, \wb_adr_5_i_0_0[1] , N_382, - N_416, \wb_adr_5_i_0_0[0] , N_383, N_423, \wb_adr_5_i_0_3[0] , - N_229_i, N_230_i, un1_wb_rst14_i_0, \wb_adr[0] , \wb_adr[1] , - \wb_adr[2] , \wb_adr_5[3] , \wb_adr_5[2] , \wb_adr[3] , \wb_adr[4] , - N_210, N_385, N_384, \wb_adr[5] , \wb_adr[6] , \wb_adr_5[7] , N_386, - \wb_adr[7] , N_214, N_471_3, wb_cyc_stb_4_iv_0_a3_0_0, N_471_2, - un1_PHI2r3, N_471, wb_cyc_stb_4, N_178, wb_rst10, wb_cyc_stb, N_207, - \wb_dati_5_1_iv_0_1[1] , N_578, \wb_dati_5_0_iv_0_a3_1[0] , wb_we, - N_576, \wb_dati_5[1] , \wb_dati_5[0] , \wb_dati[0] , \wb_dati[1] , - \wb_dati_5_1_iv_i_i_0[3] , \wb_dati_5_1_iv_i_i_1[3] , - \wb_dati_5_1_iv_i_i_a3_1[3] , N_579, N_361, \wb_dati_5_1_iv_i_i[3] , - \wb_dati_5[2] , \wb_dati[2] , \wb_dati[3] , \wb_dati[4] , - \wb_dati_5_1_iv_0_0[4] , \wb_dati_5_1_iv_0_1[4] , \wb_dati_5[5] , - \wb_dati_5[4] , \wb_dati[5] , N_484, N_486, N_488, - \wb_dati_5_1_iv_0_0[7] , \wb_dati_5_1_iv_0_1[6] , \wb_dati_5[7] , - \wb_dati_5[6] , \wb_dati[6] , \wb_dati[7] , N_92_i, N_31_i, wb_req, - wb_reqe_0, N_515, wb_rst, wb_rste_0, CmdUFMData, wb_we_0_i_0_1, - N_231_i, N_479, N_217, N_209, CBR_fast, N_408, nRCAS_0_sqmuxa_1, - N_248_i_sx, un1_nRCAS_6_sqmuxa_i_0_0, nRCAS_r_i_0_o2_0_0, N_599, - N_407, N_427, wb_we_0_i_0_a3_0_0, wb_we_0_i_0_0, \Din_c[6] , N_539, - un1_CmdEnable20_0_0_0, \wb_adr_5_i_0_a3_0_1[0] , N_424, N_542, - \wb_adr_5_i_0_1[0] , N_208, \wb_dati_5_1_iv_0_a3_0_1[7] , - \ufmefb/g0_0_a3_2 , N_226, \wb_dati_5_1_iv_0_a3_0_1[1] , N_477, N_236, - N_596, N_412, N_536, N_502, N_522, nRCS_9_u_i_0_o3, - \wb_dati_5_1_iv_i_i_a3_3_0[3] , un1_nRCAS_6_sqmuxa_i_0_0_o2_0, N_221, - N_246_i, un1_CmdEnable20_0_0_a3_1_1, nRWE_s_i_0_tz_0, N_590, N_595, - N_49_i, CmdUFMData_1_sqmuxa, N_248_i_1_0, N_247_i, \Bank[1] , - \Bank[3] , \Bank[4] , \Bank[5] , un1_CmdEnable20_0_0_o3_10, - un1_CmdEnable20_0_0_o3_11, \Bank[7] , \Bank[6] , N_537, N_514, N_473, - N_472, RA10s_i, nRWE_s_i_0_a3_1_0, wb_ack, wb_cyc_stb_2_sqmuxa_i_a3_0, - \Bank[0] , \Bank[2] , un1_CmdEnable20_0_0_o3_4, - un1_CmdEnable20_0_0_o3_3, N_248_i_1, N_248_i, N_511, N_404, - wb_cyc_stb_4_iv_0_a3_0_2_0, N_505, \Din_c[2] , \Din_c[7] , - XOR8MEG_3_u_0_0_0_a2, G_4_0_a3_0, RDQMH_c, RDQML_c, \RA_c[6] , - \RA_c[8] , \RA_c[9] , \RA_c[0] , \RA_c[7] , \RA_c[1] , \RA_c[5] , - \RA_c[2] , \RA_c[4] , \CROW_c[1] , RA11d_0, \RBAd_0[1] , \wb_dato[0] , - \RD_in[0] , \WRD[0] , nRCAS_c, nRRAS_c, nRWE_c, nRCS_c, \RD_in[7] , - \WRD[7] , \RD_in[6] , \WRD[6] , \RD_in[5] , \WRD[5] , \RD_in[4] , - \WRD[4] , \RD_in[3] , \WRD[3] , \RD_in[2] , \WRD[2] , \RD_in[1] , - \WRD[1] , \RA_c[11] , \RA_c[10] , \RBA_c[1] , \RBA_c[0] , VCCI; + \FS_s[3] , \FS_cry[2] , \FS[2] , \FS[1] , \FS_s[2] , \FS_s[1] , N_367, + \MAin_c[1] , ADSubmitted, CmdEnable16, CmdEnable17, N_293_i, + ADSubmitted_r_0_0, PHI2_c, N_457, N_483, C1Submitted, C1Submitted_RNO, + nCCAS_c, nCCAS_c_i, CASr, CASr2, \IS[3] , RASr2, \S[1] , CO0, N_279_i, + Ready_0_sqmuxa_0_a2_2, N_482, un1_CmdEnable20_i, CmdEnable, + CmdEnable_0_sqmuxa, CmdEnable_s, \Din_c[1] , N_260, + CmdLEDEN_4_u_i_m2_i_a2_0_0, CmdLEDEN, CmdLEDEN_4_u_i_m2_i_0, LEDEN, + N_461, N_17_i, XOR8MEG18, \IS[0] , \Din_c[0] , CmdUFMData_1_sqmuxa, + \IS_i[0] , CmdUFMData, CmdUFMShift, CmdUFMShift_3, GND, CmdUFMWrite, + N_415, CmdUFMWrite_3, \Din_c[5] , N_353, \Din_c[3] , \Din_c[4] , + CmdValid_r, CmdValid, \MAin_c[0] , N_34_fast, CmdValid_fast, + Cmdn8MEGEN, n8MEGEN, Cmdn8MEGEN_4_u_i_m2_i_0, N_15_i, nFWE_c, + nFWE_c_i, nCRAS_c, FWEr, RD_1_i, un1_nRCAS_6_sqmuxa_i_o2, + IS_0_sqmuxa_0_o2, nRCS_9_u_i_0_0, Ready, N_76_i_i, N_32_i, \IS[1] , + \IS[2] , N_73_i_i, N_69_i, N_261_i, IS_0_sqmuxa_0_o3, N_74_i_i, + nRWE_s_i_a2_1_0, InitReady, InitReady3, N_705_0, wb_rst10, + \wb_dato[1] , LEDEN_6, un1_FS_38_i, LEDENe_0, \CROW_c[0] , Ready_fast, + PHI2r2, PHI2r, \RBAd_0[0] , VCC, PHI2r3, \RowA[6] , \MAin_c[6] , + nRowColSel, nCRAS_c_i_0, RASr, \RA_c[6] , RASr3, \wb_adr_5_i_0_o2[0] , + \S_0_i_o3[1] , RCKEEN_8_u_0_0, RCKEEN_8_u_1, CBR, RCKEEN_8, RCKEEN, + RCKE_2, RCKE_c, m3_0_a2_0, Ready_0_sqmuxa_0_o2, N_706_0, + Ready_0_sqmuxa, N_707_0, \RowAd_0[1] , \RowAd_0[0] , \RowA[0] , + \RowA[1] , \MAin_c[3] , \MAin_c[2] , \RowAd_0[3] , \RowAd_0[2] , + \RowA[2] , \RowA[3] , \MAin_c[5] , \MAin_c[4] , \RowAd_0[5] , + \RowAd_0[4] , \RowA[4] , \RowA[5] , \MAin_c[7] , \RowAd_0[7] , + \RowAd_0[6] , \RowA[7] , \MAin_c[9] , \MAin_c[8] , \RowAd_0[9] , + \RowAd_0[8] , \RowA[8] , \RowA[9] , XOR8MEG, XOR8MEG_3_u_0_0_a2_0_2, + N_411, XOR8MEG_3, N_4, g1_0, n8MEGENe_1_0, n8MEGENe_0, CASr3, N_70_i, + N_251_i_1_0, nRowColSel_0_0, nRRAS_0_sqmuxa, \wb_adr_5_i_3_0_a2[1] , + N_216, \wb_adr_5_i_3_0_a2_0[1] , \wb_adr_5_i_3_0_0[1] , + \wb_dati_5_1_iv_0_a2_11[3] , \FS_RNIOVGI[9] , \wb_adr_5_i_0_3[0] , + \wb_adr_5_i_0_2[0] , N_45_i, N_47_i, N_126_i, \wb_adr[0] , + \wb_adr[1] , \wb_adr[2] , \wb_adr_5[3] , \wb_adr_5[2] , \wb_adr[3] , + \wb_adr[4] , \FS_RNI82PA[15] , \wb_adr_5[5] , \wb_adr_5[4] , + \wb_adr[5] , \wb_adr[6] , \wb_adr_5[7] , \wb_adr_5[6] , \wb_adr[7] , + N_99_1, wb_cyc_stb_4_iv_0_0_a2_0_0, \FS_RNIHVJI[15] , N_99_2, + un1_PHI2r3_i_li, wb_cyc_stb_4_iv_0_0_a2_0, wb_cyc_stb_4, + wb_cyc_stb_2_sqmuxa_i_0_0, wb_cyc_stb, \FS_RNIGOCT[12] , + \wb_dati_5_1_iv_0_1[1] , \FS_RNIS637[9] , \wb_dati_5_0_iv_0_a2_1[0] , + \wb_dati_5_1_iv_0_a2_12[3] , wb_we, \wb_dati_5[1] , \wb_dati_5[0] , + \wb_dati[0] , \wb_dati[1] , \wb_dati_5_1_iv_0_0_a2_1[3] , + \wb_dati_5_1_iv_0_0_1[3] , \wb_dati_5_1_iv_0_0_0[3] , + \wb_dati_5_1_iv_0_a2_13[3] , \wb_dati_5_1_iv_0_0_o2[5] , + \wb_dati_5[3] , \wb_dati_5[2] , \wb_dati[2] , \wb_dati[3] , + \wb_dati[4] , \wb_dati_5_1_iv_0_1_0[4] , \wb_dati_5_1_iv_0_0_1[4] , + \wb_dati_5[5] , \wb_dati_5[4] , \wb_dati[5] , + \wb_dati_5_1_iv_0_RNO[7] , \wb_dati_5_1_iv_0_1[7] , + \wb_dati_5_1_iv_0_a2_5[7] , \wb_dati_5_1_iv_0_0_1[6] , \wb_dati_5[7] , + \wb_dati_5[6] , \wb_dati[6] , \wb_dati[7] , un1_wb_rst14_2_0_o2, + N_122_i, un1_wb_rst14_2_i, wb_req, wb_reqe_0, wb_rst, wb_rst_3, + wb_rste_0, wb_we_0_0_i_1, N_346_i, \wb_dati_5_1_iv_0_o2[7] , + \wb_dati_5_1_iv_0_o2_0_RNIMDJC1[4] , \wb_dati_5_1_iv_0_0_o2[3] , + \FS_RNIJO0F[12] , \wb_dati_5_1_iv_0_o2_0[7] , \FS_RNI9Q57[12] , + \wb_adr_5_i_0_1[0] , N_313, \wb_adr_5_i_0_0[0] , N_48, N_466, + \Din_c[6] , un1_CmdEnable20_0_0_0, \wb_dati_5_1_iv_0_a2_0_2[1] , + \wb_dati_5_1_iv_0_0[1] , \wb_dati_5_1_iv_0_0_o2[4] , + \ufmefb/g0_0_a3_2 , \FS_RNIF2MA[9] , nRWE_s_i_tz_0, nRCS_9_u_i_o3_0_0, + RCKEEN_8_u_0_o3, nRCS_9_u_i_o3_0_2, \wb_adr_5_i_0_a2_6[0] , + wb_we_0_0_i_1_1, \wb_adr_5_i_3_0_a2_3[1] , \wb_dati_5_1_iv_0_o2_0[4] , + \FS_RNI7U6M[14] , \wb_dati_5_1_iv_0_1_RNO[7] , CBR_fast, N_142, + nRCAS_0_sqmuxa_1, N_141, N_252_i, un1_CmdEnable20_0_0_a2_1_1, + N_251_i_1, nRCS_9_u_i_0, N_37_i, RA10s_i, \Bank[3] , \Bank[6] , + \Bank[2] , \Bank[5] , \Bank[4] , un1_CmdEnable20_0_0_o2_11, \Bank[0] , + un1_CmdEnable20_0_0_o2_10, \wb_dati_5_1_iv_0_a2_6[4] , + \wb_dati_5_1_iv_0_a2_7[4] , \wb_dati_5_1_iv_0_0_a2[6] , + \wb_dati_5_1_iv_0_a2_2[4] , \wb_dati_5_1_iv_0_a2_0_0[7] , + \wb_dati_5_1_iv_0_a2_0[7] , \wb_dati_5_1_iv_0_a2_7[3] , + \wb_dati_5_1_iv_0_a2_5[3] , wb_cyc_stb_2_sqmuxa_i_0_0_a2_0, wb_ack, + \Bank[1] , \Bank[7] , un1_CmdEnable20_0_0_o2_4, + un1_CmdEnable20_0_0_o2_3, N_442, \Din_c[2] , wb_we_0_0_i_a2_0, + wb_cyc_stb_2_sqmuxa_i_a2_2_0, \Din_c[7] , N_452, InitReady3_0_a2_1_0, + G_4_0_a3_0, N_251_i_sx, N_251_i, LED_c, RDQMH_c, RDQML_c, + \wb_dato[0] , \RA_c[2] , \RA_c[0] , \RA_c[8] , \RA_c[1] , \RA_c[3] , + \RA_c[4] , \RA_c[9] , \RA_c[5] , \RA_c[7] , \CROW_c[1] , RA11d_0, + \RBAd_0[1] , \RD_in[0] , \WRD[0] , nRCAS_c, nRRAS_c, nRWE_c, + RCLKout_c, nRCS_c, \RD_in[7] , \WRD[7] , \RD_in[6] , \WRD[6] , + \RD_in[5] , \WRD[5] , \RD_in[4] , \WRD[4] , \RD_in[3] , \WRD[3] , + \RD_in[2] , \WRD[2] , \RD_in[1] , \WRD[1] , \RA_c[11] , \RA_c[10] , + \RBA_c[1] , \RBA_c[0] , VCCI; SLICE_0 SLICE_0( .A1(\FS[0] ), .DI1(\FS_s[0] ), .CLK(RCLK_c), .F1(\FS_s[0] ), .Q1(\FS[0] ), .FCO(\FS_cry[0] )); @@ -126,349 +139,380 @@ module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, SLICE_9 SLICE_9( .A1(\FS[2] ), .A0(\FS[1] ), .DI1(\FS_s[2] ), .DI0(\FS_s[1] ), .CLK(RCLK_c), .FCI(\FS_cry[0] ), .F0(\FS_s[1] ), .Q0(\FS[1] ), .F1(\FS_s[2] ), .Q1(\FS[2] ), .FCO(\FS_cry[2] )); - SLICE_10 SLICE_10( .D1(\MAin_c[1] ), .C1(un1_CmdEnable20_0_0_o3), - .D0(ADSubmitted), .C0(CmdEnable17), .B0(N_524), .A0(CmdEnable16), - .DI0(ADSubmitted_r_0_0), .CLK(PHI2_c), .F0(ADSubmitted_r_0_0), - .Q0(ADSubmitted), .F1(N_524)); - SLICE_11 SLICE_11( .D1(un1_CmdEnable20_0_0_o3), .C1(N_518), .B1(\MAin_c[1] ), - .A1(N_594), .D0(un1_CmdEnable20_0_0_o3), .C0(CmdEnable16), - .B0(\MAin_c[1] ), .A0(C1Submitted), .DI0(C1Submitted_RNO), .CLK(PHI2_c), - .F0(C1Submitted_RNO), .Q0(C1Submitted), .F1(CmdEnable16)); - SLICE_12 SLICE_12( .D0(nCCAS_c), .DI0(nCCAS_c_i), .M1(CASr), .CLK(RCLK_c), + SLICE_10 SLICE_10( .D1(N_367), .C1(\MAin_c[1] ), .D0(ADSubmitted), + .C0(CmdEnable16), .B0(CmdEnable17), .A0(N_293_i), .DI0(ADSubmitted_r_0_0), + .CLK(PHI2_c), .F0(ADSubmitted_r_0_0), .Q0(ADSubmitted), .F1(N_293_i)); + SLICE_11 SLICE_11( .D1(N_367), .C1(N_457), .B1(\MAin_c[1] ), .A1(N_483), + .D0(N_367), .C0(CmdEnable16), .B0(\MAin_c[1] ), .A0(C1Submitted), + .DI0(C1Submitted_RNO), .CLK(PHI2_c), .F0(C1Submitted_RNO), + .Q0(C1Submitted), .F1(CmdEnable16)); + SLICE_12 SLICE_12( .A0(nCCAS_c), .DI0(nCCAS_c_i), .M1(CASr), .CLK(RCLK_c), .F0(nCCAS_c_i), .Q0(CASr), .Q1(CASr2)); - SLICE_16 SLICE_16( .C1(CO0), .A1(\S[1] ), .C0(CO0), .A0(\S[1] ), - .DI0(N_123_i), .LSR(RASr2), .CLK(RCLK_c), .F0(N_123_i), .Q0(CO0), - .F1(N_345_i)); - SLICE_17 SLICE_17( .D1(N_518), .C1(N_593), .B1(\MAin_c[1] ), - .A1(un1_CmdEnable20_0_0_o3), .D0(CmdEnable_0_sqmuxa), .C0(CmdEnable17), - .B0(un1_CmdEnable20_i), .A0(CmdEnable), .DI0(CmdEnable_s), .CLK(PHI2_c), - .F0(CmdEnable_s), .Q0(CmdEnable), .F1(CmdEnable17)); - SLICE_18 SLICE_18( .D1(\Din_c[1] ), .C1(CmdLEDEN_4_u_i_0_a3_0_0), - .B1(CmdValid_2_i_o2_1_o3), .A1(CmdLEDEN), .C0(LEDEN), - .B0(CmdLEDEN_4_u_i_0_0), .A0(N_531), .DI0(N_40_i), .CE(XOR8MEG18), - .CLK(PHI2_c), .F0(N_40_i), .Q0(CmdLEDEN), .F1(CmdLEDEN_4_u_i_0_0)); - SLICE_20 SLICE_20( .D0(\Din_c[1] ), .C0(N_531), .B0(CmdValid_2_i_o2_1_o3), - .A0(CmdUFMShift), .DI0(CmdUFMShift_3), .CE(XOR8MEG18), .CLK(PHI2_c), - .F0(CmdUFMShift_3), .Q0(CmdUFMShift)); - SLICE_21 SLICE_21( .D1(CmdValid_2_i_o2_1_o3), .A1(CmdUFMWrite), - .D0(\Din_c[0] ), .C0(N_462), .B0(\Din_c[1] ), .A0(N_531), - .DI0(CmdUFMWrite_3), .CE(XOR8MEG18), .CLK(PHI2_c), .F0(CmdUFMWrite_3), - .Q0(CmdUFMWrite), .F1(N_462)); - SLICE_22 SLICE_22( .D1(N_213), .C1(\Din_c[3] ), .B1(\Din_c[4] ), - .A1(\Din_c[5] ), .C0(CmdValid_2_i_o2_1_o3), .A0(XOR8MEG18), - .DI0(CmdValid_r), .CLK(PHI2_c), .F0(CmdValid_r), .Q0(CmdValid), - .F1(CmdValid_2_i_o2_1_o3)); - SLICE_23 SLICE_23( .D1(CmdEnable), .C1(\MAin_c[1] ), .B1(\MAin_c[0] ), - .A1(un1_CmdEnable20_0_0_o3), .C0(XOR8MEG18), .B0(CmdValid_2_i_o2_1_o3), - .DI0(N_36_fast), .CLK(PHI2_c), .F0(N_36_fast), .Q0(CmdValid_fast), - .F1(XOR8MEG18)); - SLICE_24 SLICE_24( .D1(CmdValid_2_i_o2_1_o3), .C1(\Din_c[0] ), - .B1(Cmdn8MEGEN), .A1(CmdLEDEN_4_u_i_0_a3_0_0), .D0(n8MEGEN), - .C0(Cmdn8MEGEN_4_u_i_0_0), .B0(N_531), .DI0(N_38_i), .CE(XOR8MEG18), - .CLK(PHI2_c), .F0(N_38_i), .Q0(Cmdn8MEGEN), .F1(Cmdn8MEGEN_4_u_i_0_0)); - SLICE_25 SLICE_25( .B1(nFWE_c), .A1(nCCAS_c), .A0(nFWE_c), .DI0(nFWE_c_i), + SLICE_16 SLICE_16( .D1(\IS[3] ), .C1(RASr2), .B1(\S[1] ), .A1(CO0), + .B0(\S[1] ), .A0(CO0), .DI0(N_279_i), .LSR(RASr2), .CLK(RCLK_c), + .F0(N_279_i), .Q0(CO0), .F1(Ready_0_sqmuxa_0_a2_2)); + SLICE_17 SLICE_17( .D1(N_367), .C1(\MAin_c[1] ), .B1(N_457), .A1(N_482), + .D0(un1_CmdEnable20_i), .C0(CmdEnable17), .B0(CmdEnable), + .A0(CmdEnable_0_sqmuxa), .DI0(CmdEnable_s), .CLK(PHI2_c), .F0(CmdEnable_s), + .Q0(CmdEnable), .F1(CmdEnable17)); + SLICE_18 SLICE_18( .D1(\Din_c[1] ), .C1(N_260), + .B1(CmdLEDEN_4_u_i_m2_i_a2_0_0), .A1(CmdLEDEN), .C0(CmdLEDEN_4_u_i_m2_i_0), + .B0(LEDEN), .A0(N_461), .DI0(N_17_i), .CE(XOR8MEG18), .CLK(PHI2_c), + .F0(N_17_i), .Q0(CmdLEDEN), .F1(CmdLEDEN_4_u_i_m2_i_0)); + SLICE_19 SLICE_19( .B0(\IS[0] ), .M0(\Din_c[0] ), .CE(CmdUFMData_1_sqmuxa), + .CLK(PHI2_c), .F0(\IS_i[0] ), .Q0(CmdUFMData)); + SLICE_20 SLICE_20( .D0(N_461), .C0(N_260), .B0(\Din_c[1] ), .A0(CmdUFMShift), + .DI0(CmdUFMShift_3), .CE(XOR8MEG18), .CLK(PHI2_c), .F0(CmdUFMShift_3), + .Q0(CmdUFMShift), .F1(GND)); + SLICE_21 SLICE_21( .B1(CmdUFMWrite), .A1(N_260), .D0(\Din_c[1] ), .C0(N_415), + .B0(N_461), .A0(\Din_c[0] ), .DI0(CmdUFMWrite_3), .CE(XOR8MEG18), + .CLK(PHI2_c), .F0(CmdUFMWrite_3), .Q0(CmdUFMWrite), .F1(N_415)); + SLICE_22 SLICE_22( .D1(\Din_c[5] ), .C1(N_353), .B1(\Din_c[3] ), + .A1(\Din_c[4] ), .D0(N_260), .C0(XOR8MEG18), .DI0(CmdValid_r), + .CLK(PHI2_c), .F0(CmdValid_r), .Q0(CmdValid), .F1(N_260)); + SLICE_23 SLICE_23( .D1(\MAin_c[1] ), .C1(\MAin_c[0] ), .B1(N_367), + .A1(CmdEnable), .C0(N_260), .B0(XOR8MEG18), .DI0(N_34_fast), .CLK(PHI2_c), + .F0(N_34_fast), .Q0(CmdValid_fast), .F1(XOR8MEG18)); + SLICE_24 SLICE_24( .D1(CmdLEDEN_4_u_i_m2_i_a2_0_0), .C1(N_260), + .B1(\Din_c[0] ), .A1(Cmdn8MEGEN), .D0(n8MEGEN), + .C0(Cmdn8MEGEN_4_u_i_m2_i_0), .A0(N_461), .DI0(N_15_i), .CE(XOR8MEG18), + .CLK(PHI2_c), .F0(N_15_i), .Q0(Cmdn8MEGEN), .F1(Cmdn8MEGEN_4_u_i_m2_i_0)); + SLICE_25 SLICE_25( .D1(nFWE_c), .A1(nCCAS_c), .D0(nFWE_c), .DI0(nFWE_c_i), .CLK(nCRAS_c), .F0(nFWE_c_i), .Q0(FWEr), .F1(RD_1_i)); - SLICE_26 SLICE_26( .B1(CASr2), .A1(CO0), .B0(nRCS_9_u_i_0_o2_1_RNIL2K71), - .A0(\IS[0] ), .DI0(N_351_i_i), .CLK(RCLK_c), .F0(N_351_i_i), .Q0(\IS[0] ), - .F1(N_267)); - SLICE_27 SLICE_27( .C1(\IS[0] ), .B1(\IS[1] ), .A1(\IS[2] ), .C0(\IS[0] ), - .A0(\IS[1] ), .DI1(N_348_i_i), .DI0(N_344_i), .CE(N_360_i), .CLK(RCLK_c), - .F0(N_344_i), .Q0(\IS[1] ), .F1(N_348_i_i), .Q1(\IS[2] )); - SLICE_28 SLICE_28( .B1(\IS[0] ), .D0(\IS[2] ), .C0(\IS[1] ), .B0(\IS[0] ), - .A0(\IS[3] ), .DI0(N_350_i_i), .CE(N_360_i), .CLK(RCLK_c), .F0(N_350_i_i), - .Q0(\IS[3] ), .F1(\IS_i[0] )); - SLICE_29 SLICE_29( .D1(\FS[10] ), .C1(N_581), .B1(InitReady3_0_a3_1), - .A1(\FS[11] ), .C0(InitReady3), .A0(InitReady), .DI0(N_757_0), - .CLK(RCLK_c), .F0(N_757_0), .Q0(InitReady), .F1(InitReady3)); + SLICE_26 SLICE_26( .D1(un1_nRCAS_6_sqmuxa_i_o2), .C1(IS_0_sqmuxa_0_o2), + .B1(nRCS_9_u_i_0_0), .A1(\IS[0] ), .C0(IS_0_sqmuxa_0_o2), .B0(Ready), + .A0(\IS[0] ), .DI0(N_76_i_i), .CLK(RCLK_c), .F0(N_76_i_i), .Q0(\IS[0] ), + .F1(N_32_i)); + SLICE_27 SLICE_27( .D1(\IS[1] ), .B1(\IS[0] ), .A1(\IS[2] ), .B0(\IS[0] ), + .A0(\IS[1] ), .DI1(N_73_i_i), .DI0(N_69_i), .CE(N_261_i), .CLK(RCLK_c), + .F0(N_69_i), .Q0(\IS[1] ), .F1(N_73_i_i), .Q1(\IS[2] )); + SLICE_28 SLICE_28( .D1(\IS[1] ), .C1(IS_0_sqmuxa_0_o3), .B1(\IS[0] ), + .A1(\IS[2] ), .D0(\IS[1] ), .C0(\IS[0] ), .B0(\IS[3] ), .A0(\IS[2] ), + .DI0(N_74_i_i), .CE(N_261_i), .CLK(RCLK_c), .F0(N_74_i_i), .Q0(\IS[3] ), + .F1(nRWE_s_i_a2_1_0)); + SLICE_29 SLICE_29( .D1(InitReady), .C1(\FS[15] ), .B1(\FS[16] ), + .A1(\FS[17] ), .B0(InitReady3), .A0(InitReady), .DI0(N_705_0), + .CLK(RCLK_c), .F0(N_705_0), .Q0(InitReady), .F1(wb_rst10)); SLICE_30 SLICE_30( .C1(\wb_dato[1] ), .B1(InitReady), .A1(CmdLEDEN), - .D0(LEDEN), .B0(LEDEN_6_i_m2_i_m2), .A0(CmdValid_RNIOOBE2), .DI0(LEDENe_0), - .CLK(RCLK_c), .F0(LEDENe_0), .Q0(LEDEN), .F1(LEDEN_6_i_m2_i_m2)); - SLICE_31 SLICE_31( .B0(Ready_fast), .A0(\CROW_c[0] ), .M1(PHI2r2), - .M0(PHI2r), .CLK(RCLK_c), .F0(\RBAd_0[0] ), .Q0(PHI2r2), .Q1(PHI2r3)); - SLICE_32 SLICE_32( .D1(CBR), .C1(nCRAS_c), .B1(LEDEN), .C0(nCRAS_c), - .DI0(nCRAS_c_i_0), .M1(RASr), .CLK(RCLK_c), .F0(nCRAS_c_i_0), .Q0(RASr), - .F1(LED_c), .Q1(RASr2)); - SLICE_33 SLICE_33( .D1(nRowColSel), .C1(\RowA[3] ), .B1(\MAin_c[3] ), + .C0(LEDEN_6), .B0(un1_FS_38_i), .A0(LEDEN), .DI0(LEDENe_0), .CLK(RCLK_c), + .F0(LEDENe_0), .Q0(LEDEN), .F1(LEDEN_6)); + SLICE_31 SLICE_31( .D0(\CROW_c[0] ), .B0(Ready_fast), .M1(PHI2r2), + .M0(PHI2r), .CLK(RCLK_c), .F0(\RBAd_0[0] ), .Q0(PHI2r2), .F1(VCC), + .Q1(PHI2r3)); + SLICE_32 SLICE_32( .C1(\RowA[6] ), .B1(\MAin_c[6] ), .A1(nRowColSel), + .B0(nCRAS_c), .DI0(nCRAS_c_i_0), .M1(RASr), .CLK(RCLK_c), .F0(nCRAS_c_i_0), + .Q0(RASr), .F1(\RA_c[6] ), .Q1(RASr2)); + SLICE_33 SLICE_33( .C1(\FS[9] ), .B1(\FS[11] ), .A1(\FS[10] ), .C0(CmdEnable16), .A0(ADSubmitted), .M0(RASr2), .CLK(RCLK_c), - .F0(CmdEnable_0_sqmuxa), .Q0(RASr3), .F1(\RA_c[3] )); - SLICE_34 SLICE_34( .D1(N_216), .C1(RASr2), .B1(InitReady), .A1(Ready), - .D0(RCKEEN_8_u_0_1_0), .C0(RCKEEN_8_u_0_0_0), .B0(CBR), .A0(Ready), + .F0(CmdEnable_0_sqmuxa), .Q0(RASr3), .F1(\wb_adr_5_i_0_o2[0] )); + SLICE_34 SLICE_34( .D1(InitReady), .C1(\S_0_i_o3[1] ), .B1(RASr2), + .A1(Ready), .D0(Ready), .C0(RCKEEN_8_u_0_0), .B0(RCKEEN_8_u_1), .A0(CBR), .DI0(RCKEEN_8), .CLK(RCLK_c), .F0(RCKEEN_8), .Q0(RCKEEN), - .F1(RCKEEN_8_u_0_0_0)); - SLICE_35 SLICE_35( .C1(RASr2), .A1(\S[1] ), .D0(RASr2), .C0(RASr3), - .B0(RCKEEN), .A0(RASr), .DI0(RCKE_2), .CLK(RCLK_c), .F0(RCKE_2), + .F1(RCKEEN_8_u_0_0)); + SLICE_35 SLICE_35( .C1(\S[1] ), .B1(RASr2), .D0(RASr), .C0(RCKEEN), + .B0(RASr2), .A0(RASr3), .DI0(RCKE_2), .CLK(RCLK_c), .F0(RCKE_2), .Q0(RCKE_c), .F1(m3_0_a2_0)); - SLICE_36 SLICE_36( .D1(\IS[1] ), .C1(\IS[0] ), .B1(\IS[2] ), - .D0(Ready_0_sqmuxa_0_a2_4_a3_2), .C0(N_347), .B0(InitReady), .A0(Ready), - .DI0(N_758_0), .CLK(RCLK_c), .F0(N_758_0), .Q0(Ready), .F1(N_347)); - SLICE_37 SLICE_37( .D1(Ready_0_sqmuxa_0_a2_4_a3_2), .C1(N_347), - .B1(InitReady), .A1(Ready), .C0(Ready_0_sqmuxa), .A0(Ready_fast), - .DI0(N_759_0), .CLK(RCLK_c), .F0(N_759_0), .Q0(Ready_fast), + SLICE_36 SLICE_36( .D1(\IS[1] ), .B1(\IS[0] ), .A1(\IS[2] ), + .D0(Ready_0_sqmuxa_0_o2), .C0(Ready_0_sqmuxa_0_a2_2), .B0(InitReady), + .A0(Ready), .DI0(N_706_0), .CLK(RCLK_c), .F0(N_706_0), .Q0(Ready), + .F1(Ready_0_sqmuxa_0_o2)); + SLICE_37 SLICE_37( .D1(InitReady), .C1(Ready_0_sqmuxa_0_a2_2), + .B1(Ready_0_sqmuxa_0_o2), .A1(Ready), .C0(Ready_0_sqmuxa), .A0(Ready_fast), + .DI0(N_707_0), .CLK(RCLK_c), .F0(N_707_0), .Q0(Ready_fast), .F1(Ready_0_sqmuxa)); - SLICE_38 SLICE_38( .B1(Ready_fast), .A1(\MAin_c[1] ), .B0(Ready_fast), - .A0(\MAin_c[0] ), .DI1(\RowAd_0[1] ), .DI0(\RowAd_0[0] ), .CLK(nCRAS_c), + SLICE_38 SLICE_38( .C1(\MAin_c[1] ), .A1(Ready_fast), .B0(\MAin_c[0] ), + .A0(Ready_fast), .DI1(\RowAd_0[1] ), .DI0(\RowAd_0[0] ), .CLK(nCRAS_c), .F0(\RowAd_0[0] ), .Q0(\RowA[0] ), .F1(\RowAd_0[1] ), .Q1(\RowA[1] )); - SLICE_39 SLICE_39( .B1(Ready_fast), .A1(\MAin_c[3] ), .C0(\MAin_c[2] ), - .B0(Ready_fast), .DI1(\RowAd_0[3] ), .DI0(\RowAd_0[2] ), .CLK(nCRAS_c), + SLICE_39 SLICE_39( .D1(\MAin_c[3] ), .C1(Ready_fast), .C0(Ready_fast), + .B0(\MAin_c[2] ), .DI1(\RowAd_0[3] ), .DI0(\RowAd_0[2] ), .CLK(nCRAS_c), .F0(\RowAd_0[2] ), .Q0(\RowA[2] ), .F1(\RowAd_0[3] ), .Q1(\RowA[3] )); SLICE_40 SLICE_40( .C1(Ready_fast), .B1(\MAin_c[5] ), .C0(Ready_fast), .B0(\MAin_c[4] ), .DI1(\RowAd_0[5] ), .DI0(\RowAd_0[4] ), .CLK(nCRAS_c), .F0(\RowAd_0[4] ), .Q0(\RowA[4] ), .F1(\RowAd_0[5] ), .Q1(\RowA[5] )); - SLICE_41 SLICE_41( .C1(Ready_fast), .B1(\MAin_c[7] ), .C0(Ready_fast), - .B0(\MAin_c[6] ), .DI1(\RowAd_0[7] ), .DI0(\RowAd_0[6] ), .CLK(nCRAS_c), + SLICE_41 SLICE_41( .D1(\MAin_c[7] ), .A1(Ready_fast), .B0(\MAin_c[6] ), + .A0(Ready_fast), .DI1(\RowAd_0[7] ), .DI0(\RowAd_0[6] ), .CLK(nCRAS_c), .F0(\RowAd_0[6] ), .Q0(\RowA[6] ), .F1(\RowAd_0[7] ), .Q1(\RowA[7] )); - SLICE_42 SLICE_42( .D1(Ready_fast), .A1(\MAin_c[9] ), .D0(Ready_fast), - .C0(\MAin_c[8] ), .DI1(\RowAd_0[9] ), .DI0(\RowAd_0[8] ), .CLK(nCRAS_c), + SLICE_42 SLICE_42( .B1(Ready_fast), .A1(\MAin_c[9] ), .C0(\MAin_c[8] ), + .B0(Ready_fast), .DI1(\RowAd_0[9] ), .DI0(\RowAd_0[8] ), .CLK(nCRAS_c), .F0(\RowAd_0[8] ), .Q0(\RowA[8] ), .F1(\RowAd_0[9] ), .Q1(\RowA[9] )); - SLICE_43 SLICE_43( .D1(RASr2), .C1(CO0), .B1(\IS[3] ), .A1(\S[1] ), .B0(CO0), - .A0(\S[1] ), .DI0(N_216), .LSR(RASr2), .CLK(RCLK_c), .F0(N_216), - .Q0(\S[1] ), .F1(Ready_0_sqmuxa_0_a2_4_a3_2)); - SLICE_44 SLICE_44( .D1(\Din_c[5] ), .C1(\Din_c[4] ), .B1(N_213), - .A1(XOR8MEG), .D0(\Din_c[1] ), .C0(LEDEN), .B0(N_441), - .A0(XOR8MEG_3_u_0_0_a3_0_2), .DI0(XOR8MEG_3), .CE(XOR8MEG18), .CLK(PHI2_c), - .F0(XOR8MEG_3), .Q0(XOR8MEG), .F1(N_441)); + SLICE_43 SLICE_43( .D1(RCKE_c), .C1(Ready), .B1(RASr2), .A1(\S_0_i_o3[1] ), + .C0(CO0), .A0(\S[1] ), .DI0(\S_0_i_o3[1] ), .LSR(RASr2), .CLK(RCLK_c), + .F0(\S_0_i_o3[1] ), .Q0(\S[1] ), .F1(nRCS_9_u_i_0_0)); + SLICE_44 SLICE_44( .D1(N_353), .C1(\Din_c[5] ), .B1(\Din_c[4] ), + .A1(XOR8MEG), .D0(XOR8MEG_3_u_0_0_a2_0_2), .C0(N_411), .B0(LEDEN), + .A0(\Din_c[1] ), .DI0(XOR8MEG_3), .CE(XOR8MEG18), .CLK(PHI2_c), + .F0(XOR8MEG_3), .Q0(XOR8MEG), .F1(N_411)); SLICE_45 SLICE_45( .D1(CmdValid), .C1(N_4), .B1(InitReady), .A1(g1_0), - .D0(n8MEGENe_1_0), .C0(CmdValid_RNIOOBE2), .A0(n8MEGEN), .DI0(n8MEGENe_0), - .CLK(RCLK_c), .F0(n8MEGENe_0), .Q0(n8MEGEN), .F1(CmdValid_RNIOOBE2)); - SLICE_46 SLICE_46( .C1(CASr3), .A1(FWEr), .D0(CBR), .C0(N_248_i_1_1), - .B0(N_345_i), .A0(Ready), .DI0(nRowColSel_0_0_0), .LSR(nRRAS_0_sqmuxa), - .CLK(RCLK_c), .F0(nRowColSel_0_0_0), .Q0(nRowColSel), .F1(N_248_i_1_1)); - SLICE_47 SLICE_47( .D1(N_417), .C1(\wb_adr_5_i_0_0[1] ), .B1(N_382), - .A1(N_416), .D0(\wb_adr_5_i_0_0[0] ), .C0(N_383), .B0(N_423), - .A0(\wb_adr_5_i_0_3[0] ), .DI1(N_229_i), .DI0(N_230_i), - .CE(un1_wb_rst14_i_0), .CLK(RCLK_c), .F0(N_230_i), .Q0(\wb_adr[0] ), - .F1(N_229_i), .Q1(\wb_adr[1] )); - SLICE_48 SLICE_48( .D1(\wb_adr[2] ), .A1(InitReady), .C0(\wb_adr[1] ), - .A0(InitReady), .DI1(\wb_adr_5[3] ), .DI0(\wb_adr_5[2] ), - .CE(un1_wb_rst14_i_0), .CLK(RCLK_c), .F0(\wb_adr_5[2] ), .Q0(\wb_adr[2] ), - .F1(\wb_adr_5[3] ), .Q1(\wb_adr[3] )); - SLICE_49 SLICE_49( .D1(InitReady), .C1(\wb_adr[4] ), .B1(N_210), - .A1(\FS[15] ), .D0(InitReady), .C0(\wb_adr[3] ), .B0(N_210), .A0(\FS[15] ), - .DI1(N_385), .DI0(N_384), .CE(un1_wb_rst14_i_0), .CLK(RCLK_c), .F0(N_384), - .Q0(\wb_adr[4] ), .F1(N_385), .Q1(\wb_adr[5] )); - SLICE_50 SLICE_50( .B1(\wb_adr[6] ), .A1(InitReady), .D0(\FS[15] ), - .C0(\wb_adr[5] ), .B0(N_210), .A0(InitReady), .DI1(\wb_adr_5[7] ), - .DI0(N_386), .CE(un1_wb_rst14_i_0), .CLK(RCLK_c), .F0(N_386), + .D0(n8MEGENe_1_0), .C0(un1_FS_38_i), .A0(n8MEGEN), .DI0(n8MEGENe_0), + .CLK(RCLK_c), .F0(n8MEGENe_0), .Q0(n8MEGEN), .F1(un1_FS_38_i)); + SLICE_46 SLICE_46( .C1(CASr3), .B1(FWEr), .D0(N_70_i), .C0(Ready), + .B0(N_251_i_1_0), .A0(CBR), .DI0(nRowColSel_0_0), .LSR(nRRAS_0_sqmuxa), + .CLK(RCLK_c), .F0(nRowColSel_0_0), .Q0(nRowColSel), .F1(N_251_i_1_0)); + SLICE_47 SLICE_47( .D1(\wb_adr_5_i_3_0_a2[1] ), .C1(N_216), + .B1(\wb_adr_5_i_3_0_a2_0[1] ), .A1(\wb_adr_5_i_3_0_0[1] ), + .D0(\wb_dati_5_1_iv_0_a2_11[3] ), .C0(\FS_RNIOVGI[9] ), + .B0(\wb_adr_5_i_0_3[0] ), .A0(\wb_adr_5_i_0_2[0] ), .DI1(N_45_i), + .DI0(N_47_i), .CE(N_126_i), .CLK(RCLK_c), .F0(N_47_i), .Q0(\wb_adr[0] ), + .F1(N_45_i), .Q1(\wb_adr[1] )); + SLICE_48 SLICE_48( .B1(InitReady), .A1(\wb_adr[2] ), .B0(InitReady), + .A0(\wb_adr[1] ), .DI1(\wb_adr_5[3] ), .DI0(\wb_adr_5[2] ), .CE(N_126_i), + .CLK(RCLK_c), .F0(\wb_adr_5[2] ), .Q0(\wb_adr[2] ), .F1(\wb_adr_5[3] ), + .Q1(\wb_adr[3] )); + SLICE_49 SLICE_49( .D1(\wb_adr[4] ), .C1(\FS_RNI82PA[15] ), .A1(InitReady), + .D0(\wb_adr[3] ), .C0(\FS_RNI82PA[15] ), .A0(InitReady), + .DI1(\wb_adr_5[5] ), .DI0(\wb_adr_5[4] ), .CE(N_126_i), .CLK(RCLK_c), + .F0(\wb_adr_5[4] ), .Q0(\wb_adr[4] ), .F1(\wb_adr_5[5] ), .Q1(\wb_adr[5] )); + SLICE_50 SLICE_50( .C1(InitReady), .B1(\wb_adr[6] ), .C0(InitReady), + .B0(\wb_adr[5] ), .A0(\FS_RNI82PA[15] ), .DI1(\wb_adr_5[7] ), + .DI0(\wb_adr_5[6] ), .CE(N_126_i), .CLK(RCLK_c), .F0(\wb_adr_5[6] ), .Q0(\wb_adr[6] ), .F1(\wb_adr_5[7] ), .Q1(\wb_adr[7] )); - SLICE_51 SLICE_51( .D1(N_214), .C1(N_471_3), .B1(wb_cyc_stb_4_iv_0_a3_0_0), - .A1(N_471_2), .D0(un1_PHI2r3), .C0(N_471), .B0(CmdUFMWrite), - .A0(InitReady), .DI0(wb_cyc_stb_4), .CE(N_178), .LSR(wb_rst10), - .CLK(RCLK_c), .F0(wb_cyc_stb_4), .Q0(wb_cyc_stb), .F1(N_471)); - SLICE_52 SLICE_52( .D1(N_207), .C1(\wb_dati_5_1_iv_0_1[1] ), .B1(\FS[11] ), - .A1(N_578), .D0(InitReady), .C0(\wb_dati_5_0_iv_0_a3_1[0] ), .B0(wb_we), - .A0(N_576), .DI1(\wb_dati_5[1] ), .DI0(\wb_dati_5[0] ), - .CE(un1_wb_rst14_i_0), .CLK(RCLK_c), .F0(\wb_dati_5[0] ), - .Q0(\wb_dati[0] ), .F1(\wb_dati_5[1] ), .Q1(\wb_dati[1] )); - SLICE_53 SLICE_53( .D1(\wb_dati_5_1_iv_i_i_0[3] ), - .C1(\wb_dati_5_1_iv_i_i_1[3] ), .B1(\wb_dati_5_1_iv_i_i_a3_1[3] ), - .A1(N_579), .D0(N_361), .C0(\wb_dati[1] ), .A0(InitReady), - .DI1(\wb_dati_5_1_iv_i_i[3] ), .DI0(\wb_dati_5[2] ), .CE(un1_wb_rst14_i_0), - .CLK(RCLK_c), .F0(\wb_dati_5[2] ), .Q0(\wb_dati[2] ), - .F1(\wb_dati_5_1_iv_i_i[3] ), .Q1(\wb_dati[3] )); - SLICE_54 SLICE_54( .D1(InitReady), .C1(N_361), .A1(\wb_dati[4] ), - .D0(\wb_dati_5_1_iv_0_0[4] ), .C0(\FS[9] ), .B0(\wb_dati_5_1_iv_0_1[4] ), - .A0(N_578), .DI1(\wb_dati_5[5] ), .DI0(\wb_dati_5[4] ), - .CE(un1_wb_rst14_i_0), .CLK(RCLK_c), .F0(\wb_dati_5[4] ), - .Q0(\wb_dati[4] ), .F1(\wb_dati_5[5] ), .Q1(\wb_dati[5] )); - SLICE_55 SLICE_55( .D1(N_484), .C1(N_486), .B1(N_488), - .A1(\wb_dati_5_1_iv_0_0[7] ), .D0(N_207), .C0(N_578), .B0(\FS[11] ), - .A0(\wb_dati_5_1_iv_0_1[6] ), .DI1(\wb_dati_5[7] ), .DI0(\wb_dati_5[6] ), - .CE(un1_wb_rst14_i_0), .CLK(RCLK_c), .F0(\wb_dati_5[6] ), + SLICE_51 SLICE_51( .D1(N_99_1), .C1(wb_cyc_stb_4_iv_0_0_a2_0_0), + .B1(\FS_RNIHVJI[15] ), .A1(N_99_2), .D0(un1_PHI2r3_i_li), .C0(InitReady), + .B0(wb_cyc_stb_4_iv_0_0_a2_0), .A0(CmdUFMWrite), .DI0(wb_cyc_stb_4), + .CE(wb_cyc_stb_2_sqmuxa_i_0_0), .LSR(wb_rst10), .CLK(RCLK_c), + .F0(wb_cyc_stb_4), .Q0(wb_cyc_stb), .F1(wb_cyc_stb_4_iv_0_0_a2_0)); + SLICE_52 SLICE_52( .D1(\FS_RNIGOCT[12] ), .C1(\wb_dati_5_1_iv_0_1[1] ), + .B1(\FS_RNIS637[9] ), .A1(\FS[11] ), .D0(\wb_dati_5_0_iv_0_a2_1[0] ), + .C0(\wb_dati_5_1_iv_0_a2_12[3] ), .B0(InitReady), .A0(wb_we), + .DI1(\wb_dati_5[1] ), .DI0(\wb_dati_5[0] ), .CE(N_126_i), .CLK(RCLK_c), + .F0(\wb_dati_5[0] ), .Q0(\wb_dati[0] ), .F1(\wb_dati_5[1] ), + .Q1(\wb_dati[1] )); + SLICE_53 SLICE_53( .D1(\wb_dati_5_1_iv_0_0_a2_1[3] ), + .C1(\wb_dati_5_1_iv_0_0_1[3] ), .B1(\wb_dati_5_1_iv_0_0_0[3] ), + .A1(\wb_dati_5_1_iv_0_a2_13[3] ), .D0(\wb_dati_5_1_iv_0_0_o2[5] ), + .B0(InitReady), .A0(\wb_dati[1] ), .DI1(\wb_dati_5[3] ), + .DI0(\wb_dati_5[2] ), .CE(N_126_i), .CLK(RCLK_c), .F0(\wb_dati_5[2] ), + .Q0(\wb_dati[2] ), .F1(\wb_dati_5[3] ), .Q1(\wb_dati[3] )); + SLICE_54 SLICE_54( .D1(\wb_dati[4] ), .C1(\wb_dati_5_1_iv_0_0_o2[5] ), + .B1(InitReady), .D0(\FS[9] ), .C0(\wb_dati_5_1_iv_0_1_0[4] ), + .B0(\wb_dati_5_1_iv_0_0_1[4] ), .A0(\FS_RNIGOCT[12] ), + .DI1(\wb_dati_5[5] ), .DI0(\wb_dati_5[4] ), .CE(N_126_i), .CLK(RCLK_c), + .F0(\wb_dati_5[4] ), .Q0(\wb_dati[4] ), .F1(\wb_dati_5[5] ), + .Q1(\wb_dati[5] )); + SLICE_55 SLICE_55( .D1(\wb_dati_5_1_iv_0_RNO[7] ), + .C1(\wb_dati_5_1_iv_0_a2_13[3] ), .B1(\wb_dati_5_1_iv_0_1[7] ), + .A1(\wb_dati_5_1_iv_0_a2_5[7] ), .D0(\FS[11] ), .C0(\FS_RNIGOCT[12] ), + .B0(\FS_RNIS637[9] ), .A0(\wb_dati_5_1_iv_0_0_1[6] ), .DI1(\wb_dati_5[7] ), + .DI0(\wb_dati_5[6] ), .CE(N_126_i), .CLK(RCLK_c), .F0(\wb_dati_5[6] ), .Q0(\wb_dati[6] ), .F1(\wb_dati_5[7] ), .Q1(\wb_dati[7] )); - SLICE_56 SLICE_56( .D1(\FS[17] ), .C1(\FS[16] ), .B1(N_581), .A1(InitReady), - .C0(N_92_i), .B0(N_31_i), .A0(wb_req), .DI0(wb_reqe_0), .LSR(wb_rst10), - .CLK(RCLK_c), .F0(wb_reqe_0), .Q0(wb_req), .F1(N_31_i)); - SLICE_57 SLICE_57( .D1(InitReady), .C1(\FS[16] ), .B1(\FS[17] ), - .A1(\FS[15] ), .D0(wb_rst10), .C0(N_515), .B0(N_92_i), .A0(wb_rst), - .DI0(wb_rste_0), .CLK(RCLK_c), .F0(wb_rste_0), .Q0(wb_rst), .F1(wb_rst10)); - SLICE_58 SLICE_58( .D1(InitReady), .C1(\wb_adr[0] ), .B1(N_210), - .A1(\FS[15] ), .D0(InitReady), .C0(CmdUFMData), .B0(N_210), - .A0(wb_we_0_i_0_1), .DI0(N_231_i), .CE(un1_wb_rst14_i_0), .LSR(wb_rst10), - .CLK(RCLK_c), .F0(N_231_i), .Q0(wb_we), .F1(N_382)); - wb_dati_5_1_iv_0_o3_5__SLICE_59 \wb_dati_5_1_iv_0_o3[5]/SLICE_59 ( - .D1(N_214), .C1(\FS[12] ), .B1(N_479), .A1(N_217), .D0(N_214), .C0(N_209), - .B0(N_479), .A0(\FS[13] ), .M0(\FS[9] ), .OFX0(N_361)); - SLICE_60 SLICE_60( .D1(Ready), .C1(CO0), .B1(m3_0_a2_0), .A1(CBR_fast), - .D0(CO0), .C0(N_408), .B0(nRCAS_0_sqmuxa_1), .A0(\S[1] ), .F0(N_248_i_sx), - .F1(nRCAS_0_sqmuxa_1)); - SLICE_61 SLICE_61( .D1(\S[1] ), .C1(N_408), .B1(Ready), .A1(CO0), - .D0(un1_nRCAS_6_sqmuxa_i_0_0), .C0(CO0), .B0(CASr2), - .F0(nRCAS_r_i_0_o2_0_0), .F1(un1_nRCAS_6_sqmuxa_i_0_0)); - SLICE_62 SLICE_62( .D1(\FS[10] ), .C1(InitReady), .B1(\FS[11] ), - .A1(\FS[9] ), .D0(\FS[14] ), .C0(InitReady), .B0(N_599), .F0(N_407), - .F1(N_599)); - SLICE_63 SLICE_63( .D1(N_427), .C1(N_207), .B1(\FS[12] ), - .A1(wb_we_0_i_0_a3_0_0), .D0(N_407), .C0(wb_we_0_i_0_0), .B0(\FS[12] ), - .A0(\FS[13] ), .F0(wb_we_0_i_0_1), .F1(wb_we_0_i_0_0)); - SLICE_64 SLICE_64( .D1(\Din_c[6] ), .C1(N_539), .B1(\MAin_c[0] ), - .A1(\Din_c[3] ), .D0(N_594), .C0(N_518), .B0(\MAin_c[0] ), - .A0(\MAin_c[1] ), .F0(un1_CmdEnable20_0_0_0), .F1(N_594)); - SLICE_65 SLICE_65( .D1(\FS[10] ), .C1(\FS[9] ), - .B1(\wb_adr_5_i_0_a3_0_1[0] ), .A1(N_424), .D0(N_542), .C0(\FS[9] ), - .B0(\wb_adr_5_i_0_1[0] ), .A0(N_208), .F0(\wb_adr_5_i_0_3[0] ), - .F1(\wb_adr_5_i_0_1[0] )); - SLICE_66 SLICE_66( .D1(InitReady), .C1(\FS[15] ), .B1(\FS[17] ), - .A1(\FS[16] ), .D0(InitReady), .C0(N_214), .B0(\wb_dati[6] ), - .A0(\wb_dati_5_1_iv_0_a3_0_1[7] ), .F0(\wb_dati_5_1_iv_0_0[7] ), - .F1(N_214)); - SLICE_67 SLICE_67( .D1(N_579), .C1(\FS[9] ), .B1(N_208), .A1(\FS[10] ), - .D0(\FS[10] ), .B0(\FS[13] ), .A0(\FS[11] ), .F0(N_208), - .F1(\wb_dati_5_1_iv_0_0[4] )); - SLICE_68 SLICE_68( .D1(\FS[9] ), .C1(\FS[10] ), .A1(\FS[11] ), - .D0(\ufmefb/g0_0_a3_2 ), .C0(N_214), .A0(N_226), .F0(N_4), .F1(N_226)); - SLICE_69 SLICE_69( .D1(N_214), .C1(\FS[14] ), - .B1(\wb_dati_5_1_iv_0_a3_0_1[1] ), .A1(\FS[12] ), .D0(\FS[11] ), - .C0(\FS[10] ), .B0(\FS[9] ), .A0(\FS[13] ), - .F0(\wb_dati_5_1_iv_0_a3_0_1[1] ), .F1(N_477)); - SLICE_70 SLICE_70( .D1(\FS[13] ), .C1(N_236), .B1(N_542), .A1(\FS[11] ), - .D0(\FS[14] ), .C0(\FS[12] ), .B0(InitReady), .F0(N_542), .F1(N_424)); - SLICE_71 SLICE_71( .D1(N_596), .C1(N_412), .B1(N_536), .A1(N_502), - .D0(\FS[10] ), .C0(\FS[9] ), .A0(\FS[11] ), .F0(N_596), - .F1(\wb_dati_5_1_iv_i_i_1[3] )); - SLICE_72 SLICE_72( .D1(RCKE_c), .C1(RASr2), .B1(N_522), .A1(nRRAS_0_sqmuxa), - .C0(CO0), .B0(\S[1] ), .A0(Ready), .F0(nRRAS_0_sqmuxa), - .F1(nRCS_9_u_i_0_o3)); - SLICE_73 SLICE_73( .D1(\wb_dati[2] ), .C1(\wb_dati_5_1_iv_i_i_a3_3_0[3] ), - .B1(InitReady), .A1(N_502), .D0(\FS[12] ), .C0(\FS[9] ), .B0(\FS[10] ), - .A0(\FS[11] ), .F0(\wb_dati_5_1_iv_i_i_a3_3_0[3] ), - .F1(\wb_dati_5_1_iv_i_i_0[3] )); - SLICE_74 SLICE_74( .D1(\IS[2] ), .C1(\IS[3] ), .A1(\IS[1] ), .D0(InitReady), - .C0(un1_nRCAS_6_sqmuxa_i_0_0_o2_0), .B0(RASr2), .A0(Ready), .F0(N_408), - .F1(un1_nRCAS_6_sqmuxa_i_0_0_o2_0)); - SLICE_75 SLICE_75( .D1(\FS[14] ), .B1(InitReady), .D0(\FS[12] ), .C0(N_207), - .B0(N_515), .A0(\FS[11] ), .F0(\wb_adr_5_i_0_0[1] ), .F1(N_515)); - SLICE_76 SLICE_76( .D1(\FS[10] ), .C1(\FS[11] ), .B1(\FS[14] ), - .A1(\FS[13] ), .D0(N_214), .C0(N_217), .B0(\FS[9] ), .A0(\FS[12] ), - .F0(N_486), .F1(N_217)); - SLICE_77 SLICE_77( .D1(\FS[13] ), .C1(\FS[12] ), .B1(\FS[14] ), .A1(N_214), - .D0(\FS[9] ), .C0(N_578), .B0(\FS[10] ), .A0(\FS[11] ), .F0(N_484), - .F1(N_578)); - SLICE_78 SLICE_78( .D1(N_221), .C1(\IS[0] ), .B1(N_216), - .A1(un1_nRCAS_6_sqmuxa_i_0_0_o2_0), .D0(nRRAS_0_sqmuxa), .C0(N_522), - .B0(RASr2), .A0(RCKE_c), .F0(N_246_i), .F1(N_522)); - SLICE_79 SLICE_79( .D1(InitReady), .A1(RASr2), .D0(CO0), .C0(N_221), - .B0(\S[1] ), .A0(Ready), .F0(N_360_i), .F1(N_221)); - SLICE_80 SLICE_80( .D1(\MAin_c[1] ), .C1(N_518), .B1(N_593), - .D0(un1_CmdEnable20_0_0_0), .C0(un1_CmdEnable20_0_0_a3_1_1), - .B0(un1_CmdEnable20_0_0_o3), .A0(C1Submitted), .M1(nCCAS_c_i), - .M0(nCCAS_c_i), .CLK(nCRAS_c), .F0(un1_CmdEnable20_i), .Q0(CBR), - .F1(un1_CmdEnable20_0_0_a3_1_1), .Q1(CBR_fast)); - SLICE_81 SLICE_81( .D1(\S[1] ), .C1(Ready), .A1(CBR), .D0(nRWE_s_i_0_tz_0), - .C0(N_590), .B0(N_595), .A0(nRCAS_0_sqmuxa_1), .F0(N_49_i), .F1(N_590)); - SLICE_82 SLICE_82( .D1(\Din_c[5] ), .C1(\Din_c[4] ), .B1(N_213), - .A1(\Din_c[3] ), .C0(N_531), .B0(XOR8MEG18), .M0(\Din_c[0] ), - .CE(CmdUFMData_1_sqmuxa), .CLK(PHI2_c), .F0(CmdUFMData_1_sqmuxa), - .Q0(CmdUFMData), .F1(N_531)); - SLICE_83 SLICE_83( .D1(CO0), .B1(FWEr), .D0(N_595), .C0(nRCS_9_u_i_0_o3), - .B0(N_590), .A0(N_248_i_1_0), .F0(N_247_i), .F1(N_248_i_1_0)); - SLICE_84 SLICE_84( .D1(\Bank[1] ), .C1(\Bank[3] ), .B1(\Bank[4] ), - .A1(\Bank[5] ), .D0(un1_CmdEnable20_0_0_o3_10), - .C0(un1_CmdEnable20_0_0_o3_11), .B0(\Bank[7] ), .A0(\Bank[6] ), - .F0(un1_CmdEnable20_0_0_o3), .F1(un1_CmdEnable20_0_0_o3_11)); - SLICE_85 SLICE_85( .D1(N_576), .C1(N_537), .B1(\FS[10] ), .A1(N_514), - .D0(InitReady), .C0(\wb_dati[5] ), .B0(N_473), .A0(N_472), - .F0(\wb_dati_5_1_iv_0_1[6] ), .F1(N_473)); - SLICE_86 SLICE_86( .D1(\FS[11] ), .C1(N_536), .B1(N_207), .A1(N_502), - .D0(N_479), .C0(\wb_dati[3] ), .B0(InitReady), .A0(N_473), - .F0(\wb_dati_5_1_iv_0_1[4] ), .F1(N_479)); - SLICE_87 SLICE_87( .D1(N_214), .C1(\FS[14] ), .A1(\FS[12] ), .D0(\FS[10] ), - .C0(N_579), .B0(\FS[11] ), .A0(\FS[13] ), .F0(N_488), .F1(N_579)); - SLICE_88 SLICE_88( .D1(CO0), .C1(\S[1] ), .B1(Ready), .A1(N_221), - .D0(\IS[3] ), .C0(\IS[1] ), .B0(\IS[2] ), .A0(nRCS_9_u_i_0_o2_1_RNIL2K71), - .F0(RA10s_i), .F1(nRCS_9_u_i_0_o2_1_RNIL2K71)); - SLICE_89 SLICE_89( .C1(\FS[9] ), .B1(\FS[10] ), .D0(\FS[13] ), .C0(N_236), - .B0(N_579), .A0(\FS[11] ), .F0(N_472), .F1(N_236)); - SLICE_90 SLICE_90( .D1(\IS[1] ), .C1(nRCS_9_u_i_0_o2_1_RNIL2K71), - .B1(\IS[0] ), .A1(\IS[2] ), .D0(nRRAS_0_sqmuxa), .C0(nRWE_s_i_0_a3_1_0), - .B0(RCKE_c), .A0(RASr2), .F0(nRWE_s_i_0_tz_0), .F1(nRWE_s_i_0_a3_1_0)); - SLICE_91 SLICE_91( .D1(N_214), .C1(\FS[13] ), .B1(\FS[9] ), .A1(N_209), - .D0(InitReady), .C0(\wb_dati[0] ), .B0(N_412), .A0(N_477), - .F0(\wb_dati_5_1_iv_0_1[1] ), .F1(N_412)); - SLICE_92 SLICE_92( .D1(wb_req), .C1(\FS[0] ), .B1(N_471_3), .D0(N_471_2), - .C0(wb_ack), .B0(wb_cyc_stb_2_sqmuxa_i_a3_0), .A0(N_214), .F0(N_178), - .F1(wb_cyc_stb_2_sqmuxa_i_a3_0)); - SLICE_93 SLICE_93( .D1(\MAin_c[7] ), .C1(\MAin_c[2] ), .B1(\MAin_c[3] ), - .A1(\MAin_c[5] ), .D0(\Bank[0] ), .C0(\Bank[2] ), - .B0(un1_CmdEnable20_0_0_o3_4), .A0(un1_CmdEnable20_0_0_o3_3), - .F0(un1_CmdEnable20_0_0_o3_10), .F1(un1_CmdEnable20_0_0_o3_4)); - SLICE_94 SLICE_94( .D1(N_248_i_1), .C1(N_248_i_1_0), .B1(N_248_i_sx), - .A1(N_248_i_1_1), .D0(nRCAS_r_i_0_o2_0_0), .C0(FWEr), .B0(N_267), .A0(CBR), - .F0(N_248_i_1), .F1(N_248_i)); - SLICE_95 SLICE_95( .D1(\FS[12] ), .A1(\FS[13] ), .D0(N_536), .C0(InitReady), - .B0(N_207), .A0(\FS[11] ), .F0(N_427), .F1(N_536)); - SLICE_96 SLICE_96( .D1(\FS[14] ), .C1(InitReady), .D0(N_511), .C0(N_404), - .B0(\FS[12] ), .A0(\FS[13] ), .F0(\wb_adr_5_i_0_0[0] ), .F1(N_511)); - SLICE_97 SLICE_97( .C1(\FS[16] ), .B1(\FS[17] ), .D0(N_210), - .C0(\wb_dati[7] ), .B0(InitReady), .A0(\FS[15] ), .F0(N_383), .F1(N_210)); - SLICE_98 SLICE_98( .B1(\FS[4] ), .A1(\FS[3] ), .D0(\FS[2] ), .C0(\FS[7] ), - .B0(wb_cyc_stb_4_iv_0_a3_0_2_0), .A0(\FS[6] ), .F0(N_471_2), - .F1(wb_cyc_stb_4_iv_0_a3_0_2_0)); - SLICE_99 SLICE_99( .C1(\Din_c[3] ), .B1(\Din_c[5] ), .D0(\MAin_c[0] ), - .C0(\Din_c[6] ), .B0(N_505), .A0(\Din_c[2] ), .F0(N_593), .F1(N_505)); - SLICE_100 SLICE_100( .C1(\Din_c[7] ), .A1(\Din_c[6] ), - .D0(XOR8MEG_3_u_0_0_0_a2), .C0(N_213), .B0(N_539), .A0(\Din_c[3] ), - .F0(XOR8MEG_3_u_0_0_a3_0_2), .F1(N_213)); - SLICE_101 SLICE_101( .D1(\FS[14] ), .C1(\FS[12] ), .D0(N_537), .C0(\FS[10] ), - .B0(\FS[9] ), .A0(N_514), .F0(\wb_dati_5_1_iv_0_a3_0_1[7] ), .F1(N_537)); - SLICE_102 SLICE_102( .D1(\FS[11] ), .A1(\FS[13] ), .D0(\FS[10] ), - .C0(\FS[12] ), .B0(\FS[14] ), .A0(N_514), .F0(\wb_dati_5_0_iv_0_a3_1[0] ), - .F1(N_514)); - SLICE_103 SLICE_103( .C1(PHI2r3), .B1(PHI2r2), .D0(CmdValid_fast), - .C0(CmdUFMShift), .B0(G_4_0_a3_0), .A0(InitReady), .F0(un1_wb_rst14_i_0), + SLICE_56 SLICE_56( .D1(\FS[14] ), .C1(\FS[13] ), .B1(\FS[12] ), + .A1(un1_wb_rst14_2_0_o2), .D0(N_122_i), .C0(un1_wb_rst14_2_i), .A0(wb_req), + .DI0(wb_reqe_0), .LSR(wb_rst10), .CLK(RCLK_c), .F0(wb_reqe_0), .Q0(wb_req), + .F1(un1_wb_rst14_2_i)); + SLICE_57 SLICE_57( .D1(PHI2r2), .C1(PHI2r3), .B1(InitReady), .A1(CmdValid), + .D0(wb_rst), .C0(N_122_i), .A0(wb_rst_3), .DI0(wb_rste_0), .CLK(RCLK_c), + .F0(wb_rste_0), .Q0(wb_rst), .F1(N_122_i)); + SLICE_58 SLICE_58( .C1(InitReady), .B1(\FS[17] ), .A1(\FS[16] ), + .D0(wb_we_0_0_i_1), .C0(InitReady), .B0(un1_wb_rst14_2_0_o2), + .A0(CmdUFMData), .DI0(N_346_i), .CE(N_126_i), .LSR(wb_rst10), .CLK(RCLK_c), + .F0(N_346_i), .Q0(wb_we), .F1(un1_wb_rst14_2_0_o2)); + wb_dati_5_1_iv_0_0_o2_5__SLICE_59 \wb_dati_5_1_iv_0_0_o2[5]/SLICE_59 ( + .D1(\FS[12] ), .C1(\wb_dati_5_1_iv_0_o2[7] ), .B1(\FS_RNIHVJI[15] ), + .A1(\wb_dati_5_1_iv_0_o2_0_RNIMDJC1[4] ), .D0(\FS[13] ), + .C0(\wb_dati_5_1_iv_0_0_o2[3] ), .B0(\FS_RNIHVJI[15] ), + .A0(\wb_dati_5_1_iv_0_o2_0_RNIMDJC1[4] ), .M0(\FS[9] ), + .OFX0(\wb_dati_5_1_iv_0_0_o2[5] )); + wb_adr_5_i_0_1_0__SLICE_60 \wb_adr_5_i_0_1[0]/SLICE_60 ( .D1(\FS[13] ), + .C1(\FS_RNIJO0F[12] ), .A1(\wb_dati_5_1_iv_0_o2_0[7] ), .D0(InitReady), + .C0(\FS[9] ), .B0(\FS_RNI9Q57[12] ), .A0(\FS[10] ), .M0(\FS[11] ), + .OFX0(\wb_adr_5_i_0_1[0] )); + SLICE_61 SLICE_61( .D1(N_313), .C1(InitReady), .B1(\FS[14] ), + .A1(\FS_RNI9Q57[12] ), .D0(\FS[13] ), .C0(\wb_adr_5_i_0_o2[0] ), + .B0(\FS[14] ), .A0(InitReady), .F0(N_313), .F1(\wb_adr_5_i_0_0[0] )); + SLICE_62 SLICE_62( .D1(InitReady), .C1(CO0), .B1(\S[1] ), .A1(RASr2), + .D0(\S[1] ), .C0(IS_0_sqmuxa_0_o2), .B0(Ready), + .A0(un1_nRCAS_6_sqmuxa_i_o2), .F0(N_48), .F1(IS_0_sqmuxa_0_o2)); + SLICE_63 SLICE_63( .D1(\Din_c[3] ), .C1(\MAin_c[0] ), .B1(N_466), + .A1(\Din_c[6] ), .D0(N_483), .C0(\MAin_c[0] ), .B0(N_457), + .A0(\MAin_c[1] ), .F0(un1_CmdEnable20_0_0_0), .F1(N_483)); + SLICE_64 SLICE_64( .D1(\FS[16] ), .C1(\FS[17] ), .B1(\FS[15] ), + .A1(InitReady), .D0(\wb_dati[0] ), .C0(InitReady), .B0(\FS_RNIHVJI[15] ), + .A0(\wb_dati_5_1_iv_0_a2_0_2[1] ), .F0(\wb_dati_5_1_iv_0_0[1] ), + .F1(\FS_RNIHVJI[15] )); + SLICE_65 SLICE_65( .D1(\FS[9] ), .C1(\wb_dati_5_1_iv_0_0_o2[4] ), + .B1(\FS[10] ), .A1(\wb_dati_5_1_iv_0_a2_13[3] ), .D0(\FS[11] ), + .C0(\FS[13] ), .B0(\FS[10] ), .F0(\wb_dati_5_1_iv_0_0_o2[4] ), + .F1(\wb_dati_5_1_iv_0_1_0[4] )); + SLICE_66 SLICE_66( .D1(\FS[10] ), .C1(\FS[11] ), .B1(\FS[9] ), + .D0(\ufmefb/g0_0_a3_2 ), .C0(\FS_RNIF2MA[9] ), .A0(\FS_RNIHVJI[15] ), + .F0(N_4), .F1(\FS_RNIF2MA[9] )); + SLICE_67 SLICE_67( .D1(\wb_dati_5_1_iv_0_0_o2[4] ), .C1(\FS[9] ), + .B1(\wb_adr_5_i_0_1[0] ), .A1(\FS_RNIJO0F[12] ), .D0(\FS[14] ), + .B0(InitReady), .A0(\FS[12] ), .F0(\FS_RNIJO0F[12] ), + .F1(\wb_adr_5_i_0_3[0] )); + SLICE_68 SLICE_68( .D1(RASr2), .C1(nRWE_s_i_a2_1_0), .B1(RCKE_c), + .A1(nRRAS_0_sqmuxa), .D0(Ready), .C0(\S[1] ), .B0(CO0), + .F0(nRRAS_0_sqmuxa), .F1(nRWE_s_i_tz_0)); + SLICE_69 SLICE_69( .D1(CBR), .C1(nRCS_9_u_i_o3_0_0), .B1(FWEr), + .A1(RCKEEN_8_u_0_o3), .D0(N_48), .C0(CASr2), .A0(CO0), + .F0(nRCS_9_u_i_o3_0_0), .F1(nRCS_9_u_i_o3_0_2)); + SLICE_70 SLICE_70( .D1(\wb_adr_5_i_0_a2_6[0] ), .C1(\FS_RNI9Q57[12] ), + .B1(\FS_RNIOVGI[9] ), .A1(wb_we_0_0_i_1_1), .D0(\FS[11] ), .C0(\FS[10] ), + .B0(InitReady), .A0(\FS[9] ), .F0(\FS_RNIOVGI[9] ), .F1(wb_we_0_0_i_1)); + SLICE_71 SLICE_71( .C1(\FS[9] ), .A1(\FS[10] ), + .D0(\wb_adr_5_i_3_0_a2_3[1] ), .C0(\FS_RNIS637[9] ), .B0(\FS[12] ), + .A0(\FS[11] ), .F0(\wb_adr_5_i_3_0_0[1] ), .F1(\FS_RNIS637[9] )); + SLICE_72 SLICE_72( .D1(\FS[9] ), .C1(\FS[10] ), .B1(\FS[11] ), .D0(\FS[12] ), + .C0(\wb_dati_5_1_iv_0_o2_0[4] ), .B0(\FS[13] ), .A0(\FS_RNI7U6M[14] ), + .F0(\wb_dati_5_1_iv_0_o2_0_RNIMDJC1[4] ), .F1(\wb_dati_5_1_iv_0_o2_0[4] )); + SLICE_73 SLICE_73( .D1(\FS[14] ), .C1(\wb_dati_5_1_iv_0_a2_5[7] ), + .A1(\wb_dati_5_1_iv_0_0_o2[4] ), .D0(\FS[12] ), .C0(\FS[9] ), + .B0(\wb_dati_5_1_iv_0_o2[7] ), .A0(\FS_RNIHVJI[15] ), + .F0(\wb_dati_5_1_iv_0_1_RNO[7] ), .F1(\wb_dati_5_1_iv_0_o2[7] )); + SLICE_74 SLICE_74( .D1(\FS[13] ), .C1(\FS[12] ), .B1(\FS[14] ), + .A1(\FS_RNIHVJI[15] ), .D0(\FS_RNIGOCT[12] ), .C0(\FS[9] ), .B0(\FS[11] ), + .A0(\FS[10] ), .F0(\wb_dati_5_1_iv_0_RNO[7] ), .F1(\FS_RNIGOCT[12] )); + SLICE_75 SLICE_75( .D1(CBR_fast), .C1(CO0), .B1(m3_0_a2_0), .A1(Ready), + .D0(nRWE_s_i_tz_0), .C0(N_142), .B0(nRCAS_0_sqmuxa_1), .A0(N_141), + .F0(N_252_i), .F1(nRCAS_0_sqmuxa_1)); + SLICE_76 SLICE_76( .D1(\MAin_c[1] ), .C1(N_457), .A1(N_482), .D0(N_367), + .C0(un1_CmdEnable20_0_0_a2_1_1), .B0(un1_CmdEnable20_0_0_0), + .A0(C1Submitted), .M1(nCCAS_c_i), .M0(nCCAS_c_i), .CLK(nCRAS_c), + .F0(un1_CmdEnable20_i), .Q0(CBR), .F1(un1_CmdEnable20_0_0_a2_1_1), + .Q1(CBR_fast)); + SLICE_77 SLICE_77( .D1(\Din_c[3] ), .C1(N_353), .B1(\Din_c[4] ), + .A1(\Din_c[5] ), .C0(XOR8MEG18), .B0(N_461), .M0(CASr2), .CLK(RCLK_c), + .F0(CmdUFMData_1_sqmuxa), .Q0(CASr3), .F1(N_461)); + SLICE_78 SLICE_78( .D1(CO0), .A1(FWEr), .D0(N_251_i_1), .C0(N_142), + .B0(nRCS_9_u_i_0), .A0(N_141), .F0(N_37_i), .F1(N_251_i_1)); + SLICE_79 SLICE_79( .C1(Ready), .A1(IS_0_sqmuxa_0_o2), .D0(\IS[1] ), + .C0(IS_0_sqmuxa_0_o3), .B0(\IS[3] ), .A0(\IS[2] ), .F0(RA10s_i), + .F1(IS_0_sqmuxa_0_o3)); + SLICE_80 SLICE_80( .D1(\Bank[3] ), .C1(\Bank[6] ), .B1(\Bank[2] ), + .A1(\Bank[5] ), .D0(\Bank[4] ), .C0(un1_CmdEnable20_0_0_o2_11), + .B0(\Bank[0] ), .A0(un1_CmdEnable20_0_0_o2_10), .F0(N_367), + .F1(un1_CmdEnable20_0_0_o2_11)); + SLICE_81 SLICE_81( .D1(\wb_dati_5_1_iv_0_a2_12[3] ), + .C1(\wb_dati_5_1_iv_0_a2_6[4] ), .B1(\wb_dati_5_1_iv_0_a2_7[4] ), + .A1(\FS[10] ), .D0(\wb_dati_5_1_iv_0_0_a2[6] ), + .C0(\wb_dati_5_1_iv_0_a2_2[4] ), .B0(InitReady), .A0(\wb_dati[5] ), + .F0(\wb_dati_5_1_iv_0_0_1[6] ), .F1(\wb_dati_5_1_iv_0_a2_2[4] )); + SLICE_82 SLICE_82( .D1(\FS[10] ), .C1(\FS[9] ), + .B1(\wb_dati_5_1_iv_0_a2_0_0[7] ), .A1(\FS_RNIHVJI[15] ), .D0(InitReady), + .C0(\wb_dati_5_1_iv_0_1_RNO[7] ), .B0(\wb_dati_5_1_iv_0_a2_0[7] ), + .A0(\wb_dati[6] ), .F0(\wb_dati_5_1_iv_0_1[7] ), + .F1(\wb_dati_5_1_iv_0_a2_0[7] )); + SLICE_83 SLICE_83( .D1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[3] ), + .D0(nRCS_9_u_i_0_0), .C0(un1_nRCAS_6_sqmuxa_i_o2), .B0(IS_0_sqmuxa_0_o2), + .A0(\IS[0] ), .F0(nRCS_9_u_i_0), .F1(un1_nRCAS_6_sqmuxa_i_o2)); + SLICE_84 SLICE_84( .D1(\FS[14] ), .C1(\FS[12] ), .A1(\FS_RNIHVJI[15] ), + .D0(\wb_dati_5_1_iv_0_a2_13[3] ), .C0(\wb_dati_5_1_iv_0_o2_0[7] ), + .B0(\FS[13] ), .A0(\FS[11] ), .F0(\wb_dati_5_1_iv_0_0_a2[6] ), + .F1(\wb_dati_5_1_iv_0_a2_13[3] )); + SLICE_85 SLICE_85( .D1(\FS[10] ), .C1(\FS[12] ), .B1(\FS[14] ), + .A1(\FS[11] ), .D0(\FS[13] ), .C0(\wb_dati_5_1_iv_0_0_o2[3] ), + .B0(\wb_dati_5_1_iv_0_0[1] ), .A0(\wb_dati_5_1_iv_0_a2_12[3] ), + .F0(\wb_dati_5_1_iv_0_1[1] ), .F1(\wb_dati_5_1_iv_0_0_o2[3] )); + SLICE_86 SLICE_86( .D1(\FS_RNI7U6M[14] ), .C1(\FS[12] ), + .B1(\FS_RNIS637[9] ), .A1(\FS[11] ), .D0(\wb_dati[2] ), .C0(InitReady), + .B0(\wb_dati_5_1_iv_0_a2_7[3] ), .F0(\wb_dati_5_1_iv_0_0_0[3] ), + .F1(\wb_dati_5_1_iv_0_a2_7[3] )); + SLICE_87 SLICE_87( .D1(\FS_RNIHVJI[15] ), .B1(\FS[9] ), + .D0(\wb_dati_5_1_iv_0_a2_5[3] ), .C0(\wb_dati_5_1_iv_0_a2_12[3] ), + .B0(\wb_dati_5_1_iv_0_0_o2[3] ), .A0(\FS[13] ), + .F0(\wb_dati_5_1_iv_0_0_1[3] ), .F1(\wb_dati_5_1_iv_0_a2_12[3] )); + SLICE_88 SLICE_88( .D1(\FS[14] ), .C1(\FS_RNIHVJI[15] ), .D0(\FS[11] ), + .C0(\FS_RNI7U6M[14] ), .B0(\FS_RNIS637[9] ), + .A0(\wb_dati_5_1_iv_0_a2_11[3] ), .F0(\wb_dati_5_1_iv_0_a2_5[3] ), + .F1(\FS_RNI7U6M[14] )); + SLICE_89 SLICE_89( .D1(wb_req), .C1(\FS[0] ), .B1(N_99_1), + .D0(wb_cyc_stb_2_sqmuxa_i_0_0_a2_0), .C0(N_99_2), .B0(\FS_RNIHVJI[15] ), + .A0(wb_ack), .F0(wb_cyc_stb_2_sqmuxa_i_0_0), + .F1(wb_cyc_stb_2_sqmuxa_i_0_0_a2_0)); + SLICE_90 SLICE_90( .D1(\MAin_c[4] ), .C1(\MAin_c[7] ), .B1(\MAin_c[6] ), + .A1(nFWE_c), .D0(\Bank[1] ), .C0(\Bank[7] ), .B0(un1_CmdEnable20_0_0_o2_4), + .A0(un1_CmdEnable20_0_0_o2_3), .F0(un1_CmdEnable20_0_0_o2_10), + .F1(un1_CmdEnable20_0_0_o2_4)); + SLICE_91 SLICE_91( .D1(\FS[17] ), .C1(\FS[16] ), .A1(\FS[15] ), + .D0(\wb_adr_5_i_0_0[0] ), .C0(InitReady), .B0(\wb_dati[7] ), + .A0(\FS_RNI82PA[15] ), .F0(\wb_adr_5_i_0_2[0] ), .F1(\FS_RNI82PA[15] )); + SLICE_92 SLICE_92( .C1(\Din_c[3] ), .A1(\Din_c[5] ), .D0(\Din_c[6] ), + .C0(N_442), .B0(\Din_c[2] ), .A0(\MAin_c[0] ), .F0(N_482), .F1(N_442)); + SLICE_93 SLICE_93( .D1(\wb_dati_5_1_iv_0_o2_0[4] ), + .C1(\wb_dati_5_1_iv_0_a2_11[3] ), .B1(InitReady), .A1(wb_we_0_0_i_a2_0), + .D0(\wb_adr_5_i_0_a2_6[0] ), .C0(\FS[12] ), .B0(\FS_RNIS637[9] ), + .A0(\FS[13] ), .F0(wb_we_0_0_i_a2_0), .F1(wb_we_0_0_i_1_1)); + SLICE_94 SLICE_94( .D1(\FS[14] ), .A1(InitReady), .D0(\FS[16] ), + .C0(\FS[17] ), .B0(\wb_adr_5_i_3_0_a2_3[1] ), .A0(\FS[15] ), .F0(wb_rst_3), + .F1(\wb_adr_5_i_3_0_a2_3[1] )); + SLICE_95 SLICE_95( .D1(\FS[7] ), .B1(\FS[1] ), .D0(\FS[5] ), + .C0(wb_cyc_stb_2_sqmuxa_i_a2_2_0), .B0(\FS[4] ), .A0(\FS[2] ), .F0(N_99_2), + .F1(wb_cyc_stb_2_sqmuxa_i_a2_2_0)); + SLICE_96 SLICE_96( .C1(\Din_c[7] ), .A1(\Din_c[6] ), .D0(\Din_c[3] ), + .C0(N_452), .B0(N_353), .A0(N_466), .F0(XOR8MEG_3_u_0_0_a2_0_2), + .F1(N_353)); + SLICE_97 SLICE_97( .C1(\FS[10] ), .B1(\FS[9] ), + .D0(\wb_dati_5_1_iv_0_o2_0[7] ), .C0(\FS[11] ), .B0(\FS[13] ), + .A0(\wb_dati_5_1_iv_0_a2_7[4] ), .F0(\wb_dati_5_1_iv_0_a2_0_2[1] ), + .F1(\wb_dati_5_1_iv_0_o2_0[7] )); + SLICE_98 SLICE_98( .D1(\FS[11] ), .B1(\FS[13] ), .D0(\FS[14] ), + .C0(\FS[12] ), .B0(\wb_dati_5_1_iv_0_a2_6[4] ), .A0(\FS[10] ), + .F0(\wb_dati_5_0_iv_0_a2_1[0] ), .F1(\wb_dati_5_1_iv_0_a2_6[4] )); + SLICE_99 SLICE_99( .D1(\FS_RNI9Q57[12] ), .C1(\FS[14] ), + .B1(InitReady3_0_a2_1_0), .A1(\FS[11] ), .D0(\FS[16] ), .C0(\FS[10] ), + .B0(\FS[17] ), .A0(\FS[15] ), .F0(InitReady3_0_a2_1_0), .F1(InitReady3)); + SLICE_100 SLICE_100( .D1(PHI2r2), .A1(PHI2r3), .D0(CmdValid_fast), + .C0(InitReady), .B0(CmdUFMShift), .A0(G_4_0_a3_0), .F0(N_126_i), .F1(G_4_0_a3_0)); - SLICE_104 SLICE_104( .C1(\FS[14] ), .B1(\FS[13] ), .A1(\FS[12] ), - .D0(wb_ack), .C0(\FS[14] ), .B0(\FS[13] ), .A0(\FS[12] ), - .F0(\ufmefb/g0_0_a3_2 ), .F1(N_581)); - SLICE_105 SLICE_105( .D1(\FS[14] ), .C1(InitReady), .B1(N_226), - .A1(\FS[13] ), .D0(\FS[14] ), .C0(InitReady), .B0(\FS[13] ), - .F0(wb_we_0_i_0_a3_0_0), .F1(N_417)); - SLICE_106 SLICE_106( .D1(\FS[12] ), .C1(\FS[13] ), .B1(N_599), .A1(\FS[14] ), - .D0(\FS[12] ), .C0(\FS[13] ), .B0(N_599), .F0(N_423), .F1(N_416)); - SLICE_107 SLICE_107( .C1(CmdValid), .B1(PHI2r3), .A1(PHI2r2), .D0(InitReady), - .C0(CmdValid), .B0(PHI2r3), .A0(PHI2r2), .M0(CASr2), .CLK(RCLK_c), - .F0(N_92_i), .Q0(CASr3), .F1(un1_PHI2r3)); - SLICE_108 SLICE_108( .D1(FWEr), .C1(\S[1] ), .B1(CASr2), .A1(CO0), .D0(FWEr), - .C0(CASr3), .B0(CASr2), .A0(CO0), .F0(N_595), .F1(RCKEEN_8_u_0_1_0)); - SLICE_109 SLICE_109( .D1(\FS[10] ), .C1(\FS[9] ), .B1(\FS[13] ), - .A1(\FS[11] ), .D0(\FS[10] ), .C0(\FS[9] ), .A0(\FS[11] ), .F0(N_404), - .F1(\wb_dati_5_1_iv_i_i_a3_1[3] )); - SLICE_110 SLICE_110( .D1(\FS[13] ), .C1(\FS[11] ), .B1(\FS[12] ), - .A1(InitReady), .D0(\FS[10] ), .C0(\FS[14] ), .B0(\FS[11] ), .A0(\FS[12] ), - .F0(N_209), .F1(\wb_adr_5_i_0_a3_0_1[0] )); - SLICE_111 SLICE_111( .D1(nRowColSel), .A1(\MAin_c[9] ), .D0(nRowColSel), - .A0(\MAin_c[9] ), .F0(RDQMH_c), .F1(RDQML_c)); - SLICE_112 SLICE_112( .D1(\Din_c[1] ), .C1(\Din_c[4] ), .B1(\Din_c[7] ), - .A1(\Din_c[0] ), .C0(\Din_c[4] ), .A0(\Din_c[0] ), - .F0(XOR8MEG_3_u_0_0_0_a2), .F1(N_518)); - SLICE_113 SLICE_113( .D1(\FS[14] ), .C1(N_214), .C0(N_214), .B0(\FS[9] ), - .F0(N_576), .F1(N_502)); - SLICE_114 SLICE_114( .D1(nRowColSel), .C1(\RowA[6] ), .A1(\MAin_c[6] ), - .C0(nFWE_c), .B0(\MAin_c[4] ), .A0(\MAin_c[6] ), - .F0(un1_CmdEnable20_0_0_o3_3), .F1(\RA_c[6] )); - SLICE_115 SLICE_115( .D1(\RowA[9] ), .C1(nRowColSel), .A1(\MAin_c[9] ), - .D0(\MAin_c[8] ), .C0(nRowColSel), .B0(\RowA[8] ), .F0(\RA_c[8] ), + SLICE_101 SLICE_101( .D1(N_251_i_1), .C1(nRCS_9_u_i_o3_0_2), + .B1(N_251_i_1_0), .A1(N_251_i_sx), .D0(N_48), .C0(nRCAS_0_sqmuxa_1), + .B0(\S[1] ), .F0(N_251_i_sx), .F1(N_251_i)); + SLICE_102 SLICE_102( .D1(\FS[11] ), .C1(\FS[14] ), .B1(\FS[13] ), + .A1(\FS[12] ), .D0(\FS[14] ), .C0(wb_ack), .B0(\FS[13] ), .A0(\FS[12] ), + .F0(\ufmefb/g0_0_a3_2 ), .F1(\wb_dati_5_1_iv_0_a2_0_0[7] )); + SLICE_103 SLICE_103( .D1(CASr2), .C1(\S[1] ), .B1(CO0), .A1(FWEr), .D0(FWEr), + .C0(CASr2), .B0(CO0), .A0(CASr3), .F0(N_142), .F1(RCKEEN_8_u_1)); + SLICE_104 SLICE_104( .D1(\FS[13] ), .C1(\FS[9] ), .B1(\FS[11] ), + .A1(\FS[10] ), .D0(\FS[13] ), .B0(\FS[11] ), .A0(\FS[10] ), + .F0(\wb_dati_5_1_iv_0_a2_5[7] ), .F1(\wb_dati_5_1_iv_0_0_a2_1[3] )); + SLICE_105 SLICE_105( .D1(\FS[13] ), .A1(\FS[12] ), .D0(\FS_RNIOVGI[9] ), + .C0(\FS[14] ), .B0(\FS[13] ), .A0(\FS[12] ), .F0(\wb_adr_5_i_3_0_a2[1] ), + .F1(\FS_RNI9Q57[12] )); + SLICE_106 SLICE_106( .D1(CBR), .C1(Ready), .B1(\S[1] ), .D0(CBR), .C0(Ready), + .B0(nCRAS_c), .A0(LEDEN), .F0(LED_c), .F1(N_141)); + SLICE_107 SLICE_107( .C1(\FS[14] ), .A1(InitReady), .D0(\FS[13] ), + .C0(InitReady), .B0(\FS_RNIF2MA[9] ), .A0(\FS[14] ), + .F0(\wb_adr_5_i_3_0_a2_0[1] ), .F1(\wb_adr_5_i_0_a2_6[0] )); + SLICE_108 SLICE_108( .C1(nRowColSel), .B1(\MAin_c[9] ), .C0(nRowColSel), + .B0(\MAin_c[9] ), .F0(RDQMH_c), .F1(RDQML_c)); + SLICE_109 SLICE_109( .D1(\Din_c[7] ), .C1(\Din_c[0] ), .B1(\Din_c[4] ), + .A1(\Din_c[1] ), .C0(\Din_c[0] ), .B0(\Din_c[4] ), .F0(N_452), .F1(N_457)); + SLICE_110 SLICE_110( .D1(PHI2r2), .C1(PHI2r3), .D0(PHI2r2), .C0(PHI2r3), + .A0(CmdValid), .F0(un1_PHI2r3_i_li), .F1(g1_0)); + SLICE_111 SLICE_111( .D1(InitReady), .C1(\wb_dato[0] ), .A1(Cmdn8MEGEN), + .D0(InitReady), .C0(\wb_dati_5_1_iv_0_o2_0_RNIMDJC1[4] ), + .B0(\wb_dati_5_1_iv_0_a2_2[4] ), .A0(\wb_dati[3] ), + .F0(\wb_dati_5_1_iv_0_0_1[4] ), .F1(n8MEGENe_1_0)); + SLICE_112 SLICE_112( .D1(\RowA[2] ), .B1(\MAin_c[2] ), .A1(nRowColSel), + .C0(\MAin_c[5] ), .B0(\MAin_c[2] ), .A0(\MAin_c[3] ), + .F0(un1_CmdEnable20_0_0_o2_3), .F1(\RA_c[2] )); + SLICE_113 SLICE_113( .D1(nRowColSel), .C1(\MAin_c[8] ), .A1(\RowA[8] ), + .D0(nRowColSel), .B0(\RowA[0] ), .A0(\MAin_c[0] ), .F0(\RA_c[0] ), + .F1(\RA_c[8] )); + SLICE_114 SLICE_114( .D1(nRowColSel), .C1(\RowA[3] ), .B1(\MAin_c[3] ), + .C0(\MAin_c[1] ), .B0(nRowColSel), .A0(\RowA[1] ), .F0(\RA_c[1] ), + .F1(\RA_c[3] )); + SLICE_115 SLICE_115( .D1(\RowA[9] ), .C1(nRowColSel), .B1(\MAin_c[9] ), + .D0(nRowColSel), .C0(\MAin_c[4] ), .A0(\RowA[4] ), .F0(\RA_c[4] ), .F1(\RA_c[9] )); - SLICE_116 SLICE_116( .D1(\RowA[7] ), .C1(nRowColSel), .B1(\MAin_c[7] ), - .D0(nRowColSel), .B0(\MAin_c[0] ), .A0(\RowA[0] ), .F0(\RA_c[0] ), + SLICE_116 SLICE_116( .C1(nRowColSel), .B1(\RowA[7] ), .A1(\MAin_c[7] ), + .D0(\RowA[5] ), .C0(nRowColSel), .A0(\MAin_c[5] ), .F0(\RA_c[5] ), .F1(\RA_c[7] )); - SLICE_117 SLICE_117( .D1(\MAin_c[5] ), .C1(\RowA[5] ), .A1(nRowColSel), - .C0(nRowColSel), .B0(\RowA[1] ), .A0(\MAin_c[1] ), .F0(\RA_c[1] ), - .F1(\RA_c[5] )); - SLICE_118 SLICE_118( .D1(nRowColSel), .C1(\MAin_c[4] ), .A1(\RowA[4] ), - .C0(\MAin_c[2] ), .B0(\RowA[2] ), .A0(nRowColSel), .F0(\RA_c[2] ), - .F1(\RA_c[4] )); - SLICE_119 SLICE_119( .D1(\Din_c[5] ), .C1(\Din_c[4] ), .B1(\Din_c[6] ), - .A1(\Din_c[7] ), .D0(\Din_c[5] ), .B0(\Din_c[2] ), .F0(N_539), - .F1(CmdLEDEN_4_u_i_0_a3_0_0)); - SLICE_120 SLICE_120( .C1(\CROW_c[1] ), .B1(Ready_fast), .D0(\Din_c[6] ), - .C0(XOR8MEG), .B0(Ready_fast), .A0(n8MEGEN), .F0(RA11d_0), + SLICE_117 SLICE_117( .D1(CO0), .A1(\S[1] ), .D0(CO0), .C0(CASr2), + .F0(RCKEEN_8_u_0_o3), .F1(N_70_i)); + SLICE_118 SLICE_118( .D1(\FS[14] ), .C1(\FS[12] ), .C0(\FS[12] ), + .B0(\FS[13] ), .F0(\wb_dati_5_1_iv_0_a2_11[3] ), + .F1(\wb_dati_5_1_iv_0_a2_7[4] )); + SLICE_119 SLICE_119( .D1(\Din_c[7] ), .C1(\Din_c[4] ), .B1(\Din_c[5] ), + .A1(\Din_c[6] ), .B0(\Din_c[5] ), .A0(\Din_c[2] ), .F0(N_466), + .F1(CmdLEDEN_4_u_i_m2_i_a2_0_0)); + SLICE_120 SLICE_120( .C1(Ready_fast), .B1(\CROW_c[1] ), .D0(n8MEGEN), + .C0(Ready_fast), .B0(\Din_c[6] ), .A0(XOR8MEG), .F0(RA11d_0), .F1(\RBAd_0[1] )); - SLICE_121 SLICE_121( .B1(wb_req), .A1(\FS[0] ), .C0(\FS[8] ), .B0(\FS[5] ), - .A0(\FS[1] ), .F0(N_471_3), .F1(wb_cyc_stb_4_iv_0_a3_0_0)); - SLICE_122 SLICE_122( .D1(InitReady), .C1(\wb_dato[0] ), .A1(Cmdn8MEGEN), - .B0(PHI2r3), .A0(PHI2r2), .F0(g1_0), .F1(n8MEGENe_1_0)); - SLICE_123 SLICE_123( .D1(\FS[10] ), .B1(\FS[9] ), .C0(\FS[16] ), - .B0(\FS[17] ), .A0(\FS[15] ), .F0(InitReady3_0_a3_1), .F1(N_207)); + SLICE_121 SLICE_121( .D1(\FS[0] ), .A1(wb_req), .D0(\FS[3] ), .C0(\FS[6] ), + .B0(\FS[8] ), .F0(N_99_1), .F1(wb_cyc_stb_4_iv_0_0_a2_0_0)); + SLICE_122 SLICE_122( .D1(InitReady), .C1(\FS_RNI82PA[15] ), .B1(\wb_adr[0] ), + .D0(IS_0_sqmuxa_0_o2), .C0(Ready), .F0(N_261_i), .F1(N_216)); RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .IOLDO(\WRD[0] ), .PADDT(RD_1_i), .RD0(RD[0])); RD_0__MGIOL \RD[0]_MGIOL ( .IOLDO(\WRD[0] ), .OPOS(\Din_c[0] ), @@ -479,15 +523,18 @@ module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, RDQML RDQML_I( .PADDO(RDQML_c), .RDQML(RDQML)); RDQMH RDQMH_I( .PADDO(RDQMH_c), .RDQMH(RDQMH)); nRCAS nRCAS_I( .IOLDO(nRCAS_c), .nRCAS(nRCAS)); - nRCAS_MGIOL nRCAS_MGIOL( .IOLDO(nRCAS_c), .OPOS(N_248_i), .CLK(RCLK_c)); + nRCAS_MGIOL nRCAS_MGIOL( .IOLDO(nRCAS_c), .OPOS(N_251_i), .CLK(RCLK_c)); nRRAS nRRAS_I( .IOLDO(nRRAS_c), .nRRAS(nRRAS)); - nRRAS_MGIOL nRRAS_MGIOL( .IOLDO(nRRAS_c), .OPOS(N_246_i), .CLK(RCLK_c)); + nRRAS_MGIOL nRRAS_MGIOL( .IOLDO(nRRAS_c), .OPOS(N_32_i), .CLK(RCLK_c)); nRWE nRWE_I( .IOLDO(nRWE_c), .nRWE(nRWE)); - nRWE_MGIOL nRWE_MGIOL( .IOLDO(nRWE_c), .OPOS(N_49_i), .CLK(RCLK_c)); + nRWE_MGIOL nRWE_MGIOL( .IOLDO(nRWE_c), .OPOS(N_252_i), .CLK(RCLK_c)); RCKE RCKE_I( .PADDO(RCKE_c), .RCKE(RCKE)); + RCLKout RCLKout_I( .IOLDO(RCLKout_c), .RCLKout(RCLKout)); + RCLKout_MGIOL RCLKout_MGIOL( .IOLDO(RCLKout_c), .ONEG(VCC), .OPOS(GND), + .CLK(RCLK_c)); RCLK RCLK_I( .PADDI(RCLK_c), .RCLK(RCLK)); nRCS nRCS_I( .IOLDO(nRCS_c), .nRCS(nRCS)); - nRCS_MGIOL nRCS_MGIOL( .IOLDO(nRCS_c), .OPOS(N_247_i), .CLK(RCLK_c)); + nRCS_MGIOL nRCS_MGIOL( .IOLDO(nRCS_c), .OPOS(N_37_i), .CLK(RCLK_c)); RD_7_ \RD[7]_I ( .PADDI(\RD_in[7] ), .IOLDO(\WRD[7] ), .PADDT(RD_1_i), .RD7(RD[7])); RD_7__MGIOL \RD[7]_MGIOL ( .IOLDO(\WRD[7] ), .OPOS(\Din_c[7] ), @@ -955,12 +1002,12 @@ endmodule module lut4 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0F00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h00F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40003 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h5150) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0D0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module inverter ( input I, output Z ); @@ -1007,10 +1054,10 @@ module lut40005 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFAF2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_12 ( input D0, DI0, M1, CLK, output F0, Q0, Q1 ); +module SLICE_12 ( input A0, DI0, M1, CLK, output F0, Q0, Q1 ); wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; - lut40006 nCCAS_pad_RNISUR8( .A(GNDI), .B(GNDI), .C(GNDI), .D(D0), .Z(F0)); + lut40006 nCCAS_pad_RNISUR8( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre CASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); @@ -1019,7 +1066,7 @@ module SLICE_12 ( input D0, DI0, M1, CLK, output F0, Q0, Q1 ); .LSR(GNDI), .Q(Q0)); specify - (D0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); @@ -1032,24 +1079,27 @@ endmodule module lut40006 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h00FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h5555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_16 ( input C1, A1, C0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); +module SLICE_16 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, + F1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; - lut40007 nRowColSel_0_0_0_x2( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1)); + lut40007 Ready_0_sqmuxa_0_a2_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40008 \S_RNO[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40008 \S_RNO[0] ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre0009 \S[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); @@ -1064,12 +1114,12 @@ endmodule module lut40007 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h5A5A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40008 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hAFAF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module vmuxregsre0009 ( input D0, D1, SD, SP, CK, LSR, output Q ); @@ -1082,7 +1132,7 @@ module SLICE_17 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly; - lut40010 un1_CmdEnable20_0_0_a2_0_RNI00E51( .A(A1), .B(B1), .C(C1), .D(D1), + lut40010 un1_CmdEnable20_0_0_a2_3_RNIJ3N91( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40011 CmdEnable_s( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre CmdEnable( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), @@ -1110,19 +1160,19 @@ endmodule module lut40010 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40011 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFE2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFAEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_18 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; - lut40012 CmdLEDEN_4_u_i_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40012 CmdLEDEN_4_u_i_m2_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40013 CmdLEDEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre CmdLEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), @@ -1149,33 +1199,30 @@ endmodule module lut40012 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h44F4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h50DC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40013 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h3131) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0D0D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_20 ( input D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0 ); - wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly; +module SLICE_19 ( input B0, M0, CE, CLK, output F0, Q0 ); + wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; - lut40014 CmdUFMShift_3_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre CmdUFMShift( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + lut40014 RA10_0io_RNO( .A(GNDI), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CmdUFMData( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); specify - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify @@ -1183,25 +1230,21 @@ endmodule module lut40014 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h88F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h3333) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_21 ( input D1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, - F1 ); +module SLICE_20 ( input D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; - lut40015 CmdUFMWrite_3_u_0_0_0_a3( .A(A1), .B(GNDI), .C(GNDI), .D(D1), - .Z(F1)); + lut40015 GND( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40016 CmdUFMWrite_3_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre CmdUFMWrite( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + lut40016 CmdUFMShift_3_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdUFMShift( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); specify - (D1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); @@ -1217,19 +1260,58 @@ endmodule module lut40015 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hAA00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40016 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hF0F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hB3A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_22 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 ); +module SLICE_21 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; + + lut40017 CmdUFMWrite_3_u_0_0_0_a2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40018 CmdUFMWrite_3_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdUFMWrite( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40017 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40018 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF4F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_22 ( input D1, C1, B1, A1, D0, C0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly; - lut40017 CmdValid_2_i_o2_1_o3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40018 CmdValid_r( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); + lut40019 CmdValid_2_i_o2_0_o2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut4 CmdValid_r( .A(GNDI), .B(GNDI), .C(C0), .D(D0), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre CmdValid( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); @@ -1241,8 +1323,8 @@ module SLICE_22 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 ); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); @@ -1251,21 +1333,16 @@ module SLICE_22 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 ); endmodule -module lut40017 ( input A, B, C, D, output Z ); +module lut40019 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFF3B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40018 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0A0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hF7F5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_23 ( input D1, C1, B1, A1, C0, B0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly; - lut40019 CmdUFMData_1_sqmuxa_0_a3_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40020 CmdValid_r_fast( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40020 CmdUFMData_1_sqmuxa_0_a2_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40021 CmdValid_r_fast( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre CmdValid_fast( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); @@ -1287,22 +1364,22 @@ module SLICE_23 ( input D1, C1, B1, A1, C0, B0, DI0, CLK, output F0, Q0, F1 ); endmodule -module lut40019 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40020 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h3030) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_24 ( input D1, C1, B1, A1, D0, C0, B0, DI0, CE, CLK, output F0, +module lut40021 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0C0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_24 ( input D1, C1, B1, A1, D0, C0, A0, DI0, CE, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; - lut40021 Cmdn8MEGEN_4_u_i_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40022 Cmdn8MEGEN_RNO( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40022 Cmdn8MEGEN_4_u_i_m2_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40023 Cmdn8MEGEN_RNO( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre Cmdn8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); @@ -1316,7 +1393,7 @@ module SLICE_24 ( input D1, C1, B1, A1, D0, C0, B0, DI0, CE, CLK, output F0, (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); @@ -1326,31 +1403,31 @@ module SLICE_24 ( input D1, C1, B1, A1, D0, C0, B0, DI0, CE, CLK, output F0, endmodule -module lut40021 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hB3A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40022 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0F03) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hDC50) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_25 ( input B1, A1, A0, DI0, CLK, output F0, Q0, F1 ); +module lut40023 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0F05) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_25 ( input D1, A1, D0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly; - lut40023 nCCAS_pad_RNI01SJ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40024 nCCAS_pad_RNI01SJ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40024 FWEr_RNO( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); + lut40025 FWEr_RNO( .A(GNDI), .B(GNDI), .C(GNDI), .D(D0), .Z(F0)); vmuxregsre FWEr( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); specify - (B1 => F1) = (0:0:0,0:0:0); + (D1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); @@ -1359,29 +1436,33 @@ module SLICE_25 ( input B1, A1, A0, DI0, CLK, output F0, Q0, F1 ); endmodule -module lut40023 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40024 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h5555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFFAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_26 ( input B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); +module lut40025 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h00FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_26 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, + F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly; - lut40025 RCKEEN_8_u_0_0_o2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40026 nRRAS_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40027 \IS_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40026 \IS_RNO[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre \IS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); @@ -1392,23 +1473,23 @@ module SLICE_26 ( input B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); endmodule -module lut40025 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40026 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h9999) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h3031) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_27 ( input C1, B1, A1, C0, A0, DI1, DI0, CE, CLK, output F0, Q0, +module lut40027 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA9A9) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_27 ( input D1, B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40027 \IS_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40028 \IS_RNO[2] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40007 IS_n1_0_x2_0_x2( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); + lut40029 IS_n1_0_x2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre \IS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1416,10 +1497,10 @@ module SLICE_27 ( input C1, B1, A1, C0, A0, DI1, DI0, CE, CLK, output F0, Q0, .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify - (C1 => F1) = (0:0:0,0:0:0); + (D1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); @@ -1432,23 +1513,32 @@ module SLICE_27 ( input C1, B1, A1, C0, A0, DI1, DI0, CE, CLK, output F0, Q0, endmodule -module lut40027 ( input A, B, C, D, output Z ); +module lut40028 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h6A6A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h66AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_28 ( input B1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; +module lut40029 ( input A, B, C, D, output Z ); - lut40028 RA10_0io_RNO( .A(GNDI), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 \IS_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + ROM16X1A #(16'h6666) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_28 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40030 nRWE_s_i_a2_1_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40031 \IS_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \IS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); @@ -1462,21 +1552,21 @@ module SLICE_28 ( input B1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); endmodule -module lut40028 ( input A, B, C, D, output Z ); +module lut40030 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h3333) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40029 ( input A, B, C, D, output Z ); +module lut40031 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h6AAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h6CCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_29 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 ); +module SLICE_29 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly; - lut40030 InitReady3_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40031 InitReady_RNO( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); + lut40032 \FS_RNIHVJI_0[15] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40033 InitReady_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre InitReady( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); @@ -1487,41 +1577,6 @@ module SLICE_29 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 ); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40030 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40031 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_30 ( input C1, B1, A1, D0, B0, A0, DI0, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly; - - lut40032 LEDEN_6_i_m2_i_m2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40033 LEDENe( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); - vmuxregsre LEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); @@ -1534,19 +1589,55 @@ endmodule module lut40032 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hB8B8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40033 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hDD88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_31 ( input B0, A0, M1, M0, CLK, output F0, Q0, Q1 ); +module SLICE_30 ( input C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly; + + lut40034 LEDEN_6_i_m2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40035 LEDENe( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre LEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40034 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hB8B8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40035 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hE2E2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_31 ( input D0, B0, M1, M0, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; - lut40034 \RBAd[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40036 VCC( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); + lut40037 \RBAd[0] ( .A(GNDI), .B(B0), .C(GNDI), .D(D0), .Z(F0)); vmuxregsre PHI2r3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1554,8 +1645,8 @@ module SLICE_31 ( input B0, A0, M1, M0, CLK, output F0, Q0, Q1 ); .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify + (D0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); @@ -1566,17 +1657,22 @@ module SLICE_31 ( input B0, A0, M1, M0, CLK, output F0, Q0, Q1 ); endmodule -module lut40034 ( input A, B, C, D, output Z ); +module lut40036 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_32 ( input D1, C1, B1, C0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); +module lut40037 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCC00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_32 ( input C1, B1, A1, B0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; - lut40035 LED_pad_RNO( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40038 \un9_RA_i_m2_i_m2[6] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40036 RASr_RNO( .A(GNDI), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); + lut40014 RASr_RNO( .A(GNDI), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre RASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1584,10 +1680,10 @@ module SLICE_32 ( input D1, C1, B1, C0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); .LSR(GNDI), .Q(Q0)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); @@ -1598,31 +1694,26 @@ module SLICE_32 ( input D1, C1, B1, C0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); endmodule -module lut40035 ( input A, B, C, D, output Z ); +module lut40038 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFF3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hD8D8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40036 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0F0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_33 ( input D1, C1, B1, C0, A0, M0, CLK, output F0, Q0, F1 ); +module SLICE_33 ( input C1, B1, A1, C0, A0, M0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, M0_dly, CLK_dly; - lut40037 \un9_RA_i_m2_i_m2[3] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40039 \wb_adr_5_i_0_o2[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40038 CmdEnable_0_sqmuxa_0_a3_0_a3( .A(A0), .B(GNDI), .C(C0), .D(GNDI), + lut40040 CmdEnable_0_sqmuxa_0_a2_0_a2( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre RASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); @@ -1633,12 +1724,12 @@ module SLICE_33 ( input D1, C1, B1, C0, A0, M0, CLK, output F0, Q0, F1 ); endmodule -module lut40037 ( input A, B, C, D, output Z ); +module lut40039 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hCCF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hC5C5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40038 ( input A, B, C, D, output Z ); +module lut40040 ( input A, B, C, D, output Z ); ROM16X1A #(16'hA0A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule @@ -1647,8 +1738,8 @@ module SLICE_34 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire VCCI, GNDI, DI0_dly, CLK_dly; - lut40039 RCKEEN_8_u_0_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40040 RCKEEN_8_u_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40041 RCKEEN_8_u_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40042 RCKEEN_8_u( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre RCKEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1671,64 +1762,27 @@ module SLICE_34 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, endmodule -module lut40039 ( input A, B, C, D, output Z ); +module lut40041 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h444E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h5702) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40040 ( input A, B, C, D, output Z ); +module lut40042 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hF2F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hF4F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_35 ( input C1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); +module SLICE_35 ( input C1, B1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly; - lut40041 RASr2_RNI6PUF( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1)); + lut40021 RASr2_RNI6PUF( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40042 RCKE_2_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40043 RCKE_2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre RCKE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); specify - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40041 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h5050) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40042 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCCF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_36 ( input D1, C1, B1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, - F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly; - - lut40043 Ready_0_sqmuxa_0_a2_4_o2( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40044 Ready_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre Ready( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); @@ -1745,19 +1799,51 @@ endmodule module lut40043 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h3FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hF2E2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_36 ( input D1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly; + + lut40044 Ready_0_sqmuxa_0_o2( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40045 Ready_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre Ready( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + endmodule module lut40044 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hAEAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h77FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40045 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_37 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly; - lut40045 Ready_0_sqmuxa_0_a2_4_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40031 Ready_fast_RNO( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); + lut40046 Ready_0_sqmuxa_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40047 Ready_fast_RNO( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre Ready_fast( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); @@ -1778,17 +1864,22 @@ module SLICE_37 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 ); endmodule -module lut40045 ( input A, B, C, D, output Z ); +module lut40046 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_38 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); +module lut40047 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_38 ( input C1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly; - lut40034 \RowAd[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40048 \RowAd[1] ( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40034 \RowAd[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40017 \RowAd[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre \RowA[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1797,7 +1888,7 @@ module SLICE_38 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify - (B1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); @@ -1811,12 +1902,17 @@ module SLICE_38 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); endmodule -module SLICE_39 ( input B1, A1, C0, B0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); +module lut40048 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA0A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_39 ( input D1, C1, C0, B0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly; - lut40034 \RowAd[3] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40049 \RowAd[3] ( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40046 \RowAd[2] ( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40050 \RowAd[2] ( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RowA[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1825,8 +1921,8 @@ module SLICE_39 ( input B1, A1, C0, B0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); @@ -1839,7 +1935,12 @@ module SLICE_39 ( input B1, A1, C0, B0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); endmodule -module lut40046 ( input A, B, C, D, output Z ); +module lut40049 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40050 ( input A, B, C, D, output Z ); ROM16X1A #(16'hC0C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule @@ -1847,9 +1948,9 @@ endmodule module SLICE_40 ( input C1, B1, C0, B0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly; - lut40047 \RowAd[5] ( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40051 \RowAd[5] ( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40048 \RowAd[4] ( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40050 \RowAd[4] ( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RowA[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1872,22 +1973,17 @@ module SLICE_40 ( input C1, B1, C0, B0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); endmodule -module lut40047 ( input A, B, C, D, output Z ); +module lut40051 ( input A, B, C, D, output Z ); ROM16X1A #(16'hCFCF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40048 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hC0C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_41 ( input C1, B1, C0, B0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); +module SLICE_41 ( input D1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly; - lut40048 \RowAd[7] ( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40052 \RowAd[7] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40048 \RowAd[6] ( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40017 \RowAd[6] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre \RowA[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1896,8 +1992,41 @@ module SLICE_41 ( input C1, B1, C0, B0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify - (C1 => F1) = (0:0:0,0:0:0); + (D1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + endspecify + +endmodule + +module lut40052 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAA00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_42 ( input B1, A1, C0, B0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly; + + lut40053 \RowAd[9] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40054 \RowAd[8] ( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \RowA[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre \RowA[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); @@ -1910,50 +2039,22 @@ module SLICE_41 ( input C1, B1, C0, B0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); endmodule -module SLICE_42 ( input D1, A1, D0, C0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly; - - lut40049 \RowAd[9] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40050 \RowAd[8] ( .A(GNDI), .B(GNDI), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \RowA[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - vmuxregsre \RowA[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - endspecify +module lut40053 ( input A, B, C, D, output Z ); + ROM16X1A #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40049 ( input A, B, C, D, output Z ); +module lut40054 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hAAFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hC0C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40050 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_43 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, +module SLICE_43 ( input D1, C1, B1, A1, C0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; - lut40051 Ready_0_sqmuxa_0_a2_4_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40052 \S_0_i_o2_i_o2[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40055 nRCS_9_u_i_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40047 \S_0_i_o3[1] ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre0009 \S[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); @@ -1965,7 +2066,7 @@ module SLICE_43 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); @@ -1978,22 +2079,17 @@ module SLICE_43 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, endmodule -module lut40051 ( input A, B, C, D, output Z ); +module lut40055 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40052 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h5040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_44 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly; - lut40053 XOR8MEG_3_u_0_0_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40054 XOR8MEG_3_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40056 XOR8MEG_3_u_0_0_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40057 XOR8MEG_3_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre XOR8MEG( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -2018,22 +2114,22 @@ module SLICE_44 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output endmodule -module lut40053 ( input A, B, C, D, output Z ); +module lut40056 ( input A, B, C, D, output Z ); ROM16X1A #(16'hAAA8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40054 ( input A, B, C, D, output Z ); +module lut40057 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hCEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hF7F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_45 ( input D1, C1, B1, A1, D0, C0, A0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly; - lut40055 CmdValid_RNIOOBE2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40056 n8MEGEN_RNO( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + lut40058 CmdValid_RNIOOBE2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40059 n8MEGEN_RNO( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre n8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); @@ -2055,30 +2151,30 @@ module SLICE_45 ( input D1, C1, B1, A1, D0, C0, A0, DI0, CLK, output F0, Q0, endmodule -module lut40055 ( input A, B, C, D, output Z ); +module lut40058 ( input A, B, C, D, output Z ); ROM16X1A #(16'hF8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40056 ( input A, B, C, D, output Z ); +module lut40059 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0AFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_46 ( input C1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, +module SLICE_46 ( input C1, B1, D0, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; - lut40057 nRowColSel_0_0_0_a2( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1)); + lut40060 nRowColSel_0_0_a2_1( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40058 nRowColSel_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40061 nRowColSel_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0009 nRowColSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); specify (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); @@ -2094,22 +2190,22 @@ module SLICE_46 ( input C1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, endmodule -module lut40057 ( input A, B, C, D, output Z ); +module lut40060 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0A0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0C0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40058 ( input A, B, C, D, output Z ); +module lut40061 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h88A8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hF040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_47 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40059 \wb_adr_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40060 \wb_adr_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40062 \wb_adr_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40063 \wb_adr_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \wb_adr[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -2137,23 +2233,23 @@ module SLICE_47 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, endmodule -module lut40059 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40060 ( input A, B, C, D, output Z ); +module lut40062 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_48 ( input D1, A1, C0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, +module lut40063 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_48 ( input B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40015 \wb_adr_5[3] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1)); + lut40017 \wb_adr_5[3] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40038 \wb_adr_5[2] ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); + lut40017 \wb_adr_5[2] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre \wb_adr[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -2161,41 +2257,8 @@ module SLICE_48 ( input D1, A1, C0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify - (D1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_49 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40061 \wb_adr_5_i_m2_i_m2[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40061 \wb_adr_5_i_m2_i_m2[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \wb_adr[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \wb_adr[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); @@ -2209,18 +2272,49 @@ module SLICE_49 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, endmodule -module lut40061 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF022) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_50 ( input B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, +module SLICE_49 ( input D1, C1, A1, D0, C0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40034 \wb_adr_5[7] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40064 \wb_adr_5_i_m2[5] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40062 \wb_adr_5_i_m2_i_m2[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40064 \wb_adr_5_i_m2[4] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \wb_adr[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \wb_adr[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40064 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAF05) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_50 ( input C1, B1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40054 \wb_adr_5[7] ( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40039 \wb_adr_5_i_m2[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \wb_adr[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -2228,9 +2322,8 @@ module SLICE_50 ( input B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); @@ -2245,17 +2338,12 @@ module SLICE_50 ( input B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, endmodule -module lut40062 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hB1A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); wire VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; - lut40063 wb_cyc_stb_4_iv_0_a3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40064 wb_cyc_stb_4_iv_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40065 wb_cyc_stb_4_iv_0_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40066 wb_cyc_stb_4_iv_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0009 wb_cyc_stb( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -2281,22 +2369,22 @@ module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, endmodule -module lut40063 ( input A, B, C, D, output Z ); +module lut40065 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40064 ( input A, B, C, D, output Z ); +module lut40066 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hF8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hECCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40065 \wb_dati_5_1_iv_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40066 \wb_dati_5_0_iv_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40067 \wb_dati_5_1_iv_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40068 \wb_dati_5_0_iv_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \wb_dati[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -2324,22 +2412,22 @@ module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, endmodule -module lut40065 ( input A, B, C, D, output Z ); +module lut40067 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hF0F2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hF1F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40066 ( input A, B, C, D, output Z ); +module lut40068 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_53 ( input D1, C1, B1, A1, D0, C0, A0, DI1, DI0, CE, CLK, output +module SLICE_53 ( input D1, C1, B1, A1, D0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40067 \wb_dati_5_1_iv_i_i[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40068 \wb_dati_5_1_iv_0[2] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + lut40069 \wb_dati_5_1_iv_0_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40070 \wb_dati_5_1_iv_0_0[2] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \wb_dati[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); @@ -2353,48 +2441,6 @@ module SLICE_53 ( input D1, C1, B1, A1, D0, C0, A0, DI1, DI0, CE, CLK, output (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40067 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40068 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_54 ( input D1, C1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40069 \wb_dati_5_1_iv_0[5] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40070 \wb_dati_5_1_iv_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \wb_dati[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \wb_dati[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); @@ -2410,20 +2456,62 @@ endmodule module lut40069 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFAF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFEFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40070 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hCEFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFF88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_54 ( input D1, C1, B1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40071 \wb_dati_5_1_iv_0_0[5] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40072 \wb_dati_5_1_iv_0_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \wb_dati[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \wb_dati[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40071 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFCF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40072 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_55 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 \wb_dati_5_1_iv_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40072 \wb_dati_5_1_iv_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40073 \wb_dati_5_1_iv_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40074 \wb_dati_5_1_iv_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \wb_dati[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -2451,22 +2539,22 @@ module SLICE_55 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, endmodule -module lut40071 ( input A, B, C, D, output Z ); +module lut40073 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40072 ( input A, B, C, D, output Z ); +module lut40074 ( input A, B, C, D, output Z ); ROM16X1A #(16'hAABA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_56 ( input D1, C1, B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, +module SLICE_56 ( input D1, C1, B1, A1, D0, C0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; - lut40073 wb_reqe_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40074 wb_reqe( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40075 wb_reqe_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40076 wb_reqe( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre0009 wb_req( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); @@ -2477,8 +2565,8 @@ module SLICE_56 ( input D1, C1, B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); @@ -2491,26 +2579,26 @@ module SLICE_56 ( input D1, C1, B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, endmodule -module lut40073 ( input A, B, C, D, output Z ); +module lut40075 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h1555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40074 ( input A, B, C, D, output Z ); +module lut40076 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hCACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hF0AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, - Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly; +module SLICE_57 ( input D1, C1, B1, A1, D0, C0, A0, DI0, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly; - lut40075 \FS_RNIHVJI_0[16] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40076 wb_rste( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40077 un1_InitReady_4_i_0_a2_i( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40078 wb_rste( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre wb_rst( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -2519,7 +2607,6 @@ module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); @@ -2529,28 +2616,28 @@ module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, endmodule -module lut40075 ( input A, B, C, D, output Z ); +module lut40077 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h33B3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40076 ( input A, B, C, D, output Z ); +module lut40078 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hE222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hAFA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_58 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, - output F0, Q0, F1 ); - wire VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; +module SLICE_58 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output + F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; - lut40061 \wb_adr_5_i_0_m2[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40077 wb_we_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40079 un1_wb_rst14_2_0_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40080 wb_we_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0009 wb_we( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -2570,26 +2657,33 @@ module SLICE_58 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, endmodule -module lut40077 ( input A, B, C, D, output Z ); +module lut40079 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h5011) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module wb_dati_5_1_iv_0_o3_5__SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, - M0, output OFX0 ); - wire - \wb_dati_5_1_iv_0_o3[5]/SLICE_59/wb_dati_5_1_iv_0_o3[5]/SLICE_59_K1_H1 , - \wb_dati_5_1_iv_0_o3[5]/SLICE_59/wb_dati_5_1_iv_0_o3[5]/GATE_H0 ; +module lut40080 ( input A, B, C, D, output Z ); - lut40078 \wb_dati_5_1_iv_0_o3[5]/SLICE_59_K1 ( .A(A1), .B(B1), .C(C1), + ROM16X1A #(16'h00B3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module wb_dati_5_1_iv_0_0_o2_5__SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, + A0, M0, output OFX0 ); + wire + \wb_dati_5_1_iv_0_0_o2[5]/SLICE_59/wb_dati_5_1_iv_0_0_o2[5]/SLICE_59_K1_H1 + , + \wb_dati_5_1_iv_0_0_o2[5]/SLICE_59/wb_dati_5_1_iv_0_0_o2[5]/GATE_H0 ; + + lut40081 \wb_dati_5_1_iv_0_0_o2[5]/SLICE_59_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(\wb_dati_5_1_iv_0_o3[5]/SLICE_59/wb_dati_5_1_iv_0_o3[5]/SLICE_59_K1_H1 )); - lut40079 \wb_dati_5_1_iv_0_o3[5]/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(\wb_dati_5_1_iv_0_o3[5]/SLICE_59/wb_dati_5_1_iv_0_o3[5]/GATE_H0 )); - selmux2 \wb_dati_5_1_iv_0_o3[5]/SLICE_59_K0K1MUX ( - .D0(\wb_dati_5_1_iv_0_o3[5]/SLICE_59/wb_dati_5_1_iv_0_o3[5]/GATE_H0 ), - .D1(\wb_dati_5_1_iv_0_o3[5]/SLICE_59/wb_dati_5_1_iv_0_o3[5]/SLICE_59_K1_H1 ), - .SD(M0), .Z(OFX0)); + .Z(\wb_dati_5_1_iv_0_0_o2[5]/SLICE_59/wb_dati_5_1_iv_0_0_o2[5]/SLICE_59_K1_H1 ) + ); + lut40082 \wb_dati_5_1_iv_0_0_o2[5]/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\wb_dati_5_1_iv_0_0_o2[5]/SLICE_59/wb_dati_5_1_iv_0_0_o2[5]/GATE_H0 )); + selmux2 \wb_dati_5_1_iv_0_0_o2[5]/SLICE_59_K0K1MUX ( + .D0(\wb_dati_5_1_iv_0_0_o2[5]/SLICE_59/wb_dati_5_1_iv_0_0_o2[5]/GATE_H0 ), + .D1(\wb_dati_5_1_iv_0_0_o2[5]/SLICE_59/wb_dati_5_1_iv_0_0_o2[5]/SLICE_59_K1_H1 ) + , .SD(M0), .Z(OFX0)); specify (D1 => OFX0) = (0:0:0,0:0:0); @@ -2605,14 +2699,14 @@ module wb_dati_5_1_iv_0_o3_5__SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, endmodule -module lut40078 ( input A, B, C, D, output Z ); +module lut40081 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hCCCE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hAABA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40079 ( input A, B, C, D, output Z ); +module lut40082 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hCCEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hBAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module selmux2 ( input D0, D1, SD, output Z ); @@ -2620,68 +2714,162 @@ module selmux2 ( input D0, D1, SD, output Z ); MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z)); endmodule -module SLICE_60 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module wb_adr_5_i_0_1_0__SLICE_60 ( input D1, C1, A1, D0, C0, B0, A0, M0, + output OFX0 ); + wire GNDI, \wb_adr_5_i_0_1[0]/SLICE_60/wb_adr_5_i_0_1[0]/SLICE_60_K1_H1 , + \wb_adr_5_i_0_1[0]/SLICE_60/wb_adr_5_i_0_1[0]/GATE_H0 ; - lut40080 CBR_fast_RNIQ31K1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40081 nRCAS_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40080 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40081 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCCCD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_61 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 ); - wire GNDI; - - lut40082 un1_nRCAS_6_sqmuxa_i_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40083 nRCAS_r_i_0_o2_0_2_RNO( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40083 \wb_adr_5_i_0_1[0]/SLICE_60_K1 ( .A(A1), .B(GNDI), .C(C1), .D(D1), + .Z(\wb_adr_5_i_0_1[0]/SLICE_60/wb_adr_5_i_0_1[0]/SLICE_60_K1_H1 )); gnd DRIVEGND( .PWR0(GNDI)); + lut40084 \wb_adr_5_i_0_1[0]/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\wb_adr_5_i_0_1[0]/SLICE_60/wb_adr_5_i_0_1[0]/GATE_H0 )); + selmux2 \wb_adr_5_i_0_1[0]/SLICE_60_K0K1MUX ( + .D0(\wb_adr_5_i_0_1[0]/SLICE_60/wb_adr_5_i_0_1[0]/GATE_H0 ), + .D1(\wb_adr_5_i_0_1[0]/SLICE_60/wb_adr_5_i_0_1[0]/SLICE_60_K1_H1 ), + .SD(M0), .Z(OFX0)); specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule -module lut40082 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h33FA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40083 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h00CF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0050) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 ); +module lut40084 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0048) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_61 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40085 \wb_adr_5_i_0_2_RNO[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40086 \wb_adr_5_i_0_2_RNO_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40085 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40086 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40087 IS_0_sqmuxa_0_o2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40088 un1_nRCAS_6_sqmuxa_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40087 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFDFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40088 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h31FD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40089 un1_CmdEnable20_0_0_a2_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40090 un1_CmdEnable20_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40089 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40090 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCD05) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_64 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40091 \FS_RNIHVJI[15] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40092 \wb_dati_5_1_iv_0_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40091 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40092 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 ); wire GNDI; - lut40084 \wb_adr_5_i_0_a2_1[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40085 wb_we_0_i_0_1_RNO( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40093 \wb_dati_5_1_iv_0_1_0[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40094 \wb_dati_5_1_iv_0_0_o2[4] ( .A(GNDI), .B(B0), .C(C0), .D(D0), + .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -2696,133 +2884,50 @@ module SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 ); endmodule -module lut40084 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40085 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCFCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40086 wb_we_0_i_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40087 wb_we_0_i_0_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40086 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFA2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40087 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_64 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40088 un1_CmdEnable20_0_0_a2_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40089 un1_CmdEnable20_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40088 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40089 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40090 \wb_adr_5_i_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40091 \wb_adr_5_i_0_3[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40090 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hAEEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40091 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCECC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_66 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40092 \FS_RNIHVJI[16] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40093 \wb_dati_5_1_iv_0_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40092 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40093 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hCE0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h5F33) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40094 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0C33) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_66 ( input D1, C1, B1, D0, C0, A0, output F0, F1 ); + wire GNDI; + + lut40095 \FS_RNIF2MA[9] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40096 \ufmefb/EFBInst_0_RNISI191 ( .A(A0), .B(GNDI), .C(C0), .D(D0), + .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40095 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40096 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0500) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_67 ( input D1, C1, B1, A1, D0, B0, A0, output F0, F1 ); wire GNDI; - lut40094 \wb_dati_5_1_iv_0_0[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40095 \wb_adr_5_i_0_o2[0] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); + lut40097 \wb_adr_5_i_0_3[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40098 \FS_RNIJO0F[12] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -2837,79 +2942,21 @@ module SLICE_67 ( input D1, C1, B1, A1, D0, B0, A0, output F0, F1 ); endmodule -module lut40094 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h35F5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40095 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2255) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_68 ( input D1, C1, A1, D0, C0, A0, output F0, F1 ); - wire GNDI; - - lut40096 \FS_RNIF2MA[9] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40097 \ufmefb/EFBInst_0_RNISI191 ( .A(A0), .B(GNDI), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40096 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h5FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40097 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0500) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40098 \wb_dati_5_1_iv_0_a3_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40099 \wb_dati_5_1_iv_0_a3_0_RNO[1] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - + ROM16X1A #(16'hCECC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40098 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0011) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40099 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_70 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 ); +module SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 ); wire GNDI; - lut40099 \wb_adr_5_i_0_a3_4[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40100 \FS_RNIJO0F[14] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40099 nRWE_s_i_tz_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40100 \S_RNICVV51[1] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -2924,17 +2971,21 @@ module SLICE_70 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 ); endmodule -module lut40100 ( input A, B, C, D, output Z ); +module lut40099 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0003) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hF0F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_71 ( input D1, C1, B1, A1, D0, C0, A0, output F0, F1 ); +module lut40100 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_69 ( input D1, C1, B1, A1, D0, C0, A0, output F0, F1 ); wire GNDI; - lut40101 \wb_dati_5_1_iv_i_i_1[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40102 \wb_dati_5_1_iv_i_i_1_RNO[3] ( .A(A0), .B(GNDI), .C(C0), .D(D0), - .Z(F0)); + lut40101 nRCAS_0io_RNO_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40102 nRCAS_0io_RNO_2( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -2951,26 +3002,25 @@ endmodule module lut40101 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hF8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0070) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40102 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0AAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h00F5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_72 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; +module SLICE_70 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40103 nRCS_9_u_i_0_o3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40104 Ready_RNICVV51( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); + lut40103 wb_we_0_0_i_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40104 \FS_RNIOVGI[9] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); @@ -2980,24 +3030,23 @@ endmodule module lut40103 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hEEEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hF5D5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40104 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_71 ( input C1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; - lut40105 \wb_dati_5_1_iv_i_i_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40106 \wb_dati_5_1_iv_i_i_0_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); + lut40105 \FS_RNIS637[9] ( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40106 \wb_adr_RNO_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); @@ -3009,27 +3058,27 @@ endmodule module lut40105 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h5F5F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40106 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h7300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_74 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_72 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40107 un1_nRCAS_6_sqmuxa_i_0_0_o2_0( .A(A1), .B(GNDI), .C(C1), .D(D1), + lut40107 \wb_dati_5_1_iv_0_o2_0[4] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40108 un1_nRCAS_6_sqmuxa_i_0_0_o2_0_RNIQVER( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); + lut40108 \wb_dati_5_1_iv_0_o2_0_RNIMDJC1[4] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); @@ -3040,24 +3089,25 @@ endmodule module lut40107 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h3CCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40108 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hBFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_75 ( input D1, B1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_73 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40109 \wb_adr_5_i_0_a2_0[1] ( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + lut40109 \wb_dati_5_1_iv_0_o2[7] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40110 \wb_adr_RNO_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40030 \wb_dati_5_1_iv_0_1_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); @@ -3068,135 +3118,73 @@ endmodule module lut40109 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0033) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hF0FA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_74 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40110 \FS_RNIGOCT[12] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40111 \wb_dati_5_1_iv_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + endmodule module lut40110 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h40CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_76 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40111 \wb_dati_5_1_iv_0_o2[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40112 \wb_dati_5_1_iv_0_RNO_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - + ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40111 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h100B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h2300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_75 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40112 CBR_fast_RNIQ31K1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40113 nRWE_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + endmodule module lut40112 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_77 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40113 \FS_RNIGOCT[14] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40114 \wb_dati_5_1_iv_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - + ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40113 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hCCDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40114 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4050) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_78 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40115 nRCS_9_u_i_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40116 nRRAS_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40115 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0032) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40116 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h010F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_79 ( input D1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40117 nRCS_9_u_i_0_o2_1( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40118 nRCS_9_u_i_0_o2_1_RNIL2K71_0( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40117 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h55FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40118 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_80 ( input D1, C1, B1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, +module SLICE_76 ( input D1, C1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; - lut40119 un1_CmdEnable20_0_0_a3_1_1( .A(GNDI), .B(B1), .C(C1), .D(D1), + lut40114 un1_CmdEnable20_0_0_a2_1_1( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40120 CmdEnable_s_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40115 CmdEnable_s_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre CBR_fast( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -3207,7 +3195,7 @@ module SLICE_80 ( input D1, C1, B1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); @@ -3222,26 +3210,112 @@ module SLICE_80 ( input D1, C1, B1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, endmodule -module lut40119 ( input A, B, C, D, output Z ); +module lut40114 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hC000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hA000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40120 ( input A, B, C, D, output Z ); +module lut40115 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0023) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_81 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; +module SLICE_77 ( input D1, C1, B1, A1, C0, B0, M0, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, M0_dly, CLK_dly; - lut40121 RCKEEN_8_u_0_0_a2_2( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + lut40116 Cmdn8MEGEN_4_u_i_m2_i_a2_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40050 CmdUFMData_1_sqmuxa_0_a2( .A(GNDI), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40122 nRWE_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40116 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_78 ( input D1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40117 nRCS_9_u_i_a2_0( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40118 nRCS_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40117 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0055) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40118 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1113) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_79 ( input C1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40119 IS_0_sqmuxa_0_o3( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40120 RA10_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40119 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40120 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_80 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40121 un1_CmdEnable20_0_0_o2_11( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40122 un1_CmdEnable20_0_0_o2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); @@ -3253,57 +3327,24 @@ endmodule module lut40121 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h5000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hDFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40122 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hAABF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFBFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_82 ( input D1, C1, B1, A1, C0, B0, M0, CE, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; +module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40123 CmdLEDEN_4_u_i_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40046 CmdUFMData_1_sqmuxa_0_a3( .A(GNDI), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre CmdUFMData( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + lut40123 \wb_dati_5_1_iv_0_a2_2[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40124 \wb_dati_5_1_iv_0_0_1[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - endspecify - -endmodule - -module lut40123 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_83 ( input D1, B1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40109 nRCAS_r_i_0_a2( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40124 nRCS_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); @@ -3312,15 +3353,20 @@ module SLICE_83 ( input D1, B1, D0, C0, B0, A0, output F0, F1 ); endmodule -module lut40124 ( input A, B, C, D, output Z ); +module lut40123 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0307) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module lut40124 ( input A, B, C, D, output Z ); - lut40125 un1_CmdEnable20_0_0_o3_11( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40126 un1_CmdEnable20_0_0_o3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_82 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40125 \wb_dati_5_1_iv_0_a2_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40126 \wb_dati_5_1_iv_0_1[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -3337,22 +3383,23 @@ endmodule module lut40125 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h7FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0440) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40126 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFEFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_83 ( input D1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; - lut40127 \wb_dati_5_1_iv_0_a3_0[6] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40128 \wb_dati_5_1_iv_0_1[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40127 un1_nRCAS_6_sqmuxa_i_o2( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40128 nRCS_9_u_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); @@ -3365,23 +3412,25 @@ endmodule module lut40127 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFFEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40128 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFF32) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_86 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_84 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; - lut40129 \wb_dati_5_1_iv_0_a3[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40130 \wb_dati_5_1_iv_0_1[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40129 \wb_dati_5_1_iv_0_a2_13[3] ( .A(A1), .B(GNDI), .C(C1), .D(D1), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40130 \wb_dati_5_1_iv_0_0_a2[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); @@ -3393,25 +3442,23 @@ endmodule module lut40129 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h8020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0005) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40130 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0900) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_87 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; +module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40131 \wb_dati_5_1_iv_i_i_a2_4[3] ( .A(A1), .B(GNDI), .C(C1), .D(D1), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40132 \wb_dati_5_1_iv_0_a3_3[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40131 \wb_dati_5_1_iv_0_0_o2[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40132 \wb_dati_5_1_iv_0_1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); @@ -3423,18 +3470,20 @@ endmodule module lut40131 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0005) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0810) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40132 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hECCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_88 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_86 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 ); + wire GNDI; - lut40133 nRCS_9_u_i_0_o2_1_RNIL2K71( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40134 RA10_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40133 \wb_dati_5_1_iv_0_a2_7[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40134 \wb_dati_5_1_iv_0_0_0[3] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -3444,31 +3493,30 @@ module SLICE_88 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule module lut40133 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40134 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFEFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFCCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_89 ( input C1, B1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_87 ( input D1, B1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40047 \wb_dati_5_1_iv_0_o2_0[7] ( .A(GNDI), .B(B1), .C(C1), .D(GNDI), + lut40135 \wb_dati_5_1_iv_0_a2_12[3] ( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40135 \wb_dati_5_1_iv_0_a3[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40136 \wb_dati_5_1_iv_0_0_1[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify - (C1 => F1) = (0:0:0,0:0:0); + (D1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); @@ -3480,133 +3528,110 @@ endmodule module lut40135 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0804) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_90 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40136 nRWE_s_i_0_a3_1_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40137 nRWE_s_i_0_tz_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - + ROM16X1A #(16'h0033) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40136 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFF80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_88 ( input D1, C1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40137 \FS_RNI7U6M[14] ( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40138 \wb_dati_5_1_iv_0_a2_5[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + endmodule module lut40137 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hF4F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_91 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40138 \wb_dati_5_1_iv_i_i_a3_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40139 \wb_dati_5_1_iv_0_1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - + ROM16X1A #(16'h000F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40138 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_89 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40139 wb_cyc_stb_2_sqmuxa_i_0_0_a2_0( .A(GNDI), .B(B1), .C(C1), .D(D1), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40140 wb_cyc_stb_2_sqmuxa_i_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + endmodule module lut40139 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_92 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40140 wb_cyc_stb_2_sqmuxa_i_a3_0( .A(GNDI), .B(B1), .C(C1), .D(D1), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40141 wb_cyc_stb_2_sqmuxa_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - + ROM16X1A #(16'hCC0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40140 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hCC0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_90 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40141 un1_CmdEnable20_0_0_o2_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40142 un1_CmdEnable20_0_0_o2_10( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + endmodule module lut40141 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFEFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_93 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40142 un1_CmdEnable20_0_0_o3_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40143 un1_CmdEnable20_0_0_o3_10( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - + ROM16X1A #(16'hBFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40142 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h7FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hEFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40143 ( input A, B, C, D, output Z ); +module SLICE_91 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; - ROM16X1A #(16'hFEFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_94 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40144 nRCAS_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40145 nRCAS_r_i_0_o2_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40143 \FS_RNI82PA[15] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40144 \wb_adr_5_i_0_2[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); @@ -3616,26 +3641,49 @@ module SLICE_94 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); endmodule +module lut40143 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFF5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + module lut40144 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0133) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFF3A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_92 ( input C1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40048 Cmdn8MEGEN_4_u_i_m2_i_a2_3( .A(A1), .B(GNDI), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40145 un1_CmdEnable20_0_0_a2_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + endmodule module lut40145 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h1500) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_95 ( input D1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; +module SLICE_93 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40146 \wb_dati_5_1_iv_i_i_a2_2[3] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40147 wb_we_0_i_0_a3_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40146 wb_we_0_0_i_1_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40147 wb_we_0_0_i_a2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); @@ -3647,24 +3695,25 @@ endmodule module lut40146 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h5500) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h4555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40147 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0900) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h4500) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_96 ( input D1, C1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_94 ( input D1, A1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; - lut4 \wb_adr_5_i_0_a2_1[0] ( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + lut40117 \wb_adr_5_i_3_0_a2_3[1] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), + .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40148 \wb_adr_5_i_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40148 wb_rst_3_0_a2_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); @@ -3675,18 +3724,19 @@ endmodule module lut40148 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hA800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_97 ( input C1, B1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_95 ( input D1, B1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40149 \FS_RNIH267[16] ( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40135 wb_cyc_stb_2_sqmuxa_i_a2_2_0( .A(GNDI), .B(B1), .C(GNDI), .D(D1), + .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40150 \wb_adr_5_i_0_m2[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40149 wb_cyc_stb_2_sqmuxa_i_a2_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify - (C1 => F1) = (0:0:0,0:0:0); + (D1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); @@ -3698,25 +3748,44 @@ endmodule module lut40149 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFCFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_96 ( input C1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40119 XOR8MEG_3_u_0_0_o2_1( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40150 XOR8MEG_3_u_0_0_a2_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + endmodule module lut40150 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hC0E2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_98 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_97 ( input C1, B1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40151 wb_cyc_stb_4_iv_0_a3_0_2_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + lut40151 \wb_dati_5_1_iv_0_o2_0[7] ( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40152 wb_cyc_stb_4_iv_0_a3_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40152 \wb_dati_5_1_iv_0_a2_0_2[1] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); specify + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); @@ -3727,23 +3796,24 @@ endmodule module lut40151 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hF3F3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40152 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_99 ( input C1, B1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_98 ( input D1, B1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40046 CmdLEDEN_4_u_i_0_a2_0( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40037 \wb_dati_5_1_iv_0_a2_6[4] ( .A(GNDI), .B(B1), .C(GNDI), .D(D1), + .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40080 un1_CmdEnable20_0_0_a2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40153 \wb_dati_5_0_iv_0_a2_1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify - (C1 => F1) = (0:0:0,0:0:0); + (D1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); @@ -3753,41 +3823,21 @@ module SLICE_99 ( input C1, B1, D0, C0, B0, A0, output F0, F1 ); endmodule -module SLICE_100 ( input C1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40153 XOR8MEG_3_u_0_0_o2_1( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40080 XOR8MEG_3_u_0_0_a3_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - module lut40153 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0880) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_101 ( input D1, C1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; +module SLICE_99 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40154 \wb_dati_5_1_iv_0_a2[6] ( .A(GNDI), .B(GNDI), .C(C1), .D(D1), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40155 \wb_dati_5_1_iv_0_a3_0_1[7] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); + lut40108 InitReady3_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40154 InitReady3_0_a2_1_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); @@ -3798,21 +3848,15 @@ endmodule module lut40154 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0F00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h7FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40155 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_102 ( input D1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_100 ( input D1, A1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40156 \wb_dati_5_0_iv_0_a2[0] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), - .Z(F1)); + lut40155 PHI2r3_RNIFT0I_0( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40157 \wb_dati_5_0_iv_0_a3_1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40156 CmdValid_fast_RNI3K0H1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -3825,26 +3869,56 @@ module SLICE_102 ( input D1, A1, D0, C0, B0, A0, output F0, F1 ); endmodule +module lut40155 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h00AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + module lut40156 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hAA00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h8F0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_101 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 ); + wire GNDI; + + lut40157 nRCAS_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40158 nRCAS_0io_RNO_0( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + endspecify + endmodule module lut40157 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h2800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0515) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_103 ( input C1, B1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; +module lut40158 ( input A, B, C, D, output Z ); - lut40158 PHI2r3_RNIFT0I_0( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40159 CmdValid_fast_RNI3K0H1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + ROM16X1A #(16'hF0F3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_102 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40159 \wb_dati_5_1_iv_0_a2_0_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40010 \ufmefb/EFBInst_0_RNISGNB ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); @@ -3853,24 +3927,18 @@ module SLICE_103 ( input C1, B1, D0, C0, B0, A0, output F0, F1 ); endmodule -module lut40158 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h3030) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40159 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hD555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_104 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; +module SLICE_103 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40160 \FS_RNIVOOA[14] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40161 \ufmefb/EFBInst_0_RNISGNB ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40160 RCKEEN_8_u_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40161 nRWE_s_i_a2_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -3884,19 +3952,21 @@ endmodule module lut40160 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h2DAD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40161 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_105 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 ); +module SLICE_104 ( input D1, C1, B1, A1, D0, B0, A0, output F0, F1 ); wire GNDI; - lut40162 \wb_adr_5_i_0_a3_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40163 wb_we_0_i_0_0_RNO( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40162 \wb_dati_5_1_iv_0_0_a2_1[3] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40163 \wb_dati_5_1_iv_0_a2_5[7] ( .A(A0), .B(B0), .C(GNDI), .D(D0), + .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -3905,97 +3975,88 @@ module SLICE_105 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 ); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule module lut40162 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0A08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0082) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40163 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h1100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_106 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 ); +module SLICE_105 ( input D1, A1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40164 \wb_adr_5_i_0_a3[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40165 \wb_adr_RNO_0[0] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40164 \FS_RNI9Q57[12] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); + lut40165 \wb_adr_5_i_3_0_a2[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule module lut40164 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h8C04) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hAA00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40165 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0C00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hA300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_107 ( input C1, B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0, - F1 ); - wire GNDI, VCCI, M0_dly, CLK_dly; +module SLICE_106 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; - lut40166 wb_cyc_stb_4_iv_0_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40166 RCKEEN_8_u_0_a2_2( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40167 CmdValid_RNIS5A51( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre CASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); + lut40167 LED_pad_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); endspecify endmodule module lut40166 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h00C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40167 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h40FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_108 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_107 ( input C1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; - lut40168 RCKEEN_8_u_0_1_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40169 nRWE_s_i_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40168 \wb_adr_5_i_0_a2_6[0] ( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40169 \wb_adr_5_i_3_0_a2_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); @@ -4007,20 +4068,40 @@ endmodule module lut40168 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h7A0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h5050) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40169 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0E00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_109 ( input D1, C1, B1, A1, D0, C0, A0, output F0, F1 ); +module SLICE_108 ( input C1, B1, C0, B0, output F0, F1 ); wire GNDI; - lut40170 \wb_dati_5_1_iv_i_i_a3_1_1[3] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40171 \wb_adr_5_i_0_o2_0[0] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + lut40170 RDQML_0_0( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40051 RDQMH_pad_RNO( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40170 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3F3F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_109 ( input D1, C1, B1, A1, C0, B0, output F0, F1 ); + wire GNDI; + + lut40171 un1_CmdEnable20_0_0_a2_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40172 XOR8MEG_3_u_0_0_a2_1( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -4028,6 +4109,32 @@ module SLICE_109 ( input D1, C1, B1, A1, D0, C0, A0, output F0, F1 ); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40171 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40172 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3030) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_110 ( input D1, C1, D0, C0, A0, output F0, F1 ); + wire GNDI; + + lut40173 PHI2r3_RNIFT0I( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40174 wb_cyc_stb_4_iv_0_0_RNO( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); @@ -4035,25 +4142,26 @@ module SLICE_109 ( input D1, C1, B1, A1, D0, C0, A0, output F0, F1 ); endmodule -module lut40170 ( input A, B, C, D, output Z ); +module lut40173 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h2100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h00F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40171 ( input A, B, C, D, output Z ); +module lut40174 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hA0AF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h00A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_110 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_111 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; - lut40172 \wb_adr_5_i_0_a3_0_2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40173 \wb_dati_5_1_iv_i_i_o2[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40175 n8MEGEN_RNO_0( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40176 \wb_dati_5_1_iv_0_0_1[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); @@ -4063,66 +4171,179 @@ module SLICE_110 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); endmodule -module lut40172 ( input A, B, C, D, output Z ); +module lut40175 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h550F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40173 ( input A, B, C, D, output Z ); +module lut40176 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h4002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFEFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_111 ( input D1, A1, D0, A0, output F0, F1 ); +module SLICE_112 ( input D1, B1, A1, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40174 RDQML_0_0( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1)); + lut40177 \un9_RA_i_m2_i_m2[2] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40049 RDQMH_pad_RNO( .A(A0), .B(GNDI), .C(GNDI), .D(D0), .Z(F0)); + lut40178 un1_CmdEnable20_0_0_o2_3( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule -module lut40174 ( input A, B, C, D, output Z ); +module lut40177 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h55FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hDD88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_112 ( input D1, C1, B1, A1, C0, A0, output F0, F1 ); +module lut40178 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_113 ( input D1, C1, A1, D0, B0, A0, output F0, F1 ); wire GNDI; - lut40175 un1_CmdEnable20_0_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40018 XOR8MEG_3_u_0_0_0_a2( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); + lut40179 \un9_RA[8] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); + lut40180 \un9_RA_i_m2_i_m2[0] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40179 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF0AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40180 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAACC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_114 ( input D1, C1, B1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40181 \un9_RA_i_m2_i_m2[3] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40035 \un9_RA_i_m2_i_m2[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40181 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCCF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_115 ( input D1, C1, B1, D0, C0, A0, output F0, F1 ); + wire GNDI; + + lut40182 \un9_RA_i_m2_i_m2[9] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40179 \un9_RA_i_m2_i_m2[4] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule -module lut40175 ( input A, B, C, D, output Z ); +module lut40182 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hCFC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_113 ( input D1, C1, C0, B0, output F0, F1 ); +module SLICE_116 ( input C1, B1, A1, D0, C0, A0, output F0, F1 ); wire GNDI; - lut40176 \FS_RNI7U6M[14] ( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + lut40183 \un9_RA_i_m2_i_m2[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40177 \wb_dati_5_1_iv_i_i_a2_3[3] ( .A(GNDI), .B(B0), .C(C0), .D(GNDI), + lut40184 \un9_RA_i_m2_i_m2[5] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40183 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hACAC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40184 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAFA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_117 ( input D1, A1, D0, C0, output F0, F1 ); + wire GNDI; + + lut40185 nRowColSel_0_0_x2( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40186 RCKEEN_8_u_0_o3( .A(GNDI), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40185 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h55AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40186 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_118 ( input D1, C1, C0, B0, output F0, F1 ); + wire GNDI; + + lut40187 \wb_dati_5_1_iv_0_a2_7[4] ( .A(GNDI), .B(GNDI), .C(C1), .D(D1), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40172 \wb_dati_5_1_iv_0_a2_11[3] ( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0)); specify @@ -4134,161 +4355,16 @@ module SLICE_113 ( input D1, C1, C0, B0, output F0, F1 ); endmodule -module lut40176 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h000F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40177 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0303) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_114 ( input D1, C1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40178 \un9_RA_i_m2_i_m2[6] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40179 un1_CmdEnable20_0_0_o3_3( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40178 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hAAF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40179 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF7F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_115 ( input D1, C1, A1, D0, C0, B0, output F0, F1 ); - wire GNDI; - - lut40180 \un9_RA_i_m2_i_m2[9] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40181 \un9_RA[8] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40180 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hAFA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40181 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFC0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_116 ( input D1, C1, B1, D0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40182 \un9_RA_i_m2_i_m2[7] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40183 \un9_RA_i_m2_i_m2[0] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40182 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCFC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40183 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCCAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_117 ( input D1, C1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40184 \un9_RA_i_m2_i_m2[5] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40185 \un9_RA_i_m2_i_m2[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40184 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFA50) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40185 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hACAC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_118 ( input D1, C1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40186 \un9_RA_i_m2_i_m2[4] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40187 \un9_RA_i_m2_i_m2[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40186 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF0AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40187 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hE4E4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0F00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_119 ( input D1, C1, B1, A1, D0, B0, output F0, F1 ); +module SLICE_119 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); wire GNDI; - lut40188 CmdLEDEN_4_u_i_0_a3_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40189 XOR8MEG_3_u_0_0_a2_0( .A(GNDI), .B(B0), .C(GNDI), .D(D0), .Z(F0)); + lut40188 CmdLEDEN_4_u_i_m2_i_a2_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40189 XOR8MEG_3_u_0_0_a2_2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -4296,8 +4372,8 @@ module SLICE_119 ( input D1, C1, B1, A1, D0, B0, output F0, F1 ); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule @@ -4309,13 +4385,13 @@ endmodule module lut40189 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0033) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_120 ( input C1, B1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40046 \RBAd[1] ( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40050 \RBAd[1] ( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40190 RA11d( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); @@ -4332,84 +4408,59 @@ endmodule module lut40190 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h84C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hA060) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_121 ( input B1, A1, C0, B0, A0, output F0, F1 ); +module SLICE_121 ( input D1, A1, D0, C0, B0, output F0, F1 ); wire GNDI; - lut40034 wb_cyc_stb_4_iv_0_a3_0_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + lut40052 wb_cyc_stb_4_iv_0_0_a2_0_0( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40191 wb_cyc_stb_4_iv_0_a3_0_3( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40191 wb_cyc_stb_2_sqmuxa_i_a2_1( .A(GNDI), .B(B0), .C(C0), .D(D0), + .Z(F0)); specify - (B1 => F1) = (0:0:0,0:0:0); + (D1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule module lut40191 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0003) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_122 ( input D1, C1, A1, B0, A0, output F0, F1 ); +module SLICE_122 ( input D1, C1, B1, D0, C0, output F0, F1 ); wire GNDI; - lut40192 n8MEGEN_RNO_0( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + lut40192 \wb_adr_5_i_3_0_m2[1] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40193 PHI2r3_RNIFT0I( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40193 IS_0_sqmuxa_0_o2_RNIDJQJ( .A(GNDI), .B(GNDI), .C(C0), .D(D0), + .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); endspecify endmodule module lut40192 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h550F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hCC0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40193 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h4444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_123 ( input D1, B1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40194 \wb_adr_5_i_0_o2[1] ( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40195 InitReady3_0_a3_1( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40194 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h33FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40195 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h000F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RD_0_ ( output PADDI, input IOLDO, PADDT, inout RD0 ); @@ -4458,7 +4509,7 @@ endmodule module Dout_0_ ( input PADDO, output Dout0 ); - xo2iobuf0196 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0)); + xo2iobuf0194 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0)); specify (PADDO => Dout0) = (0:0:0,0:0:0); @@ -4466,14 +4517,14 @@ module Dout_0_ ( input PADDO, output Dout0 ); endmodule -module xo2iobuf0196 ( input I, output PAD ); +module xo2iobuf0194 ( input I, output PAD ); OB INST5( .I(I), .O(PAD)); endmodule module PHI2 ( output PADDI, input PHI2 ); - xo2iobuf0197 PHI2_pad( .Z(PADDI), .PAD(PHI2)); + xo2iobuf0195 PHI2_pad( .Z(PADDI), .PAD(PHI2)); specify (PHI2 => PADDI) = (0:0:0,0:0:0); @@ -4483,7 +4534,7 @@ module PHI2 ( output PADDI, input PHI2 ); endmodule -module xo2iobuf0197 ( output Z, input PAD ); +module xo2iobuf0195 ( output Z, input PAD ); IB INST1( .I(PAD), .O(Z)); endmodule @@ -4513,7 +4564,7 @@ endmodule module RDQML ( input PADDO, output RDQML ); - xo2iobuf0198 RDQML_pad( .I(PADDO), .PAD(RDQML)); + xo2iobuf0196 RDQML_pad( .I(PADDO), .PAD(RDQML)); specify (PADDO => RDQML) = (0:0:0,0:0:0); @@ -4521,14 +4572,14 @@ module RDQML ( input PADDO, output RDQML ); endmodule -module xo2iobuf0198 ( input I, output PAD ); +module xo2iobuf0196 ( input I, output PAD ); OB INST5( .I(I), .O(PAD)); endmodule module RDQMH ( input PADDO, output RDQMH ); - xo2iobuf0198 RDQMH_pad( .I(PADDO), .PAD(RDQMH)); + xo2iobuf0196 RDQMH_pad( .I(PADDO), .PAD(RDQMH)); specify (PADDO => RDQMH) = (0:0:0,0:0:0); @@ -4538,7 +4589,7 @@ endmodule module nRCAS ( input IOLDO, output nRCAS ); - xo2iobuf0198 nRCAS_pad( .I(IOLDO), .PAD(nRCAS)); + xo2iobuf0196 nRCAS_pad( .I(IOLDO), .PAD(nRCAS)); specify (IOLDO => nRCAS) = (0:0:0,0:0:0); @@ -4549,7 +4600,7 @@ endmodule module nRCAS_MGIOL ( output IOLDO, input OPOS, CLK ); wire VCCI, GNDI, OPOS_dly, CLK_dly; - mfflsre0199 nRCAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + mfflsre0197 nRCAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); @@ -4563,7 +4614,7 @@ module nRCAS_MGIOL ( output IOLDO, input OPOS, CLK ); endmodule -module mfflsre0199 ( input D0, SP, CK, LSR, output Q ); +module mfflsre0197 ( input D0, SP, CK, LSR, output Q ); FD1P3BX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q)); defparam INST01.GSR = "DISABLED"; @@ -4571,7 +4622,7 @@ endmodule module nRRAS ( input IOLDO, output nRRAS ); - xo2iobuf0198 nRRAS_pad( .I(IOLDO), .PAD(nRRAS)); + xo2iobuf0196 nRRAS_pad( .I(IOLDO), .PAD(nRRAS)); specify (IOLDO => nRRAS) = (0:0:0,0:0:0); @@ -4582,7 +4633,7 @@ endmodule module nRRAS_MGIOL ( output IOLDO, input OPOS, CLK ); wire VCCI, GNDI, OPOS_dly, CLK_dly; - mfflsre0199 nRRAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + mfflsre0197 nRRAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); @@ -4598,7 +4649,7 @@ endmodule module nRWE ( input IOLDO, output nRWE ); - xo2iobuf0198 nRWE_pad( .I(IOLDO), .PAD(nRWE)); + xo2iobuf0196 nRWE_pad( .I(IOLDO), .PAD(nRWE)); specify (IOLDO => nRWE) = (0:0:0,0:0:0); @@ -4609,7 +4660,7 @@ endmodule module nRWE_MGIOL ( output IOLDO, input OPOS, CLK ); wire VCCI, GNDI, OPOS_dly, CLK_dly; - mfflsre0199 nRWE_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + mfflsre0197 nRWE_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); @@ -4625,7 +4676,7 @@ endmodule module RCKE ( input PADDO, output RCKE ); - xo2iobuf0198 RCKE_pad( .I(PADDO), .PAD(RCKE)); + xo2iobuf0196 RCKE_pad( .I(PADDO), .PAD(RCKE)); specify (PADDO => RCKE) = (0:0:0,0:0:0); @@ -4633,9 +4684,47 @@ module RCKE ( input PADDO, output RCKE ); endmodule +module RCLKout ( input IOLDO, output RCLKout ); + + xo2iobuf0198 RCLKout_pad( .I(IOLDO), .PAD(RCLKout)); + + specify + (IOLDO => RCLKout) = (0:0:0,0:0:0); + endspecify + +endmodule + +module xo2iobuf0198 ( input I, output PAD ); + + OB INST5( .I(I), .O(PAD)); +endmodule + +module RCLKout_MGIOL ( output IOLDO, input ONEG, OPOS, CLK ); + wire GNDI, ONEG_dly, CLK_dly, OPOS_dly; + + xo2oddr rclk_oddr( .D0(OPOS_dly), .D1(ONEG_dly), .SCLK(CLK_dly), .RST(GNDI), + .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, ONEG, 0:0:0, 0:0:0,,,, CLK_dly, ONEG_dly); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module xo2oddr ( input D0, D1, SCLK, RST, output Q ); + + ODDRXE INST1( .D0(D0), .D1(D1), .SCLK(SCLK), .RST(RST), .Q(Q)); + defparam INST1.GSR = "DISABLED"; +endmodule + module RCLK ( output PADDI, input RCLK ); - xo2iobuf0197 RCLK_pad( .Z(PADDI), .PAD(RCLK)); + xo2iobuf0195 RCLK_pad( .Z(PADDI), .PAD(RCLK)); specify (RCLK => PADDI) = (0:0:0,0:0:0); @@ -4647,7 +4736,7 @@ endmodule module nRCS ( input IOLDO, output nRCS ); - xo2iobuf0198 nRCS_pad( .I(IOLDO), .PAD(nRCS)); + xo2iobuf0196 nRCS_pad( .I(IOLDO), .PAD(nRCS)); specify (IOLDO => nRCS) = (0:0:0,0:0:0); @@ -4658,7 +4747,7 @@ endmodule module nRCS_MGIOL ( output IOLDO, input OPOS, CLK ); wire VCCI, GNDI, OPOS_dly, CLK_dly; - mfflsre0199 nRCS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + mfflsre0197 nRCS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); @@ -4898,7 +4987,7 @@ endmodule module RA_11_ ( input IOLDO, output RA11 ); - xo2iobuf0198 \RA_pad[11] ( .I(IOLDO), .PAD(RA11)); + xo2iobuf0196 \RA_pad[11] ( .I(IOLDO), .PAD(RA11)); specify (IOLDO => RA11) = (0:0:0,0:0:0); @@ -4925,7 +5014,7 @@ endmodule module RA_10_ ( input IOLDO, output RA10 ); - xo2iobuf0198 \RA_pad[10] ( .I(IOLDO), .PAD(RA10)); + xo2iobuf0196 \RA_pad[10] ( .I(IOLDO), .PAD(RA10)); specify (IOLDO => RA10) = (0:0:0,0:0:0); @@ -4936,7 +5025,7 @@ endmodule module RA_10__MGIOL ( output IOLDO, input OPOS, LSR, CLK ); wire VCCI, OPOS_dly, CLK_dly, LSR_dly; - mfflsre0200 RA10_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), + mfflsre0199 RA10_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -4950,7 +5039,7 @@ module RA_10__MGIOL ( output IOLDO, input OPOS, LSR, CLK ); endmodule -module mfflsre0200 ( input D0, SP, CK, LSR, output Q ); +module mfflsre0199 ( input D0, SP, CK, LSR, output Q ); FD1P3JX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q)); defparam INST01.GSR = "DISABLED"; @@ -4958,7 +5047,7 @@ endmodule module RA_9_ ( input PADDO, output RA9 ); - xo2iobuf0198 \RA_pad[9] ( .I(PADDO), .PAD(RA9)); + xo2iobuf0196 \RA_pad[9] ( .I(PADDO), .PAD(RA9)); specify (PADDO => RA9) = (0:0:0,0:0:0); @@ -4968,7 +5057,7 @@ endmodule module RA_8_ ( input PADDO, output RA8 ); - xo2iobuf0198 \RA_pad[8] ( .I(PADDO), .PAD(RA8)); + xo2iobuf0196 \RA_pad[8] ( .I(PADDO), .PAD(RA8)); specify (PADDO => RA8) = (0:0:0,0:0:0); @@ -4978,7 +5067,7 @@ endmodule module RA_7_ ( input PADDO, output RA7 ); - xo2iobuf0198 \RA_pad[7] ( .I(PADDO), .PAD(RA7)); + xo2iobuf0196 \RA_pad[7] ( .I(PADDO), .PAD(RA7)); specify (PADDO => RA7) = (0:0:0,0:0:0); @@ -4988,7 +5077,7 @@ endmodule module RA_6_ ( input PADDO, output RA6 ); - xo2iobuf0198 \RA_pad[6] ( .I(PADDO), .PAD(RA6)); + xo2iobuf0196 \RA_pad[6] ( .I(PADDO), .PAD(RA6)); specify (PADDO => RA6) = (0:0:0,0:0:0); @@ -4998,7 +5087,7 @@ endmodule module RA_5_ ( input PADDO, output RA5 ); - xo2iobuf0198 \RA_pad[5] ( .I(PADDO), .PAD(RA5)); + xo2iobuf0196 \RA_pad[5] ( .I(PADDO), .PAD(RA5)); specify (PADDO => RA5) = (0:0:0,0:0:0); @@ -5008,7 +5097,7 @@ endmodule module RA_4_ ( input PADDO, output RA4 ); - xo2iobuf0198 \RA_pad[4] ( .I(PADDO), .PAD(RA4)); + xo2iobuf0196 \RA_pad[4] ( .I(PADDO), .PAD(RA4)); specify (PADDO => RA4) = (0:0:0,0:0:0); @@ -5018,7 +5107,7 @@ endmodule module RA_3_ ( input PADDO, output RA3 ); - xo2iobuf0198 \RA_pad[3] ( .I(PADDO), .PAD(RA3)); + xo2iobuf0196 \RA_pad[3] ( .I(PADDO), .PAD(RA3)); specify (PADDO => RA3) = (0:0:0,0:0:0); @@ -5028,7 +5117,7 @@ endmodule module RA_2_ ( input PADDO, output RA2 ); - xo2iobuf0198 \RA_pad[2] ( .I(PADDO), .PAD(RA2)); + xo2iobuf0196 \RA_pad[2] ( .I(PADDO), .PAD(RA2)); specify (PADDO => RA2) = (0:0:0,0:0:0); @@ -5038,7 +5127,7 @@ endmodule module RA_1_ ( input PADDO, output RA1 ); - xo2iobuf0198 \RA_pad[1] ( .I(PADDO), .PAD(RA1)); + xo2iobuf0196 \RA_pad[1] ( .I(PADDO), .PAD(RA1)); specify (PADDO => RA1) = (0:0:0,0:0:0); @@ -5048,7 +5137,7 @@ endmodule module RA_0_ ( input PADDO, output RA0 ); - xo2iobuf0198 \RA_pad[0] ( .I(PADDO), .PAD(RA0)); + xo2iobuf0196 \RA_pad[0] ( .I(PADDO), .PAD(RA0)); specify (PADDO => RA0) = (0:0:0,0:0:0); @@ -5058,7 +5147,7 @@ endmodule module RBA_1_ ( input IOLDO, output RBA1 ); - xo2iobuf0198 \RBA_pad[1] ( .I(IOLDO), .PAD(RBA1)); + xo2iobuf0196 \RBA_pad[1] ( .I(IOLDO), .PAD(RBA1)); specify (IOLDO => RBA1) = (0:0:0,0:0:0); @@ -5086,7 +5175,7 @@ endmodule module RBA_0_ ( input IOLDO, output RBA0 ); - xo2iobuf0198 \RBA_pad[0] ( .I(IOLDO), .PAD(RBA0)); + xo2iobuf0196 \RBA_pad[0] ( .I(IOLDO), .PAD(RBA0)); specify (IOLDO => RBA0) = (0:0:0,0:0:0); @@ -5114,7 +5203,7 @@ endmodule module LED ( input PADDO, output LED ); - xo2iobuf0201 LED_pad( .I(PADDO), .PAD(LED)); + xo2iobuf0200 LED_pad( .I(PADDO), .PAD(LED)); specify (PADDO => LED) = (0:0:0,0:0:0); @@ -5122,14 +5211,14 @@ module LED ( input PADDO, output LED ); endmodule -module xo2iobuf0201 ( input I, output PAD ); +module xo2iobuf0200 ( input I, output PAD ); OB INST5( .I(I), .O(PAD)); endmodule module nFWE ( output PADDI, input nFWE ); - xo2iobuf0197 nFWE_pad( .Z(PADDI), .PAD(nFWE)); + xo2iobuf0195 nFWE_pad( .Z(PADDI), .PAD(nFWE)); specify (nFWE => PADDI) = (0:0:0,0:0:0); @@ -5141,7 +5230,7 @@ endmodule module nCRAS ( output PADDI, input nCRAS ); - xo2iobuf0197 nCRAS_pad( .Z(PADDI), .PAD(nCRAS)); + xo2iobuf0195 nCRAS_pad( .Z(PADDI), .PAD(nCRAS)); specify (nCRAS => PADDI) = (0:0:0,0:0:0); @@ -5153,7 +5242,7 @@ endmodule module nCCAS ( output PADDI, input nCCAS ); - xo2iobuf0197 nCCAS_pad( .Z(PADDI), .PAD(nCCAS)); + xo2iobuf0195 nCCAS_pad( .Z(PADDI), .PAD(nCCAS)); specify (nCCAS => PADDI) = (0:0:0,0:0:0); @@ -5165,7 +5254,7 @@ endmodule module Dout_7_ ( input PADDO, output Dout7 ); - xo2iobuf0196 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7)); + xo2iobuf0194 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7)); specify (PADDO => Dout7) = (0:0:0,0:0:0); @@ -5175,7 +5264,7 @@ endmodule module Dout_6_ ( input PADDO, output Dout6 ); - xo2iobuf0196 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6)); + xo2iobuf0194 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6)); specify (PADDO => Dout6) = (0:0:0,0:0:0); @@ -5185,7 +5274,7 @@ endmodule module Dout_5_ ( input PADDO, output Dout5 ); - xo2iobuf0196 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5)); + xo2iobuf0194 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5)); specify (PADDO => Dout5) = (0:0:0,0:0:0); @@ -5195,7 +5284,7 @@ endmodule module Dout_4_ ( input PADDO, output Dout4 ); - xo2iobuf0196 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4)); + xo2iobuf0194 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4)); specify (PADDO => Dout4) = (0:0:0,0:0:0); @@ -5205,7 +5294,7 @@ endmodule module Dout_3_ ( input PADDO, output Dout3 ); - xo2iobuf0196 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3)); + xo2iobuf0194 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3)); specify (PADDO => Dout3) = (0:0:0,0:0:0); @@ -5215,7 +5304,7 @@ endmodule module Dout_2_ ( input PADDO, output Dout2 ); - xo2iobuf0196 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2)); + xo2iobuf0194 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2)); specify (PADDO => Dout2) = (0:0:0,0:0:0); @@ -5225,7 +5314,7 @@ endmodule module Dout_1_ ( input PADDO, output Dout1 ); - xo2iobuf0196 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1)); + xo2iobuf0194 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1)); specify (PADDO => Dout1) = (0:0:0,0:0:0); @@ -5235,7 +5324,7 @@ endmodule module Din_7_ ( output PADDI, input Din7 ); - xo2iobuf0197 \Din_pad[7] ( .Z(PADDI), .PAD(Din7)); + xo2iobuf0195 \Din_pad[7] ( .Z(PADDI), .PAD(Din7)); specify (Din7 => PADDI) = (0:0:0,0:0:0); @@ -5264,7 +5353,7 @@ endmodule module Din_6_ ( output PADDI, input Din6 ); - xo2iobuf0197 \Din_pad[6] ( .Z(PADDI), .PAD(Din6)); + xo2iobuf0195 \Din_pad[6] ( .Z(PADDI), .PAD(Din6)); specify (Din6 => PADDI) = (0:0:0,0:0:0); @@ -5293,7 +5382,7 @@ endmodule module Din_5_ ( output PADDI, input Din5 ); - xo2iobuf0197 \Din_pad[5] ( .Z(PADDI), .PAD(Din5)); + xo2iobuf0195 \Din_pad[5] ( .Z(PADDI), .PAD(Din5)); specify (Din5 => PADDI) = (0:0:0,0:0:0); @@ -5322,7 +5411,7 @@ endmodule module Din_4_ ( output PADDI, input Din4 ); - xo2iobuf0197 \Din_pad[4] ( .Z(PADDI), .PAD(Din4)); + xo2iobuf0195 \Din_pad[4] ( .Z(PADDI), .PAD(Din4)); specify (Din4 => PADDI) = (0:0:0,0:0:0); @@ -5351,7 +5440,7 @@ endmodule module Din_3_ ( output PADDI, input Din3 ); - xo2iobuf0197 \Din_pad[3] ( .Z(PADDI), .PAD(Din3)); + xo2iobuf0195 \Din_pad[3] ( .Z(PADDI), .PAD(Din3)); specify (Din3 => PADDI) = (0:0:0,0:0:0); @@ -5380,7 +5469,7 @@ endmodule module Din_2_ ( output PADDI, input Din2 ); - xo2iobuf0197 \Din_pad[2] ( .Z(PADDI), .PAD(Din2)); + xo2iobuf0195 \Din_pad[2] ( .Z(PADDI), .PAD(Din2)); specify (Din2 => PADDI) = (0:0:0,0:0:0); @@ -5409,7 +5498,7 @@ endmodule module Din_1_ ( output PADDI, input Din1 ); - xo2iobuf0197 \Din_pad[1] ( .Z(PADDI), .PAD(Din1)); + xo2iobuf0195 \Din_pad[1] ( .Z(PADDI), .PAD(Din1)); specify (Din1 => PADDI) = (0:0:0,0:0:0); @@ -5438,7 +5527,7 @@ endmodule module Din_0_ ( output PADDI, input Din0 ); - xo2iobuf0197 \Din_pad[0] ( .Z(PADDI), .PAD(Din0)); + xo2iobuf0195 \Din_pad[0] ( .Z(PADDI), .PAD(Din0)); specify (Din0 => PADDI) = (0:0:0,0:0:0); @@ -5467,7 +5556,7 @@ endmodule module CROW_1_ ( output PADDI, input CROW1 ); - xo2iobuf0197 \CROW_pad[1] ( .Z(PADDI), .PAD(CROW1)); + xo2iobuf0195 \CROW_pad[1] ( .Z(PADDI), .PAD(CROW1)); specify (CROW1 => PADDI) = (0:0:0,0:0:0); @@ -5479,7 +5568,7 @@ endmodule module CROW_0_ ( output PADDI, input CROW0 ); - xo2iobuf0197 \CROW_pad[0] ( .Z(PADDI), .PAD(CROW0)); + xo2iobuf0195 \CROW_pad[0] ( .Z(PADDI), .PAD(CROW0)); specify (CROW0 => PADDI) = (0:0:0,0:0:0); @@ -5491,7 +5580,7 @@ endmodule module MAin_9_ ( output PADDI, input MAin9 ); - xo2iobuf0197 \MAin_pad[9] ( .Z(PADDI), .PAD(MAin9)); + xo2iobuf0195 \MAin_pad[9] ( .Z(PADDI), .PAD(MAin9)); specify (MAin9 => PADDI) = (0:0:0,0:0:0); @@ -5503,7 +5592,7 @@ endmodule module MAin_8_ ( output PADDI, input MAin8 ); - xo2iobuf0197 \MAin_pad[8] ( .Z(PADDI), .PAD(MAin8)); + xo2iobuf0195 \MAin_pad[8] ( .Z(PADDI), .PAD(MAin8)); specify (MAin8 => PADDI) = (0:0:0,0:0:0); @@ -5515,7 +5604,7 @@ endmodule module MAin_7_ ( output PADDI, input MAin7 ); - xo2iobuf0197 \MAin_pad[7] ( .Z(PADDI), .PAD(MAin7)); + xo2iobuf0195 \MAin_pad[7] ( .Z(PADDI), .PAD(MAin7)); specify (MAin7 => PADDI) = (0:0:0,0:0:0); @@ -5527,7 +5616,7 @@ endmodule module MAin_6_ ( output PADDI, input MAin6 ); - xo2iobuf0197 \MAin_pad[6] ( .Z(PADDI), .PAD(MAin6)); + xo2iobuf0195 \MAin_pad[6] ( .Z(PADDI), .PAD(MAin6)); specify (MAin6 => PADDI) = (0:0:0,0:0:0); @@ -5539,7 +5628,7 @@ endmodule module MAin_5_ ( output PADDI, input MAin5 ); - xo2iobuf0197 \MAin_pad[5] ( .Z(PADDI), .PAD(MAin5)); + xo2iobuf0195 \MAin_pad[5] ( .Z(PADDI), .PAD(MAin5)); specify (MAin5 => PADDI) = (0:0:0,0:0:0); @@ -5551,7 +5640,7 @@ endmodule module MAin_4_ ( output PADDI, input MAin4 ); - xo2iobuf0197 \MAin_pad[4] ( .Z(PADDI), .PAD(MAin4)); + xo2iobuf0195 \MAin_pad[4] ( .Z(PADDI), .PAD(MAin4)); specify (MAin4 => PADDI) = (0:0:0,0:0:0); @@ -5563,7 +5652,7 @@ endmodule module MAin_3_ ( output PADDI, input MAin3 ); - xo2iobuf0197 \MAin_pad[3] ( .Z(PADDI), .PAD(MAin3)); + xo2iobuf0195 \MAin_pad[3] ( .Z(PADDI), .PAD(MAin3)); specify (MAin3 => PADDI) = (0:0:0,0:0:0); @@ -5575,7 +5664,7 @@ endmodule module MAin_2_ ( output PADDI, input MAin2 ); - xo2iobuf0197 \MAin_pad[2] ( .Z(PADDI), .PAD(MAin2)); + xo2iobuf0195 \MAin_pad[2] ( .Z(PADDI), .PAD(MAin2)); specify (MAin2 => PADDI) = (0:0:0,0:0:0); @@ -5587,7 +5676,7 @@ endmodule module MAin_1_ ( output PADDI, input MAin1 ); - xo2iobuf0197 \MAin_pad[1] ( .Z(PADDI), .PAD(MAin1)); + xo2iobuf0195 \MAin_pad[1] ( .Z(PADDI), .PAD(MAin1)); specify (MAin1 => PADDI) = (0:0:0,0:0:0); @@ -5599,7 +5688,7 @@ endmodule module MAin_0_ ( output PADDI, input MAin0 ); - xo2iobuf0197 \MAin_pad[0] ( .Z(PADDI), .PAD(MAin0)); + xo2iobuf0195 \MAin_pad[0] ( .Z(PADDI), .PAD(MAin0)); specify (MAin0 => PADDI) = (0:0:0,0:0:0); diff --git a/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html b/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html index f41c5be..5dfe34a 100644 --- a/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html +++ b/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html @@ -2,13 +2,15 @@ Starting: parse design source files (VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v' (VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v' +WARNING - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v(23,47-23,52) (VERI-1875) identifier 'Ready' is used before its declaration (VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/REFB.v' INFO - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v(1,8-1,14) (VERI-1018) compiling module 'RAM2GS' -INFO - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v(1,1-615,10) (VERI-9000) elaborating module 'RAM2GS' +INFO - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v(1,1-618,10) (VERI-9000) elaborating module 'RAM2GS' +INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1601,1-1606,10) (VERI-9000) elaborating module 'ODDRXE_uniq_1' INFO - //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/REFB.v(8,1-113,10) (VERI-9000) elaborating module 'REFB_uniq_1' INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_1' INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_1' INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1800,1-1872,10) (VERI-9000) elaborating module 'EFB_uniq_1' -Done: design load finished with (0) errors, and (0) warnings +Done: design load finished with (0) errors, and (1) warnings \ No newline at end of file diff --git a/CPLD/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1.ior b/CPLD/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1.ior index 3ad87ea..e6ed6ac 100644 --- a/CPLD/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1.ior +++ b/CPLD/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1.ior @@ -29,7 +29,7 @@ Performance Hardware Data Status: Final Version 34.4. // Package: TQFP100 // ncd File: ram2gs_lcmxo2_640hc_impl1.ncd // Version: Diamond (64-bit) 3.12.1.454 -// Written on Thu Sep 21 05:40:03 2023 +// Written on Sat Nov 18 02:06:14 2023 // M: Minimum Performance Grade // iotiming RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml @@ -41,94 +41,95 @@ Worst Case Results across Performance Grades (M, 6, 5, 4): Port Clock Edge Setup Performance_Grade Hold Performance_Grade ---------------------------------------------------------------------- -CROW[0] nCRAS F 2.429 4 -0.163 M -CROW[1] nCRAS F 1.927 4 -0.005 M -Din[0] PHI2 F 5.424 4 3.636 4 -Din[0] nCCAS F 1.913 4 -0.130 M -Din[1] PHI2 F 5.162 4 3.516 4 -Din[1] nCCAS F 2.007 4 -0.156 M -Din[2] PHI2 F 5.078 4 3.516 4 -Din[2] nCCAS F 0.876 4 0.346 4 -Din[3] PHI2 F 6.152 4 3.516 4 -Din[3] nCCAS F 0.245 4 0.869 4 -Din[4] PHI2 F 5.240 4 3.516 4 -Din[4] nCCAS F 0.714 4 0.460 4 -Din[5] PHI2 F 6.035 4 3.516 4 -Din[5] nCCAS F 0.751 4 0.419 4 -Din[6] PHI2 F 4.496 4 3.636 4 -Din[6] nCCAS F 1.518 4 -0.020 M -Din[7] PHI2 F 4.936 4 3.636 4 -Din[7] nCCAS F 1.852 4 -0.081 M -MAin[0] PHI2 F 5.207 4 0.531 4 -MAin[0] nCRAS F 1.658 4 0.036 M -MAin[1] PHI2 F 3.450 4 0.460 4 -MAin[1] nCRAS F 2.014 4 -0.043 M -MAin[2] PHI2 F 7.941 4 -0.604 M -MAin[2] nCRAS F 1.001 4 0.498 4 -MAin[3] PHI2 F 8.770 4 -0.865 M -MAin[3] nCRAS F 2.190 4 -0.151 M -MAin[4] PHI2 F 9.575 4 -1.072 M -MAin[4] nCRAS F 1.331 4 0.186 4 -MAin[5] PHI2 F 9.093 4 -0.925 M -MAin[5] nCRAS F 1.329 4 0.186 4 -MAin[6] PHI2 F 9.450 4 -1.036 M -MAin[6] nCRAS F 1.323 4 0.191 4 -MAin[7] PHI2 F 8.247 4 -0.706 M -MAin[7] nCRAS F 1.258 4 0.267 4 -MAin[8] nCRAS F 0.994 4 0.504 4 -MAin[9] nCRAS F 0.614 4 0.830 4 +CROW[0] nCRAS F 2.058 4 -0.092 M +CROW[1] nCRAS F 2.269 4 -0.117 M +Din[0] PHI2 F 7.415 4 3.636 4 +Din[0] nCCAS F 2.760 4 -0.330 M +Din[1] PHI2 F 6.384 4 3.516 4 +Din[1] nCCAS F 1.112 4 0.128 4 +Din[2] PHI2 F 6.717 4 3.516 4 +Din[2] nCCAS F 0.113 4 0.982 4 +Din[3] PHI2 F 5.806 4 3.516 4 +Din[3] nCCAS F 1.105 4 0.134 4 +Din[4] PHI2 F 6.853 4 3.516 4 +Din[4] nCCAS F 1.538 4 -0.010 M +Din[5] PHI2 F 7.478 4 3.516 4 +Din[5] nCCAS F 0.714 4 0.460 4 +Din[6] PHI2 F 5.667 4 3.636 4 +Din[6] nCCAS F 1.504 4 -0.015 M +Din[7] PHI2 F 5.567 4 3.636 4 +Din[7] nCCAS F 1.063 4 0.194 4 +MAin[0] PHI2 F 4.483 4 0.742 4 +MAin[0] nCRAS F 1.204 4 0.334 4 +MAin[1] PHI2 F 4.440 4 0.520 4 +MAin[1] nCRAS F 1.245 4 0.313 4 +MAin[2] PHI2 F 9.497 4 -0.729 M +MAin[2] nCRAS F 0.758 4 0.714 4 +MAin[3] PHI2 F 9.534 4 -0.752 M +MAin[3] nCRAS F 0.454 4 0.874 4 +MAin[4] PHI2 F 7.882 4 -0.326 M +MAin[4] nCRAS F 0.832 4 0.632 4 +MAin[5] PHI2 F 10.136 4 -0.894 M +MAin[5] nCRAS F 0.830 4 0.632 4 +MAin[6] PHI2 F 8.759 4 -0.555 M +MAin[6] nCRAS F 1.259 4 0.268 4 +MAin[7] PHI2 F 8.430 4 -0.434 M +MAin[7] nCRAS F 0.881 4 0.510 4 +MAin[8] nCRAS F 1.066 4 0.422 4 +MAin[9] nCRAS F 0.723 4 0.746 4 PHI2 RCLK R -0.005 M 2.116 4 -nCCAS RCLK R 3.191 4 -0.531 M -nCCAS nCRAS F 3.195 4 -0.341 M -nCRAS RCLK R 2.797 4 -0.402 M -nFWE PHI2 F 8.238 4 -0.666 M -nFWE nCRAS F 1.140 4 0.400 4 +nCCAS RCLK R 3.614 4 -0.637 M +nCCAS nCRAS F 3.629 4 -0.447 M +nCRAS RCLK R 3.040 4 -0.485 M +nFWE PHI2 F 8.830 4 -0.567 M +nFWE nCRAS F 0.454 4 0.874 4 // Clock to Output Delay -Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade +Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade ------------------------------------------------------------------------ -LED RCLK R 10.962 4 3.218 M -LED nCRAS F 10.815 4 3.159 M -RA[0] RCLK R 10.143 4 3.128 M -RA[0] nCRAS F 11.178 4 3.358 M -RA[10] RCLK R 7.578 4 2.578 M -RA[11] PHI2 R 9.098 4 3.021 M -RA[1] RCLK R 10.676 4 3.248 M -RA[1] nCRAS F 11.215 4 3.370 M -RA[2] RCLK R 11.199 4 3.402 M -RA[2] nCRAS F 11.518 4 3.451 M -RA[3] RCLK R 10.446 4 3.209 M -RA[3] nCRAS F 11.264 4 3.364 M -RA[4] RCLK R 10.446 4 3.209 M -RA[4] nCRAS F 11.484 4 3.438 M -RA[5] RCLK R 11.199 4 3.402 M -RA[5] nCRAS F 11.264 4 3.364 M -RA[6] RCLK R 11.424 4 3.444 M -RA[6] nCRAS F 11.388 4 3.388 M -RA[7] RCLK R 11.112 4 3.370 M -RA[7] nCRAS F 11.608 4 3.487 M -RA[8] RCLK R 10.916 4 3.308 M -RA[8] nCRAS F 11.380 4 3.415 M -RA[9] RCLK R 11.115 4 3.362 M -RA[9] nCRAS F 11.201 4 3.380 M -RBA[0] nCRAS F 8.645 4 2.828 M -RBA[1] nCRAS F 8.645 4 2.828 M -RCKE RCLK R 8.593 4 2.793 M -RDQMH RCLK R 10.909 4 3.327 M -RDQML RCLK R 10.348 4 3.207 M -RD[0] nCCAS F 8.761 4 2.984 M -RD[1] nCCAS F 8.761 4 2.984 M -RD[2] nCCAS F 8.761 4 2.984 M -RD[3] nCCAS F 8.761 4 2.984 M -RD[4] nCCAS F 8.761 4 2.984 M -RD[5] nCCAS F 8.761 4 2.984 M -RD[6] nCCAS F 8.761 4 2.984 M -RD[7] nCCAS F 8.761 4 2.984 M -nRCAS RCLK R 7.578 4 2.578 M -nRCS RCLK R 7.578 4 2.578 M -nRRAS RCLK R 7.578 4 2.578 M -nRWE RCLK R 7.558 4 2.585 M +LED RCLK R 11.284 4 2.893 M +LED nCRAS F 11.111 4 3.244 M +RA[0] RCLK R 10.888 4 3.313 M +RA[0] nCRAS F 11.968 4 3.554 M +RA[10] RCLK R 7.578 4 2.578 M +RA[11] PHI2 R 9.098 4 3.021 M +RA[1] RCLK R 11.272 4 3.408 M +RA[1] nCRAS F 11.484 4 3.438 M +RA[2] RCLK R 11.749 4 3.528 M +RA[2] nCRAS F 11.267 4 3.385 M +RA[3] RCLK R 11.291 4 3.431 M +RA[3] nCRAS F 11.596 4 3.449 M +RA[4] RCLK R 10.696 4 3.276 M +RA[4] nCRAS F 11.720 4 3.503 M +RA[5] RCLK R 11.228 4 3.401 M +RA[5] nCRAS F 11.364 4 3.427 M +RA[6] RCLK R 10.132 4 3.112 M +RA[6] nCRAS F 10.958 4 3.284 M +RA[7] RCLK R 11.404 4 3.446 M +RA[7] nCRAS F 11.918 4 3.561 M +RA[8] RCLK R 10.488 4 3.236 M +RA[8] nCRAS F 11.512 4 3.463 M +RA[9] RCLK R 10.941 4 3.329 M +RA[9] nCRAS F 11.074 4 3.356 M +RBA[0] nCRAS F 8.645 4 2.828 M +RBA[1] nCRAS F 8.625 4 2.835 M +RCKE RCLK R 9.454 4 3.006 M +RCLKout RCLK R 6.857 4 1.980 M +RDQMH RCLK R 9.846 4 3.033 M +RDQML RCLK R 9.741 4 3.008 M +RD[0] nCCAS F 8.761 4 2.984 M +RD[1] nCCAS F 8.761 4 2.984 M +RD[2] nCCAS F 8.761 4 2.984 M +RD[3] nCCAS F 8.761 4 2.984 M +RD[4] nCCAS F 8.761 4 2.984 M +RD[5] nCCAS F 8.761 4 2.984 M +RD[6] nCCAS F 8.761 4 2.984 M +RD[7] nCCAS F 8.761 4 2.984 M +nRCAS RCLK R 7.578 4 2.578 M +nRCS RCLK R 7.578 4 2.578 M +nRRAS RCLK R 7.578 4 2.578 M +nRWE RCLK R 7.558 4 2.585 M WARNING: you must also run trce with hold speed: 4 WARNING: you must also run trce with setup speed: M diff --git a/CPLD/LCMXO2-640HC/promote.xml b/CPLD/LCMXO2-640HC/promote.xml index 8355e58..ef76b55 100644 --- a/CPLD/LCMXO2-640HC/promote.xml +++ b/CPLD/LCMXO2-640HC/promote.xml @@ -1,3 +1,3 @@ - + diff --git a/CPLD/LCMXO2-640HC/reportview.xml b/CPLD/LCMXO2-640HC/reportview.xml index ae61983..a30cbc4 100644 --- a/CPLD/LCMXO2-640HC/reportview.xml +++ b/CPLD/LCMXO2-640HC/reportview.xml @@ -3,7 +3,7 @@ - + diff --git a/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcl.html b/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcl.html new file mode 100644 index 0000000..982f141 --- /dev/null +++ b/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcl.html @@ -0,0 +1,70 @@ + +Lattice TCL Log + + +
    pn231119195558
+#Start recording tcl command: 11/18/2023 02:19:05
+#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO256C; Project name: RAM2GS_LCMXO256C
+prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO256C/RAM2GS_LCMXO256C.ldf"
+prj_run Export -impl impl1
+#Stop recording: 11/19/2023 19:55:58
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    + + diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.alt b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.alt index c0ae716..d413639 100644 --- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.alt +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.alt @@ -1,6 +1,6 @@ NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation * NOTE All Rights Reserved * -NOTE DATE CREATED: Thu Sep 21 05:38:47 2023 * +NOTE DATE CREATED: Sat Jan 06 06:25:16 2024 * NOTE DESIGN NAME: RAM2GS * NOTE DEVICE NAME: LCMXO256C-3TQFP100 * NOTE PIN ASSIGNMENTS * diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.areasrr b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.areasrr index 2a05ec7..e75d021 100644 --- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.areasrr +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.areasrr @@ -15,12 +15,12 @@ I/O cells: 67 FD1S3JX 3 100.0 GSR 1 100.0 IB 26 100.0 - INV 8 100.0 + INV 7 100.0 OB 33 100.0 - ORCALUT4 119 100.0 - PFUMX 2 100.0 + ORCALUT4 133 100.0 + PFUMX 1 100.0 PUR 1 100.0 VHI 1 100.0 VLO 1 100.0 - TOTAL 301 + TOTAL 313 diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.bgn b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.bgn index edab200..9a5951b 100644 --- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.bgn +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.bgn @@ -4,7 +4,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Thu Sep 21 05:38:46 2023 +Sat Jan 06 06:25:15 2024 Command: bitgen -w -g ES:No -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.bit b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.bit index 3674576..93d698a 100644 Binary files a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.bit and b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.bit differ diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.edi b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.edi index e56bfd3..19e77f1 100644 --- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.edi +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.edi @@ -4,7 +4,7 @@ (keywordMap (keywordLevel 0)) (status (written - (timeStamp 2023 9 21 5 38 26) + (timeStamp 2024 1 6 6 24 54) (author "Synopsys, Inc.") (program "Synplify Pro" (version "R-2021.03L-SP1, mapper map202103lat, Build 070R")) ) @@ -196,37 +196,29 @@ (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT))) ) (instance GSR_INST (viewRef PRIM (cellRef GSR (libraryRef LUCENT))) ) - (instance RASr2_RNIAFR1 (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) - (instance (rename IS_i_0 "IS_i[0]") (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) + (instance (rename S_RNO_1 "S_RNO[1]") (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) (instance Ready_fast_RNI29NA (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) (instance nCCAS_pad_RNISUR8 (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) (instance RASr_RNO (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) (instance nFWE_pad_RNI420B (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) - (instance nRCS_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (B+A)+D (!C (!B A+B !A)+C (B+A)))")) - ) - (instance C1Submitted_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (B+A)+D (!C (B+A)+C A))")) - ) (instance nRowColSel_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C (!B A))")) ) - (instance RCKEEN_8_u_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance C1Submitted_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B+A)+C A)+D A)")) + ) + (instance RCKEEN_8_u_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (!C (!B A)+C (!B+!A))+D (C !A))")) ) (instance (rename IS_RNO_3 "IS_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D A+D (!C A+C (!B A+B !A)))")) ) + (instance UFMCLK_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (B A)+D (!C (B A)+C (B+!A)))")) + ) (instance Ready_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D A+D (!C (B+A)+C A))")) ) - (instance CmdEnable_s (viewRef PRIM (cellRef PFUMX (libraryRef LUCENT))) ) - (instance CmdEnable_s_bm (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B+A)")) - ) - (instance CmdEnable_s_am (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C B+C (B A))+D (!C B+C A))")) - ) (instance nRWE_RNO_1 (viewRef PRIM (cellRef PFUMX (libraryRef LUCENT))) ) (instance nRWE_RNO_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (C (!B !A)))")) @@ -496,173 +488,194 @@ (instance (rename MAin_pad_1 "MAin_pad[1]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) (instance (rename MAin_pad_0 "MAin_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) (instance PHI2_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance CmdEnable17_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (B A)))")) + (instance CmdEnable_s_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C !B)+D (!C (!B A)))")) ) - (instance XOR8MEG18_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (!C (B A)))")) + (instance CmdEnable_s (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(!C A+C B))")) ) - (instance un1_FS_14_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D A+D (!C A+C (B+A)))")) + (instance XOR8MEG_3_u_0_a3_0_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D C+D (C+(!B+!A)))")) ) - (instance un1_FS_13_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D A+D (!C A+C (B+A)))")) - ) - (instance C1WR_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B A)")) - ) - (instance CmdEnable16_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C (B A))")) + (instance ADSubmitted_r_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) ) (instance Cmdn8MEGEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C (!B !A)+C !A)")) ) (instance CmdLEDEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C !B)+D (!C (!B A)))")) + (property lut_function (string "(!C !A+C (B !A))")) ) - (instance RA10_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(!C+(B+A)))")) + (instance un1_CmdEnable20_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B !A))")) ) - (instance C1WR_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (B A)))")) + (instance un1_FS_14_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C (B+A))")) ) - (instance XOR8MEG_3_u_0_a3_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D C+D (C+(!B+!A)))")) + (instance un1_FS_13_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C (B+A))")) + ) + (instance (rename IS_RNO_0 "IS_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B !A+B A)+C A)")) + ) + (instance XOR8MEG18 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) ) (instance UFMSDI_ens2_i_a0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D !A+D (!C !A+C (B !A)))")) + (property lut_function (string "(!D !A+D (!C (!B !A)+C !A))")) ) - (instance un1_FS_13_i_a2_8 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (!B A)))")) + (instance RA10_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(!B+!A)))")) ) - (instance nRRAS_5_u_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(!C (!B A)+C !B))")) + (instance CmdEnable17_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B A)))")) + ) + (instance CmdEnable16_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B A))")) ) (instance un1_nRCAS_6_sqmuxa_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (C+(!B+A))+D (!C (!B+A)))")) ) + (instance IS_0_sqmuxa_0_o2_0_RNIS63D (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B !A)")) + ) (instance UFMSDI_en_ss0_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C (!B !A))")) ) (instance nUFMCS15_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (!C (!B !A)))")) ) + (instance C1WR (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (B A)))")) + ) + (instance ADWR (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B A)))")) + ) + (instance CMDWR (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (B A)))")) + ) (instance Cmdn8MEGEN_4_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B+A)+C A)+D !B)")) + (property lut_function (string "(!D (C A)+D (!C !B+C (!B+A)))")) ) - (instance C1WR_0_a2_0_10 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (B A)))")) + (instance CmdLEDEN_4_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C B)+D (!C (B+!A)+C !A))")) ) - (instance UFMCLK_r_i_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C B)+D A)")) + (instance un1_CmdEnable20_0_a3_0_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B A)))")) ) (instance PHI2r3_RNITCN41 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D !B+D (!C (!B+A)+C !B))")) ) - (instance IS_0_sqmuxa_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B+A)")) + (instance XOR8MEG_3_u_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) ) (instance nRCAS_0_sqmuxa_1_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D (C (!B A)))")) ) - (instance nRowColSel_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C B+C (B+A))+D (!C B+C (B+!A)))")) + (instance LED_pad_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(!C+(!B+A)))")) ) (instance Ready_0_sqmuxa_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D (!C (!B A)))")) ) - (instance XOR8MEG_3_u_0_a3_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (!C (B A)))")) - ) - (instance nRRAS_5_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (!C (B !A)+C !A))")) - ) - (instance (rename IS_RNO_2 "IS_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B A)+C (!B+!A))")) - ) - (instance un1_FS_14_i_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (!C (B A)))")) - ) - (instance UFMSDI_ens2_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C B+C (!B A))")) - ) - (instance XOR8MEG_3_u_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B A)")) - ) - (instance ADSubmitted_r (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C+(!B A)))")) - ) - (instance LED_pad_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C+(!B+A))")) - ) - (instance InitReady3_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance C1WR_7 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D (C (B A)))")) ) - (instance UFMSDI_ens2_i_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C+(B+A))")) - ) (instance Cmdn8MEGEN_4_u_i_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C (B !A))")) ) - (instance CmdLEDEN_4_u_i_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B !A))")) + (instance nRRAS_5_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B !A)+C !A))")) + ) + (instance un1_FS_14_i_a2_0_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B !A)))")) + ) + (instance un1_FS_13_i_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B A)))")) + ) + (instance (rename IS_RNO_2 "IS_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B A)+C (!B+!A))")) + ) + (instance ADSubmitted_r (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+(!B A)))")) + ) + (instance Cmdn8MEGEN_4_u_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(B A))")) + ) + (instance nRowColSel_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C B+C (B+A))+D (!C B+C (B+!A)))")) + ) + (instance UFMSDI_ens2_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C (!B A))")) + ) + (instance un1_FS_14_i_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B A)))")) ) (instance UFMCLK_r_i_a2_2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D (C (!B A)))")) ) - (instance nRowColSel_0_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (!B !A)))")) + (instance UFMSDI_ens2_i_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(B+A))")) ) - (instance CmdEnable16_0_a2_4_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B A)))")) + (instance InitReady3_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) ) - (instance CmdEnable16_0_a2_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (!B A)))")) + (instance ADWR_8 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) ) - (instance CmdEnable17_0_a2_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C (!B A)))")) + (instance C1WR_2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B !A)))")) + ) + (instance CMDWR_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B !A)))")) ) (instance RCKE_2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (C !B)+D (C+(B+A)))")) ) - (instance (rename S_RNO_0 "S_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B+!A)")) - ) (instance Ready_0_sqmuxa_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C+(!B+!A))")) ) - (instance un1_nRCAS_6_sqmuxa_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C+(B+A))")) - ) - (instance Cmdn8MEGEN_4_u_i_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C+(B+!A))")) - ) (instance RA11_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C (!B A+B !A)+C B)")) ) (instance nCCAS_pad_RNI01SJ (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(B+A)")) ) + (instance RCKEEN_8_u_0_a2_0_m1_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B !A))")) + ) (instance InitReady3_0_a2_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D (C (B A)))")) ) - (instance un1_FS_13_i_a2_6 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (!C (!B !A)))")) + (instance CmdEnable17_0_a3_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B !A)))")) ) - (instance un1_Din_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B !A)))")) + (instance Cmdn8MEGEN_4_u_i_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(B+!A))")) + ) + (instance nRowColSel_0_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B !A)))")) + ) + (instance ADWR_8_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance RCKEEN_8_u_0_a3_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (!B+!A))")) + ) + (instance un1_Bank_1_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance un1_Bank_1_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B !A)))")) ) (instance UFMSDI_ens2_i_o2_0_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D+(C+(B+A)))")) ) - (instance C1WR_0_a2_0_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B A))")) + (instance un1_FS_13_i_a2_9_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B !A)))")) ) - (instance C1WR_0_a2_0_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (B A)))")) - ) - (instance C1WR_0_a2_0_11 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (B !A)))")) + (instance un1_FS_13_i_a2_9_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B !A)))")) ) (instance Ready_0_sqmuxa_0_a3_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D (!C (B A)))")) @@ -670,30 +683,15 @@ (instance UFMSDI_ens2_i_a2_4_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D (!C (!B A)))")) ) - (instance un1_FS_13_i_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (!C (!B !A)))")) + (instance CmdEnable16_0_a3_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B A)))")) ) - (instance un1_FS_14_i_a2_0_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance CmdEnable16_0_a3_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (!C (!B !A)))")) ) - (instance n8MEGEN_5_i_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B+A)+C (B A))")) - ) - (instance LEDEN_5_i_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B+A)+C (B A))")) - ) (instance (rename un9_RA_8 "un9_RA[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C B+C A)")) ) - (instance (rename un9_RA_0 "un9_RA[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C B+C A)")) - ) - (instance (rename un9_RA_1 "un9_RA[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C B+C A)")) - ) - (instance (rename un9_RA_2 "un9_RA[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C B+C A)")) - ) (instance (rename un9_RA_3 "un9_RA[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C B+C A)")) ) @@ -706,14 +704,32 @@ (instance (rename un9_RA_6 "un9_RA[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C B+C A)")) ) - (instance (rename un9_RA_7 "un9_RA[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C B+C A)")) - ) (instance (rename un9_RA_9 "un9_RA[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C B+C A)")) ) - (instance InitReady3_0_a2_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B A)")) + (instance (rename un9_RA_7 "un9_RA[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_2 "un9_RA[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_1 "un9_RA[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_0 "un9_RA[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance n8MEGEN_5_i_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B+A)+C (B A))")) + ) + (instance LEDEN_5_i_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B+A)+C (B A))")) + ) + (instance RA10_2_sqmuxa_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance nRCS_9_u_i_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B !A)")) ) (instance (rename S_0_i_o2_1 "S_0_i_o2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(B+A)")) @@ -721,32 +737,56 @@ (instance IS_n1_0_x2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!B A+B !A)")) ) - (instance CmdEnable16_0_a2_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B A)")) - ) - (instance CmdEnable16_0_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B !A)")) + (instance CmdEnable17_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) ) (instance CmdEnable17_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance RDQML (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!B+!A)")) ) (instance RDQMH (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!B+A)")) ) - (instance RDQML (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B+!A)")) - ) - (instance RCKEEN_8_u_0_a2_1_s (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance InitReady3_0_a2_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(B A)")) ) - (instance RCKEEN_8_u_1_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C+B)+D (C (!B+!A)))")) + (instance un1_FS_14_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B+!A)")) ) - (instance RCKEEN_8_u (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D B+D (!C B+C (B+!A)))")) + (instance ADWR_8_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance RCKEEN_8_u_0_1_a1_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B A)")) + ) + (instance RCKEEN_8_u_0_1_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B A))+D (!C !B+C (!B !A)))")) + ) + (instance RCKEEN_8_u_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D B+D (!C (B+!A)+C B))")) ) (instance nRCS_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D !B+D (!C (!B A)+C !B))")) + (property lut_function (string "(!D (!C (!B+!A))+D (!C !B))")) + ) + (instance nRCS_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D B+D (!C (B+!A)+C B))")) + ) + (instance nRCS_RNO_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B !A)))")) + ) + (instance nRCS_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B A)))")) + ) + (instance nRCS_RNO_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(B+A)))")) + ) + (instance nRCS_RNO_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B+A))")) + ) + (instance nRCS_RNO_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B A)")) ) (instance nRWE_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (C+(!B+!A))+D (C+(B !A)))")) @@ -761,13 +801,13 @@ (property lut_function (string "(C (!B A))")) ) (instance nRCAS_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B A)+C !B)+D (!B A))")) - ) - (instance nRCAS_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B !A))+D (!C (!B !A)+C (B !A)))")) + (property lut_function (string "(!D (!C !B)+D (!C (!B+!A)))")) ) (instance nRCAS_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B A)")) + (property lut_function (string "(!C !B+C (!B !A))")) + ) + (instance nRCAS_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D !C+D (C (!B A)))")) ) (instance UFMSDI_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C (!B A)+C !B)")) @@ -784,36 +824,36 @@ (instance nUFMCS_s_0_N_5_i_N_2L1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C (!B+A))")) ) + (instance nRRAS_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B+!A)+C B))")) + ) + (instance CmdLEDEN_4_u_i_a2_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B !A)))")) + ) + (instance un1_nRCAS_6_sqmuxa_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(B+A))")) + ) (instance IS_0_sqmuxa_0_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D+(C+(!B+!A)))")) ) - (instance CmdEnable17_0_a2_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C (B !A)))")) + (instance XOR8MEG_3_u_0_a3_0_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B !A)))")) ) - (instance CmdSubmitted_1_sqmuxa_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!B A)+D (!C (!B A)))")) - ) - (instance CmdLEDEN_4_u_i_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!B A)+D (!C (!B A)+C !B))")) + (instance XOR8MEG_3_u_0_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(B+A)))")) ) (instance CmdUFMCLK_1_sqmuxa_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (C (!B A)))")) ) - (instance nRRAS_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B !A)+C !A)+D (C !A))")) - ) - (instance IS_0_sqmuxa_0_o2_0_RNIS63D (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B !A)")) - ) - (instance (rename IS_RNO_0 "IS_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B !A+B A)+C A)")) - ) - (instance un1_CMDWR (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B A)+C A)")) + (instance CmdSubmitted_1_sqmuxa_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!B A)+D (!C (!B A)))")) ) (instance UFMCLK_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (C+(!B+!A))+D (C+(!B A)))")) ) + (instance CmdEnable_0_sqmuxa (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) (instance (rename FS_cry_0_16 "FS_cry_0[16]") (viewRef PRIM (cellRef CCU2 (libraryRef LUCENT))) (property INIT0 (string "0x300a")) (property INJECT1_1 (string "NO")) @@ -868,44 +908,41 @@ (property INJECT1_0 (string "NO")) (property INIT1 (string "0x300a")) ) - (net C1WR_0_a2 (joined - (portRef Z (instanceRef C1WR_0_a2)) - (portRef B (instanceRef ADSubmitted_r)) - )) (net CBR (joined (portRef Q (instanceRef CBR)) - (portRef A (instanceRef nRWE_RNO_0)) - (portRef A (instanceRef nRCS_RNO)) - (portRef A (instanceRef RCKEEN_8_u)) + (portRef A (instanceRef nRCAS_RNO_1)) + (portRef A (instanceRef RCKEEN_8_u_0)) (portRef B (instanceRef nRowColSel_0_0_a3_0)) (portRef A (instanceRef LED_pad_RNO)) )) (net C1Submitted (joined (portRef Q (instanceRef C1Submitted)) - (portRef D (instanceRef CmdEnable_s_am)) + (portRef A (instanceRef CmdEnable_s_RNO)) (portRef B (instanceRef C1Submitted_RNO)) )) (net (rename Bank_2 "Bank[2]") (joined (portRef Q (instanceRef Bank_2)) - (portRef A (instanceRef C1WR_0_a2_0_11)) + (portRef A (instanceRef un1_Bank_1_5)) )) (net Ready (joined (portRef Q (instanceRef Ready)) - (portRef B (instanceRef IS_RNO_0)) - (portRef A (instanceRef IS_0_sqmuxa_0_o2_0_RNIS63D)) (portRef C (instanceRef nRWE_RNO_2)) - (portRef D (instanceRef RCKEEN_8_u)) - (portRef A (instanceRef RCKEEN_8_u_0_a2_1_s)) + (portRef C (instanceRef nRCS_RNO_3)) + (portRef D (instanceRef RCKEEN_8_u_0)) (portRef D (instanceRef nRowColSel_0_0_a3_0)) + (portRef B (instanceRef RCKEEN_8_u_0_a2_0_m1_0_a2)) + (portRef C (instanceRef nRowColSel_0_0)) (portRef D (instanceRef nRRAS_5_u_i_0)) (portRef C (instanceRef Ready_0_sqmuxa_0_a3)) - (portRef C (instanceRef nRowColSel_0_0)) + (portRef C (instanceRef LED_pad_RNO)) (portRef D (instanceRef nRCAS_0_sqmuxa_1_0_a3)) - (portRef B (instanceRef IS_0_sqmuxa_0_o2)) + (portRef B (instanceRef IS_0_sqmuxa_0_o2_0_RNIS63D)) (portRef C (instanceRef un1_nRCAS_6_sqmuxa_i_0)) + (portRef D (instanceRef RA10_RNO)) + (portRef C (instanceRef IS_RNO_0)) (portRef C0 (instanceRef nRWE_RNO_1)) (portRef A (instanceRef Ready_RNO)) - (portRef A (instanceRef RCKEEN_8_u_RNO)) + (portRef A (instanceRef RCKEEN_8_u_0_0)) (portRef A (instanceRef nRowColSel_RNO)) )) (net n8MEGEN (joined @@ -916,28 +953,35 @@ (net CO0 (joined (portRef Q (instanceRef S_0)) (portRef D (instanceRef IS_0_sqmuxa_0_o2_0)) - (portRef B (instanceRef nRCAS_RNO_0)) + (portRef C (instanceRef nRCAS_RNO_0)) (portRef B (instanceRef nRWE_RNO_0)) - (portRef B (instanceRef RCKEEN_8_u_1_0)) + (portRef C (instanceRef nRCS_RNO_1)) + (portRef A (instanceRef nRCS_RNO_2)) + (portRef A (instanceRef nRCS_RNO_0)) + (portRef A (instanceRef RCKEEN_8_u_0_1_a1_0)) (portRef A (instanceRef S_0_i_o2_1)) + (portRef A (instanceRef nRCS_9_u_i_a2)) (portRef A (instanceRef Ready_0_sqmuxa_0_a3_2)) - (portRef A (instanceRef S_RNO_0)) + (portRef B (instanceRef RCKEEN_8_u_0_a3_0_0)) (portRef A (instanceRef nRowColSel_0_0)) (portRef B (instanceRef nRWE_RNO_4)) (portRef B (instanceRef nRWE_RNO_3)) (portRef C (instanceRef nRowColSel_RNO)) - (portRef B (instanceRef nRCS_RNO_0)) )) (net (rename S_1 "S[1]") (joined (portRef Q (instanceRef S_1)) (portRef C (instanceRef IS_0_sqmuxa_0_o2_0)) - (portRef C (instanceRef nRCAS_RNO)) + (portRef C (instanceRef nRCAS_RNO_1)) + (portRef D (instanceRef nRCAS_RNO)) (portRef C (instanceRef nRWE_RNO_0)) - (portRef D (instanceRef RCKEEN_8_u_1_0)) - (portRef B (instanceRef RCKEEN_8_u_0_a2_1_s)) + (portRef B (instanceRef nRCS_RNO_4)) + (portRef C (instanceRef nRCS_RNO_0)) + (portRef D (instanceRef RCKEEN_8_u_0_1_1)) + (portRef B (instanceRef RCKEEN_8_u_0_1_a1_0)) (portRef B (instanceRef S_0_i_o2_1)) (portRef D (instanceRef Ready_0_sqmuxa_0_a3_2)) - (portRef B (instanceRef S_RNO_0)) + (portRef C (instanceRef RCKEEN_8_u_0_a3_0_0)) + (portRef C (instanceRef RCKEEN_8_u_0_a2_0_m1_0_a2)) (portRef D (instanceRef nRowColSel_0_0)) (portRef D (instanceRef un1_nRCAS_6_sqmuxa_i_0)) (portRef A (instanceRef nRWE_RNO_4)) @@ -948,20 +992,24 @@ (portRef Q (instanceRef RASr2)) (portRef A (instanceRef IS_0_sqmuxa_0_o2_0)) (portRef D (instanceRef nRWE_RNO_5)) + (portRef A (instanceRef nRCS_RNO_3)) + (portRef B (instanceRef nRCS_RNO_2)) (portRef C (instanceRef Ready_0_sqmuxa_0_a3_2)) (portRef B (instanceRef RCKE_2_0)) (portRef B (instanceRef nRRAS_5_u_i_0)) (portRef C (instanceRef nRCAS_0_sqmuxa_1_0_a3)) (portRef D (instanceRef RASr3)) + (portRef D (instanceRef S_0)) (portRef D (instanceRef nRWE_RNO_3)) - (portRef B (instanceRef RCKEEN_8_u_RNO)) - (portRef A (instanceRef RASr2_RNIAFR1)) + (portRef B (instanceRef RCKEEN_8_u_0_0)) + (portRef A (instanceRef S_RNO_1)) )) (net InitReady (joined (portRef Q (instanceRef InitReady)) (portRef A (instanceRef UFMCLK_RNO_0)) (portRef B (instanceRef IS_0_sqmuxa_0_o2_0)) (portRef B (instanceRef nUFMCS_s_0_N_5_i_N_2L1)) + (portRef A (instanceRef nRCS_RNO_4)) (portRef B (instanceRef LEDEN_5_i_m2)) (portRef B (instanceRef n8MEGEN_5_i_m2)) (portRef B (instanceRef UFMCLK_r_i_a2_2_2)) @@ -974,76 +1022,79 @@ (portRef B (instanceRef InitReady_RNO)) (portRef D (instanceRef nRWE_RNO_4)) (portRef D (instanceRef Ready_RNO)) - (portRef C (instanceRef RCKEEN_8_u_RNO)) + (portRef C (instanceRef RCKEEN_8_u_0_0)) )) (net FWEr (joined (portRef Q (instanceRef FWEr)) - (portRef C (instanceRef nRCAS_RNO_0)) (portRef A (instanceRef nRWE_RNO)) + (portRef B (instanceRef nRCS_9_u_i_a2)) (portRef C (instanceRef nRowColSel_0_0_a3_0)) )) (net CASr3 (joined (portRef Q (instanceRef CASr3)) - (portRef B (instanceRef nRCAS_RNO_1)) + (portRef B (instanceRef nRCAS_RNO_0)) (portRef B (instanceRef nRWE_RNO_2)) + (portRef B (instanceRef nRCS_RNO_1)) (portRef A (instanceRef nRowColSel_0_0_a3_0)) - (portRef C (instanceRef nRCS_RNO_0)) )) (net (rename IS_0 "IS[0]") (joined (portRef Q (instanceRef IS_0)) - (portRef A (instanceRef IS_RNO_0)) - (portRef D (instanceRef nRRAS_RNO)) + (portRef A (instanceRef nRRAS_RNO)) (portRef A (instanceRef nRWE_RNO_5)) + (portRef A (instanceRef nRCS_RNO_5)) (portRef A (instanceRef IS_n1_0_x2)) (portRef A (instanceRef Ready_0_sqmuxa_0_o2)) (portRef A (instanceRef IS_RNO_2)) - (portRef A (instanceRef nRRAS_5_u_i)) + (portRef A (instanceRef RA10_RNO)) + (portRef A (instanceRef IS_RNO_0)) (portRef D (instanceRef IS_RNO_3)) - (portRef A (instanceRef IS_i_0)) )) (net (rename IS_3 "IS[3]") (joined (portRef Q (instanceRef IS_3)) + (portRef A (instanceRef un1_nRCAS_6_sqmuxa_i_o2)) + (portRef D (instanceRef nRCS_RNO_5)) (portRef B (instanceRef Ready_0_sqmuxa_0_a3_2)) - (portRef C (instanceRef un1_nRCAS_6_sqmuxa_i_o2)) - (portRef C (instanceRef RA10_RNO)) + (portRef B (instanceRef RA10_RNO)) (portRef A (instanceRef IS_RNO_3)) )) (net (rename IS_1 "IS[1]") (joined (portRef Q (instanceRef IS_1)) + (portRef C (instanceRef un1_nRCAS_6_sqmuxa_i_o2)) (portRef B (instanceRef nRWE_RNO_5)) + (portRef B (instanceRef nRCS_RNO_5)) (portRef B (instanceRef IS_n1_0_x2)) - (portRef A (instanceRef un1_nRCAS_6_sqmuxa_i_o2)) + (portRef A (instanceRef RA10_2_sqmuxa_0_o2)) (portRef B (instanceRef Ready_0_sqmuxa_0_o2)) (portRef B (instanceRef IS_RNO_2)) - (portRef A (instanceRef RA10_RNO)) (portRef C (instanceRef IS_RNO_3)) )) (net (rename IS_2 "IS[2]") (joined (portRef Q (instanceRef IS_2)) - (portRef C (instanceRef nRWE_RNO_5)) (portRef B (instanceRef un1_nRCAS_6_sqmuxa_i_o2)) + (portRef C (instanceRef nRWE_RNO_5)) + (portRef C (instanceRef nRCS_RNO_5)) + (portRef B (instanceRef RA10_2_sqmuxa_0_o2)) (portRef C (instanceRef Ready_0_sqmuxa_0_o2)) (portRef C (instanceRef IS_RNO_2)) - (portRef B (instanceRef RA10_RNO)) (portRef B (instanceRef IS_RNO_3)) )) (net (rename FS_5 "FS[5]") (joined (portRef Q (instanceRef FS_5)) (portRef A1 (instanceRef FS_cry_0_4)) - (portRef D (instanceRef un1_FS_14_i_a2_0_1)) - (portRef D (instanceRef un1_FS_13_i_a2_1)) (portRef A (instanceRef UFMSDI_ens2_i_o2)) + (portRef A (instanceRef un1_FS_13_i_a2_1)) + (portRef A (instanceRef un1_FS_14_i_a2_0_1)) )) (net (rename FS_6 "FS[6]") (joined (portRef Q (instanceRef FS_6)) (portRef A0 (instanceRef FS_cry_0_6)) (portRef A (instanceRef UFMSDI_ens2_i_a2_4_2)) - (portRef B (instanceRef un1_FS_13_i_a2_6)) + (portRef D (instanceRef un1_FS_13_i_a2_9_4)) )) (net (rename FS_7 "FS[7]") (joined (portRef Q (instanceRef FS_7)) (portRef A1 (instanceRef FS_cry_0_6)) - (portRef C (instanceRef un1_FS_13_i_a2_6)) + (portRef B (instanceRef un1_FS_13_i_a2_9_5)) (portRef B (instanceRef UFMSDI_ens2_i_o2)) )) (net (rename FS_8 "FS[8]") (joined @@ -1055,67 +1106,65 @@ (net (rename FS_9 "FS[9]") (joined (portRef Q (instanceRef FS_9)) (portRef A1 (instanceRef FS_cry_0_8)) + (portRef C (instanceRef un1_FS_13_i_a2_9_5)) (portRef C (instanceRef UFMSDI_ens2_i_o2)) - (portRef B (instanceRef un1_FS_13_i_a2_8)) )) (net (rename FS_0 "FS[0]") (joined (portRef Q (instanceRef FS_0)) (portRef A0 (instanceRef FS_cry_0_0)) - (portRef A (instanceRef un1_FS_14_i_a2_0_1)) - (portRef A (instanceRef un1_FS_13_i_a2_1)) + (portRef A (instanceRef un1_FS_13_i_a2_9_4)) )) (net (rename FS_1 "FS[1]") (joined (portRef Q (instanceRef FS_1)) (portRef A1 (instanceRef FS_cry_0_0)) - (portRef A (instanceRef un1_FS_13_i_a2_6)) - (portRef A (instanceRef UFMCLK_r_i_m2)) + (portRef A (instanceRef un1_FS_13_i_a2_9_5)) + (portRef B (instanceRef UFMCLK_RNO_1)) )) (net (rename FS_2 "FS[2]") (joined (portRef Q (instanceRef FS_2)) (portRef A0 (instanceRef FS_cry_0_2)) - (portRef B (instanceRef un1_FS_14_i_a2_0_1)) - (portRef B (instanceRef un1_FS_13_i_a2_1)) + (portRef B (instanceRef un1_FS_13_i_a2_9_4)) )) (net (rename FS_3 "FS[3]") (joined (portRef Q (instanceRef FS_3)) (portRef A1 (instanceRef FS_cry_0_2)) - (portRef C (instanceRef un1_FS_14_i_a2_0_1)) - (portRef C (instanceRef un1_FS_13_i_a2_1)) + (portRef C (instanceRef un1_FS_13_i_a2_9_4)) )) (net (rename FS_10 "FS[10]") (joined (portRef Q (instanceRef FS_10)) (portRef A0 (instanceRef FS_cry_0_10)) (portRef C (instanceRef UFMSDI_ens2_i_a2_4_2)) - (portRef D (instanceRef un1_FS_13_i_a2_6)) + (portRef D (instanceRef un1_FS_13_i_a2_9_5)) (portRef A (instanceRef InitReady3_0_a2)) (portRef A (instanceRef nUFMCS15_0_a2)) )) (net (rename FS_11 "FS[11]") (joined (portRef Q (instanceRef FS_11)) (portRef A1 (instanceRef FS_cry_0_10)) + (portRef B (instanceRef un1_FS_14_i_o2)) (portRef A (instanceRef InitReady3_0_a2_3)) (portRef D (instanceRef UFMSDI_ens2_i_a2_4_2)) - (portRef C (instanceRef UFMCLK_r_i_m2)) (portRef B (instanceRef nUFMCS15_0_a2)) - (portRef C (instanceRef un1_FS_13_i_a2_8)) + (portRef C (instanceRef UFMCLK_RNO_1)) )) (net (rename FS_12 "FS[12]") (joined (portRef Q (instanceRef FS_12)) (portRef A0 (instanceRef FS_cry_0_12)) + (portRef A (instanceRef UFMSDI_ens2_i_o2_0_3)) (portRef A (instanceRef InitReady3_0_a2_5)) - (portRef A (instanceRef UFMSDI_ens2_i_o2_0)) )) (net (rename FS_13 "FS[13]") (joined (portRef Q (instanceRef FS_13)) (portRef A1 (instanceRef FS_cry_0_12)) - (portRef A (instanceRef UFMSDI_ens2_i_o2_0_3)) - (portRef B (instanceRef InitReady3_0_a2_5)) + (portRef B (instanceRef InitReady3_0_a2)) + (portRef A (instanceRef UFMSDI_ens2_i_o2_0)) + (portRef A (instanceRef UFMCLK_r_i_a2_2_2)) )) (net (rename FS_14 "FS[14]") (joined (portRef Q (instanceRef FS_14)) (portRef A0 (instanceRef FS_cry_0_14)) - (portRef B (instanceRef InitReady3_0_a2_3)) (portRef B (instanceRef UFMSDI_ens2_i_o2_0_3)) + (portRef B (instanceRef InitReady3_0_a2_5)) )) (net (rename FS_15 "FS[15]") (joined (portRef Q (instanceRef FS_15)) @@ -1126,15 +1175,14 @@ (net (rename FS_16 "FS[16]") (joined (portRef Q (instanceRef FS_16)) (portRef A0 (instanceRef FS_cry_0_16)) - (portRef A (instanceRef UFMCLK_r_i_a2_2_2)) + (portRef D (instanceRef InitReady3_0_a2_5)) (portRef B (instanceRef UFMSDI_ens2_i_o2_0)) - (portRef B (instanceRef InitReady3_0_a2)) )) (net (rename FS_17 "FS[17]") (joined (portRef Q (instanceRef FS_17)) (portRef A1 (instanceRef FS_cry_0_16)) + (portRef B (instanceRef InitReady3_0_a2_3)) (portRef D (instanceRef UFMSDI_ens2_i_o2_0_3)) - (portRef D (instanceRef InitReady3_0_a2_5)) )) (net PHI2r2 (joined (portRef Q (instanceRef PHI2r2)) @@ -1148,11 +1196,11 @@ )) (net CASr2 (joined (portRef Q (instanceRef CASr2)) - (portRef A (instanceRef nRCAS_RNO_1)) + (portRef A (instanceRef nRCAS_RNO_0)) (portRef A (instanceRef nRWE_RNO_2)) - (portRef A (instanceRef RCKEEN_8_u_1_0)) + (portRef A (instanceRef nRCS_RNO_1)) + (portRef A (instanceRef RCKEEN_8_u_0_a3_0_0)) (portRef D (instanceRef CASr3)) - (portRef D (instanceRef nRCS_RNO_0)) )) (net CASr (joined (portRef Q (instanceRef CASr)) @@ -1169,31 +1217,31 @@ )) (net (rename Bank_0 "Bank[0]") (joined (portRef Q (instanceRef Bank_0)) - (portRef A (instanceRef C1WR_0_a2_0)) + (portRef A (instanceRef un1_Bank_1_4)) )) (net (rename Bank_1 "Bank[1]") (joined (portRef Q (instanceRef Bank_1)) - (portRef B (instanceRef C1WR_0_a2_0)) + (portRef B (instanceRef un1_Bank_1_4)) )) (net (rename Bank_3 "Bank[3]") (joined (portRef Q (instanceRef Bank_3)) - (portRef A (instanceRef C1WR_0_a2_0_10)) + (portRef C (instanceRef un1_Bank_1_4)) )) (net (rename Bank_4 "Bank[4]") (joined (portRef Q (instanceRef Bank_4)) - (portRef B (instanceRef C1WR_0_a2_0_10)) + (portRef D (instanceRef un1_Bank_1_4)) )) (net (rename Bank_5 "Bank[5]") (joined (portRef Q (instanceRef Bank_5)) - (portRef B (instanceRef C1WR_0_a2_0_11)) + (portRef B (instanceRef un1_Bank_1_5)) )) (net (rename Bank_6 "Bank[6]") (joined (portRef Q (instanceRef Bank_6)) - (portRef C (instanceRef C1WR_0_a2_0_11)) + (portRef C (instanceRef un1_Bank_1_5)) )) (net (rename Bank_7 "Bank[7]") (joined (portRef Q (instanceRef Bank_7)) - (portRef D (instanceRef C1WR_0_a2_0_11)) + (portRef D (instanceRef un1_Bank_1_5)) )) (net (rename RowA_0 "RowA[0]") (joined (portRef Q (instanceRef RowA_0)) @@ -1269,17 +1317,17 @@ )) (net nRowColSel (joined (portRef Q (instanceRef nRowColSel)) - (portRef B (instanceRef RDQML)) (portRef B (instanceRef RDQMH)) - (portRef C (instanceRef un9_RA_9)) + (portRef B (instanceRef RDQML)) + (portRef C (instanceRef un9_RA_0)) + (portRef C (instanceRef un9_RA_1)) + (portRef C (instanceRef un9_RA_2)) (portRef C (instanceRef un9_RA_7)) + (portRef C (instanceRef un9_RA_9)) (portRef C (instanceRef un9_RA_6)) (portRef C (instanceRef un9_RA_5)) (portRef C (instanceRef un9_RA_4)) (portRef C (instanceRef un9_RA_3)) - (portRef C (instanceRef un9_RA_2)) - (portRef C (instanceRef un9_RA_1)) - (portRef C (instanceRef un9_RA_0)) (portRef C (instanceRef un9_RA_8)) )) (net RASr3 (joined @@ -1289,13 +1337,13 @@ (net LEDEN (joined (portRef Q (instanceRef LEDEN)) (portRef B (instanceRef LED_pad_RNO)) - (portRef B (instanceRef XOR8MEG_3_u_0_a3_3)) - (portRef A (instanceRef CmdLEDEN_RNO)) + (portRef B (instanceRef CmdLEDEN_RNO)) + (portRef B (instanceRef XOR8MEG_3_u_0_a3_0_2)) )) (net CmdLEDEN (joined (portRef Q (instanceRef CmdLEDEN)) - (portRef B (instanceRef CmdLEDEN_4_u_i_a2)) (portRef A (instanceRef LEDEN_5_i_m2)) + (portRef A (instanceRef CmdLEDEN_4_u_i_0)) )) (net Cmdn8MEGEN (joined (portRef Q (instanceRef Cmdn8MEGEN)) @@ -1316,8 +1364,8 @@ (net (rename FS_4 "FS[4]") (joined (portRef Q (instanceRef FS_4)) (portRef A0 (instanceRef FS_cry_0_4)) - (portRef B (instanceRef UFMCLK_r_i_m2)) - (portRef A (instanceRef un1_FS_13_i_a2_8)) + (portRef A (instanceRef un1_FS_14_i_o2)) + (portRef D (instanceRef UFMCLK_RNO_1)) )) (net InitReady3 (joined (portRef Z (instanceRef InitReady3_0_a2)) @@ -1334,7 +1382,7 @@ (net XOR8MEG (joined (portRef Q (instanceRef XOR8MEG)) (portRef B (instanceRef RA11_2)) - (portRef A (instanceRef XOR8MEG_3_u_0_a3_0)) + (portRef B (instanceRef XOR8MEG_3_u_0_a3)) )) (net nRRAS_0_sqmuxa (joined (portRef Z (instanceRef nRowColSel_RNO)) @@ -1356,33 +1404,32 @@ )) (net nRCAS_0_sqmuxa_1 (joined (portRef Z (instanceRef nRCAS_0_sqmuxa_1_0_a3)) - (portRef B (instanceRef nRCAS_RNO)) + (portRef C (instanceRef nRCAS_RNO)) (portRef C (instanceRef nRWE_RNO)) )) (net XOR8MEG18 (joined - (portRef Z (instanceRef XOR8MEG18_0_a2)) - (portRef A (instanceRef CmdUFMCLK_1_sqmuxa_0_a2)) + (portRef Z (instanceRef XOR8MEG18)) (portRef A (instanceRef CmdSubmitted_1_sqmuxa_0_a2)) + (portRef A (instanceRef CmdUFMCLK_1_sqmuxa_0_a2)) (portRef SP (instanceRef CmdLEDEN)) (portRef SP (instanceRef Cmdn8MEGEN)) (portRef SP (instanceRef XOR8MEG)) )) (net CmdEnable (joined (portRef Q (instanceRef CmdEnable)) - (portRef A (instanceRef XOR8MEG18_0_a2)) - (portRef B (instanceRef CmdEnable_s_am)) - (portRef A (instanceRef CmdEnable_s_bm)) + (portRef B (instanceRef XOR8MEG18)) + (portRef A (instanceRef CmdEnable_s)) )) (net CmdEnable16 (joined - (portRef Z (instanceRef CmdEnable16_0_a2)) + (portRef Z (instanceRef CmdEnable16_0_a3)) (portRef D (instanceRef ADSubmitted_r)) - (portRef C0 (instanceRef CmdEnable_s)) + (portRef B (instanceRef CmdEnable_s_RNO)) (portRef A (instanceRef C1Submitted_RNO)) )) (net CmdEnable17 (joined - (portRef Z (instanceRef CmdEnable17_0_a2)) + (portRef Z (instanceRef CmdEnable17_0_a3)) (portRef C (instanceRef ADSubmitted_r)) - (portRef A (instanceRef CmdEnable_s_am)) + (portRef B (instanceRef CmdEnable_s)) )) (net CmdSubmitted_1_sqmuxa (joined (portRef Z (instanceRef CmdSubmitted_1_sqmuxa_0_a2)) @@ -1404,8 +1451,12 @@ )) (net ADSubmitted (joined (portRef Q (instanceRef ADSubmitted)) + (portRef A (instanceRef CmdEnable_0_sqmuxa)) (portRef A (instanceRef ADSubmitted_r)) - (portRef B (instanceRef CmdEnable_s_bm)) + )) + (net CmdEnable_0_sqmuxa (joined + (portRef Z (instanceRef CmdEnable_0_sqmuxa)) + (portRef D (instanceRef CmdEnable_s)) )) (net C1Submitted_RNO (joined (portRef Z (instanceRef C1Submitted_RNO)) @@ -1428,182 +1479,197 @@ (portRef D (instanceRef nRowColSel)) )) (net RCKEEN_8 (joined - (portRef Z (instanceRef RCKEEN_8_u)) + (portRef Z (instanceRef RCKEEN_8_u_0)) (portRef D (instanceRef RCKEEN)) )) - (net N_31 (joined + (net N_24 (joined (portRef Z (instanceRef un1_FS_14_i_0)) (portRef SP (instanceRef n8MEGEN)) )) - (net N_33 (joined + (net N_26 (joined (portRef Z (instanceRef un1_FS_13_i_0)) (portRef SP (instanceRef LEDEN)) )) - (net N_24 (joined - (portRef Z (instanceRef nRRAS_5_u_i)) - (portRef B (instanceRef nRCS_RNO)) - )) - (net N_41 (joined + (net un1_nRCAS_6_sqmuxa_i_0 (joined (portRef Z (instanceRef un1_nRCAS_6_sqmuxa_i_0)) - (portRef A (instanceRef nRCAS_RNO)) + (portRef B (instanceRef nRCAS_RNO_1)) )) (net (rename S_0_i_o2_1 "S_0_i_o2[1]") (joined (portRef Z (instanceRef S_0_i_o2_1)) (portRef A (instanceRef nRRAS_5_u_i_0)) (portRef B (instanceRef nRCAS_0_sqmuxa_1_0_a3)) (portRef D (instanceRef S_1)) - (portRef D (instanceRef RCKEEN_8_u_RNO)) + (portRef D (instanceRef RCKEEN_8_u_0_0)) )) - (net N_159 (joined - (portRef Z (instanceRef IS_0_sqmuxa_0_o2)) - (portRef D (instanceRef RA10_RNO)) + (net N_45 (joined + (portRef Z (instanceRef Cmdn8MEGEN_4_u_i_o2)) + (portRef D (instanceRef CmdLEDEN_4_u_i_0)) + (portRef D (instanceRef Cmdn8MEGEN_4_u_i_0)) )) - (net N_165 (joined + (net N_36 (joined + (portRef Z (instanceRef Cmdn8MEGEN_4_u_i_o2_0)) + (portRef B (instanceRef CmdSubmitted_1_sqmuxa_0_a2)) + (portRef B (instanceRef CmdUFMCLK_1_sqmuxa_0_a2)) + (portRef C (instanceRef Cmdn8MEGEN_4_u_i_o2)) + (portRef C (instanceRef Cmdn8MEGEN_4_u_i_a2_2)) + )) + (net N_154 (joined + (portRef Z (instanceRef un1_nRCAS_6_sqmuxa_i_o2)) + (portRef C (instanceRef nRRAS_RNO)) + (portRef B (instanceRef un1_nRCAS_6_sqmuxa_i_0)) + )) + (net N_148 (joined + (portRef Z (instanceRef IS_0_sqmuxa_0_o2_0)) + (portRef B (instanceRef nRRAS_RNO)) + (portRef A (instanceRef IS_0_sqmuxa_0_o2_0_RNIS63D)) + (portRef A (instanceRef un1_nRCAS_6_sqmuxa_i_0)) + (portRef C (instanceRef RA10_RNO)) + (portRef B (instanceRef IS_RNO_0)) + )) + (net N_151 (joined + (portRef Z (instanceRef RA10_2_sqmuxa_0_o2)) + (portRef D (instanceRef RA10)) + )) + (net N_160 (joined (portRef Z (instanceRef Ready_0_sqmuxa_0_o2)) (portRef B (instanceRef Ready_0_sqmuxa_0_a3)) (portRef C (instanceRef Ready_RNO)) )) - (net N_95_5 (joined - (portRef Z (instanceRef InitReady3_0_a2_5)) - (portRef D (instanceRef UFMCLK_r_i_a2_2_2)) - (portRef D (instanceRef InitReady3_0_a2)) - )) - (net N_95_3 (joined - (portRef Z (instanceRef InitReady3_0_a2_3)) - (portRef C (instanceRef UFMCLK_r_i_a2_2_2)) - (portRef C (instanceRef InitReady3_0_a2)) - )) - (net N_51 (joined - (portRef Z (instanceRef UFMSDI_ens2_i_o2_0)) - (portRef D (instanceRef UFMCLK_r_i_m2)) - (portRef D (instanceRef nUFMCS15_0_a2)) - (portRef C (instanceRef UFMSDI_en_ss0_0_a2_0)) - (portRef B (instanceRef UFMSDI_ens2_i_a0)) - )) - (net N_126 (joined - (portRef Z (instanceRef UFMSDI_ens2_i_o2)) - (portRef C (instanceRef UFMSDI_ens2_i_a0)) - )) - (net N_151 (joined - (portRef Z (instanceRef UFMSDI_en_ss0_0_a2_0)) - (portRef C (instanceRef UFMSDI_RNO_0)) - (portRef D (instanceRef un1_FS_13_i_a2_8)) - )) - (net N_137_8 (joined - (portRef Z (instanceRef un1_FS_13_i_a2_8)) - (portRef C (instanceRef un1_FS_13_i_0)) - (portRef C (instanceRef un1_FS_14_i_0)) - )) - (net N_129 (joined - (portRef Z (instanceRef UFMCLK_r_i_m2)) - (portRef D (instanceRef UFMCLK_RNO_0)) - )) - (net N_155 (joined - (portRef Z (instanceRef IS_0_sqmuxa_0_o2_0)) - (portRef C (instanceRef IS_RNO_0)) - (portRef B (instanceRef IS_0_sqmuxa_0_o2_0_RNIS63D)) - (portRef C (instanceRef nRRAS_RNO)) - (portRef A (instanceRef IS_0_sqmuxa_0_o2)) - (portRef A (instanceRef un1_nRCAS_6_sqmuxa_i_0)) - (portRef B (instanceRef nRRAS_5_u_i)) - )) - (net N_56_i (joined - (portRef Z (instanceRef IS_n1_0_x2)) - (portRef D (instanceRef IS_1)) - )) - (net N_160 (joined - (portRef Z (instanceRef un1_nRCAS_6_sqmuxa_i_o2)) - (portRef B (instanceRef nRRAS_RNO)) - (portRef B (instanceRef un1_nRCAS_6_sqmuxa_i_0)) - (portRef C (instanceRef nRRAS_5_u_i)) - )) - (net N_136 (joined - (portRef Z (instanceRef un1_FS_14_i_a2)) - (portRef A (instanceRef un1_FS_13_i_0)) - (portRef A (instanceRef un1_FS_14_i_0)) - )) - (net N_69 (joined - (portRef Z (instanceRef n8MEGEN_5_i_m2)) - (portRef D (instanceRef n8MEGEN)) - )) - (net N_70 (joined - (portRef Z (instanceRef LEDEN_5_i_m2)) - (portRef D (instanceRef LEDEN)) - )) - (net N_137_6 (joined - (portRef Z (instanceRef un1_FS_13_i_a2_6)) - (portRef B (instanceRef un1_FS_13_i_0)) - (portRef B (instanceRef un1_FS_14_i_0)) - )) - (net XOR8MEG_3 (joined - (portRef Z (instanceRef XOR8MEG_3_u_0_a3_3)) - (portRef D (instanceRef XOR8MEG)) - )) - (net CmdEnable16_1 (joined - (portRef Z (instanceRef CmdEnable16_0_a2_1)) - (portRef A (instanceRef CmdEnable16_0_a2_5)) - )) - (net N_43 (joined - (portRef Z (instanceRef CmdEnable17_0_o2)) - (portRef D (instanceRef CmdEnable17_0_a2_4)) - (portRef C (instanceRef Cmdn8MEGEN_4_u_i_0)) - )) - (net N_147 (joined - (portRef Z (instanceRef C1WR_0_a2_0)) - (portRef A (instanceRef un1_CMDWR)) - (portRef C (instanceRef CmdEnable16_0_a2)) - (portRef B (instanceRef C1WR_0_a2)) - (portRef D (instanceRef XOR8MEG18_0_a2)) - (portRef D (instanceRef CmdEnable17_0_a2)) - (portRef C (instanceRef C1Submitted_RNO)) - )) - (net CmdEnable16_4 (joined - (portRef Z (instanceRef CmdEnable16_0_a2_4)) - (portRef A (instanceRef CmdEnable16_0_a2_4_0)) - (portRef A (instanceRef Cmdn8MEGEN_4_u_i_0)) - )) - (net un1_Din_4 (joined - (portRef Z (instanceRef un1_Din_4)) - (portRef B (instanceRef XOR8MEG_3_u_0_a3_0)) - (portRef D (instanceRef XOR8MEG_3_u_0_a3_2)) - )) - (net N_171 (joined - (portRef Z (instanceRef XOR8MEG_3_u_0_a3_0)) - (portRef C (instanceRef XOR8MEG_3_u_0_a3_3)) - )) - (net N_128 (joined - (portRef Z (instanceRef Cmdn8MEGEN_4_u_i_o2_0)) - (portRef B (instanceRef CmdUFMCLK_1_sqmuxa_0_a2)) - (portRef A (instanceRef CmdLEDEN_4_u_i_a2)) - (portRef B (instanceRef CmdSubmitted_1_sqmuxa_0_a2)) - (portRef C (instanceRef CmdLEDEN_4_u_i_a2_0)) - (portRef C (instanceRef Cmdn8MEGEN_4_u_i_a2_2)) - (portRef D (instanceRef Cmdn8MEGEN_4_u_i_0)) - )) - (net N_152 (joined + (net N_95 (joined (portRef Z (instanceRef Cmdn8MEGEN_4_u_i_a2_2)) - (portRef D (instanceRef CmdLEDEN_RNO)) + (portRef C (instanceRef CmdLEDEN_RNO)) (portRef B (instanceRef Cmdn8MEGEN_RNO)) )) - (net N_132 (joined - (portRef Z (instanceRef CmdLEDEN_4_u_i_a2)) - (portRef B (instanceRef CmdLEDEN_RNO)) + (net N_184 (joined + (portRef Z (instanceRef RCKEEN_8_u_0_a2_0_m1_0_a2)) + (portRef B (instanceRef nRCS_RNO)) )) - (net N_133 (joined - (portRef Z (instanceRef CmdLEDEN_4_u_i_a2_0)) - (portRef C (instanceRef CmdLEDEN_RNO)) - )) - (net un1_CMDWR (joined - (portRef Z (instanceRef un1_CMDWR)) - (portRef C (instanceRef CmdEnable_s_am)) - )) - (net N_179 (joined + (net N_112 (joined (portRef Z (instanceRef nRowColSel_0_0_a3_0)) (portRef B (instanceRef nRowColSel_0_0)) )) - (net XOR8MEG_3_u_0_a3_2 (joined - (portRef Z (instanceRef XOR8MEG_3_u_0_a3_2)) - (portRef D (instanceRef XOR8MEG_3_u_0_a3_3)) + (net N_125 (joined + (portRef Z (instanceRef nRCS_9_u_i_a2)) + (portRef A (instanceRef nRCS_RNO)) + )) + (net N_69_i (joined + (portRef Z (instanceRef IS_n1_0_x2)) + (portRef D (instanceRef IS_1)) + )) + (net N_121 (joined + (portRef Z (instanceRef un1_CmdEnable20_0_a3)) + (portRef C (instanceRef CmdEnable_s_RNO)) + )) + (net CMDWR (joined + (portRef Z (instanceRef CMDWR)) + (portRef A (instanceRef XOR8MEG18)) + (portRef C (instanceRef un1_CmdEnable20_0_a3)) + )) + (net C1WR_7 (joined + (portRef Z (instanceRef C1WR_7)) + (portRef A (instanceRef CMDWR)) + (portRef B (instanceRef C1WR)) + )) + (net C1WR (joined + (portRef Z (instanceRef C1WR)) + (portRef D (instanceRef CmdEnable_0_sqmuxa)) + (portRef A (instanceRef CmdEnable16_0_a3)) + (portRef B (instanceRef un1_CmdEnable20_0_a3)) + (portRef B (instanceRef ADSubmitted_r_RNO)) + (portRef C (instanceRef C1Submitted_RNO)) + )) + (net ADWR_8 (joined + (portRef Z (instanceRef ADWR_8)) + (portRef A (instanceRef un1_CmdEnable20_0_a3_0_2)) + (portRef A (instanceRef ADWR)) + )) + (net ADWR (joined + (portRef Z (instanceRef ADWR)) + (portRef A (instanceRef CmdEnable17_0_a3)) + (portRef A (instanceRef un1_CmdEnable20_0_a3)) + (portRef A (instanceRef ADSubmitted_r_RNO)) + (portRef D (instanceRef C1Submitted_RNO)) + )) + (net N_166 (joined + (portRef Z (instanceRef XOR8MEG_3_u_0_a3)) + (portRef C (instanceRef XOR8MEG_3_u_0_a3_0_2)) + )) + (net N_163 (joined + (portRef Z (instanceRef XOR8MEG_3_u_0_o2_0)) + (portRef A (instanceRef XOR8MEG_3_u_0_a3_0_1)) + (portRef A (instanceRef XOR8MEG_3_u_0_a3)) + )) + (net N_180 (joined + (portRef Z (instanceRef CmdEnable17_0_a2)) + (portRef D (instanceRef un1_CmdEnable20_0_a3_0_2)) + (portRef D (instanceRef CmdEnable17_0_a3)) + )) + (net XOR8MEG_3 (joined + (portRef Z (instanceRef XOR8MEG_3_u_0_a3_0_2)) + (portRef D (instanceRef XOR8MEG)) + )) + (net N_156 (joined + (portRef Z (instanceRef CmdEnable17_0_o2)) + (portRef C (instanceRef un1_CmdEnable20_0_a3_0_2)) + (portRef C (instanceRef CmdEnable17_0_a3)) + )) + (net N_122_5 (joined + (portRef Z (instanceRef CmdEnable17_0_a3_4)) + (portRef B (instanceRef un1_CmdEnable20_0_a3_0_2)) + (portRef B (instanceRef CmdEnable17_0_a3)) + )) + (net N_133_5 (joined + (portRef Z (instanceRef InitReady3_0_a2_5)) + (portRef D (instanceRef InitReady3_0_a2)) + (portRef D (instanceRef UFMCLK_r_i_a2_2_2)) + )) + (net N_133_3 (joined + (portRef Z (instanceRef InitReady3_0_a2_3)) + (portRef C (instanceRef InitReady3_0_a2)) + (portRef C (instanceRef UFMCLK_r_i_a2_2_2)) + )) + (net N_128 (joined + (portRef Z (instanceRef UFMSDI_ens2_i_o2_0)) + (portRef D (instanceRef nUFMCS15_0_a2)) + (portRef C (instanceRef UFMSDI_en_ss0_0_a2_0)) + (portRef C (instanceRef UFMSDI_ens2_i_a0)) + (portRef A (instanceRef UFMCLK_RNO_1)) + )) + (net N_34 (joined + (portRef Z (instanceRef UFMSDI_ens2_i_o2)) + (portRef B (instanceRef UFMSDI_ens2_i_a0)) + )) + (net N_94 (joined + (portRef Z (instanceRef UFMSDI_en_ss0_0_a2_0)) + (portRef C (instanceRef UFMSDI_RNO_0)) + (portRef A (instanceRef un1_FS_13_i_0)) + (portRef A (instanceRef un1_FS_14_i_0)) + )) + (net N_43 (joined + (portRef Z (instanceRef un1_FS_14_i_o2)) + (portRef B (instanceRef un1_FS_13_i_a2_1)) + (portRef B (instanceRef un1_FS_14_i_a2_0_1)) + )) + (net N_129 (joined + (portRef Z (instanceRef UFMCLK_RNO_1)) + (portRef D (instanceRef UFMCLK_RNO_0)) + )) + (net N_134 (joined + (portRef Z (instanceRef un1_FS_14_i_a2)) + (portRef B (instanceRef un1_FS_13_i_0)) + (portRef B (instanceRef un1_FS_14_i_0)) + )) + (net N_48 (joined + (portRef Z (instanceRef n8MEGEN_5_i_m2)) + (portRef D (instanceRef n8MEGEN)) + )) + (net N_49 (joined + (portRef Z (instanceRef LEDEN_5_i_m2)) + (portRef D (instanceRef LEDEN)) + )) + (net XOR8MEG_3_u_0_a3_0_1 (joined + (portRef Z (instanceRef XOR8MEG_3_u_0_a3_0_1)) + (portRef D (instanceRef XOR8MEG_3_u_0_a3_0_2)) )) (net UFMCLK_r_i_a2_2_2 (joined (portRef Z (instanceRef UFMCLK_r_i_a2_2_2)) @@ -1618,13 +1684,20 @@ (portRef Z (instanceRef UFMSDI_ens2_i_a0)) (portRef B (instanceRef UFMSDI_RNO_0)) )) - (net RCKEEN_8_u_0_0 (joined - (portRef Z (instanceRef RCKEEN_8_u_RNO)) - (portRef B (instanceRef RCKEEN_8_u)) + (net ADWR_8_2 (joined + (portRef Z (instanceRef ADWR_8_2)) + (portRef A (instanceRef ADWR_8)) + (portRef A (instanceRef C1WR_7)) )) - (net RCKEEN_8_u_0_a2_1_out (joined - (portRef Z (instanceRef RCKEEN_8_u_0_a2_1_s)) - (portRef D (instanceRef nRCS_RNO)) + (net CmdLEDEN_4_u_i_a2_0_0 (joined + (portRef Z (instanceRef CmdLEDEN_4_u_i_a2_0_0)) + (portRef B (instanceRef CmdLEDEN_4_u_i_0)) + (portRef A (instanceRef Cmdn8MEGEN_4_u_i_0)) + )) + (net RCKEEN_8_u_0_1_a1_0 (joined + (portRef Z (instanceRef RCKEEN_8_u_0_1_a1_0)) + (portRef B (instanceRef RCKEEN_8_u_0_1_1)) + (portRef CD (instanceRef S_0)) )) (net nCRAS_c_i (joined (portRef Z (instanceRef nCRAS_pad_RNIBPVB)) @@ -1645,12 +1718,6 @@ (portRef CK (instanceRef RowA_1)) (portRef CK (instanceRef RowA_0)) )) - (net N_159_i (joined - (portRef Z (instanceRef IS_0_sqmuxa_0_o2_0_RNIS63D)) - (portRef SP (instanceRef IS_3)) - (portRef SP (instanceRef IS_2)) - (portRef SP (instanceRef IS_1)) - )) (net RD_1_i (joined (portRef Z (instanceRef nCCAS_pad_RNI01SJ)) (portRef T (instanceRef RD_pad_0)) @@ -1662,15 +1729,21 @@ (portRef T (instanceRef RD_pad_6)) (portRef T (instanceRef RD_pad_7)) )) - (net N_28_i (joined + (net N_153_i (joined + (portRef Z (instanceRef IS_0_sqmuxa_0_o2_0_RNIS63D)) + (portRef SP (instanceRef IS_3)) + (portRef SP (instanceRef IS_2)) + (portRef SP (instanceRef IS_1)) + )) + (net N_143_i (joined (portRef Z (instanceRef nRCS_RNO)) (portRef D (instanceRef nRCS)) )) - (net N_37_i (joined + (net N_46_i (joined (portRef Z (instanceRef nRCAS_RNO)) (portRef D (instanceRef nRCAS)) )) - (net N_24_i (joined + (net N_142_i (joined (portRef Z (instanceRef nRRAS_RNO)) (portRef D (instanceRef nRRAS)) )) @@ -1678,40 +1751,44 @@ (portRef Z (instanceRef nUFMCS_s_0_N_5_i)) (portRef D (instanceRef nUFMCS)) )) - (net N_39_i (joined + (net N_144_i (joined (portRef Z (instanceRef nRWE_RNO)) (portRef D (instanceRef nRWE)) )) - (net N_64_i_i (joined + (net N_77_i_i (joined (portRef Z (instanceRef IS_RNO_0)) (portRef D (instanceRef IS_0)) )) - (net N_61_i_i (joined + (net N_75_i_i (joined (portRef Z (instanceRef IS_RNO_3)) (portRef D (instanceRef IS_3)) )) - (net N_60_i_i (joined + (net N_74_i_i (joined (portRef Z (instanceRef IS_RNO_2)) (portRef D (instanceRef IS_2)) )) - (net N_177_i (joined - (portRef Z (instanceRef S_RNO_0)) - (portRef D (instanceRef S_0)) - )) - (net N_21_i (joined + (net N_14_i (joined (portRef Z (instanceRef CmdLEDEN_RNO)) (portRef D (instanceRef CmdLEDEN)) )) - (net N_19_i (joined + (net N_12_i (joined (portRef Z (instanceRef Cmdn8MEGEN_RNO)) (portRef D (instanceRef Cmdn8MEGEN)) )) - (net N_139_i (joined + (net un1_CmdEnable20_i (joined + (portRef Z (instanceRef CmdEnable_s_RNO)) + (portRef C (instanceRef CmdEnable_s)) + )) + (net N_137_i (joined (portRef Z (instanceRef PHI2r3_RNITCN41)) (portRef A (instanceRef nUFMCS_s_0_N_5_i)) (portRef A (instanceRef UFMCLK_RNO)) (portRef A (instanceRef UFMSDI_RNO)) )) + (net N_183_i (joined + (portRef Z (instanceRef ADSubmitted_r_RNO)) + (portRef B (instanceRef ADSubmitted_r)) + )) (net (rename FS_cry_0 "FS_cry[0]") (joined (portRef COUT0 (instanceRef FS_cry_0_0)) )) @@ -1847,29 +1924,49 @@ (portRef Z (instanceRef RA10_RNO)) (portRef PD (instanceRef RA10)) )) + (net ADWR_8_4 (joined + (portRef Z (instanceRef ADWR_8_4)) + (portRef B (instanceRef ADWR_8)) + )) (net Cmdn8MEGEN_4_u_i_0 (joined (portRef Z (instanceRef Cmdn8MEGEN_4_u_i_0)) (portRef A (instanceRef Cmdn8MEGEN_RNO)) )) + (net CmdLEDEN_4_u_i_0 (joined + (portRef Z (instanceRef CmdLEDEN_4_u_i_0)) + (portRef A (instanceRef CmdLEDEN_RNO)) + )) + (net RCKEEN_8_u_0_a3_0_0 (joined + (portRef Z (instanceRef RCKEEN_8_u_0_a3_0_0)) + (portRef C (instanceRef RCKEEN_8_u_0_1_1)) + )) + (net un1_Bank_1_4 (joined + (portRef Z (instanceRef un1_Bank_1_4)) + (portRef C (instanceRef C1WR_7)) + (portRef C (instanceRef ADWR)) + )) + (net un1_Bank_1_5 (joined + (portRef Z (instanceRef un1_Bank_1_5)) + (portRef D (instanceRef C1WR_7)) + (portRef D (instanceRef ADWR)) + )) + (net un1_CmdEnable20_0_a3_0_2 (joined + (portRef Z (instanceRef un1_CmdEnable20_0_a3_0_2)) + (portRef D (instanceRef CmdEnable_s_RNO)) + )) (net UFMSDI_ens2_i_o2_0_3 (joined (portRef Z (instanceRef UFMSDI_ens2_i_o2_0_3)) (portRef C (instanceRef UFMSDI_ens2_i_o2_0)) )) - (net C1WR_0_a2_0_3 (joined - (portRef Z (instanceRef C1WR_0_a2_0_3)) - (portRef C (instanceRef C1WR_0_a2_0_10)) + (net un1_FS_13_i_a2_9_4 (joined + (portRef Z (instanceRef un1_FS_13_i_a2_9_4)) + (portRef C (instanceRef un1_FS_13_i_a2_1)) + (portRef C (instanceRef un1_FS_14_i_a2_0_1)) )) - (net C1WR_0_a2_0_4 (joined - (portRef Z (instanceRef C1WR_0_a2_0_4)) - (portRef D (instanceRef C1WR_0_a2_0_10)) - )) - (net C1WR_0_a2_0_10 (joined - (portRef Z (instanceRef C1WR_0_a2_0_10)) - (portRef C (instanceRef C1WR_0_a2_0)) - )) - (net C1WR_0_a2_0_11 (joined - (portRef Z (instanceRef C1WR_0_a2_0_11)) - (portRef D (instanceRef C1WR_0_a2_0)) + (net un1_FS_13_i_a2_9_5 (joined + (portRef Z (instanceRef un1_FS_13_i_a2_9_5)) + (portRef D (instanceRef un1_FS_13_i_a2_1)) + (portRef D (instanceRef un1_FS_14_i_a2_0_1)) )) (net Ready_0_sqmuxa_0_a3_2 (joined (portRef Z (instanceRef Ready_0_sqmuxa_0_a3_2)) @@ -1880,43 +1977,68 @@ (portRef Z (instanceRef UFMSDI_ens2_i_a2_4_2)) (portRef D (instanceRef UFMSDI_ens2_i_a0)) )) - (net CmdEnable16_0_a2_4 (joined - (portRef Z (instanceRef CmdEnable16_0_a2_4_0)) - (portRef A (instanceRef CmdEnable16_0_a2)) + (net RCKEEN_8_u_0_0 (joined + (portRef Z (instanceRef RCKEEN_8_u_0_0)) + (portRef B (instanceRef RCKEEN_8_u_0)) )) - (net CmdEnable16_0_a2_5 (joined - (portRef Z (instanceRef CmdEnable16_0_a2_5)) - (portRef B (instanceRef CmdEnable16_0_a2)) + (net C1WR_2_0 (joined + (portRef Z (instanceRef C1WR_2_0)) + (portRef A (instanceRef C1WR)) + )) + (net CMDWR_2 (joined + (portRef Z (instanceRef CMDWR_2)) + (portRef B (instanceRef CMDWR)) )) (net nRRAS_5_u_i_0 (joined (portRef Z (instanceRef nRRAS_5_u_i_0)) - (portRef A (instanceRef nRRAS_RNO)) - (portRef D (instanceRef nRRAS_5_u_i)) - )) - (net CmdEnable17_0_a2_3 (joined - (portRef Z (instanceRef CmdEnable17_0_a2_3)) - (portRef A (instanceRef CmdEnable17_0_a2)) - )) - (net CmdEnable17_0_a2_4 (joined - (portRef Z (instanceRef CmdEnable17_0_a2_4)) - (portRef B (instanceRef CmdEnable17_0_a2)) - )) - (net un1_FS_13_i_a2_1 (joined - (portRef Z (instanceRef un1_FS_13_i_a2_1)) - (portRef D (instanceRef un1_FS_13_i_0)) + (portRef D (instanceRef nRRAS_RNO)) )) (net un1_FS_14_i_a2_0_1 (joined (portRef Z (instanceRef un1_FS_14_i_a2_0_1)) - (portRef D (instanceRef un1_FS_14_i_0)) + (portRef C (instanceRef un1_FS_14_i_0)) + )) + (net un1_FS_13_i_a2_1 (joined + (portRef Z (instanceRef un1_FS_13_i_a2_1)) + (portRef C (instanceRef un1_FS_13_i_0)) + )) + (net CmdEnable16_0_a3_4 (joined + (portRef Z (instanceRef CmdEnable16_0_a3_4)) + (portRef C (instanceRef CmdEnable_0_sqmuxa)) + (portRef B (instanceRef CmdEnable16_0_a3)) + )) + (net CmdEnable16_0_a3_5 (joined + (portRef Z (instanceRef CmdEnable16_0_a3_5)) + (portRef B (instanceRef CmdEnable_0_sqmuxa)) + (portRef C (instanceRef CmdEnable16_0_a3)) )) (net (rename FS_cry_0_COUT1_16 "FS_cry_0_COUT1[16]") (joined (portRef COUT1 (instanceRef FS_cry_0_16)) )) - (net RCKEEN_8_u_1 (joined - (portRef Z (instanceRef RCKEEN_8_u_1_0)) - (portRef C (instanceRef RCKEEN_8_u)) + (net RCKEEN_8_u_0_1_1 (joined + (portRef Z (instanceRef RCKEEN_8_u_0_1_1)) + (portRef C (instanceRef RCKEEN_8_u_0)) )) - (net N_28_i_1 (joined + (net g3 (joined + (portRef Z (instanceRef nRCS_RNO_5)) + (portRef D (instanceRef nRCS_RNO_2)) + )) + (net N_9 (joined + (portRef Z (instanceRef nRCS_RNO_2)) + (portRef B (instanceRef nRCS_RNO_0)) + )) + (net g0_i_a5_1 (joined + (portRef Z (instanceRef nRCS_RNO_3)) + (portRef D (instanceRef nRCS_RNO_0)) + )) + (net g0_i_a5_1_2 (joined + (portRef Z (instanceRef nRCS_RNO_1)) + (portRef D (instanceRef nRCS_RNO)) + )) + (net g0_i_a5_2_1 (joined + (portRef Z (instanceRef nRCS_RNO_4)) + (portRef C (instanceRef nRCS_RNO_2)) + )) + (net g0_i_0 (joined (portRef Z (instanceRef nRCS_RNO_0)) (portRef C (instanceRef nRCS_RNO)) )) @@ -1936,29 +2058,31 @@ (portRef Z (instanceRef nRWE_RNO_0)) (portRef B (instanceRef nRWE_RNO)) )) - (net g0_1 (joined - (portRef Z (instanceRef nRCAS_RNO_0)) - (portRef D (instanceRef nRCAS_RNO)) - )) - (net g4_0_0_0 (joined - (portRef Z (instanceRef nRCAS_RNO_1)) - (portRef D (instanceRef nRCAS_RNO_0)) - )) (net CBR_fast (joined (portRef Q (instanceRef CBR_fast)) - (portRef A (instanceRef nRCAS_RNO_0)) + (portRef A (instanceRef nRWE_RNO_0)) + (portRef A (instanceRef RCKEEN_8_u_0_a2_0_m1_0_a2)) (portRef A (instanceRef nRCAS_0_sqmuxa_1_0_a3)) )) (net FWEr_fast (joined (portRef Q (instanceRef FWEr_fast)) - (portRef C (instanceRef RCKEEN_8_u_1_0)) - (portRef A (instanceRef nRCS_RNO_0)) + (portRef D (instanceRef nRCAS_RNO_0)) + (portRef D (instanceRef nRCS_RNO_1)) + (portRef A (instanceRef RCKEEN_8_u_0_1_1)) )) (net Ready_fast (joined (portRef Q (instanceRef Ready_fast)) (portRef B (instanceRef Ready_fast_RNO)) (portRef A (instanceRef Ready_fast_RNI29NA)) )) + (net G_1_0 (joined + (portRef Z (instanceRef nRCAS_RNO_0)) + (portRef A (instanceRef nRCAS_RNO)) + )) + (net G_1_1 (joined + (portRef Z (instanceRef nRCAS_RNO_1)) + (portRef B (instanceRef nRCAS_RNO)) + )) (net UFMSDI_r_xx_mm_1 (joined (portRef Z (instanceRef UFMSDI_RNO_0)) (portRef D (instanceRef UFMSDI_RNO)) @@ -2066,11 +2190,10 @@ )) (net (rename MAin_c_0 "MAin_c[0]") (joined (portRef O (instanceRef MAin_pad_0)) - (portRef B (instanceRef un1_CMDWR)) (portRef A (instanceRef un9_RA_0)) - (portRef D (instanceRef CmdEnable16_0_a2_4_0)) - (portRef B (instanceRef XOR8MEG18_0_a2)) - (portRef C (instanceRef CmdEnable17_0_a2)) + (portRef A (instanceRef ADWR_8_4)) + (portRef A (instanceRef C1WR_2_0)) + (portRef C (instanceRef CMDWR)) (portRef D (instanceRef RowA_0)) )) (net (rename MAin_0 "MAin[0]") (joined @@ -2079,14 +2202,11 @@ )) (net (rename MAin_c_1 "MAin_c[1]") (joined (portRef O (instanceRef MAin_pad_1)) - (portRef C (instanceRef un1_CMDWR)) (portRef A (instanceRef un9_RA_1)) - (portRef C (instanceRef CmdEnable17_0_a2_4)) - (portRef D (instanceRef CmdEnable16_0_a2_5)) - (portRef A (instanceRef C1WR_0_a2)) - (portRef C (instanceRef XOR8MEG18_0_a2)) + (portRef B (instanceRef ADWR_8_4)) + (portRef A (instanceRef CMDWR_2)) + (portRef B (instanceRef C1WR_2_0)) (portRef D (instanceRef RowA_1)) - (portRef D (instanceRef C1Submitted_RNO)) )) (net (rename MAin_1 "MAin[1]") (joined (portRef (member main 8)) @@ -2095,7 +2215,9 @@ (net (rename MAin_c_2 "MAin_c[2]") (joined (portRef O (instanceRef MAin_pad_2)) (portRef A (instanceRef un9_RA_2)) - (portRef A (instanceRef C1WR_0_a2_0_3)) + (portRef B (instanceRef CMDWR_2)) + (portRef C (instanceRef ADWR_8)) + (portRef C (instanceRef C1WR)) (portRef D (instanceRef RowA_2)) )) (net (rename MAin_2 "MAin[2]") (joined @@ -2105,7 +2227,9 @@ (net (rename MAin_c_3 "MAin_c[3]") (joined (portRef O (instanceRef MAin_pad_3)) (portRef A (instanceRef un9_RA_3)) - (portRef B (instanceRef C1WR_0_a2_0_3)) + (portRef C (instanceRef CMDWR_2)) + (portRef C (instanceRef C1WR_2_0)) + (portRef D (instanceRef ADWR_8)) (portRef D (instanceRef RowA_3)) )) (net (rename MAin_3 "MAin[3]") (joined @@ -2115,7 +2239,9 @@ (net (rename MAin_c_4 "MAin_c[4]") (joined (portRef O (instanceRef MAin_pad_4)) (portRef A (instanceRef un9_RA_4)) - (portRef A (instanceRef C1WR_0_a2_0_4)) + (portRef C (instanceRef ADWR_8_4)) + (portRef D (instanceRef CMDWR_2)) + (portRef D (instanceRef C1WR_2_0)) (portRef D (instanceRef RowA_4)) )) (net (rename MAin_4 "MAin[4]") (joined @@ -2125,7 +2251,8 @@ (net (rename MAin_c_5 "MAin_c[5]") (joined (portRef O (instanceRef MAin_pad_5)) (portRef A (instanceRef un9_RA_5)) - (portRef B (instanceRef C1WR_0_a2_0_4)) + (portRef D (instanceRef ADWR_8_4)) + (portRef B (instanceRef C1WR_7)) (portRef D (instanceRef RowA_5)) )) (net (rename MAin_5 "MAin[5]") (joined @@ -2134,8 +2261,8 @@ )) (net (rename MAin_c_6 "MAin_c[6]") (joined (portRef O (instanceRef MAin_pad_6)) + (portRef A (instanceRef ADWR_8_2)) (portRef A (instanceRef un9_RA_6)) - (portRef C (instanceRef C1WR_0_a2_0_4)) (portRef D (instanceRef RowA_6)) )) (net (rename MAin_6 "MAin[6]") (joined @@ -2144,8 +2271,8 @@ )) (net (rename MAin_c_7 "MAin_c[7]") (joined (portRef O (instanceRef MAin_pad_7)) + (portRef B (instanceRef ADWR_8_2)) (portRef A (instanceRef un9_RA_7)) - (portRef D (instanceRef C1WR_0_a2_0_4)) (portRef D (instanceRef RowA_7)) )) (net (rename MAin_7 "MAin[7]") (joined @@ -2163,8 +2290,8 @@ )) (net (rename MAin_c_9 "MAin_c[9]") (joined (portRef O (instanceRef MAin_pad_9)) - (portRef A (instanceRef RDQML)) (portRef A (instanceRef RDQMH)) + (portRef A (instanceRef RDQML)) (portRef A (instanceRef un9_RA_9)) (portRef D (instanceRef RowA_9)) )) @@ -2190,9 +2317,10 @@ )) (net (rename Din_c_0 "Din_c[0]") (joined (portRef O (instanceRef Din_pad_0)) - (portRef B (instanceRef CmdEnable17_0_a2_3)) - (portRef A (instanceRef CmdEnable16_0_a2_4)) - (portRef A (instanceRef XOR8MEG_3_u_0_a3_2)) + (portRef D (instanceRef XOR8MEG_3_u_0_a3_0_1)) + (portRef A (instanceRef CmdEnable17_0_a2)) + (portRef A (instanceRef CmdEnable16_0_a3_4)) + (portRef C (instanceRef Cmdn8MEGEN_4_u_i_0)) (portRef D (instanceRef Bank_0)) (portRef D (instanceRef CmdUFMSDI)) (portRef D (instanceRef WRD_0)) @@ -2203,10 +2331,10 @@ )) (net (rename Din_c_1 "Din_c[1]") (joined (portRef O (instanceRef Din_pad_1)) - (portRef A (instanceRef CmdEnable17_0_a2_3)) - (portRef B (instanceRef CmdEnable16_0_a2_4_0)) - (portRef A (instanceRef CmdLEDEN_4_u_i_a2_0)) - (portRef A (instanceRef XOR8MEG_3_u_0_a3_3)) + (portRef A (instanceRef CmdEnable16_0_a3_5)) + (portRef A (instanceRef CmdEnable17_0_a3_4)) + (portRef C (instanceRef CmdLEDEN_4_u_i_0)) + (portRef A (instanceRef XOR8MEG_3_u_0_a3_0_2)) (portRef D (instanceRef Bank_1)) (portRef D (instanceRef CmdUFMCLK)) (portRef D (instanceRef WRD_1)) @@ -2217,9 +2345,9 @@ )) (net (rename Din_c_2 "Din_c[2]") (joined (portRef O (instanceRef Din_pad_2)) - (portRef A (instanceRef CmdEnable17_0_a2_4)) - (portRef B (instanceRef CmdEnable16_0_a2_5)) - (portRef B (instanceRef XOR8MEG_3_u_0_a3_2)) + (portRef C (instanceRef XOR8MEG_3_u_0_a3_0_1)) + (portRef B (instanceRef CmdEnable17_0_a2)) + (portRef B (instanceRef CmdEnable16_0_a3_5)) (portRef D (instanceRef Bank_2)) (portRef D (instanceRef CmdUFMCS)) (portRef D (instanceRef WRD_2)) @@ -2230,13 +2358,13 @@ )) (net (rename Din_c_3 "Din_c[3]") (joined (portRef O (instanceRef Din_pad_3)) - (portRef D (instanceRef CmdUFMCLK_1_sqmuxa_0_a2)) - (portRef D (instanceRef CmdLEDEN_4_u_i_a2)) (portRef D (instanceRef CmdSubmitted_1_sqmuxa_0_a2)) - (portRef A (instanceRef CmdEnable17_0_o2)) - (portRef C (instanceRef CmdEnable16_0_a2_4_0)) + (portRef D (instanceRef CmdUFMCLK_1_sqmuxa_0_a2)) + (portRef B (instanceRef XOR8MEG_3_u_0_a3_0_1)) + (portRef C (instanceRef CmdEnable16_0_a3_5)) + (portRef B (instanceRef CmdEnable17_0_a3_4)) + (portRef A (instanceRef Cmdn8MEGEN_4_u_i_o2)) (portRef A (instanceRef Cmdn8MEGEN_4_u_i_a2_2)) - (portRef C (instanceRef XOR8MEG_3_u_0_a3_2)) (portRef D (instanceRef Bank_3)) (portRef D (instanceRef WRD_3)) )) @@ -2246,9 +2374,10 @@ )) (net (rename Din_c_4 "Din_c[4]") (joined (portRef O (instanceRef Din_pad_4)) - (portRef D (instanceRef CmdEnable17_0_a2_3)) - (portRef A (instanceRef CmdEnable16_0_a2_1)) - (portRef A (instanceRef un1_Din_4)) + (portRef D (instanceRef XOR8MEG_3_u_0_o2_0)) + (portRef D (instanceRef CmdLEDEN_4_u_i_a2_0_0)) + (portRef A (instanceRef CmdEnable17_0_o2)) + (portRef D (instanceRef CmdEnable16_0_a3_5)) (portRef A (instanceRef Cmdn8MEGEN_4_u_i_o2_0)) (portRef D (instanceRef Bank_4)) (portRef D (instanceRef WRD_4)) @@ -2259,13 +2388,13 @@ )) (net (rename Din_c_5 "Din_c[5]") (joined (portRef O (instanceRef Din_pad_5)) - (portRef C (instanceRef CmdUFMCLK_1_sqmuxa_0_a2)) - (portRef C (instanceRef CmdLEDEN_4_u_i_a2)) (portRef C (instanceRef CmdSubmitted_1_sqmuxa_0_a2)) - (portRef B (instanceRef CmdEnable17_0_o2)) - (portRef B (instanceRef CmdEnable16_0_a2_4)) - (portRef B (instanceRef un1_Din_4)) - (portRef B (instanceRef CmdLEDEN_4_u_i_a2_0)) + (portRef C (instanceRef CmdUFMCLK_1_sqmuxa_0_a2)) + (portRef B (instanceRef XOR8MEG_3_u_0_o2_0)) + (portRef A (instanceRef CmdLEDEN_4_u_i_a2_0_0)) + (portRef B (instanceRef CmdEnable16_0_a3_4)) + (portRef C (instanceRef CmdEnable17_0_a3_4)) + (portRef B (instanceRef Cmdn8MEGEN_4_u_i_o2)) (portRef B (instanceRef Cmdn8MEGEN_4_u_i_a2_2)) (portRef D (instanceRef Bank_5)) (portRef D (instanceRef WRD_5)) @@ -2276,11 +2405,12 @@ )) (net (rename Din_c_6 "Din_c[6]") (joined (portRef O (instanceRef Din_pad_6)) - (portRef C (instanceRef un1_Din_4)) - (portRef A (instanceRef RA11_2)) + (portRef C (instanceRef XOR8MEG_3_u_0_o2_0)) + (portRef C (instanceRef CmdLEDEN_4_u_i_a2_0_0)) + (portRef B (instanceRef CmdEnable17_0_o2)) + (portRef C (instanceRef CmdEnable16_0_a3_4)) (portRef B (instanceRef Cmdn8MEGEN_4_u_i_o2_0)) - (portRef B (instanceRef CmdEnable17_0_a2_4)) - (portRef C (instanceRef CmdEnable16_0_a2_5)) + (portRef A (instanceRef RA11_2)) (portRef D (instanceRef Bank_6)) (portRef D (instanceRef WRD_6)) )) @@ -2290,10 +2420,11 @@ )) (net (rename Din_c_7 "Din_c[7]") (joined (portRef O (instanceRef Din_pad_7)) - (portRef C (instanceRef CmdEnable17_0_a2_3)) - (portRef B (instanceRef CmdEnable16_0_a2_1)) - (portRef D (instanceRef un1_Din_4)) + (portRef A (instanceRef XOR8MEG_3_u_0_o2_0)) + (portRef B (instanceRef CmdLEDEN_4_u_i_a2_0_0)) + (portRef D (instanceRef CmdEnable16_0_a3_4)) (portRef C (instanceRef Cmdn8MEGEN_4_u_i_o2_0)) + (portRef D (instanceRef CmdEnable17_0_a3_4)) (portRef D (instanceRef Bank_7)) (portRef D (instanceRef WRD_7)) )) @@ -2344,7 +2475,7 @@ )) (net nCRAS_c (joined (portRef O (instanceRef nCRAS_pad)) - (portRef C (instanceRef LED_pad_RNO)) + (portRef D (instanceRef LED_pad_RNO)) (portRef A (instanceRef nCRAS_pad_RNIBPVB)) (portRef A (instanceRef RASr_RNO)) )) @@ -2354,8 +2485,10 @@ )) (net nFWE_c (joined (portRef O (instanceRef nFWE_pad)) - (portRef C (instanceRef C1WR_0_a2_0_3)) (portRef B (instanceRef nCCAS_pad_RNI01SJ)) + (portRef D (instanceRef CMDWR)) + (portRef B (instanceRef ADWR)) + (portRef D (instanceRef C1WR)) (portRef A (instanceRef nFWE_pad_RNI420B)) )) (net nFWE (joined @@ -2612,6 +2745,7 @@ )) (net RCKE_c (joined (portRef Q (instanceRef RCKE)) + (portRef B (instanceRef nRCS_RNO_3)) (portRef C (instanceRef nRRAS_5_u_i_0)) (portRef I (instanceRef RCKE_pad)) (portRef C (instanceRef nRWE_RNO_3)) @@ -2696,19 +2830,19 @@ (portRef UFMSDO) (portRef I (instanceRef UFMSDO_pad)) )) - (net N_460_0 (joined + (net N_428_0 (joined (portRef Z (instanceRef CmdSubmitted_RNO)) (portRef D (instanceRef CmdSubmitted)) )) - (net N_461_0 (joined + (net N_429_0 (joined (portRef Z (instanceRef InitReady_RNO)) (portRef D (instanceRef InitReady)) )) - (net N_462_0 (joined + (net N_430_0 (joined (portRef Z (instanceRef Ready_RNO)) (portRef D (instanceRef Ready)) )) - (net N_463_0 (joined + (net N_431_0 (joined (portRef Z (instanceRef Ready_fast_RNO)) (portRef D (instanceRef Ready_fast)) )) @@ -2751,14 +2885,9 @@ (portRef CD (instanceRef RowA_1)) (portRef CD (instanceRef RowA_0)) )) - (net (rename IS_i_0 "IS_i[0]") (joined - (portRef Z (instanceRef IS_i_0)) - (portRef D (instanceRef RA10)) - )) (net RASr2_i (joined - (portRef Z (instanceRef RASr2_RNIAFR1)) + (portRef Z (instanceRef S_RNO_1)) (portRef CD (instanceRef S_1)) - (portRef CD (instanceRef S_0)) )) (net nRWE_RNO_4 (joined (portRef Z (instanceRef nRWE_RNO_4)) @@ -2768,14 +2897,6 @@ (portRef Z (instanceRef nRWE_RNO_3)) (portRef ALUT (instanceRef nRWE_RNO_1)) )) - (net CmdEnable_s_am (joined - (portRef Z (instanceRef CmdEnable_s_am)) - (portRef BLUT (instanceRef CmdEnable_s)) - )) - (net CmdEnable_s_bm (joined - (portRef Z (instanceRef CmdEnable_s_bm)) - (portRef ALUT (instanceRef CmdEnable_s)) - )) ) (property orig_inst_of (string "RAM2GS")) ) diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.jed b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.jed index 397bb6e..578cdf4 100644 --- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.jed +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.jed @@ -6,7 +6,7 @@ NOTE Readback: Off* NOTE Security: Off* NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation * NOTE All Rights Reserved * -NOTE DATE CREATED: Thu Sep 21 05:38:47 2023 * +NOTE DATE CREATED: Sat Jan 06 06:25:16 2024 * NOTE DESIGN NAME: RAM2GS * NOTE DEVICE NAME: LCMXO256C-3TQFP100 * NOTE PIN ASSIGNMENTS * @@ -89,7 +89,7 @@ L00000 11111101111011111111111111111111101111001010010011010111011100101001001101011110 11001010010011010111101111111111 11111111001011111111011110111100101111111101111011110010111111110111101111001011 -11111101111011111111111111111111101111001010010011010111011100101001001101011101 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+11111111111011110011000100111101101011001100010011110010011100110001001111011001 11001010010011110111011111111111 11111111111111111111111111111111111111111111111111110010100100111100111111111111 -11111111111111110011000100111101100111111111111111111111111100110001001111001001 +11111111111111110011000100111100101111111111111111111111111100110001001111001001 11111111111111111111111111111111 11111111111111111111111111111111111111111111111111110010111111110111101111111111 11111111111111110010100100111100111111111111111111111111111100110001001111011001 11111111111111111111111111111111 * -CD82C* +CAF82* N User Electronic Signature Data* U00000000000000000000000000000000* -239B +22F3 diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mrp b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mrp index e52b0db..14ecc9d 100644 --- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mrp +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mrp @@ -15,18 +15,18 @@ Target Vendor: LATTICE Target Device: LCMXO256CTQFP100 Target Performance: 3 Mapper: mj5g00, version: Diamond (64-bit) 3.12.1.454 -Mapped on: 09/21/23 05:38:29 +Mapped on: 01/06/24 06:24:57 Design Summary -------------- Number of PFU registers: 92 out of 256 (36%) - Number of SLICEs: 69 out of 128 (54%) - SLICEs as Logic/ROM: 69 out of 128 (54%) + Number of SLICEs: 76 out of 128 (59%) + SLICEs as Logic/ROM: 76 out of 128 (59%) SLICEs as RAM: 0 out of 64 (0%) SLICEs as Carry: 9 out of 128 (7%) - Number of LUT4s: 137 out of 256 (54%) - Number used as logic LUTs: 119 + Number of LUT4s: 151 out of 256 (59%) + Number used as logic LUTs: 133 Number used as distributed RAM: 0 Number used as ripple logic: 18 Number used as shift registers: 0 @@ -49,37 +49,38 @@ Design Summary Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS ) Number of Clock Enables: 5 Net XOR8MEG18: 3 loads, 3 LSLICEs - Net N_31: 1 loads, 1 LSLICEs - Net N_33: 1 loads, 1 LSLICEs - Net N_159_i: 2 loads, 2 LSLICEs + Net N_24: 1 loads, 1 LSLICEs + Net N_26: 1 loads, 1 LSLICEs + Net N_153_i: 2 loads, 2 LSLICEs Net CmdUFMCLK_1_sqmuxa: 2 loads, 2 LSLICEs - Number of LSRs: 4 + Number of LSRs: 5 Net RA10s_i: 1 loads, 1 LSLICEs Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs - Net RASr2: 2 loads, 2 LSLICEs + Net RASr2: 1 loads, 1 LSLICEs Net Ready_fast: 7 loads, 7 LSLICEs + Net RCKEEN_8_u_0_1_a1_0: 1 loads, 1 LSLICEs Number of nets driven by tri-state buffers: 0 - Top 10 highest fanout non-clock nets: Page 1 -Design: RAM2GS Date: 09/21/23 05:38:29 +Design: RAM2GS Date: 01/06/24 06:24:57 Design Summary (cont) --------------------- - Net InitReady: 16 loads - Net Ready: 16 loads - Net S[1]: 13 loads - Net CO0: 12 loads + Top 10 highest fanout non-clock nets: + Net Ready: 18 loads + Net InitReady: 17 loads + Net S[1]: 17 loads + Net CO0: 16 loads + Net RASr2: 13 loads Net nRowColSel: 12 loads - Net RASr2: 11 loads Net Din_c[5]: 10 loads Net Din_c[3]: 9 loads Net IS[0]: 9 loads - Net MAin_c[1]: 8 loads + Net IS[1]: 8 loads @@ -125,17 +126,17 @@ IO (PIO) Attributes | nRWE | OUTPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | RCKE | OUTPUT | LVCMOS33 | | | -+---------------------+-----------+-----------+------------+------------+ Page 2 -Design: RAM2GS Date: 09/21/23 05:38:29 +Design: RAM2GS Date: 01/06/24 06:24:57 IO (PIO) Attributes (cont) -------------------------- ++---------------------+-----------+-----------+------------+------------+ | RCLK | INPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | nRCS | OUTPUT | LVCMOS33 | | | @@ -191,17 +192,17 @@ IO (PIO) Attributes (cont) | nCCAS | INPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | Dout[7] | OUTPUT | LVCMOS33 | | | -+---------------------+-----------+-----------+------------+------------+ Page 3 -Design: RAM2GS Date: 09/21/23 05:38:29 +Design: RAM2GS Date: 01/06/24 06:24:57 IO (PIO) Attributes (cont) -------------------------- ++---------------------+-----------+-----------+------------+------------+ | Dout[6] | OUTPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | Dout[5] | OUTPUT | LVCMOS33 | | | @@ -258,13 +259,12 @@ IO (PIO) Attributes (cont) - Page 4 -Design: RAM2GS Date: 09/21/23 05:38:29 +Design: RAM2GS Date: 01/06/24 06:24:57 Removed logic ------------- @@ -275,7 +275,6 @@ Signal nFWE_c_i was merged into signal nFWE_c Signal nCRAS_c_i_0 was merged into signal nCRAS_c Signal nCCAS_c_i was merged into signal nCCAS_c Signal Ready_fast_i was merged into signal Ready_fast -Signal IS_i[0] was merged into signal IS[0] Signal RASr2_i was merged into signal RASr2 Signal XOR8MEG.CN was merged into signal PHI2_c Signal GND undriven or does not drive anything - clipped. @@ -295,8 +294,7 @@ Block nFWE_pad_RNI420B was optimized away. Block RASr_RNO was optimized away. Block nCCAS_pad_RNISUR8 was optimized away. Block Ready_fast_RNI29NA was optimized away. -Block IS_i[0] was optimized away. -Block RASr2_RNIAFR1 was optimized away. +Block S_RNO[1] was optimized away. Block XOR8MEG.CN was optimized away. Block GND was optimized away. Block VCC was optimized away. @@ -325,6 +323,8 @@ Run Time and Memory Usage + + Page 5 diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pad b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pad index 8b560f5..e078f75 100644 --- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pad +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pad @@ -6,7 +6,7 @@ Performance Grade: 3 PACKAGE: TQFP100 Package Status: Final Version 1.19 -Thu Sep 21 05:38:42 2023 +Sat Jan 06 06:25:11 2024 Pinout by Port Name: +-----------+----------+---------------+------+----------------------------------+ @@ -267,5 +267,5 @@ Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Thu Sep 21 05:38:42 2023 +Sat Jan 06 06:25:11 2024 diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.prf b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.prf index eb655eb..a4d23ac 100644 --- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.prf +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.prf @@ -1,5 +1,5 @@ SCHEMATIC START ; -# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Thu Sep 21 05:38:29 2023 +# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Sat Jan 06 06:24:58 2024 SYSCONFIG INBUF=ON CONFIG_SECURE=OFF ; LOCATE COMP "RD[0]" SITE "64" ; diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.srr b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.srr index 6b8430b..d9fe748 100644 --- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.srr +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.srr @@ -3,7 +3,7 @@ #OS: Windows 8 6.2 #Hostname: ZANEMACWIN11 -# Thu Sep 21 05:38:16 2023 +# Sat Jan 6 06:24:47 2024 #Implementation: impl1 @@ -50,19 +50,22 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-SPI.v" (library work) Verilog syntax check successful! + +Compiler output is up to date. No re-compile necessary + Selecting top level module RAM2GS @N: CG364 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work. Running optimization stage 1 on RAM2GS ....... -Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 100MB) +Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 100MB) Running optimization stage 2 on RAM2GS ....... Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB) -At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 96MB peak: 97MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Sep 21 05:38:17 2023 +# Sat Jan 6 06:24:47 2024 ###########################################################] ###########################################################[ @@ -89,7 +92,7 @@ At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Sep 21 05:38:17 2023 +# Sat Jan 6 06:24:48 2024 ###########################################################] @@ -104,7 +107,7 @@ At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Sep 21 05:38:17 2023 +# Sat Jan 6 06:24:48 2024 ###########################################################] ###########################################################[ @@ -125,18 +128,17 @@ Implementation : impl1 Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ @N|Running in 64-bit mode +File \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Sep 21 05:38:18 2023 +# Sat Jan 6 06:24:49 2024 ###########################################################] -Premap Report - -# Thu Sep 21 05:38:19 2023 +# Sat Jan 6 06:24:49 2024 Copyright (C) 1994-2021 Synopsys, Inc. @@ -158,7 +160,7 @@ Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB) -Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 140MB) +Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 140MB) Reading constraint file: \\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc @L: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1_scck.rpt @@ -186,7 +188,6 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h @N: FX493 |Applying initial value "0" on instance CmdLEDEN. @N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN. @N: FX493 |Applying initial value "1" on instance nRCS. -@N: FX493 |Applying initial value "0" on instance LEDEN. @N: FX493 |Applying initial value "0" on instance n8MEGEN. @N: FX493 |Applying initial value "1" on instance nRRAS. @N: FX493 |Applying initial value "0" on instance CmdUFMCLK. @@ -205,17 +206,17 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) -Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) +Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) -Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) +Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) -Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) +Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) @N: FX1184 |Applying syn_allowed_resources blockrams=0 on top level netlist RAM2GS -Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 181MB peak: 181MB) +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) @@ -282,10 +283,10 @@ Clock Tree ID Driving Element Drive Element Type Fanout Sample I @N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. -Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB) +Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) -Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB) +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB) Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB) @@ -294,13 +295,11 @@ Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 98MB peak: 184MB) -Process took 0h:00m:02s realtime, 0h:00m:01s cputime -# Thu Sep 21 05:38:21 2023 +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Sat Jan 6 06:24:51 2024 ###########################################################] -Map & Optimize Report - -# Thu Sep 21 05:38:21 2023 +# Sat Jan 6 06:24:51 2024 Copyright (C) 1994-2021 Synopsys, Inc. @@ -319,29 +318,29 @@ Implementation : impl1 Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @ -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB) +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB) @N: MF916 |Option synthesis_strategy=base is enabled. @N: MF248 |Running in 64-bit mode. @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 140MB) +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 139MB) -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 140MB) +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 139MB) -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB) +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB) -Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 179MB peak: 179MB) +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 178MB peak: 178MB) -Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) @N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":147:4:147:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] @N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":134:4:134:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] @@ -351,10 +350,10 @@ Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00 @N: FX493 |Applying initial value "0" on instance IS[2]. @N: FX493 |Applying initial value "0" on instance IS[3]. -Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 184MB peak: 184MB) +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 184MB peak: 184MB) -Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB) +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 185MB peak: 185MB) Available hyper_sources - for debug and ip models @@ -367,64 +366,61 @@ Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CP Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 187MB) -Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB) +Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB) -Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB) +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB) -Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB) +Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB) -Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB) +Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ - 1 0h:00m:01s -3.26ns 127 / 89 - 2 0h:00m:01s -3.23ns 123 / 89 - 3 0h:00m:01s -3.23ns 123 / 89 - 4 0h:00m:01s -3.23ns 123 / 89 - 5 0h:00m:01s -3.23ns 124 / 89 - 6 0h:00m:01s -3.23ns 124 / 89 -@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 7 loads 1 time to improve timing. -@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing. -@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":147:4:147:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 15 loads 1 time to improve timing. + 1 0h:00m:01s -4.01ns 133 / 89 + 2 0h:00m:01s -3.96ns 131 / 89 +@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 8 loads 1 time to improve timing. +@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 7 loads 1 time to improve timing. +@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":147:4:147:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 19 loads 1 time to improve timing. Timing driven replication report Added 3 Registers via timing driven replication Added 1 LUTs via timing driven replication - 7 0h:00m:02s -2.99ns 128 / 92 + 3 0h:00m:02s -3.08ns 143 / 92 + 4 0h:00m:02s -3.08ns 141 / 92 - 8 0h:00m:02s -2.99ns 127 / 92 - 9 0h:00m:02s -3.09ns 127 / 92 - 10 0h:00m:02s -3.19ns 127 / 92 - 11 0h:00m:02s -3.19ns 127 / 92 - 12 0h:00m:02s -3.19ns 127 / 92 + 5 0h:00m:02s -3.08ns 140 / 92 + 6 0h:00m:02s -3.19ns 140 / 92 + 7 0h:00m:02s -3.19ns 140 / 92 + 8 0h:00m:02s -3.19ns 140 / 92 + 9 0h:00m:02s -3.19ns 140 / 92 -Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 190MB) +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 191MB) -Finished restoring hierarchy (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 191MB) +Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 191MB) -Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 155MB peak: 191MB) +Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 155MB peak: 192MB) Writing Analyst data base \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_m.srm -Finished Writing Netlist Databases (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 192MB peak: 192MB) +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 192MB) Writing EDIF Netlist and constraint files @N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.edi @N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF -Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 196MB peak: 196MB) +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 196MB peak: 196MB) -Finished Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 196MB peak: 196MB) +Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 196MB peak: 197MB) -Start final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 194MB peak: 196MB) +Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 195MB peak: 197MB) @N: MT615 |Found clock RCLK with period 16.00ns @N: MT615 |Found clock PHI2 with period 350.00ns @@ -433,7 +429,7 @@ Start final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:0 ##### START OF TIMING REPORT #####[ -# Timing report written on Thu Sep 21 05:38:27 2023 +# Timing report written on Sat Jan 6 06:24:55 2024 # @@ -466,8 +462,8 @@ nCRAS 2.9 MHz 0.6 MHz 350.000 1613.150 -3.60 Estimated period and frequency reported as NA means no slack depends directly on the clock waveform -@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. @W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small. +@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. @W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. @W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small. @W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small. @@ -481,10 +477,10 @@ Clocks | rise to rise | fall to fall | rise to --------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack --------------------------------------------------------------------------------------------------------------- -RCLK RCLK | 16.000 7.560 | No paths - | No paths - | No paths - +RCLK RCLK | 16.000 7.464 | No paths - | No paths - | No paths - RCLK PHI2 | 2.000 -1.216 | No paths - | 1.000 -2.312 | No paths - PHI2 RCLK | No paths - | No paths - | No paths - | 1.000 -3.705 -PHI2 PHI2 | No paths - | 350.000 343.998 | 175.000 166.500 | 175.000 171.784 +PHI2 PHI2 | No paths - | 350.000 344.094 | 175.000 165.215 | 175.000 171.784 nCRAS RCLK | No paths - | No paths - | No paths - | 1.000 -3.609 =============================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. @@ -518,10 +514,10 @@ CmdUFMCS PHI2 FD1P3AX Q CmdUFMCS 1.348 CmdUFMSDI PHI2 FD1P3AX Q CmdUFMSDI 1.348 -3.297 CmdLEDEN PHI2 FD1P3AX Q CmdLEDEN 1.456 -2.216 Cmdn8MEGEN PHI2 FD1P3AX Q Cmdn8MEGEN 1.456 -2.216 -Bank[2] PHI2 FD1S3AX Q Bank[2] 1.348 166.500 -Bank[3] PHI2 FD1S3AX Q Bank[3] 1.348 166.500 -Bank[4] PHI2 FD1S3AX Q Bank[4] 1.348 166.500 -Bank[5] PHI2 FD1S3AX Q Bank[5] 1.348 166.500 +Bank[0] PHI2 FD1S3AX Q Bank[0] 1.348 165.215 +Bank[1] PHI2 FD1S3AX Q Bank[1] 1.348 165.215 +Bank[2] PHI2 FD1S3AX Q Bank[2] 1.348 165.215 +Bank[3] PHI2 FD1S3AX Q Bank[3] 1.348 165.215 ======================================================================================= @@ -535,13 +531,13 @@ Instance Reference Type Pin Net Time UFMCLK PHI2 FD1S3AX D UFMCLK_RNO -0.003 -3.705 UFMSDI PHI2 FD1S3AX D UFMSDI_RNO -0.003 -3.705 nUFMCS PHI2 FD1S3AY D nUFMCS_s_0_N_5_i -0.003 -3.705 -LEDEN PHI2 FD1P3AX SP N_33 0.806 -2.800 -n8MEGEN PHI2 FD1P3AX SP N_31 0.806 -2.800 -LEDEN PHI2 FD1P3AX D N_70 -0.003 -2.216 -n8MEGEN PHI2 FD1P3AX D N_69 -0.003 -2.216 -CmdSubmitted PHI2 FD1S3AX D N_460_0 173.997 166.500 -ADSubmitted PHI2 FD1S3AX D ADSubmitted_r 173.997 167.797 -C1Submitted PHI2 FD1S3AX D C1Submitted_RNO 173.997 167.797 +LEDEN PHI2 FD1P3AX SP N_26 0.806 -2.800 +n8MEGEN PHI2 FD1P3AX SP N_24 0.806 -2.800 +LEDEN PHI2 FD1P3AX D N_49 -0.003 -2.216 +n8MEGEN PHI2 FD1P3AX D N_48 -0.003 -2.216 +CmdEnable PHI2 FD1S3AX D CmdEnable_s 173.997 165.215 +CmdSubmitted PHI2 FD1S3AX D N_428_0 173.997 165.311 +ADSubmitted PHI2 FD1S3AX D ADSubmitted_r 173.997 166.404 ============================================================================================ @@ -573,7 +569,7 @@ CmdSubmitted FD1S3AX Q Out 1.552 1.552 r - CmdSubmitted Net - - - - 3 PHI2r3_RNITCN41 ORCALUT4 A In 0.000 1.552 r - PHI2r3_RNITCN41 ORCALUT4 Z Out 1.393 2.945 r - -N_139_i Net - - - - 3 +N_137_i Net - - - - 3 UFMCLK_RNO ORCALUT4 A In 0.000 2.945 r - UFMCLK_RNO ORCALUT4 Z Out 0.757 3.702 r - UFMCLK_RNO Net - - - - 1 @@ -604,7 +600,7 @@ CmdSubmitted FD1S3AX Q Out 1.552 1.552 r - CmdSubmitted Net - - - - 3 PHI2r3_RNITCN41 ORCALUT4 A In 0.000 1.552 r - PHI2r3_RNITCN41 ORCALUT4 Z Out 1.393 2.945 r - -N_139_i Net - - - - 3 +N_137_i Net - - - - 3 nUFMCS_s_0_N_5_i ORCALUT4 A In 0.000 2.945 r - nUFMCS_s_0_N_5_i ORCALUT4 Z Out 0.757 3.702 r - nUFMCS_s_0_N_5_i Net - - - - 1 @@ -635,7 +631,7 @@ CmdSubmitted FD1S3AX Q Out 1.552 1.552 r - CmdSubmitted Net - - - - 3 PHI2r3_RNITCN41 ORCALUT4 A In 0.000 1.552 r - PHI2r3_RNITCN41 ORCALUT4 Z Out 1.393 2.945 r - -N_139_i Net - - - - 3 +N_137_i Net - - - - 3 UFMSDI_RNO ORCALUT4 A In 0.000 2.945 r - UFMSDI_RNO ORCALUT4 Z Out 0.757 3.702 r - UFMSDI_RNO Net - - - - 1 @@ -654,21 +650,21 @@ Detailed Report for Clock: RCLK Starting Points with Worst Slack ******************************** - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------ -LEDEN RCLK FD1P3AX Q LEDEN 1.552 -2.312 -n8MEGEN RCLK FD1P3AX Q n8MEGEN 1.456 -2.216 -FS[13] RCLK FD1S3AX Q FS[13] 1.552 7.560 -FS[14] RCLK FD1S3AX Q FS[14] 1.552 7.560 -FS[15] RCLK FD1S3AX Q FS[15] 1.552 7.560 -FS[17] RCLK FD1S3AX Q FS[17] 1.552 7.560 -S[1] RCLK FD1S3IX Q S[1] 1.768 8.533 -S[0] RCLK FD1S3IX Q CO0 1.756 8.545 -FS[16] RCLK FD1S3AX Q FS[16] 1.612 8.689 -FS[12] RCLK FD1S3AX Q FS[12] 1.552 8.749 -============================================================================= + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------- +LEDEN RCLK FD1P3AX Q LEDEN 1.552 -2.312 +n8MEGEN RCLK FD1P3AX Q n8MEGEN 1.456 -2.216 +FS[12] RCLK FD1S3AX Q FS[12] 1.552 7.464 +FS[14] RCLK FD1S3AX Q FS[14] 1.552 7.464 +FS[15] RCLK FD1S3AX Q FS[15] 1.552 7.464 +FS[17] RCLK FD1S3AX Q FS[17] 1.552 7.464 +InitReady RCLK FD1S3AX Q InitReady 1.792 8.569 +S[1] RCLK FD1S3IX Q S[1] 1.792 8.569 +S[0] RCLK FD1S3IX Q CO0 1.780 8.581 +FS[13] RCLK FD1S3AX Q FS[13] 1.612 8.593 +================================================================================ Ending Points with Worst Slack @@ -678,16 +674,16 @@ Ending Points with Worst Slack Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------- -CmdLEDEN RCLK FD1P3AX D N_21_i -0.003 -2.312 +CmdLEDEN RCLK FD1P3AX D N_14_i -0.003 -2.312 XOR8MEG RCLK FD1P3AX D XOR8MEG_3 -0.003 -2.312 -Cmdn8MEGEN RCLK FD1P3AX D N_19_i -0.003 -2.216 +Cmdn8MEGEN RCLK FD1P3AX D N_12_i -0.003 -2.216 RA11 RCLK FD1S3IX D RA11_2 0.997 -1.216 -UFMSDI RCLK FD1S3AX D UFMSDI_RNO 14.997 7.560 +UFMSDI RCLK FD1S3AX D UFMSDI_RNO 14.997 7.464 UFMCLK RCLK FD1S3AX D UFMCLK_RNO 14.997 7.668 -LEDEN RCLK FD1P3AX SP N_33 15.806 8.261 -n8MEGEN RCLK FD1P3AX SP N_31 15.806 8.261 -nRCS RCLK FD1S3AY D N_28_i 14.997 8.533 +nRCAS RCLK FD1S3AY D N_46_i 14.997 8.569 nUFMCS RCLK FD1S3AY D nUFMCS_s_0_N_5_i 14.997 8.653 +nRCS RCLK FD1S3AY D N_143_i 14.997 8.881 +LEDEN RCLK FD1P3AX SP N_26 15.806 9.463 ========================================================================================= @@ -717,9 +713,9 @@ Name Type Name Dir Delay Time Fan Out(s --------------------------------------------------------------------------------- LEDEN FD1P3AX Q Out 1.552 1.552 r - LEDEN Net - - - - 3 -CmdLEDEN_RNO ORCALUT4 A In 0.000 1.552 r - +CmdLEDEN_RNO ORCALUT4 B In 0.000 1.552 r - CmdLEDEN_RNO ORCALUT4 Z Out 0.757 2.309 r - -N_21_i Net - - - - 1 +N_14_i Net - - - - 1 CmdLEDEN FD1P3AX D In 0.000 2.309 r - ================================================================================= @@ -740,16 +736,16 @@ Path information for path number 2: The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK The end point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------- -LEDEN FD1P3AX Q Out 1.552 1.552 r - -LEDEN Net - - - - 3 -XOR8MEG_3_u_0_a3_3 ORCALUT4 B In 0.000 1.552 r - -XOR8MEG_3_u_0_a3_3 ORCALUT4 Z Out 0.757 2.309 f - -XOR8MEG_3 Net - - - - 1 -XOR8MEG FD1P3AX D In 0.000 2.309 f - -===================================================================================== +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------------- +LEDEN FD1P3AX Q Out 1.552 1.552 r - +LEDEN Net - - - - 3 +XOR8MEG_3_u_0_a3_0_2 ORCALUT4 B In 0.000 1.552 r - +XOR8MEG_3_u_0_a3_0_2 ORCALUT4 Z Out 0.757 2.309 f - +XOR8MEG_3 Net - - - - 1 +XOR8MEG FD1P3AX D In 0.000 2.309 f - +======================================================================================= Path information for path number 3: @@ -775,7 +771,7 @@ n8MEGEN FD1P3AX Q Out 1.456 1.456 r - n8MEGEN Net - - - - 2 Cmdn8MEGEN_RNO ORCALUT4 C In 0.000 1.456 r - Cmdn8MEGEN_RNO ORCALUT4 Z Out 0.757 2.213 r - -N_19_i Net - - - - 1 +N_12_i Net - - - - 1 Cmdn8MEGEN FD1P3AX D In 0.000 2.213 r - ================================================================================= @@ -795,10 +791,10 @@ Starting Points with Worst Slack Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------- -CBR nCRAS FD1S3AX Q CBR 1.660 -3.609 -CBR_fast nCRAS FD1S3AX Q CBR_fast 1.456 -3.513 +CBR_fast nCRAS FD1S3AX Q CBR_fast 1.552 -3.609 +CBR nCRAS FD1S3AX Q CBR 1.612 -3.561 FWEr nCRAS FD1S3AX Q FWEr 1.552 -3.501 -FWEr_fast nCRAS FD1S3AX Q FWEr_fast 1.456 -3.405 +FWEr_fast nCRAS FD1S3AX Q FWEr_fast 1.552 -3.501 ================================================================================ @@ -809,11 +805,11 @@ Ending Points with Worst Slack Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------- -nRWE nCRAS FD1S3AY D N_39_i -0.003 -3.609 -nRowColSel nCRAS FD1S3IX D nRowColSel_0_0 -0.003 -3.609 -nRCAS nCRAS FD1S3AY D N_37_i -0.003 -3.513 -RCKEEN nCRAS FD1S3AX D RCKEEN_8 -0.003 -3.405 -nRCS nCRAS FD1S3AY D N_28_i -0.003 -3.405 +nRCAS nCRAS FD1S3AY D N_46_i -0.003 -3.609 +nRWE nCRAS FD1S3AY D N_144_i -0.003 -3.609 +nRowColSel nCRAS FD1S3IX D nRowColSel_0_0 -0.003 -3.561 +RCKEEN nCRAS FD1S3AX D RCKEEN_8 -0.003 -3.501 +nRCS nCRAS FD1S3AY D N_143_i -0.003 -3.501 ======================================================================================= @@ -833,24 +829,24 @@ Path information for path number 1: = Slack (non-critical) : -3.609 Number of logic level(s): 2 - Starting point: CBR / Q - Ending point: nRWE / D + Starting point: CBR_fast / Q + Ending point: nRCAS / D The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------- -CBR FD1S3AX Q Out 1.660 1.660 r - -CBR Net - - - - 5 -nRWE_RNO_0 ORCALUT4 A In 0.000 1.660 r - -nRWE_RNO_0 ORCALUT4 Z Out 1.189 2.849 f - -G_17_1 Net - - - - 1 -nRWE_RNO ORCALUT4 B In 0.000 2.849 f - -nRWE_RNO ORCALUT4 Z Out 0.757 3.606 r - -N_39_i Net - - - - 1 -nRWE FD1S3AY D In 0.000 3.606 r - -================================================================================= +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +---------------------------------------------------------------------------------------- +CBR_fast FD1S3AX Q Out 1.552 1.552 r - +CBR_fast Net - - - - 3 +nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 A In 0.000 1.552 r - +nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 Z Out 1.297 2.849 r - +nRCAS_0_sqmuxa_1 Net - - - - 2 +nRCAS_RNO ORCALUT4 C In 0.000 2.849 r - +nRCAS_RNO ORCALUT4 Z Out 0.757 3.606 f - +N_46_i Net - - - - 1 +nRCAS FD1S3AY D In 0.000 3.606 f - +======================================================================================== Path information for path number 2: @@ -864,24 +860,24 @@ Path information for path number 2: = Slack (non-critical) : -3.609 Number of logic level(s): 2 - Starting point: CBR / Q - Ending point: nRowColSel / D + Starting point: CBR_fast / Q + Ending point: nRWE / D The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------- -CBR FD1S3AX Q Out 1.660 1.660 r - -CBR Net - - - - 5 -nRowColSel_0_0_a3_0 ORCALUT4 B In 0.000 1.660 r - -nRowColSel_0_0_a3_0 ORCALUT4 Z Out 1.189 2.849 f - -N_179 Net - - - - 1 -nRowColSel_0_0 ORCALUT4 B In 0.000 2.849 f - -nRowColSel_0_0 ORCALUT4 Z Out 0.757 3.606 f - -nRowColSel_0_0 Net - - - - 1 -nRowColSel FD1S3IX D In 0.000 3.606 f - -====================================================================================== +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +---------------------------------------------------------------------------------------- +CBR_fast FD1S3AX Q Out 1.552 1.552 r - +CBR_fast Net - - - - 3 +nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 A In 0.000 1.552 r - +nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 Z Out 1.297 2.849 r - +nRCAS_0_sqmuxa_1 Net - - - - 2 +nRWE_RNO ORCALUT4 C In 0.000 2.849 r - +nRWE_RNO ORCALUT4 Z Out 0.757 3.606 r - +N_144_i Net - - - - 1 +nRWE FD1S3AY D In 0.000 3.606 r - +======================================================================================== Path information for path number 3: @@ -890,29 +886,29 @@ Path information for path number 3: + Clock delay at ending point: 0.000 (ideal) = Required time: -0.003 - - Propagation time: 3.510 + - Propagation time: 3.558 - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : -3.513 + = Slack (non-critical) : -3.561 Number of logic level(s): 2 - Starting point: CBR_fast / Q + Starting point: CBR / Q Ending point: nRCAS / D The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------- -CBR_fast FD1S3AX Q Out 1.456 1.456 r - -CBR_fast Net - - - - 2 -nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 A In 0.000 1.456 r - -nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 Z Out 1.297 2.753 r - -nRCAS_0_sqmuxa_1 Net - - - - 2 -nRCAS_RNO ORCALUT4 B In 0.000 2.753 r - -nRCAS_RNO ORCALUT4 Z Out 0.757 3.510 f - -N_37_i Net - - - - 1 -nRCAS FD1S3AY D In 0.000 3.510 f - -======================================================================================== +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------- +CBR FD1S3AX Q Out 1.612 1.612 r - +CBR Net - - - - 4 +nRCAS_RNO_1 ORCALUT4 A In 0.000 1.612 r - +nRCAS_RNO_1 ORCALUT4 Z Out 1.189 2.801 f - +G_1_1 Net - - - - 1 +nRCAS_RNO ORCALUT4 B In 0.000 2.801 f - +nRCAS_RNO ORCALUT4 Z Out 0.757 3.558 r - +N_46_i Net - - - - 1 +nRCAS FD1S3AY D In 0.000 3.558 r - +================================================================================= @@ -920,10 +916,10 @@ nRCAS FD1S3AY D In 0.000 3.510 f - Timing exceptions that could not be applied -Finished final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 195MB peak: 196MB) +Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 196MB peak: 197MB) -Finished timing report (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 195MB peak: 196MB) +Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 196MB peak: 197MB) --------------------------------------- Resource Usage Report @@ -944,18 +940,18 @@ FD1S3IX: 14 FD1S3JX: 3 GSR: 1 IB: 26 -INV: 8 +INV: 7 OB: 33 -ORCALUT4: 119 -PFUMX: 2 +ORCALUT4: 133 +PFUMX: 1 PUR: 1 VHI: 1 VLO: 1 Mapper successful! -At Mapper Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 80MB peak: 196MB) +At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 78MB peak: 197MB) -Process took 0h:00m:05s realtime, 0h:00m:04s cputime -# Thu Sep 21 05:38:27 2023 +Process took 0h:00m:03s realtime, 0h:00m:03s cputime +# Sat Jan 6 06:24:55 2024 ###########################################################] diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.tw1 b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.tw1 index 54b6ebf..227bbf9 100644 --- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.tw1 +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.tw1 @@ -13,7 +13,7 @@ Setup and Hold Report -------------------------------------------------------------------------------- Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 -Thu Sep 21 05:38:30 2023 +Sat Jan 06 06:24:59 2024 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -38,46 +38,48 @@ BLOCK RESETPATHS ================================================================================ Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ; - 129 items scored, 0 timing errors detected. + 168 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- -Passed: The following path meets requirements by 162.619ns (weighted slack = 325.238ns) +Passed: The following path meets requirements by 160.807ns (weighted slack = 321.614ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank[2] (from PHI2_c +) - Destination: FF Data in CmdSubmitted (to PHI2_c -) + Source: FF Q Bank[6] (from PHI2_c +) + Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 9.621ns (25.1% logic, 74.9% route), 6 logic levels. + Delay: 11.433ns (24.4% logic, 75.6% route), 7 logic levels. Constraint Details: - 9.621ns physical path delay SLICE_71 to SLICE_22 meets + 11.433ns physical path delay SLICE_75 to SLICE_20 meets 172.414ns delay constraint less - 0.174ns DIN_SET requirement (totaling 172.240ns) by 162.619ns + 0.174ns DIN_SET requirement (totaling 172.240ns) by 160.807ns Physical Path Details: - Data path SLICE_71 to SLICE_22: + Data path SLICE_75 to SLICE_20: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 SLICE_71.CLK to SLICE_71.Q0 SLICE_71 (from PHI2_c) -ROUTE 1 e 1.441 SLICE_71.Q0 to SLICE_56.A1 Bank[2] -CTOF_DEL --- 0.371 SLICE_56.A1 to SLICE_56.F1 SLICE_56 -ROUTE 1 e 1.441 SLICE_56.F1 to SLICE_70.D1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 SLICE_70.D1 to SLICE_70.F1 SLICE_70 -ROUTE 6 e 1.441 SLICE_70.F1 to SLICE_67.D0 N_147 -CTOF_DEL --- 0.371 SLICE_67.D0 to SLICE_67.F0 SLICE_67 -ROUTE 5 e 1.441 SLICE_67.F0 to SLICE_82.A0 XOR8MEG18 -CTOF_DEL --- 0.371 SLICE_82.A0 to SLICE_82.F0 SLICE_82 -ROUTE 1 e 1.441 SLICE_82.F0 to SLICE_22.A0 CmdSubmitted_1_sqmuxa -CTOF_DEL --- 0.371 SLICE_22.A0 to SLICE_22.F0 SLICE_22 -ROUTE 1 e 0.001 SLICE_22.F0 to SLICE_22.DI0 N_460_0 (to PHI2_c) +REG_DEL --- 0.560 SLICE_75.CLK to SLICE_75.Q0 SLICE_75 (from PHI2_c) +ROUTE 1 e 1.441 SLICE_75.Q0 to SLICE_77.C1 Bank[6] +CTOF_DEL --- 0.371 SLICE_77.C1 to SLICE_77.F1 SLICE_77 +ROUTE 2 e 1.441 SLICE_77.F1 to SLICE_79.D0 un1_Bank_1_5 +CTOF_DEL --- 0.371 SLICE_79.D0 to SLICE_79.F0 SLICE_79 +ROUTE 2 e 1.441 SLICE_79.F0 to SLICE_76.B0 C1WR_7 +CTOF_DEL --- 0.371 SLICE_76.B0 to SLICE_76.F0 SLICE_76 +ROUTE 5 e 1.441 SLICE_76.F0 to SLICE_70.B0 C1WR +CTOF_DEL --- 0.371 SLICE_70.B0 to SLICE_70.F0 SLICE_70 +ROUTE 1 e 1.441 SLICE_70.F0 to SLICE_14.C1 N_121 +CTOF_DEL --- 0.371 SLICE_14.C1 to SLICE_14.F1 SLICE_14 +ROUTE 1 e 1.441 SLICE_14.F1 to SLICE_20.C0 un1_CmdEnable20_i +CTOF_DEL --- 0.371 SLICE_20.C0 to SLICE_20.F0 SLICE_20 +ROUTE 1 e 0.001 SLICE_20.F0 to SLICE_20.DI0 CmdEnable_s (to PHI2_c) -------- - 9.621 (25.1% logic, 74.9% route), 6 logic levels. + 11.433 (24.4% logic, 75.6% route), 7 logic levels. -Report: 51.046MHz is the maximum frequency for this preference. +Report: 43.077MHz is the maximum frequency for this preference. ================================================================================ @@ -118,46 +120,46 @@ Report: 400.000MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; - 388 items scored, 0 timing errors detected. + 392 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- -Passed: The following path meets requirements by 4.695ns +Passed: The following path meets requirements by 6.198ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[17] (from RCLK_c +) - Destination: FF Data in LEDEN (to RCLK_c +) + Destination: FF Data in UFMSDI (to RCLK_c +) - Delay: 11.061ns (21.8% logic, 78.2% route), 6 logic levels. + Delay: 9.621ns (25.1% logic, 74.9% route), 6 logic levels. Constraint Details: - 11.061ns physical path delay SLICE_1 to SLICE_33 meets + 9.621ns physical path delay SLICE_1 to SLICE_52 meets 16.000ns delay constraint less - 0.244ns CE_SET requirement (totaling 15.756ns) by 4.695ns + 0.181ns DIN_SET requirement (totaling 15.819ns) by 6.198ns Physical Path Details: - Data path SLICE_1 to SLICE_33: + Data path SLICE_1 to SLICE_52: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.560 SLICE_1.CLK to SLICE_1.Q1 SLICE_1 (from RCLK_c) -ROUTE 3 e 1.441 SLICE_1.Q1 to SLICE_81.D1 FS[17] -CTOF_DEL --- 0.371 SLICE_81.D1 to SLICE_81.F1 SLICE_81 -ROUTE 1 e 1.441 SLICE_81.F1 to SLICE_72.C1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 SLICE_72.C1 to SLICE_72.F1 SLICE_72 -ROUTE 4 e 1.441 SLICE_72.F1 to SLICE_58.C1 N_51 +ROUTE 3 e 1.441 SLICE_1.Q1 to SLICE_86.D1 FS[17] +CTOF_DEL --- 0.371 SLICE_86.D1 to SLICE_86.F1 SLICE_86 +ROUTE 1 e 1.441 SLICE_86.F1 to SLICE_69.C1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.371 SLICE_69.C1 to SLICE_69.F1 SLICE_69 +ROUTE 4 e 1.441 SLICE_69.F1 to SLICE_58.C1 N_128 CTOF_DEL --- 0.371 SLICE_58.C1 to SLICE_58.F1 SLICE_58 -ROUTE 2 e 1.441 SLICE_58.F1 to SLICE_87.D0 N_151 -CTOF_DEL --- 0.371 SLICE_87.D0 to SLICE_87.F0 SLICE_87 -ROUTE 2 e 1.441 SLICE_87.F0 to SLICE_69.C0 N_137_8 -CTOF_DEL --- 0.371 SLICE_69.C0 to SLICE_69.F0 SLICE_69 -ROUTE 1 e 1.441 SLICE_69.F0 to SLICE_33.CE N_33 (to RCLK_c) +ROUTE 3 e 1.441 SLICE_58.F1 to SLICE_55.C0 N_94 +CTOF_DEL --- 0.371 SLICE_55.C0 to SLICE_55.F0 SLICE_55 +ROUTE 1 e 1.441 SLICE_55.F0 to SLICE_52.D0 UFMSDI_r_xx_mm_1 +CTOF_DEL --- 0.371 SLICE_52.D0 to SLICE_52.F0 SLICE_52 +ROUTE 1 e 0.001 SLICE_52.F0 to SLICE_52.DI0 UFMSDI_RNO (to RCLK_c) -------- - 11.061 (21.8% logic, 78.2% route), 6 logic levels. + 9.621 (25.1% logic, 74.9% route), 6 logic levels. -Report: 88.456MHz is the maximum frequency for this preference. +Report: 102.020MHz is the maximum frequency for this preference. Report Summary -------------- @@ -165,13 +167,13 @@ Report Summary Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | -FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 51.046 MHz| 6 +FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 43.077 MHz| 7 | | | FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 400.000 MHz| 0 | | | FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 400.000 MHz| 0 | | | -FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 88.456 MHz| 6 +FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 102.020 MHz| 6 | | | ---------------------------------------------------------------------------- @@ -226,11 +228,11 @@ Timing summary (Setup): Timing errors: 0 Score: 0 Cumulative negative slack: 0 -Constraints cover 517 paths, 4 nets, and 395 connections (62.40% coverage) +Constraints cover 560 paths, 4 nets, and 424 connections (62.26% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 -Thu Sep 21 05:38:30 2023 +Sat Jan 06 06:24:59 2024 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -255,7 +257,7 @@ BLOCK RESETPATHS ================================================================================ Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ; - 129 items scored, 0 timing errors detected. + 168 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- @@ -301,7 +303,7 @@ Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ; ================================================================================ Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; - 388 items scored, 0 timing errors detected. + 392 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- @@ -316,17 +318,17 @@ Passed: The following path meets requirements by 0.342ns Constraint Details: - 0.325ns physical path delay SLICE_75 to SLICE_75 meets + 0.325ns physical path delay SLICE_74 to SLICE_74 meets -0.017ns M_HLD and 0.000ns delay constraint requirement (totaling -0.017ns) by 0.342ns Physical Path Details: - Data path SLICE_75 to SLICE_75: + Data path SLICE_74 to SLICE_74: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.126 SLICE_75.CLK to SLICE_75.Q0 SLICE_75 (from RCLK_c) -ROUTE 1 e 0.199 SLICE_75.Q0 to SLICE_75.M1 CASr (to RCLK_c) +REG_DEL --- 0.126 SLICE_74.CLK to SLICE_74.Q0 SLICE_74 (from RCLK_c) +ROUTE 1 e 0.199 SLICE_74.Q0 to SLICE_74.M1 CASr (to RCLK_c) -------- 0.325 (38.8% logic, 61.2% route), 1 logic levels. @@ -397,7 +399,7 @@ Timing summary (Hold): Timing errors: 0 Score: 0 Cumulative negative slack: 0 -Constraints cover 517 paths, 4 nets, and 395 connections (62.40% coverage) +Constraints cover 560 paths, 4 nets, and 424 connections (62.26% coverage) diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.twr b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.twr index b41df39..e0a400b 100644 --- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.twr +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.twr @@ -13,7 +13,7 @@ Setup and Hold Report -------------------------------------------------------------------------------- Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 -Thu Sep 21 05:38:43 2023 +Sat Jan 06 06:25:12 2024 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -38,528 +38,557 @@ BLOCK RESETPATHS ================================================================================ Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ; - 129 items scored, 0 timing errors detected. + 168 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- -Passed: The following path meets requirements by 163.490ns (weighted slack = 326.980ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank[2] (from PHI2_c +) - Destination: FF Data in CmdSubmitted (to PHI2_c -) - - Delay: 8.750ns (27.6% logic, 72.4% route), 6 logic levels. - - Constraint Details: - - 8.750ns physical path delay SLICE_71 to SLICE_22 meets - 172.414ns delay constraint less - 0.000ns skew and - 0.174ns DIN_SET requirement (totaling 172.240ns) by 163.490ns - - Physical Path Details: - - Data path SLICE_71 to SLICE_22: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R6C2C.CLK to R6C2C.Q0 SLICE_71 (from PHI2_c) -ROUTE 1 1.583 R6C2C.Q0 to R4C5A.A1 Bank[2] -CTOF_DEL --- 0.371 R4C5A.A1 to R4C5A.F1 SLICE_56 -ROUTE 1 1.643 R4C5A.F1 to R5C2C.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R5C2C.B1 to R5C2C.F1 SLICE_70 -ROUTE 6 1.075 R5C2C.F1 to R5C3A.A0 N_147 -CTOF_DEL --- 0.371 R5C3A.A0 to R5C3A.F0 SLICE_67 -ROUTE 5 1.215 R5C3A.F0 to R6C4D.D0 XOR8MEG18 -CTOF_DEL --- 0.371 R6C4D.D0 to R6C4D.F0 SLICE_82 -ROUTE 1 0.819 R6C4D.F0 to R6C4A.C0 CmdSubmitted_1_sqmuxa -CTOF_DEL --- 0.371 R6C4A.C0 to R6C4A.F0 SLICE_22 -ROUTE 1 0.000 R6C4A.F0 to R6C4A.DI0 N_460_0 (to PHI2_c) - -------- - 8.750 (27.6% logic, 72.4% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_71: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.919 39.PADDI to R6C2C.CLK PHI2_c - -------- - 3.919 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_22: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.919 39.PADDI to R6C4A.CLK PHI2_c - -------- - 3.919 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 163.526ns (weighted slack = 327.052ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank[5] (from PHI2_c +) - Destination: FF Data in CmdSubmitted (to PHI2_c -) - - Delay: 8.714ns (27.7% logic, 72.3% route), 6 logic levels. - - Constraint Details: - - 8.714ns physical path delay SLICE_76 to SLICE_22 meets - 172.414ns delay constraint less - 0.000ns skew and - 0.174ns DIN_SET requirement (totaling 172.240ns) by 163.526ns - - Physical Path Details: - - Data path SLICE_76 to SLICE_22: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R6C3D.CLK to R6C3D.Q1 SLICE_76 (from PHI2_c) -ROUTE 1 1.547 R6C3D.Q1 to R4C5A.B1 Bank[5] -CTOF_DEL --- 0.371 R4C5A.B1 to R4C5A.F1 SLICE_56 -ROUTE 1 1.643 R4C5A.F1 to R5C2C.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R5C2C.B1 to R5C2C.F1 SLICE_70 -ROUTE 6 1.075 R5C2C.F1 to R5C3A.A0 N_147 -CTOF_DEL --- 0.371 R5C3A.A0 to R5C3A.F0 SLICE_67 -ROUTE 5 1.215 R5C3A.F0 to R6C4D.D0 XOR8MEG18 -CTOF_DEL --- 0.371 R6C4D.D0 to R6C4D.F0 SLICE_82 -ROUTE 1 0.819 R6C4D.F0 to R6C4A.C0 CmdSubmitted_1_sqmuxa -CTOF_DEL --- 0.371 R6C4A.C0 to R6C4A.F0 SLICE_22 -ROUTE 1 0.000 R6C4A.F0 to R6C4A.DI0 N_460_0 (to PHI2_c) - -------- - 8.714 (27.7% logic, 72.3% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_76: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.919 39.PADDI to R6C3D.CLK PHI2_c - -------- - 3.919 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_22: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.919 39.PADDI to R6C4A.CLK PHI2_c - -------- - 3.919 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 163.560ns (weighted slack = 327.120ns) +Passed: The following path meets requirements by 161.825ns (weighted slack = 323.650ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Bank[7] (from PHI2_c +) - Destination: FF Data in CmdSubmitted (to PHI2_c -) - - Delay: 8.680ns (27.8% logic, 72.2% route), 6 logic levels. - - Constraint Details: - - 8.680ns physical path delay SLICE_77 to SLICE_22 meets - 172.414ns delay constraint less - 0.000ns skew and - 0.174ns DIN_SET requirement (totaling 172.240ns) by 163.560ns - - Physical Path Details: - - Data path SLICE_77 to SLICE_22: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R6C3A.CLK to R6C3A.Q1 SLICE_77 (from PHI2_c) -ROUTE 1 1.513 R6C3A.Q1 to R4C5A.D1 Bank[7] -CTOF_DEL --- 0.371 R4C5A.D1 to R4C5A.F1 SLICE_56 -ROUTE 1 1.643 R4C5A.F1 to R5C2C.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R5C2C.B1 to R5C2C.F1 SLICE_70 -ROUTE 6 1.075 R5C2C.F1 to R5C3A.A0 N_147 -CTOF_DEL --- 0.371 R5C3A.A0 to R5C3A.F0 SLICE_67 -ROUTE 5 1.215 R5C3A.F0 to R6C4D.D0 XOR8MEG18 -CTOF_DEL --- 0.371 R6C4D.D0 to R6C4D.F0 SLICE_82 -ROUTE 1 0.819 R6C4D.F0 to R6C4A.C0 CmdSubmitted_1_sqmuxa -CTOF_DEL --- 0.371 R6C4A.C0 to R6C4A.F0 SLICE_22 -ROUTE 1 0.000 R6C4A.F0 to R6C4A.DI0 N_460_0 (to PHI2_c) - -------- - 8.680 (27.8% logic, 72.2% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_77: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.919 39.PADDI to R6C3A.CLK PHI2_c - -------- - 3.919 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_22: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.919 39.PADDI to R6C4A.CLK PHI2_c - -------- - 3.919 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 163.688ns (weighted slack = 327.376ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank[2] (from PHI2_c +) Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 8.552ns (26.9% logic, 73.1% route), 5 logic levels. + Delay: 10.415ns (26.7% logic, 73.3% route), 7 logic levels. Constraint Details: - 8.552ns physical path delay SLICE_71 to SLICE_20 meets + 10.415ns physical path delay SLICE_75 to SLICE_20 meets 172.414ns delay constraint less 0.000ns skew and - 0.174ns DIN_SET requirement (totaling 172.240ns) by 163.688ns + 0.174ns DIN_SET requirement (totaling 172.240ns) by 161.825ns Physical Path Details: - Data path SLICE_71 to SLICE_20: + Data path SLICE_75 to SLICE_20: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R6C2C.CLK to R6C2C.Q0 SLICE_71 (from PHI2_c) -ROUTE 1 1.583 R6C2C.Q0 to R4C5A.A1 Bank[2] -CTOF_DEL --- 0.371 R4C5A.A1 to R4C5A.F1 SLICE_56 -ROUTE 1 1.643 R4C5A.F1 to R5C2C.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R5C2C.B1 to R5C2C.F1 SLICE_70 -ROUTE 6 1.578 R5C2C.F1 to R2C2B.B1 N_147 -CTOF_DEL --- 0.371 R2C2B.B1 to R2C2B.F1 SLICE_90 -ROUTE 1 1.444 R2C2B.F1 to R5C3D.C0 un1_CMDWR -CTOOFX_DEL --- 0.631 R5C3D.C0 to R5C3D.OFX0 SLICE_20 -ROUTE 1 0.000 R5C3D.OFX0 to R5C3D.DI0 CmdEnable_s (to PHI2_c) +REG_DEL --- 0.560 R5C3D.CLK to R5C3D.Q1 SLICE_75 (from PHI2_c) +ROUTE 1 2.039 R5C3D.Q1 to R5C2D.B1 Bank[7] +CTOF_DEL --- 0.371 R5C2D.B1 to R5C2D.F1 SLICE_77 +ROUTE 2 0.835 R5C2D.F1 to R5C2B.C0 un1_Bank_1_5 +CTOF_DEL --- 0.371 R5C2B.C0 to R5C2B.F0 SLICE_79 +ROUTE 2 1.092 R5C2B.F0 to R6C2C.B0 C1WR_7 +CTOF_DEL --- 0.371 R6C2C.B0 to R6C2C.F0 SLICE_76 +ROUTE 5 1.529 R6C2C.F0 to R5C3D.A0 C1WR +CTOF_DEL --- 0.371 R5C3D.A0 to R5C3D.F0 SLICE_75 +ROUTE 3 1.108 R5C3D.F0 to R6C3A.B1 CmdEnable16 +CTOF_DEL --- 0.371 R6C3A.B1 to R6C3A.F1 SLICE_14 +ROUTE 1 1.026 R6C3A.F1 to R5C3C.A0 un1_CmdEnable20_i +CTOF_DEL --- 0.371 R5C3C.A0 to R5C3C.F0 SLICE_20 +ROUTE 1 0.000 R5C3C.F0 to R5C3C.DI0 CmdEnable_s (to PHI2_c) -------- - 8.552 (26.9% logic, 73.1% route), 5 logic levels. + 10.415 (26.7% logic, 73.3% route), 7 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_71: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.919 39.PADDI to R6C2C.CLK PHI2_c - -------- - 3.919 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_20: + Source Clock Path PHI2 to SLICE_75: Name Fanout Delay (ns) Site Resource ROUTE 15 3.919 39.PADDI to R5C3D.CLK PHI2_c -------- 3.919 (0.0% logic, 100.0% route), 0 logic levels. + Destination Clock Path PHI2 to SLICE_20: -Passed: The following path meets requirements by 163.724ns (weighted slack = 327.448ns) + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.919 39.PADDI to R5C3C.CLK PHI2_c + -------- + 3.919 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.064ns (weighted slack = 324.128ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank[5] (from PHI2_c +) - Destination: FF Data in CmdEnable (to PHI2_c -) + Source: FF Q Bank[7] (from PHI2_c +) + Destination: FF Data in CmdSubmitted (to PHI2_c -) - Delay: 8.516ns (27.1% logic, 72.9% route), 5 logic levels. + Delay: 10.176ns (27.4% logic, 72.6% route), 7 logic levels. Constraint Details: - 8.516ns physical path delay SLICE_76 to SLICE_20 meets + 10.176ns physical path delay SLICE_75 to SLICE_22 meets 172.414ns delay constraint less 0.000ns skew and - 0.174ns DIN_SET requirement (totaling 172.240ns) by 163.724ns + 0.174ns DIN_SET requirement (totaling 172.240ns) by 162.064ns + + Physical Path Details: + + Data path SLICE_75 to SLICE_22: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R5C3D.CLK to R5C3D.Q1 SLICE_75 (from PHI2_c) +ROUTE 1 2.039 R5C3D.Q1 to R5C2D.B1 Bank[7] +CTOF_DEL --- 0.371 R5C2D.B1 to R5C2D.F1 SLICE_77 +ROUTE 2 0.835 R5C2D.F1 to R5C2B.C0 un1_Bank_1_5 +CTOF_DEL --- 0.371 R5C2B.C0 to R5C2B.F0 SLICE_79 +ROUTE 2 0.893 R5C2B.F0 to R6C2B.C1 C1WR_7 +CTOF_DEL --- 0.371 R6C2B.C1 to R6C2B.F1 SLICE_70 +ROUTE 2 1.563 R6C2B.F1 to R5C3B.B0 CMDWR +CTOF_DEL --- 0.371 R5C3B.B0 to R5C3B.F0 SLICE_73 +ROUTE 5 0.513 R5C3B.F0 to R5C3B.C1 XOR8MEG18 +CTOF_DEL --- 0.371 R5C3B.C1 to R5C3B.F1 SLICE_73 +ROUTE 1 1.547 R5C3B.F1 to R6C5C.B0 CmdSubmitted_1_sqmuxa +CTOF_DEL --- 0.371 R6C5C.B0 to R6C5C.F0 SLICE_22 +ROUTE 1 0.000 R6C5C.F0 to R6C5C.DI0 N_428_0 (to PHI2_c) + -------- + 10.176 (27.4% logic, 72.6% route), 7 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_75: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.919 39.PADDI to R5C3D.CLK PHI2_c + -------- + 3.919 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_22: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.919 39.PADDI to R6C5C.CLK PHI2_c + -------- + 3.919 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.564ns (weighted slack = 325.128ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank[7] (from PHI2_c +) + Destination: FF Data in CmdUFMCS (to PHI2_c -) + FF CmdUFMCLK + + Delay: 9.585ns (25.2% logic, 74.8% route), 6 logic levels. + + Constraint Details: + + 9.585ns physical path delay SLICE_75 to SLICE_85 meets + 172.414ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 172.149ns) by 162.564ns + + Physical Path Details: + + Data path SLICE_75 to SLICE_85: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R5C3D.CLK to R5C3D.Q1 SLICE_75 (from PHI2_c) +ROUTE 1 2.039 R5C3D.Q1 to R5C2D.B1 Bank[7] +CTOF_DEL --- 0.371 R5C2D.B1 to R5C2D.F1 SLICE_77 +ROUTE 2 0.835 R5C2D.F1 to R5C2B.C0 un1_Bank_1_5 +CTOF_DEL --- 0.371 R5C2B.C0 to R5C2B.F0 SLICE_79 +ROUTE 2 0.893 R5C2B.F0 to R6C2B.C1 C1WR_7 +CTOF_DEL --- 0.371 R6C2B.C1 to R6C2B.F1 SLICE_70 +ROUTE 2 1.563 R6C2B.F1 to R5C3B.B0 CMDWR +CTOF_DEL --- 0.371 R5C3B.B0 to R5C3B.F0 SLICE_73 +ROUTE 5 1.185 R5C3B.F0 to R6C4A.D1 XOR8MEG18 +CTOF_DEL --- 0.371 R6C4A.D1 to R6C4A.F1 SLICE_85 +ROUTE 2 0.655 R6C4A.F1 to R6C4A.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) + -------- + 9.585 (25.2% logic, 74.8% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_75: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.919 39.PADDI to R5C3D.CLK PHI2_c + -------- + 3.919 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_85: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.919 39.PADDI to R6C4A.CLK PHI2_c + -------- + 3.919 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.564ns (weighted slack = 325.128ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank[7] (from PHI2_c +) + Destination: FF Data in CmdUFMSDI (to PHI2_c -) + + Delay: 9.585ns (25.2% logic, 74.8% route), 6 logic levels. + + Constraint Details: + + 9.585ns physical path delay SLICE_75 to SLICE_88 meets + 172.414ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 172.149ns) by 162.564ns + + Physical Path Details: + + Data path SLICE_75 to SLICE_88: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R5C3D.CLK to R5C3D.Q1 SLICE_75 (from PHI2_c) +ROUTE 1 2.039 R5C3D.Q1 to R5C2D.B1 Bank[7] +CTOF_DEL --- 0.371 R5C2D.B1 to R5C2D.F1 SLICE_77 +ROUTE 2 0.835 R5C2D.F1 to R5C2B.C0 un1_Bank_1_5 +CTOF_DEL --- 0.371 R5C2B.C0 to R5C2B.F0 SLICE_79 +ROUTE 2 0.893 R5C2B.F0 to R6C2B.C1 C1WR_7 +CTOF_DEL --- 0.371 R6C2B.C1 to R6C2B.F1 SLICE_70 +ROUTE 2 1.563 R6C2B.F1 to R5C3B.B0 CMDWR +CTOF_DEL --- 0.371 R5C3B.B0 to R5C3B.F0 SLICE_73 +ROUTE 5 1.185 R5C3B.F0 to R6C4A.D1 XOR8MEG18 +CTOF_DEL --- 0.371 R6C4A.D1 to R6C4A.F1 SLICE_85 +ROUTE 2 0.655 R6C4A.F1 to R6C4B.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) + -------- + 9.585 (25.2% logic, 74.8% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_75: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.919 39.PADDI to R5C3D.CLK PHI2_c + -------- + 3.919 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_88: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.919 39.PADDI to R6C4B.CLK PHI2_c + -------- + 3.919 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.699ns (weighted slack = 325.398ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank[1] (from PHI2_c +) + Destination: FF Data in CmdEnable (to PHI2_c -) + + Delay: 9.541ns (29.2% logic, 70.8% route), 7 logic levels. + + Constraint Details: + + 9.541ns physical path delay SLICE_76 to SLICE_20 meets + 172.414ns delay constraint less + 0.000ns skew and + 0.174ns DIN_SET requirement (totaling 172.240ns) by 162.699ns Physical Path Details: Data path SLICE_76 to SLICE_20: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R6C3D.CLK to R6C3D.Q1 SLICE_76 (from PHI2_c) -ROUTE 1 1.547 R6C3D.Q1 to R4C5A.B1 Bank[5] -CTOF_DEL --- 0.371 R4C5A.B1 to R4C5A.F1 SLICE_56 -ROUTE 1 1.643 R4C5A.F1 to R5C2C.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R5C2C.B1 to R5C2C.F1 SLICE_70 -ROUTE 6 1.578 R5C2C.F1 to R2C2B.B1 N_147 -CTOF_DEL --- 0.371 R2C2B.B1 to R2C2B.F1 SLICE_90 -ROUTE 1 1.444 R2C2B.F1 to R5C3D.C0 un1_CMDWR -CTOOFX_DEL --- 0.631 R5C3D.C0 to R5C3D.OFX0 SLICE_20 -ROUTE 1 0.000 R5C3D.OFX0 to R5C3D.DI0 CmdEnable_s (to PHI2_c) +REG_DEL --- 0.560 R6C2C.CLK to R6C2C.Q1 SLICE_76 (from PHI2_c) +ROUTE 1 1.026 R6C2C.Q1 to R5C2A.A0 Bank[1] +CTOF_DEL --- 0.371 R5C2A.A0 to R5C2A.F0 SLICE_100 +ROUTE 2 0.974 R5C2A.F0 to R5C2B.A0 un1_Bank_1_4 +CTOF_DEL --- 0.371 R5C2B.A0 to R5C2B.F0 SLICE_79 +ROUTE 2 1.092 R5C2B.F0 to R6C2C.B0 C1WR_7 +CTOF_DEL --- 0.371 R6C2C.B0 to R6C2C.F0 SLICE_76 +ROUTE 5 1.529 R6C2C.F0 to R5C3D.A0 C1WR +CTOF_DEL --- 0.371 R5C3D.A0 to R5C3D.F0 SLICE_75 +ROUTE 3 1.108 R5C3D.F0 to R6C3A.B1 CmdEnable16 +CTOF_DEL --- 0.371 R6C3A.B1 to R6C3A.F1 SLICE_14 +ROUTE 1 1.026 R6C3A.F1 to R5C3C.A0 un1_CmdEnable20_i +CTOF_DEL --- 0.371 R5C3C.A0 to R5C3C.F0 SLICE_20 +ROUTE 1 0.000 R5C3C.F0 to R5C3C.DI0 CmdEnable_s (to PHI2_c) -------- - 8.516 (27.1% logic, 72.9% route), 5 logic levels. + 9.541 (29.2% logic, 70.8% route), 7 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_76: - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.919 39.PADDI to R6C3D.CLK PHI2_c - -------- - 3.919 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.919 39.PADDI to R5C3D.CLK PHI2_c - -------- - 3.919 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 163.725ns (weighted slack = 327.450ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank[6] (from PHI2_c +) - Destination: FF Data in CmdSubmitted (to PHI2_c -) - - Delay: 8.515ns (28.4% logic, 71.6% route), 6 logic levels. - - Constraint Details: - - 8.515ns physical path delay SLICE_77 to SLICE_22 meets - 172.414ns delay constraint less - 0.000ns skew and - 0.174ns DIN_SET requirement (totaling 172.240ns) by 163.725ns - - Physical Path Details: - - Data path SLICE_77 to SLICE_22: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R6C3A.CLK to R6C3A.Q0 SLICE_77 (from PHI2_c) -ROUTE 1 1.348 R6C3A.Q0 to R4C5A.C1 Bank[6] -CTOF_DEL --- 0.371 R4C5A.C1 to R4C5A.F1 SLICE_56 -ROUTE 1 1.643 R4C5A.F1 to R5C2C.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R5C2C.B1 to R5C2C.F1 SLICE_70 -ROUTE 6 1.075 R5C2C.F1 to R5C3A.A0 N_147 -CTOF_DEL --- 0.371 R5C3A.A0 to R5C3A.F0 SLICE_67 -ROUTE 5 1.215 R5C3A.F0 to R6C4D.D0 XOR8MEG18 -CTOF_DEL --- 0.371 R6C4D.D0 to R6C4D.F0 SLICE_82 -ROUTE 1 0.819 R6C4D.F0 to R6C4A.C0 CmdSubmitted_1_sqmuxa -CTOF_DEL --- 0.371 R6C4A.C0 to R6C4A.F0 SLICE_22 -ROUTE 1 0.000 R6C4A.F0 to R6C4A.DI0 N_460_0 (to PHI2_c) - -------- - 8.515 (28.4% logic, 71.6% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_77: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.919 39.PADDI to R6C3A.CLK PHI2_c - -------- - 3.919 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_22: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.919 39.PADDI to R6C4A.CLK PHI2_c - -------- - 3.919 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 163.758ns (weighted slack = 327.516ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank[7] (from PHI2_c +) - Destination: FF Data in CmdEnable (to PHI2_c -) - - Delay: 8.482ns (27.2% logic, 72.8% route), 5 logic levels. - - Constraint Details: - - 8.482ns physical path delay SLICE_77 to SLICE_20 meets - 172.414ns delay constraint less - 0.000ns skew and - 0.174ns DIN_SET requirement (totaling 172.240ns) by 163.758ns - - Physical Path Details: - - Data path SLICE_77 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R6C3A.CLK to R6C3A.Q1 SLICE_77 (from PHI2_c) -ROUTE 1 1.513 R6C3A.Q1 to R4C5A.D1 Bank[7] -CTOF_DEL --- 0.371 R4C5A.D1 to R4C5A.F1 SLICE_56 -ROUTE 1 1.643 R4C5A.F1 to R5C2C.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R5C2C.B1 to R5C2C.F1 SLICE_70 -ROUTE 6 1.578 R5C2C.F1 to R2C2B.B1 N_147 -CTOF_DEL --- 0.371 R2C2B.B1 to R2C2B.F1 SLICE_90 -ROUTE 1 1.444 R2C2B.F1 to R5C3D.C0 un1_CMDWR -CTOOFX_DEL --- 0.631 R5C3D.C0 to R5C3D.OFX0 SLICE_20 -ROUTE 1 0.000 R5C3D.OFX0 to R5C3D.DI0 CmdEnable_s (to PHI2_c) - -------- - 8.482 (27.2% logic, 72.8% route), 5 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_77: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.919 39.PADDI to R6C3A.CLK PHI2_c - -------- - 3.919 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.919 39.PADDI to R5C3D.CLK PHI2_c - -------- - 3.919 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 163.923ns (weighted slack = 327.846ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank[6] (from PHI2_c +) - Destination: FF Data in CmdEnable (to PHI2_c -) - - Delay: 8.317ns (27.7% logic, 72.3% route), 5 logic levels. - - Constraint Details: - - 8.317ns physical path delay SLICE_77 to SLICE_20 meets - 172.414ns delay constraint less - 0.000ns skew and - 0.174ns DIN_SET requirement (totaling 172.240ns) by 163.923ns - - Physical Path Details: - - Data path SLICE_77 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R6C3A.CLK to R6C3A.Q0 SLICE_77 (from PHI2_c) -ROUTE 1 1.348 R6C3A.Q0 to R4C5A.C1 Bank[6] -CTOF_DEL --- 0.371 R4C5A.C1 to R4C5A.F1 SLICE_56 -ROUTE 1 1.643 R4C5A.F1 to R5C2C.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R5C2C.B1 to R5C2C.F1 SLICE_70 -ROUTE 6 1.578 R5C2C.F1 to R2C2B.B1 N_147 -CTOF_DEL --- 0.371 R2C2B.B1 to R2C2B.F1 SLICE_90 -ROUTE 1 1.444 R2C2B.F1 to R5C3D.C0 un1_CMDWR -CTOOFX_DEL --- 0.631 R5C3D.C0 to R5C3D.OFX0 SLICE_20 -ROUTE 1 0.000 R5C3D.OFX0 to R5C3D.DI0 CmdEnable_s (to PHI2_c) - -------- - 8.317 (27.7% logic, 72.3% route), 5 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_77: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.919 39.PADDI to R6C3A.CLK PHI2_c - -------- - 3.919 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.919 39.PADDI to R5C3D.CLK PHI2_c - -------- - 3.919 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 163.952ns (weighted slack = 327.904ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank[2] (from PHI2_c +) - Destination: FF Data in CmdUFMSDI (to PHI2_c -) - - Delay: 8.197ns (24.9% logic, 75.1% route), 5 logic levels. - - Constraint Details: - - 8.197ns physical path delay SLICE_71 to SLICE_74 meets - 172.414ns delay constraint less - 0.000ns skew and - 0.265ns CE_SET requirement (totaling 172.149ns) by 163.952ns - - Physical Path Details: - - Data path SLICE_71 to SLICE_74: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R6C2C.CLK to R6C2C.Q0 SLICE_71 (from PHI2_c) -ROUTE 1 1.583 R6C2C.Q0 to R4C5A.A1 Bank[2] -CTOF_DEL --- 0.371 R4C5A.A1 to R4C5A.F1 SLICE_56 -ROUTE 1 1.643 R4C5A.F1 to R5C2C.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R5C2C.B1 to R5C2C.F1 SLICE_70 -ROUTE 6 1.075 R5C2C.F1 to R5C3A.A0 N_147 -CTOF_DEL --- 0.371 R5C3A.A0 to R5C3A.F0 SLICE_67 -ROUTE 5 0.682 R5C3A.F0 to R5C3A.A1 XOR8MEG18 -CTOF_DEL --- 0.371 R5C3A.A1 to R5C3A.F1 SLICE_67 -ROUTE 2 1.170 R5C3A.F1 to R7C4B.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) - -------- - 8.197 (24.9% logic, 75.1% route), 5 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_71: - Name Fanout Delay (ns) Site Resource ROUTE 15 3.919 39.PADDI to R6C2C.CLK PHI2_c -------- 3.919 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_74: + Destination Clock Path PHI2 to SLICE_20: Name Fanout Delay (ns) Site Resource -ROUTE 15 3.919 39.PADDI to R7C4B.CLK PHI2_c +ROUTE 15 3.919 39.PADDI to R5C3C.CLK PHI2_c -------- 3.919 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 163.988ns (weighted slack = 327.976ns) +Passed: The following path meets requirements by 162.707ns (weighted slack = 325.414ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank[5] (from PHI2_c +) - Destination: FF Data in CmdUFMSDI (to PHI2_c -) + Source: FF Q Bank[3] (from PHI2_c +) + Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 8.161ns (25.0% logic, 75.0% route), 5 logic levels. + Delay: 9.533ns (29.2% logic, 70.8% route), 7 logic levels. Constraint Details: - 8.161ns physical path delay SLICE_76 to SLICE_74 meets + 9.533ns physical path delay SLICE_79 to SLICE_20 meets 172.414ns delay constraint less 0.000ns skew and - 0.265ns CE_SET requirement (totaling 172.149ns) by 163.988ns + 0.174ns DIN_SET requirement (totaling 172.240ns) by 162.707ns Physical Path Details: - Data path SLICE_76 to SLICE_74: + Data path SLICE_79 to SLICE_20: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R6C3D.CLK to R6C3D.Q1 SLICE_76 (from PHI2_c) -ROUTE 1 1.547 R6C3D.Q1 to R4C5A.B1 Bank[5] -CTOF_DEL --- 0.371 R4C5A.B1 to R4C5A.F1 SLICE_56 -ROUTE 1 1.643 R4C5A.F1 to R5C2C.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R5C2C.B1 to R5C2C.F1 SLICE_70 -ROUTE 6 1.075 R5C2C.F1 to R5C3A.A0 N_147 -CTOF_DEL --- 0.371 R5C3A.A0 to R5C3A.F0 SLICE_67 -ROUTE 5 0.682 R5C3A.F0 to R5C3A.A1 XOR8MEG18 -CTOF_DEL --- 0.371 R5C3A.A1 to R5C3A.F1 SLICE_67 -ROUTE 2 1.170 R5C3A.F1 to R7C4B.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) +REG_DEL --- 0.560 R5C2B.CLK to R5C2B.Q1 SLICE_79 (from PHI2_c) +ROUTE 1 1.018 R5C2B.Q1 to R5C2A.B0 Bank[3] +CTOF_DEL --- 0.371 R5C2A.B0 to R5C2A.F0 SLICE_100 +ROUTE 2 0.974 R5C2A.F0 to R5C2B.A0 un1_Bank_1_4 +CTOF_DEL --- 0.371 R5C2B.A0 to R5C2B.F0 SLICE_79 +ROUTE 2 1.092 R5C2B.F0 to R6C2C.B0 C1WR_7 +CTOF_DEL --- 0.371 R6C2C.B0 to R6C2C.F0 SLICE_76 +ROUTE 5 1.529 R6C2C.F0 to R5C3D.A0 C1WR +CTOF_DEL --- 0.371 R5C3D.A0 to R5C3D.F0 SLICE_75 +ROUTE 3 1.108 R5C3D.F0 to R6C3A.B1 CmdEnable16 +CTOF_DEL --- 0.371 R6C3A.B1 to R6C3A.F1 SLICE_14 +ROUTE 1 1.026 R6C3A.F1 to R5C3C.A0 un1_CmdEnable20_i +CTOF_DEL --- 0.371 R5C3C.A0 to R5C3C.F0 SLICE_20 +ROUTE 1 0.000 R5C3C.F0 to R5C3C.DI0 CmdEnable_s (to PHI2_c) -------- - 8.161 (25.0% logic, 75.0% route), 5 logic levels. + 9.533 (29.2% logic, 70.8% route), 7 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_79: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.919 39.PADDI to R5C2B.CLK PHI2_c + -------- + 3.919 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.919 39.PADDI to R5C3C.CLK PHI2_c + -------- + 3.919 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.832ns (weighted slack = 325.664ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank[6] (from PHI2_c +) + Destination: FF Data in CmdEnable (to PHI2_c -) + + Delay: 9.408ns (29.6% logic, 70.4% route), 7 logic levels. + + Constraint Details: + + 9.408ns physical path delay SLICE_75 to SLICE_20 meets + 172.414ns delay constraint less + 0.000ns skew and + 0.174ns DIN_SET requirement (totaling 172.240ns) by 162.832ns + + Physical Path Details: + + Data path SLICE_75 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R5C3D.CLK to R5C3D.Q0 SLICE_75 (from PHI2_c) +ROUTE 1 1.032 R5C3D.Q0 to R5C2D.A1 Bank[6] +CTOF_DEL --- 0.371 R5C2D.A1 to R5C2D.F1 SLICE_77 +ROUTE 2 0.835 R5C2D.F1 to R5C2B.C0 un1_Bank_1_5 +CTOF_DEL --- 0.371 R5C2B.C0 to R5C2B.F0 SLICE_79 +ROUTE 2 1.092 R5C2B.F0 to R6C2C.B0 C1WR_7 +CTOF_DEL --- 0.371 R6C2C.B0 to R6C2C.F0 SLICE_76 +ROUTE 5 1.529 R6C2C.F0 to R5C3D.A0 C1WR +CTOF_DEL --- 0.371 R5C3D.A0 to R5C3D.F0 SLICE_75 +ROUTE 3 1.108 R5C3D.F0 to R6C3A.B1 CmdEnable16 +CTOF_DEL --- 0.371 R6C3A.B1 to R6C3A.F1 SLICE_14 +ROUTE 1 1.026 R6C3A.F1 to R5C3C.A0 un1_CmdEnable20_i +CTOF_DEL --- 0.371 R5C3C.A0 to R5C3C.F0 SLICE_20 +ROUTE 1 0.000 R5C3C.F0 to R5C3C.DI0 CmdEnable_s (to PHI2_c) + -------- + 9.408 (29.6% logic, 70.4% route), 7 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_75: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.919 39.PADDI to R5C3D.CLK PHI2_c + -------- + 3.919 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.919 39.PADDI to R5C3C.CLK PHI2_c + -------- + 3.919 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.838ns (weighted slack = 325.676ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank[4] (from PHI2_c +) + Destination: FF Data in CmdEnable (to PHI2_c -) + + Delay: 9.402ns (29.6% logic, 70.4% route), 7 logic levels. + + Constraint Details: + + 9.402ns physical path delay SLICE_93 to SLICE_20 meets + 172.414ns delay constraint less + 0.000ns skew and + 0.174ns DIN_SET requirement (totaling 172.240ns) by 162.838ns + + Physical Path Details: + + Data path SLICE_93 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R6C2A.CLK to R6C2A.Q0 SLICE_93 (from PHI2_c) +ROUTE 1 0.887 R6C2A.Q0 to R5C2A.C0 Bank[4] +CTOF_DEL --- 0.371 R5C2A.C0 to R5C2A.F0 SLICE_100 +ROUTE 2 0.974 R5C2A.F0 to R5C2B.A0 un1_Bank_1_4 +CTOF_DEL --- 0.371 R5C2B.A0 to R5C2B.F0 SLICE_79 +ROUTE 2 1.092 R5C2B.F0 to R6C2C.B0 C1WR_7 +CTOF_DEL --- 0.371 R6C2C.B0 to R6C2C.F0 SLICE_76 +ROUTE 5 1.529 R6C2C.F0 to R5C3D.A0 C1WR +CTOF_DEL --- 0.371 R5C3D.A0 to R5C3D.F0 SLICE_75 +ROUTE 3 1.108 R5C3D.F0 to R6C3A.B1 CmdEnable16 +CTOF_DEL --- 0.371 R6C3A.B1 to R6C3A.F1 SLICE_14 +ROUTE 1 1.026 R6C3A.F1 to R5C3C.A0 un1_CmdEnable20_i +CTOF_DEL --- 0.371 R5C3C.A0 to R5C3C.F0 SLICE_20 +ROUTE 1 0.000 R5C3C.F0 to R5C3C.DI0 CmdEnable_s (to PHI2_c) + -------- + 9.402 (29.6% logic, 70.4% route), 7 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.919 39.PADDI to R6C2A.CLK PHI2_c + -------- + 3.919 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.919 39.PADDI to R5C3C.CLK PHI2_c + -------- + 3.919 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.938ns (weighted slack = 325.876ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank[1] (from PHI2_c +) + Destination: FF Data in CmdSubmitted (to PHI2_c -) + + Delay: 9.302ns (30.0% logic, 70.0% route), 7 logic levels. + + Constraint Details: + + 9.302ns physical path delay SLICE_76 to SLICE_22 meets + 172.414ns delay constraint less + 0.000ns skew and + 0.174ns DIN_SET requirement (totaling 172.240ns) by 162.938ns + + Physical Path Details: + + Data path SLICE_76 to SLICE_22: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R6C2C.CLK to R6C2C.Q1 SLICE_76 (from PHI2_c) +ROUTE 1 1.026 R6C2C.Q1 to R5C2A.A0 Bank[1] +CTOF_DEL --- 0.371 R5C2A.A0 to R5C2A.F0 SLICE_100 +ROUTE 2 0.974 R5C2A.F0 to R5C2B.A0 un1_Bank_1_4 +CTOF_DEL --- 0.371 R5C2B.A0 to R5C2B.F0 SLICE_79 +ROUTE 2 0.893 R5C2B.F0 to R6C2B.C1 C1WR_7 +CTOF_DEL --- 0.371 R6C2B.C1 to R6C2B.F1 SLICE_70 +ROUTE 2 1.563 R6C2B.F1 to R5C3B.B0 CMDWR +CTOF_DEL --- 0.371 R5C3B.B0 to R5C3B.F0 SLICE_73 +ROUTE 5 0.513 R5C3B.F0 to R5C3B.C1 XOR8MEG18 +CTOF_DEL --- 0.371 R5C3B.C1 to R5C3B.F1 SLICE_73 +ROUTE 1 1.547 R5C3B.F1 to R6C5C.B0 CmdSubmitted_1_sqmuxa +CTOF_DEL --- 0.371 R6C5C.B0 to R6C5C.F0 SLICE_22 +ROUTE 1 0.000 R6C5C.F0 to R6C5C.DI0 N_428_0 (to PHI2_c) + -------- + 9.302 (30.0% logic, 70.0% route), 7 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_76: Name Fanout Delay (ns) Site Resource -ROUTE 15 3.919 39.PADDI to R6C3D.CLK PHI2_c +ROUTE 15 3.919 39.PADDI to R6C2C.CLK PHI2_c -------- 3.919 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_74: + Destination Clock Path PHI2 to SLICE_22: Name Fanout Delay (ns) Site Resource -ROUTE 15 3.919 39.PADDI to R7C4B.CLK PHI2_c +ROUTE 15 3.919 39.PADDI to R6C5C.CLK PHI2_c -------- 3.919 (0.0% logic, 100.0% route), 0 logic levels. -Report: 56.029MHz is the maximum frequency for this preference. + +Passed: The following path meets requirements by 162.946ns (weighted slack = 325.892ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank[3] (from PHI2_c +) + Destination: FF Data in CmdSubmitted (to PHI2_c -) + + Delay: 9.294ns (30.0% logic, 70.0% route), 7 logic levels. + + Constraint Details: + + 9.294ns physical path delay SLICE_79 to SLICE_22 meets + 172.414ns delay constraint less + 0.000ns skew and + 0.174ns DIN_SET requirement (totaling 172.240ns) by 162.946ns + + Physical Path Details: + + Data path SLICE_79 to SLICE_22: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R5C2B.CLK to R5C2B.Q1 SLICE_79 (from PHI2_c) +ROUTE 1 1.018 R5C2B.Q1 to R5C2A.B0 Bank[3] +CTOF_DEL --- 0.371 R5C2A.B0 to R5C2A.F0 SLICE_100 +ROUTE 2 0.974 R5C2A.F0 to R5C2B.A0 un1_Bank_1_4 +CTOF_DEL --- 0.371 R5C2B.A0 to R5C2B.F0 SLICE_79 +ROUTE 2 0.893 R5C2B.F0 to R6C2B.C1 C1WR_7 +CTOF_DEL --- 0.371 R6C2B.C1 to R6C2B.F1 SLICE_70 +ROUTE 2 1.563 R6C2B.F1 to R5C3B.B0 CMDWR +CTOF_DEL --- 0.371 R5C3B.B0 to R5C3B.F0 SLICE_73 +ROUTE 5 0.513 R5C3B.F0 to R5C3B.C1 XOR8MEG18 +CTOF_DEL --- 0.371 R5C3B.C1 to R5C3B.F1 SLICE_73 +ROUTE 1 1.547 R5C3B.F1 to R6C5C.B0 CmdSubmitted_1_sqmuxa +CTOF_DEL --- 0.371 R6C5C.B0 to R6C5C.F0 SLICE_22 +ROUTE 1 0.000 R6C5C.F0 to R6C5C.DI0 N_428_0 (to PHI2_c) + -------- + 9.294 (30.0% logic, 70.0% route), 7 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_79: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.919 39.PADDI to R5C2B.CLK PHI2_c + -------- + 3.919 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_22: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.919 39.PADDI to R6C5C.CLK PHI2_c + -------- + 3.919 (0.0% logic, 100.0% route), 0 logic levels. + +Report: 47.219MHz is the maximum frequency for this preference. ================================================================================ @@ -600,45 +629,149 @@ Report: 400.000MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; - 388 items scored, 0 timing errors detected. + 392 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- -Passed: The following path meets requirements by 8.213ns +Passed: The following path meets requirements by 6.770ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[12] (from RCLK_c +) + Destination: FF Data in UFMSDI (to RCLK_c +) + + Delay: 9.049ns (26.7% logic, 73.3% route), 6 logic levels. + + Constraint Details: + + 9.049ns physical path delay SLICE_3 to SLICE_52 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.181ns DIN_SET requirement (totaling 15.819ns) by 6.770ns + + Physical Path Details: + + Data path SLICE_3 to SLICE_52: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R8C3C.CLK to R8C3C.Q0 SLICE_3 (from RCLK_c) +ROUTE 3 1.870 R8C3C.Q0 to R8C4B.C1 FS[12] +CTOF_DEL --- 0.371 R8C4B.C1 to R8C4B.F1 SLICE_86 +ROUTE 1 0.694 R8C4B.F1 to R7C4A.D1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.371 R7C4A.D1 to R7C4A.F1 SLICE_69 +ROUTE 4 1.192 R7C4A.F1 to R6C5D.D1 N_128 +CTOF_DEL --- 0.371 R6C5D.D1 to R6C5D.F1 SLICE_58 +ROUTE 3 1.723 R6C5D.F1 to R3C5A.C0 N_94 +CTOF_DEL --- 0.371 R3C5A.C0 to R3C5A.F0 SLICE_55 +ROUTE 1 1.155 R3C5A.F0 to R7C5B.D0 UFMSDI_r_xx_mm_1 +CTOF_DEL --- 0.371 R7C5B.D0 to R7C5B.F0 SLICE_52 +ROUTE 1 0.000 R7C5B.F0 to R7C5B.DI0 UFMSDI_RNO (to RCLK_c) + -------- + 9.049 (26.7% logic, 73.3% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 1.353 86.PADDI to R8C3C.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_52: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 1.353 86.PADDI to R7C5B.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 7.278ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[10] (from RCLK_c +) + Destination: FF Data in UFMSDI (to RCLK_c +) + + Delay: 8.541ns (23.9% logic, 76.1% route), 5 logic levels. + + Constraint Details: + + 8.541ns physical path delay SLICE_4 to SLICE_52 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.181ns DIN_SET requirement (totaling 15.819ns) by 7.278ns + + Physical Path Details: + + Data path SLICE_4 to SLICE_52: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R8C3B.CLK to R8C3B.Q0 SLICE_4 (from RCLK_c) +ROUTE 5 1.886 R8C3B.Q0 to R7C3C.C1 FS[10] +CTOF_DEL --- 0.371 R7C3C.C1 to R7C3C.F1 SLICE_94 +ROUTE 1 1.840 R7C3C.F1 to R7C4B.C1 UFMSDI_ens2_i_a2_4_2 +CTOF_DEL --- 0.371 R7C4B.C1 to R7C4B.F1 SLICE_32 +ROUTE 1 1.616 R7C4B.F1 to R3C5A.D0 UFMSDI_ens2_i_a0 +CTOF_DEL --- 0.371 R3C5A.D0 to R3C5A.F0 SLICE_55 +ROUTE 1 1.155 R3C5A.F0 to R7C5B.D0 UFMSDI_r_xx_mm_1 +CTOF_DEL --- 0.371 R7C5B.D0 to R7C5B.F0 SLICE_52 +ROUTE 1 0.000 R7C5B.F0 to R7C5B.DI0 UFMSDI_RNO (to RCLK_c) + -------- + 8.541 (23.9% logic, 76.1% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_4: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 1.353 86.PADDI to R8C3B.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_52: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 1.353 86.PADDI to R7C5B.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 7.584ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[15] (from RCLK_c +) - Destination: FF Data in LEDEN (to RCLK_c +) + Destination: FF Data in UFMSDI (to RCLK_c +) - Delay: 7.543ns (32.0% logic, 68.0% route), 6 logic levels. + Delay: 8.235ns (29.3% logic, 70.7% route), 6 logic levels. Constraint Details: - 7.543ns physical path delay SLICE_2 to SLICE_33 meets + 8.235ns physical path delay SLICE_2 to SLICE_52 meets 16.000ns delay constraint less 0.000ns skew and - 0.244ns CE_SET requirement (totaling 15.756ns) by 8.213ns + 0.181ns DIN_SET requirement (totaling 15.819ns) by 7.584ns Physical Path Details: - Data path SLICE_2 to SLICE_33: + Data path SLICE_2 to SLICE_52: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.560 R8C3D.CLK to R8C3D.Q1 SLICE_2 (from RCLK_c) -ROUTE 3 1.571 R8C3D.Q1 to R7C4A.B1 FS[15] -CTOF_DEL --- 0.371 R7C4A.B1 to R7C4A.F1 SLICE_81 -ROUTE 1 0.700 R7C4A.F1 to R7C3B.D1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 R7C3B.D1 to R7C3B.F1 SLICE_72 -ROUTE 4 0.350 R7C3B.F1 to R7C3C.D1 N_51 -CTOF_DEL --- 0.371 R7C3C.D1 to R7C3C.F1 SLICE_58 -ROUTE 2 0.642 R7C3C.F1 to R7C3D.D0 N_151 -CTOF_DEL --- 0.371 R7C3D.D0 to R7C3D.F0 SLICE_87 -ROUTE 2 0.700 R7C3D.F0 to R7C2D.D0 N_137_8 -CTOF_DEL --- 0.371 R7C2D.D0 to R7C2D.F0 SLICE_69 -ROUTE 1 1.165 R7C2D.F0 to R7C5A.CE N_33 (to RCLK_c) +ROUTE 3 1.056 R8C3D.Q1 to R8C4B.A1 FS[15] +CTOF_DEL --- 0.371 R8C4B.A1 to R8C4B.F1 SLICE_86 +ROUTE 1 0.694 R8C4B.F1 to R7C4A.D1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.371 R7C4A.D1 to R7C4A.F1 SLICE_69 +ROUTE 4 1.192 R7C4A.F1 to R6C5D.D1 N_128 +CTOF_DEL --- 0.371 R6C5D.D1 to R6C5D.F1 SLICE_58 +ROUTE 3 1.723 R6C5D.F1 to R3C5A.C0 N_94 +CTOF_DEL --- 0.371 R3C5A.C0 to R3C5A.F0 SLICE_55 +ROUTE 1 1.155 R3C5A.F0 to R7C5B.D0 UFMSDI_r_xx_mm_1 +CTOF_DEL --- 0.371 R7C5B.D0 to R7C5B.F0 SLICE_52 +ROUTE 1 0.000 R7C5B.F0 to R7C5B.DI0 UFMSDI_RNO (to RCLK_c) -------- - 7.543 (32.0% logic, 68.0% route), 6 logic levels. + 8.235 (29.3% logic, 70.7% route), 6 logic levels. Clock Skew Details: @@ -649,102 +782,49 @@ ROUTE 32 1.353 86.PADDI to R8C3D.CLK RCLK_c -------- 1.353 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_33: + Destination Clock Path RCLK to SLICE_52: Name Fanout Delay (ns) Site Resource -ROUTE 32 1.353 86.PADDI to R7C5A.CLK RCLK_c +ROUTE 32 1.353 86.PADDI to R7C5B.CLK RCLK_c -------- 1.353 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 8.305ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[15] (from RCLK_c +) - Destination: FF Data in n8MEGEN (to RCLK_c +) - - Delay: 7.451ns (32.4% logic, 67.6% route), 6 logic levels. - - Constraint Details: - - 7.451ns physical path delay SLICE_2 to SLICE_58 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.244ns CE_SET requirement (totaling 15.756ns) by 8.305ns - - Physical Path Details: - - Data path SLICE_2 to SLICE_58: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C3D.CLK to R8C3D.Q1 SLICE_2 (from RCLK_c) -ROUTE 3 1.571 R8C3D.Q1 to R7C4A.B1 FS[15] -CTOF_DEL --- 0.371 R7C4A.B1 to R7C4A.F1 SLICE_81 -ROUTE 1 0.700 R7C4A.F1 to R7C3B.D1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 R7C3B.D1 to R7C3B.F1 SLICE_72 -ROUTE 4 0.350 R7C3B.F1 to R7C3C.D1 N_51 -CTOF_DEL --- 0.371 R7C3C.D1 to R7C3C.F1 SLICE_58 -ROUTE 2 0.642 R7C3C.F1 to R7C3D.D0 N_151 -CTOF_DEL --- 0.371 R7C3D.D0 to R7C3D.F0 SLICE_87 -ROUTE 2 0.700 R7C3D.F0 to R7C2B.D0 N_137_8 -CTOF_DEL --- 0.371 R7C2B.D0 to R7C2B.F0 SLICE_68 -ROUTE 1 1.073 R7C2B.F0 to R7C3C.CE N_31 (to RCLK_c) - -------- - 7.451 (32.4% logic, 67.6% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_2: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 1.353 86.PADDI to R8C3D.CLK RCLK_c - -------- - 1.353 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_58: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 1.353 86.PADDI to R7C3C.CLK RCLK_c - -------- - 1.353 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 8.378ns +Passed: The following path meets requirements by 7.591ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[17] (from RCLK_c +) - Destination: FF Data in LEDEN (to RCLK_c +) + Destination: FF Data in UFMSDI (to RCLK_c +) - Delay: 7.378ns (32.7% logic, 67.3% route), 6 logic levels. + Delay: 8.228ns (29.4% logic, 70.6% route), 6 logic levels. Constraint Details: - 7.378ns physical path delay SLICE_1 to SLICE_33 meets + 8.228ns physical path delay SLICE_1 to SLICE_52 meets 16.000ns delay constraint less 0.000ns skew and - 0.244ns CE_SET requirement (totaling 15.756ns) by 8.378ns + 0.181ns DIN_SET requirement (totaling 15.819ns) by 7.591ns Physical Path Details: - Data path SLICE_1 to SLICE_33: + Data path SLICE_1 to SLICE_52: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.560 R8C4A.CLK to R8C4A.Q1 SLICE_1 (from RCLK_c) -ROUTE 3 1.406 R8C4A.Q1 to R7C4A.A1 FS[17] -CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_81 -ROUTE 1 0.700 R7C4A.F1 to R7C3B.D1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 R7C3B.D1 to R7C3B.F1 SLICE_72 -ROUTE 4 0.350 R7C3B.F1 to R7C3C.D1 N_51 -CTOF_DEL --- 0.371 R7C3C.D1 to R7C3C.F1 SLICE_58 -ROUTE 2 0.642 R7C3C.F1 to R7C3D.D0 N_151 -CTOF_DEL --- 0.371 R7C3D.D0 to R7C3D.F0 SLICE_87 -ROUTE 2 0.700 R7C3D.F0 to R7C2D.D0 N_137_8 -CTOF_DEL --- 0.371 R7C2D.D0 to R7C2D.F0 SLICE_69 -ROUTE 1 1.165 R7C2D.F0 to R7C5A.CE N_33 (to RCLK_c) +ROUTE 3 1.049 R8C4A.Q1 to R8C4B.B1 FS[17] +CTOF_DEL --- 0.371 R8C4B.B1 to R8C4B.F1 SLICE_86 +ROUTE 1 0.694 R8C4B.F1 to R7C4A.D1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.371 R7C4A.D1 to R7C4A.F1 SLICE_69 +ROUTE 4 1.192 R7C4A.F1 to R6C5D.D1 N_128 +CTOF_DEL --- 0.371 R6C5D.D1 to R6C5D.F1 SLICE_58 +ROUTE 3 1.723 R6C5D.F1 to R3C5A.C0 N_94 +CTOF_DEL --- 0.371 R3C5A.C0 to R3C5A.F0 SLICE_55 +ROUTE 1 1.155 R3C5A.F0 to R7C5B.D0 UFMSDI_r_xx_mm_1 +CTOF_DEL --- 0.371 R7C5B.D0 to R7C5B.F0 SLICE_52 +ROUTE 1 0.000 R7C5B.F0 to R7C5B.DI0 UFMSDI_RNO (to RCLK_c) -------- - 7.378 (32.7% logic, 67.3% route), 6 logic levels. + 8.228 (29.4% logic, 70.6% route), 6 logic levels. Clock Skew Details: @@ -755,49 +835,153 @@ ROUTE 32 1.353 86.PADDI to R8C4A.CLK RCLK_c -------- 1.353 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_33: + Destination Clock Path RCLK to SLICE_52: Name Fanout Delay (ns) Site Resource -ROUTE 32 1.353 86.PADDI to R7C5A.CLK RCLK_c +ROUTE 32 1.353 86.PADDI to R7C5B.CLK RCLK_c -------- 1.353 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 8.404ns +Passed: The following path meets requirements by 7.610ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[12] (from RCLK_c +) + Destination: FF Data in n8MEGEN (to RCLK_c +) + + Delay: 8.146ns (25.1% logic, 74.9% route), 5 logic levels. + + Constraint Details: + + 8.146ns physical path delay SLICE_3 to SLICE_58 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.244ns CE_SET requirement (totaling 15.756ns) by 7.610ns + + Physical Path Details: + + Data path SLICE_3 to SLICE_58: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R8C3C.CLK to R8C3C.Q0 SLICE_3 (from RCLK_c) +ROUTE 3 1.870 R8C3C.Q0 to R8C4B.C1 FS[12] +CTOF_DEL --- 0.371 R8C4B.C1 to R8C4B.F1 SLICE_86 +ROUTE 1 0.694 R8C4B.F1 to R7C4A.D1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.371 R7C4A.D1 to R7C4A.F1 SLICE_69 +ROUTE 4 1.192 R7C4A.F1 to R6C5D.D1 N_128 +CTOF_DEL --- 0.371 R6C5D.D1 to R6C5D.F1 SLICE_58 +ROUTE 3 0.716 R6C5D.F1 to R7C5C.D0 N_94 +CTOF_DEL --- 0.371 R7C5C.D0 to R7C5C.F0 SLICE_71 +ROUTE 1 1.630 R7C5C.F0 to R6C5D.CE N_24 (to RCLK_c) + -------- + 8.146 (25.1% logic, 74.9% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 1.353 86.PADDI to R8C3C.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_58: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 1.353 86.PADDI to R6C5D.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 7.734ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[12] (from RCLK_c +) + Destination: FF Data in UFMSDI (to RCLK_c +) + + Delay: 8.085ns (29.9% logic, 70.1% route), 6 logic levels. + + Constraint Details: + + 8.085ns physical path delay SLICE_3 to SLICE_52 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.181ns DIN_SET requirement (totaling 15.819ns) by 7.734ns + + Physical Path Details: + + Data path SLICE_3 to SLICE_52: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R8C3C.CLK to R8C3C.Q0 SLICE_3 (from RCLK_c) +ROUTE 3 1.870 R8C3C.Q0 to R8C4B.C1 FS[12] +CTOF_DEL --- 0.371 R8C4B.C1 to R8C4B.F1 SLICE_86 +ROUTE 1 0.694 R8C4B.F1 to R7C4A.D1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.371 R7C4A.D1 to R7C4A.F1 SLICE_69 +ROUTE 4 0.335 R7C4A.F1 to R7C4B.D1 N_128 +CTOF_DEL --- 0.371 R7C4B.D1 to R7C4B.F1 SLICE_32 +ROUTE 1 1.616 R7C4B.F1 to R3C5A.D0 UFMSDI_ens2_i_a0 +CTOF_DEL --- 0.371 R3C5A.D0 to R3C5A.F0 SLICE_55 +ROUTE 1 1.155 R3C5A.F0 to R7C5B.D0 UFMSDI_r_xx_mm_1 +CTOF_DEL --- 0.371 R7C5B.D0 to R7C5B.F0 SLICE_52 +ROUTE 1 0.000 R7C5B.F0 to R7C5B.DI0 UFMSDI_RNO (to RCLK_c) + -------- + 8.085 (29.9% logic, 70.1% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 1.353 86.PADDI to R8C3C.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_52: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 1.353 86.PADDI to R7C5B.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 7.924ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[14] (from RCLK_c +) - Destination: FF Data in LEDEN (to RCLK_c +) + Destination: FF Data in UFMSDI (to RCLK_c +) - Delay: 7.352ns (32.8% logic, 67.2% route), 6 logic levels. + Delay: 7.895ns (30.6% logic, 69.4% route), 6 logic levels. Constraint Details: - 7.352ns physical path delay SLICE_2 to SLICE_33 meets + 7.895ns physical path delay SLICE_2 to SLICE_52 meets 16.000ns delay constraint less 0.000ns skew and - 0.244ns CE_SET requirement (totaling 15.756ns) by 8.404ns + 0.181ns DIN_SET requirement (totaling 15.819ns) by 7.924ns Physical Path Details: - Data path SLICE_2 to SLICE_33: + Data path SLICE_2 to SLICE_52: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.560 R8C3D.CLK to R8C3D.Q0 SLICE_2 (from RCLK_c) -ROUTE 3 1.380 R8C3D.Q0 to R7C4A.C1 FS[14] -CTOF_DEL --- 0.371 R7C4A.C1 to R7C4A.F1 SLICE_81 -ROUTE 1 0.700 R7C4A.F1 to R7C3B.D1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 R7C3B.D1 to R7C3B.F1 SLICE_72 -ROUTE 4 0.350 R7C3B.F1 to R7C3C.D1 N_51 -CTOF_DEL --- 0.371 R7C3C.D1 to R7C3C.F1 SLICE_58 -ROUTE 2 0.642 R7C3C.F1 to R7C3D.D0 N_151 -CTOF_DEL --- 0.371 R7C3D.D0 to R7C3D.F0 SLICE_87 -ROUTE 2 0.700 R7C3D.F0 to R7C2D.D0 N_137_8 -CTOF_DEL --- 0.371 R7C2D.D0 to R7C2D.F0 SLICE_69 -ROUTE 1 1.165 R7C2D.F0 to R7C5A.CE N_33 (to RCLK_c) +ROUTE 3 0.716 R8C3D.Q0 to R8C4B.D1 FS[14] +CTOF_DEL --- 0.371 R8C4B.D1 to R8C4B.F1 SLICE_86 +ROUTE 1 0.694 R8C4B.F1 to R7C4A.D1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.371 R7C4A.D1 to R7C4A.F1 SLICE_69 +ROUTE 4 1.192 R7C4A.F1 to R6C5D.D1 N_128 +CTOF_DEL --- 0.371 R6C5D.D1 to R6C5D.F1 SLICE_58 +ROUTE 3 1.723 R6C5D.F1 to R3C5A.C0 N_94 +CTOF_DEL --- 0.371 R3C5A.C0 to R3C5A.F0 SLICE_55 +ROUTE 1 1.155 R3C5A.F0 to R7C5B.D0 UFMSDI_r_xx_mm_1 +CTOF_DEL --- 0.371 R7C5B.D0 to R7C5B.F0 SLICE_52 +ROUTE 1 0.000 R7C5B.F0 to R7C5B.DI0 UFMSDI_RNO (to RCLK_c) -------- - 7.352 (32.8% logic, 67.2% route), 6 logic levels. + 7.895 (30.6% logic, 69.4% route), 6 logic levels. Clock Skew Details: @@ -808,204 +992,47 @@ ROUTE 32 1.353 86.PADDI to R8C3D.CLK RCLK_c -------- 1.353 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_33: + Destination Clock Path RCLK to SLICE_52: Name Fanout Delay (ns) Site Resource -ROUTE 32 1.353 86.PADDI to R7C5A.CLK RCLK_c +ROUTE 32 1.353 86.PADDI to R7C5B.CLK RCLK_c -------- 1.353 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 8.470ns +Passed: The following path meets requirements by 7.974ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS[17] (from RCLK_c +) - Destination: FF Data in n8MEGEN (to RCLK_c +) - - Delay: 7.286ns (33.1% logic, 66.9% route), 6 logic levels. - - Constraint Details: - - 7.286ns physical path delay SLICE_1 to SLICE_58 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.244ns CE_SET requirement (totaling 15.756ns) by 8.470ns - - Physical Path Details: - - Data path SLICE_1 to SLICE_58: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C4A.CLK to R8C4A.Q1 SLICE_1 (from RCLK_c) -ROUTE 3 1.406 R8C4A.Q1 to R7C4A.A1 FS[17] -CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_81 -ROUTE 1 0.700 R7C4A.F1 to R7C3B.D1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 R7C3B.D1 to R7C3B.F1 SLICE_72 -ROUTE 4 0.350 R7C3B.F1 to R7C3C.D1 N_51 -CTOF_DEL --- 0.371 R7C3C.D1 to R7C3C.F1 SLICE_58 -ROUTE 2 0.642 R7C3C.F1 to R7C3D.D0 N_151 -CTOF_DEL --- 0.371 R7C3D.D0 to R7C3D.F0 SLICE_87 -ROUTE 2 0.700 R7C3D.F0 to R7C2B.D0 N_137_8 -CTOF_DEL --- 0.371 R7C2B.D0 to R7C2B.F0 SLICE_68 -ROUTE 1 1.073 R7C2B.F0 to R7C3C.CE N_31 (to RCLK_c) - -------- - 7.286 (33.1% logic, 66.9% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_1: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 1.353 86.PADDI to R8C4A.CLK RCLK_c - -------- - 1.353 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_58: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 1.353 86.PADDI to R7C3C.CLK RCLK_c - -------- - 1.353 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 8.496ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[14] (from RCLK_c +) - Destination: FF Data in n8MEGEN (to RCLK_c +) - - Delay: 7.260ns (33.3% logic, 66.7% route), 6 logic levels. - - Constraint Details: - - 7.260ns physical path delay SLICE_2 to SLICE_58 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.244ns CE_SET requirement (totaling 15.756ns) by 8.496ns - - Physical Path Details: - - Data path SLICE_2 to SLICE_58: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C3D.CLK to R8C3D.Q0 SLICE_2 (from RCLK_c) -ROUTE 3 1.380 R8C3D.Q0 to R7C4A.C1 FS[14] -CTOF_DEL --- 0.371 R7C4A.C1 to R7C4A.F1 SLICE_81 -ROUTE 1 0.700 R7C4A.F1 to R7C3B.D1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 R7C3B.D1 to R7C3B.F1 SLICE_72 -ROUTE 4 0.350 R7C3B.F1 to R7C3C.D1 N_51 -CTOF_DEL --- 0.371 R7C3C.D1 to R7C3C.F1 SLICE_58 -ROUTE 2 0.642 R7C3C.F1 to R7C3D.D0 N_151 -CTOF_DEL --- 0.371 R7C3D.D0 to R7C3D.F0 SLICE_87 -ROUTE 2 0.700 R7C3D.F0 to R7C2B.D0 N_137_8 -CTOF_DEL --- 0.371 R7C2B.D0 to R7C2B.F0 SLICE_68 -ROUTE 1 1.073 R7C2B.F0 to R7C3C.CE N_31 (to RCLK_c) - -------- - 7.260 (33.3% logic, 66.7% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_2: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 1.353 86.PADDI to R8C3D.CLK RCLK_c - -------- - 1.353 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_58: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 1.353 86.PADDI to R7C3C.CLK RCLK_c - -------- - 1.353 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 8.592ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS[0] (from RCLK_c +) - Destination: FF Data in Ready_fast (to RCLK_c +) - - Delay: 7.227ns (23.1% logic, 76.9% route), 4 logic levels. - - Constraint Details: - - 7.227ns physical path delay SLICE_29 to SLICE_44 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.181ns DIN_SET requirement (totaling 15.819ns) by 8.592ns - - Physical Path Details: - - Data path SLICE_29 to SLICE_44: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R2C5D.CLK to R2C5D.Q0 SLICE_29 (from RCLK_c) -ROUTE 9 3.095 R2C5D.Q0 to R6C5A.B0 IS[0] -CTOF_DEL --- 0.371 R6C5A.B0 to R6C5A.F0 SLICE_83 -ROUTE 2 1.962 R6C5A.F0 to R4C4D.A1 N_165 -CTOF_DEL --- 0.371 R4C4D.A1 to R4C4D.F1 SLICE_44 -ROUTE 1 0.497 R4C4D.F1 to R4C4D.C0 Ready_0_sqmuxa -CTOF_DEL --- 0.371 R4C4D.C0 to R4C4D.F0 SLICE_44 -ROUTE 1 0.000 R4C4D.F0 to R4C4D.DI0 N_463_0 (to RCLK_c) - -------- - 7.227 (23.1% logic, 76.9% route), 4 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_29: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 1.353 86.PADDI to R2C5D.CLK RCLK_c - -------- - 1.353 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_44: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 1.353 86.PADDI to R4C4D.CLK RCLK_c - -------- - 1.353 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 8.599ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[13] (from RCLK_c +) + Source: FF Q FS[12] (from RCLK_c +) Destination: FF Data in LEDEN (to RCLK_c +) - Delay: 7.157ns (33.7% logic, 66.3% route), 6 logic levels. + Delay: 7.782ns (26.3% logic, 73.7% route), 5 logic levels. Constraint Details: - 7.157ns physical path delay SLICE_3 to SLICE_33 meets + 7.782ns physical path delay SLICE_3 to SLICE_33 meets 16.000ns delay constraint less 0.000ns skew and - 0.244ns CE_SET requirement (totaling 15.756ns) by 8.599ns + 0.244ns CE_SET requirement (totaling 15.756ns) by 7.974ns Physical Path Details: Data path SLICE_3 to SLICE_33: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C3C.CLK to R8C3C.Q1 SLICE_3 (from RCLK_c) -ROUTE 3 1.185 R8C3C.Q1 to R7C4A.D1 FS[13] -CTOF_DEL --- 0.371 R7C4A.D1 to R7C4A.F1 SLICE_81 -ROUTE 1 0.700 R7C4A.F1 to R7C3B.D1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 R7C3B.D1 to R7C3B.F1 SLICE_72 -ROUTE 4 0.350 R7C3B.F1 to R7C3C.D1 N_51 -CTOF_DEL --- 0.371 R7C3C.D1 to R7C3C.F1 SLICE_58 -ROUTE 2 0.642 R7C3C.F1 to R7C3D.D0 N_151 -CTOF_DEL --- 0.371 R7C3D.D0 to R7C3D.F0 SLICE_87 -ROUTE 2 0.700 R7C3D.F0 to R7C2D.D0 N_137_8 -CTOF_DEL --- 0.371 R7C2D.D0 to R7C2D.F0 SLICE_69 -ROUTE 1 1.165 R7C2D.F0 to R7C5A.CE N_33 (to RCLK_c) +REG_DEL --- 0.560 R8C3C.CLK to R8C3C.Q0 SLICE_3 (from RCLK_c) +ROUTE 3 1.870 R8C3C.Q0 to R8C4B.C1 FS[12] +CTOF_DEL --- 0.371 R8C4B.C1 to R8C4B.F1 SLICE_86 +ROUTE 1 0.694 R8C4B.F1 to R7C4A.D1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.371 R7C4A.D1 to R7C4A.F1 SLICE_69 +ROUTE 4 1.192 R7C4A.F1 to R6C5D.D1 N_128 +CTOF_DEL --- 0.371 R6C5D.D1 to R6C5D.F1 SLICE_58 +ROUTE 3 0.909 R6C5D.F1 to R7C5D.C0 N_94 +CTOF_DEL --- 0.371 R7C5D.C0 to R7C5D.F0 SLICE_72 +ROUTE 1 1.073 R7C5D.F0 to R6C5B.CE N_26 (to RCLK_c) -------- - 7.157 (33.7% logic, 66.3% route), 6 logic levels. + 7.782 (26.3% logic, 73.7% route), 5 logic levels. Clock Skew Details: @@ -1019,44 +1046,44 @@ ROUTE 32 1.353 86.PADDI to R8C3C.CLK RCLK_c Destination Clock Path RCLK to SLICE_33: Name Fanout Delay (ns) Site Resource -ROUTE 32 1.353 86.PADDI to R7C5A.CLK RCLK_c +ROUTE 32 1.353 86.PADDI to R6C5B.CLK RCLK_c -------- 1.353 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 8.660ns +Passed: The following path meets requirements by 7.985ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS[7] (from RCLK_c +) + Source: FF Q FS[6] (from RCLK_c +) Destination: FF Data in UFMSDI (to RCLK_c +) - Delay: 7.159ns (28.6% logic, 71.4% route), 5 logic levels. + Delay: 7.834ns (26.1% logic, 73.9% route), 5 logic levels. Constraint Details: - 7.159ns physical path delay SLICE_6 to SLICE_52 meets + 7.834ns physical path delay SLICE_6 to SLICE_52 meets 16.000ns delay constraint less 0.000ns skew and - 0.181ns DIN_SET requirement (totaling 15.819ns) by 8.660ns + 0.181ns DIN_SET requirement (totaling 15.819ns) by 7.985ns Physical Path Details: Data path SLICE_6 to SLICE_52: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C2D.CLK to R8C2D.Q1 SLICE_6 (from RCLK_c) -ROUTE 3 2.186 R8C2D.Q1 to R4C5A.B0 FS[7] -CTOF_DEL --- 0.371 R4C5A.B0 to R4C5A.F0 SLICE_56 -ROUTE 1 1.609 R4C5A.F0 to R7C3A.D1 N_126 -CTOF_DEL --- 0.371 R7C3A.D1 to R7C3A.F1 SLICE_32 -ROUTE 1 0.626 R7C3A.F1 to R7C3D.D1 UFMSDI_ens2_i_a0 -CTOF_DEL --- 0.371 R7C3D.D1 to R7C3D.F1 SLICE_87 -ROUTE 1 0.694 R7C3D.F1 to R7C5B.D0 UFMSDI_r_xx_mm_1 +REG_DEL --- 0.560 R8C2D.CLK to R8C2D.Q0 SLICE_6 (from RCLK_c) +ROUTE 3 1.179 R8C2D.Q0 to R7C3C.D1 FS[6] +CTOF_DEL --- 0.371 R7C3C.D1 to R7C3C.F1 SLICE_94 +ROUTE 1 1.840 R7C3C.F1 to R7C4B.C1 UFMSDI_ens2_i_a2_4_2 +CTOF_DEL --- 0.371 R7C4B.C1 to R7C4B.F1 SLICE_32 +ROUTE 1 1.616 R7C4B.F1 to R3C5A.D0 UFMSDI_ens2_i_a0 +CTOF_DEL --- 0.371 R3C5A.D0 to R3C5A.F0 SLICE_55 +ROUTE 1 1.155 R3C5A.F0 to R7C5B.D0 UFMSDI_r_xx_mm_1 CTOF_DEL --- 0.371 R7C5B.D0 to R7C5B.F0 SLICE_52 ROUTE 1 0.000 R7C5B.F0 to R7C5B.DI0 UFMSDI_RNO (to RCLK_c) -------- - 7.159 (28.6% logic, 71.4% route), 5 logic levels. + 7.834 (26.1% logic, 73.9% route), 5 logic levels. Clock Skew Details: @@ -1075,59 +1102,57 @@ ROUTE 32 1.353 86.PADDI to R7C5B.CLK RCLK_c 1.353 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 8.691ns +Passed: The following path meets requirements by 8.032ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS[13] (from RCLK_c +) - Destination: FF Data in n8MEGEN (to RCLK_c +) + Source: FF Q FS[11] (from RCLK_c +) + Destination: FF Data in UFMSDI (to RCLK_c +) - Delay: 7.065ns (34.2% logic, 65.8% route), 6 logic levels. + Delay: 7.787ns (26.2% logic, 73.8% route), 5 logic levels. Constraint Details: - 7.065ns physical path delay SLICE_3 to SLICE_58 meets + 7.787ns physical path delay SLICE_4 to SLICE_52 meets 16.000ns delay constraint less 0.000ns skew and - 0.244ns CE_SET requirement (totaling 15.756ns) by 8.691ns + 0.181ns DIN_SET requirement (totaling 15.819ns) by 8.032ns Physical Path Details: - Data path SLICE_3 to SLICE_58: + Data path SLICE_4 to SLICE_52: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C3C.CLK to R8C3C.Q1 SLICE_3 (from RCLK_c) -ROUTE 3 1.185 R8C3C.Q1 to R7C4A.D1 FS[13] -CTOF_DEL --- 0.371 R7C4A.D1 to R7C4A.F1 SLICE_81 -ROUTE 1 0.700 R7C4A.F1 to R7C3B.D1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 R7C3B.D1 to R7C3B.F1 SLICE_72 -ROUTE 4 0.350 R7C3B.F1 to R7C3C.D1 N_51 -CTOF_DEL --- 0.371 R7C3C.D1 to R7C3C.F1 SLICE_58 -ROUTE 2 0.642 R7C3C.F1 to R7C3D.D0 N_151 -CTOF_DEL --- 0.371 R7C3D.D0 to R7C3D.F0 SLICE_87 -ROUTE 2 0.700 R7C3D.F0 to R7C2B.D0 N_137_8 -CTOF_DEL --- 0.371 R7C2B.D0 to R7C2B.F0 SLICE_68 -ROUTE 1 1.073 R7C2B.F0 to R7C3C.CE N_31 (to RCLK_c) +REG_DEL --- 0.560 R8C3B.CLK to R8C3B.Q1 SLICE_4 (from RCLK_c) +ROUTE 6 1.132 R8C3B.Q1 to R7C3C.B1 FS[11] +CTOF_DEL --- 0.371 R7C3C.B1 to R7C3C.F1 SLICE_94 +ROUTE 1 1.840 R7C3C.F1 to R7C4B.C1 UFMSDI_ens2_i_a2_4_2 +CTOF_DEL --- 0.371 R7C4B.C1 to R7C4B.F1 SLICE_32 +ROUTE 1 1.616 R7C4B.F1 to R3C5A.D0 UFMSDI_ens2_i_a0 +CTOF_DEL --- 0.371 R3C5A.D0 to R3C5A.F0 SLICE_55 +ROUTE 1 1.155 R3C5A.F0 to R7C5B.D0 UFMSDI_r_xx_mm_1 +CTOF_DEL --- 0.371 R7C5B.D0 to R7C5B.F0 SLICE_52 +ROUTE 1 0.000 R7C5B.F0 to R7C5B.DI0 UFMSDI_RNO (to RCLK_c) -------- - 7.065 (34.2% logic, 65.8% route), 6 logic levels. + 7.787 (26.2% logic, 73.8% route), 5 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_3: + Source Clock Path RCLK to SLICE_4: Name Fanout Delay (ns) Site Resource -ROUTE 32 1.353 86.PADDI to R8C3C.CLK RCLK_c +ROUTE 32 1.353 86.PADDI to R8C3B.CLK RCLK_c -------- 1.353 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_58: + Destination Clock Path RCLK to SLICE_52: Name Fanout Delay (ns) Site Resource -ROUTE 32 1.353 86.PADDI to R7C3C.CLK RCLK_c +ROUTE 32 1.353 86.PADDI to R7C5B.CLK RCLK_c -------- 1.353 (0.0% logic, 100.0% route), 0 logic levels. -Report: 128.419MHz is the maximum frequency for this preference. +Report: 108.342MHz is the maximum frequency for this preference. Report Summary -------------- @@ -1135,13 +1160,13 @@ Report Summary Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | -FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 56.029 MHz| 6 +FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 47.219 MHz| 7 | | | FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 400.000 MHz| 0 | | | FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 400.000 MHz| 0 | | | -FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 128.419 MHz| 6 +FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 108.342 MHz| 6 | | | ---------------------------------------------------------------------------- @@ -1196,11 +1221,11 @@ Timing summary (Setup): Timing errors: 0 Score: 0 Cumulative negative slack: 0 -Constraints cover 517 paths, 4 nets, and 420 connections (66.35% coverage) +Constraints cover 560 paths, 4 nets, and 447 connections (65.64% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 -Thu Sep 21 05:38:43 2023 +Sat Jan 06 06:25:12 2024 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -1225,7 +1250,7 @@ BLOCK RESETPATHS ================================================================================ Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ; - 129 items scored, 0 timing errors detected. + 168 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- @@ -1250,10 +1275,10 @@ Passed: The following path meets requirements by 0.358ns Data path SLICE_9 to SLICE_9: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R5C3B.CLK to R5C3B.Q0 SLICE_9 (from PHI2_c) -ROUTE 2 0.128 R5C3B.Q0 to R5C3B.D0 ADSubmitted -CTOF_DEL --- 0.074 R5C3B.D0 to R5C3B.F0 SLICE_9 -ROUTE 1 0.000 R5C3B.F0 to R5C3B.DI0 ADSubmitted_r (to PHI2_c) +REG_DEL --- 0.137 R5C3A.CLK to R5C3A.Q0 SLICE_9 (from PHI2_c) +ROUTE 2 0.128 R5C3A.Q0 to R5C3A.D0 ADSubmitted +CTOF_DEL --- 0.074 R5C3A.D0 to R5C3A.F0 SLICE_9 +ROUTE 1 0.000 R5C3A.F0 to R5C3A.DI0 ADSubmitted_r (to PHI2_c) -------- 0.339 (62.2% logic, 37.8% route), 2 logic levels. @@ -1262,14 +1287,14 @@ ROUTE 1 0.000 R5C3B.F0 to R5C3B.DI0 ADSubmitted_r (to PHI Source Clock Path PHI2 to SLICE_9: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.967 39.PADDI to R5C3B.CLK PHI2_c +ROUTE 15 0.967 39.PADDI to R5C3A.CLK PHI2_c -------- 0.967 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_9: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.967 39.PADDI to R5C3B.CLK PHI2_c +ROUTE 15 0.967 39.PADDI to R5C3A.CLK PHI2_c -------- 0.967 (0.0% logic, 100.0% route), 0 logic levels. @@ -1295,10 +1320,10 @@ Passed: The following path meets requirements by 0.364ns Data path SLICE_22 to SLICE_22: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R6C4A.CLK to R6C4A.Q0 SLICE_22 (from PHI2_c) -ROUTE 3 0.134 R6C4A.Q0 to R6C4A.A0 CmdSubmitted -CTOF_DEL --- 0.074 R6C4A.A0 to R6C4A.F0 SLICE_22 -ROUTE 1 0.000 R6C4A.F0 to R6C4A.DI0 N_460_0 (to PHI2_c) +REG_DEL --- 0.137 R6C5C.CLK to R6C5C.Q0 SLICE_22 (from PHI2_c) +ROUTE 3 0.134 R6C5C.Q0 to R6C5C.A0 CmdSubmitted +CTOF_DEL --- 0.074 R6C5C.A0 to R6C5C.F0 SLICE_22 +ROUTE 1 0.000 R6C5C.F0 to R6C5C.DI0 N_428_0 (to PHI2_c) -------- 0.345 (61.2% logic, 38.8% route), 2 logic levels. @@ -1307,230 +1332,95 @@ ROUTE 1 0.000 R6C4A.F0 to R6C4A.DI0 N_460_0 (to PHI2_c) Source Clock Path PHI2 to SLICE_22: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.967 39.PADDI to R6C4A.CLK PHI2_c +ROUTE 15 0.967 39.PADDI to R6C5C.CLK PHI2_c -------- 0.967 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_22: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.967 39.PADDI to R6C4A.CLK PHI2_c +ROUTE 15 0.967 39.PADDI to R6C5C.CLK PHI2_c -------- 0.967 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 0.415ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CmdEnable (from PHI2_c -) - Destination: FF Data in CmdEnable (to PHI2_c -) - - Delay: 0.396ns (66.2% logic, 33.8% route), 2 logic levels. - - Constraint Details: - - 0.396ns physical path delay SLICE_20 to SLICE_20 meets - -0.019ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.415ns - - Physical Path Details: - - Data path SLICE_20 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R5C3D.CLK to R5C3D.Q0 SLICE_20 (from PHI2_c) -ROUTE 3 0.134 R5C3D.Q0 to R5C3D.A0 CmdEnable -CTOOFX_DEL --- 0.125 R5C3D.A0 to R5C3D.OFX0 SLICE_20 -ROUTE 1 0.000 R5C3D.OFX0 to R5C3D.DI0 CmdEnable_s (to PHI2_c) - -------- - 0.396 (66.2% logic, 33.8% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 0.967 39.PADDI to R5C3D.CLK PHI2_c - -------- - 0.967 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 0.967 39.PADDI to R5C3D.CLK PHI2_c - -------- - 0.967 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.436ns +Passed: The following path meets requirements by 0.399ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q C1Submitted (from PHI2_c -) Destination: FF Data in C1Submitted (to PHI2_c -) - Delay: 0.417ns (50.6% logic, 49.4% route), 2 logic levels. + Delay: 0.380ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: - 0.417ns physical path delay SLICE_14 to SLICE_14 meets + 0.380ns physical path delay SLICE_14 to SLICE_14 meets -0.019ns DIN_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.436ns + 0.000ns skew requirement (totaling -0.019ns) by 0.399ns Physical Path Details: Data path SLICE_14 to SLICE_14: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R5C3C.CLK to R5C3C.Q0 SLICE_14 (from PHI2_c) -ROUTE 2 0.206 R5C3C.Q0 to R5C3C.B0 C1Submitted -CTOF_DEL --- 0.074 R5C3C.B0 to R5C3C.F0 SLICE_14 -ROUTE 1 0.000 R5C3C.F0 to R5C3C.DI0 C1Submitted_RNO (to PHI2_c) +REG_DEL --- 0.137 R6C3A.CLK to R6C3A.Q0 SLICE_14 (from PHI2_c) +ROUTE 2 0.169 R6C3A.Q0 to R6C3A.C0 C1Submitted +CTOF_DEL --- 0.074 R6C3A.C0 to R6C3A.F0 SLICE_14 +ROUTE 1 0.000 R6C3A.F0 to R6C3A.DI0 C1Submitted_RNO (to PHI2_c) -------- - 0.417 (50.6% logic, 49.4% route), 2 logic levels. + 0.380 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_14: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.967 39.PADDI to R5C3C.CLK PHI2_c +ROUTE 15 0.967 39.PADDI to R6C3A.CLK PHI2_c -------- 0.967 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_14: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.967 39.PADDI to R5C3C.CLK PHI2_c +ROUTE 15 0.967 39.PADDI to R6C3A.CLK PHI2_c -------- 0.967 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 0.477ns +Passed: The following path meets requirements by 0.438ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CmdEnable (from PHI2_c -) Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 0.458ns (56.3% logic, 43.7% route), 2 logic levels. + Delay: 0.419ns (50.4% logic, 49.6% route), 2 logic levels. Constraint Details: - 0.458ns physical path delay SLICE_20 to SLICE_20 meets + 0.419ns physical path delay SLICE_20 to SLICE_20 meets -0.019ns DIN_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.477ns + 0.000ns skew requirement (totaling -0.019ns) by 0.438ns Physical Path Details: Data path SLICE_20 to SLICE_20: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R5C3D.CLK to R5C3D.Q0 SLICE_20 (from PHI2_c) -ROUTE 3 0.200 R5C3D.Q0 to R5C3D.A1 CmdEnable -CTOOFX_DEL --- 0.121 R5C3D.A1 to R5C3D.OFX0 SLICE_20 -ROUTE 1 0.000 R5C3D.OFX0 to R5C3D.DI0 CmdEnable_s (to PHI2_c) +REG_DEL --- 0.137 R5C3C.CLK to R5C3C.Q0 SLICE_20 (from PHI2_c) +ROUTE 2 0.208 R5C3C.Q0 to R5C3C.B0 CmdEnable +CTOF_DEL --- 0.074 R5C3C.B0 to R5C3C.F0 SLICE_20 +ROUTE 1 0.000 R5C3C.F0 to R5C3C.DI0 CmdEnable_s (to PHI2_c) -------- - 0.458 (56.3% logic, 43.7% route), 2 logic levels. + 0.419 (50.4% logic, 49.6% route), 2 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_20: - Name Fanout Delay (ns) Site Resource -ROUTE 15 0.967 39.PADDI to R5C3D.CLK PHI2_c - -------- - 0.967 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 0.967 39.PADDI to R5C3D.CLK PHI2_c - -------- - 0.967 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.483ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q ADSubmitted (from PHI2_c -) - Destination: FF Data in CmdEnable (to PHI2_c -) - - Delay: 0.464ns (55.6% logic, 44.4% route), 2 logic levels. - - Constraint Details: - - 0.464ns physical path delay SLICE_9 to SLICE_20 meets - -0.019ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.483ns - - Physical Path Details: - - Data path SLICE_9 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R5C3B.CLK to R5C3B.Q0 SLICE_9 (from PHI2_c) -ROUTE 2 0.206 R5C3B.Q0 to R5C3D.B1 ADSubmitted -CTOOFX_DEL --- 0.121 R5C3D.B1 to R5C3D.OFX0 SLICE_20 -ROUTE 1 0.000 R5C3D.OFX0 to R5C3D.DI0 CmdEnable_s (to PHI2_c) - -------- - 0.464 (55.6% logic, 44.4% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_9: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 0.967 39.PADDI to R5C3B.CLK PHI2_c - -------- - 0.967 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 0.967 39.PADDI to R5C3D.CLK PHI2_c - -------- - 0.967 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.487ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q C1Submitted (from PHI2_c -) - Destination: FF Data in CmdEnable (to PHI2_c -) - - Delay: 0.468ns (56.0% logic, 44.0% route), 2 logic levels. - - Constraint Details: - - 0.468ns physical path delay SLICE_14 to SLICE_20 meets - -0.019ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.487ns - - Physical Path Details: - - Data path SLICE_14 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R5C3C.CLK to R5C3C.Q0 SLICE_14 (from PHI2_c) -ROUTE 2 0.206 R5C3C.Q0 to R5C3D.B0 C1Submitted -CTOOFX_DEL --- 0.125 R5C3D.B0 to R5C3D.OFX0 SLICE_20 -ROUTE 1 0.000 R5C3D.OFX0 to R5C3D.DI0 CmdEnable_s (to PHI2_c) - -------- - 0.468 (56.0% logic, 44.0% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_14: - Name Fanout Delay (ns) Site Resource ROUTE 15 0.967 39.PADDI to R5C3C.CLK PHI2_c -------- @@ -1539,52 +1429,148 @@ ROUTE 15 0.967 39.PADDI to R5C3C.CLK PHI2_c Destination Clock Path PHI2 to SLICE_20: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.967 39.PADDI to R5C3D.CLK PHI2_c +ROUTE 15 0.967 39.PADDI to R5C3C.CLK PHI2_c -------- 0.967 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 0.595ns +Passed: The following path meets requirements by 0.572ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q CmdEnable (from PHI2_c -) + Source: FF Q Cmdn8MEGEN (from PHI2_c -) Destination: FF Data in Cmdn8MEGEN (to PHI2_c -) - Delay: 0.572ns (36.9% logic, 63.1% route), 2 logic levels. + Delay: 0.553ns (51.5% logic, 48.5% route), 3 logic levels. Constraint Details: - 0.572ns physical path delay SLICE_20 to SLICE_26 meets - -0.023ns CE_HLD and + 0.553ns physical path delay SLICE_26 to SLICE_26 meets + -0.019ns DIN_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.023ns) by 0.595ns + 0.000ns skew requirement (totaling -0.019ns) by 0.572ns Physical Path Details: - Data path SLICE_20 to SLICE_26: + Data path SLICE_26 to SLICE_26: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R5C3D.CLK to R5C3D.Q0 SLICE_20 (from PHI2_c) -ROUTE 3 0.134 R5C3D.Q0 to R5C3A.D0 CmdEnable -CTOF_DEL --- 0.074 R5C3A.D0 to R5C3A.F0 SLICE_67 -ROUTE 5 0.227 R5C3A.F0 to R6C3B.CE XOR8MEG18 (to PHI2_c) +REG_DEL --- 0.137 R6C4C.CLK to R6C4C.Q0 SLICE_26 (from PHI2_c) +ROUTE 2 0.169 R6C4C.Q0 to R6C4C.C1 Cmdn8MEGEN +CTOF_DEL --- 0.074 R6C4C.C1 to R6C4C.F1 SLICE_26 +ROUTE 1 0.099 R6C4C.F1 to R6C4C.C0 Cmdn8MEGEN_4_u_i_0 +CTOF_DEL --- 0.074 R6C4C.C0 to R6C4C.F0 SLICE_26 +ROUTE 1 0.000 R6C4C.F0 to R6C4C.DI0 N_12_i (to PHI2_c) -------- - 0.572 (36.9% logic, 63.1% route), 2 logic levels. + 0.553 (51.5% logic, 48.5% route), 3 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_20: + Source Clock Path PHI2 to SLICE_26: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.967 39.PADDI to R5C3D.CLK PHI2_c +ROUTE 15 0.967 39.PADDI to R6C4C.CLK PHI2_c -------- 0.967 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_26: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.967 39.PADDI to R6C3B.CLK PHI2_c +ROUTE 15 0.967 39.PADDI to R6C4C.CLK PHI2_c + -------- + 0.967 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.599ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdLEDEN (from PHI2_c -) + Destination: FF Data in CmdLEDEN (to PHI2_c -) + + Delay: 0.580ns (49.1% logic, 50.9% route), 3 logic levels. + + Constraint Details: + + 0.580ns physical path delay SLICE_21 to SLICE_21 meets + -0.019ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.599ns + + Physical Path Details: + + Data path SLICE_21 to SLICE_21: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R6C4D.CLK to R6C4D.Q0 SLICE_21 (from PHI2_c) +ROUTE 2 0.196 R6C4D.Q0 to R6C4D.A1 CmdLEDEN +CTOF_DEL --- 0.074 R6C4D.A1 to R6C4D.F1 SLICE_21 +ROUTE 1 0.099 R6C4D.F1 to R6C4D.C0 CmdLEDEN_4_u_i_0 +CTOF_DEL --- 0.074 R6C4D.C0 to R6C4D.F0 SLICE_21 +ROUTE 1 0.000 R6C4D.F0 to R6C4D.DI0 N_14_i (to PHI2_c) + -------- + 0.580 (49.1% logic, 50.9% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_21: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 0.967 39.PADDI to R6C4D.CLK PHI2_c + -------- + 0.967 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_21: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 0.967 39.PADDI to R6C4D.CLK PHI2_c + -------- + 0.967 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.609ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q ADSubmitted (from PHI2_c -) + Destination: FF Data in CmdEnable (to PHI2_c -) + + Delay: 0.590ns (48.3% logic, 51.7% route), 3 logic levels. + + Constraint Details: + + 0.590ns physical path delay SLICE_9 to SLICE_20 meets + -0.019ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.609ns + + Physical Path Details: + + Data path SLICE_9 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R5C3A.CLK to R5C3A.Q0 SLICE_9 (from PHI2_c) +ROUTE 2 0.206 R5C3A.Q0 to R5C3C.B1 ADSubmitted +CTOF_DEL --- 0.074 R5C3C.B1 to R5C3C.F1 SLICE_20 +ROUTE 1 0.099 R5C3C.F1 to R5C3C.C0 CmdEnable_0_sqmuxa +CTOF_DEL --- 0.074 R5C3C.C0 to R5C3C.F0 SLICE_20 +ROUTE 1 0.000 R5C3C.F0 to R5C3C.DI0 CmdEnable_s (to PHI2_c) + -------- + 0.590 (48.3% logic, 51.7% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 0.967 39.PADDI to R5C3A.CLK PHI2_c + -------- + 0.967 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 0.967 39.PADDI to R5C3C.CLK PHI2_c -------- 0.967 (0.0% logic, 100.0% route), 0 logic levels. @@ -1593,92 +1579,137 @@ Passed: The following path meets requirements by 0.611ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Cmdn8MEGEN (from PHI2_c -) - Destination: FF Data in Cmdn8MEGEN (to PHI2_c -) + Source: FF Q XOR8MEG (from PHI2_c -) + Destination: FF Data in XOR8MEG (to PHI2_c -) Delay: 0.592ns (48.1% logic, 51.9% route), 3 logic levels. Constraint Details: - 0.592ns physical path delay SLICE_26 to SLICE_26 meets + 0.592ns physical path delay SLICE_57 to SLICE_57 meets -0.019ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.611ns Physical Path Details: - Data path SLICE_26 to SLICE_26: + Data path SLICE_57 to SLICE_57: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R6C3B.CLK to R6C3B.Q0 SLICE_26 (from PHI2_c) -ROUTE 2 0.208 R6C3B.Q0 to R6C3B.B1 Cmdn8MEGEN -CTOF_DEL --- 0.074 R6C3B.B1 to R6C3B.F1 SLICE_26 -ROUTE 1 0.099 R6C3B.F1 to R6C3B.C0 Cmdn8MEGEN_4_u_i_0 -CTOF_DEL --- 0.074 R6C3B.C0 to R6C3B.F0 SLICE_26 -ROUTE 1 0.000 R6C3B.F0 to R6C3B.DI0 N_19_i (to PHI2_c) +REG_DEL --- 0.137 R5C4D.CLK to R5C4D.Q0 SLICE_57 (from PHI2_c) +ROUTE 2 0.208 R5C4D.Q0 to R5C4D.B1 XOR8MEG +CTOF_DEL --- 0.074 R5C4D.B1 to R5C4D.F1 SLICE_57 +ROUTE 1 0.099 R5C4D.F1 to R5C4D.C0 N_166 +CTOF_DEL --- 0.074 R5C4D.C0 to R5C4D.F0 SLICE_57 +ROUTE 1 0.000 R5C4D.F0 to R5C4D.DI0 XOR8MEG_3 (to PHI2_c) -------- 0.592 (48.1% logic, 51.9% route), 3 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_26: + Source Clock Path PHI2 to SLICE_57: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.967 39.PADDI to R6C3B.CLK PHI2_c +ROUTE 15 0.967 39.PADDI to R5C4D.CLK PHI2_c -------- 0.967 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_26: + Destination Clock Path PHI2 to SLICE_57: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.967 39.PADDI to R6C3B.CLK PHI2_c +ROUTE 15 0.967 39.PADDI to R5C4D.CLK PHI2_c -------- 0.967 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 0.650ns +Passed: The following path meets requirements by 0.641ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q CmdLEDEN (from PHI2_c -) - Destination: FF Data in CmdLEDEN (to PHI2_c -) + Source: FF Q C1Submitted (from PHI2_c -) + Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 0.631ns (45.2% logic, 54.8% route), 3 logic levels. + Delay: 0.622ns (45.8% logic, 54.2% route), 3 logic levels. Constraint Details: - 0.631ns physical path delay SLICE_21 to SLICE_21 meets + 0.622ns physical path delay SLICE_14 to SLICE_20 meets -0.019ns DIN_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.650ns + 0.000ns skew requirement (totaling -0.019ns) by 0.641ns Physical Path Details: - Data path SLICE_21 to SLICE_21: + Data path SLICE_14 to SLICE_20: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R6C4C.CLK to R6C4C.Q0 SLICE_21 (from PHI2_c) -ROUTE 2 0.208 R6C4C.Q0 to R6C4D.B1 CmdLEDEN -CTOF_DEL --- 0.074 R6C4D.B1 to R6C4D.F1 SLICE_82 -ROUTE 1 0.138 R6C4D.F1 to R6C4C.B0 N_132 -CTOF_DEL --- 0.074 R6C4C.B0 to R6C4C.F0 SLICE_21 -ROUTE 1 0.000 R6C4C.F0 to R6C4C.DI0 N_21_i (to PHI2_c) +REG_DEL --- 0.137 R6C3A.CLK to R6C3A.Q0 SLICE_14 (from PHI2_c) +ROUTE 2 0.130 R6C3A.Q0 to R6C3A.D1 C1Submitted +CTOF_DEL --- 0.074 R6C3A.D1 to R6C3A.F1 SLICE_14 +ROUTE 1 0.207 R6C3A.F1 to R5C3C.A0 un1_CmdEnable20_i +CTOF_DEL --- 0.074 R5C3C.A0 to R5C3C.F0 SLICE_20 +ROUTE 1 0.000 R5C3C.F0 to R5C3C.DI0 CmdEnable_s (to PHI2_c) -------- - 0.631 (45.2% logic, 54.8% route), 3 logic levels. + 0.622 (45.8% logic, 54.2% route), 3 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_21: + Source Clock Path PHI2 to SLICE_14: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.967 39.PADDI to R6C4C.CLK PHI2_c +ROUTE 15 0.967 39.PADDI to R6C3A.CLK PHI2_c + -------- + 0.967 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 0.967 39.PADDI to R5C3C.CLK PHI2_c + -------- + 0.967 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.687ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable (from PHI2_c -) + Destination: FF Data in CmdLEDEN (to PHI2_c -) + + Delay: 0.664ns (31.8% logic, 68.2% route), 2 logic levels. + + Constraint Details: + + 0.664ns physical path delay SLICE_20 to SLICE_21 meets + -0.023ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.023ns) by 0.687ns + + Physical Path Details: + + Data path SLICE_20 to SLICE_21: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R5C3C.CLK to R5C3C.Q0 SLICE_20 (from PHI2_c) +ROUTE 2 0.130 R5C3C.Q0 to R5C3B.D0 CmdEnable +CTOF_DEL --- 0.074 R5C3B.D0 to R5C3B.F0 SLICE_73 +ROUTE 5 0.323 R5C3B.F0 to R6C4D.CE XOR8MEG18 (to PHI2_c) + -------- + 0.664 (31.8% logic, 68.2% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 0.967 39.PADDI to R5C3C.CLK PHI2_c -------- 0.967 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_21: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.967 39.PADDI to R6C4C.CLK PHI2_c +ROUTE 15 0.967 39.PADDI to R6C4D.CLK PHI2_c -------- 0.967 (0.0% logic, 100.0% route), 0 logic levels. @@ -1697,7 +1728,7 @@ Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ; ================================================================================ Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; - 388 items scored, 0 timing errors detected. + 392 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- @@ -1712,121 +1743,77 @@ Passed: The following path meets requirements by 0.273ns Constraint Details: - 0.256ns physical path delay SLICE_75 to SLICE_75 meets + 0.256ns physical path delay SLICE_74 to SLICE_74 meets -0.017ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.017ns) by 0.273ns Physical Path Details: - Data path SLICE_75 to SLICE_75: + Data path SLICE_74 to SLICE_74: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.126 R6C4B.CLK to R6C4B.Q0 SLICE_75 (from RCLK_c) -ROUTE 1 0.130 R6C4B.Q0 to R6C4B.M1 CASr (to RCLK_c) +REG_DEL --- 0.126 R6C3D.CLK to R6C3D.Q0 SLICE_74 (from RCLK_c) +ROUTE 1 0.130 R6C3D.Q0 to R6C3D.M1 CASr (to RCLK_c) -------- 0.256 (49.2% logic, 50.8% route), 1 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_75: + Source Clock Path RCLK to SLICE_74: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.333 86.PADDI to R6C4B.CLK RCLK_c +ROUTE 32 0.333 86.PADDI to R6C3D.CLK RCLK_c -------- 0.333 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_75: + Destination Clock Path RCLK to SLICE_74: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.333 86.PADDI to R6C4B.CLK RCLK_c +ROUTE 32 0.333 86.PADDI to R6C3D.CLK RCLK_c -------- 0.333 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 0.277ns +Passed: The following path meets requirements by 0.275ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q PHI2r2 (from RCLK_c +) - Destination: FF Data in PHI2r3 (to RCLK_c +) + Source: FF Q RASr (from RCLK_c +) + Destination: FF Data in RASr2 (to RCLK_c +) - Delay: 0.260ns (48.5% logic, 51.5% route), 1 logic levels. + Delay: 0.258ns (48.8% logic, 51.2% route), 1 logic levels. Constraint Details: - 0.260ns physical path delay SLICE_41 to SLICE_43 meets + 0.258ns physical path delay SLICE_95 to SLICE_95 meets -0.017ns M_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.017ns) by 0.277ns + 0.000ns skew requirement (totaling -0.017ns) by 0.275ns Physical Path Details: - Data path SLICE_41 to SLICE_43: + Data path SLICE_95 to SLICE_95: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.126 R4C5C.CLK to R4C5C.Q1 SLICE_41 (from RCLK_c) -ROUTE 3 0.134 R4C5C.Q1 to R4C5D.M1 PHI2r2 (to RCLK_c) +REG_DEL --- 0.126 R2C4A.CLK to R2C4A.Q0 SLICE_95 (from RCLK_c) +ROUTE 2 0.132 R2C4A.Q0 to R2C4A.M1 RASr (to RCLK_c) -------- - 0.260 (48.5% logic, 51.5% route), 1 logic levels. + 0.258 (48.8% logic, 51.2% route), 1 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_41: + Source Clock Path RCLK to SLICE_95: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.333 86.PADDI to R4C5C.CLK RCLK_c +ROUTE 32 0.333 86.PADDI to R2C4A.CLK RCLK_c -------- 0.333 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_43: + Destination Clock Path RCLK to SLICE_95: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.333 86.PADDI to R4C5D.CLK RCLK_c - -------- - 0.333 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.301ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[17] (from RCLK_c +) - Destination: FF Data in FS[17] (to RCLK_c +) - FF FS[16] - - Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels. - - Constraint Details: - - 0.257ns physical path delay SLICE_1 to SLICE_1 meets - -0.044ns LUT_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.044ns) by 0.301ns - - Physical Path Details: - - Data path SLICE_1 to SLICE_1: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.126 R8C4A.CLK to R8C4A.Q1 SLICE_1 (from RCLK_c) -ROUTE 3 0.131 R8C4A.Q1 to R8C4A.A1 FS[17] (to RCLK_c) - -------- - 0.257 (49.0% logic, 51.0% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_1: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 0.333 86.PADDI to R8C4A.CLK RCLK_c - -------- - 0.333 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_1: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 0.333 86.PADDI to R8C4A.CLK RCLK_c +ROUTE 32 0.333 86.PADDI to R2C4A.CLK RCLK_c -------- 0.333 (0.0% logic, 100.0% route), 0 logic levels. @@ -1900,7 +1887,7 @@ Passed: The following path meets requirements by 0.301ns Name Fanout Delay (ns) Site Resource REG_DEL --- 0.126 R8C3C.CLK to R8C3C.Q1 SLICE_3 (from RCLK_c) -ROUTE 3 0.131 R8C3C.Q1 to R8C3C.A1 FS[13] (to RCLK_c) +ROUTE 4 0.131 R8C3C.Q1 to R8C3C.A1 FS[13] (to RCLK_c) -------- 0.257 (49.0% logic, 51.0% route), 1 logic levels. @@ -1925,43 +1912,88 @@ Passed: The following path meets requirements by 0.301ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS[11] (from RCLK_c +) - Destination: FF Data in FS_cry_0[10] (to RCLK_c +) - FF FS[11] - FF FS[10] + Source: FF Q FS[9] (from RCLK_c +) + Destination: FF Data in FS_cry_0[8] (to RCLK_c +) + FF FS[9] + FF FS[8] Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels. Constraint Details: - 0.257ns physical path delay SLICE_4 to SLICE_4 meets + 0.257ns physical path delay SLICE_5 to SLICE_5 meets -0.044ns LUT_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.044ns) by 0.301ns Physical Path Details: - Data path SLICE_4 to SLICE_4: + Data path SLICE_5 to SLICE_5: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.126 R8C3B.CLK to R8C3B.Q1 SLICE_4 (from RCLK_c) -ROUTE 6 0.131 R8C3B.Q1 to R8C3B.A1 FS[11] (to RCLK_c) +REG_DEL --- 0.126 R8C3A.CLK to R8C3A.Q1 SLICE_5 (from RCLK_c) +ROUTE 3 0.131 R8C3A.Q1 to R8C3A.A1 FS[9] (to RCLK_c) -------- 0.257 (49.0% logic, 51.0% route), 1 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_4: + Source Clock Path RCLK to SLICE_5: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.333 86.PADDI to R8C3B.CLK RCLK_c +ROUTE 32 0.333 86.PADDI to R8C3A.CLK RCLK_c -------- 0.333 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_4: + Destination Clock Path RCLK to SLICE_5: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.333 86.PADDI to R8C3B.CLK RCLK_c +ROUTE 32 0.333 86.PADDI to R8C3A.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.301ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[7] (from RCLK_c +) + Destination: FF Data in FS_cry_0[6] (to RCLK_c +) + FF FS[7] + FF FS[6] + + Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels. + + Constraint Details: + + 0.257ns physical path delay SLICE_6 to SLICE_6 meets + -0.044ns LUT_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.044ns) by 0.301ns + + Physical Path Details: + + Data path SLICE_6 to SLICE_6: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R8C2D.CLK to R8C2D.Q1 SLICE_6 (from RCLK_c) +ROUTE 3 0.131 R8C2D.Q1 to R8C2D.A1 FS[7] (to RCLK_c) + -------- + 0.257 (49.0% logic, 51.0% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_6: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 0.333 86.PADDI to R8C2D.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_6: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 0.333 86.PADDI to R8C2D.CLK RCLK_c -------- 0.333 (0.0% logic, 100.0% route), 0 logic levels. @@ -1990,7 +2022,7 @@ Passed: The following path meets requirements by 0.301ns Name Fanout Delay (ns) Site Resource REG_DEL --- 0.126 R8C2B.CLK to R8C2B.Q1 SLICE_8 (from RCLK_c) -ROUTE 3 0.131 R8C2B.Q1 to R8C2B.A1 FS[3] (to RCLK_c) +ROUTE 2 0.131 R8C2B.Q1 to R8C2B.A1 FS[3] (to RCLK_c) -------- 0.257 (49.0% logic, 51.0% route), 1 logic levels. @@ -2035,7 +2067,7 @@ Passed: The following path meets requirements by 0.302ns Name Fanout Delay (ns) Site Resource REG_DEL --- 0.126 R8C2A.CLK to R8C2A.Q0 SLICE_0 (from RCLK_c) -ROUTE 3 0.131 R8C2A.Q0 to R8C2A.A0 FS[0] (to RCLK_c) +ROUTE 2 0.131 R8C2A.Q0 to R8C2A.A0 FS[0] (to RCLK_c) -------- 0.257 (49.0% logic, 51.0% route), 1 logic levels. @@ -2060,42 +2092,43 @@ Passed: The following path meets requirements by 0.302ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS[16] (from RCLK_c +) - Destination: FF Data in FS[17] (to RCLK_c +) - FF FS[16] + Source: FF Q FS[14] (from RCLK_c +) + Destination: FF Data in FS_cry_0[14] (to RCLK_c +) + FF FS[15] + FF FS[14] Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels. Constraint Details: - 0.257ns physical path delay SLICE_1 to SLICE_1 meets + 0.257ns physical path delay SLICE_2 to SLICE_2 meets -0.045ns LUT_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.045ns) by 0.302ns Physical Path Details: - Data path SLICE_1 to SLICE_1: + Data path SLICE_2 to SLICE_2: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.126 R8C4A.CLK to R8C4A.Q0 SLICE_1 (from RCLK_c) -ROUTE 4 0.131 R8C4A.Q0 to R8C4A.A0 FS[16] (to RCLK_c) +REG_DEL --- 0.126 R8C3D.CLK to R8C3D.Q0 SLICE_2 (from RCLK_c) +ROUTE 3 0.131 R8C3D.Q0 to R8C3D.A0 FS[14] (to RCLK_c) -------- 0.257 (49.0% logic, 51.0% route), 1 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_1: + Source Clock Path RCLK to SLICE_2: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.333 86.PADDI to R8C4A.CLK RCLK_c +ROUTE 32 0.333 86.PADDI to R8C3D.CLK RCLK_c -------- 0.333 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_1: + Destination Clock Path RCLK to SLICE_2: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.333 86.PADDI to R8C4A.CLK RCLK_c +ROUTE 32 0.333 86.PADDI to R8C3D.CLK RCLK_c -------- 0.333 (0.0% logic, 100.0% route), 0 logic levels. @@ -2211,7 +2244,7 @@ Timing summary (Hold): Timing errors: 0 Score: 0 Cumulative negative slack: 0 -Constraints cover 517 paths, 4 nets, and 420 connections (66.35% coverage) +Constraints cover 560 paths, 4 nets, and 447 connections (65.64% coverage) diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_bgn.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_bgn.html index 6b44318..347b274 100644 --- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_bgn.html +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_bgn.html @@ -12,7 +12,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Thu Sep 21 05:38:46 2023 +Sat Jan 06 06:25:15 2024 Command: bitgen -w -g ES:No -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_cck.rpt b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_cck.rpt index e17123a..659c446 100644 --- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_cck.rpt +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_cck.rpt @@ -13,7 +13,7 @@ Hostname: ZANEMACWIN11 Implementation : impl1 -# Written on Thu Sep 21 05:38:20 2023 +# Written on Sat Jan 6 06:24:51 2024 ##### DESIGN INFO ####################################################### @@ -48,8 +48,8 @@ nCRAS RCLK | No paths | No paths | No p 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. -@W:"//mac/icloud/repos/ram2gs/cpld/ram2gs.sdc":2:0:2:0|Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. @W:"//mac/icloud/repos/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small. +@W:"//mac/icloud/repos/ram2gs/cpld/ram2gs.sdc":2:0:2:0|Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. @W:"//mac/icloud/repos/ram2gs/cpld/ram2gs.sdc":3:0:3:0|Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. @W:"//mac/icloud/repos/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small. @W:"//mac/icloud/repos/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small. diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_iotiming.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_iotiming.html index 150fbdc..5bcc09e 100644 --- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_iotiming.html +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_iotiming.html @@ -38,7 +38,7 @@ Performance Hardware Data Status: Version 1.124. // Package: TQFP100 // ncd File: ram2gs_lcmxo256c_impl1.ncd // Version: Diamond (64-bit) 3.12.1.454 -// Written on Thu Sep 21 05:38:44 2023 +// Written on Sat Jan 06 06:25:13 2024 // M: Minimum Performance Grade // iotiming RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO256C/promote.xml @@ -50,99 +50,99 @@ Worst Case Results across Performance Grades (M, 5, 4, 3): Port Clock Edge Setup Performance_Grade Hold Performance_Grade ---------------------------------------------------------------------- -CROW[0] nCRAS F -0.006 M 1.904 3 -CROW[1] nCRAS F -0.006 M 1.904 3 -Din[0] PHI2 F 4.101 3 2.207 3 -Din[0] nCCAS F 1.552 3 -0.018 M -Din[1] PHI2 F 2.668 3 3.026 3 -Din[1] nCCAS F 0.606 3 0.745 3 -Din[2] PHI2 F 2.073 3 2.917 3 -Din[2] nCCAS F 0.500 3 0.619 3 -Din[3] PHI2 F 2.620 3 3.334 3 -Din[3] nCCAS F -0.089 M 1.336 3 -Din[4] PHI2 F 5.116 3 2.411 3 -Din[4] nCCAS F 0.293 3 1.125 3 -Din[5] PHI2 F 5.590 3 2.084 3 -Din[5] nCCAS F 0.435 3 0.979 3 -Din[6] PHI2 F 5.951 3 1.726 3 -Din[6] nCCAS F 1.305 3 0.253 3 -Din[7] PHI2 F 4.412 3 1.404 3 -Din[7] nCCAS F 0.195 3 1.215 3 -MAin[0] PHI2 F 3.306 3 1.176 3 -MAin[0] nCRAS F -0.132 M 2.336 3 -MAin[1] PHI2 F 2.656 3 2.511 3 -MAin[1] nCRAS F -0.034 M 2.014 3 -MAin[2] PHI2 F 6.839 3 -0.310 M -MAin[2] nCRAS F -0.154 M 2.424 3 -MAin[3] PHI2 F 6.871 3 -0.311 M -MAin[3] nCRAS F -0.015 M 1.928 3 -MAin[4] PHI2 F 7.111 3 -0.361 M -MAin[4] nCRAS F 0.370 3 1.590 3 -MAin[5] PHI2 F 7.075 3 -0.353 M -MAin[5] nCRAS F -0.126 M 2.320 3 -MAin[6] PHI2 F 6.794 3 -0.295 M -MAin[6] nCRAS F 0.010 3 1.885 3 -MAin[7] PHI2 F 6.926 3 -0.324 M -MAin[7] nCRAS F 0.319 3 1.622 3 -MAin[8] nCRAS F -0.038 M 2.031 3 -MAin[9] nCRAS F 0.366 3 1.596 3 -PHI2 RCLK R 2.295 3 -0.174 M -UFMSDO RCLK R 1.364 3 0.511 3 -nCCAS RCLK R 2.300 3 -0.185 M -nCCAS nCRAS F 0.216 3 1.721 3 -nCRAS RCLK R 4.548 3 -0.507 M -nFWE PHI2 F 6.729 3 -0.281 M -nFWE nCRAS F -0.037 M 2.025 3 +CROW[0] nCRAS F -0.006 M 1.907 3 +CROW[1] nCRAS F -0.006 M 1.907 3 +Din[0] PHI2 F 4.304 3 2.935 3 +Din[0] nCCAS F 0.567 3 0.723 3 +Din[1] PHI2 F 4.920 3 3.034 3 +Din[1] nCCAS F 0.414 3 0.851 3 +Din[2] PHI2 F 3.171 3 3.327 3 +Din[2] nCCAS F 0.909 3 0.432 3 +Din[3] PHI2 F 4.332 3 2.525 3 +Din[3] nCCAS F 0.038 3 1.155 3 +Din[4] PHI2 F 5.624 3 2.635 3 +Din[4] nCCAS F 1.448 3 -0.041 M +Din[5] PHI2 F 4.126 3 2.124 3 +Din[5] nCCAS F 1.046 3 0.159 3 +Din[6] PHI2 F 5.565 3 2.394 3 +Din[6] nCCAS F 0.563 3 0.729 3 +Din[7] PHI2 F 5.293 3 1.654 3 +Din[7] nCCAS F 0.719 3 0.583 3 +MAin[0] PHI2 F 8.072 3 -0.164 M +MAin[0] nCRAS F -0.128 M 2.331 3 +MAin[1] PHI2 F 7.487 3 -0.178 M +MAin[1] nCRAS F -0.129 M 2.331 3 +MAin[2] PHI2 F 6.793 3 -0.034 M +MAin[2] nCRAS F -0.129 M 2.331 3 +MAin[3] PHI2 F 7.235 3 -0.226 M +MAin[3] nCRAS F -0.035 M 2.023 3 +MAin[4] PHI2 F 7.305 3 -0.207 M +MAin[4] nCRAS F 0.428 3 1.517 3 +MAin[5] PHI2 F 7.672 3 -0.236 M +MAin[5] nCRAS F -0.037 M 2.028 3 +MAin[6] PHI2 F 9.015 3 -0.710 M +MAin[6] nCRAS F -0.003 M 1.896 3 +MAin[7] PHI2 F 7.764 3 -0.441 M +MAin[7] nCRAS F -0.126 M 2.324 3 +MAin[8] nCRAS F -0.038 M 2.034 3 +MAin[9] nCRAS F 0.206 3 1.728 3 +PHI2 RCLK R 2.769 3 -0.274 M +UFMSDO RCLK R 1.753 3 -0.052 M +nCCAS RCLK R 1.935 3 -0.108 M +nCCAS nCRAS F 0.843 3 1.179 3 +nCRAS RCLK R 1.093 3 0.277 3 +nFWE PHI2 F 4.435 3 0.640 3 +nFWE nCRAS F 1.163 3 0.894 3 // Clock to Output Delay Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade ------------------------------------------------------------------------ -LED RCLK R 13.764 3 4.455 M -LED nCRAS F 16.500 3 4.993 M -RA[0] RCLK R 10.114 3 2.098 M -RA[0] nCRAS F 11.793 3 2.420 M -RA[10] RCLK R 8.581 3 1.780 M +LED RCLK R 15.407 3 4.713 M +LED nCRAS F 17.685 3 5.215 M +RA[0] RCLK R 10.436 3 2.152 M +RA[0] nCRAS F 11.488 3 2.330 M +RA[10] RCLK R 8.093 3 1.668 M RA[11] PHI2 R 9.420 3 1.925 M -RA[1] RCLK R 11.717 3 2.429 M -RA[1] nCRAS F 12.171 3 2.492 M -RA[2] RCLK R 9.514 3 1.971 M -RA[2] nCRAS F 11.301 3 2.319 M -RA[3] RCLK R 10.525 3 2.169 M -RA[3] nCRAS F 12.042 3 2.459 M -RA[4] RCLK R 11.387 3 2.343 M -RA[4] nCRAS F 12.532 3 2.543 M -RA[5] RCLK R 10.114 3 2.098 M -RA[5] nCRAS F 10.936 3 2.242 M -RA[6] RCLK R 9.514 3 1.971 M -RA[6] nCRAS F 10.544 3 2.165 M -RA[7] RCLK R 10.933 3 2.261 M -RA[7] nCRAS F 11.162 3 2.268 M -RA[8] RCLK R 10.591 3 2.178 M -RA[8] nCRAS F 11.951 3 2.426 M -RA[9] RCLK R 9.668 3 1.989 M -RA[9] nCRAS F 10.889 3 2.209 M -RBA[0] nCRAS F 8.922 3 1.828 M -RBA[1] nCRAS F 10.649 3 2.177 M -RCKE RCLK R 8.493 3 1.760 M -RDQMH RCLK R 10.817 3 2.273 M -RDQML RCLK R 11.739 3 2.471 M -RD[0] nCCAS F 9.545 3 2.093 M -RD[1] nCCAS F 8.834 3 1.965 M -RD[2] nCCAS F 9.535 3 2.092 M -RD[3] nCCAS F 9.531 3 2.092 M -RD[4] nCCAS F 9.303 3 2.066 M -RD[5] nCCAS F 11.766 3 2.555 M -RD[6] nCCAS F 9.303 3 2.066 M -RD[7] nCCAS F 10.470 3 2.285 M -UFMCLK RCLK R 9.190 3 1.937 M +RA[1] RCLK R 10.958 3 2.270 M +RA[1] nCRAS F 12.371 3 2.529 M +RA[2] RCLK R 10.892 3 2.242 M +RA[2] nCRAS F 11.786 3 2.402 M +RA[3] RCLK R 10.561 3 2.184 M +RA[3] nCRAS F 12.541 3 2.560 M +RA[4] RCLK R 10.909 3 2.257 M +RA[4] nCRAS F 12.060 3 2.456 M +RA[5] RCLK R 9.970 3 2.057 M +RA[5] nCRAS F 12.271 3 2.508 M +RA[6] RCLK R 9.222 3 1.920 M +RA[6] nCRAS F 10.844 3 2.210 M +RA[7] RCLK R 9.613 3 1.981 M +RA[7] nCRAS F 11.686 3 2.379 M +RA[8] RCLK R 9.617 3 1.982 M +RA[8] nCRAS F 11.487 3 2.339 M +RA[9] RCLK R 9.762 3 2.016 M +RA[9] nCRAS F 11.488 3 2.337 M +RBA[0] nCRAS F 8.925 3 1.828 M +RBA[1] nCRAS F 10.608 3 2.153 M +RCKE RCLK R 7.609 3 1.570 M +RDQMH RCLK R 10.915 3 2.299 M +RDQML RCLK R 11.554 3 2.433 M +RD[0] nCCAS F 8.539 3 1.899 M +RD[1] nCCAS F 9.248 3 2.027 M +RD[2] nCCAS F 9.706 3 2.118 M +RD[3] nCCAS F 8.539 3 1.899 M +RD[4] nCCAS F 9.228 3 2.015 M +RD[5] nCCAS F 8.772 3 1.924 M +RD[6] nCCAS F 8.539 3 1.899 M +RD[7] nCCAS F 9.706 3 2.118 M +UFMCLK RCLK R 8.007 3 1.714 M UFMSDI RCLK R 8.007 3 1.714 M -nRCAS RCLK R 8.209 3 1.697 M +nRCAS RCLK R 8.120 3 1.681 M nRCS RCLK R 6.854 3 1.431 M -nRRAS RCLK R 8.021 3 1.650 M +nRRAS RCLK R 8.089 3 1.669 M nRWE RCLK R 6.854 3 1.431 M -nUFMCS RCLK R 9.650 3 2.046 M +nUFMCS RCLK R 8.732 3 1.846 M WARNING: you must also run trce with hold speed: 3 WARNING: you must also run trce with setup speed: M diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvo.sdf b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvo.sdf index 5105ab8..5b37944 100644 --- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvo.sdf +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvo.sdf @@ -1,7 +1,7 @@ (DELAYFILE (SDFVERSION "3.0") (DESIGN "RAM2GS") - (DATE "Thu Sep 21 05:38:31 2023") + (DATE "Sat Jan 06 06:25:00 2024") (VENDOR "Lattice") (PROGRAM "ldbanno") (VERSION "Diamond (64-bit) 3.12.1.454") @@ -172,8 +172,6 @@ (INSTANCE SLICE_9) (DELAY (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) - (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) @@ -196,6 +194,7 @@ (INSTANCE SLICE_14) (DELAY (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) @@ -215,40 +214,18 @@ ) ) (CELL - (CELLTYPE "SLICE_19") - (INSTANCE SLICE_19) + (CELLTYPE "SLICE_20") + (INSTANCE SLICE_20) (DELAY (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) - (IOPATH CLK Q0 (515:537:560)(515:537:560)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) - (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1000:1000:1000)) - (WIDTH (negedge CLK) (1000:1000:1000)) - ) - ) - (CELL - (CELLTYPE "SLICE_20") - (INSTANCE SLICE_20) - (DELAY - (ABSOLUTE - (IOPATH B1 OFX0 (496:555:615)(496:555:615)) - (IOPATH A1 OFX0 (496:555:615)(496:555:615)) - (IOPATH D0 OFX0 (508:569:631)(508:569:631)) - (IOPATH C0 OFX0 (508:569:631)(508:569:631)) - (IOPATH B0 OFX0 (508:569:631)(508:569:631)) - (IOPATH A0 OFX0 (508:569:631)(508:569:631)) - (IOPATH M0 OFX0 (405:453:501)(405:453:501)) (IOPATH CLK Q0 (560:586:613)(560:586:613)) ) ) @@ -265,10 +242,10 @@ (INSTANCE SLICE_21) (DELAY (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) @@ -335,7 +312,6 @@ (INSTANCE SLICE_29) (DELAY (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) @@ -343,10 +319,12 @@ (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) ) ) (TIMINGCHECK (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) ) (TIMINGCHECK (WIDTH (posedge CLK) (1000:1000:1000)) @@ -429,6 +407,7 @@ (INSTANCE SLICE_33) (DELAY (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) @@ -447,11 +426,35 @@ (WIDTH (negedge CLK) (1000:1000:1000)) ) ) + (CELL + (CELLTYPE "SLICE_38") + (INSTANCE SLICE_38) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) (CELL (CELLTYPE "SLICE_39") (INSTANCE SLICE_39) (DELAY (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH C0 F0 (301:336:371)(301:336:371)) @@ -500,7 +503,6 @@ (INSTANCE SLICE_42) (DELAY (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) @@ -607,12 +609,10 @@ (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (515:537:560)(515:537:560)) - (IOPATH CLK Q1 (515:537:560)(515:537:560)) ) ) (TIMINGCHECK (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) - (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) ) (TIMINGCHECK (WIDTH (posedge CLK) (1000:1000:1000)) @@ -633,12 +633,10 @@ (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (515:537:560)(515:537:560)) - (IOPATH CLK Q1 (515:537:560)(515:537:560)) ) ) (TIMINGCHECK (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) - (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) ) (TIMINGCHECK (WIDTH (posedge CLK) (1000:1000:1000)) @@ -671,11 +669,8 @@ (INSTANCE SLICE_56) (DELAY (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) - (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (560:586:613)(560:586:613)) @@ -696,8 +691,6 @@ (INSTANCE SLICE_57) (DELAY (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) - (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) @@ -744,7 +737,6 @@ (INSTANCE SLICE_59) (DELAY (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) @@ -768,7 +760,6 @@ (INSTANCE SLICE_60) (DELAY (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) @@ -906,6 +897,7 @@ (INSTANCE SLICE_66) (DELAY (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) @@ -913,26 +905,14 @@ (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) - (IOPATH CLK Q0 (560:586:613)(560:586:613)) - (IOPATH CLK Q1 (560:586:613)(560:586:613)) ) ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1000:1000:1000)) - (WIDTH (negedge CLK) (1000:1000:1000)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) - (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) - (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) - ) ) (CELL (CELLTYPE "SLICE_67") (INSTANCE SLICE_67) (DELAY (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) @@ -967,78 +947,21 @@ (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) ) ) + (TIMINGCHECK + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) ) (CELL (CELLTYPE "SLICE_69") (INSTANCE SLICE_69) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) - (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH D0 F0 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) - ) - ) - ) - (CELL - (CELLTYPE "SLICE_70") - (INSTANCE SLICE_70) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) - (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) - (IOPATH CLK Q0 (515:537:560)(515:537:560)) - (IOPATH CLK Q1 (515:537:560)(515:537:560)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) - (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1000:1000:1000)) - (WIDTH (negedge CLK) (1000:1000:1000)) - ) - ) - (CELL - (CELLTYPE "SLICE_71") - (INSTANCE SLICE_71) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) - (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH D0 F0 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) - (IOPATH CLK Q0 (515:537:560)(515:537:560)) - (IOPATH CLK Q1 (515:537:560)(515:537:560)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) - (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1000:1000:1000)) - (WIDTH (negedge CLK) (1000:1000:1000)) - ) - ) - (CELL - (CELLTYPE "SLICE_72") - (INSTANCE SLICE_72) (DELAY (ABSOLUTE (IOPATH C1 F1 (301:336:371)(301:336:371)) @@ -1062,6 +985,51 @@ (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) ) ) + (CELL + (CELLTYPE "SLICE_70") + (INSTANCE SLICE_70) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_71") + (INSTANCE SLICE_71) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_72") + (INSTANCE SLICE_72) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) (CELL (CELLTYPE "SLICE_73") (INSTANCE SLICE_73) @@ -1084,7 +1052,7 @@ (TIMINGCHECK (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) - (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) ) ) (CELL @@ -1098,23 +1066,25 @@ (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) - (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) ) ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) (TIMINGCHECK (WIDTH (posedge CLK) (1000:1000:1000)) (WIDTH (negedge CLK) (1000:1000:1000)) ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) - (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) - ) ) (CELL (CELLTYPE "SLICE_75") (INSTANCE SLICE_75) (DELAY (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) @@ -1139,6 +1109,8 @@ (INSTANCE SLICE_76) (DELAY (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) @@ -1161,6 +1133,36 @@ (CELL (CELLTYPE "SLICE_77") (INSTANCE SLICE_77) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_78") + (INSTANCE SLICE_78) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_79") + (INSTANCE SLICE_79) (DELAY (ABSOLUTE (IOPATH B1 F1 (301:336:371)(301:336:371)) @@ -1182,55 +1184,6 @@ (WIDTH (negedge CLK) (1000:1000:1000)) ) ) - (CELL - (CELLTYPE "SLICE_78") - (INSTANCE SLICE_78) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH D0 F0 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) - (IOPATH CLK Q0 (560:586:613)(560:586:613)) - (IOPATH CLK Q1 (560:586:613)(560:586:613)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1000:1000:1000)) - (WIDTH (negedge CLK) (1000:1000:1000)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) - (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) - ) - ) - (CELL - (CELLTYPE "SLICE_79") - (INSTANCE SLICE_79) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH D0 F0 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) - (IOPATH CLK Q0 (560:586:613)(560:586:613)) - (IOPATH CLK Q1 (560:586:613)(560:586:613)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1000:1000:1000)) - (WIDTH (negedge CLK) (1000:1000:1000)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) - (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) - ) - ) (CELL (CELLTYPE "SLICE_80") (INSTANCE SLICE_80) @@ -1242,19 +1195,8 @@ (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) - (IOPATH CLK Q0 (560:586:613)(560:586:613)) - (IOPATH CLK Q1 (560:586:613)(560:586:613)) ) ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1000:1000:1000)) - (WIDTH (negedge CLK) (1000:1000:1000)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) - (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) - (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) - ) ) (CELL (CELLTYPE "SLICE_81") @@ -1269,6 +1211,21 @@ (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_82") + (INSTANCE SLICE_82) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (560:586:613)(560:586:613)) (IOPATH CLK Q1 (560:586:613)(560:586:613)) ) @@ -1283,8 +1240,8 @@ ) ) (CELL - (CELLTYPE "SLICE_82") - (INSTANCE SLICE_82) + (CELLTYPE "SLICE_83") + (INSTANCE SLICE_83) (DELAY (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) @@ -1295,28 +1252,6 @@ (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) - (IOPATH CLK Q0 (515:537:560)(515:537:560)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1000:1000:1000)) - (WIDTH (negedge CLK) (1000:1000:1000)) - ) - ) - (CELL - (CELLTYPE "SLICE_83") - (INSTANCE SLICE_83) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (560:586:613)(560:586:613)) (IOPATH CLK Q1 (560:586:613)(560:586:613)) ) @@ -1344,12 +1279,64 @@ (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) ) ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) ) (CELL (CELLTYPE "SLICE_85") (INSTANCE SLICE_85) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_86") + (INSTANCE SLICE_86) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_87") + (INSTANCE SLICE_87) (DELAY (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) @@ -1374,8 +1361,82 @@ ) ) (CELL - (CELLTYPE "SLICE_86") - (INSTANCE SLICE_86) + (CELLTYPE "SLICE_88") + (INSTANCE SLICE_88) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_89") + (INSTANCE SLICE_89) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_90") + (INSTANCE SLICE_90) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_91") + (INSTANCE SLICE_91) (DELAY (ABSOLUTE (IOPATH B1 F1 (301:336:371)(301:336:371)) @@ -1387,8 +1448,8 @@ ) ) (CELL - (CELLTYPE "SLICE_87") - (INSTANCE SLICE_87) + (CELLTYPE "SLICE_92") + (INSTANCE SLICE_92) (DELAY (ABSOLUTE (IOPATH C1 F1 (301:336:371)(301:336:371)) @@ -1402,8 +1463,142 @@ ) ) (CELL - (CELLTYPE "SLICE_88") - (INSTANCE SLICE_88) + (CELLTYPE "SLICE_93") + (INSTANCE SLICE_93) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_94") + (INSTANCE SLICE_94) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_95") + (INSTANCE SLICE_95) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_96") + (INSTANCE SLICE_96) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_97") + (INSTANCE SLICE_97) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_98") + (INSTANCE SLICE_98) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_99") + (INSTANCE SLICE_99) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_100") + (INSTANCE SLICE_100) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_101") + (INSTANCE SLICE_101) (DELAY (ABSOLUTE (IOPATH C1 F1 (301:336:371)(301:336:371)) @@ -1422,97 +1617,6 @@ (TIMINGCHECK (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) - (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) - ) - ) - (CELL - (CELLTYPE "SLICE_89") - (INSTANCE SLICE_89) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) - ) - ) - ) - (CELL - (CELLTYPE "SLICE_90") - (INSTANCE SLICE_90) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) - ) - ) - ) - (CELL - (CELLTYPE "SLICE_91") - (INSTANCE SLICE_91) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) - ) - ) - ) - (CELL - (CELLTYPE "SLICE_92") - (INSTANCE SLICE_92) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) - ) - ) - ) - (CELL - (CELLTYPE "SLICE_93") - (INSTANCE SLICE_93) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) - ) - ) - ) - (CELL - (CELLTYPE "SLICE_94") - (INSTANCE SLICE_94) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) - (IOPATH CLK Q0 (515:537:560)(515:537:560)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) - (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1000:1000:1000)) - (WIDTH (negedge CLK) (1000:1000:1000)) ) ) (CELL @@ -2284,11 +2388,10 @@ (DELAY (ABSOLUTE (INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_0/Q1 SLICE_72/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_0/Q1 SLICE_84/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_69/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_89/A1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_0/Q0 SLICE_0/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_0/Q0 SLICE_68/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_0/Q0 SLICE_69/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q0 SLICE_94/A0 (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_0/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_1/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_2/CLK (0:0:0)(0:0:0)) @@ -2298,12 +2401,12 @@ (INTERCONNECT RCLK_I/PADDI SLICE_6/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_7/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_8/CLK (0:0:0)(0:0:0)) - (INTERCONNECT RCLK_I/PADDI SLICE_19/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_29/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_30/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_31/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_32/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_33/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_38/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_41/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_42/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_43/CLK (0:0:0)(0:0:0)) @@ -2318,94 +2421,87 @@ (INTERCONNECT RCLK_I/PADDI SLICE_62/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_63/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_64/CLK (0:0:0)(0:0:0)) - (INTERCONNECT RCLK_I/PADDI SLICE_75/CLK (0:0:0)(0:0:0)) - (INTERCONNECT RCLK_I/PADDI SLICE_82/CLK (0:0:0)(0:0:0)) - (INTERCONNECT RCLK_I/PADDI SLICE_94/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_68/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_74/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_95/CLK (0:0:0)(0:0:0)) (INTERCONNECT SLICE_0/FCO SLICE_8/FCI (0:0:0)(0:0:0)) (INTERCONNECT SLICE_1/Q1 SLICE_1/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q1 SLICE_81/D1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q1 SLICE_81/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q1 SLICE_80/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q1 SLICE_86/D1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q0 SLICE_66/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q0 SLICE_72/B1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q0 SLICE_74/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_69/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_86/D0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_2/FCO SLICE_1/FCI (0:0:0)(0:0:0)) (INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q1 SLICE_81/C1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q1 SLICE_81/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_86/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_86/C0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q0 SLICE_74/B1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q0 SLICE_81/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_86/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_86/B0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_3/FCO SLICE_2/FCI (0:0:0)(0:0:0)) (INTERCONNECT SLICE_3/Q1 SLICE_3/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q1 SLICE_81/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q1 SLICE_81/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_67/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_69/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_80/B0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_3/Q0 SLICE_3/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q0 SLICE_72/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q0 SLICE_81/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_86/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_86/A0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_4/FCO SLICE_3/FCI (0:0:0)(0:0:0)) (INTERCONNECT SLICE_4/Q1 SLICE_4/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q1 SLICE_56/B1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_4/Q1 SLICE_64/B1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/Q1 SLICE_72/C0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/Q1 SLICE_74/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/Q1 SLICE_84/D1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/Q1 SLICE_87/C0 (0:0:0)(0:0:0)) + (INTERCONNECT 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SLICE_89/B0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_80/Q1 SLICE_86/B0 (0:0:0)(0:0:0)) - (INTERCONNECT nFWE_I/PADDI SLICE_81/M0 (0:0:0)(0:0:0)) - (INTERCONNECT nFWE_I/PADDI SLICE_81/M1 (0:0:0)(0:0:0)) - (INTERCONNECT nFWE_I/PADDI SLICE_88/C1 (0:0:0)(0:0:0)) - (INTERCONNECT nFWE_I/PADDI SLICE_88/B0 (0:0:0)(0:0:0)) - (INTERCONNECT CROW\[1\]_I/PADDI SLICE_83/M1 (0:0:0)(0:0:0)) - (INTERCONNECT CROW\[0\]_I/PADDI SLICE_83/M0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_83/Q0 RBA\[0\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_83/Q1 RBA\[1\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_85/Q0 RD\[2\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_85/Q1 RD\[3\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_86/F0 RA\[9\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_86/F1 RDQML_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_88/F0 RD\[0\]_I/PADDT (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_88/F0 RD\[7\]_I/PADDT (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_88/F0 RD\[6\]_I/PADDT (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_88/F0 RD\[5\]_I/PADDT (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_88/F0 RD\[4\]_I/PADDT (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_88/F0 RD\[3\]_I/PADDT (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_88/F0 RD\[2\]_I/PADDT (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_88/F0 RD\[1\]_I/PADDT (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_88/Q0 SLICE_92/B1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_88/Q1 SLICE_91/B1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_89/F0 RA\[8\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_89/F1 RDQMH_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_90/F0 RA\[0\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_91/F0 RA\[1\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_91/F1 RA\[7\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_92/F0 RA\[2\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_92/F1 RA\[6\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_93/F0 RA\[3\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_93/F1 RA\[5\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_94/Q0 RA\[10\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 SLICE_78/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/F1 SLICE_74/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/F1 SLICE_78/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_74/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_75/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_78/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_79/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_82/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_83/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_85/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/Q0 SLICE_77/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/Q1 SLICE_77/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_76/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_81/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_89/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_93/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_98/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/F1 SLICE_76/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/Q0 SLICE_100/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/Q1 SLICE_100/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93/Q1 SLICE_77/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/Q0 SLICE_77/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/F1 SLICE_77/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/F1 SLICE_79/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F0 SLICE_77/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F0 SLICE_79/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/F0 SLICE_77/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/F0 SLICE_78/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_79/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_81/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_89/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_99/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F1 SLICE_79/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F1 SLICE_81/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/Q1 SLICE_100/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/F1 SLICE_81/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/F1 SLICE_82/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/Q0 RD\[2\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/Q1 RD\[3\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_83/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_91/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_91/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_96/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[8\]_I/PADDI SLICE_83/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[8\]_I/PADDI SLICE_96/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/Q0 SLICE_96/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/Q1 SLICE_91/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/Q0 RD\[0\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/Q1 RD\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F1 SLICE_85/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F1 SLICE_88/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/Q0 SLICE_98/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/Q1 SLICE_99/B0 (0:0:0)(0:0:0)) + (INTERCONNECT CROW\[1\]_I/PADDI SLICE_90/M1 (0:0:0)(0:0:0)) + (INTERCONNECT CROW\[0\]_I/PADDI SLICE_90/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/Q0 RBA\[0\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/Q1 RBA\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/F0 RA\[9\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/F1 RDQMH_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93/Q0 SLICE_100/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93/F1 RA\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96/F0 RA\[8\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96/F1 RDQML_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97/F0 RA\[3\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97/F1 RA\[0\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/F0 RA\[4\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/F1 RA\[2\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99/F0 RA\[5\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99/F1 RA\[7\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F1 RD\[0\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F1 RD\[7\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F1 RD\[6\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F1 RD\[5\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F1 RD\[4\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F1 RD\[3\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F1 RD\[2\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F1 RD\[1\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/F1 RA\[6\]_I/PADDO (0:0:0)(0:0:0)) (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_I/PADDO (0:0:0)(0:0:0)) (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_I/PADDO (0:0:0)(0:0:0)) (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_I/PADDO (0:0:0)(0:0:0)) diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvo.vo b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvo.vo index 0bca839..7e92070 100644 --- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvo.vo +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvo.vo @@ -2,8 +2,8 @@ // Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454 // ldbanno -n Verilog -o RAM2GS_LCMXO256C_impl1_mapvo.vo -w -neg -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd -// Netlist created on Thu Sep 21 05:38:29 2023 -// Netlist written on Thu Sep 21 05:38:31 2023 +// Netlist created on Sat Jan 06 06:24:57 2024 +// Netlist written on Sat Jan 06 06:25:00 2024 // Design is for device LCMXO256C // Design is for package TQFP100 // Design is for performance grade 3 @@ -28,45 +28,48 @@ module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, \FS_cry[15] , \FS[15] , \FS[14] , \FS_cry[13] , \FS[13] , \FS[12] , \FS_cry[11] , \FS[11] , \FS[10] , \FS_cry[9] , \FS[9] , \FS[8] , \FS_cry[7] , \FS[7] , \FS[6] , \FS_cry[5] , \FS[5] , \FS[4] , - \FS_cry[3] , \FS[3] , \FS[2] , N_147, \MAin_c[0] , CmdEnable17_0_a2_4, - CmdEnable17_0_a2_3, CmdEnable16, CmdEnable17, C1WR_0_a2, ADSubmitted, - ADSubmitted_r, PHI2_c, CmdEnable16_0_a2_5, CmdEnable16_0_a2_4, - \MAin_c[1] , C1Submitted, C1Submitted_RNO, \S[1] , RASr2, \IS[3] , - CO0, N_177_i, Ready_0_sqmuxa_0_a3_2, CmdEnable, un1_CMDWR, - CmdEnable_s, N_128, \Din_c[5] , \Din_c[3] , N_152, N_133, N_132, - LEDEN, N_21_i, XOR8MEG18, CmdLEDEN, PHI2r3, PHI2r2, InitReady, - CmdSubmitted, CmdSubmitted_1_sqmuxa, N_460_0, N_136, N_43, Cmdn8MEGEN, - CmdEnable16_4, n8MEGEN, Cmdn8MEGEN_4_u_i_0, N_19_i, nRRAS_5_u_i_0, - N_160, N_155, \IS[0] , Ready, N_64_i_i, N_24, \IS[2] , \IS[1] , - N_60_i_i, N_56_i, N_159_i, N_159, N_61_i_i, RA10s_i, - UFMSDI_ens2_i_a2_4_2, N_126, N_51, InitReady3, N_461_0, - UFMSDI_ens2_i_a0, nCRAS_c, CBR, UFMSDO_c, N_70, N_33, LED_c, - un1_Din_4, XOR8MEG, \Din_c[6] , RA11_2, Ready_fast, \RA_c[11] , N_171, - FWEr_fast, CASr2, RCKEEN_8_u_1, RCKEEN_8_u_0_0, RCKEEN_8, PHI2r, - RCKEEN, RASr3, RASr, RCKE_2, RCKE_c, m18_0_a3_3, \S_0_i_o2[1] , N_165, - N_462_0, Ready_0_sqmuxa, N_463_0, nRRAS_0_sqmuxa, N_129, - UFMCLK_r_i_a2_2_2, CmdUFMCLK, UFMCLK_r_i_m4_xx_mm_1, UFMCLK_c, - nUFMCS15, N_139_i, UFMCLK_RNO, UFMSDI_r_xx_mm_1, UFMSDI_c, UFMSDI_RNO, - nRowColSel, \RowA[4] , \MAin_c[4] , \Din_c[4] , nCCAS_c, \RA_c[4] , - \WRD[4] , \WRD[5] , \Bank[7] , \Bank[6] , \Bank[5] , \Bank[2] , - \Din_c[7] , \WRD[6] , C1WR_0_a2_0_11, \WRD[7] , \Din_c[2] , - \Din_c[0] , XOR8MEG_3_u_0_a3_2, \Din_c[1] , XOR8MEG_3, N_69, N_31, - N_151, g0_1, nRCAS_0_sqmuxa_1, N_41, N_37_i, nRCAS_c, CASr3, - RCKEEN_8_u_0_a2_1_out, N_28_i_1, N_28_i, nRCS_c, N_24_i, nRRAS_c, - CBR_fast, m18_0_a2_1, G_17_1, FWEr, N_39_i, nRWE_c, N_179, - nRowColSel_0_0, nUFMCS_s_0_N_5_i_N_2L1, nUFMCS_c, nUFMCS_s_0_N_5_i, - CmdUFMCS, N_95_5, N_95_3, \RowA[0] , \RowA[1] , \MAin_c[5] , - CmdUFMCLK_1_sqmuxa, \RowA[5] , un1_FS_14_i_a2_0_1, N_137_8, N_137_6, - un1_FS_13_i_a2_1, C1WR_0_a2_0_10, \Bank[1] , \Bank[0] , \MAin_c[7] , - \MAin_c[6] , C1WR_0_a2_0_4, C1WR_0_a2_0_3, \Bank[4] , \Bank[3] , - UFMSDI_ens2_i_o2_0_3, \MAin_c[3] , \MAin_c[2] , \RowA[2] , \RowA[3] , - CmdUFMSDI, CASr, CmdEnable16_1, m6_0_a2_2, \WRD[0] , \WRD[1] , - g4_0_0_0, \MAin_c[9] , \MAin_c[8] , \RowA[8] , \RowA[9] , nFWE_c, - \CROW_c[1] , \CROW_c[0] , \RBA_c[0] , \RBA_c[1] , \WRD[2] , \WRD[3] , - \RA_c[9] , RDQML_c, RD_1_i, \RowA[6] , \RowA[7] , \RA_c[8] , RDQMH_c, - \RA_c[0] , \RA_c[1] , \RA_c[7] , \RA_c[2] , \RA_c[6] , \RA_c[3] , - \RA_c[5] , \RA_c[10] , \RD_in[0] , \RD_in[7] , \RD_in[6] , \RD_in[5] , - \RD_in[4] , \RD_in[3] , \RD_in[2] , \RD_in[1] , VCCI, GNDI_TSALL; + \FS_cry[3] , \FS[3] , \FS[2] , C1WR, ADWR, CmdEnable16, CmdEnable17, + N_183_i, ADSubmitted, ADSubmitted_r, PHI2_c, un1_CmdEnable20_0_a3_0_2, + N_121, C1Submitted, C1Submitted_RNO, un1_CmdEnable20_i, + CmdEnable16_0_a3_4, CmdEnable16_0_a3_5, CmdEnable_0_sqmuxa, CmdEnable, + CmdEnable_s, N_45, \Din_c[1] , CmdLEDEN_4_u_i_a2_0_0, CmdLEDEN, N_95, + LEDEN, CmdLEDEN_4_u_i_0, N_14_i, XOR8MEG18, PHI2r3, PHI2r2, InitReady, + CmdSubmitted, CmdSubmitted_1_sqmuxa, N_428_0, N_134, \Din_c[0] , + Cmdn8MEGEN, n8MEGEN, Cmdn8MEGEN_4_u_i_0, N_12_i, \IS[2] , \IS[1] , + \IS[0] , Ready, N_148, N_77_i_i, CASr2, N_160, CASr3, N_74_i_i, + N_69_i, N_153_i, \IS[3] , N_75_i_i, RA10s_i, UFMSDI_ens2_i_a2_4_2, + N_128, N_34, InitReady3, N_429_0, UFMSDI_ens2_i_a0, nCRAS_c, CBR, + UFMSDO_c, N_49, N_26, LED_c, N_151, \RA_c[10] , g3, \Din_c[7] , + \Din_c[6] , \Din_c[4] , XOR8MEG, RA11_2, Ready_fast, \RA_c[11] , N_36, + RCKEEN_8_u_0_a3_0_0, FWEr_fast, \S[1] , CO0, RCKEEN_8_u_0_1_1, + RCKEEN_8_u_0_0, RCKEEN_8, PHI2r, RCKEEN, RCKE_c, RASr2, RASr3, RASr, + RCKE_2, g0_i_a5_1, \S_0_i_o2[1] , Ready_0_sqmuxa_0_a3_2, N_430_0, + Ready_0_sqmuxa, N_431_0, nRRAS_0_sqmuxa, N_129, UFMCLK_r_i_a2_2_2, + CmdUFMCLK, UFMCLK_r_i_m4_xx_mm_1, UFMCLK_c, nUFMCS15, N_137_i, + UFMCLK_RNO, UFMSDI_r_xx_mm_1, UFMSDI_c, UFMSDI_RNO, N_94, CmdUFMSDI, + \Din_c[5] , nCCAS_c, \WRD[4] , \WRD[5] , FWEr, N_125, \WRD[6] , N_43, + \WRD[7] , N_163, XOR8MEG_3_u_0_a3_0_1, N_166, XOR8MEG_3, N_48, N_24, + un1_nRCAS_6_sqmuxa_i_0, nRCAS_0_sqmuxa_1, G_1_1, G_1_0, N_46_i, + nRCAS_c, CBR_fast, g0_i_a5_1_2, g0_i_0, N_184, N_143_i, nRCS_c, + nRRAS_5_u_i_0, N_154, N_142_i, nRRAS_c, m18_0_a2_1, G_17_1, N_144_i, + nRWE_c, N_112, nRowColSel_0_0, nRowColSel, nUFMCS_s_0_N_5_i_N_2L1, + nUFMCS_c, nUFMCS_s_0_N_5_i, m18_0_a3_3, CmdUFMCS, N_133_5, N_133_3, + \MAin_c[3] , \MAin_c[2] , \RowA[2] , \RowA[3] , g0_i_a5_2_1, N_9, + RCKEEN_8_u_0_1_a1_0, UFMSDI_ens2_i_o2_0_3, \MAin_c[1] , \MAin_c[0] , + \RowA[0] , \RowA[1] , nFWE_c, CMDWR_2, C1WR_7, CMDWR, + un1_FS_13_i_a2_9_5, un1_FS_13_i_a2_9_4, un1_FS_14_i_a2_0_1, + un1_FS_13_i_a2_1, \Din_c[3] , \MAin_c[7] , \MAin_c[6] , \RowA[6] , + \RowA[7] , N_180, N_156, N_122_5, CASr, \Din_c[2] , \Bank[6] , + \Bank[7] , \MAin_c[4] , C1WR_2_0, \Bank[0] , \Bank[1] , \Bank[5] , + \Bank[2] , un1_Bank_1_5, un1_Bank_1_4, ADWR_8, \MAin_c[5] , ADWR_8_2, + \Bank[3] , ADWR_8_4, m6_0_a2_2, \WRD[2] , \WRD[3] , \MAin_c[9] , + \MAin_c[8] , \RowA[8] , \RowA[9] , \WRD[0] , \WRD[1] , + CmdUFMCLK_1_sqmuxa, \RowA[4] , \RowA[5] , \CROW_c[1] , \CROW_c[0] , + \RBA_c[0] , \RBA_c[1] , \RA_c[9] , RDQMH_c, \Bank[4] , \RA_c[1] , + \RA_c[8] , RDQML_c, \RA_c[3] , \RA_c[0] , \RA_c[4] , \RA_c[2] , + \RA_c[5] , \RA_c[7] , RD_1_i, \RA_c[6] , \RD_in[0] , \RD_in[7] , + \RD_in[6] , \RD_in[5] , \RD_in[4] , \RD_in[3] , \RD_in[2] , + \RD_in[1] , VCCI, GNDI_TSALL; SLICE_0 SLICE_0( .A1(\FS[1] ), .A0(\FS[0] ), .CLK(RCLK_c), .Q0(\FS[0] ), .Q1(\FS[1] ), .FCO(\FS_cry[1] )); @@ -86,213 +89,231 @@ module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, .Q0(\FS[4] ), .Q1(\FS[5] ), .FCO(\FS_cry[5] )); SLICE_8 SLICE_8( .A1(\FS[3] ), .A0(\FS[2] ), .CLK(RCLK_c), .FCI(\FS_cry[1] ), .Q0(\FS[2] ), .Q1(\FS[3] ), .FCO(\FS_cry[3] )); - SLICE_9 SLICE_9( .D1(N_147), .C1(\MAin_c[0] ), .B1(CmdEnable17_0_a2_4), - .A1(CmdEnable17_0_a2_3), .D0(CmdEnable16), .C0(CmdEnable17), - .B0(C1WR_0_a2), .A0(ADSubmitted), .DI0(ADSubmitted_r), .CLK(PHI2_c), - .F0(ADSubmitted_r), .Q0(ADSubmitted), .F1(CmdEnable17)); - SLICE_14 SLICE_14( .C1(N_147), .B1(CmdEnable16_0_a2_5), - .A1(CmdEnable16_0_a2_4), .D0(\MAin_c[1] ), .C0(N_147), .B0(C1Submitted), + SLICE_9 SLICE_9( .B1(C1WR), .A1(ADWR), .D0(CmdEnable16), .C0(CmdEnable17), + .B0(N_183_i), .A0(ADSubmitted), .DI0(ADSubmitted_r), .CLK(PHI2_c), + .F0(ADSubmitted_r), .Q0(ADSubmitted), .F1(N_183_i)); + SLICE_14 SLICE_14( .D1(un1_CmdEnable20_0_a3_0_2), .C1(N_121), + .B1(CmdEnable16), .A1(C1Submitted), .D0(ADWR), .C0(C1WR), .B0(C1Submitted), .A0(CmdEnable16), .DI0(C1Submitted_RNO), .CLK(PHI2_c), - .F0(C1Submitted_RNO), .Q0(C1Submitted), .F1(CmdEnable16)); - SLICE_19 SLICE_19( .D1(\S[1] ), .C1(RASr2), .B1(\IS[3] ), .A1(CO0), - .B0(\S[1] ), .A0(CO0), .DI0(N_177_i), .LSR(RASr2), .CLK(RCLK_c), - .F0(N_177_i), .Q0(CO0), .F1(Ready_0_sqmuxa_0_a3_2)); - SLICE_20 SLICE_20( .B1(ADSubmitted), .A1(CmdEnable), .D0(C1Submitted), - .C0(un1_CMDWR), .B0(CmdEnable), .A0(CmdEnable17), .DI0(CmdEnable_s), - .M0(CmdEnable16), .CLK(PHI2_c), .OFX0(CmdEnable_s), .Q0(CmdEnable)); - SLICE_21 SLICE_21( .C1(N_128), .B1(\Din_c[5] ), .A1(\Din_c[3] ), .D0(N_152), - .C0(N_133), .B0(N_132), .A0(LEDEN), .DI0(N_21_i), .CE(XOR8MEG18), - .CLK(PHI2_c), .F0(N_21_i), .Q0(CmdLEDEN), .F1(N_152)); + .F0(C1Submitted_RNO), .Q0(C1Submitted), .F1(un1_CmdEnable20_i)); + SLICE_20 SLICE_20( .D1(C1WR), .C1(CmdEnable16_0_a3_4), + .B1(CmdEnable16_0_a3_5), .A1(ADSubmitted), .D0(CmdEnable_0_sqmuxa), + .C0(un1_CmdEnable20_i), .B0(CmdEnable17), .A0(CmdEnable), + .DI0(CmdEnable_s), .CLK(PHI2_c), .F0(CmdEnable_s), .Q0(CmdEnable), + .F1(CmdEnable_0_sqmuxa)); + SLICE_21 SLICE_21( .D1(N_45), .C1(\Din_c[1] ), .B1(CmdLEDEN_4_u_i_a2_0_0), + .A1(CmdLEDEN), .C0(N_95), .B0(LEDEN), .A0(CmdLEDEN_4_u_i_0), .DI0(N_14_i), + .CE(XOR8MEG18), .CLK(PHI2_c), .F0(N_14_i), .Q0(CmdLEDEN), + .F1(CmdLEDEN_4_u_i_0)); SLICE_22 SLICE_22( .D1(PHI2r3), .C1(PHI2r2), .B1(InitReady), .A1(CmdSubmitted), .B0(CmdSubmitted), .A0(CmdSubmitted_1_sqmuxa), - .DI0(N_460_0), .CLK(PHI2_c), .F0(N_460_0), .Q0(CmdSubmitted), .F1(N_136)); - SLICE_26 SLICE_26( .D1(N_128), .C1(N_43), .B1(Cmdn8MEGEN), - .A1(CmdEnable16_4), .C0(n8MEGEN), .B0(N_152), .A0(Cmdn8MEGEN_4_u_i_0), - .DI0(N_19_i), .CE(XOR8MEG18), .CLK(PHI2_c), .F0(N_19_i), .Q0(Cmdn8MEGEN), - .F1(Cmdn8MEGEN_4_u_i_0)); - SLICE_29 SLICE_29( .D1(nRRAS_5_u_i_0), .C1(N_160), .B1(N_155), .A1(\IS[0] ), - .C0(N_155), .B0(Ready), .A0(\IS[0] ), .DI0(N_64_i_i), .CLK(RCLK_c), - .F0(N_64_i_i), .Q0(\IS[0] ), .F1(N_24)); + .DI0(N_428_0), .CLK(PHI2_c), .F0(N_428_0), .Q0(CmdSubmitted), .F1(N_134)); + SLICE_26 SLICE_26( .D1(N_45), .C1(\Din_c[0] ), .B1(Cmdn8MEGEN), + .A1(CmdLEDEN_4_u_i_a2_0_0), .C0(n8MEGEN), .B0(N_95), + .A0(Cmdn8MEGEN_4_u_i_0), .DI0(N_12_i), .CE(XOR8MEG18), .CLK(PHI2_c), + .F0(N_12_i), .Q0(Cmdn8MEGEN), .F1(Cmdn8MEGEN_4_u_i_0)); + SLICE_29 SLICE_29( .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), .C0(Ready), + .B0(N_148), .A0(\IS[0] ), .DI0(N_77_i_i), .M1(CASr2), .CLK(RCLK_c), + .F0(N_77_i_i), .Q0(\IS[0] ), .F1(N_160), .Q1(CASr3)); SLICE_30 SLICE_30( .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), .B0(\IS[1] ), - .A0(\IS[0] ), .DI1(N_60_i_i), .DI0(N_56_i), .CE(N_159_i), .CLK(RCLK_c), - .F0(N_56_i), .Q0(\IS[1] ), .F1(N_60_i_i), .Q1(\IS[2] )); - SLICE_31 SLICE_31( .D1(N_159), .C1(\IS[3] ), .B1(\IS[2] ), .A1(\IS[1] ), - .D0(\IS[0] ), .C0(\IS[1] ), .B0(\IS[2] ), .A0(\IS[3] ), .DI0(N_61_i_i), - .CE(N_159_i), .CLK(RCLK_c), .F0(N_61_i_i), .Q0(\IS[3] ), .F1(RA10s_i)); - SLICE_32 SLICE_32( .D1(UFMSDI_ens2_i_a2_4_2), .C1(N_126), .B1(N_51), - .A1(InitReady), .B0(InitReady), .A0(InitReady3), .DI0(N_461_0), - .CLK(RCLK_c), .F0(N_461_0), .Q0(InitReady), .F1(UFMSDI_ens2_i_a0)); - SLICE_33 SLICE_33( .C1(nCRAS_c), .B1(LEDEN), .A1(CBR), .C0(UFMSDO_c), - .B0(InitReady), .A0(CmdLEDEN), .DI0(N_70), .CE(N_33), .CLK(RCLK_c), - .F0(N_70), .Q0(LEDEN), .F1(LED_c)); - SLICE_39 SLICE_39( .B1(un1_Din_4), .A1(XOR8MEG), .C0(n8MEGEN), .B0(XOR8MEG), - .A0(\Din_c[6] ), .DI0(RA11_2), .LSR(Ready_fast), .CLK(PHI2_c), .F0(RA11_2), - .Q0(\RA_c[11] ), .F1(N_171)); - SLICE_41 SLICE_41( .D1(\S[1] ), .C1(FWEr_fast), .B1(CO0), .A1(CASr2), - .D0(Ready), .C0(RCKEEN_8_u_1), .B0(RCKEEN_8_u_0_0), .A0(CBR), + .A0(\IS[0] ), .DI1(N_74_i_i), .DI0(N_69_i), .CE(N_153_i), .CLK(RCLK_c), + .F0(N_69_i), .Q0(\IS[1] ), .F1(N_74_i_i), .Q1(\IS[2] )); + SLICE_31 SLICE_31( .D1(Ready), .C1(N_148), .B1(\IS[3] ), .A1(\IS[0] ), + .D0(\IS[0] ), .C0(\IS[1] ), .B0(\IS[2] ), .A0(\IS[3] ), .DI0(N_75_i_i), + .CE(N_153_i), .CLK(RCLK_c), .F0(N_75_i_i), .Q0(\IS[3] ), .F1(RA10s_i)); + SLICE_32 SLICE_32( .D1(UFMSDI_ens2_i_a2_4_2), .C1(N_128), .B1(N_34), + .A1(InitReady), .B0(InitReady), .A0(InitReady3), .DI0(N_429_0), + .CLK(RCLK_c), .F0(N_429_0), .Q0(InitReady), .F1(UFMSDI_ens2_i_a0)); + SLICE_33 SLICE_33( .D1(nCRAS_c), .C1(Ready), .B1(LEDEN), .A1(CBR), + .C0(UFMSDO_c), .B0(InitReady), .A0(CmdLEDEN), .DI0(N_49), .CE(N_26), + .CLK(RCLK_c), .F0(N_49), .Q0(LEDEN), .F1(LED_c)); + SLICE_38 SLICE_38( .D1(\IS[3] ), .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), + .B0(\IS[2] ), .A0(\IS[1] ), .DI0(N_151), .LSR(RA10s_i), .CLK(RCLK_c), + .F0(N_151), .Q0(\RA_c[10] ), .F1(g3)); + SLICE_39 SLICE_39( .C1(\Din_c[7] ), .B1(\Din_c[6] ), .A1(\Din_c[4] ), + .C0(n8MEGEN), .B0(XOR8MEG), .A0(\Din_c[6] ), .DI0(RA11_2), + .LSR(Ready_fast), .CLK(PHI2_c), .F0(RA11_2), .Q0(\RA_c[11] ), .F1(N_36)); + SLICE_41 SLICE_41( .D1(RCKEEN_8_u_0_a3_0_0), .C1(FWEr_fast), .B1(\S[1] ), + .A1(CO0), .D0(Ready), .C0(RCKEEN_8_u_0_1_1), .B0(RCKEEN_8_u_0_0), .A0(CBR), .DI0(RCKEEN_8), .M1(PHI2r), .CLK(RCLK_c), .F0(RCKEEN_8), .Q0(RCKEEN), - .F1(RCKEEN_8_u_1), .Q1(PHI2r2)); - SLICE_42 SLICE_42( .D1(RASr2), .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), - .D0(RCKEEN), .C0(RASr3), .B0(RASr2), .A0(RASr), .DI0(RCKE_2), .M1(PHI2_c), - .CLK(RCLK_c), .F0(RCKE_2), .Q0(RCKE_c), .F1(m18_0_a3_3), .Q1(PHI2r)); + .F1(RCKEEN_8_u_0_1_1), .Q1(PHI2r2)); + SLICE_42 SLICE_42( .C1(Ready), .B1(RCKE_c), .A1(RASr2), .D0(RCKEEN), + .C0(RASr3), .B0(RASr2), .A0(RASr), .DI0(RCKE_2), .M1(PHI2_c), .CLK(RCLK_c), + .F0(RCKE_2), .Q0(RCKE_c), .F1(g0_i_a5_1), .Q1(PHI2r)); SLICE_43 SLICE_43( .D1(\S_0_i_o2[1] ), .C1(InitReady), .B1(RASr2), - .A1(Ready), .D0(InitReady), .C0(N_165), .B0(Ready_0_sqmuxa_0_a3_2), - .A0(Ready), .DI0(N_462_0), .M1(PHI2r2), .CLK(RCLK_c), .F0(N_462_0), + .A1(Ready), .D0(InitReady), .C0(N_160), .B0(Ready_0_sqmuxa_0_a3_2), + .A0(Ready), .DI0(N_430_0), .M1(PHI2r2), .CLK(RCLK_c), .F0(N_430_0), .Q0(Ready), .F1(RCKEEN_8_u_0_0), .Q1(PHI2r3)); - SLICE_44 SLICE_44( .D1(Ready_0_sqmuxa_0_a3_2), .C1(Ready), .B1(N_165), - .A1(InitReady), .B0(Ready_fast), .A0(Ready_0_sqmuxa), .DI0(N_463_0), - .M1(nCRAS_c), .CLK(RCLK_c), .F0(N_463_0), .Q0(Ready_fast), - .F1(Ready_0_sqmuxa), .Q1(RASr)); + SLICE_44 SLICE_44( .D1(Ready_0_sqmuxa_0_a3_2), .C1(Ready), .B1(N_160), + .A1(InitReady), .B0(Ready_fast), .A0(Ready_0_sqmuxa), .DI0(N_431_0), + .M1(RASr2), .CLK(RCLK_c), .F0(N_431_0), .Q0(Ready_fast), + .F1(Ready_0_sqmuxa), .Q1(RASr3)); SLICE_50 SLICE_50( .C1(CO0), .B1(\S[1] ), .A1(Ready), .B0(\S[1] ), .A0(CO0), .DI0(\S_0_i_o2[1] ), .LSR(RASr2), .CLK(RCLK_c), .F0(\S_0_i_o2[1] ), .Q0(\S[1] ), .F1(nRRAS_0_sqmuxa)); SLICE_51 SLICE_51( .D1(N_129), .C1(UFMCLK_r_i_a2_2_2), .B1(CmdUFMCLK), .A1(InitReady), .D0(UFMCLK_r_i_m4_xx_mm_1), .C0(UFMCLK_c), .B0(nUFMCS15), - .A0(N_139_i), .DI0(UFMCLK_RNO), .M1(RASr), .CLK(RCLK_c), .F0(UFMCLK_RNO), - .Q0(UFMCLK_c), .F1(UFMCLK_r_i_m4_xx_mm_1), .Q1(RASr2)); + .A0(N_137_i), .DI0(UFMCLK_RNO), .CLK(RCLK_c), .F0(UFMCLK_RNO), + .Q0(UFMCLK_c), .F1(UFMCLK_r_i_m4_xx_mm_1)); SLICE_52 SLICE_52( .D1(PHI2r3), .C1(PHI2r2), .B1(InitReady), .A1(CmdSubmitted), .D0(UFMSDI_r_xx_mm_1), .C0(UFMSDI_c), .B0(nUFMCS15), - .A0(N_139_i), .DI0(UFMSDI_RNO), .M1(RASr2), .CLK(RCLK_c), .F0(UFMSDI_RNO), - .Q0(UFMSDI_c), .F1(N_139_i), .Q1(RASr3)); - SLICE_55 SLICE_55( .C0(nRowColSel), .B0(\RowA[4] ), .A0(\MAin_c[4] ), - .M1(\Din_c[5] ), .M0(\Din_c[4] ), .CLK(nCCAS_c), .F0(\RA_c[4] ), + .A0(N_137_i), .DI0(UFMSDI_RNO), .CLK(RCLK_c), .F0(UFMSDI_RNO), + .Q0(UFMSDI_c), .F1(N_137_i)); + SLICE_55 SLICE_55( .C0(N_94), .B0(UFMSDI_ens2_i_a0), .A0(CmdUFMSDI), + .M1(\Din_c[5] ), .M0(\Din_c[4] ), .CLK(nCCAS_c), .F0(UFMSDI_r_xx_mm_1), .Q0(\WRD[4] ), .Q1(\WRD[5] )); - SLICE_56 SLICE_56( .D1(\Bank[7] ), .C1(\Bank[6] ), .B1(\Bank[5] ), - .A1(\Bank[2] ), .C0(\FS[9] ), .B0(\FS[7] ), .A0(\FS[5] ), .M1(\Din_c[7] ), - .M0(\Din_c[6] ), .CLK(nCCAS_c), .F0(N_126), .Q0(\WRD[6] ), - .F1(C1WR_0_a2_0_11), .Q1(\WRD[7] )); - SLICE_57 SLICE_57( .D1(un1_Din_4), .C1(\Din_c[3] ), .B1(\Din_c[2] ), - .A1(\Din_c[0] ), .D0(XOR8MEG_3_u_0_a3_2), .C0(N_171), .B0(LEDEN), - .A0(\Din_c[1] ), .DI0(XOR8MEG_3), .CE(XOR8MEG18), .CLK(PHI2_c), - .F0(XOR8MEG_3), .Q0(XOR8MEG), .F1(XOR8MEG_3_u_0_a3_2)); - SLICE_58 SLICE_58( .C1(N_51), .B1(InitReady), .A1(\FS[8] ), .C0(UFMSDO_c), - .B0(InitReady), .A0(Cmdn8MEGEN), .DI0(N_69), .CE(N_31), .CLK(RCLK_c), - .F0(N_69), .Q0(n8MEGEN), .F1(N_151)); - SLICE_59 SLICE_59( .D1(\S[1] ), .C1(Ready), .B1(N_160), .A1(N_155), - .D0(g0_1), .C0(\S[1] ), .B0(nRCAS_0_sqmuxa_1), .A0(N_41), .DI0(N_37_i), - .CLK(RCLK_c), .F0(N_37_i), .Q0(nRCAS_c), .F1(N_41)); - SLICE_60 SLICE_60( .D1(CASr2), .C1(CASr3), .B1(CO0), .A1(FWEr_fast), - .D0(RCKEEN_8_u_0_a2_1_out), .C0(N_28_i_1), .B0(N_24), .A0(CBR), - .DI0(N_28_i), .CLK(RCLK_c), .F0(N_28_i), .Q0(nRCS_c), .F1(N_28_i_1)); + SLICE_56 SLICE_56( .B1(\FS[11] ), .A1(\FS[4] ), .B0(FWEr), .A0(CO0), + .M1(\Din_c[7] ), .M0(\Din_c[6] ), .CLK(nCCAS_c), .F0(N_125), .Q0(\WRD[6] ), + .F1(N_43), .Q1(\WRD[7] )); + SLICE_57 SLICE_57( .B1(XOR8MEG), .A1(N_163), .D0(XOR8MEG_3_u_0_a3_0_1), + .C0(N_166), .B0(LEDEN), .A0(\Din_c[1] ), .DI0(XOR8MEG_3), .CE(XOR8MEG18), + .CLK(PHI2_c), .F0(XOR8MEG_3), .Q0(XOR8MEG), .F1(N_166)); + SLICE_58 SLICE_58( .C1(N_128), .B1(InitReady), .A1(\FS[8] ), .C0(UFMSDO_c), + .B0(InitReady), .A0(Cmdn8MEGEN), .DI0(N_48), .CE(N_24), .CLK(RCLK_c), + .F0(N_48), .Q0(n8MEGEN), .F1(N_94)); + SLICE_59 SLICE_59( .C1(\S[1] ), .B1(un1_nRCAS_6_sqmuxa_i_0), .A1(CBR), + .D0(\S[1] ), .C0(nRCAS_0_sqmuxa_1), .B0(G_1_1), .A0(G_1_0), .DI0(N_46_i), + .CLK(RCLK_c), .F0(N_46_i), .Q0(nRCAS_c), .F1(G_1_1)); + SLICE_60 SLICE_60( .C1(\S[1] ), .B1(Ready), .A1(CBR_fast), .D0(g0_i_a5_1_2), + .C0(g0_i_0), .B0(N_184), .A0(N_125), .DI0(N_143_i), .CLK(RCLK_c), + .F0(N_143_i), .Q0(nRCS_c), .F1(N_184)); SLICE_61 SLICE_61( .D1(Ready), .C1(RCKE_c), .B1(RASr2), .A1(\S_0_i_o2[1] ), - .D0(\IS[0] ), .C0(N_155), .B0(N_160), .A0(nRRAS_5_u_i_0), .DI0(N_24_i), - .CLK(RCLK_c), .F0(N_24_i), .Q0(nRRAS_c), .F1(nRRAS_5_u_i_0)); + .D0(nRRAS_5_u_i_0), .C0(N_154), .B0(N_148), .A0(\IS[0] ), .DI0(N_142_i), + .CLK(RCLK_c), .F0(N_142_i), .Q0(nRRAS_c), .F1(nRRAS_5_u_i_0)); SLICE_62 SLICE_62( .D1(Ready), .C1(RASr2), .B1(\S_0_i_o2[1] ), .A1(CBR_fast), .D0(m18_0_a2_1), .C0(nRCAS_0_sqmuxa_1), .B0(G_17_1), .A0(FWEr), - .DI0(N_39_i), .CLK(RCLK_c), .F0(N_39_i), .Q0(nRWE_c), + .DI0(N_144_i), .CLK(RCLK_c), .F0(N_144_i), .Q0(nRWE_c), .F1(nRCAS_0_sqmuxa_1)); SLICE_63 SLICE_63( .D1(Ready), .C1(FWEr), .B1(CBR), .A1(CASr3), .D0(\S[1] ), - .C0(Ready), .B0(N_179), .A0(CO0), .DI0(nRowColSel_0_0), + .C0(Ready), .B0(N_112), .A0(CO0), .DI0(nRowColSel_0_0), .LSR(nRRAS_0_sqmuxa), .CLK(RCLK_c), .F0(nRowColSel_0_0), .Q0(nRowColSel), - .F1(N_179)); - SLICE_64 SLICE_64( .D1(N_51), .C1(InitReady), .B1(\FS[11] ), .A1(\FS[10] ), - .D0(nUFMCS_s_0_N_5_i_N_2L1), .C0(nUFMCS_c), .B0(nUFMCS15), .A0(N_139_i), + .F1(N_112)); + SLICE_64 SLICE_64( .D1(N_128), .C1(InitReady), .B1(\FS[11] ), .A1(\FS[10] ), + .D0(nUFMCS_s_0_N_5_i_N_2L1), .C0(nUFMCS_c), .B0(nUFMCS15), .A0(N_137_i), .DI0(nUFMCS_s_0_N_5_i), .CLK(RCLK_c), .F0(nUFMCS_s_0_N_5_i), .Q0(nUFMCS_c), .F1(nUFMCS15)); nRWE_RNO_1_SLICE_65 \nRWE_RNO_1/SLICE_65 ( .D1(RASr2), .C1(RCKE_c), .B1(CO0), .A1(\S[1] ), .D0(InitReady), .C0(m18_0_a3_3), .B0(CO0), .A0(\S[1] ), .M0(Ready), .OFX0(m18_0_a2_1)); - SLICE_66 SLICE_66( .C1(UFMCLK_r_i_a2_2_2), .B1(InitReady), .A1(CmdUFMCS), - .D0(N_95_5), .C0(N_95_3), .B0(InitReady), .A0(\FS[16] ), .M1(\MAin_c[1] ), - .M0(\MAin_c[0] ), .LSR(Ready_fast), .CLK(nCRAS_c), .F0(UFMCLK_r_i_a2_2_2), - .Q0(\RowA[0] ), .F1(nUFMCS_s_0_N_5_i_N_2L1), .Q1(\RowA[1] )); - SLICE_67 SLICE_67( .D1(\Din_c[3] ), .C1(\Din_c[5] ), .B1(N_128), - .A1(XOR8MEG18), .D0(N_147), .C0(\MAin_c[1] ), .B0(\MAin_c[0] ), - .A0(CmdEnable), .M1(\MAin_c[5] ), .M0(\MAin_c[4] ), .LSR(Ready_fast), - .CLK(nCRAS_c), .F0(XOR8MEG18), .Q0(\RowA[4] ), .F1(CmdUFMCLK_1_sqmuxa), - .Q1(\RowA[5] )); - SLICE_68 SLICE_68( .D1(\FS[5] ), .C1(\FS[3] ), .B1(\FS[2] ), .A1(\FS[0] ), - .D0(un1_FS_14_i_a2_0_1), .C0(N_137_8), .B0(N_137_6), .A0(N_136), .F0(N_31), - .F1(un1_FS_14_i_a2_0_1)); - SLICE_69 SLICE_69( .D1(\FS[5] ), .C1(\FS[3] ), .B1(\FS[2] ), .A1(\FS[0] ), - .D0(un1_FS_13_i_a2_1), .C0(N_137_8), .B0(N_137_6), .A0(N_136), .F0(N_33), - .F1(un1_FS_13_i_a2_1)); - SLICE_70 SLICE_70( .D1(C1WR_0_a2_0_11), .C1(C1WR_0_a2_0_10), .B1(\Bank[1] ), - .A1(\Bank[0] ), .B0(N_147), .A0(\MAin_c[1] ), .M1(\Din_c[1] ), - .M0(\Din_c[0] ), .CLK(PHI2_c), .F0(C1WR_0_a2), .Q0(\Bank[0] ), .F1(N_147), - .Q1(\Bank[1] )); - SLICE_71 SLICE_71( .D1(\MAin_c[7] ), .C1(\MAin_c[6] ), .B1(\MAin_c[5] ), - .A1(\MAin_c[4] ), .D0(C1WR_0_a2_0_4), .C0(C1WR_0_a2_0_3), .B0(\Bank[4] ), - .A0(\Bank[3] ), .M1(\Din_c[3] ), .M0(\Din_c[2] ), .CLK(PHI2_c), - .F0(C1WR_0_a2_0_10), .Q0(\Bank[2] ), .F1(C1WR_0_a2_0_4), .Q1(\Bank[3] )); - SLICE_72 SLICE_72( .C1(UFMSDI_ens2_i_o2_0_3), .B1(\FS[16] ), .A1(\FS[12] ), - .D0(N_51), .C0(\FS[11] ), .B0(\FS[4] ), .A0(\FS[1] ), .M1(\MAin_c[3] ), - .M0(\MAin_c[2] ), .LSR(Ready_fast), .CLK(nCRAS_c), .F0(N_129), - .Q0(\RowA[2] ), .F1(N_51), .Q1(\RowA[3] )); - SLICE_73 SLICE_73( .D1(CO0), .C1(\S[1] ), .B1(InitReady), .A1(RASr2), - .B0(Ready), .A0(N_155), .M1(\Din_c[2] ), .M0(\Din_c[1] ), - .CE(CmdUFMCLK_1_sqmuxa), .CLK(PHI2_c), .F0(N_159), .Q0(CmdUFMCLK), - .F1(N_155), .Q1(CmdUFMCS)); - SLICE_74 SLICE_74( .B1(\FS[14] ), .A1(\FS[11] ), .D0(N_95_5), .C0(N_95_3), - .B0(\FS[16] ), .A0(\FS[10] ), .M0(\Din_c[0] ), .CE(CmdUFMCLK_1_sqmuxa), - .CLK(PHI2_c), .F0(InitReady3), .Q0(CmdUFMSDI), .F1(N_95_3)); - SLICE_75 SLICE_75( .C1(\Din_c[7] ), .B1(\Din_c[6] ), .A1(\Din_c[4] ), - .C0(N_128), .B0(\Din_c[5] ), .A0(\Din_c[1] ), .M1(CASr), .M0(nCCAS_c), - .CLK(RCLK_c), .F0(N_133), .Q0(CASr), .F1(N_128), .Q1(CASr2)); - SLICE_76 SLICE_76( .B1(\Din_c[5] ), .A1(\Din_c[0] ), .D0(\MAin_c[0] ), - .C0(\Din_c[3] ), .B0(\Din_c[1] ), .A0(CmdEnable16_4), .M1(\Din_c[5] ), - .M0(\Din_c[4] ), .CLK(PHI2_c), .F0(CmdEnable16_0_a2_4), .Q0(\Bank[4] ), - .F1(CmdEnable16_4), .Q1(\Bank[5] )); - SLICE_77 SLICE_77( .B1(\Din_c[7] ), .A1(\Din_c[4] ), .D0(\MAin_c[1] ), - .C0(\Din_c[6] ), .B0(\Din_c[2] ), .A0(CmdEnable16_1), .M1(\Din_c[7] ), - .M0(\Din_c[6] ), .CLK(PHI2_c), .F0(CmdEnable16_0_a2_5), .Q0(\Bank[6] ), - .F1(CmdEnable16_1), .Q1(\Bank[7] )); - SLICE_78 SLICE_78( .B1(\Din_c[5] ), .A1(\Din_c[3] ), .D0(N_43), - .C0(\MAin_c[1] ), .B0(\Din_c[6] ), .A0(\Din_c[2] ), .M1(nCCAS_c), - .M0(nCCAS_c), .CLK(nCRAS_c), .F0(CmdEnable17_0_a2_4), .Q0(CBR), .F1(N_43), - .Q1(CBR_fast)); - SLICE_79 SLICE_79( .C1(Ready), .B1(CASr3), .A1(CASr2), .D0(m6_0_a2_2), - .C0(\S[1] ), .B0(CO0), .A0(CBR), .M1(\Din_c[1] ), .M0(\Din_c[0] ), - .CLK(nCCAS_c), .F0(G_17_1), .Q0(\WRD[0] ), .F1(m6_0_a2_2), .Q1(\WRD[1] )); - SLICE_80 SLICE_80( .B1(CASr3), .A1(CASr2), .D0(g4_0_0_0), .C0(FWEr), - .B0(CO0), .A0(CBR_fast), .M1(\MAin_c[9] ), .M0(\MAin_c[8] ), - .LSR(Ready_fast), .CLK(nCRAS_c), .F0(g0_1), .Q0(\RowA[8] ), .F1(g4_0_0_0), + SLICE_66 SLICE_66( .D1(CO0), .C1(\S[1] ), .B1(InitReady), .A1(RASr2), + .D0(\S[1] ), .C0(Ready), .B0(N_154), .A0(N_148), + .F0(un1_nRCAS_6_sqmuxa_i_0), .F1(N_148)); + SLICE_67 SLICE_67( .C1(UFMCLK_r_i_a2_2_2), .B1(InitReady), .A1(CmdUFMCS), + .D0(N_133_5), .C0(N_133_3), .B0(InitReady), .A0(\FS[13] ), + .M1(\MAin_c[3] ), .M0(\MAin_c[2] ), .LSR(Ready_fast), .CLK(nCRAS_c), + .F0(UFMCLK_r_i_a2_2_2), .Q0(\RowA[2] ), .F1(nUFMCS_s_0_N_5_i_N_2L1), + .Q1(\RowA[3] )); + SLICE_68 SLICE_68( .D1(g3), .C1(g0_i_a5_2_1), .B1(RASr2), .A1(CO0), + .D0(g0_i_a5_1), .C0(\S[1] ), .B0(N_9), .A0(CO0), .M0(RASr2), + .LSR(RCKEEN_8_u_0_1_a1_0), .CLK(RCLK_c), .F0(g0_i_0), .Q0(CO0), .F1(N_9)); + SLICE_69 SLICE_69( .C1(UFMSDI_ens2_i_o2_0_3), .B1(\FS[16] ), .A1(\FS[13] ), + .D0(\FS[4] ), .C0(\FS[11] ), .B0(\FS[1] ), .A0(N_128), .M1(\MAin_c[1] ), + .M0(\MAin_c[0] ), .LSR(Ready_fast), .CLK(nCRAS_c), .F0(N_129), + .Q0(\RowA[0] ), .F1(N_128), .Q1(\RowA[1] )); + SLICE_70 SLICE_70( .D1(nFWE_c), .C1(\MAin_c[0] ), .B1(CMDWR_2), .A1(C1WR_7), + .C0(CMDWR), .B0(C1WR), .A0(ADWR), .F0(N_121), .F1(CMDWR)); + SLICE_71 SLICE_71( .D1(un1_FS_13_i_a2_9_5), .C1(un1_FS_13_i_a2_9_4), + .B1(N_43), .A1(\FS[5] ), .C0(un1_FS_14_i_a2_0_1), .B0(N_134), .A0(N_94), + .F0(N_24), .F1(un1_FS_14_i_a2_0_1)); + SLICE_72 SLICE_72( .D1(un1_FS_13_i_a2_9_5), .C1(un1_FS_13_i_a2_9_4), + .B1(N_43), .A1(\FS[5] ), .C0(un1_FS_13_i_a2_1), .B0(N_134), .A0(N_94), + .F0(N_26), .F1(un1_FS_13_i_a2_1)); + SLICE_73 SLICE_73( .D1(\Din_c[3] ), .C1(\Din_c[5] ), .B1(N_36), + .A1(XOR8MEG18), .B0(CmdEnable), .A0(CMDWR), .M1(\MAin_c[7] ), + .M0(\MAin_c[6] ), .LSR(Ready_fast), .CLK(nCRAS_c), .F0(XOR8MEG18), + .Q0(\RowA[6] ), .F1(CmdSubmitted_1_sqmuxa), .Q1(\RowA[7] )); + SLICE_74 SLICE_74( .B1(\Din_c[6] ), .A1(\Din_c[4] ), .D0(N_180), .C0(N_156), + .B0(N_122_5), .A0(ADWR), .M1(CASr), .M0(nCCAS_c), .CLK(RCLK_c), + .F0(CmdEnable17), .Q0(CASr), .F1(N_156), .Q1(CASr2)); + SLICE_75 SLICE_75( .D1(\Din_c[4] ), .C1(\Din_c[3] ), .B1(\Din_c[2] ), + .A1(\Din_c[1] ), .C0(CmdEnable16_0_a3_5), .B0(CmdEnable16_0_a3_4), + .A0(C1WR), .M1(\Din_c[7] ), .M0(\Din_c[6] ), .CLK(PHI2_c), + .F0(CmdEnable16), .Q0(\Bank[6] ), .F1(CmdEnable16_0_a3_5), .Q1(\Bank[7] )); + SLICE_76 SLICE_76( .D1(\MAin_c[4] ), .C1(\MAin_c[3] ), .B1(\MAin_c[1] ), + .A1(\MAin_c[0] ), .D0(nFWE_c), .C0(\MAin_c[2] ), .B0(C1WR_7), + .A0(C1WR_2_0), .M1(\Din_c[1] ), .M0(\Din_c[0] ), .CLK(PHI2_c), .F0(C1WR), + .Q0(\Bank[0] ), .F1(C1WR_2_0), .Q1(\Bank[1] )); + SLICE_77 SLICE_77( .D1(\Bank[7] ), .C1(\Bank[6] ), .B1(\Bank[5] ), + .A1(\Bank[2] ), .D0(un1_Bank_1_5), .C0(un1_Bank_1_4), .B0(nFWE_c), + .A0(ADWR_8), .F0(ADWR), .F1(un1_Bank_1_5)); + SLICE_78 SLICE_78( .B1(\Din_c[2] ), .A1(\Din_c[0] ), .D0(N_180), .C0(N_156), + .B0(N_122_5), .A0(ADWR_8), .F0(un1_CmdEnable20_0_a3_0_2), .F1(N_180)); + SLICE_79 SLICE_79( .B1(\MAin_c[7] ), .A1(\MAin_c[6] ), .D0(un1_Bank_1_5), + .C0(un1_Bank_1_4), .B0(\MAin_c[5] ), .A0(ADWR_8_2), .M1(\Din_c[3] ), + .M0(\Din_c[2] ), .CLK(PHI2_c), .F0(C1WR_7), .Q0(\Bank[2] ), .F1(ADWR_8_2), + .Q1(\Bank[3] )); + SLICE_80 SLICE_80( .B1(\FS[17] ), .A1(\FS[11] ), .D0(N_133_5), .C0(N_133_3), + .B0(\FS[13] ), .A0(\FS[10] ), .F0(InitReady3), .F1(N_133_3)); + SLICE_81 SLICE_81( .D1(\MAin_c[5] ), .C1(\MAin_c[4] ), .B1(\MAin_c[1] ), + .A1(\MAin_c[0] ), .D0(\MAin_c[3] ), .C0(\MAin_c[2] ), .B0(ADWR_8_4), + .A0(ADWR_8_2), .F0(ADWR_8), .F1(ADWR_8_4)); + SLICE_82 SLICE_82( .C1(Ready), .B1(CASr3), .A1(CASr2), .D0(m6_0_a2_2), + .C0(\S[1] ), .B0(CO0), .A0(CBR_fast), .M1(\Din_c[3] ), .M0(\Din_c[2] ), + .CLK(nCCAS_c), .F0(G_17_1), .Q0(\WRD[2] ), .F1(m6_0_a2_2), .Q1(\WRD[3] )); + SLICE_83 SLICE_83( .D1(\Din_c[4] ), .C1(\Din_c[6] ), .B1(\Din_c[5] ), + .A1(\Din_c[7] ), .D0(\Din_c[0] ), .C0(\Din_c[2] ), .B0(\Din_c[3] ), + .A0(N_163), .M1(\MAin_c[9] ), .M0(\MAin_c[8] ), .LSR(Ready_fast), + .CLK(nCRAS_c), .F0(XOR8MEG_3_u_0_a3_0_1), .Q0(\RowA[8] ), .F1(N_163), .Q1(\RowA[9] )); - SLICE_81 SLICE_81( .D1(\FS[17] ), .C1(\FS[15] ), .B1(\FS[14] ), - .A1(\FS[13] ), .D0(\FS[17] ), .C0(\FS[15] ), .B0(\FS[13] ), .A0(\FS[12] ), - .M1(nFWE_c), .M0(nFWE_c), .CLK(nCRAS_c), .F0(N_95_5), .Q0(FWEr), - .F1(UFMSDI_ens2_i_o2_0_3), .Q1(FWEr_fast)); - SLICE_82 SLICE_82( .D1(\Din_c[3] ), .C1(\Din_c[5] ), .B1(CmdLEDEN), - .A1(N_128), .D0(\Din_c[3] ), .C0(\Din_c[5] ), .B0(N_128), .A0(XOR8MEG18), - .M0(CASr2), .CLK(RCLK_c), .F0(CmdSubmitted_1_sqmuxa), .Q0(CASr3), - .F1(N_132)); - SLICE_83 SLICE_83( .C1(\IS[3] ), .B1(\IS[2] ), .A1(\IS[1] ), .C0(\IS[2] ), - .B0(\IS[1] ), .A0(\IS[0] ), .M1(\CROW_c[1] ), .M0(\CROW_c[0] ), - .LSR(Ready_fast), .CLK(nCRAS_c), .F0(N_165), .Q0(\RBA_c[0] ), .F1(N_160), + SLICE_84 SLICE_84( .D1(FWEr_fast), .C1(CO0), .B1(CASr3), .A1(CASr2), + .D0(FWEr_fast), .C0(CO0), .B0(CASr3), .A0(CASr2), .M1(\Din_c[1] ), + .M0(\Din_c[0] ), .CLK(nCCAS_c), .F0(g0_i_a5_1_2), .Q0(\WRD[0] ), + .F1(G_1_0), .Q1(\WRD[1] )); + SLICE_85 SLICE_85( .D1(\Din_c[3] ), .C1(\Din_c[5] ), .B1(N_36), + .A1(XOR8MEG18), .C0(N_36), .B0(\Din_c[5] ), .A0(\Din_c[3] ), + .M1(\Din_c[2] ), .M0(\Din_c[1] ), .CE(CmdUFMCLK_1_sqmuxa), .CLK(PHI2_c), + .F0(N_95), .Q0(CmdUFMCLK), .F1(CmdUFMCLK_1_sqmuxa), .Q1(CmdUFMCS)); + SLICE_86 SLICE_86( .D1(\FS[17] ), .C1(\FS[15] ), .B1(\FS[14] ), + .A1(\FS[12] ), .D0(\FS[16] ), .C0(\FS[15] ), .B0(\FS[14] ), .A0(\FS[12] ), + .F0(N_133_5), .F1(UFMSDI_ens2_i_o2_0_3)); + SLICE_87 SLICE_87( .D1(\Din_c[4] ), .C1(\Din_c[6] ), .B1(\Din_c[7] ), + .A1(\Din_c[5] ), .D0(\Din_c[7] ), .C0(\Din_c[6] ), .B0(\Din_c[5] ), + .A0(\Din_c[0] ), .M1(nCCAS_c), .M0(nCCAS_c), .CLK(nCRAS_c), + .F0(CmdEnable16_0_a3_4), .Q0(CBR), .F1(CmdLEDEN_4_u_i_a2_0_0), + .Q1(CBR_fast)); + SLICE_88 SLICE_88( .D1(\Din_c[7] ), .C1(\Din_c[5] ), .B1(\Din_c[3] ), + .A1(\Din_c[1] ), .C0(N_36), .B0(\Din_c[5] ), .A0(\Din_c[3] ), + .M0(\Din_c[0] ), .CE(CmdUFMCLK_1_sqmuxa), .CLK(PHI2_c), .F0(N_45), + .Q0(CmdUFMSDI), .F1(N_122_5)); + SLICE_89 SLICE_89( .D1(\FS[10] ), .C1(\FS[9] ), .B1(\FS[7] ), .A1(\FS[1] ), + .C0(\FS[9] ), .B0(\FS[7] ), .A0(\FS[5] ), .M1(\MAin_c[5] ), + .M0(\MAin_c[4] ), .LSR(Ready_fast), .CLK(nCRAS_c), .F0(N_34), + .Q0(\RowA[4] ), .F1(un1_FS_13_i_a2_9_5), .Q1(\RowA[5] )); + SLICE_90 SLICE_90( .B1(\S[1] ), .A1(CO0), .C0(\S[1] ), .B0(CO0), .A0(CASr2), + .M1(\CROW_c[1] ), .M0(\CROW_c[0] ), .LSR(Ready_fast), .CLK(nCRAS_c), + .F0(RCKEEN_8_u_0_a3_0_0), .Q0(\RBA_c[0] ), .F1(RCKEEN_8_u_0_1_a1_0), .Q1(\RBA_c[1] )); - SLICE_84 SLICE_84( .D1(\FS[11] ), .C1(\FS[10] ), .B1(\FS[8] ), .A1(\FS[6] ), - .D0(\FS[10] ), .C0(\FS[7] ), .B0(\FS[6] ), .A0(\FS[1] ), .F0(N_137_6), - .F1(UFMSDI_ens2_i_a2_4_2)); - SLICE_85 SLICE_85( .D1(\Din_c[4] ), .C1(\Din_c[7] ), .B1(\Din_c[0] ), - .A1(\Din_c[1] ), .D0(\Din_c[7] ), .C0(\Din_c[6] ), .B0(\Din_c[5] ), - .A0(\Din_c[4] ), .M1(\Din_c[3] ), .M0(\Din_c[2] ), .CLK(nCCAS_c), - .F0(un1_Din_4), .Q0(\WRD[2] ), .F1(CmdEnable17_0_a2_3), .Q1(\WRD[3] )); - SLICE_86 SLICE_86( .B1(nRowColSel), .A1(\MAin_c[9] ), .C0(nRowColSel), - .B0(\RowA[9] ), .A0(\MAin_c[9] ), .F0(\RA_c[9] ), .F1(RDQML_c)); - SLICE_87 SLICE_87( .C1(N_151), .B1(UFMSDI_ens2_i_a0), .A1(CmdUFMSDI), - .D0(N_151), .C0(\FS[11] ), .B0(\FS[9] ), .A0(\FS[4] ), .F0(N_137_8), - .F1(UFMSDI_r_xx_mm_1)); - SLICE_88 SLICE_88( .C1(nFWE_c), .B1(\MAin_c[3] ), .A1(\MAin_c[2] ), - .B0(nFWE_c), .A0(nCCAS_c), .M1(\MAin_c[7] ), .M0(\MAin_c[6] ), - .LSR(Ready_fast), .CLK(nCRAS_c), .F0(RD_1_i), .Q0(\RowA[6] ), - .F1(C1WR_0_a2_0_3), .Q1(\RowA[7] )); - SLICE_89 SLICE_89( .B1(nRowColSel), .A1(\MAin_c[9] ), .C0(nRowColSel), - .B0(\RowA[8] ), .A0(\MAin_c[8] ), .F0(\RA_c[8] ), .F1(RDQMH_c)); - SLICE_90 SLICE_90( .C1(\MAin_c[1] ), .B1(\MAin_c[0] ), .A1(N_147), - .C0(nRowColSel), .B0(\RowA[0] ), .A0(\MAin_c[0] ), .F0(\RA_c[0] ), - .F1(un1_CMDWR)); - SLICE_91 SLICE_91( .C1(nRowColSel), .B1(\RowA[7] ), .A1(\MAin_c[7] ), - .C0(nRowColSel), .B0(\RowA[1] ), .A0(\MAin_c[1] ), .F0(\RA_c[1] ), - .F1(\RA_c[7] )); - SLICE_92 SLICE_92( .C1(nRowColSel), .B1(\RowA[6] ), .A1(\MAin_c[6] ), - .C0(nRowColSel), .B0(\RowA[2] ), .A0(\MAin_c[2] ), .F0(\RA_c[2] ), - .F1(\RA_c[6] )); - SLICE_93 SLICE_93( .C1(nRowColSel), .B1(\RowA[5] ), .A1(\MAin_c[5] ), + SLICE_91 SLICE_91( .B1(nRowColSel), .A1(\MAin_c[9] ), .C0(nRowColSel), + .B0(\RowA[9] ), .A0(\MAin_c[9] ), .F0(\RA_c[9] ), .F1(RDQMH_c)); + SLICE_92 SLICE_92( .C1(\IS[1] ), .B1(\IS[2] ), .A1(\IS[3] ), .D0(RASr2), + .C0(\IS[2] ), .B0(\IS[1] ), .A0(\IS[0] ), .F0(m18_0_a3_3), .F1(N_154)); + SLICE_93 SLICE_93( .C1(nRowColSel), .B1(\RowA[1] ), .A1(\MAin_c[1] ), + .D0(\MAin_c[4] ), .C0(\MAin_c[3] ), .B0(\MAin_c[2] ), .A0(\MAin_c[1] ), + .M1(\Din_c[5] ), .M0(\Din_c[4] ), .CLK(PHI2_c), .F0(CMDWR_2), + .Q0(\Bank[4] ), .F1(\RA_c[1] ), .Q1(\Bank[5] )); + SLICE_94 SLICE_94( .D1(\FS[11] ), .C1(\FS[10] ), .B1(\FS[8] ), .A1(\FS[6] ), + .D0(\FS[6] ), .C0(\FS[3] ), .B0(\FS[2] ), .A0(\FS[0] ), + .F0(un1_FS_13_i_a2_9_4), .F1(UFMSDI_ens2_i_a2_4_2)); + SLICE_95 SLICE_95( .B1(\S[1] ), .A1(InitReady), .D0(\S[1] ), .C0(RASr2), + .B0(\IS[3] ), .A0(CO0), .M1(RASr), .M0(nCRAS_c), .CLK(RCLK_c), + .F0(Ready_0_sqmuxa_0_a3_2), .Q0(RASr), .F1(g0_i_a5_2_1), .Q1(RASr2)); + SLICE_96 SLICE_96( .B1(nRowColSel), .A1(\MAin_c[9] ), .C0(nRowColSel), + .B0(\RowA[8] ), .A0(\MAin_c[8] ), .F0(\RA_c[8] ), .F1(RDQML_c)); + SLICE_97 SLICE_97( .C1(nRowColSel), .B1(\RowA[0] ), .A1(\MAin_c[0] ), .C0(nRowColSel), .B0(\RowA[3] ), .A0(\MAin_c[3] ), .F0(\RA_c[3] ), - .F1(\RA_c[5] )); - SLICE_94 SLICE_94( .B1(N_155), .A1(Ready), .B0(\S[1] ), .A0(Ready), - .M0(\IS[0] ), .LSR(RA10s_i), .CLK(RCLK_c), .F0(RCKEEN_8_u_0_a2_1_out), - .Q0(\RA_c[10] ), .F1(N_159_i)); + .F1(\RA_c[0] )); + SLICE_98 SLICE_98( .C1(nRowColSel), .B1(\RowA[2] ), .A1(\MAin_c[2] ), + .C0(nRowColSel), .B0(\RowA[4] ), .A0(\MAin_c[4] ), .F0(\RA_c[4] ), + .F1(\RA_c[2] )); + SLICE_99 SLICE_99( .C1(nRowColSel), .B1(\RowA[7] ), .A1(\MAin_c[7] ), + .C0(nRowColSel), .B0(\RowA[5] ), .A0(\MAin_c[5] ), .F0(\RA_c[5] ), + .F1(\RA_c[7] )); + SLICE_100 SLICE_100( .B1(nFWE_c), .A1(nCCAS_c), .D0(\Bank[4] ), + .C0(\Bank[3] ), .B0(\Bank[1] ), .A0(\Bank[0] ), .F0(un1_Bank_1_4), + .F1(RD_1_i)); + SLICE_101 SLICE_101( .C1(nRowColSel), .B1(\RowA[6] ), .A1(\MAin_c[6] ), + .B0(Ready), .A0(N_148), .M1(nFWE_c), .M0(nFWE_c), .CLK(nCRAS_c), + .F0(N_153_i), .Q0(FWEr), .F1(\RA_c[6] ), .Q1(FWEr_fast)); RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .PADDT(RD_1_i), .PADDO(\WRD[0] ), .RD0(RD[0])); Dout_0_ \Dout[0]_I ( .PADDO(\RD_in[0] ), .Dout0(Dout[0])); @@ -660,21 +681,18 @@ module SLICE_8 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO ); endmodule -module SLICE_9 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, - F1 ); - wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly; +module SLICE_9 ( input B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly; - lut4 CmdEnable17_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut4 ADSubmitted_r_RNO( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); lut40002 ADSubmitted_r( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre ADSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); @@ -691,7 +709,7 @@ endmodule module lut4 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40002 ( input A, B, C, D, output Z ); @@ -704,19 +722,20 @@ module inverter ( input I, output Z ); INV INST1( .A(I), .Z(Z)); endmodule -module SLICE_14 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, - F1 ); - wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly; +module SLICE_14 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, + Q0, F1 ); + wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly; - lut40003 CmdEnable16_0_a2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); + lut40003 CmdEnable_s_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40004 C1Submitted_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre C1Submitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -734,83 +753,36 @@ endmodule module lut40003 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0203) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40004 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hAEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hAAAE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_19 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, - F1 ); - wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; +module SLICE_20 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, + Q0, F1 ); + wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly; - lut40005 Ready_0_sqmuxa_0_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40006 \S_RNO[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0007 \S[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + lut40005 CmdEnable_0_sqmuxa( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40006 CmdEnable_s( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdEnable( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40005 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40006 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module vmuxregsre0007 ( input D0, D1, SD, SP, CK, LSR, output Q ); - - FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module SLICE_20 ( input B1, A1, D0, C0, B0, A0, DI0, M0, CLK, output OFX0, Q0 ); - wire GNDI, \SLICE_20/SLICE_20_K1_H1 , \SLICE_20/CmdEnable_s/GATE_H0 , VCCI, - CLK_NOTIN, DI0_dly, CLK_dly; - - lut40008 SLICE_20_K1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(\SLICE_20/SLICE_20_K1_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40009 \CmdEnable_s/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(\SLICE_20/CmdEnable_s/GATE_H0 )); - vmuxregsre CmdEnable( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - selmux2 SLICE_20_K0K1MUX( .D0(\SLICE_20/CmdEnable_s/GATE_H0 ), - .D1(\SLICE_20/SLICE_20_K1_H1 ), .SD(M0), .Z(OFX0)); - - specify - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (D0 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); @@ -818,38 +790,33 @@ module SLICE_20 ( input B1, A1, D0, C0, B0, A0, DI0, M0, CLK, output OFX0, Q0 ); endmodule -module lut40008 ( input A, B, C, D, output Z ); +module lut40005 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40009 ( input A, B, C, D, output Z ); +module lut40006 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hAC8C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hFFCA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module selmux2 ( input D0, D1, SD, output Z ); - - MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z)); -endmodule - -module SLICE_21 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, +module SLICE_21 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; - lut40010 Cmdn8MEGEN_4_u_i_a2_2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40007 CmdLEDEN_4_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40008 CmdLEDEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40011 CmdLEDEN_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre CmdLEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); @@ -862,21 +829,21 @@ module SLICE_21 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, endmodule -module lut40010 ( input A, B, C, D, output Z ); +module lut40007 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h5D0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40011 ( input A, B, C, D, output Z ); +module lut40008 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0203) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h4545) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_22 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly; - lut40005 un1_FS_14_i_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40012 CmdSubmitted_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40009 un1_FS_14_i_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut4 CmdSubmitted_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre CmdSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); @@ -898,17 +865,17 @@ module SLICE_22 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); endmodule -module lut40012 ( input A, B, C, D, output Z ); +module lut40009 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_26 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; - lut40013 Cmdn8MEGEN_4_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40014 Cmdn8MEGEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40010 Cmdn8MEGEN_4_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40011 Cmdn8MEGEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre Cmdn8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); @@ -932,29 +899,30 @@ module SLICE_26 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, endmodule -module lut40013 ( input A, B, C, D, output Z ); +module lut40010 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h33AB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hB3A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40014 ( input A, B, C, D, output Z ); +module lut40011 ( input A, B, C, D, output Z ); ROM16X1 #(16'h5151) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_29 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, - F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly; +module SLICE_29 ( input C1, B1, A1, C0, B0, A0, DI0, M1, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; - lut40015 nRRAS_5_u_i( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40016 \IS_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40012 Ready_0_sqmuxa_0_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); + lut40013 \IS_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre CASr3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre \IS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -962,19 +930,21 @@ module SLICE_29 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module lut40015 ( input A, B, C, D, output Z ); +module lut40012 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hFF32) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40016 ( input A, B, C, D, output Z ); +module lut40013 ( input A, B, C, D, output Z ); ROM16X1 #(16'hA9A9) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule @@ -983,9 +953,9 @@ module SLICE_30 ( input C1, B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40017 \IS_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40014 \IS_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40018 IS_n1_0_x2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40015 IS_n1_0_x2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre \IS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1009,12 +979,12 @@ module SLICE_30 ( input C1, B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, endmodule -module lut40017 ( input A, B, C, D, output Z ); +module lut40014 ( input A, B, C, D, output Z ); ROM16X1 #(16'h7878) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40018 ( input A, B, C, D, output Z ); +module lut40015 ( input A, B, C, D, output Z ); ROM16X1 #(16'h6666) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule @@ -1023,8 +993,8 @@ module SLICE_31 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; - lut40019 RA10_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40020 \IS_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40016 RA10_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40017 \IS_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \IS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1048,12 +1018,12 @@ module SLICE_31 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output endmodule -module lut40019 ( input A, B, C, D, output Z ); +module lut40016 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hFFEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40020 ( input A, B, C, D, output Z ); +module lut40017 ( input A, B, C, D, output Z ); ROM16X1 #(16'h6AAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule @@ -1061,8 +1031,8 @@ endmodule module SLICE_32 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly; - lut40021 UFMSDI_ens2_i_a0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40012 InitReady_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40018 UFMSDI_ens2_i_a0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut4 InitReady_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre InitReady( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); @@ -1083,23 +1053,24 @@ module SLICE_32 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); endmodule -module lut40021 ( input A, B, C, D, output Z ); +module lut40018 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h4555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h5155) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_33 ( input C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, - F1 ); +module SLICE_33 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - lut40022 LED_pad_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40019 LED_pad_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40020 LEDEN_5_i_m2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40023 LEDEN_5_i_m2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre LEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -1115,28 +1086,68 @@ module SLICE_33 ( input C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, endmodule -module lut40022 ( input A, B, C, D, output Z ); +module lut40019 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hFBFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hFFBF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40023 ( input A, B, C, D, output Z ); +module lut40020 ( input A, B, C, D, output Z ); ROM16X1 #(16'h8B8B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_39 ( input B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); +module SLICE_38 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; + + lut40021 nRCS_RNO_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut4 RA10_2_sqmuxa_0_o2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 RA10( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40021 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0022 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3JY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module SLICE_39 ( input C1, B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, + F1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; - lut40024 XOR8MEG_3_u_0_a3_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40023 Cmdn8MEGEN_4_u_i_o2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40025 RA11_2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0007 RA11( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + lut40024 RA11_2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0025 RA11( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); @@ -1151,22 +1162,28 @@ module SLICE_39 ( input B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); endmodule -module lut40024 ( input A, B, C, D, output Z ); +module lut40023 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hFDFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40025 ( input A, B, C, D, output Z ); +module lut40024 ( input A, B, C, D, output Z ); ROM16X1 #(16'hC6C6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule +module vmuxregsre0025 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + module SLICE_41 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, DI0_dly, CLK_dly, M1_dly; - lut40026 RCKEEN_8_u_1_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40027 RCKEEN_8_u( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40026 RCKEEN_8_u_0_1_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40027 RCKEEN_8_u_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre PHI2r2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1195,29 +1212,28 @@ endmodule module lut40026 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h70CF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0CDC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40027 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hDCCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hCDCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_42 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output - F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, M1_dly; +module SLICE_42 ( input C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; - lut40028 nRWE_RNO_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40028 nRCS_RNO_3( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); lut40029 RCKE_2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre PHI2r( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre RCKE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -1237,7 +1253,7 @@ endmodule module lut40028 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hE0E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40029 ( input A, B, C, D, output Z ); @@ -1249,7 +1265,7 @@ module SLICE_43 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, DI0_dly, CLK_dly, M1_dly; - lut40030 RCKEEN_8_u_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40030 RCKEEN_8_u_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40031 Ready_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre PHI2r3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); @@ -1289,14 +1305,13 @@ endmodule module SLICE_44 ( input D1, C1, B1, A1, B0, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, M1_NOTIN, VCCI, DI0_dly, CLK_dly, M1_dly; + wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; - lut40028 Ready_0_sqmuxa_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40012 Ready_fast_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40032 Ready_0_sqmuxa_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut4 Ready_fast_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre RASr( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN)); + vmuxregsre RASr3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre Ready_fast( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); @@ -1318,13 +1333,18 @@ module SLICE_44 ( input D1, C1, B1, A1, B0, A0, DI0, M1, CLK, output F0, Q0, endmodule +module lut40032 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + module SLICE_50 ( input C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; - lut40032 nRowColSel_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40033 nRowColSel_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40012 \S_0_i_o2[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre0007 \S[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + lut4 \S_0_i_o2[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0025 \S[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); @@ -1344,23 +1364,21 @@ module SLICE_50 ( input C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); endmodule -module lut40032 ( input A, B, C, D, output Z ); +module lut40033 ( input A, B, C, D, output Z ); ROM16X1 #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output - F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, M1_dly; +module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, + Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly; - lut40033 UFMCLK_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40034 UFMCLK_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre RASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); + lut40034 UFMCLK_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40035 UFMCLK_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre UFMCLK( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -1372,37 +1390,33 @@ module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module lut40033 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'hF2F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40034 ( input A, B, C, D, output Z ); + ROM16X1 #(16'hF2F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40035 ( input A, B, C, D, output Z ); + ROM16X1 #(16'h1032) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output - F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, M1_dly; +module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, + Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly; - lut40035 PHI2r3_RNITCN41( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40036 UFMSDI_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre RASr3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); + lut40036 PHI2r3_RNITCN41( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40037 UFMSDI_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre UFMSDI( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -1414,21 +1428,19 @@ module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module lut40035 ( input A, B, C, D, output Z ); +module lut40036 ( input A, B, C, D, output Z ); ROM16X1 #(16'h3B33) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40036 ( input A, B, C, D, output Z ); +module lut40037 ( input A, B, C, D, output Z ); ROM16X1 #(16'h3210) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule @@ -1436,7 +1448,7 @@ endmodule module SLICE_55 ( input C0, B0, A0, M1, M0, CLK, output F0, Q0, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; - lut40037 \un9_RA[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40038 UFMSDI_RNO_0( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \WRD[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); @@ -1459,18 +1471,17 @@ module SLICE_55 ( input C0, B0, A0, M1, M0, CLK, output F0, Q0, Q1 ); endmodule -module lut40037 ( input A, B, C, D, output Z ); +module lut40038 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hACAC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h3232) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_56 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, - F1, Q1 ); +module SLICE_56 ( input B1, A1, B0, A0, M1, M0, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; - lut40038 C1WR_0_a2_0_11( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40039 UFMSDI_ens2_i_o2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40039 un1_FS_14_i_o2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); + lut40040 nRCS_9_u_i_a2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre \WRD[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1479,11 +1490,8 @@ module SLICE_56 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); @@ -1496,31 +1504,29 @@ module SLICE_56 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, endmodule -module lut40038 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40039 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h2C2C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output - F0, Q0, F1 ); - wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly; +module lut40040 ( input A, B, C, D, output Z ); - lut40005 XOR8MEG_3_u_0_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40040 XOR8MEG_3_u_0_a3_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + ROM16X1 #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_57 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; + + lut40041 XOR8MEG_3_u_0_a3( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 XOR8MEG_3_u_0_a3_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre XOR8MEG( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); @@ -1536,7 +1542,12 @@ module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output endmodule -module lut40040 ( input A, B, C, D, output Z ); +module lut40041 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40042 ( input A, B, C, D, output Z ); ROM16X1 #(16'hF7F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule @@ -1545,9 +1556,9 @@ module SLICE_58 ( input C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - lut40041 UFMSDI_en_ss0_0_a2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40043 UFMSDI_en_ss0_0_a2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40023 n8MEGEN_5_i_m2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40020 n8MEGEN_5_i_m2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre n8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1568,24 +1579,23 @@ module SLICE_58 ( input C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, endmodule -module lut40041 ( input A, B, C, D, output Z ); +module lut40043 ( input A, B, C, D, output Z ); ROM16X1 #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, - Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly; +module SLICE_59 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly; - lut40042 un1_nRCAS_6_sqmuxa_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40043 nRCAS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0044 nRCAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + lut40044 nRCAS_RNO_1( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40045 nRCAS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0046 nRCAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -1601,73 +1611,34 @@ module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, endmodule -module lut40042 ( input A, B, C, D, output Z ); +module lut40044 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0BFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h1313) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40043 ( input A, B, C, D, output Z ); +module lut40045 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h2232) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0703) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module vmuxregsre0044 ( input D0, D1, SD, SP, CK, LSR, output Q ); +module vmuxregsre0046 ( input D0, D1, SD, SP, CK, LSR, output Q ); FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); defparam INST01.GSR = "DISABLED"; endmodule -module SLICE_60 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, - Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly; +module SLICE_60 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly; - lut40045 nRCS_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40046 nRCS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0044 nRCS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + lut40047 RCKEEN_8_u_0_a2_0_m1_0_a2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40048 nRCS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0046 nRCS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40045 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'hE6EE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40046 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h3233) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_61 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, - Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly; - - lut40047 nRRAS_5_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40048 nRRAS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0044 nRRAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -1685,21 +1656,21 @@ endmodule module lut40047 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h5400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40048 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h5051) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0307) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, +module SLICE_61 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire VCCI, GNDI, DI0_dly, CLK_dly; - lut40049 nRCAS_0_sqmuxa_1_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40050 nRWE_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0044 nRWE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + lut40049 nRRAS_5_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40050 nRRAS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0046 nRRAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); @@ -1723,11 +1694,49 @@ endmodule module lut40049 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h5400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40050 ( input A, B, C, D, output Z ); + ROM16X1 #(16'h00CD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, + Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly; + + lut40051 nRCAS_0_sqmuxa_1_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40052 nRWE_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0046 nRWE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40051 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40052 ( input A, B, C, D, output Z ); + ROM16X1 #(16'hF4F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule @@ -1735,9 +1744,9 @@ module SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); wire VCCI, DI0_dly, CLK_dly, LSR_dly; - lut40051 nRowColSel_0_0_a3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40052 nRowColSel_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0007 nRowColSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + lut40053 nRowColSel_0_0_a3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40054 nRowColSel_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0025 nRowColSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1759,12 +1768,12 @@ module SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output endmodule -module lut40051 ( input A, B, C, D, output Z ); +module lut40053 ( input A, B, C, D, output Z ); ROM16X1 #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40052 ( input A, B, C, D, output Z ); +module lut40054 ( input A, B, C, D, output Z ); ROM16X1 #(16'hDCEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule @@ -1773,9 +1782,9 @@ module SLICE_64 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire VCCI, GNDI, DI0_dly, CLK_dly; - lut40053 nUFMCS15_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40054 nUFMCS_s_0_N_5_i( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0044 nUFMCS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + lut40055 nUFMCS15_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40056 nUFMCS_s_0_N_5_i( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0046 nUFMCS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); @@ -1797,12 +1806,12 @@ module SLICE_64 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, endmodule -module lut40053 ( input A, B, C, D, output Z ); +module lut40055 ( input A, B, C, D, output Z ); ROM16X1 #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40054 ( input A, B, C, D, output Z ); +module lut40056 ( input A, B, C, D, output Z ); ROM16X1 #(16'hDCFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule @@ -1812,9 +1821,9 @@ module nRWE_RNO_1_SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, output wire \nRWE_RNO_1/SLICE_65/nRWE_RNO_1/SLICE_65_K1_H1 , \nRWE_RNO_1/SLICE_65/nRWE_RNO_1/GATE_H0 ; - lut40055 \nRWE_RNO_1/SLICE_65_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40057 \nRWE_RNO_1/SLICE_65_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/SLICE_65_K1_H1 )); - lut40056 \nRWE_RNO_1/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40058 \nRWE_RNO_1/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/GATE_H0 )); selmux2 \nRWE_RNO_1/SLICE_65_K0K1MUX ( .D0(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/GATE_H0 ), @@ -1834,29 +1843,57 @@ module nRWE_RNO_1_SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, output endmodule -module lut40055 ( input A, B, C, D, output Z ); +module lut40057 ( input A, B, C, D, output Z ); ROM16X1 #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40056 ( input A, B, C, D, output Z ); +module lut40058 ( input A, B, C, D, output Z ); ROM16X1 #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_66 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output +module selmux2 ( input D0, D1, SD, output Z ); + + MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z)); +endmodule + +module SLICE_66 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40016 IS_0_sqmuxa_0_o2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40059 un1_nRCAS_6_sqmuxa_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40059 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0BFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_67 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - lut40057 nUFMCS_s_0_N_5_i_N_2L1( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40060 nUFMCS_s_0_N_5_i_N_2L1( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40049 UFMCLK_r_i_a2_2_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0007 \RowA[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + lut40051 UFMCLK_r_i_a2_2_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0025 \RowA[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0007 \RowA[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + vmuxregsre0025 \RowA[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify @@ -1878,84 +1915,21 @@ module SLICE_66 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output endmodule -module lut40057 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h0B0B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_67 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40058 CmdUFMCLK_1_sqmuxa_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40005 XOR8MEG18_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0059 \RowA[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0007 \RowA[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40058 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module vmuxregsre0059 ( input D0, D1, SD, SP, CK, LSR, output Q ); - - FL1P3JY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40053 un1_FS_14_i_a2_0_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40060 un1_FS_14_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - module lut40060 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hEAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0B0B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, LSR, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, M0_dly, CLK_dly, LSR_dly; - lut40061 un1_FS_13_i_a2_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40060 un1_FS_13_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40061 nRCS_RNO_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40027 nRCS_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0025 \S[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -1966,95 +1940,33 @@ module SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule module lut40061 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_70 ( input D1, C1, B1, A1, B0, A0, M1, M0, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; - - lut4 C1WR_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40062 C1WR_0_a2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \Bank[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \Bank[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40062 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_71 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, - Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly; - - lut4 C1WR_0_a2_0_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut4 C1WR_0_a2_0_10( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \Bank[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \Bank[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_72 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output +module SLICE_69 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - lut40063 UFMSDI_ens2_i_o2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40062 UFMSDI_ens2_i_o2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40064 UFMCLK_r_i_m2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0007 \RowA[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + lut40063 UFMCLK_RNO_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0025 \RowA[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0007 \RowA[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + vmuxregsre0025 \RowA[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify @@ -2076,29 +1988,97 @@ module SLICE_72 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output endmodule -module lut40063 ( input A, B, C, D, output Z ); +module lut40062 ( input A, B, C, D, output Z ); ROM16X1 #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40064 ( input A, B, C, D, output Z ); +module lut40063 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hAAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hD888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_73 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; +module SLICE_70 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; - lut40065 IS_0_sqmuxa_0_o2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40012 IS_0_sqmuxa_0_o2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40064 CMDWR( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40043 un1_CmdEnable20_0_a3( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre CmdUFMCS( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40064 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_71 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40053 un1_FS_14_i_a2_0_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40065 un1_FS_14_i_0( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40065 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hECEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_72 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40051 un1_FS_13_i_a2_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40065 un1_FS_13_i_0( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_73 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40066 CmdSubmitted_1_sqmuxa_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40041 XOR8MEG18( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0025 \RowA[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - vmuxregsre CmdUFMCLK( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0025 \RowA[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -2113,50 +2093,23 @@ module SLICE_73 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module lut40065 ( input A, B, C, D, output Z ); +module lut40066 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_74 ( input B1, A1, D0, C0, B0, A0, M0, CE, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; - - lut40062 InitReady3_0_a2_3( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut4 InitReady3_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre CmdUFMSDI( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - endspecify - -endmodule - -module SLICE_75 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, +module SLICE_74 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, M0_NOTIN, M1_dly, CLK_dly, M0_dly; - lut40066 Cmdn8MEGEN_4_u_i_o2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut4 CmdEnable17_0_o2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40041 CmdLEDEN_4_u_i_a2_0( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40009 CmdEnable17_0_a3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre CASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -2165,9 +2118,9 @@ module SLICE_75 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN)); specify - (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); @@ -2181,28 +2134,24 @@ module SLICE_75 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, endmodule -module lut40066 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'hFDFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_76 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, - Q1 ); +module SLICE_75 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; - lut40024 CmdEnable16_0_a2_4( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40055 CmdEnable16_0_a3_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40067 CmdEnable16_0_a3( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40067 CmdEnable16_0_a2_4_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \Bank[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + vmuxregsre \Bank[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \Bank[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + vmuxregsre \Bank[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); @@ -2218,20 +2167,88 @@ endmodule module lut40067 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_77 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, +module SLICE_76 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly; + + lut40061 C1WR_2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40064 C1WR( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \Bank[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \Bank[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_77 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40061 un1_Bank_1_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40051 ADWR( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_78 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40041 CmdEnable17_0_a2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40009 un1_CmdEnable20_0_a3_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_79 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; - lut40068 CmdEnable16_0_a2_1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40041 ADWR_8_2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40049 CmdEnable16_0_a2_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \Bank[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + lut40005 C1WR_7( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \Bank[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \Bank[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + vmuxregsre \Bank[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify @@ -2251,26 +2268,12 @@ module SLICE_77 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, endmodule -module lut40068 ( input A, B, C, D, output Z ); +module SLICE_80 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; - ROM16X1 #(16'h4444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_78 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, M1_NOTIN, VCCI, CLK_NOTIN, M0_NOTIN, M1_dly, CLK_dly, M0_dly; - - lut40069 CmdEnable17_0_o2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40041 InitReady3_0_a2_3( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40058 CmdEnable17_0_a2_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre CBR_fast( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); - inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - vmuxregsre CBR( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN)); + lut40005 InitReady3_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (B1 => F1) = (0:0:0,0:0:0); @@ -2279,6 +2282,123 @@ module SLICE_78 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40005 ADWR_8_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40005 ADWR_8( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_82 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40068 nRWE_RNO_2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40061 nRWE_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \WRD[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre \WRD[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module lut40068 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_83 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40021 XOR8MEG_3_u_0_o2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40053 XOR8MEG_3_u_0_a3_0_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0022 \RowA[9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0025 \RowA[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40069 nRCAS_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40051 nRCS_RNO_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \WRD[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre \WRD[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); @@ -2291,24 +2411,59 @@ endmodule module lut40069 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h200F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_79 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; +module SLICE_85 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; - lut40070 nRWE_RNO_2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40070 CmdUFMCLK_1_sqmuxa_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40071 Cmdn8MEGEN_4_u_i_a2_2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40038 nRWE_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \WRD[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + vmuxregsre CmdUFMCS( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - vmuxregsre \WRD[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + vmuxregsre CmdUFMCLK( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40070 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40071 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_86 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40021 UFMSDI_ens2_i_o2_0_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40005 InitReady3_0_a2_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -2316,72 +2471,23 @@ module SLICE_79 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); endspecify endmodule -module lut40070 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_80 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40024 nRCAS_RNO_1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40071 nRCAS_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0059 \RowA[9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0007 \RowA[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40071 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h4101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, +module SLICE_87 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, Q1 ); wire M1_NOTIN, VCCI, GNDI, CLK_NOTIN, M0_NOTIN, M1_dly, CLK_dly, M0_dly; - lut40072 UFMSDI_ens2_i_o2_0_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut4 InitReady3_0_a2_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre FWEr_fast( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), + lut40072 CmdLEDEN_4_u_i_a2_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40051 CmdEnable16_0_a3_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CBR_fast( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - vmuxregsre FWEr( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), + vmuxregsre CBR( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN)); @@ -2406,63 +2512,60 @@ endmodule module lut40072 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_82 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0, +module SLICE_88 ( input D1, C1, B1, A1, C0, B0, A0, M0, CE, CLK, output F0, Q0, F1 ); - wire VCCI, GNDI, M0_dly, CLK_dly; + wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; - lut40073 CmdLEDEN_4_u_i_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40074 CmdSubmitted_1_sqmuxa_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre CASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); + lut40061 CmdEnable17_0_a3_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40073 Cmdn8MEGEN_4_u_i_o2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CmdUFMSDI( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40073 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h3222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hF8F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40074 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h0222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_83 ( input C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, - Q0, F1, Q1 ); +module SLICE_89 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output + F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - lut40063 un1_nRCAS_6_sqmuxa_i_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40072 un1_FS_13_i_a2_9_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40074 UFMSDI_ens2_i_o2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40075 Ready_0_sqmuxa_0_o2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0007 \RBA[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + vmuxregsre0022 \RowA[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0007 \RBA[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + vmuxregsre0025 \RowA[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -2480,73 +2583,59 @@ module SLICE_83 ( input C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, endmodule +module lut40074 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h2C2C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_90 ( input B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40075 RCKEEN_8_u_0_1_a1_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40076 RCKEEN_8_u_0_a3_0_0( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0025 \RBA[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0025 \RBA[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + module lut40075 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40028 UFMSDI_ens2_i_a2_4_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40061 un1_FS_13_i_a2_6( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, - Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; - - lut40076 CmdEnable17_0_a2_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40053 un1_Din_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \WRD[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - vmuxregsre \WRD[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - endspecify - + ROM16X1 #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40076 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h7070) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_86 ( input B1, A1, C0, B0, A0, output F0, F1 ); +module SLICE_91 ( input B1, A1, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40069 RDQML( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40077 RDQMH( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40037 \un9_RA[9] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40078 \un9_RA[9] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); specify (B1 => F1) = (0:0:0,0:0:0); @@ -2558,44 +2647,220 @@ module SLICE_86 ( input B1, A1, C0, B0, A0, output F0, F1 ); endmodule -module SLICE_87 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40077 UFMSDI_RNO_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40049 un1_FS_13_i_a2_8( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - module lut40077 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h3232) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_88 ( input C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; +module lut40078 ( input A, B, C, D, output Z ); - lut40078 C1WR_0_a2_0_3( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + ROM16X1 #(16'hACAC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_92 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40062 un1_nRCAS_6_sqmuxa_i_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40012 nCCAS_pad_RNI01SJ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre0007 \RowA[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + lut40032 nRWE_RNO_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_93 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40078 \un9_RA[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40061 CMDWR_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \Bank[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \Bank[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_94 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40032 UFMSDI_ens2_i_a2_4_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40055 un1_FS_13_i_a2_9_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_95 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M0_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40075 nRCS_RNO_4( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40009 Ready_0_sqmuxa_0_a3_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre RASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre RASr( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_96 ( input B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40039 RDQML( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40078 \un9_RA[8] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_97 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40078 \un9_RA[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40078 \un9_RA[3] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_98 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40078 \un9_RA[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40078 \un9_RA[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_99 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40078 \un9_RA[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40078 \un9_RA[5] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_100 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut4 nCCAS_pad_RNI01SJ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40005 un1_Bank_1_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_101 ( input C1, B1, A1, B0, A0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, M1_NOTIN, VCCI, CLK_NOTIN, M0_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40078 \un9_RA[6] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40040 IS_0_sqmuxa_0_o2_0_RNIS63D( .A(A0), .B(B0), .C(GNDI), .D(GNDI), + .Z(F0)); + vmuxregsre FWEr_fast( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0007 \RowA[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + vmuxregsre FWEr( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -2609,146 +2874,10 @@ module SLICE_88 ( input C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, Q0, $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module lut40078 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_89 ( input B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40079 RDQMH( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40037 \un9_RA[8] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40079 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_90 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40080 un1_CMDWR( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40037 \un9_RA[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40080 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'hA8A8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_91 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40037 \un9_RA[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40037 \un9_RA[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module SLICE_92 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40037 \un9_RA[6] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40037 \un9_RA[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module SLICE_93 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40037 \un9_RA[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40037 \un9_RA[3] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module SLICE_94 ( input B1, A1, B0, A0, M0, LSR, CLK, output F0, Q0, F1 ); - wire GNDI, M0_NOTIN, VCCI, M0_dly, CLK_dly, LSR_dly; - - lut40081 IS_0_sqmuxa_0_o2_0_RNIS63D( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40062 RCKEEN_8_u_0_a2_1_s( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre0059 RA10( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40081 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module RD_0_ ( output PADDI, input PADDT, PADDO, inout RD0 ); mjiobuf \RD_pad[0] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD0), .PADI(RD0)); @@ -2771,7 +2900,7 @@ endmodule module Dout_0_ ( input PADDO, output Dout0 ); - mjiobuf0082 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0)); + mjiobuf0079 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0)); specify (PADDO => Dout0) = (0:0:0,0:0:0); @@ -2779,14 +2908,14 @@ module Dout_0_ ( input PADDO, output Dout0 ); endmodule -module mjiobuf0082 ( input I, output PAD ); +module mjiobuf0079 ( input I, output PAD ); OB INST5( .I(I), .O(PAD)); endmodule module PHI2 ( output PADDI, input PHI2 ); - mjiobuf0083 PHI2_pad( .Z(PADDI), .PAD(PHI2)); + mjiobuf0080 PHI2_pad( .Z(PADDI), .PAD(PHI2)); specify (PHI2 => PADDI) = (0:0:0,0:0:0); @@ -2796,14 +2925,14 @@ module PHI2 ( output PADDI, input PHI2 ); endmodule -module mjiobuf0083 ( output Z, input PAD ); +module mjiobuf0080 ( output Z, input PAD ); IB INST1( .I(PAD), .O(Z)); endmodule module UFMSDO ( output PADDI, input UFMSDO ); - mjiobuf0083 UFMSDO_pad( .Z(PADDI), .PAD(UFMSDO)); + mjiobuf0080 UFMSDO_pad( .Z(PADDI), .PAD(UFMSDO)); specify (UFMSDO => PADDI) = (0:0:0,0:0:0); @@ -2815,7 +2944,7 @@ endmodule module UFMSDI ( input PADDO, output UFMSDI ); - mjiobuf0084 UFMSDI_pad( .I(PADDO), .PAD(UFMSDI)); + mjiobuf0081 UFMSDI_pad( .I(PADDO), .PAD(UFMSDI)); specify (PADDO => UFMSDI) = (0:0:0,0:0:0); @@ -2823,14 +2952,14 @@ module UFMSDI ( input PADDO, output UFMSDI ); endmodule -module mjiobuf0084 ( input I, output PAD ); +module mjiobuf0081 ( input I, output PAD ); OB INST5( .I(I), .O(PAD)); endmodule module UFMCLK ( input PADDO, output UFMCLK ); - mjiobuf0084 UFMCLK_pad( .I(PADDO), .PAD(UFMCLK)); + mjiobuf0081 UFMCLK_pad( .I(PADDO), .PAD(UFMCLK)); specify (PADDO => UFMCLK) = (0:0:0,0:0:0); @@ -2840,7 +2969,7 @@ endmodule module nUFMCS ( input PADDO, output nUFMCS ); - mjiobuf0084 nUFMCS_pad( .I(PADDO), .PAD(nUFMCS)); + mjiobuf0081 nUFMCS_pad( .I(PADDO), .PAD(nUFMCS)); specify (PADDO => nUFMCS) = (0:0:0,0:0:0); @@ -2850,7 +2979,7 @@ endmodule module RDQML ( input PADDO, output RDQML ); - mjiobuf0084 RDQML_pad( .I(PADDO), .PAD(RDQML)); + mjiobuf0081 RDQML_pad( .I(PADDO), .PAD(RDQML)); specify (PADDO => RDQML) = (0:0:0,0:0:0); @@ -2860,7 +2989,7 @@ endmodule module RDQMH ( input PADDO, output RDQMH ); - mjiobuf0084 RDQMH_pad( .I(PADDO), .PAD(RDQMH)); + mjiobuf0081 RDQMH_pad( .I(PADDO), .PAD(RDQMH)); specify (PADDO => RDQMH) = (0:0:0,0:0:0); @@ -2870,7 +2999,7 @@ endmodule module nRCAS ( input PADDO, output nRCAS ); - mjiobuf0084 nRCAS_pad( .I(PADDO), .PAD(nRCAS)); + mjiobuf0081 nRCAS_pad( .I(PADDO), .PAD(nRCAS)); specify (PADDO => nRCAS) = (0:0:0,0:0:0); @@ -2880,7 +3009,7 @@ endmodule module nRRAS ( input PADDO, output nRRAS ); - mjiobuf0084 nRRAS_pad( .I(PADDO), .PAD(nRRAS)); + mjiobuf0081 nRRAS_pad( .I(PADDO), .PAD(nRRAS)); specify (PADDO => nRRAS) = (0:0:0,0:0:0); @@ -2890,7 +3019,7 @@ endmodule module nRWE ( input PADDO, output nRWE ); - mjiobuf0084 nRWE_pad( .I(PADDO), .PAD(nRWE)); + mjiobuf0081 nRWE_pad( .I(PADDO), .PAD(nRWE)); specify (PADDO => nRWE) = (0:0:0,0:0:0); @@ -2900,7 +3029,7 @@ endmodule module RCKE ( input PADDO, output RCKE ); - mjiobuf0084 RCKE_pad( .I(PADDO), .PAD(RCKE)); + mjiobuf0081 RCKE_pad( .I(PADDO), .PAD(RCKE)); specify (PADDO => RCKE) = (0:0:0,0:0:0); @@ -2910,7 +3039,7 @@ endmodule module RCLK ( output PADDI, input RCLK ); - mjiobuf0083 RCLK_pad( .Z(PADDI), .PAD(RCLK)); + mjiobuf0080 RCLK_pad( .Z(PADDI), .PAD(RCLK)); specify (RCLK => PADDI) = (0:0:0,0:0:0); @@ -2922,7 +3051,7 @@ endmodule module nRCS ( input PADDO, output nRCS ); - mjiobuf0084 nRCS_pad( .I(PADDO), .PAD(nRCS)); + mjiobuf0081 nRCS_pad( .I(PADDO), .PAD(nRCS)); specify (PADDO => nRCS) = (0:0:0,0:0:0); @@ -3030,7 +3159,7 @@ endmodule module RA_11_ ( input PADDO, output RA11 ); - mjiobuf0084 \RA_pad[11] ( .I(PADDO), .PAD(RA11)); + mjiobuf0081 \RA_pad[11] ( .I(PADDO), .PAD(RA11)); specify (PADDO => RA11) = (0:0:0,0:0:0); @@ -3040,7 +3169,7 @@ endmodule module RA_10_ ( input PADDO, output RA10 ); - mjiobuf0084 \RA_pad[10] ( .I(PADDO), .PAD(RA10)); + mjiobuf0081 \RA_pad[10] ( .I(PADDO), .PAD(RA10)); specify (PADDO => RA10) = (0:0:0,0:0:0); @@ -3050,7 +3179,7 @@ endmodule module RA_9_ ( input PADDO, output RA9 ); - mjiobuf0084 \RA_pad[9] ( .I(PADDO), .PAD(RA9)); + mjiobuf0081 \RA_pad[9] ( .I(PADDO), .PAD(RA9)); specify (PADDO => RA9) = (0:0:0,0:0:0); @@ -3060,7 +3189,7 @@ endmodule module RA_8_ ( input PADDO, output RA8 ); - mjiobuf0084 \RA_pad[8] ( .I(PADDO), .PAD(RA8)); + mjiobuf0081 \RA_pad[8] ( .I(PADDO), .PAD(RA8)); specify (PADDO => RA8) = (0:0:0,0:0:0); @@ -3070,7 +3199,7 @@ endmodule module RA_7_ ( input PADDO, output RA7 ); - mjiobuf0084 \RA_pad[7] ( .I(PADDO), .PAD(RA7)); + mjiobuf0081 \RA_pad[7] ( .I(PADDO), .PAD(RA7)); specify (PADDO => RA7) = (0:0:0,0:0:0); @@ -3080,7 +3209,7 @@ endmodule module RA_6_ ( input PADDO, output RA6 ); - mjiobuf0084 \RA_pad[6] ( .I(PADDO), .PAD(RA6)); + mjiobuf0081 \RA_pad[6] ( .I(PADDO), .PAD(RA6)); specify (PADDO => RA6) = (0:0:0,0:0:0); @@ -3090,7 +3219,7 @@ endmodule module RA_5_ ( input PADDO, output RA5 ); - mjiobuf0084 \RA_pad[5] ( .I(PADDO), .PAD(RA5)); + mjiobuf0081 \RA_pad[5] ( .I(PADDO), .PAD(RA5)); specify (PADDO => RA5) = (0:0:0,0:0:0); @@ -3100,7 +3229,7 @@ endmodule module RA_4_ ( input PADDO, output RA4 ); - mjiobuf0084 \RA_pad[4] ( .I(PADDO), .PAD(RA4)); + mjiobuf0081 \RA_pad[4] ( .I(PADDO), .PAD(RA4)); specify (PADDO => RA4) = (0:0:0,0:0:0); @@ -3110,7 +3239,7 @@ endmodule module RA_3_ ( input PADDO, output RA3 ); - mjiobuf0084 \RA_pad[3] ( .I(PADDO), .PAD(RA3)); + mjiobuf0081 \RA_pad[3] ( .I(PADDO), .PAD(RA3)); specify (PADDO => RA3) = (0:0:0,0:0:0); @@ -3120,7 +3249,7 @@ endmodule module RA_2_ ( input PADDO, output RA2 ); - mjiobuf0084 \RA_pad[2] ( .I(PADDO), .PAD(RA2)); + mjiobuf0081 \RA_pad[2] ( .I(PADDO), .PAD(RA2)); specify (PADDO => RA2) = (0:0:0,0:0:0); @@ -3130,7 +3259,7 @@ endmodule module RA_1_ ( input PADDO, output RA1 ); - mjiobuf0084 \RA_pad[1] ( .I(PADDO), .PAD(RA1)); + mjiobuf0081 \RA_pad[1] ( .I(PADDO), .PAD(RA1)); specify (PADDO => RA1) = (0:0:0,0:0:0); @@ -3140,7 +3269,7 @@ endmodule module RA_0_ ( input PADDO, output RA0 ); - mjiobuf0084 \RA_pad[0] ( .I(PADDO), .PAD(RA0)); + mjiobuf0081 \RA_pad[0] ( .I(PADDO), .PAD(RA0)); specify (PADDO => RA0) = (0:0:0,0:0:0); @@ -3150,7 +3279,7 @@ endmodule module RBA_1_ ( input PADDO, output RBA1 ); - mjiobuf0084 \RBA_pad[1] ( .I(PADDO), .PAD(RBA1)); + mjiobuf0081 \RBA_pad[1] ( .I(PADDO), .PAD(RBA1)); specify (PADDO => RBA1) = (0:0:0,0:0:0); @@ -3160,7 +3289,7 @@ endmodule module RBA_0_ ( input PADDO, output RBA0 ); - mjiobuf0084 \RBA_pad[0] ( .I(PADDO), .PAD(RBA0)); + mjiobuf0081 \RBA_pad[0] ( .I(PADDO), .PAD(RBA0)); specify (PADDO => RBA0) = (0:0:0,0:0:0); @@ -3170,7 +3299,7 @@ endmodule module LED ( input PADDO, output LED ); - mjiobuf0085 LED_pad( .I(PADDO), .PAD(LED)); + mjiobuf0082 LED_pad( .I(PADDO), .PAD(LED)); specify (PADDO => LED) = (0:0:0,0:0:0); @@ -3178,14 +3307,14 @@ module LED ( input PADDO, output LED ); endmodule -module mjiobuf0085 ( input I, output PAD ); +module mjiobuf0082 ( input I, output PAD ); OB INST5( .I(I), .O(PAD)); endmodule module nFWE ( output PADDI, input nFWE ); - mjiobuf0083 nFWE_pad( .Z(PADDI), .PAD(nFWE)); + mjiobuf0080 nFWE_pad( .Z(PADDI), .PAD(nFWE)); specify (nFWE => PADDI) = (0:0:0,0:0:0); @@ -3197,7 +3326,7 @@ endmodule module nCRAS ( output PADDI, input nCRAS ); - mjiobuf0083 nCRAS_pad( .Z(PADDI), .PAD(nCRAS)); + mjiobuf0080 nCRAS_pad( .Z(PADDI), .PAD(nCRAS)); specify (nCRAS => PADDI) = (0:0:0,0:0:0); @@ -3209,7 +3338,7 @@ endmodule module nCCAS ( output PADDI, input nCCAS ); - mjiobuf0083 nCCAS_pad( .Z(PADDI), .PAD(nCCAS)); + mjiobuf0080 nCCAS_pad( .Z(PADDI), .PAD(nCCAS)); specify (nCCAS => PADDI) = (0:0:0,0:0:0); @@ -3221,7 +3350,7 @@ endmodule module Dout_7_ ( input PADDO, output Dout7 ); - mjiobuf0082 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7)); + mjiobuf0079 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7)); specify (PADDO => Dout7) = (0:0:0,0:0:0); @@ -3231,7 +3360,7 @@ endmodule module Dout_6_ ( input PADDO, output Dout6 ); - mjiobuf0082 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6)); + mjiobuf0079 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6)); specify (PADDO => Dout6) = (0:0:0,0:0:0); @@ -3241,7 +3370,7 @@ endmodule module Dout_5_ ( input PADDO, output Dout5 ); - mjiobuf0082 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5)); + mjiobuf0079 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5)); specify (PADDO => Dout5) = (0:0:0,0:0:0); @@ -3251,7 +3380,7 @@ endmodule module Dout_4_ ( input PADDO, output Dout4 ); - mjiobuf0082 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4)); + mjiobuf0079 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4)); specify (PADDO => Dout4) = (0:0:0,0:0:0); @@ -3261,7 +3390,7 @@ endmodule module Dout_3_ ( input PADDO, output Dout3 ); - mjiobuf0082 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3)); + mjiobuf0079 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3)); specify (PADDO => Dout3) = (0:0:0,0:0:0); @@ -3271,7 +3400,7 @@ endmodule module Dout_2_ ( input PADDO, output Dout2 ); - mjiobuf0082 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2)); + mjiobuf0079 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2)); specify (PADDO => Dout2) = (0:0:0,0:0:0); @@ -3281,7 +3410,7 @@ endmodule module Dout_1_ ( input PADDO, output Dout1 ); - mjiobuf0082 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1)); + mjiobuf0079 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1)); specify (PADDO => Dout1) = (0:0:0,0:0:0); @@ -3291,7 +3420,7 @@ endmodule module Din_7_ ( output PADDI, input Din7 ); - mjiobuf0083 \Din_pad[7] ( .Z(PADDI), .PAD(Din7)); + mjiobuf0080 \Din_pad[7] ( .Z(PADDI), .PAD(Din7)); specify (Din7 => PADDI) = (0:0:0,0:0:0); @@ -3303,7 +3432,7 @@ endmodule module Din_6_ ( output PADDI, input Din6 ); - mjiobuf0083 \Din_pad[6] ( .Z(PADDI), .PAD(Din6)); + mjiobuf0080 \Din_pad[6] ( .Z(PADDI), .PAD(Din6)); specify (Din6 => PADDI) = (0:0:0,0:0:0); @@ -3315,7 +3444,7 @@ endmodule module Din_5_ ( output PADDI, input Din5 ); - mjiobuf0083 \Din_pad[5] ( .Z(PADDI), .PAD(Din5)); + mjiobuf0080 \Din_pad[5] ( .Z(PADDI), .PAD(Din5)); specify (Din5 => PADDI) = (0:0:0,0:0:0); @@ -3327,7 +3456,7 @@ endmodule module Din_4_ ( output PADDI, input Din4 ); - mjiobuf0083 \Din_pad[4] ( .Z(PADDI), .PAD(Din4)); + mjiobuf0080 \Din_pad[4] ( .Z(PADDI), .PAD(Din4)); specify (Din4 => PADDI) = (0:0:0,0:0:0); @@ -3339,7 +3468,7 @@ endmodule module Din_3_ ( output PADDI, input Din3 ); - mjiobuf0083 \Din_pad[3] ( .Z(PADDI), .PAD(Din3)); + mjiobuf0080 \Din_pad[3] ( .Z(PADDI), .PAD(Din3)); specify (Din3 => PADDI) = (0:0:0,0:0:0); @@ -3351,7 +3480,7 @@ endmodule module Din_2_ ( output PADDI, input Din2 ); - mjiobuf0083 \Din_pad[2] ( .Z(PADDI), .PAD(Din2)); + mjiobuf0080 \Din_pad[2] ( .Z(PADDI), .PAD(Din2)); specify (Din2 => PADDI) = (0:0:0,0:0:0); @@ -3363,7 +3492,7 @@ endmodule module Din_1_ ( output PADDI, input Din1 ); - mjiobuf0083 \Din_pad[1] ( .Z(PADDI), .PAD(Din1)); + mjiobuf0080 \Din_pad[1] ( .Z(PADDI), .PAD(Din1)); specify (Din1 => PADDI) = (0:0:0,0:0:0); @@ -3375,7 +3504,7 @@ endmodule module Din_0_ ( output PADDI, input Din0 ); - mjiobuf0083 \Din_pad[0] ( .Z(PADDI), .PAD(Din0)); + mjiobuf0080 \Din_pad[0] ( .Z(PADDI), .PAD(Din0)); specify (Din0 => PADDI) = (0:0:0,0:0:0); @@ -3387,7 +3516,7 @@ endmodule module CROW_1_ ( output PADDI, input CROW1 ); - mjiobuf0083 \CROW_pad[1] ( .Z(PADDI), .PAD(CROW1)); + mjiobuf0080 \CROW_pad[1] ( .Z(PADDI), .PAD(CROW1)); specify (CROW1 => PADDI) = (0:0:0,0:0:0); @@ -3399,7 +3528,7 @@ endmodule module CROW_0_ ( output PADDI, input CROW0 ); - mjiobuf0083 \CROW_pad[0] ( .Z(PADDI), .PAD(CROW0)); + mjiobuf0080 \CROW_pad[0] ( .Z(PADDI), .PAD(CROW0)); specify (CROW0 => PADDI) = (0:0:0,0:0:0); @@ -3411,7 +3540,7 @@ endmodule module MAin_9_ ( output PADDI, input MAin9 ); - mjiobuf0083 \MAin_pad[9] ( .Z(PADDI), .PAD(MAin9)); + mjiobuf0080 \MAin_pad[9] ( .Z(PADDI), .PAD(MAin9)); specify (MAin9 => PADDI) = (0:0:0,0:0:0); @@ -3423,7 +3552,7 @@ endmodule module MAin_8_ ( output PADDI, input MAin8 ); - mjiobuf0083 \MAin_pad[8] ( .Z(PADDI), .PAD(MAin8)); + mjiobuf0080 \MAin_pad[8] ( .Z(PADDI), .PAD(MAin8)); specify (MAin8 => PADDI) = (0:0:0,0:0:0); @@ -3435,7 +3564,7 @@ endmodule module MAin_7_ ( output PADDI, input MAin7 ); - mjiobuf0083 \MAin_pad[7] ( .Z(PADDI), .PAD(MAin7)); + mjiobuf0080 \MAin_pad[7] ( .Z(PADDI), .PAD(MAin7)); specify (MAin7 => PADDI) = (0:0:0,0:0:0); @@ -3447,7 +3576,7 @@ endmodule module MAin_6_ ( output PADDI, input MAin6 ); - mjiobuf0083 \MAin_pad[6] ( .Z(PADDI), .PAD(MAin6)); + mjiobuf0080 \MAin_pad[6] ( .Z(PADDI), .PAD(MAin6)); specify (MAin6 => PADDI) = (0:0:0,0:0:0); @@ -3459,7 +3588,7 @@ endmodule module MAin_5_ ( output PADDI, input MAin5 ); - mjiobuf0083 \MAin_pad[5] ( .Z(PADDI), .PAD(MAin5)); + mjiobuf0080 \MAin_pad[5] ( .Z(PADDI), .PAD(MAin5)); specify (MAin5 => PADDI) = (0:0:0,0:0:0); @@ -3471,7 +3600,7 @@ endmodule module MAin_4_ ( output PADDI, input MAin4 ); - mjiobuf0083 \MAin_pad[4] ( .Z(PADDI), .PAD(MAin4)); + mjiobuf0080 \MAin_pad[4] ( .Z(PADDI), .PAD(MAin4)); specify (MAin4 => PADDI) = (0:0:0,0:0:0); @@ -3483,7 +3612,7 @@ endmodule module MAin_3_ ( output PADDI, input MAin3 ); - mjiobuf0083 \MAin_pad[3] ( .Z(PADDI), .PAD(MAin3)); + mjiobuf0080 \MAin_pad[3] ( .Z(PADDI), .PAD(MAin3)); specify (MAin3 => PADDI) = (0:0:0,0:0:0); @@ -3495,7 +3624,7 @@ endmodule module MAin_2_ ( output PADDI, input MAin2 ); - mjiobuf0083 \MAin_pad[2] ( .Z(PADDI), .PAD(MAin2)); + mjiobuf0080 \MAin_pad[2] ( .Z(PADDI), .PAD(MAin2)); specify (MAin2 => PADDI) = (0:0:0,0:0:0); @@ -3507,7 +3636,7 @@ endmodule module MAin_1_ ( output PADDI, input MAin1 ); - mjiobuf0083 \MAin_pad[1] ( .Z(PADDI), .PAD(MAin1)); + mjiobuf0080 \MAin_pad[1] ( .Z(PADDI), .PAD(MAin1)); specify (MAin1 => PADDI) = (0:0:0,0:0:0); @@ -3519,7 +3648,7 @@ endmodule module MAin_0_ ( output PADDI, input MAin0 ); - mjiobuf0083 \MAin_pad[0] ( .Z(PADDI), .PAD(MAin0)); + mjiobuf0080 \MAin_pad[0] ( .Z(PADDI), .PAD(MAin0)); specify (MAin0 => PADDI) = (0:0:0,0:0:0); diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mrp.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mrp.html index 0803b67..15fdd38 100644 --- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mrp.html +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mrp.html @@ -23,17 +23,17 @@ Target Vendor: LATTICE Target Device: LCMXO256CTQFP100 Target Performance: 3 Mapper: mj5g00, version: Diamond (64-bit) 3.12.1.454 -Mapped on: 09/21/23 05:38:29 +Mapped on: 01/06/24 06:24:57 Design Summary Number of PFU registers: 92 out of 256 (36%) - Number of SLICEs: 69 out of 128 (54%) - SLICEs as Logic/ROM: 69 out of 128 (54%) + Number of SLICEs: 76 out of 128 (59%) + SLICEs as Logic/ROM: 76 out of 128 (59%) SLICEs as RAM: 0 out of 64 (0%) SLICEs as Carry: 9 out of 128 (7%) - Number of LUT4s: 137 out of 256 (54%) - Number used as logic LUTs: 119 + Number of LUT4s: 151 out of 256 (59%) + Number used as logic LUTs: 133 Number used as distributed RAM: 0 Number used as ripple logic: 18 Number used as shift registers: 0 @@ -56,28 +56,29 @@ Mapped on: 09/21/23 05:38:29 Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS ) Number of Clock Enables: 5 Net XOR8MEG18: 3 loads, 3 LSLICEs - Net N_31: 1 loads, 1 LSLICEs - Net N_33: 1 loads, 1 LSLICEs - Net N_159_i: 2 loads, 2 LSLICEs + Net N_24: 1 loads, 1 LSLICEs + Net N_26: 1 loads, 1 LSLICEs + Net N_153_i: 2 loads, 2 LSLICEs Net CmdUFMCLK_1_sqmuxa: 2 loads, 2 LSLICEs - Number of LSRs: 4 + Number of LSRs: 5 Net RA10s_i: 1 loads, 1 LSLICEs Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs - Net RASr2: 2 loads, 2 LSLICEs + Net RASr2: 1 loads, 1 LSLICEs Net Ready_fast: 7 loads, 7 LSLICEs + Net RCKEEN_8_u_0_1_a1_0: 1 loads, 1 LSLICEs Number of nets driven by tri-state buffers: 0 - Top 10 highest fanout non-clock nets: - Net InitReady: 16 loads - Net Ready: 16 loads - Net S[1]: 13 loads - Net CO0: 12 loads + Top 10 highest fanout non-clock nets: + Net Ready: 18 loads + Net InitReady: 17 loads + Net S[1]: 17 loads + Net CO0: 16 loads + Net RASr2: 13 loads Net nRowColSel: 12 loads - Net RASr2: 11 loads Net Din_c[5]: 10 loads Net Din_c[3]: 9 loads Net IS[0]: 9 loads - Net MAin_c[1]: 8 loads + Net IS[1]: 8 loads @@ -126,8 +127,8 @@ Mapped on: 09/21/23 05:38:29 | nRWE | OUTPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | RCKE | OUTPUT | LVCMOS33 | | | -+---------------------+-----------+-----------+------------+------------+ ++---------------------+-----------+-----------+------------+------------+ | RCLK | INPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | nRCS | OUTPUT | LVCMOS33 | | | @@ -183,8 +184,8 @@ Mapped on: 09/21/23 05:38:29 | nCCAS | INPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | Dout[7] | OUTPUT | LVCMOS33 | | | -+---------------------+-----------+-----------+------------+------------+ ++---------------------+-----------+-----------+------------+------------+ | Dout[6] | OUTPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | Dout[5] | OUTPUT | LVCMOS33 | | | @@ -243,7 +244,6 @@ Mapped on: 09/21/23 05:38:29 - Removed logic Block GSR_INST undriven or does not drive anything - clipped. @@ -252,7 +252,6 @@ Signal nFWE_c_i was merged into signal nFWE_c Signal nCRAS_c_i_0 was merged into signal nCRAS_c Signal nCCAS_c_i was merged into signal nCCAS_c Signal Ready_fast_i was merged into signal Ready_fast -Signal IS_i[0] was merged into signal IS[0] Signal RASr2_i was merged into signal RASr2 Signal XOR8MEG.CN was merged into signal PHI2_c Signal GND undriven or does not drive anything - clipped. @@ -272,8 +271,7 @@ Block nFWE_pad_RNI420B was optimized away. Block RASr_RNO was optimized away. Block nCCAS_pad_RNISUR8 was optimized away. Block Ready_fast_RNI29NA was optimized away. -Block IS_i[0] was optimized away. -Block RASr2_RNIAFR1 was optimized away. +Block S_RNO[1] was optimized away. Block XOR8MEG.CN was optimized away. Block GND was optimized away. Block VCC was optimized away. @@ -304,6 +302,8 @@ Block VCC was optimized away. + + Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_pad.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_pad.html index a2aec36..2bd8ffb 100644 --- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_pad.html +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_pad.html @@ -14,7 +14,7 @@ Performance Grade: 3 PACKAGE: TQFP100 Package Status: Final Version 1.19 -Thu Sep 21 05:38:42 2023 +Sat Jan 06 06:25:11 2024 Pinout by Port Name: +-----------+----------+---------------+------+----------------------------------+ @@ -276,7 +276,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Thu Sep 21 05:38:42 2023 +Sat Jan 06 06:25:11 2024 diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_par.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_par.html index 3e42fe5..3c0fddf 100644 --- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_par.html +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_par.html @@ -12,7 +12,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Thu Sep 21 05:38:31 2023 +Sat Jan 06 06:25:01 2024 C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO256C_impl1.p2t RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir @@ -26,17 +26,17 @@ Preference file: RAM2GS_LCMXO256C_impl1.prf. Level/ Number Worst Timing Worst Timing Run NCD Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status ---------- -------- ----- ------ ----------- ----------- ---- ------ -5_1 * 0 8.213 0 0.273 0 12 Completed +5_1 * 0 6.770 0 0.273 0 11 Completed * : Design saved. -Total (real) run time for 1-seed: 12 secs +Total (real) run time for 1-seed: 11 secs par done! Note: user must run 'Trace' for timing closure signoff. Lattice Place and Route Report for Design "RAM2GS_LCMXO256C_impl1_map.ncd" -Thu Sep 21 05:38:31 2023 +Sat Jan 06 06:25:01 2024 Best Par Run @@ -65,12 +65,12 @@ Ignore Preference Error(s): True PIO (prelim) 67/79 84% used 67/78 85% bonded - SLICE 69/128 53% used + SLICE 76/128 59% used -Number of Signals: 251 -Number of Connections: 633 +Number of Signals: 266 +Number of Connections: 681 Pin Constraint Summary: 67 out of 67 pins locked (100% locked). @@ -84,17 +84,17 @@ The following 1 signal is selected to use the secondary clock routing resources: No signal is selected as Global Set/Reset. Starting Placer Phase 0. -........ +...... Finished Placer Phase 0. REAL time: 0 secs Starting Placer Phase 1. ................. -Placer score = 582801. -Finished Placer Phase 1. REAL time: 10 secs +Placer score = 783987. +Finished Placer Phase 1. REAL time: 9 secs Starting Placer Phase 2. . -Placer score = 582334 +Placer score = 783552 Finished Placer Phase 2. REAL time: 10 secs @@ -134,7 +134,7 @@ Total placer CPU time: 9 secs Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd. -0 connections routed; 633 unrouted. +0 connections routed; 681 unrouted. Starting router resource preassignment WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew. WARNING - par: The driver of secondary clock net nCRAS_c is not placed on one of the PIO sites dedicated for secondary clocks. This secondary clock will be routed through general routing resource and may suffer from excessive delay or skew. @@ -142,9 +142,9 @@ WARNING - par: The driver of secondary clock net nCRAS_c is not placed on one of WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. Signal=nCCAS_c loads=8 clock_loads=4 -Completed router resource preassignment. Real time: 11 secs +Completed router resource preassignment. Real time: 10 secs -Start NBR router at 05:38:42 09/21/23 +Start NBR router at 06:25:11 01/06/24 ***************************************************************** Info: NBR allows conflicts(one node used by more than one signal) @@ -159,41 +159,44 @@ Note: NBR uses a different method to calculate timing slacks. The your design. ***************************************************************** -Start NBR special constraint process at 05:38:42 09/21/23 +Start NBR special constraint process at 06:25:11 01/06/24 -Start NBR section for initial routing at 05:38:42 09/21/23 +Start NBR section for initial routing at 06:25:11 01/06/24 Level 1, iteration 1 -0(0.00%) conflict; 545(86.10%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 8.344ns/0.000ns; real time: 11 secs +0(0.00%) conflict; 593(87.08%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack<setup>: 7.904ns/0.000ns; real time: 10 secs Level 2, iteration 1 -0(0.00%) conflict; 543(85.78%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 8.344ns/0.000ns; real time: 11 secs +0(0.00%) conflict; 592(86.93%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack<setup>: 8.083ns/0.000ns; real time: 10 secs Level 3, iteration 1 -0(0.00%) conflict; 543(85.78%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 8.405ns/0.000ns; real time: 11 secs +0(0.00%) conflict; 591(86.78%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack<setup>: 7.994ns/0.000ns; real time: 10 secs Level 4, iteration 1 -10(0.08%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 8.213ns/0.000ns; real time: 11 secs +13(0.11%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack<setup>: 7.278ns/0.000ns; real time: 10 secs Info: Initial congestion level at 75% usage is 0 Info: Initial congestion area at 75% usage is 0 (0.00%) -Start NBR section for normal routing at 05:38:42 09/21/23 +Start NBR section for normal routing at 06:25:11 01/06/24 Level 4, iteration 1 -5(0.04%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 8.213ns/0.000ns; real time: 11 secs +7(0.06%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack<setup>: 6.770ns/0.000ns; real time: 10 secs Level 4, iteration 2 +4(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack<setup>: 6.770ns/0.000ns; real time: 10 secs +Level 4, iteration 3 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 8.213ns/0.000ns; real time: 11 secs +Estimated worst slack/total negative slack<setup>: 6.770ns/0.000ns; real time: 10 secs -Start NBR section for setup/hold timing optimization with effort level 3 at 05:38:42 09/21/23 +Start NBR section for setup/hold timing optimization with effort level 3 at 06:25:11 01/06/24 -Start NBR section for re-routing at 05:38:42 09/21/23 +Start NBR section for re-routing at 06:25:11 01/06/24 Level 4, iteration 1 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 8.213ns/0.000ns; real time: 11 secs +Estimated worst slack/total negative slack<setup>: 6.770ns/0.000ns; real time: 10 secs -Start NBR section for post-routing at 05:38:42 09/21/23 +Start NBR section for post-routing at 06:25:11 01/06/24 End NBR router with 0 unrouted connection @@ -201,7 +204,7 @@ NBR Summary ----------- Number of unrouted connections : 0 (0.00%) Number of connections with timing violations : 0 (0.00%) - Estimated worst slack<setup> : 8.213ns + Estimated worst slack<setup> : 6.770ns Timing score<setup> : 0 ----------- Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. @@ -212,9 +215,9 @@ WARNING - par: The following clock signals will be routed by using generic routi Signal=nCCAS_c loads=8 clock_loads=4 Total CPU time 10 secs -Total REAL time: 12 secs +Total REAL time: 11 secs Completely routed. -End of route. 633 routed (100.00%); 0 unrouted. +End of route. 681 routed (100.00%); 0 unrouted. Hold time timing score: 0, hold timing errors: 0 @@ -228,14 +231,14 @@ All signals are completely routed. PAR_SUMMARY::Run status = Completed PAR_SUMMARY::Number of unrouted conns = 0 -PAR_SUMMARY::Worst slack<setup/<ns>> = 8.213 +PAR_SUMMARY::Worst slack<setup/<ns>> = 6.770 PAR_SUMMARY::Timing score<setup/<ns>> = 0.000 PAR_SUMMARY::Worst slack<hold /<ns>> = 0.273 PAR_SUMMARY::Timing score<hold /<ns>> = 0.000 PAR_SUMMARY::Number of errors = 0 Total CPU time to completion: 10 secs -Total REAL time to completion: 12 secs +Total REAL time to completion: 11 secs par done! diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_scck.rpt b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_scck.rpt index 1ef397f..990c73a 100644 --- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_scck.rpt +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_scck.rpt @@ -13,7 +13,7 @@ Hostname: ZANEMACWIN11 Implementation : impl1 -# Written on Thu Sep 21 05:38:19 2023 +# Written on Sat Jan 6 06:24:50 2024 ##### FILES SYNTAX CHECKED ############################################## Constraint File(s): "\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc" diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_summary.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_summary.html index b990416..717bdfa 100644 --- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_summary.html +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_summary.html @@ -62,7 +62,7 @@ Updated: -2023/09/21 05:38:51 +2024/01/06 06:25:20 Implementation Location: diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_synplify.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_synplify.html index 08ed40b..368f07a 100644 --- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_synplify.html +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_synplify.html @@ -12,7 +12,7 @@ #OS: Windows 8 6.2 #Hostname: ZANEMACWIN11 -# Thu Sep 21 05:38:16 2023 +# Sat Jan 6 06:24:47 2024 #Implementation: impl1 @@ -59,19 +59,22 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-SPI.v" (library work) Verilog syntax check successful! + +Compiler output is up to date. No re-compile necessary + Selecting top level module RAM2GS @N: CG364 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work. Running optimization stage 1 on RAM2GS ....... -Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 100MB) +Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 100MB) Running optimization stage 2 on RAM2GS ....... Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB) -At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 96MB peak: 97MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Sep 21 05:38:17 2023 +# Sat Jan 6 06:24:47 2024 ###########################################################] ###########################################################[ @@ -98,7 +101,7 @@ At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Sep 21 05:38:17 2023 +# Sat Jan 6 06:24:48 2024 ###########################################################] @@ -113,7 +116,7 @@ At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Sep 21 05:38:17 2023 +# Sat Jan 6 06:24:48 2024 ###########################################################] ###########################################################[ @@ -134,18 +137,17 @@ Implementation : impl1 Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ @N|Running in 64-bit mode +File \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Sep 21 05:38:18 2023 +# Sat Jan 6 06:24:49 2024 ###########################################################] -Premap Report - -# Thu Sep 21 05:38:19 2023 +# Sat Jan 6 06:24:49 2024 Copyright (C) 1994-2021 Synopsys, Inc. @@ -167,7 +169,7 @@ Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB) -Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 140MB) +Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 140MB) Reading constraint file: \\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc @L: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1_scck.rpt @@ -195,7 +197,6 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h @N: FX493 |Applying initial value "0" on instance CmdLEDEN. @N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN. @N: FX493 |Applying initial value "1" on instance nRCS. -@N: FX493 |Applying initial value "0" on instance LEDEN. @N: FX493 |Applying initial value "0" on instance n8MEGEN. @N: FX493 |Applying initial value "1" on instance nRRAS. @N: FX493 |Applying initial value "0" on instance CmdUFMCLK. @@ -214,17 +215,17 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) -Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) +Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) -Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) +Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) -Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) +Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) @N: FX1184 |Applying syn_allowed_resources blockrams=0 on top level netlist RAM2GS -Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 181MB peak: 181MB) +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) @@ -291,10 +292,10 @@ Clock Tree ID Driving Element Drive Element Type Fanout Sample I @N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. -Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB) +Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) -Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB) +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB) Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB) @@ -303,13 +304,11 @@ Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 98MB peak: 184MB) -Process took 0h:00m:02s realtime, 0h:00m:01s cputime -# Thu Sep 21 05:38:21 2023 +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Sat Jan 6 06:24:51 2024 ###########################################################] -Map & Optimize Report - -# Thu Sep 21 05:38:21 2023 +# Sat Jan 6 06:24:51 2024 Copyright (C) 1994-2021 Synopsys, Inc. @@ -328,29 +327,29 @@ Implementation : impl1 Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @ -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB) +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB) @N: MF916 |Option synthesis_strategy=base is enabled. @N: MF248 |Running in 64-bit mode. @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 140MB) +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 139MB) -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 140MB) +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 139MB) -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB) +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB) -Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 179MB peak: 179MB) +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 178MB peak: 178MB) -Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) @N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":147:4:147:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] @N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":134:4:134:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] @@ -360,10 +359,10 @@ Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00 @N: FX493 |Applying initial value "0" on instance IS[2]. @N: FX493 |Applying initial value "0" on instance IS[3]. -Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 184MB peak: 184MB) +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 184MB peak: 184MB) -Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB) +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 185MB peak: 185MB) Available hyper_sources - for debug and ip models @@ -376,64 +375,61 @@ Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CP Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 187MB) -Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB) +Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB) -Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB) +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB) -Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB) +Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB) -Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB) +Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ - 1 0h:00m:01s -3.26ns 127 / 89 - 2 0h:00m:01s -3.23ns 123 / 89 - 3 0h:00m:01s -3.23ns 123 / 89 - 4 0h:00m:01s -3.23ns 123 / 89 - 5 0h:00m:01s -3.23ns 124 / 89 - 6 0h:00m:01s -3.23ns 124 / 89 -@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 7 loads 1 time to improve timing. -@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing. -@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":147:4:147:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 15 loads 1 time to improve timing. + 1 0h:00m:01s -4.01ns 133 / 89 + 2 0h:00m:01s -3.96ns 131 / 89 +@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 8 loads 1 time to improve timing. +@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 7 loads 1 time to improve timing. +@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":147:4:147:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 19 loads 1 time to improve timing. Timing driven replication report Added 3 Registers via timing driven replication Added 1 LUTs via timing driven replication - 7 0h:00m:02s -2.99ns 128 / 92 + 3 0h:00m:02s -3.08ns 143 / 92 + 4 0h:00m:02s -3.08ns 141 / 92 - 8 0h:00m:02s -2.99ns 127 / 92 - 9 0h:00m:02s -3.09ns 127 / 92 - 10 0h:00m:02s -3.19ns 127 / 92 - 11 0h:00m:02s -3.19ns 127 / 92 - 12 0h:00m:02s -3.19ns 127 / 92 + 5 0h:00m:02s -3.08ns 140 / 92 + 6 0h:00m:02s -3.19ns 140 / 92 + 7 0h:00m:02s -3.19ns 140 / 92 + 8 0h:00m:02s -3.19ns 140 / 92 + 9 0h:00m:02s -3.19ns 140 / 92 -Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 190MB) +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 191MB) -Finished restoring hierarchy (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 191MB) +Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 191MB) -Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 155MB peak: 191MB) +Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 155MB peak: 192MB) Writing Analyst data base \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_m.srm -Finished Writing Netlist Databases (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 192MB peak: 192MB) +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 192MB) Writing EDIF Netlist and constraint files @N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.edi @N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF -Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 196MB peak: 196MB) +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 196MB peak: 196MB) -Finished Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 196MB peak: 196MB) +Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 196MB peak: 197MB) -Start final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 194MB peak: 196MB) +Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 195MB peak: 197MB) @N: MT615 |Found clock RCLK with period 16.00ns @N: MT615 |Found clock PHI2 with period 350.00ns @@ -442,7 +438,7 @@ Start final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:0 ##### START OF TIMING REPORT #####[ -# Timing report written on Thu Sep 21 05:38:27 2023 +# Timing report written on Sat Jan 6 06:24:55 2024 # @@ -475,8 +471,8 @@ nCRAS 2.9 MHz 0.6 MHz 350.000 1613.150 -3.60 Estimated period and frequency reported as NA means no slack depends directly on the clock waveform -@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. @W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small. +@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. @W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. @W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small. @W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small. @@ -490,10 +486,10 @@ Clocks | rise to rise | fall to fall | rise to --------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack --------------------------------------------------------------------------------------------------------------- -RCLK RCLK | 16.000 7.560 | No paths - | No paths - | No paths - +RCLK RCLK | 16.000 7.464 | No paths - | No paths - | No paths - RCLK PHI2 | 2.000 -1.216 | No paths - | 1.000 -2.312 | No paths - PHI2 RCLK | No paths - | No paths - | No paths - | 1.000 -3.705 -PHI2 PHI2 | No paths - | 350.000 343.998 | 175.000 166.500 | 175.000 171.784 +PHI2 PHI2 | No paths - | 350.000 344.094 | 175.000 165.215 | 175.000 171.784 nCRAS RCLK | No paths - | No paths - | No paths - | 1.000 -3.609 =============================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. @@ -527,10 +523,10 @@ CmdUFMCS PHI2 FD1P3AX Q CmdUFMCS 1.348 CmdUFMSDI PHI2 FD1P3AX Q CmdUFMSDI 1.348 -3.297 CmdLEDEN PHI2 FD1P3AX Q CmdLEDEN 1.456 -2.216 Cmdn8MEGEN PHI2 FD1P3AX Q Cmdn8MEGEN 1.456 -2.216 -Bank[2] PHI2 FD1S3AX Q Bank[2] 1.348 166.500 -Bank[3] PHI2 FD1S3AX Q Bank[3] 1.348 166.500 -Bank[4] PHI2 FD1S3AX Q Bank[4] 1.348 166.500 -Bank[5] PHI2 FD1S3AX Q Bank[5] 1.348 166.500 +Bank[0] PHI2 FD1S3AX Q Bank[0] 1.348 165.215 +Bank[1] PHI2 FD1S3AX Q Bank[1] 1.348 165.215 +Bank[2] PHI2 FD1S3AX Q Bank[2] 1.348 165.215 +Bank[3] PHI2 FD1S3AX Q Bank[3] 1.348 165.215 ======================================================================================= @@ -544,13 +540,13 @@ Instance Reference Type Pin Net Time UFMCLK PHI2 FD1S3AX D UFMCLK_RNO -0.003 -3.705 UFMSDI PHI2 FD1S3AX D UFMSDI_RNO -0.003 -3.705 nUFMCS PHI2 FD1S3AY D nUFMCS_s_0_N_5_i -0.003 -3.705 -LEDEN PHI2 FD1P3AX SP N_33 0.806 -2.800 -n8MEGEN PHI2 FD1P3AX SP N_31 0.806 -2.800 -LEDEN PHI2 FD1P3AX D N_70 -0.003 -2.216 -n8MEGEN PHI2 FD1P3AX D N_69 -0.003 -2.216 -CmdSubmitted PHI2 FD1S3AX D N_460_0 173.997 166.500 -ADSubmitted PHI2 FD1S3AX D ADSubmitted_r 173.997 167.797 -C1Submitted PHI2 FD1S3AX D C1Submitted_RNO 173.997 167.797 +LEDEN PHI2 FD1P3AX SP N_26 0.806 -2.800 +n8MEGEN PHI2 FD1P3AX SP N_24 0.806 -2.800 +LEDEN PHI2 FD1P3AX D N_49 -0.003 -2.216 +n8MEGEN PHI2 FD1P3AX D N_48 -0.003 -2.216 +CmdEnable PHI2 FD1S3AX D CmdEnable_s 173.997 165.215 +CmdSubmitted PHI2 FD1S3AX D N_428_0 173.997 165.311 +ADSubmitted PHI2 FD1S3AX D ADSubmitted_r 173.997 166.404 ============================================================================================ @@ -582,7 +578,7 @@ CmdSubmitted FD1S3AX Q Out 1.552 1.552 r - CmdSubmitted Net - - - - 3 PHI2r3_RNITCN41 ORCALUT4 A In 0.000 1.552 r - PHI2r3_RNITCN41 ORCALUT4 Z Out 1.393 2.945 r - -N_139_i Net - - - - 3 +N_137_i Net - - - - 3 UFMCLK_RNO ORCALUT4 A In 0.000 2.945 r - UFMCLK_RNO ORCALUT4 Z Out 0.757 3.702 r - UFMCLK_RNO Net - - - - 1 @@ -613,7 +609,7 @@ CmdSubmitted FD1S3AX Q Out 1.552 1.552 r - CmdSubmitted Net - - - - 3 PHI2r3_RNITCN41 ORCALUT4 A In 0.000 1.552 r - PHI2r3_RNITCN41 ORCALUT4 Z Out 1.393 2.945 r - -N_139_i Net - - - - 3 +N_137_i Net - - - - 3 nUFMCS_s_0_N_5_i ORCALUT4 A In 0.000 2.945 r - nUFMCS_s_0_N_5_i ORCALUT4 Z Out 0.757 3.702 r - nUFMCS_s_0_N_5_i Net - - - - 1 @@ -644,7 +640,7 @@ CmdSubmitted FD1S3AX Q Out 1.552 1.552 r - CmdSubmitted Net - - - - 3 PHI2r3_RNITCN41 ORCALUT4 A In 0.000 1.552 r - PHI2r3_RNITCN41 ORCALUT4 Z Out 1.393 2.945 r - -N_139_i Net - - - - 3 +N_137_i Net - - - - 3 UFMSDI_RNO ORCALUT4 A In 0.000 2.945 r - UFMSDI_RNO ORCALUT4 Z Out 0.757 3.702 r - UFMSDI_RNO Net - - - - 1 @@ -663,21 +659,21 @@ Detailed Report for Clock: RCLK Starting Points with Worst Slack ******************************** - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------ -LEDEN RCLK FD1P3AX Q LEDEN 1.552 -2.312 -n8MEGEN RCLK FD1P3AX Q n8MEGEN 1.456 -2.216 -FS[13] RCLK FD1S3AX Q FS[13] 1.552 7.560 -FS[14] RCLK FD1S3AX Q FS[14] 1.552 7.560 -FS[15] RCLK FD1S3AX Q FS[15] 1.552 7.560 -FS[17] RCLK FD1S3AX Q FS[17] 1.552 7.560 -S[1] RCLK FD1S3IX Q S[1] 1.768 8.533 -S[0] RCLK FD1S3IX Q CO0 1.756 8.545 -FS[16] RCLK FD1S3AX Q FS[16] 1.612 8.689 -FS[12] RCLK FD1S3AX Q FS[12] 1.552 8.749 -============================================================================= + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------- +LEDEN RCLK FD1P3AX Q LEDEN 1.552 -2.312 +n8MEGEN RCLK FD1P3AX Q n8MEGEN 1.456 -2.216 +FS[12] RCLK FD1S3AX Q FS[12] 1.552 7.464 +FS[14] RCLK FD1S3AX Q FS[14] 1.552 7.464 +FS[15] RCLK FD1S3AX Q FS[15] 1.552 7.464 +FS[17] RCLK FD1S3AX Q FS[17] 1.552 7.464 +InitReady RCLK FD1S3AX Q InitReady 1.792 8.569 +S[1] RCLK FD1S3IX Q S[1] 1.792 8.569 +S[0] RCLK FD1S3IX Q CO0 1.780 8.581 +FS[13] RCLK FD1S3AX Q FS[13] 1.612 8.593 +================================================================================ Ending Points with Worst Slack @@ -687,16 +683,16 @@ Ending Points with Worst Slack Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------- -CmdLEDEN RCLK FD1P3AX D N_21_i -0.003 -2.312 +CmdLEDEN RCLK FD1P3AX D N_14_i -0.003 -2.312 XOR8MEG RCLK FD1P3AX D XOR8MEG_3 -0.003 -2.312 -Cmdn8MEGEN RCLK FD1P3AX D N_19_i -0.003 -2.216 +Cmdn8MEGEN RCLK FD1P3AX D N_12_i -0.003 -2.216 RA11 RCLK FD1S3IX D RA11_2 0.997 -1.216 -UFMSDI RCLK FD1S3AX D UFMSDI_RNO 14.997 7.560 +UFMSDI RCLK FD1S3AX D UFMSDI_RNO 14.997 7.464 UFMCLK RCLK FD1S3AX D UFMCLK_RNO 14.997 7.668 -LEDEN RCLK FD1P3AX SP N_33 15.806 8.261 -n8MEGEN RCLK FD1P3AX SP N_31 15.806 8.261 -nRCS RCLK FD1S3AY D N_28_i 14.997 8.533 +nRCAS RCLK FD1S3AY D N_46_i 14.997 8.569 nUFMCS RCLK FD1S3AY D nUFMCS_s_0_N_5_i 14.997 8.653 +nRCS RCLK FD1S3AY D N_143_i 14.997 8.881 +LEDEN RCLK FD1P3AX SP N_26 15.806 9.463 ========================================================================================= @@ -726,9 +722,9 @@ Name Type Name Dir Delay Time Fan Out(s --------------------------------------------------------------------------------- LEDEN FD1P3AX Q Out 1.552 1.552 r - LEDEN Net - - - - 3 -CmdLEDEN_RNO ORCALUT4 A In 0.000 1.552 r - +CmdLEDEN_RNO ORCALUT4 B In 0.000 1.552 r - CmdLEDEN_RNO ORCALUT4 Z Out 0.757 2.309 r - -N_21_i Net - - - - 1 +N_14_i Net - - - - 1 CmdLEDEN FD1P3AX D In 0.000 2.309 r - ================================================================================= @@ -749,16 +745,16 @@ Path information for path number 2: The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK The end point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------- -LEDEN FD1P3AX Q Out 1.552 1.552 r - -LEDEN Net - - - - 3 -XOR8MEG_3_u_0_a3_3 ORCALUT4 B In 0.000 1.552 r - -XOR8MEG_3_u_0_a3_3 ORCALUT4 Z Out 0.757 2.309 f - -XOR8MEG_3 Net - - - - 1 -XOR8MEG FD1P3AX D In 0.000 2.309 f - -===================================================================================== +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------------- +LEDEN FD1P3AX Q Out 1.552 1.552 r - +LEDEN Net - - - - 3 +XOR8MEG_3_u_0_a3_0_2 ORCALUT4 B In 0.000 1.552 r - +XOR8MEG_3_u_0_a3_0_2 ORCALUT4 Z Out 0.757 2.309 f - +XOR8MEG_3 Net - - - - 1 +XOR8MEG FD1P3AX D In 0.000 2.309 f - +======================================================================================= Path information for path number 3: @@ -784,7 +780,7 @@ n8MEGEN FD1P3AX Q Out 1.456 1.456 r - n8MEGEN Net - - - - 2 Cmdn8MEGEN_RNO ORCALUT4 C In 0.000 1.456 r - Cmdn8MEGEN_RNO ORCALUT4 Z Out 0.757 2.213 r - -N_19_i Net - - - - 1 +N_12_i Net - - - - 1 Cmdn8MEGEN FD1P3AX D In 0.000 2.213 r - ================================================================================= @@ -804,10 +800,10 @@ Starting Points with Worst Slack Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------- -CBR nCRAS FD1S3AX Q CBR 1.660 -3.609 -CBR_fast nCRAS FD1S3AX Q CBR_fast 1.456 -3.513 +CBR_fast nCRAS FD1S3AX Q CBR_fast 1.552 -3.609 +CBR nCRAS FD1S3AX Q CBR 1.612 -3.561 FWEr nCRAS FD1S3AX Q FWEr 1.552 -3.501 -FWEr_fast nCRAS FD1S3AX Q FWEr_fast 1.456 -3.405 +FWEr_fast nCRAS FD1S3AX Q FWEr_fast 1.552 -3.501 ================================================================================ @@ -818,11 +814,11 @@ Ending Points with Worst Slack Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------- -nRWE nCRAS FD1S3AY D N_39_i -0.003 -3.609 -nRowColSel nCRAS FD1S3IX D nRowColSel_0_0 -0.003 -3.609 -nRCAS nCRAS FD1S3AY D N_37_i -0.003 -3.513 -RCKEEN nCRAS FD1S3AX D RCKEEN_8 -0.003 -3.405 -nRCS nCRAS FD1S3AY D N_28_i -0.003 -3.405 +nRCAS nCRAS FD1S3AY D N_46_i -0.003 -3.609 +nRWE nCRAS FD1S3AY D N_144_i -0.003 -3.609 +nRowColSel nCRAS FD1S3IX D nRowColSel_0_0 -0.003 -3.561 +RCKEEN nCRAS FD1S3AX D RCKEEN_8 -0.003 -3.501 +nRCS nCRAS FD1S3AY D N_143_i -0.003 -3.501 ======================================================================================= @@ -842,24 +838,24 @@ Path information for path number 1: = Slack (non-critical) : -3.609 Number of logic level(s): 2 - Starting point: CBR / Q - Ending point: nRWE / D + Starting point: CBR_fast / Q + Ending point: nRCAS / D The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------- -CBR FD1S3AX Q Out 1.660 1.660 r - -CBR Net - - - - 5 -nRWE_RNO_0 ORCALUT4 A In 0.000 1.660 r - -nRWE_RNO_0 ORCALUT4 Z Out 1.189 2.849 f - -G_17_1 Net - - - - 1 -nRWE_RNO ORCALUT4 B In 0.000 2.849 f - -nRWE_RNO ORCALUT4 Z Out 0.757 3.606 r - -N_39_i Net - - - - 1 -nRWE FD1S3AY D In 0.000 3.606 r - -================================================================================= +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +---------------------------------------------------------------------------------------- +CBR_fast FD1S3AX Q Out 1.552 1.552 r - +CBR_fast Net - - - - 3 +nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 A In 0.000 1.552 r - +nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 Z Out 1.297 2.849 r - +nRCAS_0_sqmuxa_1 Net - - - - 2 +nRCAS_RNO ORCALUT4 C In 0.000 2.849 r - +nRCAS_RNO ORCALUT4 Z Out 0.757 3.606 f - +N_46_i Net - - - - 1 +nRCAS FD1S3AY D In 0.000 3.606 f - +======================================================================================== Path information for path number 2: @@ -873,24 +869,24 @@ Path information for path number 2: = Slack (non-critical) : -3.609 Number of logic level(s): 2 - Starting point: CBR / Q - Ending point: nRowColSel / D + Starting point: CBR_fast / Q + Ending point: nRWE / D The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------- -CBR FD1S3AX Q Out 1.660 1.660 r - -CBR Net - - - - 5 -nRowColSel_0_0_a3_0 ORCALUT4 B In 0.000 1.660 r - -nRowColSel_0_0_a3_0 ORCALUT4 Z Out 1.189 2.849 f - -N_179 Net - - - - 1 -nRowColSel_0_0 ORCALUT4 B In 0.000 2.849 f - -nRowColSel_0_0 ORCALUT4 Z Out 0.757 3.606 f - -nRowColSel_0_0 Net - - - - 1 -nRowColSel FD1S3IX D In 0.000 3.606 f - -====================================================================================== +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +---------------------------------------------------------------------------------------- +CBR_fast FD1S3AX Q Out 1.552 1.552 r - +CBR_fast Net - - - - 3 +nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 A In 0.000 1.552 r - +nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 Z Out 1.297 2.849 r - +nRCAS_0_sqmuxa_1 Net - - - - 2 +nRWE_RNO ORCALUT4 C In 0.000 2.849 r - +nRWE_RNO ORCALUT4 Z Out 0.757 3.606 r - +N_144_i Net - - - - 1 +nRWE FD1S3AY D In 0.000 3.606 r - +======================================================================================== Path information for path number 3: @@ -899,29 +895,29 @@ Path information for path number 3: + Clock delay at ending point: 0.000 (ideal) = Required time: -0.003 - - Propagation time: 3.510 + - Propagation time: 3.558 - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : -3.513 + = Slack (non-critical) : -3.561 Number of logic level(s): 2 - Starting point: CBR_fast / Q + Starting point: CBR / Q Ending point: nRCAS / D The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------- -CBR_fast FD1S3AX Q Out 1.456 1.456 r - -CBR_fast Net - - - - 2 -nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 A In 0.000 1.456 r - -nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 Z Out 1.297 2.753 r - -nRCAS_0_sqmuxa_1 Net - - - - 2 -nRCAS_RNO ORCALUT4 B In 0.000 2.753 r - -nRCAS_RNO ORCALUT4 Z Out 0.757 3.510 f - -N_37_i Net - - - - 1 -nRCAS FD1S3AY D In 0.000 3.510 f - -======================================================================================== +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------- +CBR FD1S3AX Q Out 1.612 1.612 r - +CBR Net - - - - 4 +nRCAS_RNO_1 ORCALUT4 A In 0.000 1.612 r - +nRCAS_RNO_1 ORCALUT4 Z Out 1.189 2.801 f - +G_1_1 Net - - - - 1 +nRCAS_RNO ORCALUT4 B In 0.000 2.801 f - +nRCAS_RNO ORCALUT4 Z Out 0.757 3.558 r - +N_46_i Net - - - - 1 +nRCAS FD1S3AY D In 0.000 3.558 r - +================================================================================= @@ -929,10 +925,10 @@ nRCAS FD1S3AY D In 0.000 3.510 f - Timing exceptions that could not be applied -Finished final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 195MB peak: 196MB) +Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 196MB peak: 197MB) -Finished timing report (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 195MB peak: 196MB) +Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 196MB peak: 197MB) --------------------------------------- Resource Usage Report @@ -953,19 +949,19 @@ FD1S3IX: 14 FD1S3JX: 3 GSR: 1 IB: 26 -INV: 8 +INV: 7 OB: 33 -ORCALUT4: 119 -PFUMX: 2 +ORCALUT4: 133 +PFUMX: 1 PUR: 1 VHI: 1 VLO: 1 Mapper successful! -At Mapper Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 80MB peak: 196MB) +At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 78MB peak: 197MB) -Process took 0h:00m:05s realtime, 0h:00m:04s cputime -# Thu Sep 21 05:38:27 2023 +Process took 0h:00m:03s realtime, 0h:00m:03s cputime +# Sat Jan 6 06:24:55 2024 ###########################################################] diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_tw1.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_tw1.html index 612084e..7efd519 100644 --- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_tw1.html +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_tw1.html @@ -22,7 +22,7 @@ Setup and Hold Report -------------------------------------------------------------------------------- Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 -Thu Sep 21 05:38:30 2023 +Sat Jan 06 06:24:59 2024 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -41,8 +41,8 @@ Report level: verbose report, limited to 1 item per preference Preference Summary -
  • FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)
    • 129 items scored, 0 timing errors detected. -Report: 51.046MHz is the maximum frequency for this preference. +
  • FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)
    • 168 items scored, 0 timing errors detected. +Report: 43.077MHz is the maximum frequency for this preference.
  • FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)
    • 0 items scored, 0 timing errors detected. Report: 400.000MHz is the maximum frequency for this preference. @@ -50,8 +50,8 @@ Report: 400.000MHz is the maximum frequency for this preference.
  • FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)
    • 0 items scored, 0 timing errors detected. Report: 400.000MHz is the maximum frequency for this preference. -
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    • 388 items scored, 0 timing errors detected. -Report: 88.456MHz is the maximum frequency for this preference. +
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    • 392 items scored, 0 timing errors detected. +Report: 102.020MHz is the maximum frequency for this preference. BLOCK ASYNCPATHS BLOCK RESETPATHS @@ -61,46 +61,48 @@ BLOCK RESETPATHS ================================================================================ Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ; - 129 items scored, 0 timing errors detected. + 168 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- -Passed: The following path meets requirements by 162.619ns (weighted slack = 325.238ns) +Passed: The following path meets requirements by 160.807ns (weighted slack = 321.614ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank[2] (from PHI2_c +) - Destination: FF Data in CmdSubmitted (to PHI2_c -) + Source: FF Q Bank[6] (from PHI2_c +) + Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 9.621ns (25.1% logic, 74.9% route), 6 logic levels. + Delay: 11.433ns (24.4% logic, 75.6% route), 7 logic levels. Constraint Details: - 9.621ns physical path delay SLICE_71 to SLICE_22 meets + 11.433ns physical path delay SLICE_75 to SLICE_20 meets 172.414ns delay constraint less - 0.174ns DIN_SET requirement (totaling 172.240ns) by 162.619ns + 0.174ns DIN_SET requirement (totaling 172.240ns) by 160.807ns Physical Path Details: - Data path SLICE_71 to SLICE_22: + Data path SLICE_75 to SLICE_20: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 SLICE_71.CLK to SLICE_71.Q0 SLICE_71 (from PHI2_c) -ROUTE 1 e 1.441 SLICE_71.Q0 to SLICE_56.A1 Bank[2] -CTOF_DEL --- 0.371 SLICE_56.A1 to SLICE_56.F1 SLICE_56 -ROUTE 1 e 1.441 SLICE_56.F1 to SLICE_70.D1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 SLICE_70.D1 to SLICE_70.F1 SLICE_70 -ROUTE 6 e 1.441 SLICE_70.F1 to SLICE_67.D0 N_147 -CTOF_DEL --- 0.371 SLICE_67.D0 to SLICE_67.F0 SLICE_67 -ROUTE 5 e 1.441 SLICE_67.F0 to SLICE_82.A0 XOR8MEG18 -CTOF_DEL --- 0.371 SLICE_82.A0 to SLICE_82.F0 SLICE_82 -ROUTE 1 e 1.441 SLICE_82.F0 to SLICE_22.A0 CmdSubmitted_1_sqmuxa -CTOF_DEL --- 0.371 SLICE_22.A0 to SLICE_22.F0 SLICE_22 -ROUTE 1 e 0.001 SLICE_22.F0 to SLICE_22.DI0 N_460_0 (to PHI2_c) +REG_DEL --- 0.560 SLICE_75.CLK to SLICE_75.Q0 SLICE_75 (from PHI2_c) +ROUTE 1 e 1.441 SLICE_75.Q0 to SLICE_77.C1 Bank[6] +CTOF_DEL --- 0.371 SLICE_77.C1 to SLICE_77.F1 SLICE_77 +ROUTE 2 e 1.441 SLICE_77.F1 to SLICE_79.D0 un1_Bank_1_5 +CTOF_DEL --- 0.371 SLICE_79.D0 to SLICE_79.F0 SLICE_79 +ROUTE 2 e 1.441 SLICE_79.F0 to SLICE_76.B0 C1WR_7 +CTOF_DEL --- 0.371 SLICE_76.B0 to SLICE_76.F0 SLICE_76 +ROUTE 5 e 1.441 SLICE_76.F0 to SLICE_70.B0 C1WR +CTOF_DEL --- 0.371 SLICE_70.B0 to SLICE_70.F0 SLICE_70 +ROUTE 1 e 1.441 SLICE_70.F0 to SLICE_14.C1 N_121 +CTOF_DEL --- 0.371 SLICE_14.C1 to SLICE_14.F1 SLICE_14 +ROUTE 1 e 1.441 SLICE_14.F1 to SLICE_20.C0 un1_CmdEnable20_i +CTOF_DEL --- 0.371 SLICE_20.C0 to SLICE_20.F0 SLICE_20 +ROUTE 1 e 0.001 SLICE_20.F0 to SLICE_20.DI0 CmdEnable_s (to PHI2_c) -------- - 9.621 (25.1% logic, 74.9% route), 6 logic levels. + 11.433 (24.4% logic, 75.6% route), 7 logic levels. -Report: 51.046MHz is the maximum frequency for this preference. +Report: 43.077MHz is the maximum frequency for this preference. ================================================================================ @@ -141,46 +143,46 @@ Report: 400.000MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; - 388 items scored, 0 timing errors detected. + 392 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- -Passed: The following path meets requirements by 4.695ns +Passed: The following path meets requirements by 6.198ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[17] (from RCLK_c +) - Destination: FF Data in LEDEN (to RCLK_c +) + Destination: FF Data in UFMSDI (to RCLK_c +) - Delay: 11.061ns (21.8% logic, 78.2% route), 6 logic levels. + Delay: 9.621ns (25.1% logic, 74.9% route), 6 logic levels. Constraint Details: - 11.061ns physical path delay SLICE_1 to SLICE_33 meets + 9.621ns physical path delay SLICE_1 to SLICE_52 meets 16.000ns delay constraint less - 0.244ns CE_SET requirement (totaling 15.756ns) by 4.695ns + 0.181ns DIN_SET requirement (totaling 15.819ns) by 6.198ns Physical Path Details: - Data path SLICE_1 to SLICE_33: + Data path SLICE_1 to SLICE_52: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.560 SLICE_1.CLK to SLICE_1.Q1 SLICE_1 (from RCLK_c) -ROUTE 3 e 1.441 SLICE_1.Q1 to SLICE_81.D1 FS[17] -CTOF_DEL --- 0.371 SLICE_81.D1 to SLICE_81.F1 SLICE_81 -ROUTE 1 e 1.441 SLICE_81.F1 to SLICE_72.C1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 SLICE_72.C1 to SLICE_72.F1 SLICE_72 -ROUTE 4 e 1.441 SLICE_72.F1 to SLICE_58.C1 N_51 +ROUTE 3 e 1.441 SLICE_1.Q1 to SLICE_86.D1 FS[17] +CTOF_DEL --- 0.371 SLICE_86.D1 to SLICE_86.F1 SLICE_86 +ROUTE 1 e 1.441 SLICE_86.F1 to SLICE_69.C1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.371 SLICE_69.C1 to SLICE_69.F1 SLICE_69 +ROUTE 4 e 1.441 SLICE_69.F1 to SLICE_58.C1 N_128 CTOF_DEL --- 0.371 SLICE_58.C1 to SLICE_58.F1 SLICE_58 -ROUTE 2 e 1.441 SLICE_58.F1 to SLICE_87.D0 N_151 -CTOF_DEL --- 0.371 SLICE_87.D0 to SLICE_87.F0 SLICE_87 -ROUTE 2 e 1.441 SLICE_87.F0 to SLICE_69.C0 N_137_8 -CTOF_DEL --- 0.371 SLICE_69.C0 to SLICE_69.F0 SLICE_69 -ROUTE 1 e 1.441 SLICE_69.F0 to SLICE_33.CE N_33 (to RCLK_c) +ROUTE 3 e 1.441 SLICE_58.F1 to SLICE_55.C0 N_94 +CTOF_DEL --- 0.371 SLICE_55.C0 to SLICE_55.F0 SLICE_55 +ROUTE 1 e 1.441 SLICE_55.F0 to SLICE_52.D0 UFMSDI_r_xx_mm_1 +CTOF_DEL --- 0.371 SLICE_52.D0 to SLICE_52.F0 SLICE_52 +ROUTE 1 e 0.001 SLICE_52.F0 to SLICE_52.DI0 UFMSDI_RNO (to RCLK_c) -------- - 11.061 (21.8% logic, 78.2% route), 6 logic levels. + 9.621 (25.1% logic, 74.9% route), 6 logic levels. -Report: 88.456MHz is the maximum frequency for this preference. +Report: 102.020MHz is the maximum frequency for this preference. Report Summary -------------- @@ -188,13 +190,13 @@ Report: 88.456MHz is the maximum frequency for this preference. Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | -FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 51.046 MHz| 6 +FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 43.077 MHz| 7 | | | FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 400.000 MHz| 0 | | | FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 400.000 MHz| 0 | | | -FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 88.456 MHz| 6 +FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 102.020 MHz| 6 | | | ---------------------------------------------------------------------------- @@ -249,11 +251,11 @@ Clock Domain: PHI2_c Source: PHI2.PAD Loads: 15 Timing errors: 0 Score: 0 Cumulative negative slack: 0 -Constraints cover 517 paths, 4 nets, and 395 connections (62.40% coverage) +Constraints cover 560 paths, 4 nets, and 424 connections (62.26% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 -Thu Sep 21 05:38:30 2023 +Sat Jan 06 06:24:59 2024 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -272,13 +274,13 @@ Report level: verbose report, limited to 1 item per preference Preference Summary -
  • FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)
    • 129 items scored, 0 timing errors detected. +
  • FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)
    • 168 items scored, 0 timing errors detected.
  • FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)
    • 0 items scored, 0 timing errors detected.
  • FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)
    • 0 items scored, 0 timing errors detected. -
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    • 388 items scored, 0 timing errors detected. +
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    • 392 items scored, 0 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS @@ -288,7 +290,7 @@ BLOCK RESETPATHS ================================================================================ Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ; - 129 items scored, 0 timing errors detected. + 168 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- @@ -334,7 +336,7 @@ ROUTE 1 e 0.001 SLICE_14.F0 to SLICE_14.DI0 C1Submitted_RNO (to P ================================================================================ Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; - 388 items scored, 0 timing errors detected. + 392 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- @@ -349,17 +351,17 @@ Passed: The following path meets requirements by 0.342ns Constraint Details: - 0.325ns physical path delay SLICE_75 to SLICE_75 meets + 0.325ns physical path delay SLICE_74 to SLICE_74 meets -0.017ns M_HLD and 0.000ns delay constraint requirement (totaling -0.017ns) by 0.342ns Physical Path Details: - Data path SLICE_75 to SLICE_75: + Data path SLICE_74 to SLICE_74: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.126 SLICE_75.CLK to SLICE_75.Q0 SLICE_75 (from RCLK_c) -ROUTE 1 e 0.199 SLICE_75.Q0 to SLICE_75.M1 CASr (to RCLK_c) +REG_DEL --- 0.126 SLICE_74.CLK to SLICE_74.Q0 SLICE_74 (from RCLK_c) +ROUTE 1 e 0.199 SLICE_74.Q0 to SLICE_74.M1 CASr (to RCLK_c) -------- 0.325 (38.8% logic, 61.2% route), 1 logic levels. @@ -430,7 +432,7 @@ Clock Domain: PHI2_c Source: PHI2.PAD Loads: 15 Timing errors: 0 Score: 0 Cumulative negative slack: 0 -Constraints cover 517 paths, 4 nets, and 395 connections (62.40% coverage) +Constraints cover 560 paths, 4 nets, and 424 connections (62.26% coverage) diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_twr.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_twr.html index 1e9c86d..422a429 100644 --- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_twr.html +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_twr.html @@ -22,7 +22,7 @@ Setup and Hold Report -------------------------------------------------------------------------------- Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 -Thu Sep 21 05:38:43 2023 +Sat Jan 06 06:25:12 2024 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -41,8 +41,8 @@ Report level: verbose report, limited to 10 items per preference Preference Summary -
  • FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)
    • 129 items scored, 0 timing errors detected. -Report: 56.029MHz is the maximum frequency for this preference. +
  • FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)
    • 168 items scored, 0 timing errors detected. +Report: 47.219MHz is the maximum frequency for this preference.
  • FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)
    • 0 items scored, 0 timing errors detected. Report: 400.000MHz is the maximum frequency for this preference. @@ -50,8 +50,8 @@ Report: 400.000MHz is the maximum frequency for this preference.
  • FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)
    • 0 items scored, 0 timing errors detected. Report: 400.000MHz is the maximum frequency for this preference. -
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    • 388 items scored, 0 timing errors detected. -Report: 128.419MHz is the maximum frequency for this preference. +
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    • 392 items scored, 0 timing errors detected. +Report: 108.342MHz is the maximum frequency for this preference. BLOCK ASYNCPATHS BLOCK RESETPATHS @@ -61,528 +61,557 @@ BLOCK RESETPATHS ================================================================================ Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ; - 129 items scored, 0 timing errors detected. + 168 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- -Passed: The following path meets requirements by 163.490ns (weighted slack = 326.980ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank[2] (from PHI2_c +) - Destination: FF Data in CmdSubmitted (to PHI2_c -) - - Delay: 8.750ns (27.6% logic, 72.4% route), 6 logic levels. - - Constraint Details: - - 8.750ns physical path delay SLICE_71 to SLICE_22 meets - 172.414ns delay constraint less - 0.000ns skew and - 0.174ns DIN_SET requirement (totaling 172.240ns) by 163.490ns - - Physical Path Details: - - Data path SLICE_71 to SLICE_22: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R6C2C.CLK to R6C2C.Q0 SLICE_71 (from PHI2_c) -ROUTE 1 1.583 R6C2C.Q0 to R4C5A.A1 Bank[2] -CTOF_DEL --- 0.371 R4C5A.A1 to R4C5A.F1 SLICE_56 -ROUTE 1 1.643 R4C5A.F1 to R5C2C.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R5C2C.B1 to R5C2C.F1 SLICE_70 -ROUTE 6 1.075 R5C2C.F1 to R5C3A.A0 N_147 -CTOF_DEL --- 0.371 R5C3A.A0 to R5C3A.F0 SLICE_67 -ROUTE 5 1.215 R5C3A.F0 to R6C4D.D0 XOR8MEG18 -CTOF_DEL --- 0.371 R6C4D.D0 to R6C4D.F0 SLICE_82 -ROUTE 1 0.819 R6C4D.F0 to R6C4A.C0 CmdSubmitted_1_sqmuxa -CTOF_DEL --- 0.371 R6C4A.C0 to R6C4A.F0 SLICE_22 -ROUTE 1 0.000 R6C4A.F0 to R6C4A.DI0 N_460_0 (to PHI2_c) - -------- - 8.750 (27.6% logic, 72.4% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_71: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.919 39.PADDI to R6C2C.CLK PHI2_c - -------- - 3.919 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_22: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.919 39.PADDI to R6C4A.CLK PHI2_c - -------- - 3.919 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 163.526ns (weighted slack = 327.052ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank[5] (from PHI2_c +) - Destination: FF Data in CmdSubmitted (to PHI2_c -) - - Delay: 8.714ns (27.7% logic, 72.3% route), 6 logic levels. - - Constraint Details: - - 8.714ns physical path delay SLICE_76 to SLICE_22 meets - 172.414ns delay constraint less - 0.000ns skew and - 0.174ns DIN_SET requirement (totaling 172.240ns) by 163.526ns - - Physical Path Details: - - Data path SLICE_76 to SLICE_22: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R6C3D.CLK to R6C3D.Q1 SLICE_76 (from PHI2_c) -ROUTE 1 1.547 R6C3D.Q1 to R4C5A.B1 Bank[5] -CTOF_DEL --- 0.371 R4C5A.B1 to R4C5A.F1 SLICE_56 -ROUTE 1 1.643 R4C5A.F1 to R5C2C.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R5C2C.B1 to R5C2C.F1 SLICE_70 -ROUTE 6 1.075 R5C2C.F1 to R5C3A.A0 N_147 -CTOF_DEL --- 0.371 R5C3A.A0 to R5C3A.F0 SLICE_67 -ROUTE 5 1.215 R5C3A.F0 to R6C4D.D0 XOR8MEG18 -CTOF_DEL --- 0.371 R6C4D.D0 to R6C4D.F0 SLICE_82 -ROUTE 1 0.819 R6C4D.F0 to R6C4A.C0 CmdSubmitted_1_sqmuxa -CTOF_DEL --- 0.371 R6C4A.C0 to R6C4A.F0 SLICE_22 -ROUTE 1 0.000 R6C4A.F0 to R6C4A.DI0 N_460_0 (to PHI2_c) - -------- - 8.714 (27.7% logic, 72.3% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_76: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.919 39.PADDI to R6C3D.CLK PHI2_c - -------- - 3.919 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_22: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.919 39.PADDI to R6C4A.CLK PHI2_c - -------- - 3.919 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 163.560ns (weighted slack = 327.120ns) +Passed: The following path meets requirements by 161.825ns (weighted slack = 323.650ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Bank[7] (from PHI2_c +) - Destination: FF Data in CmdSubmitted (to PHI2_c -) - - Delay: 8.680ns (27.8% logic, 72.2% route), 6 logic levels. - - Constraint Details: - - 8.680ns physical path delay SLICE_77 to SLICE_22 meets - 172.414ns delay constraint less - 0.000ns skew and - 0.174ns DIN_SET requirement (totaling 172.240ns) by 163.560ns - - Physical Path Details: - - Data path SLICE_77 to SLICE_22: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R6C3A.CLK to R6C3A.Q1 SLICE_77 (from PHI2_c) -ROUTE 1 1.513 R6C3A.Q1 to R4C5A.D1 Bank[7] -CTOF_DEL --- 0.371 R4C5A.D1 to R4C5A.F1 SLICE_56 -ROUTE 1 1.643 R4C5A.F1 to R5C2C.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R5C2C.B1 to R5C2C.F1 SLICE_70 -ROUTE 6 1.075 R5C2C.F1 to R5C3A.A0 N_147 -CTOF_DEL --- 0.371 R5C3A.A0 to R5C3A.F0 SLICE_67 -ROUTE 5 1.215 R5C3A.F0 to R6C4D.D0 XOR8MEG18 -CTOF_DEL --- 0.371 R6C4D.D0 to R6C4D.F0 SLICE_82 -ROUTE 1 0.819 R6C4D.F0 to R6C4A.C0 CmdSubmitted_1_sqmuxa -CTOF_DEL --- 0.371 R6C4A.C0 to R6C4A.F0 SLICE_22 -ROUTE 1 0.000 R6C4A.F0 to R6C4A.DI0 N_460_0 (to PHI2_c) - -------- - 8.680 (27.8% logic, 72.2% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_77: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.919 39.PADDI to R6C3A.CLK PHI2_c - -------- - 3.919 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_22: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.919 39.PADDI to R6C4A.CLK PHI2_c - -------- - 3.919 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 163.688ns (weighted slack = 327.376ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank[2] (from PHI2_c +) Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 8.552ns (26.9% logic, 73.1% route), 5 logic levels. + Delay: 10.415ns (26.7% logic, 73.3% route), 7 logic levels. Constraint Details: - 8.552ns physical path delay SLICE_71 to SLICE_20 meets + 10.415ns physical path delay SLICE_75 to SLICE_20 meets 172.414ns delay constraint less 0.000ns skew and - 0.174ns DIN_SET requirement (totaling 172.240ns) by 163.688ns + 0.174ns DIN_SET requirement (totaling 172.240ns) by 161.825ns Physical Path Details: - Data path SLICE_71 to SLICE_20: + Data path SLICE_75 to SLICE_20: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R6C2C.CLK to R6C2C.Q0 SLICE_71 (from PHI2_c) -ROUTE 1 1.583 R6C2C.Q0 to R4C5A.A1 Bank[2] -CTOF_DEL --- 0.371 R4C5A.A1 to R4C5A.F1 SLICE_56 -ROUTE 1 1.643 R4C5A.F1 to R5C2C.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R5C2C.B1 to R5C2C.F1 SLICE_70 -ROUTE 6 1.578 R5C2C.F1 to R2C2B.B1 N_147 -CTOF_DEL --- 0.371 R2C2B.B1 to R2C2B.F1 SLICE_90 -ROUTE 1 1.444 R2C2B.F1 to R5C3D.C0 un1_CMDWR -CTOOFX_DEL --- 0.631 R5C3D.C0 to R5C3D.OFX0 SLICE_20 -ROUTE 1 0.000 R5C3D.OFX0 to R5C3D.DI0 CmdEnable_s (to PHI2_c) +REG_DEL --- 0.560 R5C3D.CLK to R5C3D.Q1 SLICE_75 (from PHI2_c) +ROUTE 1 2.039 R5C3D.Q1 to R5C2D.B1 Bank[7] +CTOF_DEL --- 0.371 R5C2D.B1 to R5C2D.F1 SLICE_77 +ROUTE 2 0.835 R5C2D.F1 to R5C2B.C0 un1_Bank_1_5 +CTOF_DEL --- 0.371 R5C2B.C0 to R5C2B.F0 SLICE_79 +ROUTE 2 1.092 R5C2B.F0 to R6C2C.B0 C1WR_7 +CTOF_DEL --- 0.371 R6C2C.B0 to R6C2C.F0 SLICE_76 +ROUTE 5 1.529 R6C2C.F0 to R5C3D.A0 C1WR +CTOF_DEL --- 0.371 R5C3D.A0 to R5C3D.F0 SLICE_75 +ROUTE 3 1.108 R5C3D.F0 to R6C3A.B1 CmdEnable16 +CTOF_DEL --- 0.371 R6C3A.B1 to R6C3A.F1 SLICE_14 +ROUTE 1 1.026 R6C3A.F1 to R5C3C.A0 un1_CmdEnable20_i +CTOF_DEL --- 0.371 R5C3C.A0 to R5C3C.F0 SLICE_20 +ROUTE 1 0.000 R5C3C.F0 to R5C3C.DI0 CmdEnable_s (to PHI2_c) -------- - 8.552 (26.9% logic, 73.1% route), 5 logic levels. + 10.415 (26.7% logic, 73.3% route), 7 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_71: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.919 39.PADDI to R6C2C.CLK PHI2_c - -------- - 3.919 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_20: + Source Clock Path PHI2 to SLICE_75: Name Fanout Delay (ns) Site Resource ROUTE 15 3.919 39.PADDI to R5C3D.CLK PHI2_c -------- 3.919 (0.0% logic, 100.0% route), 0 logic levels. + Destination Clock Path PHI2 to SLICE_20: -Passed: The following path meets requirements by 163.724ns (weighted slack = 327.448ns) + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.919 39.PADDI to R5C3C.CLK PHI2_c + -------- + 3.919 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.064ns (weighted slack = 324.128ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank[5] (from PHI2_c +) - Destination: FF Data in CmdEnable (to PHI2_c -) + Source: FF Q Bank[7] (from PHI2_c +) + Destination: FF Data in CmdSubmitted (to PHI2_c -) - Delay: 8.516ns (27.1% logic, 72.9% route), 5 logic levels. + Delay: 10.176ns (27.4% logic, 72.6% route), 7 logic levels. Constraint Details: - 8.516ns physical path delay SLICE_76 to SLICE_20 meets + 10.176ns physical path delay SLICE_75 to SLICE_22 meets 172.414ns delay constraint less 0.000ns skew and - 0.174ns DIN_SET requirement (totaling 172.240ns) by 163.724ns + 0.174ns DIN_SET requirement (totaling 172.240ns) by 162.064ns + + Physical Path Details: + + Data path SLICE_75 to SLICE_22: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R5C3D.CLK to R5C3D.Q1 SLICE_75 (from PHI2_c) +ROUTE 1 2.039 R5C3D.Q1 to R5C2D.B1 Bank[7] +CTOF_DEL --- 0.371 R5C2D.B1 to R5C2D.F1 SLICE_77 +ROUTE 2 0.835 R5C2D.F1 to R5C2B.C0 un1_Bank_1_5 +CTOF_DEL --- 0.371 R5C2B.C0 to R5C2B.F0 SLICE_79 +ROUTE 2 0.893 R5C2B.F0 to R6C2B.C1 C1WR_7 +CTOF_DEL --- 0.371 R6C2B.C1 to R6C2B.F1 SLICE_70 +ROUTE 2 1.563 R6C2B.F1 to R5C3B.B0 CMDWR +CTOF_DEL --- 0.371 R5C3B.B0 to R5C3B.F0 SLICE_73 +ROUTE 5 0.513 R5C3B.F0 to R5C3B.C1 XOR8MEG18 +CTOF_DEL --- 0.371 R5C3B.C1 to R5C3B.F1 SLICE_73 +ROUTE 1 1.547 R5C3B.F1 to R6C5C.B0 CmdSubmitted_1_sqmuxa +CTOF_DEL --- 0.371 R6C5C.B0 to R6C5C.F0 SLICE_22 +ROUTE 1 0.000 R6C5C.F0 to R6C5C.DI0 N_428_0 (to PHI2_c) + -------- + 10.176 (27.4% logic, 72.6% route), 7 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_75: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.919 39.PADDI to R5C3D.CLK PHI2_c + -------- + 3.919 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_22: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.919 39.PADDI to R6C5C.CLK PHI2_c + -------- + 3.919 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.564ns (weighted slack = 325.128ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank[7] (from PHI2_c +) + Destination: FF Data in CmdUFMCS (to PHI2_c -) + FF CmdUFMCLK + + Delay: 9.585ns (25.2% logic, 74.8% route), 6 logic levels. + + Constraint Details: + + 9.585ns physical path delay SLICE_75 to SLICE_85 meets + 172.414ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 172.149ns) by 162.564ns + + Physical Path Details: + + Data path SLICE_75 to SLICE_85: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R5C3D.CLK to R5C3D.Q1 SLICE_75 (from PHI2_c) +ROUTE 1 2.039 R5C3D.Q1 to R5C2D.B1 Bank[7] +CTOF_DEL --- 0.371 R5C2D.B1 to R5C2D.F1 SLICE_77 +ROUTE 2 0.835 R5C2D.F1 to R5C2B.C0 un1_Bank_1_5 +CTOF_DEL --- 0.371 R5C2B.C0 to R5C2B.F0 SLICE_79 +ROUTE 2 0.893 R5C2B.F0 to R6C2B.C1 C1WR_7 +CTOF_DEL --- 0.371 R6C2B.C1 to R6C2B.F1 SLICE_70 +ROUTE 2 1.563 R6C2B.F1 to R5C3B.B0 CMDWR +CTOF_DEL --- 0.371 R5C3B.B0 to R5C3B.F0 SLICE_73 +ROUTE 5 1.185 R5C3B.F0 to R6C4A.D1 XOR8MEG18 +CTOF_DEL --- 0.371 R6C4A.D1 to R6C4A.F1 SLICE_85 +ROUTE 2 0.655 R6C4A.F1 to R6C4A.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) + -------- + 9.585 (25.2% logic, 74.8% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_75: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.919 39.PADDI to R5C3D.CLK PHI2_c + -------- + 3.919 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_85: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.919 39.PADDI to R6C4A.CLK PHI2_c + -------- + 3.919 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.564ns (weighted slack = 325.128ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank[7] (from PHI2_c +) + Destination: FF Data in CmdUFMSDI (to PHI2_c -) + + Delay: 9.585ns (25.2% logic, 74.8% route), 6 logic levels. + + Constraint Details: + + 9.585ns physical path delay SLICE_75 to SLICE_88 meets + 172.414ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 172.149ns) by 162.564ns + + Physical Path Details: + + Data path SLICE_75 to SLICE_88: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R5C3D.CLK to R5C3D.Q1 SLICE_75 (from PHI2_c) +ROUTE 1 2.039 R5C3D.Q1 to R5C2D.B1 Bank[7] +CTOF_DEL --- 0.371 R5C2D.B1 to R5C2D.F1 SLICE_77 +ROUTE 2 0.835 R5C2D.F1 to R5C2B.C0 un1_Bank_1_5 +CTOF_DEL --- 0.371 R5C2B.C0 to R5C2B.F0 SLICE_79 +ROUTE 2 0.893 R5C2B.F0 to R6C2B.C1 C1WR_7 +CTOF_DEL --- 0.371 R6C2B.C1 to R6C2B.F1 SLICE_70 +ROUTE 2 1.563 R6C2B.F1 to R5C3B.B0 CMDWR +CTOF_DEL --- 0.371 R5C3B.B0 to R5C3B.F0 SLICE_73 +ROUTE 5 1.185 R5C3B.F0 to R6C4A.D1 XOR8MEG18 +CTOF_DEL --- 0.371 R6C4A.D1 to R6C4A.F1 SLICE_85 +ROUTE 2 0.655 R6C4A.F1 to R6C4B.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) + -------- + 9.585 (25.2% logic, 74.8% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_75: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.919 39.PADDI to R5C3D.CLK PHI2_c + -------- + 3.919 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_88: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.919 39.PADDI to R6C4B.CLK PHI2_c + -------- + 3.919 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.699ns (weighted slack = 325.398ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank[1] (from PHI2_c +) + Destination: FF Data in CmdEnable (to PHI2_c -) + + Delay: 9.541ns (29.2% logic, 70.8% route), 7 logic levels. + + Constraint Details: + + 9.541ns physical path delay SLICE_76 to SLICE_20 meets + 172.414ns delay constraint less + 0.000ns skew and + 0.174ns DIN_SET requirement (totaling 172.240ns) by 162.699ns Physical Path Details: Data path SLICE_76 to SLICE_20: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R6C3D.CLK to R6C3D.Q1 SLICE_76 (from PHI2_c) -ROUTE 1 1.547 R6C3D.Q1 to R4C5A.B1 Bank[5] -CTOF_DEL --- 0.371 R4C5A.B1 to R4C5A.F1 SLICE_56 -ROUTE 1 1.643 R4C5A.F1 to R5C2C.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R5C2C.B1 to R5C2C.F1 SLICE_70 -ROUTE 6 1.578 R5C2C.F1 to R2C2B.B1 N_147 -CTOF_DEL --- 0.371 R2C2B.B1 to R2C2B.F1 SLICE_90 -ROUTE 1 1.444 R2C2B.F1 to R5C3D.C0 un1_CMDWR -CTOOFX_DEL --- 0.631 R5C3D.C0 to R5C3D.OFX0 SLICE_20 -ROUTE 1 0.000 R5C3D.OFX0 to R5C3D.DI0 CmdEnable_s (to PHI2_c) +REG_DEL --- 0.560 R6C2C.CLK to R6C2C.Q1 SLICE_76 (from PHI2_c) +ROUTE 1 1.026 R6C2C.Q1 to R5C2A.A0 Bank[1] +CTOF_DEL --- 0.371 R5C2A.A0 to R5C2A.F0 SLICE_100 +ROUTE 2 0.974 R5C2A.F0 to R5C2B.A0 un1_Bank_1_4 +CTOF_DEL --- 0.371 R5C2B.A0 to R5C2B.F0 SLICE_79 +ROUTE 2 1.092 R5C2B.F0 to R6C2C.B0 C1WR_7 +CTOF_DEL --- 0.371 R6C2C.B0 to R6C2C.F0 SLICE_76 +ROUTE 5 1.529 R6C2C.F0 to R5C3D.A0 C1WR +CTOF_DEL --- 0.371 R5C3D.A0 to R5C3D.F0 SLICE_75 +ROUTE 3 1.108 R5C3D.F0 to R6C3A.B1 CmdEnable16 +CTOF_DEL --- 0.371 R6C3A.B1 to R6C3A.F1 SLICE_14 +ROUTE 1 1.026 R6C3A.F1 to R5C3C.A0 un1_CmdEnable20_i +CTOF_DEL --- 0.371 R5C3C.A0 to R5C3C.F0 SLICE_20 +ROUTE 1 0.000 R5C3C.F0 to R5C3C.DI0 CmdEnable_s (to PHI2_c) -------- - 8.516 (27.1% logic, 72.9% route), 5 logic levels. + 9.541 (29.2% logic, 70.8% route), 7 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_76: - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.919 39.PADDI to R6C3D.CLK PHI2_c - -------- - 3.919 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.919 39.PADDI to R5C3D.CLK PHI2_c - -------- - 3.919 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 163.725ns (weighted slack = 327.450ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank[6] (from PHI2_c +) - Destination: FF Data in CmdSubmitted (to PHI2_c -) - - Delay: 8.515ns (28.4% logic, 71.6% route), 6 logic levels. - - Constraint Details: - - 8.515ns physical path delay SLICE_77 to SLICE_22 meets - 172.414ns delay constraint less - 0.000ns skew and - 0.174ns DIN_SET requirement (totaling 172.240ns) by 163.725ns - - Physical Path Details: - - Data path SLICE_77 to SLICE_22: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R6C3A.CLK to R6C3A.Q0 SLICE_77 (from PHI2_c) -ROUTE 1 1.348 R6C3A.Q0 to R4C5A.C1 Bank[6] -CTOF_DEL --- 0.371 R4C5A.C1 to R4C5A.F1 SLICE_56 -ROUTE 1 1.643 R4C5A.F1 to R5C2C.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R5C2C.B1 to R5C2C.F1 SLICE_70 -ROUTE 6 1.075 R5C2C.F1 to R5C3A.A0 N_147 -CTOF_DEL --- 0.371 R5C3A.A0 to R5C3A.F0 SLICE_67 -ROUTE 5 1.215 R5C3A.F0 to R6C4D.D0 XOR8MEG18 -CTOF_DEL --- 0.371 R6C4D.D0 to R6C4D.F0 SLICE_82 -ROUTE 1 0.819 R6C4D.F0 to R6C4A.C0 CmdSubmitted_1_sqmuxa -CTOF_DEL --- 0.371 R6C4A.C0 to R6C4A.F0 SLICE_22 -ROUTE 1 0.000 R6C4A.F0 to R6C4A.DI0 N_460_0 (to PHI2_c) - -------- - 8.515 (28.4% logic, 71.6% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_77: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.919 39.PADDI to R6C3A.CLK PHI2_c - -------- - 3.919 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_22: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.919 39.PADDI to R6C4A.CLK PHI2_c - -------- - 3.919 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 163.758ns (weighted slack = 327.516ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank[7] (from PHI2_c +) - Destination: FF Data in CmdEnable (to PHI2_c -) - - Delay: 8.482ns (27.2% logic, 72.8% route), 5 logic levels. - - Constraint Details: - - 8.482ns physical path delay SLICE_77 to SLICE_20 meets - 172.414ns delay constraint less - 0.000ns skew and - 0.174ns DIN_SET requirement (totaling 172.240ns) by 163.758ns - - Physical Path Details: - - Data path SLICE_77 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R6C3A.CLK to R6C3A.Q1 SLICE_77 (from PHI2_c) -ROUTE 1 1.513 R6C3A.Q1 to R4C5A.D1 Bank[7] -CTOF_DEL --- 0.371 R4C5A.D1 to R4C5A.F1 SLICE_56 -ROUTE 1 1.643 R4C5A.F1 to R5C2C.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R5C2C.B1 to R5C2C.F1 SLICE_70 -ROUTE 6 1.578 R5C2C.F1 to R2C2B.B1 N_147 -CTOF_DEL --- 0.371 R2C2B.B1 to R2C2B.F1 SLICE_90 -ROUTE 1 1.444 R2C2B.F1 to R5C3D.C0 un1_CMDWR -CTOOFX_DEL --- 0.631 R5C3D.C0 to R5C3D.OFX0 SLICE_20 -ROUTE 1 0.000 R5C3D.OFX0 to R5C3D.DI0 CmdEnable_s (to PHI2_c) - -------- - 8.482 (27.2% logic, 72.8% route), 5 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_77: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.919 39.PADDI to R6C3A.CLK PHI2_c - -------- - 3.919 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.919 39.PADDI to R5C3D.CLK PHI2_c - -------- - 3.919 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 163.923ns (weighted slack = 327.846ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank[6] (from PHI2_c +) - Destination: FF Data in CmdEnable (to PHI2_c -) - - Delay: 8.317ns (27.7% logic, 72.3% route), 5 logic levels. - - Constraint Details: - - 8.317ns physical path delay SLICE_77 to SLICE_20 meets - 172.414ns delay constraint less - 0.000ns skew and - 0.174ns DIN_SET requirement (totaling 172.240ns) by 163.923ns - - Physical Path Details: - - Data path SLICE_77 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R6C3A.CLK to R6C3A.Q0 SLICE_77 (from PHI2_c) -ROUTE 1 1.348 R6C3A.Q0 to R4C5A.C1 Bank[6] -CTOF_DEL --- 0.371 R4C5A.C1 to R4C5A.F1 SLICE_56 -ROUTE 1 1.643 R4C5A.F1 to R5C2C.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R5C2C.B1 to R5C2C.F1 SLICE_70 -ROUTE 6 1.578 R5C2C.F1 to R2C2B.B1 N_147 -CTOF_DEL --- 0.371 R2C2B.B1 to R2C2B.F1 SLICE_90 -ROUTE 1 1.444 R2C2B.F1 to R5C3D.C0 un1_CMDWR -CTOOFX_DEL --- 0.631 R5C3D.C0 to R5C3D.OFX0 SLICE_20 -ROUTE 1 0.000 R5C3D.OFX0 to R5C3D.DI0 CmdEnable_s (to PHI2_c) - -------- - 8.317 (27.7% logic, 72.3% route), 5 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_77: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.919 39.PADDI to R6C3A.CLK PHI2_c - -------- - 3.919 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.919 39.PADDI to R5C3D.CLK PHI2_c - -------- - 3.919 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 163.952ns (weighted slack = 327.904ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank[2] (from PHI2_c +) - Destination: FF Data in CmdUFMSDI (to PHI2_c -) - - Delay: 8.197ns (24.9% logic, 75.1% route), 5 logic levels. - - Constraint Details: - - 8.197ns physical path delay SLICE_71 to SLICE_74 meets - 172.414ns delay constraint less - 0.000ns skew and - 0.265ns CE_SET requirement (totaling 172.149ns) by 163.952ns - - Physical Path Details: - - Data path SLICE_71 to SLICE_74: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R6C2C.CLK to R6C2C.Q0 SLICE_71 (from PHI2_c) -ROUTE 1 1.583 R6C2C.Q0 to R4C5A.A1 Bank[2] -CTOF_DEL --- 0.371 R4C5A.A1 to R4C5A.F1 SLICE_56 -ROUTE 1 1.643 R4C5A.F1 to R5C2C.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R5C2C.B1 to R5C2C.F1 SLICE_70 -ROUTE 6 1.075 R5C2C.F1 to R5C3A.A0 N_147 -CTOF_DEL --- 0.371 R5C3A.A0 to R5C3A.F0 SLICE_67 -ROUTE 5 0.682 R5C3A.F0 to R5C3A.A1 XOR8MEG18 -CTOF_DEL --- 0.371 R5C3A.A1 to R5C3A.F1 SLICE_67 -ROUTE 2 1.170 R5C3A.F1 to R7C4B.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) - -------- - 8.197 (24.9% logic, 75.1% route), 5 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_71: - Name Fanout Delay (ns) Site Resource ROUTE 15 3.919 39.PADDI to R6C2C.CLK PHI2_c -------- 3.919 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_74: + Destination Clock Path PHI2 to SLICE_20: Name Fanout Delay (ns) Site Resource -ROUTE 15 3.919 39.PADDI to R7C4B.CLK PHI2_c +ROUTE 15 3.919 39.PADDI to R5C3C.CLK PHI2_c -------- 3.919 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 163.988ns (weighted slack = 327.976ns) +Passed: The following path meets requirements by 162.707ns (weighted slack = 325.414ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank[5] (from PHI2_c +) - Destination: FF Data in CmdUFMSDI (to PHI2_c -) + Source: FF Q Bank[3] (from PHI2_c +) + Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 8.161ns (25.0% logic, 75.0% route), 5 logic levels. + Delay: 9.533ns (29.2% logic, 70.8% route), 7 logic levels. Constraint Details: - 8.161ns physical path delay SLICE_76 to SLICE_74 meets + 9.533ns physical path delay SLICE_79 to SLICE_20 meets 172.414ns delay constraint less 0.000ns skew and - 0.265ns CE_SET requirement (totaling 172.149ns) by 163.988ns + 0.174ns DIN_SET requirement (totaling 172.240ns) by 162.707ns Physical Path Details: - Data path SLICE_76 to SLICE_74: + Data path SLICE_79 to SLICE_20: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R6C3D.CLK to R6C3D.Q1 SLICE_76 (from PHI2_c) -ROUTE 1 1.547 R6C3D.Q1 to R4C5A.B1 Bank[5] -CTOF_DEL --- 0.371 R4C5A.B1 to R4C5A.F1 SLICE_56 -ROUTE 1 1.643 R4C5A.F1 to R5C2C.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R5C2C.B1 to R5C2C.F1 SLICE_70 -ROUTE 6 1.075 R5C2C.F1 to R5C3A.A0 N_147 -CTOF_DEL --- 0.371 R5C3A.A0 to R5C3A.F0 SLICE_67 -ROUTE 5 0.682 R5C3A.F0 to R5C3A.A1 XOR8MEG18 -CTOF_DEL --- 0.371 R5C3A.A1 to R5C3A.F1 SLICE_67 -ROUTE 2 1.170 R5C3A.F1 to R7C4B.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) +REG_DEL --- 0.560 R5C2B.CLK to R5C2B.Q1 SLICE_79 (from PHI2_c) +ROUTE 1 1.018 R5C2B.Q1 to R5C2A.B0 Bank[3] +CTOF_DEL --- 0.371 R5C2A.B0 to R5C2A.F0 SLICE_100 +ROUTE 2 0.974 R5C2A.F0 to R5C2B.A0 un1_Bank_1_4 +CTOF_DEL --- 0.371 R5C2B.A0 to R5C2B.F0 SLICE_79 +ROUTE 2 1.092 R5C2B.F0 to R6C2C.B0 C1WR_7 +CTOF_DEL --- 0.371 R6C2C.B0 to R6C2C.F0 SLICE_76 +ROUTE 5 1.529 R6C2C.F0 to R5C3D.A0 C1WR +CTOF_DEL --- 0.371 R5C3D.A0 to R5C3D.F0 SLICE_75 +ROUTE 3 1.108 R5C3D.F0 to R6C3A.B1 CmdEnable16 +CTOF_DEL --- 0.371 R6C3A.B1 to R6C3A.F1 SLICE_14 +ROUTE 1 1.026 R6C3A.F1 to R5C3C.A0 un1_CmdEnable20_i +CTOF_DEL --- 0.371 R5C3C.A0 to R5C3C.F0 SLICE_20 +ROUTE 1 0.000 R5C3C.F0 to R5C3C.DI0 CmdEnable_s (to PHI2_c) -------- - 8.161 (25.0% logic, 75.0% route), 5 logic levels. + 9.533 (29.2% logic, 70.8% route), 7 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_79: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.919 39.PADDI to R5C2B.CLK PHI2_c + -------- + 3.919 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.919 39.PADDI to R5C3C.CLK PHI2_c + -------- + 3.919 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.832ns (weighted slack = 325.664ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank[6] (from PHI2_c +) + Destination: FF Data in CmdEnable (to PHI2_c -) + + Delay: 9.408ns (29.6% logic, 70.4% route), 7 logic levels. + + Constraint Details: + + 9.408ns physical path delay SLICE_75 to SLICE_20 meets + 172.414ns delay constraint less + 0.000ns skew and + 0.174ns DIN_SET requirement (totaling 172.240ns) by 162.832ns + + Physical Path Details: + + Data path SLICE_75 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R5C3D.CLK to R5C3D.Q0 SLICE_75 (from PHI2_c) +ROUTE 1 1.032 R5C3D.Q0 to R5C2D.A1 Bank[6] +CTOF_DEL --- 0.371 R5C2D.A1 to R5C2D.F1 SLICE_77 +ROUTE 2 0.835 R5C2D.F1 to R5C2B.C0 un1_Bank_1_5 +CTOF_DEL --- 0.371 R5C2B.C0 to R5C2B.F0 SLICE_79 +ROUTE 2 1.092 R5C2B.F0 to R6C2C.B0 C1WR_7 +CTOF_DEL --- 0.371 R6C2C.B0 to R6C2C.F0 SLICE_76 +ROUTE 5 1.529 R6C2C.F0 to R5C3D.A0 C1WR +CTOF_DEL --- 0.371 R5C3D.A0 to R5C3D.F0 SLICE_75 +ROUTE 3 1.108 R5C3D.F0 to R6C3A.B1 CmdEnable16 +CTOF_DEL --- 0.371 R6C3A.B1 to R6C3A.F1 SLICE_14 +ROUTE 1 1.026 R6C3A.F1 to R5C3C.A0 un1_CmdEnable20_i +CTOF_DEL --- 0.371 R5C3C.A0 to R5C3C.F0 SLICE_20 +ROUTE 1 0.000 R5C3C.F0 to R5C3C.DI0 CmdEnable_s (to PHI2_c) + -------- + 9.408 (29.6% logic, 70.4% route), 7 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_75: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.919 39.PADDI to R5C3D.CLK PHI2_c + -------- + 3.919 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.919 39.PADDI to R5C3C.CLK PHI2_c + -------- + 3.919 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.838ns (weighted slack = 325.676ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank[4] (from PHI2_c +) + Destination: FF Data in CmdEnable (to PHI2_c -) + + Delay: 9.402ns (29.6% logic, 70.4% route), 7 logic levels. + + Constraint Details: + + 9.402ns physical path delay SLICE_93 to SLICE_20 meets + 172.414ns delay constraint less + 0.000ns skew and + 0.174ns DIN_SET requirement (totaling 172.240ns) by 162.838ns + + Physical Path Details: + + Data path SLICE_93 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R6C2A.CLK to R6C2A.Q0 SLICE_93 (from PHI2_c) +ROUTE 1 0.887 R6C2A.Q0 to R5C2A.C0 Bank[4] +CTOF_DEL --- 0.371 R5C2A.C0 to R5C2A.F0 SLICE_100 +ROUTE 2 0.974 R5C2A.F0 to R5C2B.A0 un1_Bank_1_4 +CTOF_DEL --- 0.371 R5C2B.A0 to R5C2B.F0 SLICE_79 +ROUTE 2 1.092 R5C2B.F0 to R6C2C.B0 C1WR_7 +CTOF_DEL --- 0.371 R6C2C.B0 to R6C2C.F0 SLICE_76 +ROUTE 5 1.529 R6C2C.F0 to R5C3D.A0 C1WR +CTOF_DEL --- 0.371 R5C3D.A0 to R5C3D.F0 SLICE_75 +ROUTE 3 1.108 R5C3D.F0 to R6C3A.B1 CmdEnable16 +CTOF_DEL --- 0.371 R6C3A.B1 to R6C3A.F1 SLICE_14 +ROUTE 1 1.026 R6C3A.F1 to R5C3C.A0 un1_CmdEnable20_i +CTOF_DEL --- 0.371 R5C3C.A0 to R5C3C.F0 SLICE_20 +ROUTE 1 0.000 R5C3C.F0 to R5C3C.DI0 CmdEnable_s (to PHI2_c) + -------- + 9.402 (29.6% logic, 70.4% route), 7 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.919 39.PADDI to R6C2A.CLK PHI2_c + -------- + 3.919 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.919 39.PADDI to R5C3C.CLK PHI2_c + -------- + 3.919 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.938ns (weighted slack = 325.876ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank[1] (from PHI2_c +) + Destination: FF Data in CmdSubmitted (to PHI2_c -) + + Delay: 9.302ns (30.0% logic, 70.0% route), 7 logic levels. + + Constraint Details: + + 9.302ns physical path delay SLICE_76 to SLICE_22 meets + 172.414ns delay constraint less + 0.000ns skew and + 0.174ns DIN_SET requirement (totaling 172.240ns) by 162.938ns + + Physical Path Details: + + Data path SLICE_76 to SLICE_22: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R6C2C.CLK to R6C2C.Q1 SLICE_76 (from PHI2_c) +ROUTE 1 1.026 R6C2C.Q1 to R5C2A.A0 Bank[1] +CTOF_DEL --- 0.371 R5C2A.A0 to R5C2A.F0 SLICE_100 +ROUTE 2 0.974 R5C2A.F0 to R5C2B.A0 un1_Bank_1_4 +CTOF_DEL --- 0.371 R5C2B.A0 to R5C2B.F0 SLICE_79 +ROUTE 2 0.893 R5C2B.F0 to R6C2B.C1 C1WR_7 +CTOF_DEL --- 0.371 R6C2B.C1 to R6C2B.F1 SLICE_70 +ROUTE 2 1.563 R6C2B.F1 to R5C3B.B0 CMDWR +CTOF_DEL --- 0.371 R5C3B.B0 to R5C3B.F0 SLICE_73 +ROUTE 5 0.513 R5C3B.F0 to R5C3B.C1 XOR8MEG18 +CTOF_DEL --- 0.371 R5C3B.C1 to R5C3B.F1 SLICE_73 +ROUTE 1 1.547 R5C3B.F1 to R6C5C.B0 CmdSubmitted_1_sqmuxa +CTOF_DEL --- 0.371 R6C5C.B0 to R6C5C.F0 SLICE_22 +ROUTE 1 0.000 R6C5C.F0 to R6C5C.DI0 N_428_0 (to PHI2_c) + -------- + 9.302 (30.0% logic, 70.0% route), 7 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_76: Name Fanout Delay (ns) Site Resource -ROUTE 15 3.919 39.PADDI to R6C3D.CLK PHI2_c +ROUTE 15 3.919 39.PADDI to R6C2C.CLK PHI2_c -------- 3.919 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_74: + Destination Clock Path PHI2 to SLICE_22: Name Fanout Delay (ns) Site Resource -ROUTE 15 3.919 39.PADDI to R7C4B.CLK PHI2_c +ROUTE 15 3.919 39.PADDI to R6C5C.CLK PHI2_c -------- 3.919 (0.0% logic, 100.0% route), 0 logic levels. -Report: 56.029MHz is the maximum frequency for this preference. + +Passed: The following path meets requirements by 162.946ns (weighted slack = 325.892ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank[3] (from PHI2_c +) + Destination: FF Data in CmdSubmitted (to PHI2_c -) + + Delay: 9.294ns (30.0% logic, 70.0% route), 7 logic levels. + + Constraint Details: + + 9.294ns physical path delay SLICE_79 to SLICE_22 meets + 172.414ns delay constraint less + 0.000ns skew and + 0.174ns DIN_SET requirement (totaling 172.240ns) by 162.946ns + + Physical Path Details: + + Data path SLICE_79 to SLICE_22: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R5C2B.CLK to R5C2B.Q1 SLICE_79 (from PHI2_c) +ROUTE 1 1.018 R5C2B.Q1 to R5C2A.B0 Bank[3] +CTOF_DEL --- 0.371 R5C2A.B0 to R5C2A.F0 SLICE_100 +ROUTE 2 0.974 R5C2A.F0 to R5C2B.A0 un1_Bank_1_4 +CTOF_DEL --- 0.371 R5C2B.A0 to R5C2B.F0 SLICE_79 +ROUTE 2 0.893 R5C2B.F0 to R6C2B.C1 C1WR_7 +CTOF_DEL --- 0.371 R6C2B.C1 to R6C2B.F1 SLICE_70 +ROUTE 2 1.563 R6C2B.F1 to R5C3B.B0 CMDWR +CTOF_DEL --- 0.371 R5C3B.B0 to R5C3B.F0 SLICE_73 +ROUTE 5 0.513 R5C3B.F0 to R5C3B.C1 XOR8MEG18 +CTOF_DEL --- 0.371 R5C3B.C1 to R5C3B.F1 SLICE_73 +ROUTE 1 1.547 R5C3B.F1 to R6C5C.B0 CmdSubmitted_1_sqmuxa +CTOF_DEL --- 0.371 R6C5C.B0 to R6C5C.F0 SLICE_22 +ROUTE 1 0.000 R6C5C.F0 to R6C5C.DI0 N_428_0 (to PHI2_c) + -------- + 9.294 (30.0% logic, 70.0% route), 7 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_79: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.919 39.PADDI to R5C2B.CLK PHI2_c + -------- + 3.919 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_22: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.919 39.PADDI to R6C5C.CLK PHI2_c + -------- + 3.919 (0.0% logic, 100.0% route), 0 logic levels. + +Report: 47.219MHz is the maximum frequency for this preference. ================================================================================ @@ -623,45 +652,149 @@ Report: 400.000MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; - 388 items scored, 0 timing errors detected. + 392 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- -Passed: The following path meets requirements by 8.213ns +Passed: The following path meets requirements by 6.770ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[12] (from RCLK_c +) + Destination: FF Data in UFMSDI (to RCLK_c +) + + Delay: 9.049ns (26.7% logic, 73.3% route), 6 logic levels. + + Constraint Details: + + 9.049ns physical path delay SLICE_3 to SLICE_52 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.181ns DIN_SET requirement (totaling 15.819ns) by 6.770ns + + Physical Path Details: + + Data path SLICE_3 to SLICE_52: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R8C3C.CLK to R8C3C.Q0 SLICE_3 (from RCLK_c) +ROUTE 3 1.870 R8C3C.Q0 to R8C4B.C1 FS[12] +CTOF_DEL --- 0.371 R8C4B.C1 to R8C4B.F1 SLICE_86 +ROUTE 1 0.694 R8C4B.F1 to R7C4A.D1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.371 R7C4A.D1 to R7C4A.F1 SLICE_69 +ROUTE 4 1.192 R7C4A.F1 to R6C5D.D1 N_128 +CTOF_DEL --- 0.371 R6C5D.D1 to R6C5D.F1 SLICE_58 +ROUTE 3 1.723 R6C5D.F1 to R3C5A.C0 N_94 +CTOF_DEL --- 0.371 R3C5A.C0 to R3C5A.F0 SLICE_55 +ROUTE 1 1.155 R3C5A.F0 to R7C5B.D0 UFMSDI_r_xx_mm_1 +CTOF_DEL --- 0.371 R7C5B.D0 to R7C5B.F0 SLICE_52 +ROUTE 1 0.000 R7C5B.F0 to R7C5B.DI0 UFMSDI_RNO (to RCLK_c) + -------- + 9.049 (26.7% logic, 73.3% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 1.353 86.PADDI to R8C3C.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_52: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 1.353 86.PADDI to R7C5B.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 7.278ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[10] (from RCLK_c +) + Destination: FF Data in UFMSDI (to RCLK_c +) + + Delay: 8.541ns (23.9% logic, 76.1% route), 5 logic levels. + + Constraint Details: + + 8.541ns physical path delay SLICE_4 to SLICE_52 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.181ns DIN_SET requirement (totaling 15.819ns) by 7.278ns + + Physical Path Details: + + Data path SLICE_4 to SLICE_52: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R8C3B.CLK to R8C3B.Q0 SLICE_4 (from RCLK_c) +ROUTE 5 1.886 R8C3B.Q0 to R7C3C.C1 FS[10] +CTOF_DEL --- 0.371 R7C3C.C1 to R7C3C.F1 SLICE_94 +ROUTE 1 1.840 R7C3C.F1 to R7C4B.C1 UFMSDI_ens2_i_a2_4_2 +CTOF_DEL --- 0.371 R7C4B.C1 to R7C4B.F1 SLICE_32 +ROUTE 1 1.616 R7C4B.F1 to R3C5A.D0 UFMSDI_ens2_i_a0 +CTOF_DEL --- 0.371 R3C5A.D0 to R3C5A.F0 SLICE_55 +ROUTE 1 1.155 R3C5A.F0 to R7C5B.D0 UFMSDI_r_xx_mm_1 +CTOF_DEL --- 0.371 R7C5B.D0 to R7C5B.F0 SLICE_52 +ROUTE 1 0.000 R7C5B.F0 to R7C5B.DI0 UFMSDI_RNO (to RCLK_c) + -------- + 8.541 (23.9% logic, 76.1% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_4: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 1.353 86.PADDI to R8C3B.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_52: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 1.353 86.PADDI to R7C5B.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 7.584ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[15] (from RCLK_c +) - Destination: FF Data in LEDEN (to RCLK_c +) + Destination: FF Data in UFMSDI (to RCLK_c +) - Delay: 7.543ns (32.0% logic, 68.0% route), 6 logic levels. + Delay: 8.235ns (29.3% logic, 70.7% route), 6 logic levels. Constraint Details: - 7.543ns physical path delay SLICE_2 to SLICE_33 meets + 8.235ns physical path delay SLICE_2 to SLICE_52 meets 16.000ns delay constraint less 0.000ns skew and - 0.244ns CE_SET requirement (totaling 15.756ns) by 8.213ns + 0.181ns DIN_SET requirement (totaling 15.819ns) by 7.584ns Physical Path Details: - Data path SLICE_2 to SLICE_33: + Data path SLICE_2 to SLICE_52: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.560 R8C3D.CLK to R8C3D.Q1 SLICE_2 (from RCLK_c) -ROUTE 3 1.571 R8C3D.Q1 to R7C4A.B1 FS[15] -CTOF_DEL --- 0.371 R7C4A.B1 to R7C4A.F1 SLICE_81 -ROUTE 1 0.700 R7C4A.F1 to R7C3B.D1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 R7C3B.D1 to R7C3B.F1 SLICE_72 -ROUTE 4 0.350 R7C3B.F1 to R7C3C.D1 N_51 -CTOF_DEL --- 0.371 R7C3C.D1 to R7C3C.F1 SLICE_58 -ROUTE 2 0.642 R7C3C.F1 to R7C3D.D0 N_151 -CTOF_DEL --- 0.371 R7C3D.D0 to R7C3D.F0 SLICE_87 -ROUTE 2 0.700 R7C3D.F0 to R7C2D.D0 N_137_8 -CTOF_DEL --- 0.371 R7C2D.D0 to R7C2D.F0 SLICE_69 -ROUTE 1 1.165 R7C2D.F0 to R7C5A.CE N_33 (to RCLK_c) +ROUTE 3 1.056 R8C3D.Q1 to R8C4B.A1 FS[15] +CTOF_DEL --- 0.371 R8C4B.A1 to R8C4B.F1 SLICE_86 +ROUTE 1 0.694 R8C4B.F1 to R7C4A.D1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.371 R7C4A.D1 to R7C4A.F1 SLICE_69 +ROUTE 4 1.192 R7C4A.F1 to R6C5D.D1 N_128 +CTOF_DEL --- 0.371 R6C5D.D1 to R6C5D.F1 SLICE_58 +ROUTE 3 1.723 R6C5D.F1 to R3C5A.C0 N_94 +CTOF_DEL --- 0.371 R3C5A.C0 to R3C5A.F0 SLICE_55 +ROUTE 1 1.155 R3C5A.F0 to R7C5B.D0 UFMSDI_r_xx_mm_1 +CTOF_DEL --- 0.371 R7C5B.D0 to R7C5B.F0 SLICE_52 +ROUTE 1 0.000 R7C5B.F0 to R7C5B.DI0 UFMSDI_RNO (to RCLK_c) -------- - 7.543 (32.0% logic, 68.0% route), 6 logic levels. + 8.235 (29.3% logic, 70.7% route), 6 logic levels. Clock Skew Details: @@ -672,102 +805,49 @@ ROUTE 32 1.353 86.PADDI to R8C3D.CLK RCLK_c -------- 1.353 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_33: + Destination Clock Path RCLK to SLICE_52: Name Fanout Delay (ns) Site Resource -ROUTE 32 1.353 86.PADDI to R7C5A.CLK RCLK_c +ROUTE 32 1.353 86.PADDI to R7C5B.CLK RCLK_c -------- 1.353 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 8.305ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[15] (from RCLK_c +) - Destination: FF Data in n8MEGEN (to RCLK_c +) - - Delay: 7.451ns (32.4% logic, 67.6% route), 6 logic levels. - - Constraint Details: - - 7.451ns physical path delay SLICE_2 to SLICE_58 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.244ns CE_SET requirement (totaling 15.756ns) by 8.305ns - - Physical Path Details: - - Data path SLICE_2 to SLICE_58: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C3D.CLK to R8C3D.Q1 SLICE_2 (from RCLK_c) -ROUTE 3 1.571 R8C3D.Q1 to R7C4A.B1 FS[15] -CTOF_DEL --- 0.371 R7C4A.B1 to R7C4A.F1 SLICE_81 -ROUTE 1 0.700 R7C4A.F1 to R7C3B.D1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 R7C3B.D1 to R7C3B.F1 SLICE_72 -ROUTE 4 0.350 R7C3B.F1 to R7C3C.D1 N_51 -CTOF_DEL --- 0.371 R7C3C.D1 to R7C3C.F1 SLICE_58 -ROUTE 2 0.642 R7C3C.F1 to R7C3D.D0 N_151 -CTOF_DEL --- 0.371 R7C3D.D0 to R7C3D.F0 SLICE_87 -ROUTE 2 0.700 R7C3D.F0 to R7C2B.D0 N_137_8 -CTOF_DEL --- 0.371 R7C2B.D0 to R7C2B.F0 SLICE_68 -ROUTE 1 1.073 R7C2B.F0 to R7C3C.CE N_31 (to RCLK_c) - -------- - 7.451 (32.4% logic, 67.6% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_2: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 1.353 86.PADDI to R8C3D.CLK RCLK_c - -------- - 1.353 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_58: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 1.353 86.PADDI to R7C3C.CLK RCLK_c - -------- - 1.353 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 8.378ns +Passed: The following path meets requirements by 7.591ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[17] (from RCLK_c +) - Destination: FF Data in LEDEN (to RCLK_c +) + Destination: FF Data in UFMSDI (to RCLK_c +) - Delay: 7.378ns (32.7% logic, 67.3% route), 6 logic levels. + Delay: 8.228ns (29.4% logic, 70.6% route), 6 logic levels. Constraint Details: - 7.378ns physical path delay SLICE_1 to SLICE_33 meets + 8.228ns physical path delay SLICE_1 to SLICE_52 meets 16.000ns delay constraint less 0.000ns skew and - 0.244ns CE_SET requirement (totaling 15.756ns) by 8.378ns + 0.181ns DIN_SET requirement (totaling 15.819ns) by 7.591ns Physical Path Details: - Data path SLICE_1 to SLICE_33: + Data path SLICE_1 to SLICE_52: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.560 R8C4A.CLK to R8C4A.Q1 SLICE_1 (from RCLK_c) -ROUTE 3 1.406 R8C4A.Q1 to R7C4A.A1 FS[17] -CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_81 -ROUTE 1 0.700 R7C4A.F1 to R7C3B.D1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 R7C3B.D1 to R7C3B.F1 SLICE_72 -ROUTE 4 0.350 R7C3B.F1 to R7C3C.D1 N_51 -CTOF_DEL --- 0.371 R7C3C.D1 to R7C3C.F1 SLICE_58 -ROUTE 2 0.642 R7C3C.F1 to R7C3D.D0 N_151 -CTOF_DEL --- 0.371 R7C3D.D0 to R7C3D.F0 SLICE_87 -ROUTE 2 0.700 R7C3D.F0 to R7C2D.D0 N_137_8 -CTOF_DEL --- 0.371 R7C2D.D0 to R7C2D.F0 SLICE_69 -ROUTE 1 1.165 R7C2D.F0 to R7C5A.CE N_33 (to RCLK_c) +ROUTE 3 1.049 R8C4A.Q1 to R8C4B.B1 FS[17] +CTOF_DEL --- 0.371 R8C4B.B1 to R8C4B.F1 SLICE_86 +ROUTE 1 0.694 R8C4B.F1 to R7C4A.D1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.371 R7C4A.D1 to R7C4A.F1 SLICE_69 +ROUTE 4 1.192 R7C4A.F1 to R6C5D.D1 N_128 +CTOF_DEL --- 0.371 R6C5D.D1 to R6C5D.F1 SLICE_58 +ROUTE 3 1.723 R6C5D.F1 to R3C5A.C0 N_94 +CTOF_DEL --- 0.371 R3C5A.C0 to R3C5A.F0 SLICE_55 +ROUTE 1 1.155 R3C5A.F0 to R7C5B.D0 UFMSDI_r_xx_mm_1 +CTOF_DEL --- 0.371 R7C5B.D0 to R7C5B.F0 SLICE_52 +ROUTE 1 0.000 R7C5B.F0 to R7C5B.DI0 UFMSDI_RNO (to RCLK_c) -------- - 7.378 (32.7% logic, 67.3% route), 6 logic levels. + 8.228 (29.4% logic, 70.6% route), 6 logic levels. Clock Skew Details: @@ -778,49 +858,153 @@ ROUTE 32 1.353 86.PADDI to R8C4A.CLK RCLK_c -------- 1.353 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_33: + Destination Clock Path RCLK to SLICE_52: Name Fanout Delay (ns) Site Resource -ROUTE 32 1.353 86.PADDI to R7C5A.CLK RCLK_c +ROUTE 32 1.353 86.PADDI to R7C5B.CLK RCLK_c -------- 1.353 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 8.404ns +Passed: The following path meets requirements by 7.610ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[12] (from RCLK_c +) + Destination: FF Data in n8MEGEN (to RCLK_c +) + + Delay: 8.146ns (25.1% logic, 74.9% route), 5 logic levels. + + Constraint Details: + + 8.146ns physical path delay SLICE_3 to SLICE_58 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.244ns CE_SET requirement (totaling 15.756ns) by 7.610ns + + Physical Path Details: + + Data path SLICE_3 to SLICE_58: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R8C3C.CLK to R8C3C.Q0 SLICE_3 (from RCLK_c) +ROUTE 3 1.870 R8C3C.Q0 to R8C4B.C1 FS[12] +CTOF_DEL --- 0.371 R8C4B.C1 to R8C4B.F1 SLICE_86 +ROUTE 1 0.694 R8C4B.F1 to R7C4A.D1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.371 R7C4A.D1 to R7C4A.F1 SLICE_69 +ROUTE 4 1.192 R7C4A.F1 to R6C5D.D1 N_128 +CTOF_DEL --- 0.371 R6C5D.D1 to R6C5D.F1 SLICE_58 +ROUTE 3 0.716 R6C5D.F1 to R7C5C.D0 N_94 +CTOF_DEL --- 0.371 R7C5C.D0 to R7C5C.F0 SLICE_71 +ROUTE 1 1.630 R7C5C.F0 to R6C5D.CE N_24 (to RCLK_c) + -------- + 8.146 (25.1% logic, 74.9% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 1.353 86.PADDI to R8C3C.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_58: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 1.353 86.PADDI to R6C5D.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 7.734ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[12] (from RCLK_c +) + Destination: FF Data in UFMSDI (to RCLK_c +) + + Delay: 8.085ns (29.9% logic, 70.1% route), 6 logic levels. + + Constraint Details: + + 8.085ns physical path delay SLICE_3 to SLICE_52 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.181ns DIN_SET requirement (totaling 15.819ns) by 7.734ns + + Physical Path Details: + + Data path SLICE_3 to SLICE_52: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R8C3C.CLK to R8C3C.Q0 SLICE_3 (from RCLK_c) +ROUTE 3 1.870 R8C3C.Q0 to R8C4B.C1 FS[12] +CTOF_DEL --- 0.371 R8C4B.C1 to R8C4B.F1 SLICE_86 +ROUTE 1 0.694 R8C4B.F1 to R7C4A.D1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.371 R7C4A.D1 to R7C4A.F1 SLICE_69 +ROUTE 4 0.335 R7C4A.F1 to R7C4B.D1 N_128 +CTOF_DEL --- 0.371 R7C4B.D1 to R7C4B.F1 SLICE_32 +ROUTE 1 1.616 R7C4B.F1 to R3C5A.D0 UFMSDI_ens2_i_a0 +CTOF_DEL --- 0.371 R3C5A.D0 to R3C5A.F0 SLICE_55 +ROUTE 1 1.155 R3C5A.F0 to R7C5B.D0 UFMSDI_r_xx_mm_1 +CTOF_DEL --- 0.371 R7C5B.D0 to R7C5B.F0 SLICE_52 +ROUTE 1 0.000 R7C5B.F0 to R7C5B.DI0 UFMSDI_RNO (to RCLK_c) + -------- + 8.085 (29.9% logic, 70.1% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 1.353 86.PADDI to R8C3C.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_52: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 1.353 86.PADDI to R7C5B.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 7.924ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[14] (from RCLK_c +) - Destination: FF Data in LEDEN (to RCLK_c +) + Destination: FF Data in UFMSDI (to RCLK_c +) - Delay: 7.352ns (32.8% logic, 67.2% route), 6 logic levels. + Delay: 7.895ns (30.6% logic, 69.4% route), 6 logic levels. Constraint Details: - 7.352ns physical path delay SLICE_2 to SLICE_33 meets + 7.895ns physical path delay SLICE_2 to SLICE_52 meets 16.000ns delay constraint less 0.000ns skew and - 0.244ns CE_SET requirement (totaling 15.756ns) by 8.404ns + 0.181ns DIN_SET requirement (totaling 15.819ns) by 7.924ns Physical Path Details: - Data path SLICE_2 to SLICE_33: + Data path SLICE_2 to SLICE_52: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.560 R8C3D.CLK to R8C3D.Q0 SLICE_2 (from RCLK_c) -ROUTE 3 1.380 R8C3D.Q0 to R7C4A.C1 FS[14] -CTOF_DEL --- 0.371 R7C4A.C1 to R7C4A.F1 SLICE_81 -ROUTE 1 0.700 R7C4A.F1 to R7C3B.D1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 R7C3B.D1 to R7C3B.F1 SLICE_72 -ROUTE 4 0.350 R7C3B.F1 to R7C3C.D1 N_51 -CTOF_DEL --- 0.371 R7C3C.D1 to R7C3C.F1 SLICE_58 -ROUTE 2 0.642 R7C3C.F1 to R7C3D.D0 N_151 -CTOF_DEL --- 0.371 R7C3D.D0 to R7C3D.F0 SLICE_87 -ROUTE 2 0.700 R7C3D.F0 to R7C2D.D0 N_137_8 -CTOF_DEL --- 0.371 R7C2D.D0 to R7C2D.F0 SLICE_69 -ROUTE 1 1.165 R7C2D.F0 to R7C5A.CE N_33 (to RCLK_c) +ROUTE 3 0.716 R8C3D.Q0 to R8C4B.D1 FS[14] +CTOF_DEL --- 0.371 R8C4B.D1 to R8C4B.F1 SLICE_86 +ROUTE 1 0.694 R8C4B.F1 to R7C4A.D1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.371 R7C4A.D1 to R7C4A.F1 SLICE_69 +ROUTE 4 1.192 R7C4A.F1 to R6C5D.D1 N_128 +CTOF_DEL --- 0.371 R6C5D.D1 to R6C5D.F1 SLICE_58 +ROUTE 3 1.723 R6C5D.F1 to R3C5A.C0 N_94 +CTOF_DEL --- 0.371 R3C5A.C0 to R3C5A.F0 SLICE_55 +ROUTE 1 1.155 R3C5A.F0 to R7C5B.D0 UFMSDI_r_xx_mm_1 +CTOF_DEL --- 0.371 R7C5B.D0 to R7C5B.F0 SLICE_52 +ROUTE 1 0.000 R7C5B.F0 to R7C5B.DI0 UFMSDI_RNO (to RCLK_c) -------- - 7.352 (32.8% logic, 67.2% route), 6 logic levels. + 7.895 (30.6% logic, 69.4% route), 6 logic levels. Clock Skew Details: @@ -831,204 +1015,47 @@ ROUTE 32 1.353 86.PADDI to R8C3D.CLK RCLK_c -------- 1.353 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_33: + Destination Clock Path RCLK to SLICE_52: Name Fanout Delay (ns) Site Resource -ROUTE 32 1.353 86.PADDI to R7C5A.CLK RCLK_c +ROUTE 32 1.353 86.PADDI to R7C5B.CLK RCLK_c -------- 1.353 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 8.470ns +Passed: The following path meets requirements by 7.974ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS[17] (from RCLK_c +) - Destination: FF Data in n8MEGEN (to RCLK_c +) - - Delay: 7.286ns (33.1% logic, 66.9% route), 6 logic levels. - - Constraint Details: - - 7.286ns physical path delay SLICE_1 to SLICE_58 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.244ns CE_SET requirement (totaling 15.756ns) by 8.470ns - - Physical Path Details: - - Data path SLICE_1 to SLICE_58: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C4A.CLK to R8C4A.Q1 SLICE_1 (from RCLK_c) -ROUTE 3 1.406 R8C4A.Q1 to R7C4A.A1 FS[17] -CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_81 -ROUTE 1 0.700 R7C4A.F1 to R7C3B.D1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 R7C3B.D1 to R7C3B.F1 SLICE_72 -ROUTE 4 0.350 R7C3B.F1 to R7C3C.D1 N_51 -CTOF_DEL --- 0.371 R7C3C.D1 to R7C3C.F1 SLICE_58 -ROUTE 2 0.642 R7C3C.F1 to R7C3D.D0 N_151 -CTOF_DEL --- 0.371 R7C3D.D0 to R7C3D.F0 SLICE_87 -ROUTE 2 0.700 R7C3D.F0 to R7C2B.D0 N_137_8 -CTOF_DEL --- 0.371 R7C2B.D0 to R7C2B.F0 SLICE_68 -ROUTE 1 1.073 R7C2B.F0 to R7C3C.CE N_31 (to RCLK_c) - -------- - 7.286 (33.1% logic, 66.9% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_1: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 1.353 86.PADDI to R8C4A.CLK RCLK_c - -------- - 1.353 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_58: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 1.353 86.PADDI to R7C3C.CLK RCLK_c - -------- - 1.353 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 8.496ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[14] (from RCLK_c +) - Destination: FF Data in n8MEGEN (to RCLK_c +) - - Delay: 7.260ns (33.3% logic, 66.7% route), 6 logic levels. - - Constraint Details: - - 7.260ns physical path delay SLICE_2 to SLICE_58 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.244ns CE_SET requirement (totaling 15.756ns) by 8.496ns - - Physical Path Details: - - Data path SLICE_2 to SLICE_58: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C3D.CLK to R8C3D.Q0 SLICE_2 (from RCLK_c) -ROUTE 3 1.380 R8C3D.Q0 to R7C4A.C1 FS[14] -CTOF_DEL --- 0.371 R7C4A.C1 to R7C4A.F1 SLICE_81 -ROUTE 1 0.700 R7C4A.F1 to R7C3B.D1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 R7C3B.D1 to R7C3B.F1 SLICE_72 -ROUTE 4 0.350 R7C3B.F1 to R7C3C.D1 N_51 -CTOF_DEL --- 0.371 R7C3C.D1 to R7C3C.F1 SLICE_58 -ROUTE 2 0.642 R7C3C.F1 to R7C3D.D0 N_151 -CTOF_DEL --- 0.371 R7C3D.D0 to R7C3D.F0 SLICE_87 -ROUTE 2 0.700 R7C3D.F0 to R7C2B.D0 N_137_8 -CTOF_DEL --- 0.371 R7C2B.D0 to R7C2B.F0 SLICE_68 -ROUTE 1 1.073 R7C2B.F0 to R7C3C.CE N_31 (to RCLK_c) - -------- - 7.260 (33.3% logic, 66.7% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_2: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 1.353 86.PADDI to R8C3D.CLK RCLK_c - -------- - 1.353 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_58: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 1.353 86.PADDI to R7C3C.CLK RCLK_c - -------- - 1.353 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 8.592ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS[0] (from RCLK_c +) - Destination: FF Data in Ready_fast (to RCLK_c +) - - Delay: 7.227ns (23.1% logic, 76.9% route), 4 logic levels. - - Constraint Details: - - 7.227ns physical path delay SLICE_29 to SLICE_44 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.181ns DIN_SET requirement (totaling 15.819ns) by 8.592ns - - Physical Path Details: - - Data path SLICE_29 to SLICE_44: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R2C5D.CLK to R2C5D.Q0 SLICE_29 (from RCLK_c) -ROUTE 9 3.095 R2C5D.Q0 to R6C5A.B0 IS[0] -CTOF_DEL --- 0.371 R6C5A.B0 to R6C5A.F0 SLICE_83 -ROUTE 2 1.962 R6C5A.F0 to R4C4D.A1 N_165 -CTOF_DEL --- 0.371 R4C4D.A1 to R4C4D.F1 SLICE_44 -ROUTE 1 0.497 R4C4D.F1 to R4C4D.C0 Ready_0_sqmuxa -CTOF_DEL --- 0.371 R4C4D.C0 to R4C4D.F0 SLICE_44 -ROUTE 1 0.000 R4C4D.F0 to R4C4D.DI0 N_463_0 (to RCLK_c) - -------- - 7.227 (23.1% logic, 76.9% route), 4 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_29: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 1.353 86.PADDI to R2C5D.CLK RCLK_c - -------- - 1.353 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_44: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 1.353 86.PADDI to R4C4D.CLK RCLK_c - -------- - 1.353 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 8.599ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[13] (from RCLK_c +) + Source: FF Q FS[12] (from RCLK_c +) Destination: FF Data in LEDEN (to RCLK_c +) - Delay: 7.157ns (33.7% logic, 66.3% route), 6 logic levels. + Delay: 7.782ns (26.3% logic, 73.7% route), 5 logic levels. Constraint Details: - 7.157ns physical path delay SLICE_3 to SLICE_33 meets + 7.782ns physical path delay SLICE_3 to SLICE_33 meets 16.000ns delay constraint less 0.000ns skew and - 0.244ns CE_SET requirement (totaling 15.756ns) by 8.599ns + 0.244ns CE_SET requirement (totaling 15.756ns) by 7.974ns Physical Path Details: Data path SLICE_3 to SLICE_33: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C3C.CLK to R8C3C.Q1 SLICE_3 (from RCLK_c) -ROUTE 3 1.185 R8C3C.Q1 to R7C4A.D1 FS[13] -CTOF_DEL --- 0.371 R7C4A.D1 to R7C4A.F1 SLICE_81 -ROUTE 1 0.700 R7C4A.F1 to R7C3B.D1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 R7C3B.D1 to R7C3B.F1 SLICE_72 -ROUTE 4 0.350 R7C3B.F1 to R7C3C.D1 N_51 -CTOF_DEL --- 0.371 R7C3C.D1 to R7C3C.F1 SLICE_58 -ROUTE 2 0.642 R7C3C.F1 to R7C3D.D0 N_151 -CTOF_DEL --- 0.371 R7C3D.D0 to R7C3D.F0 SLICE_87 -ROUTE 2 0.700 R7C3D.F0 to R7C2D.D0 N_137_8 -CTOF_DEL --- 0.371 R7C2D.D0 to R7C2D.F0 SLICE_69 -ROUTE 1 1.165 R7C2D.F0 to R7C5A.CE N_33 (to RCLK_c) +REG_DEL --- 0.560 R8C3C.CLK to R8C3C.Q0 SLICE_3 (from RCLK_c) +ROUTE 3 1.870 R8C3C.Q0 to R8C4B.C1 FS[12] +CTOF_DEL --- 0.371 R8C4B.C1 to R8C4B.F1 SLICE_86 +ROUTE 1 0.694 R8C4B.F1 to R7C4A.D1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.371 R7C4A.D1 to R7C4A.F1 SLICE_69 +ROUTE 4 1.192 R7C4A.F1 to R6C5D.D1 N_128 +CTOF_DEL --- 0.371 R6C5D.D1 to R6C5D.F1 SLICE_58 +ROUTE 3 0.909 R6C5D.F1 to R7C5D.C0 N_94 +CTOF_DEL --- 0.371 R7C5D.C0 to R7C5D.F0 SLICE_72 +ROUTE 1 1.073 R7C5D.F0 to R6C5B.CE N_26 (to RCLK_c) -------- - 7.157 (33.7% logic, 66.3% route), 6 logic levels. + 7.782 (26.3% logic, 73.7% route), 5 logic levels. Clock Skew Details: @@ -1042,44 +1069,44 @@ ROUTE 32 1.353 86.PADDI to R8C3C.CLK RCLK_c Destination Clock Path RCLK to SLICE_33: Name Fanout Delay (ns) Site Resource -ROUTE 32 1.353 86.PADDI to R7C5A.CLK RCLK_c +ROUTE 32 1.353 86.PADDI to R6C5B.CLK RCLK_c -------- 1.353 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 8.660ns +Passed: The following path meets requirements by 7.985ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS[7] (from RCLK_c +) + Source: FF Q FS[6] (from RCLK_c +) Destination: FF Data in UFMSDI (to RCLK_c +) - Delay: 7.159ns (28.6% logic, 71.4% route), 5 logic levels. + Delay: 7.834ns (26.1% logic, 73.9% route), 5 logic levels. Constraint Details: - 7.159ns physical path delay SLICE_6 to SLICE_52 meets + 7.834ns physical path delay SLICE_6 to SLICE_52 meets 16.000ns delay constraint less 0.000ns skew and - 0.181ns DIN_SET requirement (totaling 15.819ns) by 8.660ns + 0.181ns DIN_SET requirement (totaling 15.819ns) by 7.985ns Physical Path Details: Data path SLICE_6 to SLICE_52: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C2D.CLK to R8C2D.Q1 SLICE_6 (from RCLK_c) -ROUTE 3 2.186 R8C2D.Q1 to R4C5A.B0 FS[7] -CTOF_DEL --- 0.371 R4C5A.B0 to R4C5A.F0 SLICE_56 -ROUTE 1 1.609 R4C5A.F0 to R7C3A.D1 N_126 -CTOF_DEL --- 0.371 R7C3A.D1 to R7C3A.F1 SLICE_32 -ROUTE 1 0.626 R7C3A.F1 to R7C3D.D1 UFMSDI_ens2_i_a0 -CTOF_DEL --- 0.371 R7C3D.D1 to R7C3D.F1 SLICE_87 -ROUTE 1 0.694 R7C3D.F1 to R7C5B.D0 UFMSDI_r_xx_mm_1 +REG_DEL --- 0.560 R8C2D.CLK to R8C2D.Q0 SLICE_6 (from RCLK_c) +ROUTE 3 1.179 R8C2D.Q0 to R7C3C.D1 FS[6] +CTOF_DEL --- 0.371 R7C3C.D1 to R7C3C.F1 SLICE_94 +ROUTE 1 1.840 R7C3C.F1 to R7C4B.C1 UFMSDI_ens2_i_a2_4_2 +CTOF_DEL --- 0.371 R7C4B.C1 to R7C4B.F1 SLICE_32 +ROUTE 1 1.616 R7C4B.F1 to R3C5A.D0 UFMSDI_ens2_i_a0 +CTOF_DEL --- 0.371 R3C5A.D0 to R3C5A.F0 SLICE_55 +ROUTE 1 1.155 R3C5A.F0 to R7C5B.D0 UFMSDI_r_xx_mm_1 CTOF_DEL --- 0.371 R7C5B.D0 to R7C5B.F0 SLICE_52 ROUTE 1 0.000 R7C5B.F0 to R7C5B.DI0 UFMSDI_RNO (to RCLK_c) -------- - 7.159 (28.6% logic, 71.4% route), 5 logic levels. + 7.834 (26.1% logic, 73.9% route), 5 logic levels. Clock Skew Details: @@ -1098,59 +1125,57 @@ ROUTE 32 1.353 86.PADDI to R7C5B.CLK RCLK_c 1.353 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 8.691ns +Passed: The following path meets requirements by 8.032ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS[13] (from RCLK_c +) - Destination: FF Data in n8MEGEN (to RCLK_c +) + Source: FF Q FS[11] (from RCLK_c +) + Destination: FF Data in UFMSDI (to RCLK_c +) - Delay: 7.065ns (34.2% logic, 65.8% route), 6 logic levels. + Delay: 7.787ns (26.2% logic, 73.8% route), 5 logic levels. Constraint Details: - 7.065ns physical path delay SLICE_3 to SLICE_58 meets + 7.787ns physical path delay SLICE_4 to SLICE_52 meets 16.000ns delay constraint less 0.000ns skew and - 0.244ns CE_SET requirement (totaling 15.756ns) by 8.691ns + 0.181ns DIN_SET requirement (totaling 15.819ns) by 8.032ns Physical Path Details: - Data path SLICE_3 to SLICE_58: + Data path SLICE_4 to SLICE_52: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C3C.CLK to R8C3C.Q1 SLICE_3 (from RCLK_c) -ROUTE 3 1.185 R8C3C.Q1 to R7C4A.D1 FS[13] -CTOF_DEL --- 0.371 R7C4A.D1 to R7C4A.F1 SLICE_81 -ROUTE 1 0.700 R7C4A.F1 to R7C3B.D1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 R7C3B.D1 to R7C3B.F1 SLICE_72 -ROUTE 4 0.350 R7C3B.F1 to R7C3C.D1 N_51 -CTOF_DEL --- 0.371 R7C3C.D1 to R7C3C.F1 SLICE_58 -ROUTE 2 0.642 R7C3C.F1 to R7C3D.D0 N_151 -CTOF_DEL --- 0.371 R7C3D.D0 to R7C3D.F0 SLICE_87 -ROUTE 2 0.700 R7C3D.F0 to R7C2B.D0 N_137_8 -CTOF_DEL --- 0.371 R7C2B.D0 to R7C2B.F0 SLICE_68 -ROUTE 1 1.073 R7C2B.F0 to R7C3C.CE N_31 (to RCLK_c) +REG_DEL --- 0.560 R8C3B.CLK to R8C3B.Q1 SLICE_4 (from RCLK_c) +ROUTE 6 1.132 R8C3B.Q1 to R7C3C.B1 FS[11] +CTOF_DEL --- 0.371 R7C3C.B1 to R7C3C.F1 SLICE_94 +ROUTE 1 1.840 R7C3C.F1 to R7C4B.C1 UFMSDI_ens2_i_a2_4_2 +CTOF_DEL --- 0.371 R7C4B.C1 to R7C4B.F1 SLICE_32 +ROUTE 1 1.616 R7C4B.F1 to R3C5A.D0 UFMSDI_ens2_i_a0 +CTOF_DEL --- 0.371 R3C5A.D0 to R3C5A.F0 SLICE_55 +ROUTE 1 1.155 R3C5A.F0 to R7C5B.D0 UFMSDI_r_xx_mm_1 +CTOF_DEL --- 0.371 R7C5B.D0 to R7C5B.F0 SLICE_52 +ROUTE 1 0.000 R7C5B.F0 to R7C5B.DI0 UFMSDI_RNO (to RCLK_c) -------- - 7.065 (34.2% logic, 65.8% route), 6 logic levels. + 7.787 (26.2% logic, 73.8% route), 5 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_3: + Source Clock Path RCLK to SLICE_4: Name Fanout Delay (ns) Site Resource -ROUTE 32 1.353 86.PADDI to R8C3C.CLK RCLK_c +ROUTE 32 1.353 86.PADDI to R8C3B.CLK RCLK_c -------- 1.353 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_58: + Destination Clock Path RCLK to SLICE_52: Name Fanout Delay (ns) Site Resource -ROUTE 32 1.353 86.PADDI to R7C3C.CLK RCLK_c +ROUTE 32 1.353 86.PADDI to R7C5B.CLK RCLK_c -------- 1.353 (0.0% logic, 100.0% route), 0 logic levels. -Report: 128.419MHz is the maximum frequency for this preference. +Report: 108.342MHz is the maximum frequency for this preference. Report Summary -------------- @@ -1158,13 +1183,13 @@ Report: 128.419MHz is the maximum frequency for this preference. Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | -FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 56.029 MHz| 6 +FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 47.219 MHz| 7 | | | FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 400.000 MHz| 0 | | | FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 400.000 MHz| 0 | | | -FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 128.419 MHz| 6 +FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 108.342 MHz| 6 | | | ---------------------------------------------------------------------------- @@ -1219,11 +1244,11 @@ Clock Domain: PHI2_c Source: PHI2.PAD Loads: 15 Timing errors: 0 Score: 0 Cumulative negative slack: 0 -Constraints cover 517 paths, 4 nets, and 420 connections (66.35% coverage) +Constraints cover 560 paths, 4 nets, and 447 connections (65.64% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 -Thu Sep 21 05:38:43 2023 +Sat Jan 06 06:25:12 2024 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -1242,13 +1267,13 @@ Report level: verbose report, limited to 10 items per preference Preference Summary -
  • FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)
    • 129 items scored, 0 timing errors detected. +
  • FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)
    • 168 items scored, 0 timing errors detected.
  • FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)
    • 0 items scored, 0 timing errors detected.
  • FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)
    • 0 items scored, 0 timing errors detected. -
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    • 388 items scored, 0 timing errors detected. +
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    • 392 items scored, 0 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS @@ -1258,7 +1283,7 @@ BLOCK RESETPATHS ================================================================================ Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ; - 129 items scored, 0 timing errors detected. + 168 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- @@ -1283,10 +1308,10 @@ Passed: The following path meets requirements by 0.358ns Data path SLICE_9 to SLICE_9: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R5C3B.CLK to R5C3B.Q0 SLICE_9 (from PHI2_c) -ROUTE 2 0.128 R5C3B.Q0 to R5C3B.D0 ADSubmitted -CTOF_DEL --- 0.074 R5C3B.D0 to R5C3B.F0 SLICE_9 -ROUTE 1 0.000 R5C3B.F0 to R5C3B.DI0 ADSubmitted_r (to PHI2_c) +REG_DEL --- 0.137 R5C3A.CLK to R5C3A.Q0 SLICE_9 (from PHI2_c) +ROUTE 2 0.128 R5C3A.Q0 to R5C3A.D0 ADSubmitted +CTOF_DEL --- 0.074 R5C3A.D0 to R5C3A.F0 SLICE_9 +ROUTE 1 0.000 R5C3A.F0 to R5C3A.DI0 ADSubmitted_r (to PHI2_c) -------- 0.339 (62.2% logic, 37.8% route), 2 logic levels. @@ -1295,14 +1320,14 @@ ROUTE 1 0.000 R5C3B.F0 to R5C3B.DI0 ADSubmitted_r (to PHI Source Clock Path PHI2 to SLICE_9: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.967 39.PADDI to R5C3B.CLK PHI2_c +ROUTE 15 0.967 39.PADDI to R5C3A.CLK PHI2_c -------- 0.967 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_9: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.967 39.PADDI to R5C3B.CLK PHI2_c +ROUTE 15 0.967 39.PADDI to R5C3A.CLK PHI2_c -------- 0.967 (0.0% logic, 100.0% route), 0 logic levels. @@ -1328,10 +1353,10 @@ Passed: The following path meets requirements by 0.364ns Data path SLICE_22 to SLICE_22: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R6C4A.CLK to R6C4A.Q0 SLICE_22 (from PHI2_c) -ROUTE 3 0.134 R6C4A.Q0 to R6C4A.A0 CmdSubmitted -CTOF_DEL --- 0.074 R6C4A.A0 to R6C4A.F0 SLICE_22 -ROUTE 1 0.000 R6C4A.F0 to R6C4A.DI0 N_460_0 (to PHI2_c) +REG_DEL --- 0.137 R6C5C.CLK to R6C5C.Q0 SLICE_22 (from PHI2_c) +ROUTE 3 0.134 R6C5C.Q0 to R6C5C.A0 CmdSubmitted +CTOF_DEL --- 0.074 R6C5C.A0 to R6C5C.F0 SLICE_22 +ROUTE 1 0.000 R6C5C.F0 to R6C5C.DI0 N_428_0 (to PHI2_c) -------- 0.345 (61.2% logic, 38.8% route), 2 logic levels. @@ -1340,230 +1365,95 @@ ROUTE 1 0.000 R6C4A.F0 to R6C4A.DI0 N_460_0 (to PHI2_c) Source Clock Path PHI2 to SLICE_22: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.967 39.PADDI to R6C4A.CLK PHI2_c +ROUTE 15 0.967 39.PADDI to R6C5C.CLK PHI2_c -------- 0.967 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_22: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.967 39.PADDI to R6C4A.CLK PHI2_c +ROUTE 15 0.967 39.PADDI to R6C5C.CLK PHI2_c -------- 0.967 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 0.415ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CmdEnable (from PHI2_c -) - Destination: FF Data in CmdEnable (to PHI2_c -) - - Delay: 0.396ns (66.2% logic, 33.8% route), 2 logic levels. - - Constraint Details: - - 0.396ns physical path delay SLICE_20 to SLICE_20 meets - -0.019ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.415ns - - Physical Path Details: - - Data path SLICE_20 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R5C3D.CLK to R5C3D.Q0 SLICE_20 (from PHI2_c) -ROUTE 3 0.134 R5C3D.Q0 to R5C3D.A0 CmdEnable -CTOOFX_DEL --- 0.125 R5C3D.A0 to R5C3D.OFX0 SLICE_20 -ROUTE 1 0.000 R5C3D.OFX0 to R5C3D.DI0 CmdEnable_s (to PHI2_c) - -------- - 0.396 (66.2% logic, 33.8% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 0.967 39.PADDI to R5C3D.CLK PHI2_c - -------- - 0.967 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 0.967 39.PADDI to R5C3D.CLK PHI2_c - -------- - 0.967 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.436ns +Passed: The following path meets requirements by 0.399ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q C1Submitted (from PHI2_c -) Destination: FF Data in C1Submitted (to PHI2_c -) - Delay: 0.417ns (50.6% logic, 49.4% route), 2 logic levels. + Delay: 0.380ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: - 0.417ns physical path delay SLICE_14 to SLICE_14 meets + 0.380ns physical path delay SLICE_14 to SLICE_14 meets -0.019ns DIN_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.436ns + 0.000ns skew requirement (totaling -0.019ns) by 0.399ns Physical Path Details: Data path SLICE_14 to SLICE_14: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R5C3C.CLK to R5C3C.Q0 SLICE_14 (from PHI2_c) -ROUTE 2 0.206 R5C3C.Q0 to R5C3C.B0 C1Submitted -CTOF_DEL --- 0.074 R5C3C.B0 to R5C3C.F0 SLICE_14 -ROUTE 1 0.000 R5C3C.F0 to R5C3C.DI0 C1Submitted_RNO (to PHI2_c) +REG_DEL --- 0.137 R6C3A.CLK to R6C3A.Q0 SLICE_14 (from PHI2_c) +ROUTE 2 0.169 R6C3A.Q0 to R6C3A.C0 C1Submitted +CTOF_DEL --- 0.074 R6C3A.C0 to R6C3A.F0 SLICE_14 +ROUTE 1 0.000 R6C3A.F0 to R6C3A.DI0 C1Submitted_RNO (to PHI2_c) -------- - 0.417 (50.6% logic, 49.4% route), 2 logic levels. + 0.380 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_14: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.967 39.PADDI to R5C3C.CLK PHI2_c +ROUTE 15 0.967 39.PADDI to R6C3A.CLK PHI2_c -------- 0.967 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_14: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.967 39.PADDI to R5C3C.CLK PHI2_c +ROUTE 15 0.967 39.PADDI to R6C3A.CLK PHI2_c -------- 0.967 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 0.477ns +Passed: The following path meets requirements by 0.438ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CmdEnable (from PHI2_c -) Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 0.458ns (56.3% logic, 43.7% route), 2 logic levels. + Delay: 0.419ns (50.4% logic, 49.6% route), 2 logic levels. Constraint Details: - 0.458ns physical path delay SLICE_20 to SLICE_20 meets + 0.419ns physical path delay SLICE_20 to SLICE_20 meets -0.019ns DIN_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.477ns + 0.000ns skew requirement (totaling -0.019ns) by 0.438ns Physical Path Details: Data path SLICE_20 to SLICE_20: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R5C3D.CLK to R5C3D.Q0 SLICE_20 (from PHI2_c) -ROUTE 3 0.200 R5C3D.Q0 to R5C3D.A1 CmdEnable -CTOOFX_DEL --- 0.121 R5C3D.A1 to R5C3D.OFX0 SLICE_20 -ROUTE 1 0.000 R5C3D.OFX0 to R5C3D.DI0 CmdEnable_s (to PHI2_c) +REG_DEL --- 0.137 R5C3C.CLK to R5C3C.Q0 SLICE_20 (from PHI2_c) +ROUTE 2 0.208 R5C3C.Q0 to R5C3C.B0 CmdEnable +CTOF_DEL --- 0.074 R5C3C.B0 to R5C3C.F0 SLICE_20 +ROUTE 1 0.000 R5C3C.F0 to R5C3C.DI0 CmdEnable_s (to PHI2_c) -------- - 0.458 (56.3% logic, 43.7% route), 2 logic levels. + 0.419 (50.4% logic, 49.6% route), 2 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_20: - Name Fanout Delay (ns) Site Resource -ROUTE 15 0.967 39.PADDI to R5C3D.CLK PHI2_c - -------- - 0.967 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 0.967 39.PADDI to R5C3D.CLK PHI2_c - -------- - 0.967 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.483ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q ADSubmitted (from PHI2_c -) - Destination: FF Data in CmdEnable (to PHI2_c -) - - Delay: 0.464ns (55.6% logic, 44.4% route), 2 logic levels. - - Constraint Details: - - 0.464ns physical path delay SLICE_9 to SLICE_20 meets - -0.019ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.483ns - - Physical Path Details: - - Data path SLICE_9 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R5C3B.CLK to R5C3B.Q0 SLICE_9 (from PHI2_c) -ROUTE 2 0.206 R5C3B.Q0 to R5C3D.B1 ADSubmitted -CTOOFX_DEL --- 0.121 R5C3D.B1 to R5C3D.OFX0 SLICE_20 -ROUTE 1 0.000 R5C3D.OFX0 to R5C3D.DI0 CmdEnable_s (to PHI2_c) - -------- - 0.464 (55.6% logic, 44.4% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_9: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 0.967 39.PADDI to R5C3B.CLK PHI2_c - -------- - 0.967 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 0.967 39.PADDI to R5C3D.CLK PHI2_c - -------- - 0.967 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.487ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q C1Submitted (from PHI2_c -) - Destination: FF Data in CmdEnable (to PHI2_c -) - - Delay: 0.468ns (56.0% logic, 44.0% route), 2 logic levels. - - Constraint Details: - - 0.468ns physical path delay SLICE_14 to SLICE_20 meets - -0.019ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.487ns - - Physical Path Details: - - Data path SLICE_14 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R5C3C.CLK to R5C3C.Q0 SLICE_14 (from PHI2_c) -ROUTE 2 0.206 R5C3C.Q0 to R5C3D.B0 C1Submitted -CTOOFX_DEL --- 0.125 R5C3D.B0 to R5C3D.OFX0 SLICE_20 -ROUTE 1 0.000 R5C3D.OFX0 to R5C3D.DI0 CmdEnable_s (to PHI2_c) - -------- - 0.468 (56.0% logic, 44.0% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_14: - Name Fanout Delay (ns) Site Resource ROUTE 15 0.967 39.PADDI to R5C3C.CLK PHI2_c -------- @@ -1572,52 +1462,148 @@ ROUTE 15 0.967 39.PADDI to R5C3C.CLK PHI2_c Destination Clock Path PHI2 to SLICE_20: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.967 39.PADDI to R5C3D.CLK PHI2_c +ROUTE 15 0.967 39.PADDI to R5C3C.CLK PHI2_c -------- 0.967 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 0.595ns +Passed: The following path meets requirements by 0.572ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q CmdEnable (from PHI2_c -) + Source: FF Q Cmdn8MEGEN (from PHI2_c -) Destination: FF Data in Cmdn8MEGEN (to PHI2_c -) - Delay: 0.572ns (36.9% logic, 63.1% route), 2 logic levels. + Delay: 0.553ns (51.5% logic, 48.5% route), 3 logic levels. Constraint Details: - 0.572ns physical path delay SLICE_20 to SLICE_26 meets - -0.023ns CE_HLD and + 0.553ns physical path delay SLICE_26 to SLICE_26 meets + -0.019ns DIN_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.023ns) by 0.595ns + 0.000ns skew requirement (totaling -0.019ns) by 0.572ns Physical Path Details: - Data path SLICE_20 to SLICE_26: + Data path SLICE_26 to SLICE_26: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R5C3D.CLK to R5C3D.Q0 SLICE_20 (from PHI2_c) -ROUTE 3 0.134 R5C3D.Q0 to R5C3A.D0 CmdEnable -CTOF_DEL --- 0.074 R5C3A.D0 to R5C3A.F0 SLICE_67 -ROUTE 5 0.227 R5C3A.F0 to R6C3B.CE XOR8MEG18 (to PHI2_c) +REG_DEL --- 0.137 R6C4C.CLK to R6C4C.Q0 SLICE_26 (from PHI2_c) +ROUTE 2 0.169 R6C4C.Q0 to R6C4C.C1 Cmdn8MEGEN +CTOF_DEL --- 0.074 R6C4C.C1 to R6C4C.F1 SLICE_26 +ROUTE 1 0.099 R6C4C.F1 to R6C4C.C0 Cmdn8MEGEN_4_u_i_0 +CTOF_DEL --- 0.074 R6C4C.C0 to R6C4C.F0 SLICE_26 +ROUTE 1 0.000 R6C4C.F0 to R6C4C.DI0 N_12_i (to PHI2_c) -------- - 0.572 (36.9% logic, 63.1% route), 2 logic levels. + 0.553 (51.5% logic, 48.5% route), 3 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_20: + Source Clock Path PHI2 to SLICE_26: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.967 39.PADDI to R5C3D.CLK PHI2_c +ROUTE 15 0.967 39.PADDI to R6C4C.CLK PHI2_c -------- 0.967 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_26: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.967 39.PADDI to R6C3B.CLK PHI2_c +ROUTE 15 0.967 39.PADDI to R6C4C.CLK PHI2_c + -------- + 0.967 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.599ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdLEDEN (from PHI2_c -) + Destination: FF Data in CmdLEDEN (to PHI2_c -) + + Delay: 0.580ns (49.1% logic, 50.9% route), 3 logic levels. + + Constraint Details: + + 0.580ns physical path delay SLICE_21 to SLICE_21 meets + -0.019ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.599ns + + Physical Path Details: + + Data path SLICE_21 to SLICE_21: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R6C4D.CLK to R6C4D.Q0 SLICE_21 (from PHI2_c) +ROUTE 2 0.196 R6C4D.Q0 to R6C4D.A1 CmdLEDEN +CTOF_DEL --- 0.074 R6C4D.A1 to R6C4D.F1 SLICE_21 +ROUTE 1 0.099 R6C4D.F1 to R6C4D.C0 CmdLEDEN_4_u_i_0 +CTOF_DEL --- 0.074 R6C4D.C0 to R6C4D.F0 SLICE_21 +ROUTE 1 0.000 R6C4D.F0 to R6C4D.DI0 N_14_i (to PHI2_c) + -------- + 0.580 (49.1% logic, 50.9% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_21: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 0.967 39.PADDI to R6C4D.CLK PHI2_c + -------- + 0.967 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_21: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 0.967 39.PADDI to R6C4D.CLK PHI2_c + -------- + 0.967 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.609ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q ADSubmitted (from PHI2_c -) + Destination: FF Data in CmdEnable (to PHI2_c -) + + Delay: 0.590ns (48.3% logic, 51.7% route), 3 logic levels. + + Constraint Details: + + 0.590ns physical path delay SLICE_9 to SLICE_20 meets + -0.019ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.609ns + + Physical Path Details: + + Data path SLICE_9 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R5C3A.CLK to R5C3A.Q0 SLICE_9 (from PHI2_c) +ROUTE 2 0.206 R5C3A.Q0 to R5C3C.B1 ADSubmitted +CTOF_DEL --- 0.074 R5C3C.B1 to R5C3C.F1 SLICE_20 +ROUTE 1 0.099 R5C3C.F1 to R5C3C.C0 CmdEnable_0_sqmuxa +CTOF_DEL --- 0.074 R5C3C.C0 to R5C3C.F0 SLICE_20 +ROUTE 1 0.000 R5C3C.F0 to R5C3C.DI0 CmdEnable_s (to PHI2_c) + -------- + 0.590 (48.3% logic, 51.7% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 0.967 39.PADDI to R5C3A.CLK PHI2_c + -------- + 0.967 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 0.967 39.PADDI to R5C3C.CLK PHI2_c -------- 0.967 (0.0% logic, 100.0% route), 0 logic levels. @@ -1626,92 +1612,137 @@ Passed: The following path meets requirements by 0.611ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Cmdn8MEGEN (from PHI2_c -) - Destination: FF Data in Cmdn8MEGEN (to PHI2_c -) + Source: FF Q XOR8MEG (from PHI2_c -) + Destination: FF Data in XOR8MEG (to PHI2_c -) Delay: 0.592ns (48.1% logic, 51.9% route), 3 logic levels. Constraint Details: - 0.592ns physical path delay SLICE_26 to SLICE_26 meets + 0.592ns physical path delay SLICE_57 to SLICE_57 meets -0.019ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.611ns Physical Path Details: - Data path SLICE_26 to SLICE_26: + Data path SLICE_57 to SLICE_57: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R6C3B.CLK to R6C3B.Q0 SLICE_26 (from PHI2_c) -ROUTE 2 0.208 R6C3B.Q0 to R6C3B.B1 Cmdn8MEGEN -CTOF_DEL --- 0.074 R6C3B.B1 to R6C3B.F1 SLICE_26 -ROUTE 1 0.099 R6C3B.F1 to R6C3B.C0 Cmdn8MEGEN_4_u_i_0 -CTOF_DEL --- 0.074 R6C3B.C0 to R6C3B.F0 SLICE_26 -ROUTE 1 0.000 R6C3B.F0 to R6C3B.DI0 N_19_i (to PHI2_c) +REG_DEL --- 0.137 R5C4D.CLK to R5C4D.Q0 SLICE_57 (from PHI2_c) +ROUTE 2 0.208 R5C4D.Q0 to R5C4D.B1 XOR8MEG +CTOF_DEL --- 0.074 R5C4D.B1 to R5C4D.F1 SLICE_57 +ROUTE 1 0.099 R5C4D.F1 to R5C4D.C0 N_166 +CTOF_DEL --- 0.074 R5C4D.C0 to R5C4D.F0 SLICE_57 +ROUTE 1 0.000 R5C4D.F0 to R5C4D.DI0 XOR8MEG_3 (to PHI2_c) -------- 0.592 (48.1% logic, 51.9% route), 3 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_26: + Source Clock Path PHI2 to SLICE_57: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.967 39.PADDI to R6C3B.CLK PHI2_c +ROUTE 15 0.967 39.PADDI to R5C4D.CLK PHI2_c -------- 0.967 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_26: + Destination Clock Path PHI2 to SLICE_57: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.967 39.PADDI to R6C3B.CLK PHI2_c +ROUTE 15 0.967 39.PADDI to R5C4D.CLK PHI2_c -------- 0.967 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 0.650ns +Passed: The following path meets requirements by 0.641ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q CmdLEDEN (from PHI2_c -) - Destination: FF Data in CmdLEDEN (to PHI2_c -) + Source: FF Q C1Submitted (from PHI2_c -) + Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 0.631ns (45.2% logic, 54.8% route), 3 logic levels. + Delay: 0.622ns (45.8% logic, 54.2% route), 3 logic levels. Constraint Details: - 0.631ns physical path delay SLICE_21 to SLICE_21 meets + 0.622ns physical path delay SLICE_14 to SLICE_20 meets -0.019ns DIN_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.650ns + 0.000ns skew requirement (totaling -0.019ns) by 0.641ns Physical Path Details: - Data path SLICE_21 to SLICE_21: + Data path SLICE_14 to SLICE_20: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R6C4C.CLK to R6C4C.Q0 SLICE_21 (from PHI2_c) -ROUTE 2 0.208 R6C4C.Q0 to R6C4D.B1 CmdLEDEN -CTOF_DEL --- 0.074 R6C4D.B1 to R6C4D.F1 SLICE_82 -ROUTE 1 0.138 R6C4D.F1 to R6C4C.B0 N_132 -CTOF_DEL --- 0.074 R6C4C.B0 to R6C4C.F0 SLICE_21 -ROUTE 1 0.000 R6C4C.F0 to R6C4C.DI0 N_21_i (to PHI2_c) +REG_DEL --- 0.137 R6C3A.CLK to R6C3A.Q0 SLICE_14 (from PHI2_c) +ROUTE 2 0.130 R6C3A.Q0 to R6C3A.D1 C1Submitted +CTOF_DEL --- 0.074 R6C3A.D1 to R6C3A.F1 SLICE_14 +ROUTE 1 0.207 R6C3A.F1 to R5C3C.A0 un1_CmdEnable20_i +CTOF_DEL --- 0.074 R5C3C.A0 to R5C3C.F0 SLICE_20 +ROUTE 1 0.000 R5C3C.F0 to R5C3C.DI0 CmdEnable_s (to PHI2_c) -------- - 0.631 (45.2% logic, 54.8% route), 3 logic levels. + 0.622 (45.8% logic, 54.2% route), 3 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_21: + Source Clock Path PHI2 to SLICE_14: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.967 39.PADDI to R6C4C.CLK PHI2_c +ROUTE 15 0.967 39.PADDI to R6C3A.CLK PHI2_c + -------- + 0.967 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 0.967 39.PADDI to R5C3C.CLK PHI2_c + -------- + 0.967 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.687ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable (from PHI2_c -) + Destination: FF Data in CmdLEDEN (to PHI2_c -) + + Delay: 0.664ns (31.8% logic, 68.2% route), 2 logic levels. + + Constraint Details: + + 0.664ns physical path delay SLICE_20 to SLICE_21 meets + -0.023ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.023ns) by 0.687ns + + Physical Path Details: + + Data path SLICE_20 to SLICE_21: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R5C3C.CLK to R5C3C.Q0 SLICE_20 (from PHI2_c) +ROUTE 2 0.130 R5C3C.Q0 to R5C3B.D0 CmdEnable +CTOF_DEL --- 0.074 R5C3B.D0 to R5C3B.F0 SLICE_73 +ROUTE 5 0.323 R5C3B.F0 to R6C4D.CE XOR8MEG18 (to PHI2_c) + -------- + 0.664 (31.8% logic, 68.2% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 0.967 39.PADDI to R5C3C.CLK PHI2_c -------- 0.967 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_21: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.967 39.PADDI to R6C4C.CLK PHI2_c +ROUTE 15 0.967 39.PADDI to R6C4D.CLK PHI2_c -------- 0.967 (0.0% logic, 100.0% route), 0 logic levels. @@ -1730,7 +1761,7 @@ ROUTE 15 0.967 39.PADDI to R6C4C.CLK PHI2_c ================================================================================ Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; - 388 items scored, 0 timing errors detected. + 392 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- @@ -1745,121 +1776,77 @@ Passed: The following path meets requirements by 0.273ns Constraint Details: - 0.256ns physical path delay SLICE_75 to SLICE_75 meets + 0.256ns physical path delay SLICE_74 to SLICE_74 meets -0.017ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.017ns) by 0.273ns Physical Path Details: - Data path SLICE_75 to SLICE_75: + Data path SLICE_74 to SLICE_74: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.126 R6C4B.CLK to R6C4B.Q0 SLICE_75 (from RCLK_c) -ROUTE 1 0.130 R6C4B.Q0 to R6C4B.M1 CASr (to RCLK_c) +REG_DEL --- 0.126 R6C3D.CLK to R6C3D.Q0 SLICE_74 (from RCLK_c) +ROUTE 1 0.130 R6C3D.Q0 to R6C3D.M1 CASr (to RCLK_c) -------- 0.256 (49.2% logic, 50.8% route), 1 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_75: + Source Clock Path RCLK to SLICE_74: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.333 86.PADDI to R6C4B.CLK RCLK_c +ROUTE 32 0.333 86.PADDI to R6C3D.CLK RCLK_c -------- 0.333 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_75: + Destination Clock Path RCLK to SLICE_74: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.333 86.PADDI to R6C4B.CLK RCLK_c +ROUTE 32 0.333 86.PADDI to R6C3D.CLK RCLK_c -------- 0.333 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 0.277ns +Passed: The following path meets requirements by 0.275ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q PHI2r2 (from RCLK_c +) - Destination: FF Data in PHI2r3 (to RCLK_c +) + Source: FF Q RASr (from RCLK_c +) + Destination: FF Data in RASr2 (to RCLK_c +) - Delay: 0.260ns (48.5% logic, 51.5% route), 1 logic levels. + Delay: 0.258ns (48.8% logic, 51.2% route), 1 logic levels. Constraint Details: - 0.260ns physical path delay SLICE_41 to SLICE_43 meets + 0.258ns physical path delay SLICE_95 to SLICE_95 meets -0.017ns M_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.017ns) by 0.277ns + 0.000ns skew requirement (totaling -0.017ns) by 0.275ns Physical Path Details: - Data path SLICE_41 to SLICE_43: + Data path SLICE_95 to SLICE_95: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.126 R4C5C.CLK to R4C5C.Q1 SLICE_41 (from RCLK_c) -ROUTE 3 0.134 R4C5C.Q1 to R4C5D.M1 PHI2r2 (to RCLK_c) +REG_DEL --- 0.126 R2C4A.CLK to R2C4A.Q0 SLICE_95 (from RCLK_c) +ROUTE 2 0.132 R2C4A.Q0 to R2C4A.M1 RASr (to RCLK_c) -------- - 0.260 (48.5% logic, 51.5% route), 1 logic levels. + 0.258 (48.8% logic, 51.2% route), 1 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_41: + Source Clock Path RCLK to SLICE_95: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.333 86.PADDI to R4C5C.CLK RCLK_c +ROUTE 32 0.333 86.PADDI to R2C4A.CLK RCLK_c -------- 0.333 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_43: + Destination Clock Path RCLK to SLICE_95: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.333 86.PADDI to R4C5D.CLK RCLK_c - -------- - 0.333 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.301ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[17] (from RCLK_c +) - Destination: FF Data in FS[17] (to RCLK_c +) - FF FS[16] - - Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels. - - Constraint Details: - - 0.257ns physical path delay SLICE_1 to SLICE_1 meets - -0.044ns LUT_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.044ns) by 0.301ns - - Physical Path Details: - - Data path SLICE_1 to SLICE_1: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.126 R8C4A.CLK to R8C4A.Q1 SLICE_1 (from RCLK_c) -ROUTE 3 0.131 R8C4A.Q1 to R8C4A.A1 FS[17] (to RCLK_c) - -------- - 0.257 (49.0% logic, 51.0% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_1: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 0.333 86.PADDI to R8C4A.CLK RCLK_c - -------- - 0.333 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_1: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 0.333 86.PADDI to R8C4A.CLK RCLK_c +ROUTE 32 0.333 86.PADDI to R2C4A.CLK RCLK_c -------- 0.333 (0.0% logic, 100.0% route), 0 logic levels. @@ -1933,7 +1920,7 @@ Passed: The following path meets requirements by 0.301ns Name Fanout Delay (ns) Site Resource REG_DEL --- 0.126 R8C3C.CLK to R8C3C.Q1 SLICE_3 (from RCLK_c) -ROUTE 3 0.131 R8C3C.Q1 to R8C3C.A1 FS[13] (to RCLK_c) +ROUTE 4 0.131 R8C3C.Q1 to R8C3C.A1 FS[13] (to RCLK_c) -------- 0.257 (49.0% logic, 51.0% route), 1 logic levels. @@ -1958,43 +1945,88 @@ Passed: The following path meets requirements by 0.301ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS[11] (from RCLK_c +) - Destination: FF Data in FS_cry_0[10] (to RCLK_c +) - FF FS[11] - FF FS[10] + Source: FF Q FS[9] (from RCLK_c +) + Destination: FF Data in FS_cry_0[8] (to RCLK_c +) + FF FS[9] + FF FS[8] Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels. Constraint Details: - 0.257ns physical path delay SLICE_4 to SLICE_4 meets + 0.257ns physical path delay SLICE_5 to SLICE_5 meets -0.044ns LUT_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.044ns) by 0.301ns Physical Path Details: - Data path SLICE_4 to SLICE_4: + Data path SLICE_5 to SLICE_5: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.126 R8C3B.CLK to R8C3B.Q1 SLICE_4 (from RCLK_c) -ROUTE 6 0.131 R8C3B.Q1 to R8C3B.A1 FS[11] (to RCLK_c) +REG_DEL --- 0.126 R8C3A.CLK to R8C3A.Q1 SLICE_5 (from RCLK_c) +ROUTE 3 0.131 R8C3A.Q1 to R8C3A.A1 FS[9] (to RCLK_c) -------- 0.257 (49.0% logic, 51.0% route), 1 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_4: + Source Clock Path RCLK to SLICE_5: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.333 86.PADDI to R8C3B.CLK RCLK_c +ROUTE 32 0.333 86.PADDI to R8C3A.CLK RCLK_c -------- 0.333 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_4: + Destination Clock Path RCLK to SLICE_5: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.333 86.PADDI to R8C3B.CLK RCLK_c +ROUTE 32 0.333 86.PADDI to R8C3A.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.301ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[7] (from RCLK_c +) + Destination: FF Data in FS_cry_0[6] (to RCLK_c +) + FF FS[7] + FF FS[6] + + Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels. + + Constraint Details: + + 0.257ns physical path delay SLICE_6 to SLICE_6 meets + -0.044ns LUT_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.044ns) by 0.301ns + + Physical Path Details: + + Data path SLICE_6 to SLICE_6: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R8C2D.CLK to R8C2D.Q1 SLICE_6 (from RCLK_c) +ROUTE 3 0.131 R8C2D.Q1 to R8C2D.A1 FS[7] (to RCLK_c) + -------- + 0.257 (49.0% logic, 51.0% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_6: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 0.333 86.PADDI to R8C2D.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_6: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 0.333 86.PADDI to R8C2D.CLK RCLK_c -------- 0.333 (0.0% logic, 100.0% route), 0 logic levels. @@ -2023,7 +2055,7 @@ Passed: The following path meets requirements by 0.301ns Name Fanout Delay (ns) Site Resource REG_DEL --- 0.126 R8C2B.CLK to R8C2B.Q1 SLICE_8 (from RCLK_c) -ROUTE 3 0.131 R8C2B.Q1 to R8C2B.A1 FS[3] (to RCLK_c) +ROUTE 2 0.131 R8C2B.Q1 to R8C2B.A1 FS[3] (to RCLK_c) -------- 0.257 (49.0% logic, 51.0% route), 1 logic levels. @@ -2068,7 +2100,7 @@ Passed: The following path meets requirements by 0.302ns Name Fanout Delay (ns) Site Resource REG_DEL --- 0.126 R8C2A.CLK to R8C2A.Q0 SLICE_0 (from RCLK_c) -ROUTE 3 0.131 R8C2A.Q0 to R8C2A.A0 FS[0] (to RCLK_c) +ROUTE 2 0.131 R8C2A.Q0 to R8C2A.A0 FS[0] (to RCLK_c) -------- 0.257 (49.0% logic, 51.0% route), 1 logic levels. @@ -2093,42 +2125,43 @@ Passed: The following path meets requirements by 0.302ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS[16] (from RCLK_c +) - Destination: FF Data in FS[17] (to RCLK_c +) - FF FS[16] + Source: FF Q FS[14] (from RCLK_c +) + Destination: FF Data in FS_cry_0[14] (to RCLK_c +) + FF FS[15] + FF FS[14] Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels. Constraint Details: - 0.257ns physical path delay SLICE_1 to SLICE_1 meets + 0.257ns physical path delay SLICE_2 to SLICE_2 meets -0.045ns LUT_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.045ns) by 0.302ns Physical Path Details: - Data path SLICE_1 to SLICE_1: + Data path SLICE_2 to SLICE_2: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.126 R8C4A.CLK to R8C4A.Q0 SLICE_1 (from RCLK_c) -ROUTE 4 0.131 R8C4A.Q0 to R8C4A.A0 FS[16] (to RCLK_c) +REG_DEL --- 0.126 R8C3D.CLK to R8C3D.Q0 SLICE_2 (from RCLK_c) +ROUTE 3 0.131 R8C3D.Q0 to R8C3D.A0 FS[14] (to RCLK_c) -------- 0.257 (49.0% logic, 51.0% route), 1 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_1: + Source Clock Path RCLK to SLICE_2: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.333 86.PADDI to R8C4A.CLK RCLK_c +ROUTE 32 0.333 86.PADDI to R8C3D.CLK RCLK_c -------- 0.333 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_1: + Destination Clock Path RCLK to SLICE_2: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.333 86.PADDI to R8C4A.CLK RCLK_c +ROUTE 32 0.333 86.PADDI to R8C3D.CLK RCLK_c -------- 0.333 (0.0% logic, 100.0% route), 0 logic levels. @@ -2244,7 +2277,7 @@ Clock Domain: PHI2_c Source: PHI2.PAD Loads: 15 Timing errors: 0 Score: 0 Cumulative negative slack: 0 -Constraints cover 517 paths, 4 nets, and 420 connections (66.35% coverage) +Constraints cover 560 paths, 4 nets, and 447 connections (65.64% coverage) diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_vo.sdf b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_vo.sdf index 6daf471..fad42b7 100644 --- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_vo.sdf +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_vo.sdf @@ -1,7 +1,7 @@ (DELAYFILE (SDFVERSION "3.0") (DESIGN "RAM2GS") - (DATE "Thu Sep 21 05:38:46 2023") + (DATE "Sat Jan 06 06:25:15 2024") (VENDOR "Lattice") (PROGRAM "ldbanno") (VERSION "Diamond (64-bit) 3.12.1.454") @@ -173,8 +173,6 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) - (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH C0 F0 (301:336:371)(301:336:371)) @@ -198,6 +196,7 @@ (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH C0 F0 (301:336:371)(301:336:371)) @@ -215,40 +214,18 @@ ) ) (CELL - (CELLTYPE "SLICE_19") - (INSTANCE SLICE_19) + (CELLTYPE "SLICE_20") + (INSTANCE SLICE_20) (DELAY (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) - (IOPATH CLK Q0 (515:537:560)(515:537:560)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) - (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1000:1000:1000)) - (WIDTH (negedge CLK) (1000:1000:1000)) - ) - ) - (CELL - (CELLTYPE "SLICE_20") - (INSTANCE SLICE_20) - (DELAY - (ABSOLUTE - (IOPATH B1 OFX0 (496:555:615)(496:555:615)) - (IOPATH A1 OFX0 (496:555:615)(496:555:615)) - (IOPATH D0 OFX0 (508:569:631)(508:569:631)) - (IOPATH C0 OFX0 (508:569:631)(508:569:631)) - (IOPATH B0 OFX0 (508:569:631)(508:569:631)) - (IOPATH A0 OFX0 (508:569:631)(508:569:631)) - (IOPATH M0 OFX0 (405:453:501)(405:453:501)) (IOPATH CLK Q0 (560:586:613)(560:586:613)) ) ) @@ -266,12 +243,12 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (560:586:613)(560:586:613)) ) ) @@ -293,7 +270,7 @@ (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (560:586:613)(560:586:613)) ) @@ -337,16 +314,17 @@ (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) ) ) (TIMINGCHECK (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) ) (TIMINGCHECK (WIDTH (posedge CLK) (1000:1000:1000)) @@ -411,7 +389,7 @@ (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (515:537:560)(515:537:560)) ) @@ -431,10 +409,11 @@ (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (515:537:560)(515:537:560)) ) ) @@ -447,15 +426,39 @@ (WIDTH (negedge CLK) (1000:1000:1000)) ) ) + (CELL + (CELLTYPE "SLICE_38") + (INSTANCE SLICE_38) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) (CELL (CELLTYPE "SLICE_39") (INSTANCE SLICE_39) (DELAY (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (515:537:560)(515:537:560)) ) @@ -500,7 +503,6 @@ (INSTANCE SLICE_42) (DELAY (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) @@ -578,7 +580,7 @@ (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (515:537:560)(515:537:560)) @@ -607,12 +609,10 @@ (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (515:537:560)(515:537:560)) - (IOPATH CLK Q1 (515:537:560)(515:537:560)) ) ) (TIMINGCHECK (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) - (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) ) (TIMINGCHECK (WIDTH (posedge CLK) (1000:1000:1000)) @@ -633,12 +633,10 @@ (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (515:537:560)(515:537:560)) - (IOPATH CLK Q1 (515:537:560)(515:537:560)) ) ) (TIMINGCHECK (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) - (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) ) (TIMINGCHECK (WIDTH (posedge CLK) (1000:1000:1000)) @@ -651,8 +649,8 @@ (DELAY (ABSOLUTE (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (560:586:613)(560:586:613)) (IOPATH CLK Q1 (560:586:613)(560:586:613)) ) @@ -671,13 +669,10 @@ (INSTANCE SLICE_56) (DELAY (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (560:586:613)(560:586:613)) (IOPATH CLK Q1 (560:586:613)(560:586:613)) ) @@ -697,9 +692,7 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) - (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) @@ -725,8 +718,8 @@ (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (515:537:560)(515:537:560)) ) ) @@ -745,7 +738,6 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) - (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) @@ -769,7 +761,6 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) - (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) @@ -909,23 +900,13 @@ (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) - (IOPATH CLK Q0 (560:586:613)(560:586:613)) - (IOPATH CLK Q1 (560:586:613)(560:586:613)) ) ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1000:1000:1000)) - (WIDTH (negedge CLK) (1000:1000:1000)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) - (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) - (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) - ) ) (CELL (CELLTYPE "SLICE_67") @@ -934,7 +915,6 @@ (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH C0 F0 (301:336:371)(301:336:371)) @@ -967,78 +947,21 @@ (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) ) ) + (TIMINGCHECK + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) ) (CELL (CELLTYPE "SLICE_69") (INSTANCE SLICE_69) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) - (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH D0 F0 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) - ) - ) - ) - (CELL - (CELLTYPE "SLICE_70") - (INSTANCE SLICE_70) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) - (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) - (IOPATH CLK Q0 (515:537:560)(515:537:560)) - (IOPATH CLK Q1 (515:537:560)(515:537:560)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) - (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1000:1000:1000)) - (WIDTH (negedge CLK) (1000:1000:1000)) - ) - ) - (CELL - (CELLTYPE "SLICE_71") - (INSTANCE SLICE_71) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) - (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH D0 F0 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) - (IOPATH CLK Q0 (515:537:560)(515:537:560)) - (IOPATH CLK Q1 (515:537:560)(515:537:560)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) - (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1000:1000:1000)) - (WIDTH (negedge CLK) (1000:1000:1000)) - ) - ) - (CELL - (CELLTYPE "SLICE_72") - (INSTANCE SLICE_72) (DELAY (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) @@ -1062,6 +985,51 @@ (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) ) ) + (CELL + (CELLTYPE "SLICE_70") + (INSTANCE SLICE_70) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_71") + (INSTANCE SLICE_71) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_72") + (INSTANCE SLICE_72) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + ) + ) + ) (CELL (CELLTYPE "SLICE_73") (INSTANCE SLICE_73) @@ -1071,8 +1039,8 @@ (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (560:586:613)(560:586:613)) (IOPATH CLK Q1 (560:586:613)(560:586:613)) ) @@ -1084,7 +1052,7 @@ (TIMINGCHECK (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) - (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) ) ) (CELL @@ -1092,23 +1060,24 @@ (INSTANCE SLICE_74) (DELAY (ABSOLUTE - (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) - (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) ) ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) (TIMINGCHECK (WIDTH (posedge CLK) (1000:1000:1000)) (WIDTH (negedge CLK) (1000:1000:1000)) ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) - (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) - ) ) (CELL (CELLTYPE "SLICE_75") @@ -1116,11 +1085,12 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (515:537:560)(515:537:560)) (IOPATH CLK Q1 (515:537:560)(515:537:560)) ) @@ -1140,7 +1110,9 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) @@ -1164,11 +1136,41 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_78") + (INSTANCE SLICE_78) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_79") + (INSTANCE SLICE_79) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (515:537:560)(515:537:560)) (IOPATH CLK Q1 (515:537:560)(515:537:560)) ) @@ -1182,79 +1184,19 @@ (WIDTH (negedge CLK) (1000:1000:1000)) ) ) - (CELL - (CELLTYPE "SLICE_78") - (INSTANCE SLICE_78) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH D0 F0 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) - (IOPATH CLK Q0 (560:586:613)(560:586:613)) - (IOPATH CLK Q1 (560:586:613)(560:586:613)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1000:1000:1000)) - (WIDTH (negedge CLK) (1000:1000:1000)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) - (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) - ) - ) - (CELL - (CELLTYPE "SLICE_79") - (INSTANCE SLICE_79) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH D0 F0 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) - (IOPATH CLK Q0 (560:586:613)(560:586:613)) - (IOPATH CLK Q1 (560:586:613)(560:586:613)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1000:1000:1000)) - (WIDTH (negedge CLK) (1000:1000:1000)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) - (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) - ) - ) (CELL (CELLTYPE "SLICE_80") (INSTANCE SLICE_80) (DELAY (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) - (IOPATH CLK Q0 (560:586:613)(560:586:613)) - (IOPATH CLK Q1 (560:586:613)(560:586:613)) ) ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1000:1000:1000)) - (WIDTH (negedge CLK) (1000:1000:1000)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) - (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) - (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) - ) ) (CELL (CELLTYPE "SLICE_81") @@ -1269,6 +1211,21 @@ (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_82") + (INSTANCE SLICE_82) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (560:586:613)(560:586:613)) (IOPATH CLK Q1 (560:586:613)(560:586:613)) ) @@ -1283,8 +1240,8 @@ ) ) (CELL - (CELLTYPE "SLICE_82") - (INSTANCE SLICE_82) + (CELLTYPE "SLICE_83") + (INSTANCE SLICE_83) (DELAY (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) @@ -1295,28 +1252,6 @@ (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) - (IOPATH CLK Q0 (515:537:560)(515:537:560)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1000:1000:1000)) - (WIDTH (negedge CLK) (1000:1000:1000)) - ) - ) - (CELL - (CELLTYPE "SLICE_83") - (INSTANCE SLICE_83) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (560:586:613)(560:586:613)) (IOPATH CLK Q1 (560:586:613)(560:586:613)) ) @@ -1344,12 +1279,64 @@ (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) ) ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) ) (CELL (CELLTYPE "SLICE_85") (INSTANCE SLICE_85) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_86") + (INSTANCE SLICE_86) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_87") + (INSTANCE SLICE_87) (DELAY (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) @@ -1373,34 +1360,6 @@ (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) ) ) - (CELL - (CELLTYPE "SLICE_86") - (INSTANCE SLICE_86) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH D0 F0 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) - ) - ) - ) - (CELL - (CELLTYPE "SLICE_87") - (INSTANCE SLICE_87) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH D0 F0 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) - ) - ) - ) (CELL (CELLTYPE "SLICE_88") (INSTANCE SLICE_88) @@ -1409,7 +1368,33 @@ (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_89") + (INSTANCE SLICE_89) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (560:586:613)(560:586:613)) (IOPATH CLK Q1 (560:586:613)(560:586:613)) @@ -1425,44 +1410,40 @@ (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) ) ) - (CELL - (CELLTYPE "SLICE_89") - (INSTANCE SLICE_89) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) - (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH D0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) - ) - ) - ) (CELL (CELLTYPE "SLICE_90") (INSTANCE SLICE_90) (DELAY (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) - (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) ) ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) ) (CELL (CELLTYPE "SLICE_91") (INSTANCE SLICE_91) (DELAY (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) ) ) ) @@ -1472,11 +1453,12 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) - (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) ) ) ) @@ -1489,32 +1471,154 @@ (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) ) ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) ) (CELL (CELLTYPE "SLICE_94") (INSTANCE SLICE_94) (DELAY (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_95") + (INSTANCE SLICE_95) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) ) ) (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) - (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) ) (TIMINGCHECK (WIDTH (posedge CLK) (1000:1000:1000)) (WIDTH (negedge CLK) (1000:1000:1000)) ) ) + (CELL + (CELLTYPE "SLICE_96") + (INSTANCE SLICE_96) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_97") + (INSTANCE SLICE_97) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_98") + (INSTANCE SLICE_98) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_99") + (INSTANCE SLICE_99) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_100") + (INSTANCE SLICE_100) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_101") + (INSTANCE SLICE_101) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) (CELL (CELLTYPE "RD_0_") (INSTANCE RD\[0\]_I) @@ -2284,11 +2388,10 @@ (DELAY (ABSOLUTE (INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (545:606:667)(545:606:667)) - (INTERCONNECT SLICE_0/Q1 SLICE_72/A0 (1232:1375:1519)(1232:1375:1519)) - (INTERCONNECT SLICE_0/Q1 SLICE_84/B0 (1203:1339:1475)(1203:1339:1475)) + (INTERCONNECT SLICE_0/Q1 SLICE_69/A0 (1560:1718:1876)(1560:1718:1876)) + (INTERCONNECT SLICE_0/Q1 SLICE_89/A1 (1560:1718:1876)(1560:1718:1876)) (INTERCONNECT SLICE_0/Q0 SLICE_0/A0 (530:591:652)(530:591:652)) - (INTERCONNECT SLICE_0/Q0 SLICE_68/B1 (903:1005:1108)(903:1005:1108)) - (INTERCONNECT SLICE_0/Q0 SLICE_69/D1 (588:652:716)(588:652:716)) + (INTERCONNECT SLICE_0/Q0 SLICE_94/C0 (1142:1253:1364)(1142:1253:1364)) (INTERCONNECT RCLK_I/PADDI SLICE_0/CLK (730:1041:1353)(730:1041:1353)) (INTERCONNECT RCLK_I/PADDI SLICE_1/CLK (730:1041:1353)(730:1041:1353)) (INTERCONNECT RCLK_I/PADDI SLICE_2/CLK (730:1041:1353)(730:1041:1353)) @@ -2298,12 +2401,12 @@ (INTERCONNECT RCLK_I/PADDI SLICE_6/CLK (730:1041:1353)(730:1041:1353)) (INTERCONNECT RCLK_I/PADDI SLICE_7/CLK (730:1041:1353)(730:1041:1353)) (INTERCONNECT RCLK_I/PADDI SLICE_8/CLK (730:1041:1353)(730:1041:1353)) - (INTERCONNECT RCLK_I/PADDI SLICE_19/CLK (730:1041:1353)(730:1041:1353)) (INTERCONNECT RCLK_I/PADDI SLICE_29/CLK (730:1041:1353)(730:1041:1353)) (INTERCONNECT RCLK_I/PADDI SLICE_30/CLK (730:1041:1353)(730:1041:1353)) (INTERCONNECT RCLK_I/PADDI SLICE_31/CLK (730:1041:1353)(730:1041:1353)) (INTERCONNECT RCLK_I/PADDI SLICE_32/CLK (730:1041:1353)(730:1041:1353)) (INTERCONNECT RCLK_I/PADDI SLICE_33/CLK (730:1041:1353)(730:1041:1353)) + (INTERCONNECT RCLK_I/PADDI SLICE_38/CLK (730:1041:1353)(730:1041:1353)) (INTERCONNECT RCLK_I/PADDI SLICE_41/CLK (730:1041:1353)(730:1041:1353)) (INTERCONNECT RCLK_I/PADDI SLICE_42/CLK (730:1041:1353)(730:1041:1353)) (INTERCONNECT RCLK_I/PADDI SLICE_43/CLK (730:1041:1353)(730:1041:1353)) @@ -2318,94 +2421,87 @@ (INTERCONNECT RCLK_I/PADDI SLICE_62/CLK (730:1041:1353)(730:1041:1353)) (INTERCONNECT RCLK_I/PADDI SLICE_63/CLK (730:1041:1353)(730:1041:1353)) (INTERCONNECT RCLK_I/PADDI SLICE_64/CLK (730:1041:1353)(730:1041:1353)) - (INTERCONNECT RCLK_I/PADDI SLICE_75/CLK (730:1041:1353)(730:1041:1353)) - (INTERCONNECT RCLK_I/PADDI SLICE_82/CLK (730:1041:1353)(730:1041:1353)) - (INTERCONNECT RCLK_I/PADDI SLICE_94/CLK (730:1041:1353)(730:1041:1353)) + (INTERCONNECT RCLK_I/PADDI SLICE_68/CLK (730:1041:1353)(730:1041:1353)) + (INTERCONNECT RCLK_I/PADDI SLICE_74/CLK (730:1041:1353)(730:1041:1353)) + (INTERCONNECT RCLK_I/PADDI SLICE_95/CLK (730:1041:1353)(730:1041:1353)) (INTERCONNECT SLICE_0/FCO SLICE_8/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q1 SLICE_1/A1 (530:591:652)(530:591:652)) - (INTERCONNECT SLICE_1/Q1 SLICE_81/A1 (1146:1276:1406)(1146:1276:1406)) - (INTERCONNECT SLICE_1/Q1 SLICE_81/C0 (743:826:909)(743:826:909)) - (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (530:591:652)(530:591:652)) - (INTERCONNECT SLICE_1/Q0 SLICE_66/A0 (862:958:1054)(862:958:1054)) - (INTERCONNECT SLICE_1/Q0 SLICE_72/C1 (1151:1263:1376)(1151:1263:1376)) - (INTERCONNECT SLICE_1/Q0 SLICE_74/B0 (908:1011:1114)(908:1011:1114)) + (INTERCONNECT SLICE_1/Q1 SLICE_1/A1 (545:606:667)(545:606:667)) + (INTERCONNECT SLICE_1/Q1 SLICE_80/D1 (595:663:731)(595:663:731)) + (INTERCONNECT SLICE_1/Q1 SLICE_86/B1 (856:952:1049)(856:952:1049)) + (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (545:606:667)(545:606:667)) + (INTERCONNECT SLICE_1/Q0 SLICE_69/C1 (754:836:918)(754:836:918)) + (INTERCONNECT SLICE_1/Q0 SLICE_86/C0 (696:773:850)(696:773:850)) (INTERCONNECT SLICE_2/FCO SLICE_1/FCI (0:0:0)(0:0:0)) (INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (530:591:652)(530:591:652)) - (INTERCONNECT SLICE_2/Q1 SLICE_81/B1 (1309:1440:1571)(1309:1440:1571)) - (INTERCONNECT SLICE_2/Q1 SLICE_81/B0 (1309:1440:1571)(1309:1440:1571)) - (INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (545:606:667)(545:606:667)) - (INTERCONNECT SLICE_2/Q0 SLICE_74/A1 (1271:1394:1518)(1271:1394:1518)) - (INTERCONNECT SLICE_2/Q0 SLICE_81/C1 (1118:1249:1380)(1118:1249:1380)) + (INTERCONNECT SLICE_2/Q1 SLICE_86/A1 (856:956:1056)(856:956:1056)) + (INTERCONNECT SLICE_2/Q1 SLICE_86/A0 (856:956:1056)(856:956:1056)) + (INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (530:591:652)(530:591:652)) + (INTERCONNECT SLICE_2/Q0 SLICE_86/D1 (588:652:716)(588:652:716)) + (INTERCONNECT SLICE_2/Q0 SLICE_86/D0 (588:652:716)(588:652:716)) (INTERCONNECT SLICE_3/FCO SLICE_2/FCI (0:0:0)(0:0:0)) (INTERCONNECT SLICE_3/Q1 SLICE_3/A1 (530:591:652)(530:591:652)) - (INTERCONNECT SLICE_3/Q1 SLICE_81/D1 (956:1070:1185)(956:1070:1185)) - (INTERCONNECT SLICE_3/Q1 SLICE_81/D0 (956:1070:1185)(956:1070:1185)) + (INTERCONNECT SLICE_3/Q1 SLICE_67/A0 (1270:1395:1520)(1270:1395:1520)) + (INTERCONNECT SLICE_3/Q1 SLICE_69/A1 (1270:1395:1520)(1270:1395:1520)) + (INTERCONNECT SLICE_3/Q1 SLICE_80/A0 (1270:1395:1520)(1270:1395:1520)) (INTERCONNECT SLICE_3/Q0 SLICE_3/A0 (530:591:652)(530:591:652)) - (INTERCONNECT SLICE_3/Q0 SLICE_72/A1 (1663:1816:1970)(1663:1816:1970)) - (INTERCONNECT SLICE_3/Q0 SLICE_81/A0 (1260:1384:1509)(1260:1384:1509)) + (INTERCONNECT SLICE_3/Q0 SLICE_86/C1 (1564:1717:1870)(1564:1717:1870)) + (INTERCONNECT SLICE_3/Q0 SLICE_86/B0 (1724:1896:2069)(1724:1896:2069)) (INTERCONNECT SLICE_4/FCO SLICE_3/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/Q1 SLICE_4/A1 (530:591:652)(530:591:652)) - (INTERCONNECT SLICE_4/Q1 SLICE_64/D1 (1001:1094:1188)(1001:1094:1188)) - (INTERCONNECT SLICE_4/Q1 SLICE_72/B0 (1733:1895:2058)(1733:1895:2058)) - (INTERCONNECT SLICE_4/Q1 SLICE_74/B1 (1733:1895:2058)(1733:1895:2058)) - (INTERCONNECT SLICE_4/Q1 SLICE_84/B1 (1316:1448:1580)(1316:1448:1580)) - (INTERCONNECT SLICE_4/Q1 SLICE_87/B0 (1733:1895:2058)(1733:1895:2058)) - (INTERCONNECT SLICE_4/Q0 SLICE_4/A0 (530:591:652)(530:591:652)) - (INTERCONNECT SLICE_4/Q0 SLICE_64/A1 (1245:1393:1541)(1245:1393:1541)) - (INTERCONNECT SLICE_4/Q0 SLICE_74/A0 (1648:1825:2002)(1648:1825:2002)) - (INTERCONNECT SLICE_4/Q0 SLICE_84/C1 (1131:1266:1402)(1131:1266:1402)) - (INTERCONNECT SLICE_4/Q0 SLICE_84/C0 (1131:1266:1402)(1131:1266:1402)) + (INTERCONNECT SLICE_4/Q1 SLICE_4/A1 (560:621:682)(560:621:682)) + (INTERCONNECT SLICE_4/Q1 SLICE_56/C1 (1675:1819:1964)(1675:1819:1964)) + (INTERCONNECT SLICE_4/Q1 SLICE_64/A1 (1176:1306:1436)(1176:1306:1436)) + (INTERCONNECT SLICE_4/Q1 SLICE_69/C0 (1675:1819:1964)(1675:1819:1964)) + (INTERCONNECT SLICE_4/Q1 SLICE_80/A1 (1486:1654:1823)(1486:1654:1823)) + (INTERCONNECT SLICE_4/Q1 SLICE_94/B1 (929:1030:1132)(929:1030:1132)) + (INTERCONNECT SLICE_4/Q0 SLICE_4/A0 (560:621:682)(560:621:682)) + (INTERCONNECT SLICE_4/Q0 SLICE_64/D1 (985:1097:1210)(985:1097:1210)) + (INTERCONNECT SLICE_4/Q0 SLICE_80/D0 (985:1097:1210)(985:1097:1210)) + (INTERCONNECT SLICE_4/Q0 SLICE_89/C1 (769:851:933)(769:851:933)) + (INTERCONNECT SLICE_4/Q0 SLICE_94/C1 (1583:1734:1886)(1583:1734:1886)) (INTERCONNECT SLICE_5/FCO SLICE_4/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_5/Q1 SLICE_5/A1 (545:606:667)(545:606:667)) - (INTERCONNECT SLICE_5/Q1 SLICE_56/C0 (1652:1794:1936)(1652:1794:1936)) - (INTERCONNECT SLICE_5/Q1 SLICE_87/C0 (750:837:924)(750:837:924)) + (INTERCONNECT SLICE_5/Q1 SLICE_5/A1 (530:591:652)(530:591:652)) + (INTERCONNECT SLICE_5/Q1 SLICE_89/B1 (903:1005:1108)(903:1005:1108)) + (INTERCONNECT SLICE_5/Q1 SLICE_89/B0 (903:1005:1108)(903:1005:1108)) (INTERCONNECT SLICE_5/Q0 SLICE_5/A0 (530:591:652)(530:591:652)) - (INTERCONNECT SLICE_5/Q0 SLICE_58/A1 (857:952:1048)(857:952:1048)) - (INTERCONNECT SLICE_5/Q0 SLICE_84/A1 (1663:1816:1970)(1663:1816:1970)) + (INTERCONNECT SLICE_5/Q0 SLICE_58/C1 (1146:1258:1370)(1146:1258:1370)) + (INTERCONNECT SLICE_5/Q0 SLICE_94/A1 (857:952:1048)(857:952:1048)) (INTERCONNECT SLICE_6/FCO SLICE_5/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_6/Q1 SLICE_6/A1 (545:606:667)(545:606:667)) - (INTERCONNECT SLICE_6/Q1 SLICE_56/B0 (1844:2015:2186)(1844:2015:2186)) - (INTERCONNECT SLICE_6/Q1 SLICE_84/D0 (599:662:725)(599:662:725)) - (INTERCONNECT SLICE_6/Q0 SLICE_6/A0 (545:606:667)(545:606:667)) - (INTERCONNECT SLICE_6/Q0 SLICE_84/D1 (595:663:731)(595:663:731)) - (INTERCONNECT SLICE_6/Q0 SLICE_84/A0 (864:963:1063)(864:963:1063)) + (INTERCONNECT SLICE_6/Q1 SLICE_6/A1 (530:591:652)(530:591:652)) + (INTERCONNECT SLICE_6/Q1 SLICE_89/D1 (994:1086:1179)(994:1086:1179)) + (INTERCONNECT SLICE_6/Q1 SLICE_89/D0 (994:1086:1179)(994:1086:1179)) + (INTERCONNECT SLICE_6/Q0 SLICE_6/A0 (530:591:652)(530:591:652)) + (INTERCONNECT SLICE_6/Q0 SLICE_94/D1 (994:1086:1179)(994:1086:1179)) + (INTERCONNECT SLICE_6/Q0 SLICE_94/D0 (994:1086:1179)(994:1086:1179)) (INTERCONNECT SLICE_7/FCO SLICE_6/FCI (0:0:0)(0:0:0)) (INTERCONNECT SLICE_7/Q1 SLICE_7/A1 (545:606:667)(545:606:667)) - (INTERCONNECT SLICE_7/Q1 SLICE_56/D0 (1497:1620:1743)(1497:1620:1743)) - (INTERCONNECT SLICE_7/Q1 SLICE_68/D1 (603:667:731)(603:667:731)) - (INTERCONNECT SLICE_7/Q1 SLICE_69/B1 (918:1020:1123)(918:1020:1123)) - (INTERCONNECT SLICE_7/Q0 SLICE_7/A0 (545:606:667)(545:606:667)) - (INTERCONNECT SLICE_7/Q0 SLICE_72/D0 (1002:1094:1186)(1002:1094:1186)) - (INTERCONNECT SLICE_7/Q0 SLICE_87/A0 (1232:1375:1519)(1232:1375:1519)) + (INTERCONNECT SLICE_7/Q1 SLICE_71/C1 (1257:1372:1488)(1257:1372:1488)) + (INTERCONNECT SLICE_7/Q1 SLICE_72/B1 (1417:1552:1687)(1417:1552:1687)) + (INTERCONNECT SLICE_7/Q1 SLICE_89/A0 (1271:1394:1518)(1271:1394:1518)) + (INTERCONNECT SLICE_7/Q0 SLICE_7/A0 (530:591:652)(530:591:652)) + (INTERCONNECT SLICE_7/Q0 SLICE_56/A1 (1794:1959:2125)(1794:1959:2125)) + (INTERCONNECT SLICE_7/Q0 SLICE_69/D0 (1928:2091:2254)(1928:2091:2254)) (INTERCONNECT SLICE_8/FCO SLICE_7/FCI (0:0:0)(0:0:0)) (INTERCONNECT SLICE_8/Q1 SLICE_8/A1 (530:591:652)(530:591:652)) - (INTERCONNECT SLICE_8/Q1 SLICE_68/A1 (1675:1841:2008)(1675:1841:2008)) - (INTERCONNECT SLICE_8/Q1 SLICE_69/C1 (1561:1715:1869)(1561:1715:1869)) + (INTERCONNECT SLICE_8/Q1 SLICE_94/A0 (1217:1360:1504)(1217:1360:1504)) (INTERCONNECT SLICE_8/Q0 SLICE_8/A0 (530:591:652)(530:591:652)) - (INTERCONNECT SLICE_8/Q0 SLICE_68/C1 (743:826:909)(743:826:909)) - (INTERCONNECT SLICE_8/Q0 SLICE_69/A1 (857:952:1048)(857:952:1048)) - (INTERCONNECT SLICE_78/F0 SLICE_9/D1 (568:631:694)(568:631:694)) - (INTERCONNECT SLICE_85/F1 SLICE_9/C1 (1087:1218:1349)(1087:1218:1349)) - (INTERCONNECT MAin\[0\]_I/PADDI SLICE_9/B1 (1843:2032:2222)(1843:2032:2222)) - (INTERCONNECT MAin\[0\]_I/PADDI SLICE_66/M0 (1203:1325:1448)(1203:1325:1448)) - (INTERCONNECT MAin\[0\]_I/PADDI SLICE_67/C0 (1683:1853:2023)(1683:1853:2023)) - (INTERCONNECT MAin\[0\]_I/PADDI SLICE_76/D0 (1528:1679:1830)(1528:1679:1830)) - (INTERCONNECT MAin\[0\]_I/PADDI SLICE_90/D1 (2744:2982:3221)(2744:2982:3221)) - (INTERCONNECT MAin\[0\]_I/PADDI SLICE_90/D0 (2744:2982:3221)(2744:2982:3221)) - (INTERCONNECT SLICE_70/F1 SLICE_9/A1 (882:978:1075)(882:978:1075)) - (INTERCONNECT SLICE_70/F1 SLICE_14/A1 (882:978:1075)(882:978:1075)) - (INTERCONNECT SLICE_70/F1 SLICE_14/A0 (882:978:1075)(882:978:1075)) - (INTERCONNECT SLICE_70/F1 SLICE_67/A0 (882:978:1075)(882:978:1075)) - (INTERCONNECT SLICE_70/F1 SLICE_70/C0 (431:479:528)(431:479:528)) - (INTERCONNECT SLICE_70/F1 SLICE_90/B1 (1317:1447:1578)(1317:1447:1578)) + (INTERCONNECT SLICE_8/Q0 SLICE_94/B0 (1302:1432:1563)(1302:1432:1563)) + (INTERCONNECT SLICE_77/F0 SLICE_9/D1 (261:290:320)(261:290:320)) + (INTERCONNECT SLICE_77/F0 SLICE_14/D0 (998:1091:1185)(998:1091:1185)) + (INTERCONNECT SLICE_77/F0 SLICE_70/A0 (857:952:1048)(857:952:1048)) + (INTERCONNECT SLICE_77/F0 SLICE_74/D0 (998:1091:1185)(998:1091:1185)) + (INTERCONNECT SLICE_76/F0 SLICE_9/A1 (1277:1403:1529)(1277:1403:1529)) + (INTERCONNECT SLICE_76/F0 SLICE_14/A0 (1680:1835:1990)(1680:1835:1990)) + (INTERCONNECT SLICE_76/F0 SLICE_20/A1 (1277:1403:1529)(1277:1403:1529)) + (INTERCONNECT SLICE_76/F0 SLICE_70/D0 (261:290:320)(261:290:320)) + (INTERCONNECT SLICE_76/F0 SLICE_75/A0 (1277:1403:1529)(1277:1403:1529)) (INTERCONNECT SLICE_9/Q0 SLICE_9/D0 (517:575:634)(517:575:634)) (INTERCONNECT SLICE_9/Q0 SLICE_20/B1 (832:929:1026)(832:929:1026)) - (INTERCONNECT SLICE_9/F1 SLICE_9/C0 (416:464:513)(416:464:513)) - (INTERCONNECT SLICE_9/F1 SLICE_20/D0 (261:290:320)(261:290:320)) - (INTERCONNECT SLICE_14/F1 SLICE_9/B0 (591:659:727)(591:659:727)) - (INTERCONNECT SLICE_14/F1 SLICE_14/C0 (431:479:528)(431:479:528)) - (INTERCONNECT SLICE_14/F1 SLICE_20/M0 (559:618:678)(559:618:678)) - (INTERCONNECT SLICE_70/F0 SLICE_9/A0 (837:931:1026)(837:931:1026)) + (INTERCONNECT SLICE_75/F0 SLICE_9/C0 (681:758:835)(681:758:835)) + (INTERCONNECT SLICE_75/F0 SLICE_14/B1 (903:1005:1108)(903:1005:1108)) + (INTERCONNECT SLICE_75/F0 SLICE_14/B0 (903:1005:1108)(903:1005:1108)) + (INTERCONNECT SLICE_9/F1 SLICE_9/B0 (560:628:696)(560:628:696)) + (INTERCONNECT SLICE_74/F0 SLICE_9/A0 (849:948:1048)(849:948:1048)) + (INTERCONNECT SLICE_74/F0 SLICE_20/D0 (584:647:710)(584:647:710)) (INTERCONNECT SLICE_9/F0 SLICE_9/DI0 (0:0:0)(0:0:0)) (INTERCONNECT PHI2_I/PADDI SLICE_9/CLK (2731:3325:3919)(2731:3325:3919)) (INTERCONNECT PHI2_I/PADDI SLICE_14/CLK (2731:3325:3919)(2731:3325:3919)) @@ -2414,505 +2510,561 @@ (INTERCONNECT PHI2_I/PADDI SLICE_22/CLK (2731:3325:3919)(2731:3325:3919)) (INTERCONNECT PHI2_I/PADDI SLICE_26/CLK (2731:3325:3919)(2731:3325:3919)) (INTERCONNECT PHI2_I/PADDI SLICE_39/CLK (2731:3325:3919)(2731:3325:3919)) - (INTERCONNECT PHI2_I/PADDI SLICE_42/M1 (2182:2416:2650)(2182:2416:2650)) + (INTERCONNECT PHI2_I/PADDI SLICE_42/M1 (2586:2855:3124)(2586:2855:3124)) (INTERCONNECT PHI2_I/PADDI SLICE_57/CLK (2731:3325:3919)(2731:3325:3919)) - (INTERCONNECT PHI2_I/PADDI SLICE_70/CLK (2731:3325:3919)(2731:3325:3919)) - (INTERCONNECT PHI2_I/PADDI SLICE_71/CLK (2731:3325:3919)(2731:3325:3919)) - (INTERCONNECT PHI2_I/PADDI SLICE_73/CLK (2731:3325:3919)(2731:3325:3919)) - (INTERCONNECT PHI2_I/PADDI SLICE_74/CLK (2731:3325:3919)(2731:3325:3919)) + (INTERCONNECT PHI2_I/PADDI SLICE_75/CLK (2731:3325:3919)(2731:3325:3919)) (INTERCONNECT PHI2_I/PADDI SLICE_76/CLK (2731:3325:3919)(2731:3325:3919)) - (INTERCONNECT PHI2_I/PADDI SLICE_77/CLK (2731:3325:3919)(2731:3325:3919)) - (INTERCONNECT SLICE_77/F0 SLICE_14/D1 (564:632:700)(564:632:700)) - (INTERCONNECT SLICE_76/F0 SLICE_14/C1 (1530:1676:1822)(1530:1676:1822)) - (INTERCONNECT MAin\[1\]_I/PADDI SLICE_14/D0 (1225:1351:1478)(1225:1351:1478)) - (INTERCONNECT MAin\[1\]_I/PADDI SLICE_66/M1 (1525:1685:1846)(1525:1685:1846)) - (INTERCONNECT MAin\[1\]_I/PADDI SLICE_67/B0 (1540:1705:1870)(1540:1705:1870)) - (INTERCONNECT MAin\[1\]_I/PADDI SLICE_70/A0 (1879:2062:2246)(1879:2062:2246)) - (INTERCONNECT MAin\[1\]_I/PADDI SLICE_77/C0 (1373:1516:1660)(1373:1516:1660)) - (INTERCONNECT MAin\[1\]_I/PADDI SLICE_78/D0 (1225:1351:1478)(1225:1351:1478)) - (INTERCONNECT MAin\[1\]_I/PADDI SLICE_90/C1 (1784:1959:2134)(1784:1959:2134)) - (INTERCONNECT MAin\[1\]_I/PADDI SLICE_91/B0 (1541:1706:1872)(1541:1706:1872)) - (INTERCONNECT SLICE_14/Q0 SLICE_14/B0 (832:929:1026)(832:929:1026)) - (INTERCONNECT SLICE_14/Q0 SLICE_20/B0 (832:929:1026)(832:929:1026)) + (INTERCONNECT PHI2_I/PADDI SLICE_79/CLK (2731:3325:3919)(2731:3325:3919)) + (INTERCONNECT PHI2_I/PADDI SLICE_85/CLK (2731:3325:3919)(2731:3325:3919)) + (INTERCONNECT PHI2_I/PADDI SLICE_88/CLK (2731:3325:3919)(2731:3325:3919)) + (INTERCONNECT PHI2_I/PADDI SLICE_93/CLK (2731:3325:3919)(2731:3325:3919)) + (INTERCONNECT SLICE_14/Q0 SLICE_14/D1 (526:584:642)(526:584:642)) + (INTERCONNECT SLICE_14/Q0 SLICE_14/C0 (681:758:835)(681:758:835)) + (INTERCONNECT SLICE_70/F0 SLICE_14/C1 (719:806:893)(719:806:893)) + (INTERCONNECT SLICE_78/F0 SLICE_14/A1 (779:868:958)(779:868:958)) (INTERCONNECT SLICE_14/F0 SLICE_14/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_51/Q1 SLICE_19/D1 (956:1070:1185)(956:1070:1185)) - (INTERCONNECT SLICE_51/Q1 SLICE_19/LSR (2110:2331:2552)(2110:2331:2552)) - (INTERCONNECT SLICE_51/Q1 SLICE_42/C1 (2657:2925:3193)(2657:2925:3193)) - (INTERCONNECT SLICE_51/Q1 SLICE_42/A0 (2482:2728:2974)(2482:2728:2974)) - (INTERCONNECT SLICE_51/Q1 SLICE_43/C1 (2365:2598:2832)(2365:2598:2832)) - (INTERCONNECT SLICE_51/Q1 SLICE_50/LSR (2110:2331:2552)(2110:2331:2552)) - (INTERCONNECT SLICE_51/Q1 SLICE_52/M1 (2620:2864:3109)(2620:2864:3109)) - (INTERCONNECT SLICE_51/Q1 SLICE_61/A1 (2054:2267:2480)(2054:2267:2480)) - (INTERCONNECT SLICE_51/Q1 SLICE_62/D1 (1793:1977:2161)(1793:1977:2161)) - (INTERCONNECT SLICE_51/Q1 nRWE_RNO_1\/SLICE_65/D1 (2210:2424:2639)(2210:2424:2639)) - (INTERCONNECT SLICE_51/Q1 SLICE_73/B1 (895:1001:1108)(895:1001:1108)) - (INTERCONNECT SLICE_50/Q0 SLICE_19/C1 (763:846:930)(763:846:930)) - (INTERCONNECT SLICE_50/Q0 SLICE_19/C0 (763:846:930)(763:846:930)) - (INTERCONNECT SLICE_50/Q0 SLICE_41/C1 (1581:1730:1879)(1581:1730:1879)) - (INTERCONNECT SLICE_50/Q0 SLICE_50/B1 (1769:1942:2115)(1769:1942:2115)) - (INTERCONNECT SLICE_50/Q0 SLICE_50/A0 (545:606:667)(545:606:667)) - (INTERCONNECT SLICE_50/Q0 SLICE_59/C1 (2019:2202:2385)(2019:2202:2385)) - (INTERCONNECT SLICE_50/Q0 SLICE_59/C0 (2019:2202:2385)(2019:2202:2385)) - (INTERCONNECT SLICE_50/Q0 SLICE_63/D0 (1454:1588:1723)(1454:1588:1723)) - (INTERCONNECT SLICE_50/Q0 nRWE_RNO_1\/SLICE_65/C1 (757:844:932)(757:844:932)) - (INTERCONNECT SLICE_50/Q0 nRWE_RNO_1\/SLICE_65/C0 (757:844:932)(757:844:932)) - (INTERCONNECT SLICE_50/Q0 SLICE_73/C1 (2026:2210:2394)(2026:2210:2394)) - (INTERCONNECT SLICE_50/Q0 SLICE_79/C0 (2026:2210:2394)(2026:2210:2394)) - (INTERCONNECT SLICE_50/Q0 SLICE_94/C0 (2026:2210:2394)(2026:2210:2394)) - (INTERCONNECT SLICE_19/Q0 SLICE_19/B1 (878:975:1072)(878:975:1072)) - (INTERCONNECT SLICE_19/Q0 SLICE_19/A0 (560:621:682)(560:621:682)) - (INTERCONNECT SLICE_19/Q0 SLICE_41/B1 (938:1041:1144)(938:1041:1144)) - (INTERCONNECT SLICE_19/Q0 SLICE_50/C1 (778:861:945)(778:861:945)) - (INTERCONNECT SLICE_19/Q0 SLICE_50/C0 (778:861:945)(778:861:945)) - (INTERCONNECT SLICE_19/Q0 SLICE_60/C1 (1181:1293:1406)(1181:1293:1406)) - (INTERCONNECT SLICE_19/Q0 SLICE_63/A0 (892:988:1084)(892:988:1084)) - (INTERCONNECT SLICE_19/Q0 nRWE_RNO_1\/SLICE_65/B1 (1362:1496:1631)(1362:1496:1631)) - (INTERCONNECT SLICE_19/Q0 nRWE_RNO_1\/SLICE_65/B0 (1362:1496:1631)(1362:1496:1631)) - (INTERCONNECT SLICE_19/Q0 SLICE_73/A1 (1316:1443:1571)(1316:1443:1571)) - (INTERCONNECT SLICE_19/Q0 SLICE_79/D0 (1047:1143:1239)(1047:1143:1239)) - (INTERCONNECT SLICE_19/Q0 SLICE_80/C0 (718:795:873)(718:795:873)) - (INTERCONNECT SLICE_31/Q0 SLICE_19/A1 (1286:1409:1533)(1286:1409:1533)) - (INTERCONNECT SLICE_31/Q0 SLICE_31/A1 (825:914:1004)(825:914:1004)) - (INTERCONNECT SLICE_31/Q0 SLICE_31/A0 (560:621:682)(560:621:682)) - (INTERCONNECT SLICE_31/Q0 SLICE_83/B1 (1424:1556:1689)(1424:1556:1689)) - (INTERCONNECT SLICE_19/F0 SLICE_19/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_19/F1 SLICE_43/A0 (849:948:1048)(849:948:1048)) - (INTERCONNECT SLICE_19/F1 SLICE_44/B1 (841:937:1034)(841:937:1034)) - (INTERCONNECT SLICE_20/Q0 SLICE_20/A1 (810:899:989)(810:899:989)) - (INTERCONNECT SLICE_20/Q0 SLICE_20/A0 (545:606:667)(545:606:667)) - (INTERCONNECT SLICE_20/Q0 SLICE_67/D0 (541:599:657)(541:599:657)) - (INTERCONNECT SLICE_90/F1 SLICE_20/C0 (1218:1331:1444)(1218:1331:1444)) - (INTERCONNECT SLICE_20/OFX0 SLICE_20/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_75/F1 SLICE_21/D1 (321:350:380)(321:350:380)) - (INTERCONNECT SLICE_75/F1 SLICE_26/D1 (640:708:776)(640:708:776)) - (INTERCONNECT SLICE_75/F1 SLICE_67/D1 (1047:1139:1231)(1047:1139:1231)) - (INTERCONNECT SLICE_75/F1 SLICE_75/C0 (476:524:573)(476:524:573)) - (INTERCONNECT SLICE_75/F1 SLICE_82/C1 (476:524:573)(476:524:573)) - (INTERCONNECT SLICE_75/F1 SLICE_82/B0 (901:997:1094)(901:997:1094)) - (INTERCONNECT Din\[5\]_I/PADDI SLICE_21/B1 (1546:1711:1877)(1546:1711:1877)) - (INTERCONNECT Din\[5\]_I/PADDI SLICE_55/M1 (2468:2685:2903)(2468:2685:2903)) - (INTERCONNECT Din\[5\]_I/PADDI SLICE_67/B1 (1949:2143:2338)(1949:2143:2338)) - (INTERCONNECT Din\[5\]_I/PADDI SLICE_75/B0 (2795:3059:3324)(2795:3059:3324)) - (INTERCONNECT Din\[5\]_I/PADDI SLICE_76/B1 (2795:3059:3324)(2795:3059:3324)) - (INTERCONNECT Din\[5\]_I/PADDI SLICE_76/M1 (1962:2156:2351)(1962:2156:2351)) - (INTERCONNECT Din\[5\]_I/PADDI SLICE_78/B1 (2795:3059:3324)(2795:3059:3324)) - (INTERCONNECT Din\[5\]_I/PADDI SLICE_82/A1 (1500:1658:1817)(1500:1658:1817)) - (INTERCONNECT Din\[5\]_I/PADDI SLICE_82/A0 (1500:1658:1817)(1500:1658:1817)) - (INTERCONNECT Din\[5\]_I/PADDI SLICE_85/D0 (1944:2137:2330)(1944:2137:2330)) - (INTERCONNECT Din\[3\]_I/PADDI SLICE_21/A1 (1398:1552:1707)(1398:1552:1707)) - (INTERCONNECT Din\[3\]_I/PADDI SLICE_57/A1 (988:1113:1238)(988:1113:1238)) - (INTERCONNECT Din\[3\]_I/PADDI SLICE_67/C1 (1556:1731:1906)(1556:1731:1906)) - (INTERCONNECT Din\[3\]_I/PADDI SLICE_71/M1 (712:804:897)(712:804:897)) - (INTERCONNECT Din\[3\]_I/PADDI SLICE_76/A0 (988:1113:1238)(988:1113:1238)) - (INTERCONNECT Din\[3\]_I/PADDI SLICE_78/D1 (709:801:894)(709:801:894)) - (INTERCONNECT Din\[3\]_I/PADDI SLICE_82/D1 (1418:1575:1733)(1418:1575:1733)) - (INTERCONNECT Din\[3\]_I/PADDI SLICE_82/C0 (1277:1418:1560)(1277:1418:1560)) - (INTERCONNECT Din\[3\]_I/PADDI SLICE_85/M1 (712:804:897)(712:804:897)) - (INTERCONNECT SLICE_75/F0 SLICE_21/D0 (245:274:304)(245:274:304)) - (INTERCONNECT SLICE_21/F1 SLICE_21/C0 (416:464:513)(416:464:513)) - (INTERCONNECT SLICE_21/F1 SLICE_26/A0 (853:947:1042)(853:947:1042)) - (INTERCONNECT SLICE_82/F1 SLICE_21/B0 (560:628:696)(560:628:696)) - (INTERCONNECT SLICE_33/Q0 SLICE_21/A0 (1514:1694:1875)(1514:1694:1875)) - (INTERCONNECT SLICE_33/Q0 SLICE_33/C1 (681:758:835)(681:758:835)) - (INTERCONNECT SLICE_33/Q0 SLICE_57/B0 (1674:1856:2038)(1674:1856:2038)) + (INTERCONNECT SLICE_14/F1 SLICE_20/A0 (837:931:1026)(837:931:1026)) + (INTERCONNECT SLICE_75/F1 SLICE_20/D1 (261:290:320)(261:290:320)) + (INTERCONNECT SLICE_75/F1 SLICE_75/C0 (416:464:513)(416:464:513)) + (INTERCONNECT SLICE_87/F0 SLICE_20/C1 (735:822:909)(735:822:909)) + (INTERCONNECT SLICE_87/F0 SLICE_75/D0 (580:648:716)(580:648:716)) + (INTERCONNECT SLICE_20/F1 SLICE_20/C0 (400:448:497)(400:448:497)) + (INTERCONNECT SLICE_20/Q0 SLICE_20/B0 (841:937:1034)(841:937:1034)) + (INTERCONNECT SLICE_20/Q0 SLICE_73/D0 (526:584:642)(526:584:642)) + (INTERCONNECT SLICE_20/F0 SLICE_20/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_21/D1 (1115:1236:1357)(1115:1236:1357)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_57/D0 (1942:2123:2304)(1942:2123:2304)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_75/D1 (1942:2123:2304)(1942:2123:2304)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_76/M1 (1012:1139:1267)(1012:1139:1267)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_84/M1 (1832:2018:2205)(1832:2018:2205)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_85/M0 (1111:1231:1352)(1111:1231:1352)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_88/A1 (2614:2855:3097)(2614:2855:3097)) + (INTERCONNECT SLICE_87/F1 SLICE_21/C1 (726:813:901)(726:813:901)) + (INTERCONNECT SLICE_87/F1 SLICE_26/A1 (840:940:1040)(840:940:1040)) + (INTERCONNECT SLICE_88/F0 SLICE_21/B1 (841:937:1034)(841:937:1034)) + (INTERCONNECT SLICE_88/F0 SLICE_26/B1 (576:644:712)(576:644:712)) + (INTERCONNECT SLICE_21/Q0 SLICE_21/A1 (795:884:974)(795:884:974)) + (INTERCONNECT SLICE_21/Q0 SLICE_33/D0 (584:647:710)(584:647:710)) + (INTERCONNECT SLICE_85/F0 SLICE_21/D0 (526:584:642)(526:584:642)) + (INTERCONNECT SLICE_85/F0 SLICE_26/A0 (530:591:652)(530:591:652)) + (INTERCONNECT SLICE_21/F1 SLICE_21/C0 (400:448:497)(400:448:497)) + (INTERCONNECT SLICE_33/Q0 SLICE_21/B0 (903:1005:1108)(903:1005:1108)) + (INTERCONNECT SLICE_33/Q0 SLICE_33/B1 (841:937:1034)(841:937:1034)) + (INTERCONNECT SLICE_33/Q0 SLICE_57/A0 (1260:1384:1509)(1260:1384:1509)) (INTERCONNECT SLICE_21/F0 SLICE_21/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_67/F0 SLICE_21/CE (1285:1433:1581)(1285:1433:1581)) - (INTERCONNECT SLICE_67/F0 SLICE_26/CE (921:1020:1119)(921:1020:1119)) - (INTERCONNECT SLICE_67/F0 SLICE_57/CE (1696:1875:2055)(1696:1875:2055)) - (INTERCONNECT SLICE_67/F0 SLICE_67/A1 (560:621:682)(560:621:682)) - (INTERCONNECT SLICE_67/F0 SLICE_82/D0 (986:1100:1215)(986:1100:1215)) - (INTERCONNECT SLICE_21/Q0 SLICE_33/A0 (1256:1379:1503)(1256:1379:1503)) - (INTERCONNECT SLICE_21/Q0 SLICE_82/B1 (841:937:1034)(841:937:1034)) - (INTERCONNECT SLICE_22/Q0 SLICE_22/D1 (541:599:657)(541:599:657)) + (INTERCONNECT SLICE_73/F0 SLICE_21/CE (1308:1438:1568)(1308:1438:1568)) + (INTERCONNECT SLICE_73/F0 SLICE_26/CE (1308:1438:1568)(1308:1438:1568)) + (INTERCONNECT SLICE_73/F0 SLICE_57/CE (1402:1531:1660)(1402:1531:1660)) + (INTERCONNECT SLICE_73/F0 SLICE_73/C1 (416:464:513)(416:464:513)) + (INTERCONNECT SLICE_73/F0 SLICE_85/D1 (998:1091:1185)(998:1091:1185)) + (INTERCONNECT SLICE_41/Q1 SLICE_22/D1 (1082:1180:1278)(1082:1180:1278)) + (INTERCONNECT SLICE_41/Q1 SLICE_43/M1 (1081:1177:1274)(1081:1177:1274)) + (INTERCONNECT SLICE_41/Q1 SLICE_52/C1 (1640:1786:1932)(1640:1786:1932)) + (INTERCONNECT SLICE_43/Q1 SLICE_22/C1 (1422:1568:1714)(1422:1568:1714)) + (INTERCONNECT SLICE_43/Q1 SLICE_52/D1 (1267:1394:1521)(1267:1394:1521)) + (INTERCONNECT SLICE_32/Q0 SLICE_22/B1 (1374:1510:1646)(1374:1510:1646)) + (INTERCONNECT SLICE_32/Q0 SLICE_32/B1 (885:983:1081)(885:983:1081)) + (INTERCONNECT SLICE_32/Q0 SLICE_32/A0 (560:621:682)(560:621:682)) + (INTERCONNECT SLICE_32/Q0 SLICE_33/C0 (1214:1330:1447)(1214:1330:1447)) + (INTERCONNECT SLICE_32/Q0 SLICE_43/C1 (1631:1778:1925)(1631:1778:1925)) + (INTERCONNECT SLICE_32/Q0 SLICE_43/C0 (1631:1778:1925)(1631:1778:1925)) + (INTERCONNECT SLICE_32/Q0 SLICE_44/D1 (1886:2043:2201)(1886:2043:2201)) + (INTERCONNECT SLICE_32/Q0 SLICE_51/B1 (943:1046:1150)(943:1046:1150)) + (INTERCONNECT SLICE_32/Q0 SLICE_52/B1 (943:1046:1150)(943:1046:1150)) + (INTERCONNECT SLICE_32/Q0 SLICE_58/A1 (1328:1457:1586)(1328:1457:1586)) + (INTERCONNECT SLICE_32/Q0 SLICE_58/A0 (1328:1457:1586)(1328:1457:1586)) + (INTERCONNECT SLICE_32/Q0 SLICE_64/C1 (1186:1299:1412)(1186:1299:1412)) + (INTERCONNECT SLICE_32/Q0 nRWE_RNO_1\/SLICE_65/D0 (1886:2043:2201)(1886:2043:2201)) + (INTERCONNECT SLICE_32/Q0 SLICE_66/C1 (1582:1722:1863)(1582:1722:1863)) + (INTERCONNECT SLICE_32/Q0 SLICE_67/D1 (570:629:689)(570:629:689)) + (INTERCONNECT SLICE_32/Q0 SLICE_67/D0 (570:629:689)(570:629:689)) + (INTERCONNECT SLICE_32/Q0 SLICE_95/B1 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SLICE_58/C0 (740:818:897)(740:818:897)) - (INTERCONNECT SLICE_32/Q0 SLICE_64/C1 (784:866:948)(784:866:948)) - (INTERCONNECT SLICE_32/Q0 nRWE_RNO_1\/SLICE_65/A0 (1746:1903:2061)(1746:1903:2061)) - (INTERCONNECT SLICE_32/Q0 SLICE_66/B1 (1777:1952:2127)(1777:1952:2127)) - (INTERCONNECT SLICE_32/Q0 SLICE_66/B0 (1777:1952:2127)(1777:1952:2127)) - (INTERCONNECT SLICE_32/Q0 SLICE_73/D1 (1477:1603:1729)(1477:1603:1729)) - (INTERCONNECT SLICE_43/Q1 SLICE_22/B1 (1302:1432:1563)(1302:1432:1563)) - (INTERCONNECT SLICE_43/Q1 SLICE_52/C1 (1103:1234:1365)(1103:1234:1365)) - (INTERCONNECT SLICE_41/Q1 SLICE_22/A1 (1260:1384:1509)(1260:1384:1509)) - (INTERCONNECT SLICE_41/Q1 SLICE_43/M1 (544:603:663)(544:603:663)) - (INTERCONNECT SLICE_41/Q1 SLICE_52/D1 (991:1084:1177)(991:1084:1177)) - (INTERCONNECT SLICE_82/F0 SLICE_22/C0 (665:742:819)(665:742:819)) + (INTERCONNECT SLICE_22/Q0 SLICE_52/A1 (1157:1286:1415)(1157:1286:1415)) + (INTERCONNECT SLICE_73/F1 SLICE_22/B0 (1286:1416:1547)(1286:1416:1547)) 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Din\[0\]_I/PADDI SLICE_76/M0 (1111:1231:1352)(1111:1231:1352)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_78/D1 (1628:1783:1939)(1628:1783:1939)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_83/C0 (2218:2429:2641)(2218:2429:2641)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_84/M0 (1960:2159:2358)(1960:2159:2358)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_87/B0 (1943:2137:2331)(1943:2137:2331)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_88/M0 (2370:2598:2827)(2370:2598:2827)) + (INTERCONNECT SLICE_26/Q0 SLICE_26/C1 (681:758:835)(681:758:835)) + (INTERCONNECT SLICE_26/Q0 SLICE_58/D0 (580:648:716)(580:648:716)) + (INTERCONNECT SLICE_58/Q0 SLICE_26/D0 (584:647:710)(584:647:710)) + (INTERCONNECT SLICE_58/Q0 SLICE_39/B0 (1706:1871:2037)(1706:1871:2037)) (INTERCONNECT SLICE_26/F1 SLICE_26/C0 (400:448:497)(400:448:497)) (INTERCONNECT SLICE_26/F0 SLICE_26/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_61/F1 SLICE_29/D1 (584:647:710)(584:647:710)) - (INTERCONNECT SLICE_61/F1 SLICE_61/B0 (576:644:712)(576:644:712)) - (INTERCONNECT SLICE_29/Q0 SLICE_29/C1 (726:803:880)(726:803:880)) - (INTERCONNECT SLICE_29/Q0 SLICE_29/D0 (571:629:687)(571:629:687)) - (INTERCONNECT SLICE_29/Q0 SLICE_30/D1 (643:708:773)(643:708:773)) - (INTERCONNECT SLICE_29/Q0 SLICE_30/D0 (643:708:773)(643:708:773)) - (INTERCONNECT SLICE_29/Q0 SLICE_31/C0 (798:882:966)(798:882:966)) - (INTERCONNECT SLICE_29/Q0 SLICE_42/D1 (1534:1657:1781)(1534:1657:1781)) - (INTERCONNECT SLICE_29/Q0 SLICE_61/D0 (932:1031:1131)(932:1031:1131)) - (INTERCONNECT SLICE_29/Q0 SLICE_83/B0 (2655:2875:3095)(2655:2875:3095)) - (INTERCONNECT SLICE_29/Q0 SLICE_94/M0 (1300:1448:1596)(1300:1448:1596)) - (INTERCONNECT SLICE_83/F1 SLICE_29/B1 (1309:1440:1571)(1309:1440:1571)) - (INTERCONNECT SLICE_83/F1 SLICE_59/A1 (1256:1379:1503)(1256:1379:1503)) - (INTERCONNECT SLICE_83/F1 SLICE_61/A0 (1263:1387:1511)(1263:1387:1511)) - (INTERCONNECT SLICE_73/F1 SLICE_29/A1 (1297:1422:1547)(1297:1422:1547)) - (INTERCONNECT SLICE_73/F1 SLICE_29/A0 (1297:1422:1547)(1297:1422:1547)) - (INTERCONNECT SLICE_73/F1 SLICE_59/D1 (1109:1203:1297)(1109:1203:1297)) - (INTERCONNECT SLICE_73/F1 SLICE_61/C0 (1062:1179:1297)(1062:1179:1297)) - (INTERCONNECT SLICE_73/F1 SLICE_73/C0 (446:494:543)(446:494:543)) - (INTERCONNECT SLICE_73/F1 SLICE_94/B1 (871:967:1064)(871:967:1064)) - (INTERCONNECT SLICE_43/Q0 SLICE_29/B0 (2198:2404:2610)(2198:2404:2610)) - (INTERCONNECT SLICE_43/Q0 SLICE_41/C0 (733:810:888)(733:810:888)) - (INTERCONNECT SLICE_43/Q0 SLICE_43/B1 (886:982:1079)(886:982:1079)) - (INTERCONNECT SLICE_43/Q0 SLICE_43/C0 (733:810:888)(733:810:888)) - (INTERCONNECT SLICE_43/Q0 SLICE_44/D1 (632:700:769)(632:700:769)) - (INTERCONNECT SLICE_43/Q0 SLICE_50/D1 (1490:1629:1769)(1490:1629:1769)) - (INTERCONNECT SLICE_43/Q0 SLICE_59/B1 (2511:2758:3006)(2511:2758:3006)) - (INTERCONNECT SLICE_43/Q0 SLICE_61/B1 (2087:2299:2511)(2087:2299:2511)) - (INTERCONNECT SLICE_43/Q0 SLICE_62/B1 (2087:2299:2511)(2087:2299:2511)) - (INTERCONNECT SLICE_43/Q0 SLICE_63/B1 (1805:1983:2161)(1805:1983:2161)) - (INTERCONNECT SLICE_43/Q0 SLICE_63/B0 (1805:1983:2161)(1805:1983:2161)) - (INTERCONNECT SLICE_43/Q0 nRWE_RNO_1\/SLICE_65/M0 (948:1049:1150)(948:1049:1150)) - (INTERCONNECT SLICE_43/Q0 SLICE_73/A0 (1199:1330:1461)(1199:1330:1461)) - (INTERCONNECT SLICE_43/Q0 SLICE_79/A1 (894:993:1093)(894:993:1093)) - (INTERCONNECT SLICE_43/Q0 SLICE_94/A1 (907:1003:1099)(907:1003:1099)) - (INTERCONNECT SLICE_43/Q0 SLICE_94/A0 (907:1003:1099)(907:1003:1099)) - (INTERCONNECT SLICE_29/F0 SLICE_29/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_29/F1 SLICE_60/B0 (825:921:1018)(825:921:1018)) - (INTERCONNECT SLICE_30/Q0 SLICE_30/B1 (885:983:1081)(885:983:1081)) - (INTERCONNECT SLICE_30/Q0 SLICE_30/A0 (560:621:682)(560:621:682)) - (INTERCONNECT SLICE_30/Q0 SLICE_31/B1 (885:983:1081)(885:983:1081)) - (INTERCONNECT SLICE_30/Q0 SLICE_31/B0 (885:983:1081)(885:983:1081)) - (INTERCONNECT SLICE_30/Q0 SLICE_42/A1 (1378:1503:1629)(1378:1503:1629)) - (INTERCONNECT SLICE_30/Q0 SLICE_83/C1 (1179:1290:1402)(1179:1290:1402)) - (INTERCONNECT SLICE_30/Q0 SLICE_83/C0 (1179:1290:1402)(1179:1290:1402)) + (INTERCONNECT SLICE_29/Q0 SLICE_29/D1 (585:644:704)(585:644:704)) + (INTERCONNECT SLICE_29/Q0 SLICE_29/A0 (575:636:697)(575:636:697)) + (INTERCONNECT SLICE_29/Q0 SLICE_30/D1 (585:644:704)(585:644:704)) + (INTERCONNECT SLICE_29/Q0 SLICE_30/D0 (585:644:704)(585:644:704)) + (INTERCONNECT SLICE_29/Q0 SLICE_31/C1 (733:810:888)(733:810:888)) + (INTERCONNECT SLICE_29/Q0 SLICE_31/C0 (733:810:888)(733:810:888)) + (INTERCONNECT SLICE_29/Q0 SLICE_38/C1 (1073:1189:1306)(1073:1189:1306)) + (INTERCONNECT SLICE_29/Q0 SLICE_61/A0 (1401:1529:1657)(1401:1529:1657)) + (INTERCONNECT SLICE_29/Q0 SLICE_92/D0 (1132:1228:1325)(1132:1228:1325)) + (INTERCONNECT SLICE_30/Q1 SLICE_29/C1 (718:795:873)(718:795:873)) (INTERCONNECT SLICE_30/Q1 SLICE_30/A1 (560:621:682)(560:621:682)) - (INTERCONNECT SLICE_30/Q1 SLICE_31/D1 (563:621:680)(563:621:680)) - (INTERCONNECT SLICE_30/Q1 SLICE_31/D0 (563:621:680)(563:621:680)) - (INTERCONNECT SLICE_30/Q1 SLICE_42/B1 (1424:1556:1689)(1424:1556:1689)) - (INTERCONNECT SLICE_30/Q1 SLICE_83/A1 (1293:1417:1541)(1293:1417:1541)) - (INTERCONNECT SLICE_30/Q1 SLICE_83/A0 (1293:1417:1541)(1293:1417:1541)) + (INTERCONNECT SLICE_30/Q1 SLICE_31/B0 (878:975:1072)(878:975:1072)) + (INTERCONNECT SLICE_30/Q1 SLICE_38/B1 (933:1035:1138)(933:1035:1138)) + (INTERCONNECT SLICE_30/Q1 SLICE_38/B0 (933:1035:1138)(933:1035:1138)) + (INTERCONNECT SLICE_30/Q1 SLICE_92/B1 (933:1035:1138)(933:1035:1138)) + (INTERCONNECT SLICE_30/Q1 SLICE_92/B0 (933:1035:1138)(933:1035:1138)) + (INTERCONNECT SLICE_30/Q0 SLICE_29/A1 (854:945:1036)(854:945:1036)) + (INTERCONNECT SLICE_30/Q0 SLICE_30/B1 (900:998:1096)(900:998:1096)) + (INTERCONNECT SLICE_30/Q0 SLICE_30/A0 (575:636:697)(575:636:697)) + (INTERCONNECT SLICE_30/Q0 SLICE_31/D0 (585:644:704)(585:644:704)) + (INTERCONNECT SLICE_30/Q0 SLICE_38/A1 (894:993:1093)(894:993:1093)) + (INTERCONNECT SLICE_30/Q0 SLICE_38/D0 (625:693:761)(625:693:761)) + (INTERCONNECT SLICE_30/Q0 SLICE_92/A1 (901:1001:1101)(901:1001:1101)) + (INTERCONNECT SLICE_30/Q0 SLICE_92/A0 (901:1001:1101)(901:1001:1101)) + (INTERCONNECT SLICE_66/F1 SLICE_29/D0 (1009:1101:1194)(1009:1101:1194)) + (INTERCONNECT SLICE_66/F1 SLICE_31/D1 (1009:1101:1194)(1009:1101:1194)) + (INTERCONNECT SLICE_66/F1 SLICE_61/D0 (603:667:731)(603:667:731)) + (INTERCONNECT SLICE_66/F1 SLICE_66/C0 (431:479:528)(431:479:528)) + (INTERCONNECT SLICE_66/F1 SLICE_101/D0 (603:667:731)(603:667:731)) + (INTERCONNECT SLICE_43/Q0 SLICE_29/C0 (1168:1303:1439)(1168:1303:1439)) + (INTERCONNECT SLICE_43/Q0 SLICE_31/B1 (1328:1483:1638)(1328:1483:1638)) + (INTERCONNECT SLICE_43/Q0 SLICE_33/D1 (1120:1215:1311)(1120:1215:1311)) + (INTERCONNECT SLICE_43/Q0 SLICE_41/A0 (839:930:1021)(839:930:1021)) + (INTERCONNECT SLICE_43/Q0 SLICE_42/C1 (1668:1831:1995)(1668:1831:1995)) + (INTERCONNECT SLICE_43/Q0 SLICE_43/A1 (839:930:1021)(839:930:1021)) + (INTERCONNECT SLICE_43/Q0 SLICE_43/A0 (560:621:682)(560:621:682)) + (INTERCONNECT SLICE_43/Q0 SLICE_44/A1 (914:1018:1122)(914:1018:1122)) + (INTERCONNECT SLICE_43/Q0 SLICE_50/C1 (1668:1831:1995)(1668:1831:1995)) + (INTERCONNECT SLICE_43/Q0 SLICE_60/D1 (1120:1215:1311)(1120:1215:1311)) + (INTERCONNECT SLICE_43/Q0 SLICE_61/B1 (2238:2450:2663)(2238:2450:2663)) + (INTERCONNECT SLICE_43/Q0 SLICE_62/A1 (839:930:1021)(839:930:1021)) + (INTERCONNECT SLICE_43/Q0 SLICE_63/C1 (800:891:983)(800:891:983)) + (INTERCONNECT SLICE_43/Q0 SLICE_63/C0 (800:891:983)(800:891:983)) + (INTERCONNECT SLICE_43/Q0 nRWE_RNO_1\/SLICE_65/M0 (1820:2000:2181)(1820:2000:2181)) + (INTERCONNECT SLICE_43/Q0 SLICE_66/D0 (1485:1625:1765)(1485:1625:1765)) + (INTERCONNECT SLICE_43/Q0 SLICE_82/B1 (1800:1978:2157)(1800:1978:2157)) + (INTERCONNECT SLICE_43/Q0 SLICE_101/B0 (2238:2450:2663)(2238:2450:2663)) + (INTERCONNECT SLICE_29/F0 SLICE_29/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q1 SLICE_29/M1 (1282:1411:1540)(1282:1411:1540)) + (INTERCONNECT SLICE_74/Q1 SLICE_82/D1 (982:1075:1169)(982:1075:1169)) + (INTERCONNECT SLICE_74/Q1 SLICE_84/A1 (1668:1823:1979)(1668:1823:1979)) + (INTERCONNECT SLICE_74/Q1 SLICE_84/A0 (1668:1823:1979)(1668:1823:1979)) + (INTERCONNECT SLICE_74/Q1 SLICE_90/B0 (1714:1876:2039)(1714:1876:2039)) + (INTERCONNECT SLICE_29/F1 SLICE_43/D0 (1074:1169:1265)(1074:1169:1265)) + (INTERCONNECT SLICE_29/F1 SLICE_44/C1 (1664:1817:1970)(1664:1817:1970)) + (INTERCONNECT SLICE_29/Q1 SLICE_63/A1 (841:936:1032)(841:936:1032)) + (INTERCONNECT SLICE_29/Q1 SLICE_82/A1 (1540:1699:1859)(1540:1699:1859)) + (INTERCONNECT SLICE_29/Q1 SLICE_84/B1 (1589:1756:1923)(1589:1756:1923)) + (INTERCONNECT SLICE_29/Q1 SLICE_84/B0 (1589:1756:1923)(1589:1756:1923)) (INTERCONNECT SLICE_30/F1 SLICE_30/DI1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_30/F0 SLICE_30/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_94/F1 SLICE_30/CE (947:1062:1178)(947:1062:1178)) - (INTERCONNECT SLICE_94/F1 SLICE_31/CE (947:1062:1178)(947:1062:1178)) - (INTERCONNECT SLICE_73/F0 SLICE_31/C1 (723:805:887)(723:805:887)) + (INTERCONNECT SLICE_101/F0 SLICE_30/CE (878:977:1077)(878:977:1077)) + (INTERCONNECT SLICE_101/F0 SLICE_31/CE (878:977:1077)(878:977:1077)) + (INTERCONNECT SLICE_31/Q0 SLICE_31/A1 (825:914:1004)(825:914:1004)) + (INTERCONNECT SLICE_31/Q0 SLICE_31/A0 (560:621:682)(560:621:682)) + (INTERCONNECT SLICE_31/Q0 SLICE_38/D1 (614:677:740)(614:677:740)) + (INTERCONNECT SLICE_31/Q0 SLICE_92/D1 (618:682:746)(618:682:746)) + (INTERCONNECT SLICE_31/Q0 SLICE_95/B0 (1625:1791:1957)(1625:1791:1957)) (INTERCONNECT SLICE_31/F0 SLICE_31/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_31/F1 SLICE_94/LSR (575:639:703)(575:639:703)) - (INTERCONNECT SLICE_56/F0 SLICE_32/D1 (1352:1480:1609)(1352:1480:1609)) - (INTERCONNECT SLICE_72/F1 SLICE_32/C1 (446:494:543)(446:494:543)) - (INTERCONNECT SLICE_72/F1 SLICE_58/D1 (291:320:350)(291:320:350)) - (INTERCONNECT SLICE_72/F1 SLICE_64/B1 (929:1030:1132)(929:1030:1132)) - (INTERCONNECT SLICE_72/F1 SLICE_72/C0 (446:494:543)(446:494:543)) - (INTERCONNECT SLICE_84/F1 SLICE_32/B1 (879:985:1092)(879:985:1092)) - (INTERCONNECT SLICE_74/F0 SLICE_32/B0 (883:984:1086)(883:984:1086)) + (INTERCONNECT SLICE_31/F1 SLICE_38/LSR (575:639:703)(575:639:703)) + (INTERCONNECT SLICE_69/F1 SLICE_32/D1 (276:305:335)(276:305:335)) + (INTERCONNECT SLICE_69/F1 SLICE_58/D1 (1006:1099:1192)(1006:1099:1192)) + (INTERCONNECT SLICE_69/F1 SLICE_64/B1 (1321:1452:1584)(1321:1452:1584)) + (INTERCONNECT SLICE_69/F1 SLICE_69/B0 (591:659:727)(591:659:727)) + (INTERCONNECT SLICE_94/F1 SLICE_32/C1 (1537:1688:1840)(1537:1688:1840)) + (INTERCONNECT SLICE_89/F0 SLICE_32/A1 (833:932:1032)(833:932:1032)) + (INTERCONNECT SLICE_80/F0 SLICE_32/D0 (245:274:304)(245:274:304)) (INTERCONNECT SLICE_32/F0 SLICE_32/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_32/F1 SLICE_87/D1 (510:568:626)(510:568:626)) - (INTERCONNECT nCRAS_I/PADDI SLICE_33/D1 (2857:3462:4068)(2857:3462:4068)) - (INTERCONNECT nCRAS_I/PADDI SLICE_44/M1 (3532:4217:4903)(3532:4217:4903)) - (INTERCONNECT nCRAS_I/PADDI SLICE_66/CLK (2293:2830:3368)(2293:2830:3368)) - (INTERCONNECT nCRAS_I/PADDI SLICE_67/CLK (2293:2830:3368)(2293:2830:3368)) - (INTERCONNECT nCRAS_I/PADDI SLICE_72/CLK (2293:2830:3368)(2293:2830:3368)) - (INTERCONNECT nCRAS_I/PADDI SLICE_78/CLK (2293:2830:3368)(2293:2830:3368)) - (INTERCONNECT nCRAS_I/PADDI SLICE_80/CLK (2293:2830:3368)(2293:2830:3368)) - (INTERCONNECT nCRAS_I/PADDI SLICE_81/CLK (2293:2830:3368)(2293:2830:3368)) - (INTERCONNECT nCRAS_I/PADDI SLICE_83/CLK (2293:2830:3368)(2293:2830:3368)) - (INTERCONNECT nCRAS_I/PADDI SLICE_88/CLK (2293:2830:3368)(2293:2830:3368)) - (INTERCONNECT SLICE_78/Q0 SLICE_33/A1 (1256:1379:1503)(1256:1379:1503)) - (INTERCONNECT SLICE_78/Q0 SLICE_41/D0 (1365:1507:1650)(1365:1507:1650)) - (INTERCONNECT SLICE_78/Q0 SLICE_60/A0 (1681:1846:2012)(1681:1846:2012)) - (INTERCONNECT SLICE_78/Q0 SLICE_63/A1 (1239:1386:1534)(1239:1386:1534)) - (INTERCONNECT SLICE_78/Q0 SLICE_79/A0 (1239:1386:1534)(1239:1386:1534)) - (INTERCONNECT UFMSDO_I/PADDI SLICE_33/D0 (702:793:885)(702:793:885)) - (INTERCONNECT UFMSDO_I/PADDI SLICE_58/D0 (1105:1225:1346)(1105:1225:1346)) + (INTERCONNECT SLICE_32/F1 SLICE_55/D0 (1374:1495:1616)(1374:1495:1616)) + (INTERCONNECT nCRAS_I/PADDI SLICE_33/C1 (3383:4051:4720)(3383:4051:4720)) + (INTERCONNECT nCRAS_I/PADDI SLICE_67/CLK (2296:2833:3371)(2296:2833:3371)) + (INTERCONNECT nCRAS_I/PADDI SLICE_69/CLK (2296:2833:3371)(2296:2833:3371)) + (INTERCONNECT nCRAS_I/PADDI SLICE_73/CLK (2296:2833:3371)(2296:2833:3371)) + (INTERCONNECT nCRAS_I/PADDI SLICE_83/CLK (2296:2833:3371)(2296:2833:3371)) + (INTERCONNECT nCRAS_I/PADDI SLICE_87/CLK (2296:2833:3371)(2296:2833:3371)) + (INTERCONNECT nCRAS_I/PADDI SLICE_89/CLK (2296:2833:3371)(2296:2833:3371)) + (INTERCONNECT nCRAS_I/PADDI SLICE_90/CLK (2296:2833:3371)(2296:2833:3371)) + (INTERCONNECT nCRAS_I/PADDI SLICE_95/M0 (1203:1325:1448)(1203:1325:1448)) + (INTERCONNECT nCRAS_I/PADDI SLICE_101/CLK (2296:2833:3371)(2296:2833:3371)) + (INTERCONNECT SLICE_87/Q0 SLICE_33/A1 (1271:1394:1518)(1271:1394:1518)) + (INTERCONNECT SLICE_87/Q0 SLICE_41/D0 (1421:1556:1691)(1421:1556:1691)) + (INTERCONNECT SLICE_87/Q0 SLICE_59/A1 (868:962:1057)(868:962:1057)) + (INTERCONNECT SLICE_87/Q0 SLICE_63/D1 (1824:1988:2152)(1824:1988:2152)) + (INTERCONNECT UFMSDO_I/PADDI SLICE_33/B0 (1419:1577:1735)(1419:1577:1735)) + (INTERCONNECT UFMSDO_I/PADDI SLICE_58/B0 (1419:1577:1735)(1419:1577:1735)) (INTERCONNECT SLICE_33/F0 SLICE_33/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_69/F0 SLICE_33/CE (939:1052:1165)(939:1052:1165)) - (INTERCONNECT SLICE_33/F1 LED_I/PADDO (646:731:817)(646:731:817)) - (INTERCONNECT SLICE_85/F0 SLICE_39/D1 (1514:1646:1779)(1514:1646:1779)) - (INTERCONNECT SLICE_85/F0 SLICE_57/D1 (526:584:642)(526:584:642)) - (INTERCONNECT SLICE_57/Q0 SLICE_39/A1 (2147:2339:2531)(2147:2339:2531)) - (INTERCONNECT SLICE_57/Q0 SLICE_39/A0 (2147:2339:2531)(2147:2339:2531)) - (INTERCONNECT Din\[6\]_I/PADDI SLICE_39/D0 (2053:2245:2437)(2053:2245:2437)) - (INTERCONNECT Din\[6\]_I/PADDI SLICE_56/M0 (3194:3483:3773)(3194:3483:3773)) - (INTERCONNECT Din\[6\]_I/PADDI SLICE_75/B1 (1519:1680:1842)(1519:1680:1842)) - (INTERCONNECT Din\[6\]_I/PADDI SLICE_77/D0 (2081:2276:2472)(2081:2276:2472)) - (INTERCONNECT Din\[6\]_I/PADDI SLICE_77/M0 (2388:2619:2851)(2388:2619:2851)) - (INTERCONNECT Din\[6\]_I/PADDI SLICE_78/B0 (2396:2630:2864)(2396:2630:2864)) - (INTERCONNECT Din\[6\]_I/PADDI SLICE_85/B0 (2799:3062:3325)(2799:3062:3325)) + (INTERCONNECT SLICE_72/F0 SLICE_33/CE (875:974:1073)(875:974:1073)) + (INTERCONNECT SLICE_33/F1 LED_I/PADDO (1532:1758:1984)(1532:1758:1984)) + (INTERCONNECT SLICE_38/F0 SLICE_38/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_38/Q0 RA\[10\]_I/PADDO (1607:1831:2056)(1607:1831:2056)) + (INTERCONNECT SLICE_38/F1 SLICE_68/A1 (1332:1457:1583)(1332:1457:1583)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_39/D1 (2042:2232:2423)(2042:2232:2423)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_56/M1 (2100:2305:2510)(2100:2305:2510)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_75/M1 (2392:2629:2867)(2392:2629:2867)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_83/C1 (2672:2926:3181)(2672:2926:3181)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_87/A1 (2786:3053:3320)(2786:3053:3320)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_87/A0 (2786:3053:3320)(2786:3053:3320)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_88/B1 (2832:3106:3380)(2832:3106:3380)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_39/B1 (2374:2604:2835)(2374:2604:2835)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_55/M0 (2366:2594:2822)(2366:2594:2822)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_74/C1 (2207:2417:2627)(2207:2417:2627)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_75/C1 (2207:2417:2627)(2207:2417:2627)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_83/A1 (3143:3433:3723)(3143:3433:3723)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_87/B1 (3478:3809:4141)(3478:3809:4141)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_93/M0 (1411:1566:1722)(1411:1566:1722)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_39/A1 (2326:2551:2776)(2326:2551:2776)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_39/A0 (2326:2551:2776)(2326:2551:2776)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_56/M0 (1954:2154:2354)(1954:2154:2354)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_74/D1 (1645:1802:1960)(1645:1802:1960)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_75/M0 (1652:1810:1969)(1652:1810:1969)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_83/B1 (1557:1724:1891)(1557:1724:1891)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_87/D1 (1242:1370:1499)(1242:1370:1499)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_87/D0 (1242:1370:1499)(1242:1370:1499)) + (INTERCONNECT SLICE_57/Q0 SLICE_39/D0 (1079:1173:1267)(1079:1173:1267)) + (INTERCONNECT SLICE_57/Q0 SLICE_57/B1 (841:937:1034)(841:937:1034)) (INTERCONNECT SLICE_39/F0 SLICE_39/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_44/Q0 SLICE_39/LSR (1313:1442:1571)(1313:1442:1571)) - (INTERCONNECT SLICE_44/Q0 SLICE_44/A0 (545:606:667)(545:606:667)) - (INTERCONNECT SLICE_44/Q0 SLICE_66/LSR (1447:1581:1716)(1447:1581:1716)) - (INTERCONNECT SLICE_44/Q0 SLICE_67/LSR (1447:1581:1716)(1447:1581:1716)) - (INTERCONNECT SLICE_44/Q0 SLICE_72/LSR (1850:2013:2177)(1850:2013:2177)) - (INTERCONNECT SLICE_44/Q0 SLICE_80/LSR (559:618:678)(559:618:678)) - (INTERCONNECT SLICE_44/Q0 SLICE_83/LSR (1842:2003:2164)(1842:2003:2164)) - (INTERCONNECT SLICE_44/Q0 SLICE_88/LSR (1447:1581:1716)(1447:1581:1716)) + (INTERCONNECT SLICE_44/Q0 SLICE_39/LSR (1285:1433:1581)(1285:1433:1581)) + (INTERCONNECT SLICE_44/Q0 SLICE_44/A0 (560:621:682)(560:621:682)) + (INTERCONNECT SLICE_44/Q0 SLICE_67/LSR (1134:1232:1331)(1134:1232:1331)) + (INTERCONNECT SLICE_44/Q0 SLICE_69/LSR (1134:1232:1331)(1134:1232:1331)) + (INTERCONNECT SLICE_44/Q0 SLICE_73/LSR (1124:1221:1319)(1124:1221:1319)) + (INTERCONNECT SLICE_44/Q0 SLICE_83/LSR (1534:1661:1788)(1534:1661:1788)) + (INTERCONNECT SLICE_44/Q0 SLICE_89/LSR (1537:1664:1792)(1537:1664:1792)) + (INTERCONNECT SLICE_44/Q0 SLICE_90/LSR (1937:2093:2249)(1937:2093:2249)) (INTERCONNECT SLICE_39/Q0 RA\[11\]_I/PADDO (646:731:817)(646:731:817)) - (INTERCONNECT SLICE_39/F1 SLICE_57/A0 (1767:1931:2095)(1767:1931:2095)) - (INTERCONNECT SLICE_75/Q1 SLICE_41/D1 (960:1076:1193)(960:1076:1193)) - (INTERCONNECT SLICE_75/Q1 SLICE_60/B1 (1967:2185:2404)(1967:2185:2404)) - (INTERCONNECT SLICE_75/Q1 SLICE_79/B1 (1275:1430:1585)(1275:1430:1585)) - (INTERCONNECT SLICE_75/Q1 SLICE_80/D1 (1370:1516:1662)(1370:1516:1662)) - (INTERCONNECT SLICE_75/Q1 SLICE_82/M0 (1780:1956:2132)(1780:1956:2132)) - (INTERCONNECT SLICE_81/Q1 SLICE_41/A1 (2097:2301:2505)(2097:2301:2505)) - (INTERCONNECT SLICE_81/Q1 SLICE_60/D1 (2924:3195:3466)(2924:3195:3466)) + (INTERCONNECT SLICE_39/F1 SLICE_73/B1 (1389:1523:1657)(1389:1523:1657)) + (INTERCONNECT SLICE_39/F1 SLICE_85/C1 (1646:1791:1936)(1646:1791:1936)) + (INTERCONNECT SLICE_39/F1 SLICE_85/C0 (1646:1791:1936)(1646:1791:1936)) + (INTERCONNECT SLICE_39/F1 SLICE_88/B0 (1806:1970:2135)(1806:1970:2135)) + (INTERCONNECT SLICE_101/Q1 SLICE_41/D1 (1267:1394:1521)(1267:1394:1521)) + (INTERCONNECT SLICE_101/Q1 SLICE_84/C1 (1946:2116:2286)(1946:2116:2286)) + (INTERCONNECT SLICE_101/Q1 SLICE_84/C0 (1946:2116:2286)(1946:2116:2286)) + (INTERCONNECT SLICE_68/Q0 SLICE_41/C1 (818:902:987)(818:902:987)) + (INTERCONNECT SLICE_68/Q0 SLICE_50/D1 (1051:1144:1237)(1051:1144:1237)) + (INTERCONNECT SLICE_68/Q0 SLICE_50/C0 (1516:1665:1814)(1516:1665:1814)) + (INTERCONNECT SLICE_68/Q0 SLICE_56/A0 (932:1029:1126)(932:1029:1126)) + (INTERCONNECT SLICE_68/Q0 SLICE_63/D0 (1008:1120:1232)(1008:1120:1232)) + (INTERCONNECT SLICE_68/Q0 nRWE_RNO_1\/SLICE_65/C1 (1516:1665:1814)(1516:1665:1814)) + (INTERCONNECT SLICE_68/Q0 nRWE_RNO_1\/SLICE_65/C0 (1516:1665:1814)(1516:1665:1814)) + (INTERCONNECT SLICE_68/Q0 SLICE_66/D1 (640:708:776)(640:708:776)) + (INTERCONNECT SLICE_68/Q0 SLICE_68/D1 (586:644:702)(586:644:702)) + (INTERCONNECT SLICE_68/Q0 SLICE_68/A0 (590:651:712)(590:651:712)) + (INTERCONNECT SLICE_68/Q0 SLICE_82/D0 (663:728:794)(663:728:794)) + (INTERCONNECT SLICE_68/Q0 SLICE_84/D1 (1087:1184:1281)(1087:1184:1281)) + (INTERCONNECT SLICE_68/Q0 SLICE_84/D0 (1087:1184:1281)(1087:1184:1281)) + (INTERCONNECT SLICE_68/Q0 SLICE_90/A1 (1356:1484:1613)(1356:1484:1613)) + (INTERCONNECT SLICE_68/Q0 SLICE_90/A0 (1356:1484:1613)(1356:1484:1613)) + (INTERCONNECT SLICE_68/Q0 SLICE_95/A0 (917:1012:1108)(917:1012:1108)) + (INTERCONNECT SLICE_50/Q0 SLICE_41/B1 (948:1050:1153)(948:1050:1153)) + (INTERCONNECT SLICE_50/Q0 SLICE_50/A1 (854:945:1036)(854:945:1036)) + (INTERCONNECT SLICE_50/Q0 SLICE_50/A0 (575:636:697)(575:636:697)) + (INTERCONNECT SLICE_50/Q0 SLICE_59/B1 (1661:1829:1998)(1661:1829:1998)) + (INTERCONNECT SLICE_50/Q0 SLICE_59/D0 (1057:1152:1248)(1057:1152:1248)) + (INTERCONNECT SLICE_50/Q0 SLICE_60/B1 (1373:1506:1640)(1373:1506:1640)) + (INTERCONNECT SLICE_50/Q0 SLICE_63/B0 (900:998:1096)(900:998:1096)) + (INTERCONNECT SLICE_50/Q0 nRWE_RNO_1\/SLICE_65/D1 (585:644:704)(585:644:704)) + (INTERCONNECT SLICE_50/Q0 nRWE_RNO_1\/SLICE_65/A0 (840:929:1019)(840:929:1019)) + (INTERCONNECT SLICE_50/Q0 SLICE_66/A1 (917:1014:1111)(917:1014:1111)) + (INTERCONNECT SLICE_50/Q0 SLICE_66/B0 (1252:1390:1529)(1252:1390:1529)) + (INTERCONNECT SLICE_50/Q0 SLICE_68/B0 (1373:1506:1640)(1373:1506:1640)) + (INTERCONNECT SLICE_50/Q0 SLICE_82/C0 (1212:1326:1441)(1212:1326:1441)) + (INTERCONNECT SLICE_50/Q0 SLICE_90/D1 (1467:1592:1717)(1467:1592:1717)) + (INTERCONNECT SLICE_50/Q0 SLICE_90/D0 (1467:1592:1717)(1467:1592:1717)) + (INTERCONNECT SLICE_50/Q0 SLICE_95/D1 (648:713:779)(648:713:779)) + (INTERCONNECT SLICE_50/Q0 SLICE_95/D0 (648:713:779)(648:713:779)) + (INTERCONNECT SLICE_90/F0 SLICE_41/A1 (1240:1363:1487)(1240:1363:1487)) + (INTERCONNECT SLICE_41/F1 SLICE_41/C0 (400:448:497)(400:448:497)) (INTERCONNECT SLICE_43/F1 SLICE_41/B0 (560:628:696)(560:628:696)) - (INTERCONNECT SLICE_41/F1 SLICE_41/A0 (779:868:958)(779:868:958)) (INTERCONNECT SLICE_41/F0 SLICE_41/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_42/Q1 SLICE_41/M1 (1342:1484:1626)(1342:1484:1626)) - (INTERCONNECT SLICE_41/Q0 SLICE_42/D0 (1352:1480:1609)(1352:1480:1609)) - (INTERCONNECT SLICE_52/Q1 SLICE_42/C0 (1218:1331:1444)(1218:1331:1444)) - (INTERCONNECT SLICE_44/Q1 SLICE_42/B0 (1293:1424:1555)(1293:1424:1555)) - (INTERCONNECT SLICE_44/Q1 SLICE_51/M1 (2091:2277:2464)(2091:2277:2464)) + (INTERCONNECT SLICE_42/Q1 SLICE_41/M1 (1773:1932:2091)(1773:1932:2091)) + (INTERCONNECT SLICE_41/Q0 SLICE_42/D0 (932:1044:1156)(932:1044:1156)) + (INTERCONNECT SLICE_95/Q1 SLICE_42/B1 (915:1013:1111)(915:1013:1111)) + (INTERCONNECT SLICE_95/Q1 SLICE_42/B0 (915:1013:1111)(915:1013:1111)) + (INTERCONNECT SLICE_95/Q1 SLICE_43/D1 (1026:1141:1257)(1026:1141:1257)) + (INTERCONNECT SLICE_95/Q1 SLICE_44/M1 (1743:1924:2105)(1743:1924:2105)) + (INTERCONNECT SLICE_95/Q1 SLICE_50/LSR (1746:1927:2109)(1746:1927:2109)) + (INTERCONNECT SLICE_95/Q1 SLICE_61/C1 (803:886:969)(803:886:969)) + (INTERCONNECT SLICE_95/Q1 SLICE_62/B1 (1341:1495:1649)(1341:1495:1649)) + (INTERCONNECT SLICE_95/Q1 nRWE_RNO_1\/SLICE_65/B1 (2043:2261:2480)(2043:2261:2480)) + (INTERCONNECT SLICE_95/Q1 SLICE_66/B1 (901:997:1094)(901:997:1094)) + (INTERCONNECT SLICE_95/Q1 SLICE_68/B1 (955:1061:1168)(955:1061:1168)) + (INTERCONNECT SLICE_95/Q1 SLICE_68/M0 (1446:1576:1706)(1446:1576:1706)) + (INTERCONNECT SLICE_95/Q1 SLICE_92/C0 (803:886:969)(803:886:969)) + (INTERCONNECT SLICE_95/Q1 SLICE_95/C0 (755:833:912)(755:833:912)) + (INTERCONNECT SLICE_42/Q0 SLICE_42/A1 (825:914:1004)(825:914:1004)) + (INTERCONNECT SLICE_42/Q0 SLICE_61/A1 (879:978:1078)(879:978:1078)) + (INTERCONNECT SLICE_42/Q0 nRWE_RNO_1\/SLICE_65/A1 (879:978:1078)(879:978:1078)) + (INTERCONNECT SLICE_42/Q0 RCKE_I/PADDO (1211:1391:1572)(1211:1391:1572)) + (INTERCONNECT SLICE_95/Q0 SLICE_42/C0 (672:749:827)(672:749:827)) + (INTERCONNECT SLICE_95/Q0 SLICE_95/M1 (535:595:655)(535:595:655)) + (INTERCONNECT SLICE_44/Q1 SLICE_42/A0 (837:931:1026)(837:931:1026)) (INTERCONNECT SLICE_42/F0 SLICE_42/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_42/Q0 SLICE_61/C1 (1543:1684:1825)(1543:1684:1825)) - (INTERCONNECT SLICE_42/Q0 nRWE_RNO_1\/SLICE_65/A1 (2060:2242:2425)(2060:2242:2425)) - (INTERCONNECT SLICE_42/Q0 RCKE_I/PADDO (1978:2217:2456)(1978:2217:2456)) - (INTERCONNECT SLICE_42/F1 nRWE_RNO_1\/SLICE_65/D0 (932:1044:1156)(932:1044:1156)) - (INTERCONNECT SLICE_50/F0 SLICE_43/A1 (1270:1395:1520)(1270:1395:1520)) - (INTERCONNECT SLICE_50/F0 SLICE_50/DI0 (16:16:16)(16:16:16)) - (INTERCONNECT SLICE_50/F0 SLICE_61/D1 (1001:1094:1188)(1001:1094:1188)) - (INTERCONNECT SLICE_50/F0 SLICE_62/C1 (1156:1268:1381)(1156:1268:1381)) - (INTERCONNECT SLICE_83/F0 SLICE_43/B0 (1255:1408:1561)(1255:1408:1561)) - (INTERCONNECT SLICE_83/F0 SLICE_44/A1 (1612:1787:1962)(1612:1787:1962)) + (INTERCONNECT SLICE_42/F1 SLICE_68/D0 (857:954:1052)(857:954:1052)) + (INTERCONNECT SLICE_50/F0 SLICE_43/B1 (2093:2310:2527)(2093:2310:2527)) + (INTERCONNECT SLICE_50/F0 SLICE_50/DI0 (31:31:31)(31:31:31)) + (INTERCONNECT SLICE_50/F0 SLICE_61/D1 (971:1085:1200)(971:1085:1200)) + (INTERCONNECT SLICE_50/F0 SLICE_62/D1 (595:663:731)(595:663:731)) + (INTERCONNECT SLICE_95/F0 SLICE_43/B0 (1788:1950:2112)(1788:1950:2112)) + (INTERCONNECT SLICE_95/F0 SLICE_44/B1 (1788:1950:2112)(1788:1950:2112)) (INTERCONNECT SLICE_43/F0 SLICE_43/DI0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_44/F1 SLICE_44/C0 (400:448:497)(400:448:497)) (INTERCONNECT SLICE_44/F0 SLICE_44/DI0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_50/F1 SLICE_63/LSR (528:587:647)(528:587:647)) - (INTERCONNECT SLICE_73/Q0 SLICE_51/D1 (1375:1502:1629)(1375:1502:1629)) - (INTERCONNECT SLICE_72/F0 SLICE_51/C1 (1126:1237:1348)(1126:1237:1348)) - (INTERCONNECT SLICE_66/F0 SLICE_51/A1 (1256:1379:1503)(1256:1379:1503)) - (INTERCONNECT SLICE_66/F0 SLICE_66/C1 (416:464:513)(416:464:513)) - (INTERCONNECT SLICE_51/Q0 SLICE_51/D0 (526:584:642)(526:584:642)) - (INTERCONNECT SLICE_51/Q0 UFMCLK_I/PADDO (1548:1774:2000)(1548:1774:2000)) - (INTERCONNECT SLICE_51/F1 SLICE_51/C0 (400:448:497)(400:448:497)) - (INTERCONNECT SLICE_64/F1 SLICE_51/B0 (1409:1541:1674)(1409:1541:1674)) - (INTERCONNECT SLICE_64/F1 SLICE_52/A0 (1271:1394:1518)(1271:1394:1518)) - (INTERCONNECT SLICE_64/F1 SLICE_64/B0 (591:659:727)(591:659:727)) - (INTERCONNECT SLICE_52/F1 SLICE_51/A0 (1157:1286:1415)(1157:1286:1415)) - (INTERCONNECT SLICE_52/F1 SLICE_52/C0 (431:479:528)(431:479:528)) - (INTERCONNECT SLICE_52/F1 SLICE_64/D0 (1002:1094:1186)(1002:1094:1186)) + (INTERCONNECT SLICE_67/F0 SLICE_51/D1 (261:290:320)(261:290:320)) + (INTERCONNECT SLICE_67/F0 SLICE_67/C1 (416:464:513)(416:464:513)) + (INTERCONNECT SLICE_69/F0 SLICE_51/C1 (723:805:887)(723:805:887)) + (INTERCONNECT SLICE_85/Q0 SLICE_51/A1 (1490:1668:1846)(1490:1668:1846)) + (INTERCONNECT SLICE_64/F1 SLICE_51/D0 (588:652:716)(588:652:716)) + (INTERCONNECT SLICE_64/F1 SLICE_52/C0 (743:826:909)(743:826:909)) + (INTERCONNECT SLICE_64/F1 SLICE_64/C0 (416:464:513)(416:464:513)) + (INTERCONNECT SLICE_52/F1 SLICE_51/C0 (1242:1357:1473)(1242:1357:1473)) + (INTERCONNECT SLICE_52/F1 SLICE_52/B0 (1402:1537:1672)(1402:1537:1672)) + (INTERCONNECT SLICE_52/F1 SLICE_64/D0 (873:970:1068)(873:970:1068)) + (INTERCONNECT SLICE_51/F1 SLICE_51/B0 (560:628:696)(560:628:696)) + (INTERCONNECT SLICE_51/Q0 SLICE_51/A0 (514:575:636)(514:575:636)) + (INTERCONNECT SLICE_51/Q0 UFMCLK_I/PADDO (646:731:817)(646:731:817)) (INTERCONNECT SLICE_51/F0 SLICE_51/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_87/F1 SLICE_52/D0 (568:631:694)(568:631:694)) - (INTERCONNECT SLICE_52/Q0 SLICE_52/B0 (825:921:1018)(825:921:1018)) + (INTERCONNECT SLICE_55/F0 SLICE_52/D0 (971:1063:1155)(971:1063:1155)) + (INTERCONNECT SLICE_52/Q0 SLICE_52/A0 (514:575:636)(514:575:636)) (INTERCONNECT SLICE_52/Q0 UFMSDI_I/PADDO (646:731:817)(646:731:817)) (INTERCONNECT SLICE_52/F0 SLICE_52/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT MAin\[4\]_I/PADDI SLICE_55/D0 (1207:1330:1453)(1207:1330:1453)) - (INTERCONNECT MAin\[4\]_I/PADDI SLICE_67/M0 (1949:2146:2344)(1949:2146:2344)) - (INTERCONNECT MAin\[4\]_I/PADDI SLICE_71/B1 (1914:2103:2292)(1914:2103:2292)) - (INTERCONNECT SLICE_63/Q0 SLICE_55/B0 (1997:2204:2411)(1997:2204:2411)) - (INTERCONNECT SLICE_63/Q0 SLICE_86/D1 (1451:1592:1734)(1451:1592:1734)) - (INTERCONNECT SLICE_63/Q0 SLICE_86/D0 (1451:1592:1734)(1451:1592:1734)) - (INTERCONNECT SLICE_63/Q0 SLICE_89/D1 (1451:1592:1734)(1451:1592:1734)) - (INTERCONNECT SLICE_63/Q0 SLICE_89/D0 (1451:1592:1734)(1451:1592:1734)) - (INTERCONNECT SLICE_63/Q0 SLICE_90/A0 (2415:2652:2889)(2415:2652:2889)) - (INTERCONNECT SLICE_63/Q0 SLICE_91/C1 (2426:2645:2865)(2426:2645:2865)) - (INTERCONNECT SLICE_63/Q0 SLICE_91/C0 (2426:2645:2865)(2426:2645:2865)) - (INTERCONNECT SLICE_63/Q0 SLICE_92/C1 (1898:2093:2289)(1898:2093:2289)) - (INTERCONNECT SLICE_63/Q0 SLICE_92/C0 (1898:2093:2289)(1898:2093:2289)) - (INTERCONNECT SLICE_63/Q0 SLICE_93/A1 (2415:2652:2889)(2415:2652:2889)) - (INTERCONNECT SLICE_63/Q0 SLICE_93/B0 (2176:2385:2595)(2176:2385:2595)) - (INTERCONNECT SLICE_67/Q0 SLICE_55/A0 (1201:1344:1488)(1201:1344:1488)) - (INTERCONNECT Din\[4\]_I/PADDI SLICE_55/M0 (2322:2541:2761)(2322:2541:2761)) - (INTERCONNECT Din\[4\]_I/PADDI SLICE_75/A1 (1473:1628:1784)(1473:1628:1784)) - (INTERCONNECT Din\[4\]_I/PADDI SLICE_76/M0 (1635:1791:1948)(1635:1791:1948)) - (INTERCONNECT Din\[4\]_I/PADDI SLICE_77/D1 (1628:1783:1939)(1628:1783:1939)) - (INTERCONNECT Din\[4\]_I/PADDI SLICE_85/D1 (1628:1783:1939)(1628:1783:1939)) - (INTERCONNECT Din\[4\]_I/PADDI SLICE_85/C0 (2072:2281:2490)(2072:2281:2490)) - (INTERCONNECT nCCAS_I/PADDI SLICE_55/CLK (2787:3031:3276)(2787:3031:3276)) - (INTERCONNECT nCCAS_I/PADDI SLICE_56/CLK (2787:3031:3276)(2787:3031:3276)) - (INTERCONNECT nCCAS_I/PADDI SLICE_75/M0 (2225:2440:2655)(2225:2440:2655)) - (INTERCONNECT nCCAS_I/PADDI SLICE_78/M0 (1818:2004:2190)(1818:2004:2190)) - (INTERCONNECT nCCAS_I/PADDI SLICE_78/M1 (1818:2004:2190)(1818:2004:2190)) - (INTERCONNECT nCCAS_I/PADDI SLICE_79/CLK (2377:2592:2807)(2377:2592:2807)) - (INTERCONNECT nCCAS_I/PADDI SLICE_85/CLK (1564:1720:1877)(1564:1720:1877)) - (INTERCONNECT nCCAS_I/PADDI SLICE_88/A0 (1798:1981:2164)(1798:1981:2164)) - (INTERCONNECT SLICE_55/F0 RA\[4\]_I/PADDO (2042:2305:2568)(2042:2305:2568)) - (INTERCONNECT SLICE_55/Q0 RD\[4\]_I/PADDO (646:731:817)(646:731:817)) - (INTERCONNECT SLICE_55/Q1 RD\[5\]_I/PADDO (2630:2955:3280)(2630:2955:3280)) - (INTERCONNECT SLICE_77/Q1 SLICE_56/D1 (1260:1386:1513)(1260:1386:1513)) - (INTERCONNECT SLICE_77/Q0 SLICE_56/C1 (1126:1237:1348)(1126:1237:1348)) - (INTERCONNECT SLICE_76/Q1 SLICE_56/B1 (1286:1416:1547)(1286:1416:1547)) - (INTERCONNECT SLICE_71/Q0 SLICE_56/A1 (1332:1457:1583)(1332:1457:1583)) - (INTERCONNECT Din\[7\]_I/PADDI SLICE_56/M1 (2232:2447:2663)(2232:2447:2663)) - (INTERCONNECT Din\[7\]_I/PADDI SLICE_75/D1 (1515:1665:1815)(1515:1665:1815)) - (INTERCONNECT Din\[7\]_I/PADDI SLICE_77/A1 (2604:2844:3085)(2604:2844:3085)) - (INTERCONNECT Din\[7\]_I/PADDI SLICE_77/M1 (2642:2887:3132)(2642:2887:3132)) - (INTERCONNECT Din\[7\]_I/PADDI SLICE_85/A1 (1381:1533:1686)(1381:1533:1686)) - (INTERCONNECT Din\[7\]_I/PADDI SLICE_85/A0 (1381:1533:1686)(1381:1533:1686)) + (INTERCONNECT SLICE_58/F1 SLICE_55/C0 (1392:1557:1723)(1392:1557:1723)) + (INTERCONNECT SLICE_58/F1 SLICE_71/D0 (588:652:716)(588:652:716)) + (INTERCONNECT SLICE_58/F1 SLICE_72/C0 (743:826:909)(743:826:909)) + (INTERCONNECT SLICE_88/Q0 SLICE_55/B0 (1378:1510:1643)(1378:1510:1643)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_55/M1 (2046:2233:2420)(2046:2233:2420)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_73/D1 (1501:1661:1821)(1501:1661:1821)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_83/D1 (1925:2116:2308)(1925:2116:2308)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_85/B1 (1944:2138:2333)(1944:2138:2333)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_85/B0 (1944:2138:2333)(1944:2138:2333)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_87/C1 (1791:1967:2143)(1791:1967:2143)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_87/C0 (1791:1967:2143)(1791:1967:2143)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_88/D1 (1921:2112:2303)(1921:2112:2303)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_88/D0 (1921:2112:2303)(1921:2112:2303)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_93/M1 (1922:2112:2303)(1922:2112:2303)) + (INTERCONNECT nCCAS_I/PADDI SLICE_55/CLK (1693:1863:2034)(1693:1863:2034)) + (INTERCONNECT nCCAS_I/PADDI SLICE_56/CLK (2110:2311:2512)(2110:2311:2512)) + (INTERCONNECT nCCAS_I/PADDI SLICE_74/M0 (1914:2102:2290)(1914:2102:2290)) + (INTERCONNECT nCCAS_I/PADDI SLICE_82/CLK (2110:2311:2512)(2110:2311:2512)) + (INTERCONNECT nCCAS_I/PADDI SLICE_84/CLK (2110:2311:2512)(2110:2311:2512)) + (INTERCONNECT nCCAS_I/PADDI SLICE_87/M0 (2363:2591:2820)(2363:2591:2820)) + (INTERCONNECT nCCAS_I/PADDI SLICE_87/M1 (2363:2591:2820)(2363:2591:2820)) + (INTERCONNECT nCCAS_I/PADDI SLICE_100/C1 (3197:3529:3861)(3197:3529:3861)) + (INTERCONNECT SLICE_55/Q0 RD\[4\]_I/PADDO (1532:1758:1984)(1532:1758:1984)) + (INTERCONNECT SLICE_55/Q1 RD\[5\]_I/PADDO (1164:1346:1528)(1164:1346:1528)) + (INTERCONNECT SLICE_101/Q0 SLICE_56/C0 (1533:1674:1815)(1533:1674:1815)) + (INTERCONNECT SLICE_101/Q0 SLICE_62/D0 (1676:1841:2006)(1676:1841:2006)) + (INTERCONNECT SLICE_101/Q0 SLICE_63/B1 (2105:2303:2501)(2105:2303:2501)) + (INTERCONNECT SLICE_56/F0 SLICE_60/B0 (1378:1510:1643)(1378:1510:1643)) (INTERCONNECT SLICE_56/Q0 RD\[6\]_I/PADDO (646:731:817)(646:731:817)) - (INTERCONNECT SLICE_56/F1 SLICE_70/B1 (1378:1510:1643)(1378:1510:1643)) + (INTERCONNECT SLICE_56/F1 SLICE_71/A1 (1247:1371:1495)(1247:1371:1495)) + (INTERCONNECT SLICE_56/F1 SLICE_72/D1 (978:1070:1163)(978:1070:1163)) (INTERCONNECT SLICE_56/Q1 RD\[7\]_I/PADDO (1532:1758:1984)(1532:1758:1984)) - (INTERCONNECT Din\[0\]_I/PADDI SLICE_57/C1 (1277:1418:1559)(1277:1418:1559)) - (INTERCONNECT Din\[0\]_I/PADDI SLICE_70/M0 (1839:2026:2214)(1839:2026:2214)) - (INTERCONNECT Din\[0\]_I/PADDI SLICE_74/M0 (2242:2458:2675)(2242:2458:2675)) - (INTERCONNECT Din\[0\]_I/PADDI SLICE_76/D1 (1532:1683:1835)(1532:1683:1835)) - (INTERCONNECT Din\[0\]_I/PADDI SLICE_79/M0 (3049:3329:3610)(3049:3329:3610)) - (INTERCONNECT Din\[0\]_I/PADDI SLICE_85/C1 (1566:1741:1917)(1566:1741:1917)) - (INTERCONNECT Din\[2\]_I/PADDI SLICE_57/B1 (1437:1597:1758)(1437:1597:1758)) - (INTERCONNECT Din\[2\]_I/PADDI SLICE_71/M0 (1129:1252:1375)(1129:1252:1375)) - (INTERCONNECT Din\[2\]_I/PADDI SLICE_73/M1 (1411:1566:1722)(1411:1566:1722)) - (INTERCONNECT Din\[2\]_I/PADDI SLICE_77/A0 (1384:1536:1689)(1384:1536:1689)) - (INTERCONNECT Din\[2\]_I/PADDI SLICE_78/A0 (1673:1860:2047)(1673:1860:2047)) - (INTERCONNECT Din\[2\]_I/PADDI SLICE_85/M0 (1429:1587:1745)(1429:1587:1745)) - (INTERCONNECT Din\[1\]_I/PADDI SLICE_57/D0 (710:802:894)(710:802:894)) - (INTERCONNECT Din\[1\]_I/PADDI SLICE_70/M1 (1420:1577:1734)(1420:1577:1734)) - (INTERCONNECT Din\[1\]_I/PADDI SLICE_73/M0 (1933:2113:2294)(1933:2113:2294)) - (INTERCONNECT Din\[1\]_I/PADDI SLICE_75/D0 (1113:1234:1355)(1113:1234:1355)) - (INTERCONNECT Din\[1\]_I/PADDI SLICE_76/B0 (1025:1155:1286)(1025:1155:1286)) - (INTERCONNECT Din\[1\]_I/PADDI SLICE_79/M1 (2233:2448:2664)(2233:2448:2664)) - (INTERCONNECT Din\[1\]_I/PADDI SLICE_85/B1 (1025:1155:1286)(1025:1155:1286)) + (INTERCONNECT SLICE_83/F1 SLICE_57/D1 (526:584:642)(526:584:642)) + (INTERCONNECT SLICE_83/F1 SLICE_83/B0 (576:644:712)(576:644:712)) (INTERCONNECT SLICE_57/F1 SLICE_57/C0 (400:448:497)(400:448:497)) + (INTERCONNECT SLICE_83/F0 SLICE_57/B0 (825:921:1018)(825:921:1018)) (INTERCONNECT SLICE_57/F0 SLICE_57/DI0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_58/F0 SLICE_58/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_68/F0 SLICE_58/CE (875:974:1073)(875:974:1073)) - (INTERCONNECT SLICE_58/F1 SLICE_87/B1 (576:644:712)(576:644:712)) - (INTERCONNECT SLICE_58/F1 SLICE_87/D0 (526:584:642)(526:584:642)) - (INTERCONNECT SLICE_59/F1 SLICE_59/D0 (510:568:626)(510:568:626)) - (INTERCONNECT SLICE_80/F0 SLICE_59/B0 (1286:1416:1547)(1286:1416:1547)) - (INTERCONNECT SLICE_62/F1 SLICE_59/A0 (1751:1905:2060)(1751:1905:2060)) + (INTERCONNECT SLICE_71/F0 SLICE_58/CE (1370:1500:1630)(1370:1500:1630)) + (INTERCONNECT SLICE_66/F0 SLICE_59/D1 (1063:1157:1251)(1063:1157:1251)) + (INTERCONNECT SLICE_62/F1 SLICE_59/C0 (1234:1347:1460)(1234:1347:1460)) (INTERCONNECT SLICE_62/F1 SLICE_62/C0 (416:464:513)(416:464:513)) + (INTERCONNECT SLICE_59/F1 SLICE_59/B0 (560:628:696)(560:628:696)) + (INTERCONNECT SLICE_84/F1 SLICE_59/A0 (779:868:958)(779:868:958)) (INTERCONNECT SLICE_59/F0 SLICE_59/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_59/Q0 nRCAS_I/PADDO (1723:1947:2172)(1723:1947:2172)) - (INTERCONNECT SLICE_82/Q0 SLICE_60/A1 (1751:1905:2060)(1751:1905:2060)) - (INTERCONNECT SLICE_82/Q0 SLICE_63/C1 (748:831:915)(748:831:915)) - (INTERCONNECT SLICE_82/Q0 SLICE_79/D1 (996:1089:1183)(996:1089:1183)) - (INTERCONNECT SLICE_82/Q0 SLICE_80/B1 (908:1011:1114)(908:1011:1114)) - (INTERCONNECT SLICE_94/F0 SLICE_60/D0 (1382:1514:1647)(1382:1514:1647)) + (INTERCONNECT SLICE_59/Q0 nRCAS_I/PADDO (1660:1871:2083)(1660:1871:2083)) + (INTERCONNECT SLICE_87/Q1 SLICE_60/A1 (1348:1473:1599)(1348:1473:1599)) + (INTERCONNECT SLICE_87/Q1 SLICE_62/C1 (1435:1581:1728)(1435:1581:1728)) + (INTERCONNECT SLICE_87/Q1 SLICE_82/A0 (1260:1384:1509)(1260:1384:1509)) + (INTERCONNECT SLICE_68/F0 SLICE_60/D0 (245:274:304)(245:274:304)) (INTERCONNECT SLICE_60/F1 SLICE_60/C0 (400:448:497)(400:448:497)) + (INTERCONNECT SLICE_84/F0 SLICE_60/A0 (1240:1363:1487)(1240:1363:1487)) (INTERCONNECT SLICE_60/F0 SLICE_60/DI0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_60/Q0 nRCS_I/PADDO (646:731:817)(646:731:817)) + (INTERCONNECT SLICE_61/F1 SLICE_61/C0 (400:448:497)(400:448:497)) + (INTERCONNECT SLICE_92/F1 SLICE_61/B0 (576:644:712)(576:644:712)) + (INTERCONNECT SLICE_92/F1 SLICE_66/A0 (853:947:1042)(853:947:1042)) (INTERCONNECT SLICE_61/F0 SLICE_61/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_61/Q0 nRRAS_I/PADDO (1532:1758:1984)(1532:1758:1984)) - (INTERCONNECT SLICE_78/Q1 SLICE_62/A1 (1348:1473:1599)(1348:1473:1599)) - (INTERCONNECT SLICE_78/Q1 SLICE_80/A0 (1256:1379:1503)(1256:1379:1503)) - (INTERCONNECT nRWE_RNO_1\/SLICE_65/OFX0 SLICE_62/D0 (568:631:694)(568:631:694)) - (INTERCONNECT SLICE_81/Q0 SLICE_62/B0 (1797:1958:2120)(1797:1958:2120)) - (INTERCONNECT SLICE_81/Q0 SLICE_63/D1 (588:652:716)(588:652:716)) - (INTERCONNECT SLICE_81/Q0 SLICE_80/D0 (1395:1523:1651)(1395:1523:1651)) - (INTERCONNECT SLICE_79/F0 SLICE_62/A0 (1201:1344:1488)(1201:1344:1488)) + (INTERCONNECT SLICE_61/Q0 nRRAS_I/PADDO (1610:1831:2052)(1610:1831:2052)) + (INTERCONNECT SLICE_82/F0 SLICE_62/B0 (879:985:1092)(879:985:1092)) + (INTERCONNECT nRWE_RNO_1\/SLICE_65/OFX0 SLICE_62/A0 (837:931:1026)(837:931:1026)) (INTERCONNECT SLICE_62/F0 SLICE_62/DI0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_62/Q0 nRWE_I/PADDO (646:731:817)(646:731:817)) - (INTERCONNECT SLICE_63/F1 SLICE_63/C0 (400:448:497)(400:448:497)) + (INTERCONNECT SLICE_63/F1 SLICE_63/A0 (779:868:958)(779:868:958)) (INTERCONNECT SLICE_63/F0 SLICE_63/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_64/Q0 SLICE_64/C0 (681:758:835)(681:758:835)) - (INTERCONNECT SLICE_64/Q0 nUFMCS_I/PADDO (1990:2225:2460)(1990:2225:2460)) - (INTERCONNECT SLICE_66/F1 SLICE_64/A0 (837:931:1026)(837:931:1026)) + (INTERCONNECT SLICE_63/Q0 SLICE_91/C1 (1547:1689:1832)(1547:1689:1832)) + (INTERCONNECT SLICE_63/Q0 SLICE_91/C0 (1547:1689:1832)(1547:1689:1832)) + (INTERCONNECT SLICE_63/Q0 SLICE_93/A1 (1689:1847:2006)(1689:1847:2006)) + (INTERCONNECT SLICE_63/Q0 SLICE_96/D1 (1288:1418:1549)(1288:1418:1549)) + (INTERCONNECT SLICE_63/Q0 SLICE_96/D0 (1288:1418:1549)(1288:1418:1549)) + (INTERCONNECT SLICE_63/Q0 SLICE_97/A1 (1981:2174:2368)(1981:2174:2368)) + (INTERCONNECT SLICE_63/Q0 SLICE_97/D0 (1420:1547:1674)(1420:1547:1674)) + (INTERCONNECT SLICE_63/Q0 SLICE_98/B1 (2027:2227:2428)(2027:2227:2428)) + (INTERCONNECT SLICE_63/Q0 SLICE_98/A0 (1689:1847:2006)(1689:1847:2006)) + (INTERCONNECT SLICE_63/Q0 SLICE_99/D1 (1285:1415:1545)(1285:1415:1545)) + (INTERCONNECT SLICE_63/Q0 SLICE_99/B0 (1311:1445:1579)(1311:1445:1579)) + (INTERCONNECT SLICE_63/Q0 SLICE_101/D1 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(INTERCONNECT MAin\[9\]_I/PADDI SLICE_86/A0 (2322:2546:2771)(2322:2546:2771)) - (INTERCONNECT MAin\[9\]_I/PADDI SLICE_89/C1 (2208:2420:2632)(2208:2420:2632)) - (INTERCONNECT MAin\[8\]_I/PADDI SLICE_80/M0 (1508:1668:1828)(1508:1668:1828)) - (INTERCONNECT MAin\[8\]_I/PADDI SLICE_89/B0 (1919:2110:2302)(1919:2110:2302)) - (INTERCONNECT SLICE_80/Q0 SLICE_89/A0 (837:931:1026)(837:931:1026)) - (INTERCONNECT SLICE_80/Q1 SLICE_86/C0 (723:805:887)(723:805:887)) - (INTERCONNECT nFWE_I/PADDI SLICE_81/M0 (1514:1673:1833)(1514:1673:1833)) - (INTERCONNECT nFWE_I/PADDI SLICE_81/M1 (1514:1673:1833)(1514:1673:1833)) - (INTERCONNECT nFWE_I/PADDI SLICE_88/C1 (1802:1985:2168)(1802:1985:2168)) - (INTERCONNECT nFWE_I/PADDI SLICE_88/C0 (1802:1985:2168)(1802:1985:2168)) - (INTERCONNECT CROW\[1\]_I/PADDI SLICE_83/M1 (1635:1796:1957)(1635:1796:1957)) - (INTERCONNECT CROW\[0\]_I/PADDI SLICE_83/M0 (1635:1796:1957)(1635:1796:1957)) - (INTERCONNECT SLICE_83/Q0 RBA\[0\]_I/PADDO (646:731:817)(646:731:817)) - (INTERCONNECT SLICE_83/Q1 RBA\[1\]_I/PADDO (2063:2303:2544)(2063:2303:2544)) - (INTERCONNECT SLICE_85/Q0 RD\[2\]_I/PADDO (1971:2209:2448)(1971:2209:2448)) - (INTERCONNECT SLICE_85/Q1 RD\[3\]_I/PADDO (1974:2209:2444)(1974:2209:2444)) - (INTERCONNECT SLICE_86/F0 RA\[9\]_I/PADDO (1165:1345:1526)(1165:1345:1526)) - (INTERCONNECT SLICE_86/F1 RDQML_I/PADDO (1974:2209:2444)(1974:2209:2444)) - (INTERCONNECT SLICE_88/F0 RD\[0\]_I/PADDT (1748:1996:2245)(1748:1996:2245)) - (INTERCONNECT SLICE_88/F0 RD\[7\]_I/PADDT (2544:2849:3155)(2544:2849:3155)) - (INTERCONNECT SLICE_88/F0 RD\[6\]_I/PADDT (2544:2849:3155)(2544:2849:3155)) - (INTERCONNECT SLICE_88/F0 RD\[5\]_I/PADDT (2544:2849:3155)(2544:2849:3155)) - (INTERCONNECT SLICE_88/F0 RD\[4\]_I/PADDT (3364:3728:4093)(3364:3728:4093)) - (INTERCONNECT SLICE_88/F0 RD\[3\]_I/PADDT (3364:3728:4093)(3364:3728:4093)) - (INTERCONNECT SLICE_88/F0 RD\[2\]_I/PADDT (1783:2025:2267)(1783:2025:2267)) - (INTERCONNECT SLICE_88/F0 RD\[1\]_I/PADDT (3357:3721:4085)(3357:3721:4085)) - (INTERCONNECT SLICE_88/Q0 SLICE_92/D1 (1063:1157:1251)(1063:1157:1251)) - (INTERCONNECT SLICE_88/Q1 SLICE_91/A1 (837:931:1026)(837:931:1026)) - (INTERCONNECT SLICE_89/F0 RA\[8\]_I/PADDO (1932:2190:2449)(1932:2190:2449)) - (INTERCONNECT SLICE_89/F1 RDQMH_I/PADDO (1168:1345:1522)(1168:1345:1522)) - (INTERCONNECT SLICE_90/F0 RA\[0\]_I/PADDO (646:731:817)(646:731:817)) - (INTERCONNECT SLICE_91/F0 RA\[1\]_I/PADDO (1974:2209:2444)(1974:2209:2444)) - (INTERCONNECT SLICE_91/F1 RA\[7\]_I/PADDO (1288:1474:1660)(1288:1474:1660)) - (INTERCONNECT SLICE_92/F0 RA\[2\]_I/PADDO (646:731:817)(646:731:817)) - (INTERCONNECT SLICE_92/F1 RA\[6\]_I/PADDO (646:731:817)(646:731:817)) - (INTERCONNECT SLICE_93/F0 RA\[3\]_I/PADDO (1168:1345:1522)(1168:1345:1522)) - (INTERCONNECT SLICE_93/F1 RA\[5\]_I/PADDO (646:731:817)(646:731:817)) - (INTERCONNECT SLICE_94/Q0 RA\[10\]_I/PADDO (2063:2303:2544)(2063:2303:2544)) + (INTERCONNECT SLICE_92/F0 nRWE_RNO_1\/SLICE_65/B0 (1697:1868:2039)(1697:1868:2039)) + (INTERCONNECT SLICE_85/Q1 SLICE_67/A1 (1332:1457:1583)(1332:1457:1583)) + (INTERCONNECT SLICE_80/F1 SLICE_67/C0 (681:758:835)(681:758:835)) + (INTERCONNECT SLICE_80/F1 SLICE_80/C0 (416:464:513)(416:464:513)) + (INTERCONNECT SLICE_86/F0 SLICE_67/B0 (1176:1313:1450)(1176:1313:1450)) + (INTERCONNECT SLICE_86/F0 SLICE_80/B0 (887:989:1092)(887:989:1092)) + (INTERCONNECT MAin\[3\]_I/PADDI SLICE_67/M1 (1519:1680:1842)(1519:1680:1842)) + (INTERCONNECT MAin\[3\]_I/PADDI SLICE_76/B1 (1972:2175:2379)(1972:2175:2379)) + (INTERCONNECT MAin\[3\]_I/PADDI SLICE_81/B0 (2261:2499:2737)(2261:2499:2737)) + (INTERCONNECT MAin\[3\]_I/PADDI SLICE_93/D0 (1657:1822:1987)(1657:1822:1987)) + (INTERCONNECT MAin\[3\]_I/PADDI SLICE_97/C0 (1770:1943:2117)(1770:1943:2117)) + (INTERCONNECT MAin\[2\]_I/PADDI SLICE_67/M0 (1211:1335:1459)(1211:1335:1459)) + (INTERCONNECT MAin\[2\]_I/PADDI SLICE_76/A0 (1897:2083:2269)(1897:2083:2269)) + (INTERCONNECT MAin\[2\]_I/PADDI SLICE_81/D0 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(1801:1984:2167)(1801:1984:2167)) + (INTERCONNECT nFWE_I/PADDI SLICE_100/D1 (1532:1683:1835)(1532:1683:1835)) + (INTERCONNECT nFWE_I/PADDI SLICE_101/M0 (2648:2894:3140)(2648:2894:3140)) + (INTERCONNECT nFWE_I/PADDI SLICE_101/M1 (2648:2894:3140)(2648:2894:3140)) + (INTERCONNECT SLICE_70/F1 SLICE_70/C0 (416:464:513)(416:464:513)) + (INTERCONNECT SLICE_70/F1 SLICE_73/B0 (1302:1432:1563)(1302:1432:1563)) + (INTERCONNECT SLICE_94/F0 SLICE_71/D1 (1074:1169:1265)(1074:1169:1265)) + (INTERCONNECT SLICE_94/F0 SLICE_72/A1 (1343:1470:1597)(1343:1470:1597)) + (INTERCONNECT SLICE_89/F1 SLICE_71/B1 (887:989:1092)(887:989:1092)) + (INTERCONNECT SLICE_89/F1 SLICE_72/C1 (1016:1133:1251)(1016:1133:1251)) + (INTERCONNECT SLICE_71/F1 SLICE_71/C0 (400:448:497)(400:448:497)) + (INTERCONNECT SLICE_72/F1 SLICE_72/B0 (825:921:1018)(825:921:1018)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_73/A1 (1669:1855:2041)(1669:1855:2041)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_75/A1 (1380:1531:1683)(1380:1531:1683)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_79/M1 (1521:1671:1821)(1521:1671:1821)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_82/M1 (1528:1678:1829)(1528:1678:1829)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_83/D0 (1952:2134:2316)(1952:2134:2316)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_85/A1 (2510:2758:3006)(2510:2758:3006)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_85/D0 (1952:2134:2316)(1952:2134:2316)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_88/C1 (2107:2308:2509)(2107:2308:2509)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_88/C0 (2107:2308:2509)(2107:2308:2509)) + (INTERCONNECT MAin\[7\]_I/PADDI SLICE_73/M1 (1218:1344:1470)(1218:1344:1470)) + (INTERCONNECT MAin\[7\]_I/PADDI SLICE_79/B1 (1526:1689:1853)(1526:1689:1853)) + (INTERCONNECT MAin\[7\]_I/PADDI SLICE_99/C1 (1769:1942:2115)(1769:1942:2115)) + (INTERCONNECT MAin\[6\]_I/PADDI SLICE_73/M0 (1646:1808:1971)(1646:1808:1971)) + (INTERCONNECT MAin\[6\]_I/PADDI SLICE_79/C1 (2612:2858:3104)(2612:2858:3104)) + (INTERCONNECT MAin\[6\]_I/PADDI SLICE_101/C1 (3015:3290:3565)(3015:3290:3565)) + (INTERCONNECT SLICE_73/Q0 SLICE_101/B1 (1247:1397:1548)(1247:1397:1548)) + (INTERCONNECT SLICE_73/Q1 SLICE_99/B1 (1286:1416:1547)(1286:1416:1547)) + (INTERCONNECT SLICE_78/F1 SLICE_74/C0 (681:758:835)(681:758:835)) + (INTERCONNECT SLICE_78/F1 SLICE_78/C0 (416:464:513)(416:464:513)) + (INTERCONNECT SLICE_74/F1 SLICE_74/B0 (832:929:1026)(832:929:1026)) + (INTERCONNECT SLICE_74/F1 SLICE_78/B0 (832:929:1026)(832:929:1026)) + (INTERCONNECT SLICE_88/F1 SLICE_74/A0 (849:948:1048)(849:948:1048)) + (INTERCONNECT SLICE_88/F1 SLICE_78/D0 (580:648:716)(580:648:716)) + (INTERCONNECT SLICE_74/Q0 SLICE_74/M1 (528:587:647)(528:587:647)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_75/B1 (1027:1158:1289)(1027:1158:1289)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_78/C1 (1270:1410:1551)(1270:1410:1551)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_79/M0 (719:812:906)(719:812:906)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_82/M0 (2251:2475:2700)(2251:2475:2700)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_83/A0 (2213:2433:2653)(2213:2433:2653)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_85/M1 (2654:2907:3161)(2654:2907:3161)) + (INTERCONNECT SLICE_75/Q0 SLICE_77/A1 (833:932:1032)(833:932:1032)) + (INTERCONNECT SLICE_75/Q1 SLICE_77/B1 (1697:1868:2039)(1697:1868:2039)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_76/A1 (1897:2084:2271)(1897:2084:2271)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_81/D1 (1628:1783:1939)(1628:1783:1939)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_89/M0 (2025:2215:2405)(2025:2215:2405)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_93/C0 (1783:1957:2132)(1783:1957:2132)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_98/C0 (1366:1510:1654)(1366:1510:1654)) + (INTERCONNECT SLICE_76/F1 SLICE_76/C0 (400:448:497)(400:448:497)) + (INTERCONNECT SLICE_76/Q0 SLICE_100/D0 (564:632:700)(564:632:700)) + (INTERCONNECT SLICE_76/Q1 SLICE_100/A0 (837:931:1026)(837:931:1026)) + (INTERCONNECT SLICE_79/Q0 SLICE_77/D1 (510:568:626)(510:568:626)) + (INTERCONNECT SLICE_93/Q1 SLICE_77/C1 (719:806:893)(719:806:893)) + (INTERCONNECT SLICE_100/F0 SLICE_77/D0 (526:584:642)(526:584:642)) + (INTERCONNECT SLICE_100/F0 SLICE_79/A0 (795:884:974)(795:884:974)) + (INTERCONNECT SLICE_77/F1 SLICE_77/C0 (416:464:513)(416:464:513)) + (INTERCONNECT SLICE_77/F1 SLICE_79/C0 (681:758:835)(681:758:835)) + (INTERCONNECT SLICE_81/F0 SLICE_77/B0 (1706:1871:2037)(1706:1871:2037)) + (INTERCONNECT SLICE_81/F0 SLICE_78/A0 (530:591:652)(530:591:652)) + (INTERCONNECT SLICE_79/F1 SLICE_79/D0 (526:584:642)(526:584:642)) + (INTERCONNECT SLICE_79/F1 SLICE_81/A0 (853:947:1042)(853:947:1042)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_79/B0 (1522:1683:1845)(1522:1683:1845)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_81/B1 (1925:2115:2306)(1925:2115:2306)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_89/M1 (1514:1673:1832)(1514:1673:1832)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_99/D0 (1207:1330:1453)(1207:1330:1453)) + (INTERCONNECT SLICE_79/Q1 SLICE_100/B0 (825:921:1018)(825:921:1018)) + (INTERCONNECT SLICE_81/F1 SLICE_81/C0 (400:448:497)(400:448:497)) + (INTERCONNECT SLICE_82/F1 SLICE_82/B0 (825:921:1018)(825:921:1018)) + (INTERCONNECT SLICE_82/Q0 RD\[2\]_I/PADDO (1532:1758:1984)(1532:1758:1984)) + (INTERCONNECT SLICE_82/Q1 RD\[3\]_I/PADDO (646:731:817)(646:731:817)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_83/M1 (1814:1998:2183)(1814:1998:2183)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_91/B1 (1965:2167:2370)(1965:2167:2370)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_91/B0 (1965:2167:2370)(1965:2167:2370)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_96/B1 (2360:2589:2818)(2360:2589:2818)) + (INTERCONNECT MAin\[8\]_I/PADDI SLICE_83/M0 (1508:1668:1828)(1508:1668:1828)) + (INTERCONNECT MAin\[8\]_I/PADDI SLICE_96/A0 (2276:2489:2703)(2276:2489:2703)) + (INTERCONNECT SLICE_83/Q0 SLICE_96/C0 (1126:1237:1348)(1126:1237:1348)) + (INTERCONNECT SLICE_83/Q1 SLICE_91/A0 (1240:1363:1487)(1240:1363:1487)) + (INTERCONNECT SLICE_84/Q0 RD\[0\]_I/PADDO (646:731:817)(646:731:817)) + (INTERCONNECT SLICE_84/Q1 RD\[1\]_I/PADDO (1165:1345:1526)(1165:1345:1526)) + (INTERCONNECT SLICE_85/F1 SLICE_85/CE (535:595:655)(535:595:655)) + (INTERCONNECT SLICE_85/F1 SLICE_88/CE (535:595:655)(535:595:655)) + (INTERCONNECT SLICE_89/Q0 SLICE_98/B0 (883:984:1086)(883:984:1086)) + (INTERCONNECT SLICE_89/Q1 SLICE_99/C0 (1529:1669:1809)(1529:1669:1809)) + (INTERCONNECT CROW\[1\]_I/PADDI SLICE_90/M1 (1635:1796:1957)(1635:1796:1957)) + (INTERCONNECT CROW\[0\]_I/PADDI SLICE_90/M0 (1635:1796:1957)(1635:1796:1957)) + (INTERCONNECT SLICE_90/Q0 RBA\[0\]_I/PADDO (646:731:817)(646:731:817)) + (INTERCONNECT SLICE_90/Q1 RBA\[1\]_I/PADDO (1964:2232:2500)(1964:2232:2500)) + (INTERCONNECT SLICE_91/F0 RA\[9\]_I/PADDO (1168:1345:1522)(1168:1345:1522)) + (INTERCONNECT SLICE_91/F1 RDQMH_I/PADDO (1168:1345:1522)(1168:1345:1522)) + (INTERCONNECT SLICE_93/Q0 SLICE_100/C0 (723:805:887)(723:805:887)) + (INTERCONNECT SLICE_93/F1 RA\[1\]_I/PADDO (2063:2303:2544)(2063:2303:2544)) + (INTERCONNECT SLICE_96/F0 RA\[8\]_I/PADDO (1288:1474:1660)(1288:1474:1660)) + (INTERCONNECT SLICE_96/F1 RDQML_I/PADDO (1974:2209:2444)(1974:2209:2444)) + (INTERCONNECT SLICE_97/F0 RA\[3\]_I/PADDO (1979:2229:2479)(1979:2229:2479)) + (INTERCONNECT SLICE_97/F1 RA\[0\]_I/PADDO (1288:1474:1660)(1288:1474:1660)) + (INTERCONNECT SLICE_98/F0 RA\[4\]_I/PADDO (2006:2250:2495)(2006:2250:2495)) + (INTERCONNECT SLICE_98/F1 RA\[2\]_I/PADDO (1607:1831:2056)(1607:1831:2056)) + (INTERCONNECT SLICE_99/F0 RA\[5\]_I/PADDO (1571:1777:1983)(1571:1777:1983)) + (INTERCONNECT SLICE_99/F1 RA\[7\]_I/PADDO (1288:1474:1660)(1288:1474:1660)) + (INTERCONNECT SLICE_100/F1 RD\[0\]_I/PADDT (1752:2007:2263)(1752:2007:2263)) + (INTERCONNECT SLICE_100/F1 RD\[7\]_I/PADDT (2134:2397:2661)(2134:2397:2661)) + (INTERCONNECT SLICE_100/F1 RD\[6\]_I/PADDT (2134:2397:2661)(2134:2397:2661)) + (INTERCONNECT SLICE_100/F1 RD\[5\]_I/PADDT (2134:2397:2661)(2134:2397:2661)) + (INTERCONNECT SLICE_100/F1 RD\[4\]_I/PADDT (2127:2389:2652)(2127:2389:2652)) + (INTERCONNECT SLICE_100/F1 RD\[3\]_I/PADDT (2127:2389:2652)(2127:2389:2652)) + (INTERCONNECT SLICE_100/F1 RD\[2\]_I/PADDT (1805:2039:2273)(1805:2039:2273)) + (INTERCONNECT SLICE_100/F1 RD\[1\]_I/PADDT (2187:2481:2775)(2187:2481:2775)) + (INTERCONNECT SLICE_101/F1 RA\[6\]_I/PADDO (646:731:817)(646:731:817)) (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_I/PADDO (2288:2578:2869)(2288:2578:2869)) (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_I/PADDO (1418:1631:1845)(1418:1631:1845)) (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_I/PADDO (2196:2460:2725)(2196:2460:2725)) (INTERCONNECT RD\[5\]_I/PADDI Dout\[5\]_I/PADDO (1421:1631:1841)(1421:1631:1841)) - (INTERCONNECT RD\[4\]_I/PADDI Dout\[4\]_I/PADDO (2196:2460:2725)(2196:2460:2725)) + (INTERCONNECT RD\[4\]_I/PADDI Dout\[4\]_I/PADDO (2193:2461:2729)(2193:2461:2729)) (INTERCONNECT RD\[3\]_I/PADDI Dout\[3\]_I/PADDO (2196:2460:2725)(2196:2460:2725)) (INTERCONNECT RD\[2\]_I/PADDI Dout\[2\]_I/PADDO (2196:2460:2725)(2196:2460:2725)) (INTERCONNECT RD\[1\]_I/PADDI Dout\[1\]_I/PADDO (2196:2460:2725)(2196:2460:2725)) diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_vo.vo b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_vo.vo index 7aa5678..6da1502 100644 --- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_vo.vo +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_vo.vo @@ -2,8 +2,8 @@ // Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454 // ldbanno -n Verilog -o RAM2GS_LCMXO256C_impl1_vo.vo -w -neg -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd -// Netlist created on Thu Sep 21 05:38:29 2023 -// Netlist written on Thu Sep 21 05:38:46 2023 +// Netlist created on Sat Jan 06 06:24:57 2024 +// Netlist written on Sat Jan 06 06:25:15 2024 // Design is for device LCMXO256C // Design is for package TQFP100 // Design is for performance grade 3 @@ -28,45 +28,49 @@ module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, \FS_cry[15] , \FS[15] , \FS[14] , \FS_cry[13] , \FS[13] , \FS[12] , \FS_cry[11] , \FS[11] , \FS[10] , \FS_cry[9] , \FS[9] , \FS[8] , \FS_cry[7] , \FS[7] , \FS[6] , \FS_cry[5] , \FS[5] , \FS[4] , - \FS_cry[3] , \FS[3] , \FS[2] , CmdEnable17_0_a2_4, CmdEnable17_0_a2_3, - \MAin_c[0] , N_147, ADSubmitted, CmdEnable17, CmdEnable16, C1WR_0_a2, - ADSubmitted_r, PHI2_c, CmdEnable16_0_a2_5, CmdEnable16_0_a2_4, - \MAin_c[1] , C1Submitted, C1Submitted_RNO, RASr2, \S[1] , CO0, - \IS[3] , N_177_i, Ready_0_sqmuxa_0_a3_2, CmdEnable, un1_CMDWR, - CmdEnable_s, N_128, \Din_c[5] , \Din_c[3] , N_133, N_152, N_132, - LEDEN, N_21_i, XOR8MEG18, CmdLEDEN, CmdSubmitted, InitReady, PHI2r3, - PHI2r2, CmdSubmitted_1_sqmuxa, N_460_0, N_136, N_43, Cmdn8MEGEN, - CmdEnable16_4, n8MEGEN, Cmdn8MEGEN_4_u_i_0, N_19_i, nRRAS_5_u_i_0, - \IS[0] , N_160, N_155, Ready, N_64_i_i, N_24, \IS[1] , \IS[2] , - N_60_i_i, N_56_i, N_159_i, N_159, N_61_i_i, RA10s_i, N_126, N_51, - UFMSDI_ens2_i_a2_4_2, InitReady3, N_461_0, UFMSDI_ens2_i_a0, nCRAS_c, - CBR, UFMSDO_c, N_70, N_33, LED_c, un1_Din_4, XOR8MEG, \Din_c[6] , - RA11_2, Ready_fast, \RA_c[11] , N_171, CASr2, FWEr_fast, - RCKEEN_8_u_0_0, RCKEEN_8_u_1, RCKEEN_8, PHI2r, RCKEEN, RASr3, RASr, - RCKE_2, RCKE_c, m18_0_a3_3, \S_0_i_o2[1] , N_165, N_462_0, - Ready_0_sqmuxa, N_463_0, nRRAS_0_sqmuxa, CmdUFMCLK, N_129, - UFMCLK_r_i_a2_2_2, UFMCLK_c, UFMCLK_r_i_m4_xx_mm_1, nUFMCS15, N_139_i, - UFMCLK_RNO, UFMSDI_r_xx_mm_1, UFMSDI_c, UFMSDI_RNO, \MAin_c[4] , - nRowColSel, \RowA[4] , \Din_c[4] , nCCAS_c, \RA_c[4] , \WRD[4] , - \WRD[5] , \Bank[7] , \Bank[6] , \Bank[5] , \Bank[2] , \Din_c[7] , - \WRD[6] , C1WR_0_a2_0_11, \WRD[7] , \Din_c[0] , \Din_c[2] , - \Din_c[1] , XOR8MEG_3_u_0_a3_2, XOR8MEG_3, N_69, N_31, N_151, N_41, - g0_1, nRCAS_0_sqmuxa_1, N_37_i, nRCAS_c, CASr3, RCKEEN_8_u_0_a2_1_out, - N_28_i_1, N_28_i, nRCS_c, N_24_i, nRRAS_c, CBR_fast, m18_0_a2_1, FWEr, - G_17_1, N_39_i, nRWE_c, N_179, nRowColSel_0_0, nUFMCS_c, - nUFMCS_s_0_N_5_i_N_2L1, nUFMCS_s_0_N_5_i, CmdUFMCS, N_95_5, N_95_3, - \RowA[0] , \RowA[1] , \MAin_c[5] , CmdUFMCLK_1_sqmuxa, \RowA[5] , - N_137_8, un1_FS_14_i_a2_0_1, N_137_6, un1_FS_13_i_a2_1, \Bank[0] , - C1WR_0_a2_0_10, \Bank[1] , \MAin_c[6] , \MAin_c[7] , C1WR_0_a2_0_3, - \Bank[3] , \Bank[4] , C1WR_0_a2_0_4, UFMSDI_ens2_i_o2_0_3, - \MAin_c[3] , \MAin_c[2] , \RowA[2] , \RowA[3] , CmdUFMSDI, CASr, - CmdEnable16_1, m6_0_a2_2, \WRD[0] , \WRD[1] , g4_0_0_0, \MAin_c[9] , - \MAin_c[8] , \RowA[8] , \RowA[9] , nFWE_c, \CROW_c[1] , \CROW_c[0] , - \RBA_c[0] , \RBA_c[1] , \WRD[2] , \WRD[3] , \RA_c[9] , RDQML_c, - RD_1_i, \RowA[6] , \RowA[7] , \RA_c[8] , RDQMH_c, \RA_c[0] , - \RA_c[1] , \RA_c[7] , \RA_c[2] , \RA_c[6] , \RA_c[3] , \RA_c[5] , - \RA_c[10] , \RD_in[0] , \RD_in[7] , \RD_in[6] , \RD_in[5] , - \RD_in[4] , \RD_in[3] , \RD_in[2] , \RD_in[1] , VCCI, GNDI_TSALL; + \FS_cry[3] , \FS[3] , \FS[2] , ADWR, C1WR, ADSubmitted, CmdEnable16, + N_183_i, CmdEnable17, ADSubmitted_r, PHI2_c, C1Submitted, N_121, + un1_CmdEnable20_0_a3_0_2, C1Submitted_RNO, un1_CmdEnable20_i, + CmdEnable16_0_a3_5, CmdEnable16_0_a3_4, CmdEnable_0_sqmuxa, CmdEnable, + CmdEnable_s, \Din_c[1] , CmdLEDEN_4_u_i_a2_0_0, N_45, CmdLEDEN, N_95, + CmdLEDEN_4_u_i_0, LEDEN, N_14_i, XOR8MEG18, PHI2r2, PHI2r3, InitReady, + CmdSubmitted, CmdSubmitted_1_sqmuxa, N_428_0, N_134, \Din_c[0] , + Cmdn8MEGEN, n8MEGEN, Cmdn8MEGEN_4_u_i_0, N_12_i, \IS[0] , \IS[2] , + \IS[1] , N_148, Ready, N_77_i_i, CASr2, N_160, CASr3, N_74_i_i, + N_69_i, N_153_i, \IS[3] , N_75_i_i, RA10s_i, N_128, + UFMSDI_ens2_i_a2_4_2, N_34, InitReady3, N_429_0, UFMSDI_ens2_i_a0, + nCRAS_c, CBR, UFMSDO_c, N_49, N_26, LED_c, N_151, \RA_c[10] , g3, + \Din_c[7] , \Din_c[4] , \Din_c[6] , XOR8MEG, RA11_2, Ready_fast, + \RA_c[11] , N_36, FWEr_fast, CO0, \S[1] , RCKEEN_8_u_0_a3_0_0, + RCKEEN_8_u_0_1_1, RCKEEN_8_u_0_0, RCKEEN_8, PHI2r, RCKEEN, RASr2, + RCKE_c, RASr, RASr3, RCKE_2, g0_i_a5_1, \S_0_i_o2[1] , + Ready_0_sqmuxa_0_a3_2, N_430_0, Ready_0_sqmuxa, N_431_0, + nRRAS_0_sqmuxa, UFMCLK_r_i_a2_2_2, N_129, CmdUFMCLK, nUFMCS15, + N_137_i, UFMCLK_r_i_m4_xx_mm_1, UFMCLK_c, UFMCLK_RNO, + UFMSDI_r_xx_mm_1, UFMSDI_c, UFMSDI_RNO, N_94, CmdUFMSDI, \Din_c[5] , + nCCAS_c, \WRD[4] , \WRD[5] , FWEr, N_125, \WRD[6] , N_43, \WRD[7] , + N_163, N_166, XOR8MEG_3_u_0_a3_0_1, XOR8MEG_3, N_48, N_24, + un1_nRCAS_6_sqmuxa_i_0, nRCAS_0_sqmuxa_1, G_1_1, G_1_0, N_46_i, + nRCAS_c, CBR_fast, g0_i_0, N_184, g0_i_a5_1_2, N_143_i, nRCS_c, + nRRAS_5_u_i_0, N_154, N_142_i, nRRAS_c, G_17_1, m18_0_a2_1, N_144_i, + nRWE_c, N_112, nRowColSel_0_0, nRowColSel, nUFMCS_c, + nUFMCS_s_0_N_5_i_N_2L1, nUFMCS_s_0_N_5_i, m18_0_a3_3, CmdUFMCS, + N_133_3, N_133_5, \MAin_c[3] , \MAin_c[2] , \RowA[2] , \RowA[3] , + g0_i_a5_2_1, N_9, RCKEEN_8_u_0_1_a1_0, UFMSDI_ens2_i_o2_0_3, + \MAin_c[1] , \MAin_c[0] , \RowA[0] , \RowA[1] , C1WR_7, CMDWR_2, + nFWE_c, CMDWR, un1_FS_13_i_a2_9_4, un1_FS_13_i_a2_9_5, + un1_FS_14_i_a2_0_1, un1_FS_13_i_a2_1, \Din_c[3] , \MAin_c[7] , + \MAin_c[6] , \RowA[6] , \RowA[7] , N_180, N_156, N_122_5, CASr, + \Din_c[2] , \Bank[6] , \Bank[7] , \MAin_c[4] , C1WR_2_0, \Bank[0] , + \Bank[1] , \Bank[2] , \Bank[5] , un1_Bank_1_4, un1_Bank_1_5, ADWR_8, + ADWR_8_2, \MAin_c[5] , \Bank[3] , ADWR_8_4, m6_0_a2_2, \WRD[2] , + \WRD[3] , \MAin_c[9] , \MAin_c[8] , \RowA[8] , \RowA[9] , \WRD[0] , + \WRD[1] , CmdUFMCLK_1_sqmuxa, \RowA[4] , \RowA[5] , \CROW_c[1] , + \CROW_c[0] , \RBA_c[0] , \RBA_c[1] , \RA_c[9] , RDQMH_c, \Bank[4] , + \RA_c[1] , \RA_c[8] , RDQML_c, \RA_c[3] , \RA_c[0] , \RA_c[4] , + \RA_c[2] , \RA_c[5] , \RA_c[7] , RD_1_i, \RA_c[6] , \RD_in[0] , + \RD_in[7] , \RD_in[6] , \RD_in[5] , \RD_in[4] , \RD_in[3] , + \RD_in[2] , \RD_in[1] , VCCI, GNDI_TSALL; SLICE_0 SLICE_0( .A1(\FS[1] ), .A0(\FS[0] ), .CLK(RCLK_c), .Q0(\FS[0] ), .Q1(\FS[1] ), .FCO(\FS_cry[1] )); @@ -86,212 +90,231 @@ module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, .Q0(\FS[4] ), .Q1(\FS[5] ), .FCO(\FS_cry[5] )); SLICE_8 SLICE_8( .A1(\FS[3] ), .A0(\FS[2] ), .CLK(RCLK_c), .FCI(\FS_cry[1] ), .Q0(\FS[2] ), .Q1(\FS[3] ), .FCO(\FS_cry[3] )); - SLICE_9 SLICE_9( .D1(CmdEnable17_0_a2_4), .C1(CmdEnable17_0_a2_3), - .B1(\MAin_c[0] ), .A1(N_147), .D0(ADSubmitted), .C0(CmdEnable17), - .B0(CmdEnable16), .A0(C1WR_0_a2), .DI0(ADSubmitted_r), .CLK(PHI2_c), - .F0(ADSubmitted_r), .Q0(ADSubmitted), .F1(CmdEnable17)); - SLICE_14 SLICE_14( .D1(CmdEnable16_0_a2_5), .C1(CmdEnable16_0_a2_4), - .A1(N_147), .D0(\MAin_c[1] ), .C0(CmdEnable16), .B0(C1Submitted), - .A0(N_147), .DI0(C1Submitted_RNO), .CLK(PHI2_c), .F0(C1Submitted_RNO), - .Q0(C1Submitted), .F1(CmdEnable16)); - SLICE_19 SLICE_19( .D1(RASr2), .C1(\S[1] ), .B1(CO0), .A1(\IS[3] ), - .C0(\S[1] ), .A0(CO0), .DI0(N_177_i), .LSR(RASr2), .CLK(RCLK_c), - .F0(N_177_i), .Q0(CO0), .F1(Ready_0_sqmuxa_0_a3_2)); - SLICE_20 SLICE_20( .B1(ADSubmitted), .A1(CmdEnable), .D0(CmdEnable17), - .C0(un1_CMDWR), .B0(C1Submitted), .A0(CmdEnable), .DI0(CmdEnable_s), - .M0(CmdEnable16), .CLK(PHI2_c), .OFX0(CmdEnable_s), .Q0(CmdEnable)); - SLICE_21 SLICE_21( .D1(N_128), .B1(\Din_c[5] ), .A1(\Din_c[3] ), .D0(N_133), - .C0(N_152), .B0(N_132), .A0(LEDEN), .DI0(N_21_i), .CE(XOR8MEG18), - .CLK(PHI2_c), .F0(N_21_i), .Q0(CmdLEDEN), .F1(N_152)); - SLICE_22 SLICE_22( .D1(CmdSubmitted), .C1(InitReady), .B1(PHI2r3), - .A1(PHI2r2), .C0(CmdSubmitted_1_sqmuxa), .A0(CmdSubmitted), .DI0(N_460_0), - .CLK(PHI2_c), .F0(N_460_0), .Q0(CmdSubmitted), .F1(N_136)); - SLICE_26 SLICE_26( .D1(N_128), .C1(N_43), .B1(Cmdn8MEGEN), - .A1(CmdEnable16_4), .D0(n8MEGEN), .C0(Cmdn8MEGEN_4_u_i_0), .A0(N_152), - .DI0(N_19_i), .CE(XOR8MEG18), .CLK(PHI2_c), .F0(N_19_i), .Q0(Cmdn8MEGEN), - .F1(Cmdn8MEGEN_4_u_i_0)); - SLICE_29 SLICE_29( .D1(nRRAS_5_u_i_0), .C1(\IS[0] ), .B1(N_160), .A1(N_155), - .D0(\IS[0] ), .B0(Ready), .A0(N_155), .DI0(N_64_i_i), .CLK(RCLK_c), - .F0(N_64_i_i), .Q0(\IS[0] ), .F1(N_24)); + SLICE_9 SLICE_9( .D1(ADWR), .A1(C1WR), .D0(ADSubmitted), .C0(CmdEnable16), + .B0(N_183_i), .A0(CmdEnable17), .DI0(ADSubmitted_r), .CLK(PHI2_c), + .F0(ADSubmitted_r), .Q0(ADSubmitted), .F1(N_183_i)); + SLICE_14 SLICE_14( .D1(C1Submitted), .C1(N_121), .B1(CmdEnable16), + .A1(un1_CmdEnable20_0_a3_0_2), .D0(ADWR), .C0(C1Submitted), + .B0(CmdEnable16), .A0(C1WR), .DI0(C1Submitted_RNO), .CLK(PHI2_c), + .F0(C1Submitted_RNO), .Q0(C1Submitted), .F1(un1_CmdEnable20_i)); + SLICE_20 SLICE_20( .D1(CmdEnable16_0_a3_5), .C1(CmdEnable16_0_a3_4), + .B1(ADSubmitted), .A1(C1WR), .D0(CmdEnable17), .C0(CmdEnable_0_sqmuxa), + .B0(CmdEnable), .A0(un1_CmdEnable20_i), .DI0(CmdEnable_s), .CLK(PHI2_c), + .F0(CmdEnable_s), .Q0(CmdEnable), .F1(CmdEnable_0_sqmuxa)); + SLICE_21 SLICE_21( .D1(\Din_c[1] ), .C1(CmdLEDEN_4_u_i_a2_0_0), .B1(N_45), + .A1(CmdLEDEN), .D0(N_95), .C0(CmdLEDEN_4_u_i_0), .B0(LEDEN), .DI0(N_14_i), + .CE(XOR8MEG18), .CLK(PHI2_c), .F0(N_14_i), .Q0(CmdLEDEN), + .F1(CmdLEDEN_4_u_i_0)); + SLICE_22 SLICE_22( .D1(PHI2r2), .C1(PHI2r3), .B1(InitReady), + .A1(CmdSubmitted), .B0(CmdSubmitted_1_sqmuxa), .A0(CmdSubmitted), + .DI0(N_428_0), .CLK(PHI2_c), .F0(N_428_0), .Q0(CmdSubmitted), .F1(N_134)); + SLICE_26 SLICE_26( .D1(\Din_c[0] ), .C1(Cmdn8MEGEN), .B1(N_45), + .A1(CmdLEDEN_4_u_i_a2_0_0), .D0(n8MEGEN), .C0(Cmdn8MEGEN_4_u_i_0), + .A0(N_95), .DI0(N_12_i), .CE(XOR8MEG18), .CLK(PHI2_c), .F0(N_12_i), + .Q0(Cmdn8MEGEN), .F1(Cmdn8MEGEN_4_u_i_0)); + SLICE_29 SLICE_29( .D1(\IS[0] ), .C1(\IS[2] ), .A1(\IS[1] ), .D0(N_148), + .C0(Ready), .A0(\IS[0] ), .DI0(N_77_i_i), .M1(CASr2), .CLK(RCLK_c), + .F0(N_77_i_i), .Q0(\IS[0] ), .F1(N_160), .Q1(CASr3)); SLICE_30 SLICE_30( .D1(\IS[0] ), .B1(\IS[1] ), .A1(\IS[2] ), .D0(\IS[0] ), - .A0(\IS[1] ), .DI1(N_60_i_i), .DI0(N_56_i), .CE(N_159_i), .CLK(RCLK_c), - .F0(N_56_i), .Q0(\IS[1] ), .F1(N_60_i_i), .Q1(\IS[2] )); - SLICE_31 SLICE_31( .D1(\IS[2] ), .C1(N_159), .B1(\IS[1] ), .A1(\IS[3] ), - .D0(\IS[2] ), .C0(\IS[0] ), .B0(\IS[1] ), .A0(\IS[3] ), .DI0(N_61_i_i), - .CE(N_159_i), .CLK(RCLK_c), .F0(N_61_i_i), .Q0(\IS[3] ), .F1(RA10s_i)); - SLICE_32 SLICE_32( .D1(N_126), .C1(N_51), .B1(UFMSDI_ens2_i_a2_4_2), - .A1(InitReady), .B0(InitReady3), .A0(InitReady), .DI0(N_461_0), - .CLK(RCLK_c), .F0(N_461_0), .Q0(InitReady), .F1(UFMSDI_ens2_i_a0)); - SLICE_33 SLICE_33( .D1(nCRAS_c), .C1(LEDEN), .A1(CBR), .D0(UFMSDO_c), - .C0(InitReady), .A0(CmdLEDEN), .DI0(N_70), .CE(N_33), .CLK(RCLK_c), - .F0(N_70), .Q0(LEDEN), .F1(LED_c)); - SLICE_39 SLICE_39( .D1(un1_Din_4), .A1(XOR8MEG), .D0(\Din_c[6] ), - .C0(n8MEGEN), .A0(XOR8MEG), .DI0(RA11_2), .LSR(Ready_fast), .CLK(PHI2_c), - .F0(RA11_2), .Q0(\RA_c[11] ), .F1(N_171)); - SLICE_41 SLICE_41( .D1(CASr2), .C1(\S[1] ), .B1(CO0), .A1(FWEr_fast), - .D0(CBR), .C0(Ready), .B0(RCKEEN_8_u_0_0), .A0(RCKEEN_8_u_1), - .DI0(RCKEEN_8), .M1(PHI2r), .CLK(RCLK_c), .F0(RCKEEN_8), .Q0(RCKEEN), - .F1(RCKEEN_8_u_1), .Q1(PHI2r2)); - SLICE_42 SLICE_42( .D1(\IS[0] ), .C1(RASr2), .B1(\IS[2] ), .A1(\IS[1] ), - .D0(RCKEEN), .C0(RASr3), .B0(RASr), .A0(RASr2), .DI0(RCKE_2), .M1(PHI2_c), - .CLK(RCLK_c), .F0(RCKE_2), .Q0(RCKE_c), .F1(m18_0_a3_3), .Q1(PHI2r)); - SLICE_43 SLICE_43( .D1(InitReady), .C1(RASr2), .B1(Ready), - .A1(\S_0_i_o2[1] ), .D0(InitReady), .C0(Ready), .B0(N_165), - .A0(Ready_0_sqmuxa_0_a3_2), .DI0(N_462_0), .M1(PHI2r2), .CLK(RCLK_c), - .F0(N_462_0), .Q0(Ready), .F1(RCKEEN_8_u_0_0), .Q1(PHI2r3)); - SLICE_44 SLICE_44( .D1(Ready), .C1(InitReady), .B1(Ready_0_sqmuxa_0_a3_2), - .A1(N_165), .C0(Ready_0_sqmuxa), .A0(Ready_fast), .DI0(N_463_0), - .M1(nCRAS_c), .CLK(RCLK_c), .F0(N_463_0), .Q0(Ready_fast), - .F1(Ready_0_sqmuxa), .Q1(RASr)); - SLICE_50 SLICE_50( .D1(Ready), .C1(CO0), .B1(\S[1] ), .C0(CO0), .A0(\S[1] ), + .A0(\IS[1] ), .DI1(N_74_i_i), .DI0(N_69_i), .CE(N_153_i), .CLK(RCLK_c), + .F0(N_69_i), .Q0(\IS[1] ), .F1(N_74_i_i), .Q1(\IS[2] )); + SLICE_31 SLICE_31( .D1(N_148), .C1(\IS[0] ), .B1(Ready), .A1(\IS[3] ), + .D0(\IS[1] ), .C0(\IS[0] ), .B0(\IS[2] ), .A0(\IS[3] ), .DI0(N_75_i_i), + .CE(N_153_i), .CLK(RCLK_c), .F0(N_75_i_i), .Q0(\IS[3] ), .F1(RA10s_i)); + SLICE_32 SLICE_32( .D1(N_128), .C1(UFMSDI_ens2_i_a2_4_2), .B1(InitReady), + .A1(N_34), .D0(InitReady3), .A0(InitReady), .DI0(N_429_0), .CLK(RCLK_c), + .F0(N_429_0), .Q0(InitReady), .F1(UFMSDI_ens2_i_a0)); + SLICE_33 SLICE_33( .D1(Ready), .C1(nCRAS_c), .B1(LEDEN), .A1(CBR), + .D0(CmdLEDEN), .C0(InitReady), .B0(UFMSDO_c), .DI0(N_49), .CE(N_26), + .CLK(RCLK_c), .F0(N_49), .Q0(LEDEN), .F1(LED_c)); + SLICE_38 SLICE_38( .D1(\IS[3] ), .C1(\IS[0] ), .B1(\IS[2] ), .A1(\IS[1] ), + .D0(\IS[1] ), .B0(\IS[2] ), .DI0(N_151), .LSR(RA10s_i), .CLK(RCLK_c), + .F0(N_151), .Q0(\RA_c[10] ), .F1(g3)); + SLICE_39 SLICE_39( .D1(\Din_c[7] ), .B1(\Din_c[4] ), .A1(\Din_c[6] ), + .D0(XOR8MEG), .B0(n8MEGEN), .A0(\Din_c[6] ), .DI0(RA11_2), + .LSR(Ready_fast), .CLK(PHI2_c), .F0(RA11_2), .Q0(\RA_c[11] ), .F1(N_36)); + SLICE_41 SLICE_41( .D1(FWEr_fast), .C1(CO0), .B1(\S[1] ), + .A1(RCKEEN_8_u_0_a3_0_0), .D0(CBR), .C0(RCKEEN_8_u_0_1_1), + .B0(RCKEEN_8_u_0_0), .A0(Ready), .DI0(RCKEEN_8), .M1(PHI2r), .CLK(RCLK_c), + .F0(RCKEEN_8), .Q0(RCKEEN), .F1(RCKEEN_8_u_0_1_1), .Q1(PHI2r2)); + SLICE_42 SLICE_42( .C1(Ready), .B1(RASr2), .A1(RCKE_c), .D0(RCKEEN), + .C0(RASr), .B0(RASr2), .A0(RASr3), .DI0(RCKE_2), .M1(PHI2_c), .CLK(RCLK_c), + .F0(RCKE_2), .Q0(RCKE_c), .F1(g0_i_a5_1), .Q1(PHI2r)); + SLICE_43 SLICE_43( .D1(RASr2), .C1(InitReady), .B1(\S_0_i_o2[1] ), + .A1(Ready), .D0(N_160), .C0(InitReady), .B0(Ready_0_sqmuxa_0_a3_2), + .A0(Ready), .DI0(N_430_0), .M1(PHI2r2), .CLK(RCLK_c), .F0(N_430_0), + .Q0(Ready), .F1(RCKEEN_8_u_0_0), .Q1(PHI2r3)); + SLICE_44 SLICE_44( .D1(InitReady), .C1(N_160), .B1(Ready_0_sqmuxa_0_a3_2), + .A1(Ready), .C0(Ready_0_sqmuxa), .A0(Ready_fast), .DI0(N_431_0), + .M1(RASr2), .CLK(RCLK_c), .F0(N_431_0), .Q0(Ready_fast), + .F1(Ready_0_sqmuxa), .Q1(RASr3)); + SLICE_50 SLICE_50( .D1(CO0), .C1(Ready), .A1(\S[1] ), .C0(CO0), .A0(\S[1] ), .DI0(\S_0_i_o2[1] ), .LSR(RASr2), .CLK(RCLK_c), .F0(\S_0_i_o2[1] ), .Q0(\S[1] ), .F1(nRRAS_0_sqmuxa)); - SLICE_51 SLICE_51( .D1(CmdUFMCLK), .C1(N_129), .B1(InitReady), - .A1(UFMCLK_r_i_a2_2_2), .D0(UFMCLK_c), .C0(UFMCLK_r_i_m4_xx_mm_1), - .B0(nUFMCS15), .A0(N_139_i), .DI0(UFMCLK_RNO), .M1(RASr), .CLK(RCLK_c), - .F0(UFMCLK_RNO), .Q0(UFMCLK_c), .F1(UFMCLK_r_i_m4_xx_mm_1), .Q1(RASr2)); - SLICE_52 SLICE_52( .D1(PHI2r2), .C1(PHI2r3), .B1(InitReady), - .A1(CmdSubmitted), .D0(UFMSDI_r_xx_mm_1), .C0(N_139_i), .B0(UFMSDI_c), - .A0(nUFMCS15), .DI0(UFMSDI_RNO), .M1(RASr2), .CLK(RCLK_c), .F0(UFMSDI_RNO), - .Q0(UFMSDI_c), .F1(N_139_i), .Q1(RASr3)); - SLICE_55 SLICE_55( .D0(\MAin_c[4] ), .B0(nRowColSel), .A0(\RowA[4] ), - .M1(\Din_c[5] ), .M0(\Din_c[4] ), .CLK(nCCAS_c), .F0(\RA_c[4] ), + SLICE_51 SLICE_51( .D1(UFMCLK_r_i_a2_2_2), .C1(N_129), .B1(InitReady), + .A1(CmdUFMCLK), .D0(nUFMCS15), .C0(N_137_i), .B0(UFMCLK_r_i_m4_xx_mm_1), + .A0(UFMCLK_c), .DI0(UFMCLK_RNO), .CLK(RCLK_c), .F0(UFMCLK_RNO), + .Q0(UFMCLK_c), .F1(UFMCLK_r_i_m4_xx_mm_1)); + SLICE_52 SLICE_52( .D1(PHI2r3), .C1(PHI2r2), .B1(InitReady), + .A1(CmdSubmitted), .D0(UFMSDI_r_xx_mm_1), .C0(nUFMCS15), .B0(N_137_i), + .A0(UFMSDI_c), .DI0(UFMSDI_RNO), .CLK(RCLK_c), .F0(UFMSDI_RNO), + .Q0(UFMSDI_c), .F1(N_137_i)); + SLICE_55 SLICE_55( .D0(UFMSDI_ens2_i_a0), .C0(N_94), .B0(CmdUFMSDI), + .M1(\Din_c[5] ), .M0(\Din_c[4] ), .CLK(nCCAS_c), .F0(UFMSDI_r_xx_mm_1), .Q0(\WRD[4] ), .Q1(\WRD[5] )); - SLICE_56 SLICE_56( .D1(\Bank[7] ), .C1(\Bank[6] ), .B1(\Bank[5] ), - .A1(\Bank[2] ), .D0(\FS[5] ), .C0(\FS[9] ), .B0(\FS[7] ), .M1(\Din_c[7] ), - .M0(\Din_c[6] ), .CLK(nCCAS_c), .F0(N_126), .Q0(\WRD[6] ), - .F1(C1WR_0_a2_0_11), .Q1(\WRD[7] )); - SLICE_57 SLICE_57( .D1(un1_Din_4), .C1(\Din_c[0] ), .B1(\Din_c[2] ), - .A1(\Din_c[3] ), .D0(\Din_c[1] ), .C0(XOR8MEG_3_u_0_a3_2), .B0(LEDEN), - .A0(N_171), .DI0(XOR8MEG_3), .CE(XOR8MEG18), .CLK(PHI2_c), .F0(XOR8MEG_3), - .Q0(XOR8MEG), .F1(XOR8MEG_3_u_0_a3_2)); - SLICE_58 SLICE_58( .D1(N_51), .C1(InitReady), .A1(\FS[8] ), .D0(UFMSDO_c), - .C0(InitReady), .B0(Cmdn8MEGEN), .DI0(N_69), .CE(N_31), .CLK(RCLK_c), - .F0(N_69), .Q0(n8MEGEN), .F1(N_151)); - SLICE_59 SLICE_59( .D1(N_155), .C1(\S[1] ), .B1(Ready), .A1(N_160), - .D0(N_41), .C0(\S[1] ), .B0(g0_1), .A0(nRCAS_0_sqmuxa_1), .DI0(N_37_i), - .CLK(RCLK_c), .F0(N_37_i), .Q0(nRCAS_c), .F1(N_41)); - SLICE_60 SLICE_60( .D1(FWEr_fast), .C1(CO0), .B1(CASr2), .A1(CASr3), - .D0(RCKEEN_8_u_0_a2_1_out), .C0(N_28_i_1), .B0(N_24), .A0(CBR), - .DI0(N_28_i), .CLK(RCLK_c), .F0(N_28_i), .Q0(nRCS_c), .F1(N_28_i_1)); - SLICE_61 SLICE_61( .D1(\S_0_i_o2[1] ), .C1(RCKE_c), .B1(Ready), .A1(RASr2), - .D0(\IS[0] ), .C0(N_155), .B0(nRRAS_5_u_i_0), .A0(N_160), .DI0(N_24_i), - .CLK(RCLK_c), .F0(N_24_i), .Q0(nRRAS_c), .F1(nRRAS_5_u_i_0)); - SLICE_62 SLICE_62( .D1(RASr2), .C1(\S_0_i_o2[1] ), .B1(Ready), .A1(CBR_fast), - .D0(m18_0_a2_1), .C0(nRCAS_0_sqmuxa_1), .B0(FWEr), .A0(G_17_1), - .DI0(N_39_i), .CLK(RCLK_c), .F0(N_39_i), .Q0(nRWE_c), + SLICE_56 SLICE_56( .C1(\FS[11] ), .A1(\FS[4] ), .C0(FWEr), .A0(CO0), + .M1(\Din_c[7] ), .M0(\Din_c[6] ), .CLK(nCCAS_c), .F0(N_125), .Q0(\WRD[6] ), + .F1(N_43), .Q1(\WRD[7] )); + SLICE_57 SLICE_57( .D1(N_163), .B1(XOR8MEG), .D0(\Din_c[1] ), .C0(N_166), + .B0(XOR8MEG_3_u_0_a3_0_1), .A0(LEDEN), .DI0(XOR8MEG_3), .CE(XOR8MEG18), + .CLK(PHI2_c), .F0(XOR8MEG_3), .Q0(XOR8MEG), .F1(N_166)); + SLICE_58 SLICE_58( .D1(N_128), .C1(\FS[8] ), .A1(InitReady), .D0(Cmdn8MEGEN), + .B0(UFMSDO_c), .A0(InitReady), .DI0(N_48), .CE(N_24), .CLK(RCLK_c), + .F0(N_48), .Q0(n8MEGEN), .F1(N_94)); + SLICE_59 SLICE_59( .D1(un1_nRCAS_6_sqmuxa_i_0), .B1(\S[1] ), .A1(CBR), + .D0(\S[1] ), .C0(nRCAS_0_sqmuxa_1), .B0(G_1_1), .A0(G_1_0), .DI0(N_46_i), + .CLK(RCLK_c), .F0(N_46_i), .Q0(nRCAS_c), .F1(G_1_1)); + SLICE_60 SLICE_60( .D1(Ready), .B1(\S[1] ), .A1(CBR_fast), .D0(g0_i_0), + .C0(N_184), .B0(N_125), .A0(g0_i_a5_1_2), .DI0(N_143_i), .CLK(RCLK_c), + .F0(N_143_i), .Q0(nRCS_c), .F1(N_184)); + SLICE_61 SLICE_61( .D1(\S_0_i_o2[1] ), .C1(RASr2), .B1(Ready), .A1(RCKE_c), + .D0(N_148), .C0(nRRAS_5_u_i_0), .B0(N_154), .A0(\IS[0] ), .DI0(N_142_i), + .CLK(RCLK_c), .F0(N_142_i), .Q0(nRRAS_c), .F1(nRRAS_5_u_i_0)); + SLICE_62 SLICE_62( .D1(\S_0_i_o2[1] ), .C1(CBR_fast), .B1(RASr2), .A1(Ready), + .D0(FWEr), .C0(nRCAS_0_sqmuxa_1), .B0(G_17_1), .A0(m18_0_a2_1), + .DI0(N_144_i), .CLK(RCLK_c), .F0(N_144_i), .Q0(nRWE_c), .F1(nRCAS_0_sqmuxa_1)); - SLICE_63 SLICE_63( .D1(FWEr), .C1(CASr3), .B1(Ready), .A1(CBR), .D0(\S[1] ), - .C0(N_179), .B0(Ready), .A0(CO0), .DI0(nRowColSel_0_0), + SLICE_63 SLICE_63( .D1(CBR), .C1(Ready), .B1(FWEr), .A1(CASr3), .D0(CO0), + .C0(Ready), .B0(\S[1] ), .A0(N_112), .DI0(nRowColSel_0_0), .LSR(nRRAS_0_sqmuxa), .CLK(RCLK_c), .F0(nRowColSel_0_0), .Q0(nRowColSel), - .F1(N_179)); - SLICE_64 SLICE_64( .D1(\FS[11] ), .C1(InitReady), .B1(N_51), .A1(\FS[10] ), - .D0(N_139_i), .C0(nUFMCS_c), .B0(nUFMCS15), .A0(nUFMCS_s_0_N_5_i_N_2L1), + .F1(N_112)); + SLICE_64 SLICE_64( .D1(\FS[10] ), .C1(InitReady), .B1(N_128), .A1(\FS[11] ), + .D0(N_137_i), .C0(nUFMCS15), .B0(nUFMCS_c), .A0(nUFMCS_s_0_N_5_i_N_2L1), .DI0(nUFMCS_s_0_N_5_i), .CLK(RCLK_c), .F0(nUFMCS_s_0_N_5_i), .Q0(nUFMCS_c), .F1(nUFMCS15)); - nRWE_RNO_1_SLICE_65 \nRWE_RNO_1/SLICE_65 ( .D1(RASr2), .C1(\S[1] ), .B1(CO0), - .A1(RCKE_c), .D0(m18_0_a3_3), .C0(\S[1] ), .B0(CO0), .A0(InitReady), + nRWE_RNO_1_SLICE_65 \nRWE_RNO_1/SLICE_65 ( .D1(\S[1] ), .C1(CO0), .B1(RASr2), + .A1(RCKE_c), .D0(InitReady), .C0(CO0), .B0(m18_0_a3_3), .A0(\S[1] ), .M0(Ready), .OFX0(m18_0_a2_1)); - SLICE_66 SLICE_66( .D1(CmdUFMCS), .C1(UFMCLK_r_i_a2_2_2), .B1(InitReady), - .D0(N_95_5), .C0(N_95_3), .B0(InitReady), .A0(\FS[16] ), .M1(\MAin_c[1] ), - .M0(\MAin_c[0] ), .LSR(Ready_fast), .CLK(nCRAS_c), .F0(UFMCLK_r_i_a2_2_2), - .Q0(\RowA[0] ), .F1(nUFMCS_s_0_N_5_i_N_2L1), .Q1(\RowA[1] )); - SLICE_67 SLICE_67( .D1(N_128), .C1(\Din_c[3] ), .B1(\Din_c[5] ), - .A1(XOR8MEG18), .D0(CmdEnable), .C0(\MAin_c[0] ), .B0(\MAin_c[1] ), - .A0(N_147), .M1(\MAin_c[5] ), .M0(\MAin_c[4] ), .LSR(Ready_fast), - .CLK(nCRAS_c), .F0(XOR8MEG18), .Q0(\RowA[4] ), .F1(CmdUFMCLK_1_sqmuxa), - .Q1(\RowA[5] )); - SLICE_68 SLICE_68( .D1(\FS[5] ), .C1(\FS[2] ), .B1(\FS[0] ), .A1(\FS[3] ), - .D0(N_137_8), .C0(N_136), .B0(un1_FS_14_i_a2_0_1), .A0(N_137_6), .F0(N_31), - .F1(un1_FS_14_i_a2_0_1)); - SLICE_69 SLICE_69( .D1(\FS[0] ), .C1(\FS[3] ), .B1(\FS[5] ), .A1(\FS[2] ), - .D0(N_137_8), .C0(N_136), .B0(N_137_6), .A0(un1_FS_13_i_a2_1), .F0(N_33), - .F1(un1_FS_13_i_a2_1)); - SLICE_70 SLICE_70( .D1(\Bank[0] ), .C1(C1WR_0_a2_0_10), .B1(C1WR_0_a2_0_11), - .A1(\Bank[1] ), .C0(N_147), .A0(\MAin_c[1] ), .M1(\Din_c[1] ), - .M0(\Din_c[0] ), .CLK(PHI2_c), .F0(C1WR_0_a2), .Q0(\Bank[0] ), .F1(N_147), - .Q1(\Bank[1] )); - SLICE_71 SLICE_71( .D1(\MAin_c[6] ), .C1(\MAin_c[7] ), .B1(\MAin_c[4] ), - .A1(\MAin_c[5] ), .D0(C1WR_0_a2_0_3), .C0(\Bank[3] ), .B0(\Bank[4] ), - .A0(C1WR_0_a2_0_4), .M1(\Din_c[3] ), .M0(\Din_c[2] ), .CLK(PHI2_c), - .F0(C1WR_0_a2_0_10), .Q0(\Bank[2] ), .F1(C1WR_0_a2_0_4), .Q1(\Bank[3] )); - SLICE_72 SLICE_72( .D1(UFMSDI_ens2_i_o2_0_3), .C1(\FS[16] ), .A1(\FS[12] ), - .D0(\FS[4] ), .C0(N_51), .B0(\FS[11] ), .A0(\FS[1] ), .M1(\MAin_c[3] ), - .M0(\MAin_c[2] ), .LSR(Ready_fast), .CLK(nCRAS_c), .F0(N_129), - .Q0(\RowA[2] ), .F1(N_51), .Q1(\RowA[3] )); - SLICE_73 SLICE_73( .D1(InitReady), .C1(\S[1] ), .B1(RASr2), .A1(CO0), - .C0(N_155), .A0(Ready), .M1(\Din_c[2] ), .M0(\Din_c[1] ), - .CE(CmdUFMCLK_1_sqmuxa), .CLK(PHI2_c), .F0(N_159), .Q0(CmdUFMCLK), - .F1(N_155), .Q1(CmdUFMCS)); - SLICE_74 SLICE_74( .B1(\FS[11] ), .A1(\FS[14] ), .D0(N_95_5), .C0(N_95_3), - .B0(\FS[16] ), .A0(\FS[10] ), .M0(\Din_c[0] ), .CE(CmdUFMCLK_1_sqmuxa), - .CLK(PHI2_c), .F0(InitReady3), .Q0(CmdUFMSDI), .F1(N_95_3)); - SLICE_75 SLICE_75( .D1(\Din_c[7] ), .B1(\Din_c[6] ), .A1(\Din_c[4] ), - .D0(\Din_c[1] ), .C0(N_128), .B0(\Din_c[5] ), .M1(CASr), .M0(nCCAS_c), - .CLK(RCLK_c), .F0(N_133), .Q0(CASr), .F1(N_128), .Q1(CASr2)); - SLICE_76 SLICE_76( .D1(\Din_c[0] ), .B1(\Din_c[5] ), .D0(\MAin_c[0] ), - .C0(CmdEnable16_4), .B0(\Din_c[1] ), .A0(\Din_c[3] ), .M1(\Din_c[5] ), - .M0(\Din_c[4] ), .CLK(PHI2_c), .F0(CmdEnable16_0_a2_4), .Q0(\Bank[4] ), - .F1(CmdEnable16_4), .Q1(\Bank[5] )); - SLICE_77 SLICE_77( .D1(\Din_c[4] ), .A1(\Din_c[7] ), .D0(\Din_c[6] ), - .C0(\MAin_c[1] ), .B0(CmdEnable16_1), .A0(\Din_c[2] ), .M1(\Din_c[7] ), - .M0(\Din_c[6] ), .CLK(PHI2_c), .F0(CmdEnable16_0_a2_5), .Q0(\Bank[6] ), - .F1(CmdEnable16_1), .Q1(\Bank[7] )); - SLICE_78 SLICE_78( .D1(\Din_c[3] ), .B1(\Din_c[5] ), .D0(\MAin_c[1] ), - .C0(N_43), .B0(\Din_c[6] ), .A0(\Din_c[2] ), .M1(nCCAS_c), .M0(nCCAS_c), - .CLK(nCRAS_c), .F0(CmdEnable17_0_a2_4), .Q0(CBR), .F1(N_43), .Q1(CBR_fast)); - SLICE_79 SLICE_79( .D1(CASr3), .B1(CASr2), .A1(Ready), .D0(CO0), .C0(\S[1] ), - .B0(m6_0_a2_2), .A0(CBR), .M1(\Din_c[1] ), .M0(\Din_c[0] ), .CLK(nCCAS_c), - .F0(G_17_1), .Q0(\WRD[0] ), .F1(m6_0_a2_2), .Q1(\WRD[1] )); - SLICE_80 SLICE_80( .D1(CASr2), .B1(CASr3), .D0(FWEr), .C0(CO0), - .B0(g4_0_0_0), .A0(CBR_fast), .M1(\MAin_c[9] ), .M0(\MAin_c[8] ), - .LSR(Ready_fast), .CLK(nCRAS_c), .F0(g0_1), .Q0(\RowA[8] ), .F1(g4_0_0_0), + SLICE_66 SLICE_66( .D1(CO0), .C1(InitReady), .B1(RASr2), .A1(\S[1] ), + .D0(Ready), .C0(N_148), .B0(\S[1] ), .A0(N_154), + .F0(un1_nRCAS_6_sqmuxa_i_0), .F1(N_148)); + SLICE_67 SLICE_67( .D1(InitReady), .C1(UFMCLK_r_i_a2_2_2), .A1(CmdUFMCS), + .D0(InitReady), .C0(N_133_3), .B0(N_133_5), .A0(\FS[13] ), + .M1(\MAin_c[3] ), .M0(\MAin_c[2] ), .LSR(Ready_fast), .CLK(nCRAS_c), + .F0(UFMCLK_r_i_a2_2_2), .Q0(\RowA[2] ), .F1(nUFMCS_s_0_N_5_i_N_2L1), + .Q1(\RowA[3] )); + SLICE_68 SLICE_68( .D1(CO0), .C1(g0_i_a5_2_1), .B1(RASr2), .A1(g3), + .D0(g0_i_a5_1), .C0(N_9), .B0(\S[1] ), .A0(CO0), .M0(RASr2), + .LSR(RCKEEN_8_u_0_1_a1_0), .CLK(RCLK_c), .F0(g0_i_0), .Q0(CO0), .F1(N_9)); + SLICE_69 SLICE_69( .D1(UFMSDI_ens2_i_o2_0_3), .C1(\FS[16] ), .A1(\FS[13] ), + .D0(\FS[4] ), .C0(\FS[11] ), .B0(N_128), .A0(\FS[1] ), .M1(\MAin_c[1] ), + .M0(\MAin_c[0] ), .LSR(Ready_fast), .CLK(nCRAS_c), .F0(N_129), + .Q0(\RowA[0] ), .F1(N_128), .Q1(\RowA[1] )); + SLICE_70 SLICE_70( .D1(\MAin_c[0] ), .C1(C1WR_7), .B1(CMDWR_2), .A1(nFWE_c), + .D0(C1WR), .C0(CMDWR), .A0(ADWR), .F0(N_121), .F1(CMDWR)); + SLICE_71 SLICE_71( .D1(un1_FS_13_i_a2_9_4), .C1(\FS[5] ), + .B1(un1_FS_13_i_a2_9_5), .A1(N_43), .D0(N_94), .C0(un1_FS_14_i_a2_0_1), + .A0(N_134), .F0(N_24), .F1(un1_FS_14_i_a2_0_1)); + SLICE_72 SLICE_72( .D1(N_43), .C1(un1_FS_13_i_a2_9_5), .B1(\FS[5] ), + .A1(un1_FS_13_i_a2_9_4), .D0(N_134), .C0(N_94), .B0(un1_FS_13_i_a2_1), + .F0(N_26), .F1(un1_FS_13_i_a2_1)); + SLICE_73 SLICE_73( .D1(\Din_c[5] ), .C1(XOR8MEG18), .B1(N_36), + .A1(\Din_c[3] ), .D0(CmdEnable), .B0(CMDWR), .M1(\MAin_c[7] ), + .M0(\MAin_c[6] ), .LSR(Ready_fast), .CLK(nCRAS_c), .F0(XOR8MEG18), + .Q0(\RowA[6] ), .F1(CmdSubmitted_1_sqmuxa), .Q1(\RowA[7] )); + SLICE_74 SLICE_74( .D1(\Din_c[6] ), .C1(\Din_c[4] ), .D0(ADWR), .C0(N_180), + .B0(N_156), .A0(N_122_5), .M1(CASr), .M0(nCCAS_c), .CLK(RCLK_c), + .F0(CmdEnable17), .Q0(CASr), .F1(N_156), .Q1(CASr2)); + SLICE_75 SLICE_75( .D1(\Din_c[1] ), .C1(\Din_c[4] ), .B1(\Din_c[2] ), + .A1(\Din_c[3] ), .D0(CmdEnable16_0_a3_4), .C0(CmdEnable16_0_a3_5), + .A0(C1WR), .M1(\Din_c[7] ), .M0(\Din_c[6] ), .CLK(PHI2_c), + .F0(CmdEnable16), .Q0(\Bank[6] ), .F1(CmdEnable16_0_a3_5), .Q1(\Bank[7] )); + SLICE_76 SLICE_76( .D1(\MAin_c[0] ), .C1(\MAin_c[1] ), .B1(\MAin_c[3] ), + .A1(\MAin_c[4] ), .D0(nFWE_c), .C0(C1WR_2_0), .B0(C1WR_7), + .A0(\MAin_c[2] ), .M1(\Din_c[1] ), .M0(\Din_c[0] ), .CLK(PHI2_c), + .F0(C1WR), .Q0(\Bank[0] ), .F1(C1WR_2_0), .Q1(\Bank[1] )); + SLICE_77 SLICE_77( .D1(\Bank[2] ), .C1(\Bank[5] ), .B1(\Bank[7] ), + .A1(\Bank[6] ), .D0(un1_Bank_1_4), .C0(un1_Bank_1_5), .B0(ADWR_8), + .A0(nFWE_c), .F0(ADWR), .F1(un1_Bank_1_5)); + SLICE_78 SLICE_78( .D1(\Din_c[0] ), .C1(\Din_c[2] ), .D0(N_122_5), + .C0(N_180), .B0(N_156), .A0(ADWR_8), .F0(un1_CmdEnable20_0_a3_0_2), + .F1(N_180)); + SLICE_79 SLICE_79( .C1(\MAin_c[6] ), .B1(\MAin_c[7] ), .D0(ADWR_8_2), + .C0(un1_Bank_1_5), .B0(\MAin_c[5] ), .A0(un1_Bank_1_4), .M1(\Din_c[3] ), + .M0(\Din_c[2] ), .CLK(PHI2_c), .F0(C1WR_7), .Q0(\Bank[2] ), .F1(ADWR_8_2), + .Q1(\Bank[3] )); + SLICE_80 SLICE_80( .D1(\FS[17] ), .A1(\FS[11] ), .D0(\FS[10] ), .C0(N_133_3), + .B0(N_133_5), .A0(\FS[13] ), .F0(InitReady3), .F1(N_133_3)); + SLICE_81 SLICE_81( .D1(\MAin_c[4] ), .C1(\MAin_c[1] ), .B1(\MAin_c[5] ), + .A1(\MAin_c[0] ), .D0(\MAin_c[2] ), .C0(ADWR_8_4), .B0(\MAin_c[3] ), + .A0(ADWR_8_2), .F0(ADWR_8), .F1(ADWR_8_4)); + SLICE_82 SLICE_82( .D1(CASr2), .B1(Ready), .A1(CASr3), .D0(CO0), .C0(\S[1] ), + .B0(m6_0_a2_2), .A0(CBR_fast), .M1(\Din_c[3] ), .M0(\Din_c[2] ), + .CLK(nCCAS_c), .F0(G_17_1), .Q0(\WRD[2] ), .F1(m6_0_a2_2), .Q1(\WRD[3] )); + SLICE_83 SLICE_83( .D1(\Din_c[5] ), .C1(\Din_c[7] ), .B1(\Din_c[6] ), + .A1(\Din_c[4] ), .D0(\Din_c[3] ), .C0(\Din_c[0] ), .B0(N_163), + .A0(\Din_c[2] ), .M1(\MAin_c[9] ), .M0(\MAin_c[8] ), .LSR(Ready_fast), + .CLK(nCRAS_c), .F0(XOR8MEG_3_u_0_a3_0_1), .Q0(\RowA[8] ), .F1(N_163), .Q1(\RowA[9] )); - SLICE_81 SLICE_81( .D1(\FS[13] ), .C1(\FS[14] ), .B1(\FS[15] ), - .A1(\FS[17] ), .D0(\FS[13] ), .C0(\FS[17] ), .B0(\FS[15] ), .A0(\FS[12] ), - .M1(nFWE_c), .M0(nFWE_c), .CLK(nCRAS_c), .F0(N_95_5), .Q0(FWEr), - .F1(UFMSDI_ens2_i_o2_0_3), .Q1(FWEr_fast)); - SLICE_82 SLICE_82( .D1(\Din_c[3] ), .C1(N_128), .B1(CmdLEDEN), - .A1(\Din_c[5] ), .D0(XOR8MEG18), .C0(\Din_c[3] ), .B0(N_128), - .A0(\Din_c[5] ), .M0(CASr2), .CLK(RCLK_c), .F0(CmdSubmitted_1_sqmuxa), - .Q0(CASr3), .F1(N_132)); - SLICE_83 SLICE_83( .C1(\IS[1] ), .B1(\IS[3] ), .A1(\IS[2] ), .C0(\IS[1] ), - .B0(\IS[0] ), .A0(\IS[2] ), .M1(\CROW_c[1] ), .M0(\CROW_c[0] ), - .LSR(Ready_fast), .CLK(nCRAS_c), .F0(N_165), .Q0(\RBA_c[0] ), .F1(N_160), + SLICE_84 SLICE_84( .D1(CO0), .C1(FWEr_fast), .B1(CASr3), .A1(CASr2), + .D0(CO0), .C0(FWEr_fast), .B0(CASr3), .A0(CASr2), .M1(\Din_c[1] ), + .M0(\Din_c[0] ), .CLK(nCCAS_c), .F0(g0_i_a5_1_2), .Q0(\WRD[0] ), + .F1(G_1_0), .Q1(\WRD[1] )); + SLICE_85 SLICE_85( .D1(XOR8MEG18), .C1(N_36), .B1(\Din_c[5] ), + .A1(\Din_c[3] ), .D0(\Din_c[3] ), .C0(N_36), .B0(\Din_c[5] ), + .M1(\Din_c[2] ), .M0(\Din_c[1] ), .CE(CmdUFMCLK_1_sqmuxa), .CLK(PHI2_c), + .F0(N_95), .Q0(CmdUFMCLK), .F1(CmdUFMCLK_1_sqmuxa), .Q1(CmdUFMCS)); + SLICE_86 SLICE_86( .D1(\FS[14] ), .C1(\FS[12] ), .B1(\FS[17] ), + .A1(\FS[15] ), .D0(\FS[14] ), .C0(\FS[16] ), .B0(\FS[12] ), .A0(\FS[15] ), + .F0(N_133_5), .F1(UFMSDI_ens2_i_o2_0_3)); + SLICE_87 SLICE_87( .D1(\Din_c[6] ), .C1(\Din_c[5] ), .B1(\Din_c[4] ), + .A1(\Din_c[7] ), .D0(\Din_c[6] ), .C0(\Din_c[5] ), .B0(\Din_c[0] ), + .A0(\Din_c[7] ), .M1(nCCAS_c), .M0(nCCAS_c), .CLK(nCRAS_c), + .F0(CmdEnable16_0_a3_4), .Q0(CBR), .F1(CmdLEDEN_4_u_i_a2_0_0), + .Q1(CBR_fast)); + SLICE_88 SLICE_88( .D1(\Din_c[5] ), .C1(\Din_c[3] ), .B1(\Din_c[7] ), + .A1(\Din_c[1] ), .D0(\Din_c[5] ), .C0(\Din_c[3] ), .B0(N_36), + .M0(\Din_c[0] ), .CE(CmdUFMCLK_1_sqmuxa), .CLK(PHI2_c), .F0(N_45), + .Q0(CmdUFMSDI), .F1(N_122_5)); + SLICE_89 SLICE_89( .D1(\FS[7] ), .C1(\FS[10] ), .B1(\FS[9] ), .A1(\FS[1] ), + .D0(\FS[7] ), .B0(\FS[9] ), .A0(\FS[5] ), .M1(\MAin_c[5] ), + .M0(\MAin_c[4] ), .LSR(Ready_fast), .CLK(nCRAS_c), .F0(N_34), + .Q0(\RowA[4] ), .F1(un1_FS_13_i_a2_9_5), .Q1(\RowA[5] )); + SLICE_90 SLICE_90( .D1(\S[1] ), .A1(CO0), .D0(\S[1] ), .B0(CASr2), .A0(CO0), + .M1(\CROW_c[1] ), .M0(\CROW_c[0] ), .LSR(Ready_fast), .CLK(nCRAS_c), + .F0(RCKEEN_8_u_0_a3_0_0), .Q0(\RBA_c[0] ), .F1(RCKEEN_8_u_0_1_a1_0), .Q1(\RBA_c[1] )); - SLICE_84 SLICE_84( .D1(\FS[6] ), .C1(\FS[10] ), .B1(\FS[11] ), .A1(\FS[8] ), - .D0(\FS[7] ), .C0(\FS[10] ), .B0(\FS[1] ), .A0(\FS[6] ), .F0(N_137_6), - .F1(UFMSDI_ens2_i_a2_4_2)); - SLICE_85 SLICE_85( .D1(\Din_c[4] ), .C1(\Din_c[0] ), .B1(\Din_c[1] ), - .A1(\Din_c[7] ), .D0(\Din_c[5] ), .C0(\Din_c[4] ), .B0(\Din_c[6] ), - .A0(\Din_c[7] ), .M1(\Din_c[3] ), .M0(\Din_c[2] ), .CLK(nCCAS_c), - .F0(un1_Din_4), .Q0(\WRD[2] ), .F1(CmdEnable17_0_a2_3), .Q1(\WRD[3] )); - SLICE_86 SLICE_86( .D1(nRowColSel), .A1(\MAin_c[9] ), .D0(nRowColSel), - .C0(\RowA[9] ), .A0(\MAin_c[9] ), .F0(\RA_c[9] ), .F1(RDQML_c)); - SLICE_87 SLICE_87( .D1(UFMSDI_ens2_i_a0), .B1(N_151), .A1(CmdUFMSDI), - .D0(N_151), .C0(\FS[9] ), .B0(\FS[11] ), .A0(\FS[4] ), .F0(N_137_8), - .F1(UFMSDI_r_xx_mm_1)); - SLICE_88 SLICE_88( .D1(\MAin_c[2] ), .C1(nFWE_c), .B1(\MAin_c[3] ), - .C0(nFWE_c), .A0(nCCAS_c), .M1(\MAin_c[7] ), .M0(\MAin_c[6] ), - .LSR(Ready_fast), .CLK(nCRAS_c), .F0(RD_1_i), .Q0(\RowA[6] ), - .F1(C1WR_0_a2_0_3), .Q1(\RowA[7] )); - SLICE_89 SLICE_89( .D1(nRowColSel), .C1(\MAin_c[9] ), .D0(nRowColSel), - .B0(\MAin_c[8] ), .A0(\RowA[8] ), .F0(\RA_c[8] ), .F1(RDQMH_c)); - SLICE_90 SLICE_90( .D1(\MAin_c[0] ), .C1(\MAin_c[1] ), .B1(N_147), - .D0(\MAin_c[0] ), .B0(\RowA[0] ), .A0(nRowColSel), .F0(\RA_c[0] ), - .F1(un1_CMDWR)); - SLICE_91 SLICE_91( .D1(\MAin_c[7] ), .C1(nRowColSel), .A1(\RowA[7] ), - .D0(\RowA[1] ), .C0(nRowColSel), .B0(\MAin_c[1] ), .F0(\RA_c[1] ), + SLICE_91 SLICE_91( .C1(nRowColSel), .B1(\MAin_c[9] ), .C0(nRowColSel), + .B0(\MAin_c[9] ), .A0(\RowA[9] ), .F0(\RA_c[9] ), .F1(RDQMH_c)); + SLICE_92 SLICE_92( .D1(\IS[3] ), .B1(\IS[2] ), .A1(\IS[1] ), .D0(\IS[0] ), + .C0(RASr2), .B0(\IS[2] ), .A0(\IS[1] ), .F0(m18_0_a3_3), .F1(N_154)); + SLICE_93 SLICE_93( .C1(\RowA[1] ), .B1(\MAin_c[1] ), .A1(nRowColSel), + .D0(\MAin_c[3] ), .C0(\MAin_c[4] ), .B0(\MAin_c[1] ), .A0(\MAin_c[2] ), + .M1(\Din_c[5] ), .M0(\Din_c[4] ), .CLK(PHI2_c), .F0(CMDWR_2), + .Q0(\Bank[4] ), .F1(\RA_c[1] ), .Q1(\Bank[5] )); + SLICE_94 SLICE_94( .D1(\FS[6] ), .C1(\FS[10] ), .B1(\FS[11] ), .A1(\FS[8] ), + .D0(\FS[6] ), .C0(\FS[0] ), .B0(\FS[2] ), .A0(\FS[3] ), + .F0(un1_FS_13_i_a2_9_4), .F1(UFMSDI_ens2_i_a2_4_2)); + SLICE_95 SLICE_95( .D1(\S[1] ), .B1(InitReady), .D0(\S[1] ), .C0(RASr2), + .B0(\IS[3] ), .A0(CO0), .M1(RASr), .M0(nCRAS_c), .CLK(RCLK_c), + .F0(Ready_0_sqmuxa_0_a3_2), .Q0(RASr), .F1(g0_i_a5_2_1), .Q1(RASr2)); + SLICE_96 SLICE_96( .D1(nRowColSel), .B1(\MAin_c[9] ), .D0(nRowColSel), + .C0(\RowA[8] ), .A0(\MAin_c[8] ), .F0(\RA_c[8] ), .F1(RDQML_c)); + SLICE_97 SLICE_97( .D1(\MAin_c[0] ), .C1(\RowA[0] ), .A1(nRowColSel), + .D0(nRowColSel), .C0(\MAin_c[3] ), .A0(\RowA[3] ), .F0(\RA_c[3] ), + .F1(\RA_c[0] )); + SLICE_98 SLICE_98( .D1(\RowA[2] ), .B1(nRowColSel), .A1(\MAin_c[2] ), + .C0(\MAin_c[4] ), .B0(\RowA[4] ), .A0(nRowColSel), .F0(\RA_c[4] ), + .F1(\RA_c[2] )); + SLICE_99 SLICE_99( .D1(nRowColSel), .C1(\MAin_c[7] ), .B1(\RowA[7] ), + .D0(\MAin_c[5] ), .C0(\RowA[5] ), .B0(nRowColSel), .F0(\RA_c[5] ), .F1(\RA_c[7] )); - SLICE_92 SLICE_92( .D1(\RowA[6] ), .C1(nRowColSel), .A1(\MAin_c[6] ), - .D0(\MAin_c[2] ), .C0(nRowColSel), .B0(\RowA[2] ), .F0(\RA_c[2] ), - .F1(\RA_c[6] )); - SLICE_93 SLICE_93( .C1(\MAin_c[5] ), .B1(\RowA[5] ), .A1(nRowColSel), - .D0(\MAin_c[3] ), .B0(nRowColSel), .A0(\RowA[3] ), .F0(\RA_c[3] ), - .F1(\RA_c[5] )); - SLICE_94 SLICE_94( .B1(N_155), .A1(Ready), .C0(\S[1] ), .A0(Ready), - .M0(\IS[0] ), .LSR(RA10s_i), .CLK(RCLK_c), .F0(RCKEEN_8_u_0_a2_1_out), - .Q0(\RA_c[10] ), .F1(N_159_i)); + SLICE_100 SLICE_100( .D1(nFWE_c), .C1(nCCAS_c), .D0(\Bank[0] ), + .C0(\Bank[4] ), .B0(\Bank[3] ), .A0(\Bank[1] ), .F0(un1_Bank_1_4), + .F1(RD_1_i)); + SLICE_101 SLICE_101( .D1(nRowColSel), .C1(\MAin_c[6] ), .B1(\RowA[6] ), + .D0(N_148), .B0(Ready), .M1(nFWE_c), .M0(nFWE_c), .CLK(nCRAS_c), + .F0(N_153_i), .Q0(FWEr), .F1(\RA_c[6] ), .Q1(FWEr_fast)); RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .PADDT(RD_1_i), .PADDO(\WRD[0] ), .RD0(RD[0])); Dout_0_ \Dout[0]_I ( .PADDO(\RD_in[0] ), .Dout0(Dout[0])); @@ -659,22 +682,19 @@ module SLICE_8 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO ); endmodule -module SLICE_9 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, - F1 ); - wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly; +module SLICE_9 ( input D1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly; - lut4 CmdEnable17_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut4 ADSubmitted_r_RNO( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); lut40002 ADSubmitted_r( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre ADSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); specify (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); @@ -690,12 +710,12 @@ endmodule module lut4 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hFFAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40002 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h3130) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0B0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module inverter ( input I, output Z ); @@ -703,21 +723,22 @@ module inverter ( input I, output Z ); INV INST1( .A(I), .Z(Z)); endmodule -module SLICE_14 ( input D1, C1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, - F1 ); - wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly; +module SLICE_14 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, + Q0, F1 ); + wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly; - lut40003 CmdEnable16_0_a2( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); + lut40003 CmdEnable_s_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40004 C1Submitted_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre C1Submitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); @@ -733,119 +754,29 @@ endmodule module lut40003 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hA000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0301) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40004 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hF4FC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hCCDC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_19 ( input D1, C1, B1, A1, C0, A0, DI0, LSR, CLK, output F0, Q0, - F1 ); - wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; +module SLICE_20 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, + Q0, F1 ); + wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly; - lut40005 Ready_0_sqmuxa_0_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40006 \S_RNO[0] ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0007 \S[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40005 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40006 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'hF5F5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module vmuxregsre0007 ( input D0, D1, SD, SP, CK, LSR, output Q ); - - FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module SLICE_20 ( input B1, A1, D0, C0, B0, A0, DI0, M0, CLK, output OFX0, Q0 ); - wire GNDI, \SLICE_20/SLICE_20_K1_H1 , \SLICE_20/CmdEnable_s/GATE_H0 , VCCI, - CLK_NOTIN, DI0_dly, CLK_dly; - - lut40008 SLICE_20_K1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(\SLICE_20/SLICE_20_K1_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40009 \CmdEnable_s/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(\SLICE_20/CmdEnable_s/GATE_H0 )); + lut40005 CmdEnable_0_sqmuxa( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40006 CmdEnable_s( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre CmdEnable( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - selmux2 SLICE_20_K0K1MUX( .D0(\SLICE_20/CmdEnable_s/GATE_H0 ), - .D1(\SLICE_20/SLICE_20_K1_H1 ), .SD(M0), .Z(OFX0)); - - specify - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (D0 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - endspecify - -endmodule - -module lut40008 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40009 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'hEA0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module selmux2 ( input D0, D1, SD, output Z ); - - MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z)); -endmodule - -module SLICE_21 ( input D1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, - Q0, F1 ); - wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; - - lut40010 Cmdn8MEGEN_4_u_i_a2_2( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40011 CmdLEDEN_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre CmdLEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); @@ -856,26 +787,64 @@ module SLICE_21 ( input D1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + endspecify + +endmodule + +module lut40005 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40006 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFEF4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_21 ( input D1, C1, B1, A1, D0, C0, B0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; + + lut40007 CmdLEDEN_4_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40008 CmdLEDEN_RNO( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CmdLEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule -module lut40010 ( input A, B, C, D, output Z ); +module lut40007 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0044) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h44F4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40011 ( input A, B, C, D, output Z ); +module lut40008 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0023) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0C0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_22 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 ); +module SLICE_22 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly; - lut40012 un1_FS_14_i_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40013 CmdSubmitted_RNO( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); + lut40009 un1_FS_14_i_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40010 CmdSubmitted_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre CmdSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); @@ -887,7 +856,7 @@ module SLICE_22 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 ); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); @@ -897,22 +866,22 @@ module SLICE_22 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 ); endmodule -module lut40012 ( input A, B, C, D, output Z ); +module lut40009 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40013 ( input A, B, C, D, output Z ); +module lut40010 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hFAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_26 ( input D1, C1, B1, A1, D0, C0, A0, DI0, CE, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; - lut40014 Cmdn8MEGEN_4_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40015 Cmdn8MEGEN_RNO( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + lut40011 Cmdn8MEGEN_4_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40012 Cmdn8MEGEN_RNO( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre Cmdn8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); @@ -936,60 +905,63 @@ module SLICE_26 ( input D1, C1, B1, A1, D0, C0, A0, DI0, CE, CLK, output F0, endmodule -module lut40014 ( input A, B, C, D, output Z ); +module lut40011 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h33AB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hAE0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40015 ( input A, B, C, D, output Z ); +module lut40012 ( input A, B, C, D, output Z ); ROM16X1 #(16'h0F05) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_29 ( input D1, C1, B1, A1, D0, B0, A0, DI0, CLK, output F0, Q0, - F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly; +module SLICE_29 ( input D1, C1, A1, D0, C0, A0, DI0, M1, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; - lut40016 nRRAS_5_u_i( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40017 \IS_RNO[0] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); + lut40013 Ready_0_sqmuxa_0_o2( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); + lut40014 \IS_RNO[0] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CASr3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre \IS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module lut40016 ( input A, B, C, D, output Z ); +module lut40013 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hFF54) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h5FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40017 ( input A, B, C, D, output Z ); +module lut40014 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hEE11) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hAAA5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_30 ( input D1, B1, A1, D0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40018 \IS_RNO[2] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + lut40015 \IS_RNO[2] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40019 IS_n1_0_x2( .A(A0), .B(GNDI), .C(GNDI), .D(D0), .Z(F0)); + lut40016 IS_n1_0_x2( .A(A0), .B(GNDI), .C(GNDI), .D(D0), .Z(F0)); vmuxregsre \IS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1013,12 +985,12 @@ module SLICE_30 ( input D1, B1, A1, D0, A0, DI1, DI0, CE, CLK, output F0, Q0, endmodule -module lut40018 ( input A, B, C, D, output Z ); +module lut40015 ( input A, B, C, D, output Z ); ROM16X1 #(16'h66AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40019 ( input A, B, C, D, output Z ); +module lut40016 ( input A, B, C, D, output Z ); ROM16X1 #(16'h55AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule @@ -1027,8 +999,8 @@ module SLICE_31 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; - lut40020 RA10_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40021 \IS_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40017 RA10_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40018 \IS_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \IS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1052,21 +1024,21 @@ module SLICE_31 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output endmodule -module lut40020 ( input A, B, C, D, output Z ); +module lut40017 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hFFFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hFFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40021 ( input A, B, C, D, output Z ); +module lut40018 ( input A, B, C, D, output Z ); ROM16X1 #(16'h6AAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_32 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); +module SLICE_32 ( input D1, C1, B1, A1, D0, A0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly; - lut40022 UFMSDI_ens2_i_a0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40023 InitReady_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40019 UFMSDI_ens2_i_a0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut4 InitReady_RNO( .A(A0), .B(GNDI), .C(GNDI), .D(D0), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre InitReady( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); @@ -1077,7 +1049,7 @@ module SLICE_32 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); @@ -1087,23 +1059,18 @@ module SLICE_32 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); endmodule -module lut40022 ( input A, B, C, D, output Z ); +module lut40019 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h5155) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h3313) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40023 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_33 ( input D1, C1, A1, D0, C0, A0, DI0, CE, CLK, output F0, Q0, - F1 ); +module SLICE_33 ( input D1, C1, B1, A1, D0, C0, B0, DI0, CE, CLK, output F0, + Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - lut40024 LED_pad_RNO( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + lut40020 LED_pad_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40021 LEDEN_5_i_m2( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40025 LEDEN_5_i_m2( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); vmuxregsre LEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1111,10 +1078,11 @@ module SLICE_33 ( input D1, C1, A1, D0, C0, A0, DI0, CE, CLK, output F0, Q0, specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); @@ -1124,32 +1092,77 @@ module SLICE_33 ( input D1, C1, A1, D0, C0, A0, DI0, CE, CLK, output F0, Q0, endmodule -module lut40024 ( input A, B, C, D, output Z ); +module lut40020 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hFFAF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hFBFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40025 ( input A, B, C, D, output Z ); +module lut40021 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hA0AF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hF303) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_39 ( input D1, A1, D0, C0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); +module SLICE_38 ( input D1, C1, B1, A1, D0, B0, DI0, LSR, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; + + lut40022 nRCS_RNO_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40023 RA10_2_sqmuxa_0_o2( .A(GNDI), .B(B0), .C(GNDI), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0024 RA10( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40022 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40023 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFFCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0024 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3JY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module SLICE_39 ( input D1, B1, A1, D0, B0, A0, DI0, LSR, CLK, output F0, Q0, + F1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; - lut40026 XOR8MEG_3_u_0_a3_0( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1)); + lut40025 Cmdn8MEGEN_4_u_i_o2_0( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40027 RA11_2( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0007 RA11( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + lut40026 RA11_2( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); + vmuxregsre0027 RA11( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); @@ -1160,22 +1173,28 @@ module SLICE_39 ( input D1, A1, D0, C0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); endmodule -module lut40026 ( input A, B, C, D, output Z ); +module lut40025 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h00AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hFFBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40027 ( input A, B, C, D, output Z ); +module lut40026 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hA5AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hDD22) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0027 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; endmodule module SLICE_41 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, DI0_dly, CLK_dly, M1_dly; - lut40028 RCKEEN_8_u_1_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40029 RCKEEN_8_u( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40028 RCKEEN_8_u_0_1_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40029 RCKEEN_8_u_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre PHI2r2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1204,29 +1223,28 @@ endmodule module lut40028 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h2DAD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h45CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40029 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hCCEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hCCCE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_42 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output - F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, M1_dly; +module SLICE_42 ( input C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; - lut40030 nRWE_RNO_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40030 nRCS_RNO_3( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); lut40031 RCKE_2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre PHI2r( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre RCKE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -1246,19 +1264,19 @@ endmodule module lut40030 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hE0E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40031 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hFE50) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hFE22) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_43 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, DI0_dly, CLK_dly, M1_dly; - lut40032 RCKEEN_8_u_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40032 RCKEEN_8_u_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40033 Ready_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre PHI2r3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); @@ -1288,24 +1306,23 @@ endmodule module lut40032 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h3704) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h5072) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40033 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hF2F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hAAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_44 ( input D1, C1, B1, A1, C0, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, M1_NOTIN, VCCI, DI0_dly, CLK_dly, M1_dly; + wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; lut40034 Ready_0_sqmuxa_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40013 Ready_fast_RNO( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); + lut40035 Ready_fast_RNO( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre RASr( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN)); + vmuxregsre RASr3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre Ready_fast( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); @@ -1329,16 +1346,21 @@ endmodule module lut40034 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_50 ( input D1, C1, B1, C0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); +module lut40035 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_50 ( input D1, C1, A1, C0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; - lut40035 nRowColSel_RNO( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40036 nRowColSel_RNO( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40013 \S_0_i_o2[1] ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0007 \S[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + lut40035 \S_0_i_o2[1] ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0027 \S[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); @@ -1346,7 +1368,7 @@ module SLICE_50 ( input D1, C1, B1, C0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); @@ -1358,23 +1380,21 @@ module SLICE_50 ( input D1, C1, B1, C0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); endmodule -module lut40035 ( input A, B, C, D, output Z ); +module lut40036 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0050) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output - F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, M1_dly; +module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, + Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly; - lut40036 UFMCLK_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40037 UFMCLK_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre RASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); + lut40037 UFMCLK_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40038 UFMCLK_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre UFMCLK( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -1386,37 +1406,33 @@ module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module lut40036 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'hABEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40037 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h1302) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hFF47) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output - F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, M1_dly; +module lut40038 ( input A, B, C, D, output Z ); - lut40038 PHI2r3_RNITCN41( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40039 UFMSDI_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre RASr3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); + ROM16X1 #(16'h003A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, + Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly; + + lut40039 PHI2r3_RNITCN41( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40040 UFMSDI_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre UFMSDI( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -1428,29 +1444,27 @@ module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module lut40038 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h33B3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40039 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h5404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h3B33) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_55 ( input D0, B0, A0, M1, M0, CLK, output F0, Q0, Q1 ); +module lut40040 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0E02) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_55 ( input D0, C0, B0, M1, M0, CLK, output F0, Q0, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; - lut40040 \un9_RA[4] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); + lut40041 UFMSDI_RNO_0( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \WRD[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); @@ -1460,43 +1474,6 @@ module SLICE_55 ( input D0, B0, A0, M1, M0, CLK, output F0, Q0, Q1 ); .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify - (D0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - endspecify - -endmodule - -module lut40040 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'hEE22) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_56 ( input D1, C1, B1, A1, D0, C0, B0, M1, M0, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; - - lut40041 C1WR_0_a2_0_11( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40042 UFMSDI_ens2_i_o2( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \WRD[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - vmuxregsre \WRD[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); @@ -1512,31 +1489,62 @@ endmodule module lut40041 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h00FC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_56 ( input C1, A1, C0, A0, M1, M0, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40042 un1_FS_14_i_o2( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40043 nRCS_9_u_i_a2( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \WRD[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre \WRD[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + endmodule module lut40042 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h3C0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h5F5F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output - F0, Q0, F1 ); - wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly; +module lut40043 ( input A, B, C, D, output Z ); - lut40043 XOR8MEG_3_u_0_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40044 XOR8MEG_3_u_0_a3_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + ROM16X1 #(16'h0505) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_57 ( input D1, B1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; + + lut40044 XOR8MEG_3_u_0_a3( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40045 XOR8MEG_3_u_0_a3_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre XOR8MEG( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); specify (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); @@ -1550,23 +1558,23 @@ module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output endmodule -module lut40043 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40044 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hBAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hCC00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_58 ( input D1, C1, A1, D0, C0, B0, DI0, CE, CLK, output F0, Q0, +module lut40045 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hF4FC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_58 ( input D1, C1, A1, D0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - lut40045 UFMSDI_en_ss0_0_a2_0( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + lut40046 UFMSDI_en_ss0_0_a2_0( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40046 n8MEGEN_5_i_m2( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40047 n8MEGEN_5_i_m2( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); vmuxregsre n8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1576,8 +1584,8 @@ module SLICE_58 ( input D1, C1, A1, D0, C0, B0, DI0, CE, CLK, output F0, Q0, (C1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); @@ -1587,30 +1595,29 @@ module SLICE_58 ( input D1, C1, A1, D0, C0, B0, DI0, CE, CLK, output F0, Q0, endmodule -module lut40045 ( input A, B, C, D, output Z ); +module lut40046 ( input A, B, C, D, output Z ); ROM16X1 #(16'h0005) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40046 ( input A, B, C, D, output Z ); +module lut40047 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hC0CF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hBB11) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, - Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly; +module SLICE_59 ( input D1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly; - lut40047 un1_nRCAS_6_sqmuxa_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40048 nRCAS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0049 nRCAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + lut40048 nRCAS_RNO_1( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40049 nRCAS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0050 nRCAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); specify (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); @@ -1625,36 +1632,35 @@ module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, endmodule -module lut40047 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h3F1D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40048 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h5510) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0077) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module vmuxregsre0049 ( input D0, D1, SD, SP, CK, LSR, output Q ); +module lut40049 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0703) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0050 ( input D0, D1, SD, SP, CK, LSR, output Q ); FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); defparam INST01.GSR = "DISABLED"; endmodule -module SLICE_60 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, - Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly; +module SLICE_60 ( input D1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly; - lut40050 nRCS_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40051 nRCS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0049 nRCS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + lut40051 RCKEEN_8_u_0_a2_0_m1_0_a2( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40052 nRCS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0050 nRCS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); specify (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); @@ -1669,23 +1675,23 @@ module SLICE_60 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, endmodule -module lut40050 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'hBFF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40051 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h3233) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h4400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40052 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h001F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_61 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire VCCI, GNDI, DI0_dly, CLK_dly; - lut40052 nRRAS_5_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40053 nRRAS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0049 nRRAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + lut40053 nRRAS_5_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40054 nRRAS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0050 nRRAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); @@ -1707,23 +1713,23 @@ module SLICE_61 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, endmodule -module lut40052 ( input A, B, C, D, output Z ); +module lut40053 ( input A, B, C, D, output Z ); ROM16X1 #(16'h00C8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40053 ( input A, B, C, D, output Z ); +module lut40054 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h3031) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0F01) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire VCCI, GNDI, DI0_dly, CLK_dly; - lut40054 nRCAS_0_sqmuxa_1_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40055 nRWE_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0049 nRWE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + lut40055 nRCAS_0_sqmuxa_1_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40056 nRWE_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0050 nRWE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); @@ -1745,23 +1751,23 @@ module SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, endmodule -module lut40054 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40055 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hF2F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40056 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hF1FD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); wire VCCI, DI0_dly, CLK_dly, LSR_dly; - lut40056 nRowColSel_0_0_a3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40057 nRowColSel_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0007 nRowColSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + lut40057 nRowColSel_0_0_a3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40058 nRowColSel_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0027 nRowColSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1783,23 +1789,23 @@ module SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output endmodule -module lut40056 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40057 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hF4F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40058 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hBAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_64 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire VCCI, GNDI, DI0_dly, CLK_dly; - lut40058 nUFMCS15_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40059 nUFMCS_s_0_N_5_i( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0049 nUFMCS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + lut40059 nUFMCS15_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40060 nUFMCS_s_0_N_5_i( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0050 nUFMCS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); @@ -1821,14 +1827,14 @@ module SLICE_64 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, endmodule -module lut40058 ( input A, B, C, D, output Z ); +module lut40059 ( input A, B, C, D, output Z ); ROM16X1 #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40059 ( input A, B, C, D, output Z ); +module lut40060 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hDDFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hF5FC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module nRWE_RNO_1_SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, output @@ -1836,9 +1842,9 @@ module nRWE_RNO_1_SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, output wire \nRWE_RNO_1/SLICE_65/nRWE_RNO_1/SLICE_65_K1_H1 , \nRWE_RNO_1/SLICE_65/nRWE_RNO_1/GATE_H0 ; - lut40060 \nRWE_RNO_1/SLICE_65_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40061 \nRWE_RNO_1/SLICE_65_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/SLICE_65_K1_H1 )); - lut40061 \nRWE_RNO_1/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40062 \nRWE_RNO_1/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/GATE_H0 )); selmux2 \nRWE_RNO_1/SLICE_65_K0K1MUX ( .D0(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/GATE_H0 ), @@ -1858,79 +1864,67 @@ module nRWE_RNO_1_SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, output endmodule -module lut40060 ( input A, B, C, D, output Z ); +module lut40061 ( input A, B, C, D, output Z ); ROM16X1 #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40061 ( input A, B, C, D, output Z ); +module lut40062 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_66 ( input D1, C1, B1, D0, C0, B0, A0, M1, M0, LSR, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; +module selmux2 ( input D0, D1, SD, output Z ); - lut40062 nUFMCS_s_0_N_5_i_N_2L1( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40063 UFMCLK_r_i_a2_2_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0007 \RowA[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0007 \RowA[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z)); +endmodule + +module SLICE_66 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40063 IS_0_sqmuxa_0_o2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40064 un1_nRCAS_6_sqmuxa_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module lut40062 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h0F03) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40063 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hFFBF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_67 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; +module lut40064 ( input A, B, C, D, output Z ); - lut40064 CmdUFMCLK_1_sqmuxa_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40065 XOR8MEG18_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0066 \RowA[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + ROM16X1 #(16'h33F5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_67 ( input D1, C1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40065 nUFMCS_s_0_N_5_i_N_2L1( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40066 UFMCLK_r_i_a2_2_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0027 \RowA[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0007 \RowA[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + vmuxregsre0027 \RowA[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); @@ -1947,26 +1941,26 @@ module SLICE_67 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, endmodule -module lut40064 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40065 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0A0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module vmuxregsre0066 ( input D0, D1, SD, SP, CK, LSR, output Q ); +module lut40066 ( input A, B, C, D, output Z ); - FL1P3JY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; + ROM16X1 #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, LSR, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, M0_dly, CLK_dly, LSR_dly; - lut40067 un1_FS_14_i_a2_0_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40068 un1_FS_14_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40067 nRCS_RNO_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40068 nRCS_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0027 \S[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -1977,24 +1971,133 @@ module SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule module lut40067 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40068 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hF8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hF1F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_69 ( input D1, C1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - lut40069 un1_FS_13_i_a2_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40070 un1_FS_13_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40069 UFMSDI_ens2_i_o2_0( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40070 UFMCLK_RNO_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0027 \RowA[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0027 \RowA[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40069 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFFFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40070 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hB888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_70 ( input D1, C1, B1, A1, D0, C0, A0, output F0, F1 ); + wire GNDI; + + lut40071 CMDWR( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40072 un1_CmdEnable20_0_a3( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40071 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40072 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0005) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_71 ( input D1, C1, B1, A1, D0, C0, A0, output F0, F1 ); + wire GNDI; + + lut40073 un1_FS_14_i_a2_0_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40074 un1_FS_14_i_0( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40073 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40074 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_72 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 ); + wire GNDI; + + lut40075 un1_FS_13_i_a2_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40076 un1_FS_13_i_0( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -2004,74 +2107,158 @@ module SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule -module lut40069 ( input A, B, C, D, output Z ); +module lut40075 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40070 ( input A, B, C, D, output Z ); +module lut40076 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hF8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hFFC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_70 ( input D1, C1, B1, A1, C0, A0, M1, M0, CLK, output F0, Q0, F1, +module SLICE_73 ( input D1, C1, B1, A1, D0, B0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40077 CmdSubmitted_1_sqmuxa_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40078 XOR8MEG18( .A(GNDI), .B(B0), .C(GNDI), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0027 \RowA[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0027 \RowA[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40077 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h1030) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40078 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hCC00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_74 ( input D1, C1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M0_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40079 CmdEnable17_0_o2( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40080 CmdEnable17_0_a3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre CASr( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40079 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFFF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40080 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_75 ( input D1, C1, B1, A1, D0, C0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; - lut40071 C1WR_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40072 C1WR_0_a2( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); + lut40081 CmdEnable16_0_a3_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40082 CmdEnable16_0_a3( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \Bank[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \Bank[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40081 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40082 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hA000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_76 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly; + + lut40083 C1WR_2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40084 C1WR( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \Bank[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \Bank[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40071 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40072 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'hA0A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_71 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, - Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly; - - lut40073 C1WR_0_a2_0_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40074 C1WR_0_a2_0_10( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \Bank[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \Bank[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); @@ -2091,34 +2278,224 @@ module SLICE_71 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, endmodule -module lut40073 ( input A, B, C, D, output Z ); +module lut40083 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40074 ( input A, B, C, D, output Z ); +module lut40084 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_72 ( input D1, C1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; +module SLICE_77 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40075 UFMSDI_ens2_i_o2_0( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + lut40085 un1_Bank_1_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40086 ADWR( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40085 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40086 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_78 ( input D1, C1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40087 CmdEnable17_0_a2( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40076 UFMCLK_r_i_m2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0007 \RowA[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + lut40088 un1_CmdEnable20_0_a3_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40087 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hF000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40088 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_79 ( input C1, B1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40089 ADWR_8_2( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40090 C1WR_7( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \Bank[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \Bank[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40089 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hC0C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40090 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_80 ( input D1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40091 InitReady3_0_a2_3( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40092 InitReady3_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40091 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hAA00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40092 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40093 ADWR_8_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40093 ADWR_8( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40093 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_82 ( input D1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40094 nRWE_RNO_2( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40095 nRWE_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \WRD[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre \WRD[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module lut40094 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h4400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40095 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_83 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40096 XOR8MEG_3_u_0_o2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40097 XOR8MEG_3_u_0_a3_0_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0024 \RowA[9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0007 \RowA[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + vmuxregsre0027 \RowA[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); @@ -2135,22 +2512,65 @@ module SLICE_72 ( input D1, C1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output endmodule -module lut40075 ( input A, B, C, D, output Z ); +module lut40096 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hFFFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40076 ( input A, B, C, D, output Z ); +module lut40097 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hACA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_73 ( input D1, C1, B1, A1, C0, A0, M1, M0, CE, CLK, output F0, Q0, - F1, Q1 ); +module SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40098 nRCAS_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40099 nRCS_RNO_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \WRD[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre \WRD[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module lut40098 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h200F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40099 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; - lut40077 IS_0_sqmuxa_0_o2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40013 IS_0_sqmuxa_0_o2( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); + lut40100 CmdUFMCLK_1_sqmuxa_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40101 Cmdn8MEGEN_4_u_i_a2_2( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre CmdUFMCS( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); @@ -2164,8 +2584,9 @@ module SLICE_73 ( input D1, C1, B1, A1, C0, A0, M1, M0, CE, CLK, output F0, Q0, (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); @@ -2177,180 +2598,55 @@ module SLICE_73 ( input D1, C1, B1, A1, C0, A0, M1, M0, CE, CLK, output F0, Q0, endmodule -module lut40077 ( input A, B, C, D, output Z ); +module lut40100 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hFBFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_74 ( input B1, A1, D0, C0, B0, A0, M0, CE, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; +module lut40101 ( input A, B, C, D, output Z ); - lut40078 InitReady3_0_a2_3( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40079 InitReady3_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre CmdUFMSDI( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + ROM16X1 #(16'h000C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_86 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40102 UFMSDI_ens2_i_o2_0_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40103 InitReady3_0_a2_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule -module lut40078 ( input A, B, C, D, output Z ); +module lut40102 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40079 ( input A, B, C, D, output Z ); +module lut40103 ( input A, B, C, D, output Z ); ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_75 ( input D1, B1, A1, D0, C0, B0, M1, M0, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, M0_NOTIN, M1_dly, CLK_dly, M0_dly; +module SLICE_87 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, + Q0, F1, Q1 ); + wire M1_NOTIN, VCCI, GNDI, CLK_NOTIN, M0_NOTIN, M1_dly, CLK_dly, M0_dly; - lut40080 Cmdn8MEGEN_4_u_i_o2_0( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40081 CmdLEDEN_4_u_i_a2_0( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre CASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre CASr( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40080 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'hFFDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40081 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h0003) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_76 ( input D1, B1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; - - lut40082 CmdEnable16_0_a2_4( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40083 CmdEnable16_0_a2_4_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \Bank[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \Bank[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40082 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h3300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40083 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_77 ( input D1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; - - lut40084 CmdEnable16_0_a2_1( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40085 CmdEnable16_0_a2_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \Bank[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \Bank[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40084 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h00AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40085 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_78 ( input D1, B1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, M1_NOTIN, VCCI, CLK_NOTIN, M0_NOTIN, M1_dly, CLK_dly, M0_dly; - - lut40086 CmdEnable17_0_o2( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40087 CmdEnable17_0_a2_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40104 CmdLEDEN_4_u_i_a2_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40105 CmdEnable16_0_a3_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre CBR_fast( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN)); vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre CBR( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); @@ -2358,47 +2654,7 @@ module SLICE_78 ( input D1, B1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, specify (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - endspecify - -endmodule - -module lut40086 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h33FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40087 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_79 ( input D1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; - - lut40088 nRWE_RNO_2( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40089 nRWE_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \WRD[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - vmuxregsre \WRD[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); @@ -2415,36 +2671,76 @@ module SLICE_79 ( input D1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, endmodule -module lut40088 ( input A, B, C, D, output Z ); +module lut40104 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0088) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40089 ( input A, B, C, D, output Z ); +module lut40105 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_88 ( input D1, C1, B1, A1, D0, C0, B0, M0, CE, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; + + lut40106 CmdEnable17_0_a3_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40107 Cmdn8MEGEN_4_u_i_o2( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CmdUFMSDI( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40106 ( input A, B, C, D, output Z ); ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_80 ( input D1, B1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, - Q0, F1, Q1 ); +module lut40107 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFCCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_89 ( input D1, C1, B1, A1, D0, B0, A0, M1, M0, LSR, CLK, output + F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - lut40082 nRCAS_RNO_1( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + lut40108 un1_FS_13_i_a2_9_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40109 UFMSDI_ens2_i_o2( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40090 nRCAS_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0066 \RowA[9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + vmuxregsre0024 \RowA[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0007 \RowA[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + vmuxregsre0027 \RowA[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); @@ -2458,22 +2754,370 @@ module SLICE_80 ( input D1, B1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, endmodule -module lut40090 ( input A, B, C, D, output Z ); +module lut40108 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h4005) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, - Q0, F1, Q1 ); - wire M1_NOTIN, VCCI, GNDI, CLK_NOTIN, M0_NOTIN, M1_dly, CLK_dly, M0_dly; +module lut40109 ( input A, B, C, D, output Z ); - lut40091 UFMSDI_ens2_i_o2_0_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40092 InitReady3_0_a2_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + ROM16X1 #(16'h3388) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_90 ( input D1, A1, D0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40110 RCKEEN_8_u_0_1_a1_0( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40111 RCKEEN_8_u_0_a3_0_0( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); + vmuxregsre0027 \RBA[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0027 \RBA[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40110 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h00AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40111 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h7700) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_91 ( input C1, B1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40112 RDQMH( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40113 \un9_RA[9] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40112 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hCFCF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40113 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hCACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_92 ( input D1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40114 un1_nRCAS_6_sqmuxa_i_o2( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40115 nRWE_RNO_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40114 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFFEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40115 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_93 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40116 \un9_RA[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40117 CMDWR_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \Bank[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \Bank[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40116 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hD8D8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40117 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_94 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40118 UFMSDI_ens2_i_a2_4_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40119 un1_FS_13_i_a2_9_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40118 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40119 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_95 ( input D1, B1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M0_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40120 nRCS_RNO_4( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40121 Ready_0_sqmuxa_0_a3_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre RASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre RASr( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40120 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h00CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40121 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_96 ( input D1, B1, D0, C0, A0, output F0, F1 ); + wire GNDI; + + lut40122 RDQML( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40123 \un9_RA[8] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40122 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h33FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40123 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hAAF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_97 ( input D1, C1, A1, D0, C0, A0, output F0, F1 ); + wire GNDI; + + lut40124 \un9_RA[0] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40125 \un9_RA[3] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40124 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFA50) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40125 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hF0AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_98 ( input D1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40126 \un9_RA[2] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40127 \un9_RA[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40126 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hBB88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40127 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hE4E4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_99 ( input D1, C1, B1, D0, C0, B0, output F0, F1 ); + wire GNDI; + + lut40128 \un9_RA[7] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40129 \un9_RA[5] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40128 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hF0CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40129 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFC30) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_100 ( input D1, C1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40079 nCCAS_pad_RNI01SJ( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40130 un1_Bank_1_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40130 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_101 ( input D1, C1, B1, D0, B0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, M1_NOTIN, VCCI, CLK_NOTIN, M0_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40128 \un9_RA[6] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40131 IS_0_sqmuxa_0_o2_0_RNIS63D( .A(GNDI), .B(B0), .C(GNDI), .D(D0), + .Z(F0)); vmuxregsre FWEr_fast( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre FWEr( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); @@ -2483,11 +3127,8 @@ module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); @@ -2498,429 +3139,9 @@ module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, endmodule -module lut40091 ( input A, B, C, D, output Z ); +module lut40131 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40092 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_82 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0, - F1 ); - wire VCCI, GNDI, M0_dly, CLK_dly; - - lut40093 CmdLEDEN_4_u_i_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40094 CmdSubmitted_1_sqmuxa_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre CASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40093 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h3230) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40094 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h1300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_83 ( input C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40095 un1_nRCAS_6_sqmuxa_i_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40096 Ready_0_sqmuxa_0_o2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0007 \RBA[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0007 \RBA[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40095 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40096 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40097 UFMSDI_ens2_i_a2_4_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40098 un1_FS_13_i_a2_6( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40097 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40098 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, - Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; - - lut40099 CmdEnable17_0_a2_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40100 un1_Din_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \WRD[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - vmuxregsre \WRD[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - endspecify - -endmodule - -module lut40099 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40100 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_86 ( input D1, A1, D0, C0, A0, output F0, F1 ); - wire GNDI; - - lut40101 RDQML( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40102 \un9_RA[9] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40101 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h55FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40102 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'hAAF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_87 ( input D1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40103 UFMSDI_RNO_0( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40104 un1_FS_13_i_a2_8( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40103 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h00EE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40104 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_88 ( input D1, C1, B1, C0, A0, M1, M0, LSR, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40105 C1WR_0_a2_0_3( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40106 nCCAS_pad_RNI01SJ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0007 \RowA[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0007 \RowA[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40105 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h0C00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40106 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'hFAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_89 ( input D1, C1, D0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40107 RDQMH( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40108 \un9_RA[8] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40107 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'hF0FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40108 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'hCCAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_90 ( input D1, C1, B1, D0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40109 un1_CMDWR( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40110 \un9_RA[0] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40109 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'hCCC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40110 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'hEE44) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_91 ( input D1, C1, A1, D0, C0, B0, output F0, F1 ); - wire GNDI; - - lut40111 \un9_RA[7] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40112 \un9_RA[1] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40111 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'hFA0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40112 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'hCFC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_92 ( input D1, C1, A1, D0, C0, B0, output F0, F1 ); - wire GNDI; - - lut40113 \un9_RA[6] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40114 \un9_RA[2] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40113 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'hAFA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40114 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'hFC0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_93 ( input C1, B1, A1, D0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40115 \un9_RA[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40040 \un9_RA[3] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40115 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'hE4E4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_94 ( input B1, A1, C0, A0, M0, LSR, CLK, output F0, Q0, F1 ); - wire GNDI, M0_NOTIN, VCCI, M0_dly, CLK_dly, LSR_dly; - - lut40116 IS_0_sqmuxa_0_o2_0_RNIS63D( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40072 RCKEEN_8_u_0_a2_1_s( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0066 RA10( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40116 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0033) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RD_0_ ( output PADDI, input PADDT, PADDO, inout RD0 ); @@ -2945,7 +3166,7 @@ endmodule module Dout_0_ ( input PADDO, output Dout0 ); - mjiobuf0117 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0)); + mjiobuf0132 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0)); specify (PADDO => Dout0) = (0:0:0,0:0:0); @@ -2953,14 +3174,14 @@ module Dout_0_ ( input PADDO, output Dout0 ); endmodule -module mjiobuf0117 ( input I, output PAD ); +module mjiobuf0132 ( input I, output PAD ); OB INST5( .I(I), .O(PAD)); endmodule module PHI2 ( output PADDI, input PHI2 ); - mjiobuf0118 PHI2_pad( .Z(PADDI), .PAD(PHI2)); + mjiobuf0133 PHI2_pad( .Z(PADDI), .PAD(PHI2)); specify (PHI2 => PADDI) = (0:0:0,0:0:0); @@ -2970,14 +3191,14 @@ module PHI2 ( output PADDI, input PHI2 ); endmodule -module mjiobuf0118 ( output Z, input PAD ); +module mjiobuf0133 ( output Z, input PAD ); IB INST1( .I(PAD), .O(Z)); endmodule module UFMSDO ( output PADDI, input UFMSDO ); - mjiobuf0118 UFMSDO_pad( .Z(PADDI), .PAD(UFMSDO)); + mjiobuf0133 UFMSDO_pad( .Z(PADDI), .PAD(UFMSDO)); specify (UFMSDO => PADDI) = (0:0:0,0:0:0); @@ -2989,7 +3210,7 @@ endmodule module UFMSDI ( input PADDO, output UFMSDI ); - mjiobuf0119 UFMSDI_pad( .I(PADDO), .PAD(UFMSDI)); + mjiobuf0134 UFMSDI_pad( .I(PADDO), .PAD(UFMSDI)); specify (PADDO => UFMSDI) = (0:0:0,0:0:0); @@ -2997,14 +3218,14 @@ module UFMSDI ( input PADDO, output UFMSDI ); endmodule -module mjiobuf0119 ( input I, output PAD ); +module mjiobuf0134 ( input I, output PAD ); OB INST5( .I(I), .O(PAD)); endmodule module UFMCLK ( input PADDO, output UFMCLK ); - mjiobuf0119 UFMCLK_pad( .I(PADDO), .PAD(UFMCLK)); + mjiobuf0134 UFMCLK_pad( .I(PADDO), .PAD(UFMCLK)); specify (PADDO => UFMCLK) = (0:0:0,0:0:0); @@ -3014,7 +3235,7 @@ endmodule module nUFMCS ( input PADDO, output nUFMCS ); - mjiobuf0119 nUFMCS_pad( .I(PADDO), .PAD(nUFMCS)); + mjiobuf0134 nUFMCS_pad( .I(PADDO), .PAD(nUFMCS)); specify (PADDO => nUFMCS) = (0:0:0,0:0:0); @@ -3024,7 +3245,7 @@ endmodule module RDQML ( input PADDO, output RDQML ); - mjiobuf0119 RDQML_pad( .I(PADDO), .PAD(RDQML)); + mjiobuf0134 RDQML_pad( .I(PADDO), .PAD(RDQML)); specify (PADDO => RDQML) = (0:0:0,0:0:0); @@ -3034,7 +3255,7 @@ endmodule module RDQMH ( input PADDO, output RDQMH ); - mjiobuf0119 RDQMH_pad( .I(PADDO), .PAD(RDQMH)); + mjiobuf0134 RDQMH_pad( .I(PADDO), .PAD(RDQMH)); specify (PADDO => RDQMH) = (0:0:0,0:0:0); @@ -3044,7 +3265,7 @@ endmodule module nRCAS ( input PADDO, output nRCAS ); - mjiobuf0119 nRCAS_pad( .I(PADDO), .PAD(nRCAS)); + mjiobuf0134 nRCAS_pad( .I(PADDO), .PAD(nRCAS)); specify (PADDO => nRCAS) = (0:0:0,0:0:0); @@ -3054,7 +3275,7 @@ endmodule module nRRAS ( input PADDO, output nRRAS ); - mjiobuf0119 nRRAS_pad( .I(PADDO), .PAD(nRRAS)); + mjiobuf0134 nRRAS_pad( .I(PADDO), .PAD(nRRAS)); specify (PADDO => nRRAS) = (0:0:0,0:0:0); @@ -3064,7 +3285,7 @@ endmodule module nRWE ( input PADDO, output nRWE ); - mjiobuf0119 nRWE_pad( .I(PADDO), .PAD(nRWE)); + mjiobuf0134 nRWE_pad( .I(PADDO), .PAD(nRWE)); specify (PADDO => nRWE) = (0:0:0,0:0:0); @@ -3074,7 +3295,7 @@ endmodule module RCKE ( input PADDO, output RCKE ); - mjiobuf0119 RCKE_pad( .I(PADDO), .PAD(RCKE)); + mjiobuf0134 RCKE_pad( .I(PADDO), .PAD(RCKE)); specify (PADDO => RCKE) = (0:0:0,0:0:0); @@ -3084,7 +3305,7 @@ endmodule module RCLK ( output PADDI, input RCLK ); - mjiobuf0118 RCLK_pad( .Z(PADDI), .PAD(RCLK)); + mjiobuf0133 RCLK_pad( .Z(PADDI), .PAD(RCLK)); specify (RCLK => PADDI) = (0:0:0,0:0:0); @@ -3096,7 +3317,7 @@ endmodule module nRCS ( input PADDO, output nRCS ); - mjiobuf0119 nRCS_pad( .I(PADDO), .PAD(nRCS)); + mjiobuf0134 nRCS_pad( .I(PADDO), .PAD(nRCS)); specify (PADDO => nRCS) = (0:0:0,0:0:0); @@ -3204,7 +3425,7 @@ endmodule module RA_11_ ( input PADDO, output RA11 ); - mjiobuf0119 \RA_pad[11] ( .I(PADDO), .PAD(RA11)); + mjiobuf0134 \RA_pad[11] ( .I(PADDO), .PAD(RA11)); specify (PADDO => RA11) = (0:0:0,0:0:0); @@ -3214,7 +3435,7 @@ endmodule module RA_10_ ( input PADDO, output RA10 ); - mjiobuf0119 \RA_pad[10] ( .I(PADDO), .PAD(RA10)); + mjiobuf0134 \RA_pad[10] ( .I(PADDO), .PAD(RA10)); specify (PADDO => RA10) = (0:0:0,0:0:0); @@ -3224,7 +3445,7 @@ endmodule module RA_9_ ( input PADDO, output RA9 ); - mjiobuf0119 \RA_pad[9] ( .I(PADDO), .PAD(RA9)); + mjiobuf0134 \RA_pad[9] ( .I(PADDO), .PAD(RA9)); specify (PADDO => RA9) = (0:0:0,0:0:0); @@ -3234,7 +3455,7 @@ endmodule module RA_8_ ( input PADDO, output RA8 ); - mjiobuf0119 \RA_pad[8] ( .I(PADDO), .PAD(RA8)); + mjiobuf0134 \RA_pad[8] ( .I(PADDO), .PAD(RA8)); specify (PADDO => RA8) = (0:0:0,0:0:0); @@ -3244,7 +3465,7 @@ endmodule module RA_7_ ( input PADDO, output RA7 ); - mjiobuf0119 \RA_pad[7] ( .I(PADDO), .PAD(RA7)); + mjiobuf0134 \RA_pad[7] ( .I(PADDO), .PAD(RA7)); specify (PADDO => RA7) = (0:0:0,0:0:0); @@ -3254,7 +3475,7 @@ endmodule module RA_6_ ( input PADDO, output RA6 ); - mjiobuf0119 \RA_pad[6] ( .I(PADDO), .PAD(RA6)); + mjiobuf0134 \RA_pad[6] ( .I(PADDO), .PAD(RA6)); specify (PADDO => RA6) = (0:0:0,0:0:0); @@ -3264,7 +3485,7 @@ endmodule module RA_5_ ( input PADDO, output RA5 ); - mjiobuf0119 \RA_pad[5] ( .I(PADDO), .PAD(RA5)); + mjiobuf0134 \RA_pad[5] ( .I(PADDO), .PAD(RA5)); specify (PADDO => RA5) = (0:0:0,0:0:0); @@ -3274,7 +3495,7 @@ endmodule module RA_4_ ( input PADDO, output RA4 ); - mjiobuf0119 \RA_pad[4] ( .I(PADDO), .PAD(RA4)); + mjiobuf0134 \RA_pad[4] ( .I(PADDO), .PAD(RA4)); specify (PADDO => RA4) = (0:0:0,0:0:0); @@ -3284,7 +3505,7 @@ endmodule module RA_3_ ( input PADDO, output RA3 ); - mjiobuf0119 \RA_pad[3] ( .I(PADDO), .PAD(RA3)); + mjiobuf0134 \RA_pad[3] ( .I(PADDO), .PAD(RA3)); specify (PADDO => RA3) = (0:0:0,0:0:0); @@ -3294,7 +3515,7 @@ endmodule module RA_2_ ( input PADDO, output RA2 ); - mjiobuf0119 \RA_pad[2] ( .I(PADDO), .PAD(RA2)); + mjiobuf0134 \RA_pad[2] ( .I(PADDO), .PAD(RA2)); specify (PADDO => RA2) = (0:0:0,0:0:0); @@ -3304,7 +3525,7 @@ endmodule module RA_1_ ( input PADDO, output RA1 ); - mjiobuf0119 \RA_pad[1] ( .I(PADDO), .PAD(RA1)); + mjiobuf0134 \RA_pad[1] ( .I(PADDO), .PAD(RA1)); specify (PADDO => RA1) = (0:0:0,0:0:0); @@ -3314,7 +3535,7 @@ endmodule module RA_0_ ( input PADDO, output RA0 ); - mjiobuf0119 \RA_pad[0] ( .I(PADDO), .PAD(RA0)); + mjiobuf0134 \RA_pad[0] ( .I(PADDO), .PAD(RA0)); specify (PADDO => RA0) = (0:0:0,0:0:0); @@ -3324,7 +3545,7 @@ endmodule module RBA_1_ ( input PADDO, output RBA1 ); - mjiobuf0119 \RBA_pad[1] ( .I(PADDO), .PAD(RBA1)); + mjiobuf0134 \RBA_pad[1] ( .I(PADDO), .PAD(RBA1)); specify (PADDO => RBA1) = (0:0:0,0:0:0); @@ -3334,7 +3555,7 @@ endmodule module RBA_0_ ( input PADDO, output RBA0 ); - mjiobuf0119 \RBA_pad[0] ( .I(PADDO), .PAD(RBA0)); + mjiobuf0134 \RBA_pad[0] ( .I(PADDO), .PAD(RBA0)); specify (PADDO => RBA0) = (0:0:0,0:0:0); @@ -3344,7 +3565,7 @@ endmodule module LED ( input PADDO, output LED ); - mjiobuf0120 LED_pad( .I(PADDO), .PAD(LED)); + mjiobuf0135 LED_pad( .I(PADDO), .PAD(LED)); specify (PADDO => LED) = (0:0:0,0:0:0); @@ -3352,14 +3573,14 @@ module LED ( input PADDO, output LED ); endmodule -module mjiobuf0120 ( input I, output PAD ); +module mjiobuf0135 ( input I, output PAD ); OB INST5( .I(I), .O(PAD)); endmodule module nFWE ( output PADDI, input nFWE ); - mjiobuf0118 nFWE_pad( .Z(PADDI), .PAD(nFWE)); + mjiobuf0133 nFWE_pad( .Z(PADDI), .PAD(nFWE)); specify (nFWE => PADDI) = (0:0:0,0:0:0); @@ -3371,7 +3592,7 @@ endmodule module nCRAS ( output PADDI, input nCRAS ); - mjiobuf0118 nCRAS_pad( .Z(PADDI), .PAD(nCRAS)); + mjiobuf0133 nCRAS_pad( .Z(PADDI), .PAD(nCRAS)); specify (nCRAS => PADDI) = (0:0:0,0:0:0); @@ -3383,7 +3604,7 @@ endmodule module nCCAS ( output PADDI, input nCCAS ); - mjiobuf0118 nCCAS_pad( .Z(PADDI), .PAD(nCCAS)); + mjiobuf0133 nCCAS_pad( .Z(PADDI), .PAD(nCCAS)); specify (nCCAS => PADDI) = (0:0:0,0:0:0); @@ -3395,7 +3616,7 @@ endmodule module Dout_7_ ( input PADDO, output Dout7 ); - mjiobuf0117 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7)); + mjiobuf0132 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7)); specify (PADDO => Dout7) = (0:0:0,0:0:0); @@ -3405,7 +3626,7 @@ endmodule module Dout_6_ ( input PADDO, output Dout6 ); - mjiobuf0117 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6)); + mjiobuf0132 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6)); specify (PADDO => Dout6) = (0:0:0,0:0:0); @@ -3415,7 +3636,7 @@ endmodule module Dout_5_ ( input PADDO, output Dout5 ); - mjiobuf0117 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5)); + mjiobuf0132 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5)); specify (PADDO => Dout5) = (0:0:0,0:0:0); @@ -3425,7 +3646,7 @@ endmodule module Dout_4_ ( input PADDO, output Dout4 ); - mjiobuf0117 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4)); + mjiobuf0132 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4)); specify (PADDO => Dout4) = (0:0:0,0:0:0); @@ -3435,7 +3656,7 @@ endmodule module Dout_3_ ( input PADDO, output Dout3 ); - mjiobuf0117 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3)); + mjiobuf0132 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3)); specify (PADDO => Dout3) = (0:0:0,0:0:0); @@ -3445,7 +3666,7 @@ endmodule module Dout_2_ ( input PADDO, output Dout2 ); - mjiobuf0117 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2)); + mjiobuf0132 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2)); specify (PADDO => Dout2) = (0:0:0,0:0:0); @@ -3455,7 +3676,7 @@ endmodule module Dout_1_ ( input PADDO, output Dout1 ); - mjiobuf0117 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1)); + mjiobuf0132 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1)); specify (PADDO => Dout1) = (0:0:0,0:0:0); @@ -3465,7 +3686,7 @@ endmodule module Din_7_ ( output PADDI, input Din7 ); - mjiobuf0118 \Din_pad[7] ( .Z(PADDI), .PAD(Din7)); + mjiobuf0133 \Din_pad[7] ( .Z(PADDI), .PAD(Din7)); specify (Din7 => PADDI) = (0:0:0,0:0:0); @@ -3477,7 +3698,7 @@ endmodule module Din_6_ ( output PADDI, input Din6 ); - mjiobuf0118 \Din_pad[6] ( .Z(PADDI), .PAD(Din6)); + mjiobuf0133 \Din_pad[6] ( .Z(PADDI), .PAD(Din6)); specify (Din6 => PADDI) = (0:0:0,0:0:0); @@ -3489,7 +3710,7 @@ endmodule module Din_5_ ( output PADDI, input Din5 ); - mjiobuf0118 \Din_pad[5] ( .Z(PADDI), .PAD(Din5)); + mjiobuf0133 \Din_pad[5] ( .Z(PADDI), .PAD(Din5)); specify (Din5 => PADDI) = (0:0:0,0:0:0); @@ -3501,7 +3722,7 @@ endmodule module Din_4_ ( output PADDI, input Din4 ); - mjiobuf0118 \Din_pad[4] ( .Z(PADDI), .PAD(Din4)); + mjiobuf0133 \Din_pad[4] ( .Z(PADDI), .PAD(Din4)); specify (Din4 => PADDI) = (0:0:0,0:0:0); @@ -3513,7 +3734,7 @@ endmodule module Din_3_ ( output PADDI, input Din3 ); - mjiobuf0118 \Din_pad[3] ( .Z(PADDI), .PAD(Din3)); + mjiobuf0133 \Din_pad[3] ( .Z(PADDI), .PAD(Din3)); specify (Din3 => PADDI) = (0:0:0,0:0:0); @@ -3525,7 +3746,7 @@ endmodule module Din_2_ ( output PADDI, input Din2 ); - mjiobuf0118 \Din_pad[2] ( .Z(PADDI), .PAD(Din2)); + mjiobuf0133 \Din_pad[2] ( .Z(PADDI), .PAD(Din2)); specify (Din2 => PADDI) = (0:0:0,0:0:0); @@ -3537,7 +3758,7 @@ endmodule module Din_1_ ( output PADDI, input Din1 ); - mjiobuf0118 \Din_pad[1] ( .Z(PADDI), .PAD(Din1)); + mjiobuf0133 \Din_pad[1] ( .Z(PADDI), .PAD(Din1)); specify (Din1 => PADDI) = (0:0:0,0:0:0); @@ -3549,7 +3770,7 @@ endmodule module Din_0_ ( output PADDI, input Din0 ); - mjiobuf0118 \Din_pad[0] ( .Z(PADDI), .PAD(Din0)); + mjiobuf0133 \Din_pad[0] ( .Z(PADDI), .PAD(Din0)); specify (Din0 => PADDI) = (0:0:0,0:0:0); @@ -3561,7 +3782,7 @@ endmodule module CROW_1_ ( output PADDI, input CROW1 ); - mjiobuf0118 \CROW_pad[1] ( .Z(PADDI), .PAD(CROW1)); + mjiobuf0133 \CROW_pad[1] ( .Z(PADDI), .PAD(CROW1)); specify (CROW1 => PADDI) = (0:0:0,0:0:0); @@ -3573,7 +3794,7 @@ endmodule module CROW_0_ ( output PADDI, input CROW0 ); - mjiobuf0118 \CROW_pad[0] ( .Z(PADDI), .PAD(CROW0)); + mjiobuf0133 \CROW_pad[0] ( .Z(PADDI), .PAD(CROW0)); specify (CROW0 => PADDI) = (0:0:0,0:0:0); @@ -3585,7 +3806,7 @@ endmodule module MAin_9_ ( output PADDI, input MAin9 ); - mjiobuf0118 \MAin_pad[9] ( .Z(PADDI), .PAD(MAin9)); + mjiobuf0133 \MAin_pad[9] ( .Z(PADDI), .PAD(MAin9)); specify (MAin9 => PADDI) = (0:0:0,0:0:0); @@ -3597,7 +3818,7 @@ endmodule module MAin_8_ ( output PADDI, input MAin8 ); - mjiobuf0118 \MAin_pad[8] ( .Z(PADDI), .PAD(MAin8)); + mjiobuf0133 \MAin_pad[8] ( .Z(PADDI), .PAD(MAin8)); specify (MAin8 => PADDI) = (0:0:0,0:0:0); @@ -3609,7 +3830,7 @@ endmodule module MAin_7_ ( output PADDI, input MAin7 ); - mjiobuf0118 \MAin_pad[7] ( .Z(PADDI), .PAD(MAin7)); + mjiobuf0133 \MAin_pad[7] ( .Z(PADDI), .PAD(MAin7)); specify (MAin7 => PADDI) = (0:0:0,0:0:0); @@ -3621,7 +3842,7 @@ endmodule module MAin_6_ ( output PADDI, input MAin6 ); - mjiobuf0118 \MAin_pad[6] ( .Z(PADDI), .PAD(MAin6)); + mjiobuf0133 \MAin_pad[6] ( .Z(PADDI), .PAD(MAin6)); specify (MAin6 => PADDI) = (0:0:0,0:0:0); @@ -3633,7 +3854,7 @@ endmodule module MAin_5_ ( output PADDI, input MAin5 ); - mjiobuf0118 \MAin_pad[5] ( .Z(PADDI), .PAD(MAin5)); + mjiobuf0133 \MAin_pad[5] ( .Z(PADDI), .PAD(MAin5)); specify (MAin5 => PADDI) = (0:0:0,0:0:0); @@ -3645,7 +3866,7 @@ endmodule module MAin_4_ ( output PADDI, input MAin4 ); - mjiobuf0118 \MAin_pad[4] ( .Z(PADDI), .PAD(MAin4)); + mjiobuf0133 \MAin_pad[4] ( .Z(PADDI), .PAD(MAin4)); specify (MAin4 => PADDI) = (0:0:0,0:0:0); @@ -3657,7 +3878,7 @@ endmodule module MAin_3_ ( output PADDI, input MAin3 ); - mjiobuf0118 \MAin_pad[3] ( .Z(PADDI), .PAD(MAin3)); + mjiobuf0133 \MAin_pad[3] ( .Z(PADDI), .PAD(MAin3)); specify (MAin3 => PADDI) = (0:0:0,0:0:0); @@ -3669,7 +3890,7 @@ endmodule module MAin_2_ ( output PADDI, input MAin2 ); - mjiobuf0118 \MAin_pad[2] ( .Z(PADDI), .PAD(MAin2)); + mjiobuf0133 \MAin_pad[2] ( .Z(PADDI), .PAD(MAin2)); specify (MAin2 => PADDI) = (0:0:0,0:0:0); @@ -3681,7 +3902,7 @@ endmodule module MAin_1_ ( output PADDI, input MAin1 ); - mjiobuf0118 \MAin_pad[1] ( .Z(PADDI), .PAD(MAin1)); + mjiobuf0133 \MAin_pad[1] ( .Z(PADDI), .PAD(MAin1)); specify (MAin1 => PADDI) = (0:0:0,0:0:0); @@ -3693,7 +3914,7 @@ endmodule module MAin_0_ ( output PADDI, input MAin0 ); - mjiobuf0118 \MAin_pad[0] ( .Z(PADDI), .PAD(MAin0)); + mjiobuf0133 \MAin_pad[0] ( .Z(PADDI), .PAD(MAin0)); specify (MAin0 => PADDI) = (0:0:0,0:0:0); diff --git a/CPLD/LCMXO256C/impl1/hdla_gen_hierarchy.html b/CPLD/LCMXO256C/impl1/hdla_gen_hierarchy.html index e8b523c..169abaa 100644 --- a/CPLD/LCMXO256C/impl1/hdla_gen_hierarchy.html +++ b/CPLD/LCMXO256C/impl1/hdla_gen_hierarchy.html @@ -2,8 +2,9 @@ Starting: parse design source files (VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v' (VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-SPI.v' +WARNING - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-SPI.v(23,47-23,52) (VERI-1875) identifier 'Ready' is used before its declaration INFO - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-SPI.v(1,8-1,14) (VERI-1018) compiling module 'RAM2GS' INFO - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-SPI.v(1,1-410,10) (VERI-9000) elaborating module 'RAM2GS' -Done: design load finished with (0) errors, and (0) warnings +Done: design load finished with (0) errors, and (1) warnings \ No newline at end of file diff --git a/CPLD/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1.ior b/CPLD/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1.ior index 5ba7069..8211cda 100644 --- a/CPLD/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1.ior +++ b/CPLD/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1.ior @@ -29,7 +29,7 @@ Performance Hardware Data Status: Version 1.124. // Package: TQFP100 // ncd File: ram2gs_lcmxo256c_impl1.ncd // Version: Diamond (64-bit) 3.12.1.454 -// Written on Thu Sep 21 05:38:44 2023 +// Written on Sat Jan 06 06:25:13 2024 // M: Minimum Performance Grade // iotiming RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO256C/promote.xml @@ -41,98 +41,98 @@ Worst Case Results across Performance Grades (M, 5, 4, 3): Port Clock Edge Setup Performance_Grade Hold Performance_Grade ---------------------------------------------------------------------- -CROW[0] nCRAS F -0.006 M 1.904 3 -CROW[1] nCRAS F -0.006 M 1.904 3 -Din[0] PHI2 F 4.101 3 2.207 3 -Din[0] nCCAS F 1.552 3 -0.018 M -Din[1] PHI2 F 2.668 3 3.026 3 -Din[1] nCCAS F 0.606 3 0.745 3 -Din[2] PHI2 F 2.073 3 2.917 3 -Din[2] nCCAS F 0.500 3 0.619 3 -Din[3] PHI2 F 2.620 3 3.334 3 -Din[3] nCCAS F -0.089 M 1.336 3 -Din[4] PHI2 F 5.116 3 2.411 3 -Din[4] nCCAS F 0.293 3 1.125 3 -Din[5] PHI2 F 5.590 3 2.084 3 -Din[5] nCCAS F 0.435 3 0.979 3 -Din[6] PHI2 F 5.951 3 1.726 3 -Din[6] nCCAS F 1.305 3 0.253 3 -Din[7] PHI2 F 4.412 3 1.404 3 -Din[7] nCCAS F 0.195 3 1.215 3 -MAin[0] PHI2 F 3.306 3 1.176 3 -MAin[0] nCRAS F -0.132 M 2.336 3 -MAin[1] PHI2 F 2.656 3 2.511 3 -MAin[1] nCRAS F -0.034 M 2.014 3 -MAin[2] PHI2 F 6.839 3 -0.310 M -MAin[2] nCRAS F -0.154 M 2.424 3 -MAin[3] PHI2 F 6.871 3 -0.311 M -MAin[3] nCRAS F -0.015 M 1.928 3 -MAin[4] PHI2 F 7.111 3 -0.361 M -MAin[4] nCRAS F 0.370 3 1.590 3 -MAin[5] PHI2 F 7.075 3 -0.353 M -MAin[5] nCRAS F -0.126 M 2.320 3 -MAin[6] PHI2 F 6.794 3 -0.295 M -MAin[6] nCRAS F 0.010 3 1.885 3 -MAin[7] PHI2 F 6.926 3 -0.324 M -MAin[7] nCRAS F 0.319 3 1.622 3 -MAin[8] nCRAS F -0.038 M 2.031 3 -MAin[9] nCRAS F 0.366 3 1.596 3 -PHI2 RCLK R 2.295 3 -0.174 M -UFMSDO RCLK R 1.364 3 0.511 3 -nCCAS RCLK R 2.300 3 -0.185 M -nCCAS nCRAS F 0.216 3 1.721 3 -nCRAS RCLK R 4.548 3 -0.507 M -nFWE PHI2 F 6.729 3 -0.281 M -nFWE nCRAS F -0.037 M 2.025 3 +CROW[0] nCRAS F -0.006 M 1.907 3 +CROW[1] nCRAS F -0.006 M 1.907 3 +Din[0] PHI2 F 4.304 3 2.935 3 +Din[0] nCCAS F 0.567 3 0.723 3 +Din[1] PHI2 F 4.920 3 3.034 3 +Din[1] nCCAS F 0.414 3 0.851 3 +Din[2] PHI2 F 3.171 3 3.327 3 +Din[2] nCCAS F 0.909 3 0.432 3 +Din[3] PHI2 F 4.332 3 2.525 3 +Din[3] nCCAS F 0.038 3 1.155 3 +Din[4] PHI2 F 5.624 3 2.635 3 +Din[4] nCCAS F 1.448 3 -0.041 M +Din[5] PHI2 F 4.126 3 2.124 3 +Din[5] nCCAS F 1.046 3 0.159 3 +Din[6] PHI2 F 5.565 3 2.394 3 +Din[6] nCCAS F 0.563 3 0.729 3 +Din[7] PHI2 F 5.293 3 1.654 3 +Din[7] nCCAS F 0.719 3 0.583 3 +MAin[0] PHI2 F 8.072 3 -0.164 M +MAin[0] nCRAS F -0.128 M 2.331 3 +MAin[1] PHI2 F 7.487 3 -0.178 M +MAin[1] nCRAS F -0.129 M 2.331 3 +MAin[2] PHI2 F 6.793 3 -0.034 M +MAin[2] nCRAS F -0.129 M 2.331 3 +MAin[3] PHI2 F 7.235 3 -0.226 M +MAin[3] nCRAS F -0.035 M 2.023 3 +MAin[4] PHI2 F 7.305 3 -0.207 M +MAin[4] nCRAS F 0.428 3 1.517 3 +MAin[5] PHI2 F 7.672 3 -0.236 M +MAin[5] nCRAS F -0.037 M 2.028 3 +MAin[6] PHI2 F 9.015 3 -0.710 M +MAin[6] nCRAS F -0.003 M 1.896 3 +MAin[7] PHI2 F 7.764 3 -0.441 M +MAin[7] nCRAS F -0.126 M 2.324 3 +MAin[8] nCRAS F -0.038 M 2.034 3 +MAin[9] nCRAS F 0.206 3 1.728 3 +PHI2 RCLK R 2.769 3 -0.274 M +UFMSDO RCLK R 1.753 3 -0.052 M +nCCAS RCLK R 1.935 3 -0.108 M +nCCAS nCRAS F 0.843 3 1.179 3 +nCRAS RCLK R 1.093 3 0.277 3 +nFWE PHI2 F 4.435 3 0.640 3 +nFWE nCRAS F 1.163 3 0.894 3 // Clock to Output Delay Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade ------------------------------------------------------------------------ -LED RCLK R 13.764 3 4.455 M -LED nCRAS F 16.500 3 4.993 M -RA[0] RCLK R 10.114 3 2.098 M -RA[0] nCRAS F 11.793 3 2.420 M -RA[10] RCLK R 8.581 3 1.780 M +LED RCLK R 15.407 3 4.713 M +LED nCRAS F 17.685 3 5.215 M +RA[0] RCLK R 10.436 3 2.152 M +RA[0] nCRAS F 11.488 3 2.330 M +RA[10] RCLK R 8.093 3 1.668 M RA[11] PHI2 R 9.420 3 1.925 M -RA[1] RCLK R 11.717 3 2.429 M -RA[1] nCRAS F 12.171 3 2.492 M -RA[2] RCLK R 9.514 3 1.971 M -RA[2] nCRAS F 11.301 3 2.319 M -RA[3] RCLK R 10.525 3 2.169 M -RA[3] nCRAS F 12.042 3 2.459 M -RA[4] RCLK R 11.387 3 2.343 M -RA[4] nCRAS F 12.532 3 2.543 M -RA[5] RCLK R 10.114 3 2.098 M -RA[5] nCRAS F 10.936 3 2.242 M -RA[6] RCLK R 9.514 3 1.971 M -RA[6] nCRAS F 10.544 3 2.165 M -RA[7] RCLK R 10.933 3 2.261 M -RA[7] nCRAS F 11.162 3 2.268 M -RA[8] RCLK R 10.591 3 2.178 M -RA[8] nCRAS F 11.951 3 2.426 M -RA[9] RCLK R 9.668 3 1.989 M -RA[9] nCRAS F 10.889 3 2.209 M -RBA[0] nCRAS F 8.922 3 1.828 M -RBA[1] nCRAS F 10.649 3 2.177 M -RCKE RCLK R 8.493 3 1.760 M -RDQMH RCLK R 10.817 3 2.273 M -RDQML RCLK R 11.739 3 2.471 M -RD[0] nCCAS F 9.545 3 2.093 M -RD[1] nCCAS F 8.834 3 1.965 M -RD[2] nCCAS F 9.535 3 2.092 M -RD[3] nCCAS F 9.531 3 2.092 M -RD[4] nCCAS F 9.303 3 2.066 M -RD[5] nCCAS F 11.766 3 2.555 M -RD[6] nCCAS F 9.303 3 2.066 M -RD[7] nCCAS F 10.470 3 2.285 M -UFMCLK RCLK R 9.190 3 1.937 M +RA[1] RCLK R 10.958 3 2.270 M +RA[1] nCRAS F 12.371 3 2.529 M +RA[2] RCLK R 10.892 3 2.242 M +RA[2] nCRAS F 11.786 3 2.402 M +RA[3] RCLK R 10.561 3 2.184 M +RA[3] nCRAS F 12.541 3 2.560 M +RA[4] RCLK R 10.909 3 2.257 M +RA[4] nCRAS F 12.060 3 2.456 M +RA[5] RCLK R 9.970 3 2.057 M +RA[5] nCRAS F 12.271 3 2.508 M +RA[6] RCLK R 9.222 3 1.920 M +RA[6] nCRAS F 10.844 3 2.210 M +RA[7] RCLK R 9.613 3 1.981 M +RA[7] nCRAS F 11.686 3 2.379 M +RA[8] RCLK R 9.617 3 1.982 M +RA[8] nCRAS F 11.487 3 2.339 M +RA[9] RCLK R 9.762 3 2.016 M +RA[9] nCRAS F 11.488 3 2.337 M +RBA[0] nCRAS F 8.925 3 1.828 M +RBA[1] nCRAS F 10.608 3 2.153 M +RCKE RCLK R 7.609 3 1.570 M +RDQMH RCLK R 10.915 3 2.299 M +RDQML RCLK R 11.554 3 2.433 M +RD[0] nCCAS F 8.539 3 1.899 M +RD[1] nCCAS F 9.248 3 2.027 M +RD[2] nCCAS F 9.706 3 2.118 M +RD[3] nCCAS F 8.539 3 1.899 M +RD[4] nCCAS F 9.228 3 2.015 M +RD[5] nCCAS F 8.772 3 1.924 M +RD[6] nCCAS F 8.539 3 1.899 M +RD[7] nCCAS F 9.706 3 2.118 M +UFMCLK RCLK R 8.007 3 1.714 M UFMSDI RCLK R 8.007 3 1.714 M -nRCAS RCLK R 8.209 3 1.697 M +nRCAS RCLK R 8.120 3 1.681 M nRCS RCLK R 6.854 3 1.431 M -nRRAS RCLK R 8.021 3 1.650 M +nRRAS RCLK R 8.089 3 1.669 M nRWE RCLK R 6.854 3 1.431 M -nUFMCS RCLK R 9.650 3 2.046 M +nUFMCS RCLK R 8.732 3 1.846 M WARNING: you must also run trce with hold speed: 3 WARNING: you must also run trce with setup speed: M diff --git a/CPLD/LCMXO256C/promote.xml b/CPLD/LCMXO256C/promote.xml index 893846a..2ff32e4 100644 --- a/CPLD/LCMXO256C/promote.xml +++ b/CPLD/LCMXO256C/promote.xml @@ -1,3 +1,3 @@ - + diff --git a/CPLD/LCMXO256C/reportview.xml b/CPLD/LCMXO256C/reportview.xml index 04684bf..ae43cff 100644 --- a/CPLD/LCMXO256C/reportview.xml +++ b/CPLD/LCMXO256C/reportview.xml @@ -3,7 +3,7 @@ - + diff --git a/CPLD/LCMXO640C/RAM2GS_LCMXO640C_tcl.html b/CPLD/LCMXO640C/RAM2GS_LCMXO640C_tcl.html new file mode 100644 index 0000000..a0e657a --- /dev/null +++ b/CPLD/LCMXO640C/RAM2GS_LCMXO640C_tcl.html @@ -0,0 +1,70 @@ + +Lattice TCL Log + + +
    pn231119195557
+#Start recording tcl command: 11/18/2023 02:19:15
+#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO640C; Project name: RAM2GS_LCMXO640C
+prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO640C/RAM2GS_LCMXO640C.ldf"
+prj_run Export -impl impl1
+#Stop recording: 11/19/2023 19:55:57
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    + + diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.alt b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.alt index 4affcc7..9b87289 100644 --- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.alt +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.alt @@ -1,6 +1,6 @@ NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation * NOTE All Rights Reserved * -NOTE DATE CREATED: Thu Sep 21 05:38:46 2023 * +NOTE DATE CREATED: Sat Jan 06 06:25:24 2024 * NOTE DESIGN NAME: RAM2GS * NOTE DEVICE NAME: LCMXO640C-3TQFP100 * NOTE PIN ASSIGNMENTS * diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.areasrr b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.areasrr index 0c38afe..289931b 100644 --- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.areasrr +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.areasrr @@ -15,12 +15,12 @@ I/O cells: 67 FD1S3JX 3 100.0 GSR 1 100.0 IB 26 100.0 - INV 8 100.0 + INV 7 100.0 OB 33 100.0 - ORCALUT4 119 100.0 - PFUMX 2 100.0 + ORCALUT4 133 100.0 + PFUMX 1 100.0 PUR 1 100.0 VHI 1 100.0 VLO 1 100.0 - TOTAL 301 + TOTAL 313 diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.bgn b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.bgn index c5d555f..3068c8a 100644 --- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.bgn +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.bgn @@ -4,7 +4,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Thu Sep 21 05:38:46 2023 +Sat Jan 06 06:25:23 2024 Command: bitgen -w -g ES:No -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.bit b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.bit index 38de2c2..aeeecee 100644 Binary files a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.bit and b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.bit differ diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.edi b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.edi index 70645df..68705ec 100644 --- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.edi +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.edi @@ -4,7 +4,7 @@ (keywordMap (keywordLevel 0)) (status (written - (timeStamp 2023 9 21 5 38 28) + (timeStamp 2024 1 6 6 25 7) (author "Synopsys, Inc.") (program "Synplify Pro" (version "R-2021.03L-SP1, mapper map202103lat, Build 070R")) ) @@ -196,37 +196,29 @@ (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT))) ) (instance GSR_INST (viewRef PRIM (cellRef GSR (libraryRef LUCENT))) ) - (instance RASr2_RNIAFR1 (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) - (instance (rename IS_i_0 "IS_i[0]") (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) + (instance (rename S_RNO_1 "S_RNO[1]") (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) (instance Ready_fast_RNI29NA (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) (instance nCCAS_pad_RNISUR8 (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) (instance RASr_RNO (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) (instance nFWE_pad_RNI420B (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) - (instance nRCS_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (B+A)+D (!C (!B A+B !A)+C (B+A)))")) - ) - (instance C1Submitted_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (B+A)+D (!C (B+A)+C A))")) - ) (instance nRowColSel_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C (!B A))")) ) - (instance RCKEEN_8_u_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance C1Submitted_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B+A)+C A)+D A)")) + ) + (instance RCKEEN_8_u_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (!C (!B A)+C (!B+!A))+D (C !A))")) ) (instance (rename IS_RNO_3 "IS_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D A+D (!C A+C (!B A+B !A)))")) ) + (instance UFMCLK_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (B A)+D (!C (B A)+C (B+!A)))")) + ) (instance Ready_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D A+D (!C (B+A)+C A))")) ) - (instance CmdEnable_s (viewRef PRIM (cellRef PFUMX (libraryRef LUCENT))) ) - (instance CmdEnable_s_bm (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B+A)")) - ) - (instance CmdEnable_s_am (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C B+C (B A))+D (!C B+C A))")) - ) (instance nRWE_RNO_1 (viewRef PRIM (cellRef PFUMX (libraryRef LUCENT))) ) (instance nRWE_RNO_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (C (!B !A)))")) @@ -496,173 +488,194 @@ (instance (rename MAin_pad_1 "MAin_pad[1]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) (instance (rename MAin_pad_0 "MAin_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) (instance PHI2_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance CmdEnable17_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (B A)))")) + (instance CmdEnable_s_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C !B)+D (!C (!B A)))")) ) - (instance XOR8MEG18_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (!C (B A)))")) + (instance CmdEnable_s (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(!C A+C B))")) ) - (instance un1_FS_14_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D A+D (!C A+C (B+A)))")) + (instance XOR8MEG_3_u_0_a3_0_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D C+D (C+(!B+!A)))")) ) - (instance un1_FS_13_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D A+D (!C A+C (B+A)))")) - ) - (instance C1WR_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B A)")) - ) - (instance CmdEnable16_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C (B A))")) + (instance ADSubmitted_r_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) ) (instance Cmdn8MEGEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C (!B !A)+C !A)")) ) (instance CmdLEDEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C !B)+D (!C (!B A)))")) + (property lut_function (string "(!C !A+C (B !A))")) ) - (instance RA10_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(!C+(B+A)))")) + (instance un1_CmdEnable20_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B !A))")) ) - (instance C1WR_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (B A)))")) + (instance un1_FS_14_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C (B+A))")) ) - (instance XOR8MEG_3_u_0_a3_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D C+D (C+(!B+!A)))")) + (instance un1_FS_13_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C (B+A))")) + ) + (instance (rename IS_RNO_0 "IS_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B !A+B A)+C A)")) + ) + (instance XOR8MEG18 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) ) (instance UFMSDI_ens2_i_a0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D !A+D (!C !A+C (B !A)))")) + (property lut_function (string "(!D !A+D (!C (!B !A)+C !A))")) ) - (instance un1_FS_13_i_a2_8 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (!B A)))")) + (instance RA10_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(!B+!A)))")) ) - (instance nRRAS_5_u_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(!C (!B A)+C !B))")) + (instance CmdEnable17_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B A)))")) + ) + (instance CmdEnable16_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B A))")) ) (instance un1_nRCAS_6_sqmuxa_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (C+(!B+A))+D (!C (!B+A)))")) ) + (instance IS_0_sqmuxa_0_o2_0_RNIS63D (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B !A)")) + ) (instance UFMSDI_en_ss0_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C (!B !A))")) ) (instance nUFMCS15_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (!C (!B !A)))")) ) + (instance C1WR (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (B A)))")) + ) + (instance ADWR (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B A)))")) + ) + (instance CMDWR (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (B A)))")) + ) (instance Cmdn8MEGEN_4_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B+A)+C A)+D !B)")) + (property lut_function (string "(!D (C A)+D (!C !B+C (!B+A)))")) ) - (instance C1WR_0_a2_0_10 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (B A)))")) + (instance CmdLEDEN_4_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C B)+D (!C (B+!A)+C !A))")) ) - (instance UFMCLK_r_i_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C B)+D A)")) + (instance un1_CmdEnable20_0_a3_0_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B A)))")) ) (instance PHI2r3_RNITCN41 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D !B+D (!C (!B+A)+C !B))")) ) - (instance IS_0_sqmuxa_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B+A)")) + (instance XOR8MEG_3_u_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) ) (instance nRCAS_0_sqmuxa_1_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D (C (!B A)))")) ) - (instance nRowColSel_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C B+C (B+A))+D (!C B+C (B+!A)))")) + (instance LED_pad_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(!C+(!B+A)))")) ) (instance Ready_0_sqmuxa_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D (!C (!B A)))")) ) - (instance XOR8MEG_3_u_0_a3_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (!C (B A)))")) - ) - (instance nRRAS_5_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (!C (B !A)+C !A))")) - ) - (instance (rename IS_RNO_2 "IS_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B A)+C (!B+!A))")) - ) - (instance un1_FS_14_i_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (!C (B A)))")) - ) - (instance UFMSDI_ens2_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C B+C (!B A))")) - ) - (instance XOR8MEG_3_u_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B A)")) - ) - (instance ADSubmitted_r (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C+(!B A)))")) - ) - (instance LED_pad_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C+(!B+A))")) - ) - (instance InitReady3_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance C1WR_7 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D (C (B A)))")) ) - (instance UFMSDI_ens2_i_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C+(B+A))")) - ) (instance Cmdn8MEGEN_4_u_i_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C (B !A))")) ) - (instance CmdLEDEN_4_u_i_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B !A))")) + (instance nRRAS_5_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B !A)+C !A))")) + ) + (instance un1_FS_14_i_a2_0_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B !A)))")) + ) + (instance un1_FS_13_i_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B A)))")) + ) + (instance (rename IS_RNO_2 "IS_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B A)+C (!B+!A))")) + ) + (instance ADSubmitted_r (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+(!B A)))")) + ) + (instance Cmdn8MEGEN_4_u_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(B A))")) + ) + (instance nRowColSel_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C B+C (B+A))+D (!C B+C (B+!A)))")) + ) + (instance UFMSDI_ens2_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C (!B A))")) + ) + (instance un1_FS_14_i_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B A)))")) ) (instance UFMCLK_r_i_a2_2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D (C (!B A)))")) ) - (instance nRowColSel_0_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (!B !A)))")) + (instance UFMSDI_ens2_i_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(B+A))")) ) - (instance CmdEnable16_0_a2_4_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B A)))")) + (instance InitReady3_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) ) - (instance CmdEnable16_0_a2_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (!B A)))")) + (instance ADWR_8 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) ) - (instance CmdEnable17_0_a2_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C (!B A)))")) + (instance C1WR_2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B !A)))")) + ) + (instance CMDWR_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B !A)))")) ) (instance RCKE_2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (C !B)+D (C+(B+A)))")) ) - (instance (rename S_RNO_0 "S_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B+!A)")) - ) (instance Ready_0_sqmuxa_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C+(!B+!A))")) ) - (instance un1_nRCAS_6_sqmuxa_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C+(B+A))")) - ) - (instance Cmdn8MEGEN_4_u_i_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C+(B+!A))")) - ) (instance RA11_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C (!B A+B !A)+C B)")) ) (instance nCCAS_pad_RNI01SJ (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(B+A)")) ) + (instance RCKEEN_8_u_0_a2_0_m1_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B !A))")) + ) (instance InitReady3_0_a2_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D (C (B A)))")) ) - (instance un1_FS_13_i_a2_6 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (!C (!B !A)))")) + (instance CmdEnable17_0_a3_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B !A)))")) ) - (instance un1_Din_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B !A)))")) + (instance Cmdn8MEGEN_4_u_i_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(B+!A))")) + ) + (instance nRowColSel_0_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B !A)))")) + ) + (instance ADWR_8_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance RCKEEN_8_u_0_a3_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (!B+!A))")) + ) + (instance un1_Bank_1_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance un1_Bank_1_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B !A)))")) ) (instance UFMSDI_ens2_i_o2_0_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D+(C+(B+A)))")) ) - (instance C1WR_0_a2_0_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B A))")) + (instance un1_FS_13_i_a2_9_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B !A)))")) ) - (instance C1WR_0_a2_0_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (B A)))")) - ) - (instance C1WR_0_a2_0_11 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (B !A)))")) + (instance un1_FS_13_i_a2_9_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B !A)))")) ) (instance Ready_0_sqmuxa_0_a3_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D (!C (B A)))")) @@ -670,30 +683,15 @@ (instance UFMSDI_ens2_i_a2_4_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D (!C (!B A)))")) ) - (instance un1_FS_13_i_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (!C (!B !A)))")) + (instance CmdEnable16_0_a3_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B A)))")) ) - (instance un1_FS_14_i_a2_0_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance CmdEnable16_0_a3_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (!C (!B !A)))")) ) - (instance n8MEGEN_5_i_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B+A)+C (B A))")) - ) - (instance LEDEN_5_i_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B+A)+C (B A))")) - ) (instance (rename un9_RA_8 "un9_RA[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C B+C A)")) ) - (instance (rename un9_RA_0 "un9_RA[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C B+C A)")) - ) - (instance (rename un9_RA_1 "un9_RA[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C B+C A)")) - ) - (instance (rename un9_RA_2 "un9_RA[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C B+C A)")) - ) (instance (rename un9_RA_3 "un9_RA[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C B+C A)")) ) @@ -706,14 +704,32 @@ (instance (rename un9_RA_6 "un9_RA[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C B+C A)")) ) - (instance (rename un9_RA_7 "un9_RA[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C B+C A)")) - ) (instance (rename un9_RA_9 "un9_RA[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C B+C A)")) ) - (instance InitReady3_0_a2_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B A)")) + (instance (rename un9_RA_7 "un9_RA[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_2 "un9_RA[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_1 "un9_RA[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_0 "un9_RA[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance n8MEGEN_5_i_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B+A)+C (B A))")) + ) + (instance LEDEN_5_i_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B+A)+C (B A))")) + ) + (instance RA10_2_sqmuxa_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance nRCS_9_u_i_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B !A)")) ) (instance (rename S_0_i_o2_1 "S_0_i_o2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(B+A)")) @@ -721,32 +737,56 @@ (instance IS_n1_0_x2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!B A+B !A)")) ) - (instance CmdEnable16_0_a2_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B A)")) - ) - (instance CmdEnable16_0_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B !A)")) + (instance CmdEnable17_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) ) (instance CmdEnable17_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance RDQML (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!B+!A)")) ) (instance RDQMH (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!B+A)")) ) - (instance RDQML (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B+!A)")) - ) - (instance RCKEEN_8_u_0_a2_1_s (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (instance InitReady3_0_a2_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(B A)")) ) - (instance RCKEEN_8_u_1_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C+B)+D (C (!B+!A)))")) + (instance un1_FS_14_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B+!A)")) ) - (instance RCKEEN_8_u (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D B+D (!C B+C (B+!A)))")) + (instance ADWR_8_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance RCKEEN_8_u_0_1_a1_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B A)")) + ) + (instance RCKEEN_8_u_0_1_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B A))+D (!C !B+C (!B !A)))")) + ) + (instance RCKEEN_8_u_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D B+D (!C (B+!A)+C B))")) ) (instance nRCS_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D !B+D (!C (!B A)+C !B))")) + (property lut_function (string "(!D (!C (!B+!A))+D (!C !B))")) + ) + (instance nRCS_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D B+D (!C (B+!A)+C B))")) + ) + (instance nRCS_RNO_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B !A)))")) + ) + (instance nRCS_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B A)))")) + ) + (instance nRCS_RNO_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(B+A)))")) + ) + (instance nRCS_RNO_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B+A))")) + ) + (instance nRCS_RNO_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B A)")) ) (instance nRWE_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (C+(!B+!A))+D (C+(B !A)))")) @@ -761,13 +801,13 @@ (property lut_function (string "(C (!B A))")) ) (instance nRCAS_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B A)+C !B)+D (!B A))")) - ) - (instance nRCAS_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B !A))+D (!C (!B !A)+C (B !A)))")) + (property lut_function (string "(!D (!C !B)+D (!C (!B+!A)))")) ) (instance nRCAS_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B A)")) + (property lut_function (string "(!C !B+C (!B !A))")) + ) + (instance nRCAS_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D !C+D (C (!B A)))")) ) (instance UFMSDI_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C (!B A)+C !B)")) @@ -784,36 +824,36 @@ (instance nUFMCS_s_0_N_5_i_N_2L1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!C (!B+A))")) ) + (instance nRRAS_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B+!A)+C B))")) + ) + (instance CmdLEDEN_4_u_i_a2_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B !A)))")) + ) + (instance un1_nRCAS_6_sqmuxa_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(B+A))")) + ) (instance IS_0_sqmuxa_0_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(D+(C+(!B+!A)))")) ) - (instance CmdEnable17_0_a2_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C (B !A)))")) + (instance XOR8MEG_3_u_0_a3_0_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B !A)))")) ) - (instance CmdSubmitted_1_sqmuxa_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!B A)+D (!C (!B A)))")) - ) - (instance CmdLEDEN_4_u_i_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!B A)+D (!C (!B A)+C !B))")) + (instance XOR8MEG_3_u_0_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(B+A)))")) ) (instance CmdUFMCLK_1_sqmuxa_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (C (!B A)))")) ) - (instance nRRAS_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B !A)+C !A)+D (C !A))")) - ) - (instance IS_0_sqmuxa_0_o2_0_RNIS63D (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B !A)")) - ) - (instance (rename IS_RNO_0 "IS_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B !A+B A)+C A)")) - ) - (instance un1_CMDWR (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B A)+C A)")) + (instance CmdSubmitted_1_sqmuxa_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!B A)+D (!C (!B A)))")) ) (instance UFMCLK_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) (property lut_function (string "(!D (C+(!B+!A))+D (C+(!B A)))")) ) + (instance CmdEnable_0_sqmuxa (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) (instance (rename FS_cry_0_16 "FS_cry_0[16]") (viewRef PRIM (cellRef CCU2 (libraryRef LUCENT))) (property INIT0 (string "0x300a")) (property INJECT1_1 (string "NO")) @@ -868,44 +908,41 @@ (property INJECT1_0 (string "NO")) (property INIT1 (string "0x300a")) ) - (net C1WR_0_a2 (joined - (portRef Z (instanceRef C1WR_0_a2)) - (portRef B (instanceRef ADSubmitted_r)) - )) (net CBR (joined (portRef Q (instanceRef CBR)) - (portRef A (instanceRef nRWE_RNO_0)) - (portRef A (instanceRef nRCS_RNO)) - (portRef A (instanceRef RCKEEN_8_u)) + (portRef A (instanceRef nRCAS_RNO_1)) + (portRef A (instanceRef RCKEEN_8_u_0)) (portRef B (instanceRef nRowColSel_0_0_a3_0)) (portRef A (instanceRef LED_pad_RNO)) )) (net C1Submitted (joined (portRef Q (instanceRef C1Submitted)) - (portRef D (instanceRef CmdEnable_s_am)) + (portRef A (instanceRef CmdEnable_s_RNO)) (portRef B (instanceRef C1Submitted_RNO)) )) (net (rename Bank_2 "Bank[2]") (joined (portRef Q (instanceRef Bank_2)) - (portRef A (instanceRef C1WR_0_a2_0_11)) + (portRef A (instanceRef un1_Bank_1_5)) )) (net Ready (joined (portRef Q (instanceRef Ready)) - (portRef B (instanceRef IS_RNO_0)) - (portRef A (instanceRef IS_0_sqmuxa_0_o2_0_RNIS63D)) (portRef C (instanceRef nRWE_RNO_2)) - (portRef D (instanceRef RCKEEN_8_u)) - (portRef A (instanceRef RCKEEN_8_u_0_a2_1_s)) + (portRef C (instanceRef nRCS_RNO_3)) + (portRef D (instanceRef RCKEEN_8_u_0)) (portRef D (instanceRef nRowColSel_0_0_a3_0)) + (portRef B (instanceRef RCKEEN_8_u_0_a2_0_m1_0_a2)) + (portRef C (instanceRef nRowColSel_0_0)) (portRef D (instanceRef nRRAS_5_u_i_0)) (portRef C (instanceRef Ready_0_sqmuxa_0_a3)) - (portRef C (instanceRef nRowColSel_0_0)) + (portRef C (instanceRef LED_pad_RNO)) (portRef D (instanceRef nRCAS_0_sqmuxa_1_0_a3)) - (portRef B (instanceRef IS_0_sqmuxa_0_o2)) + (portRef B (instanceRef IS_0_sqmuxa_0_o2_0_RNIS63D)) (portRef C (instanceRef un1_nRCAS_6_sqmuxa_i_0)) + (portRef D (instanceRef RA10_RNO)) + (portRef C (instanceRef IS_RNO_0)) (portRef C0 (instanceRef nRWE_RNO_1)) (portRef A (instanceRef Ready_RNO)) - (portRef A (instanceRef RCKEEN_8_u_RNO)) + (portRef A (instanceRef RCKEEN_8_u_0_0)) (portRef A (instanceRef nRowColSel_RNO)) )) (net n8MEGEN (joined @@ -916,28 +953,35 @@ (net CO0 (joined (portRef Q (instanceRef S_0)) (portRef D (instanceRef IS_0_sqmuxa_0_o2_0)) - (portRef B (instanceRef nRCAS_RNO_0)) + (portRef C (instanceRef nRCAS_RNO_0)) (portRef B (instanceRef nRWE_RNO_0)) - (portRef B (instanceRef RCKEEN_8_u_1_0)) + (portRef C (instanceRef nRCS_RNO_1)) + (portRef A (instanceRef nRCS_RNO_2)) + (portRef A (instanceRef nRCS_RNO_0)) + (portRef A (instanceRef RCKEEN_8_u_0_1_a1_0)) (portRef A (instanceRef S_0_i_o2_1)) + (portRef A (instanceRef nRCS_9_u_i_a2)) (portRef A (instanceRef Ready_0_sqmuxa_0_a3_2)) - (portRef A (instanceRef S_RNO_0)) + (portRef B (instanceRef RCKEEN_8_u_0_a3_0_0)) (portRef A (instanceRef nRowColSel_0_0)) (portRef B (instanceRef nRWE_RNO_4)) (portRef B (instanceRef nRWE_RNO_3)) (portRef C (instanceRef nRowColSel_RNO)) - (portRef B (instanceRef nRCS_RNO_0)) )) (net (rename S_1 "S[1]") (joined (portRef Q (instanceRef S_1)) (portRef C (instanceRef IS_0_sqmuxa_0_o2_0)) - (portRef C (instanceRef nRCAS_RNO)) + (portRef C (instanceRef nRCAS_RNO_1)) + (portRef D (instanceRef nRCAS_RNO)) (portRef C (instanceRef nRWE_RNO_0)) - (portRef D (instanceRef RCKEEN_8_u_1_0)) - (portRef B (instanceRef RCKEEN_8_u_0_a2_1_s)) + (portRef B (instanceRef nRCS_RNO_4)) + (portRef C (instanceRef nRCS_RNO_0)) + (portRef D (instanceRef RCKEEN_8_u_0_1_1)) + (portRef B (instanceRef RCKEEN_8_u_0_1_a1_0)) (portRef B (instanceRef S_0_i_o2_1)) (portRef D (instanceRef Ready_0_sqmuxa_0_a3_2)) - (portRef B (instanceRef S_RNO_0)) + (portRef C (instanceRef RCKEEN_8_u_0_a3_0_0)) + (portRef C (instanceRef RCKEEN_8_u_0_a2_0_m1_0_a2)) (portRef D (instanceRef nRowColSel_0_0)) (portRef D (instanceRef un1_nRCAS_6_sqmuxa_i_0)) (portRef A (instanceRef nRWE_RNO_4)) @@ -948,20 +992,24 @@ (portRef Q (instanceRef RASr2)) (portRef A (instanceRef IS_0_sqmuxa_0_o2_0)) (portRef D (instanceRef nRWE_RNO_5)) + (portRef A (instanceRef nRCS_RNO_3)) + (portRef B (instanceRef nRCS_RNO_2)) (portRef C (instanceRef Ready_0_sqmuxa_0_a3_2)) (portRef B (instanceRef RCKE_2_0)) (portRef B (instanceRef nRRAS_5_u_i_0)) (portRef C (instanceRef nRCAS_0_sqmuxa_1_0_a3)) (portRef D (instanceRef RASr3)) + (portRef D (instanceRef S_0)) (portRef D (instanceRef nRWE_RNO_3)) - (portRef B (instanceRef RCKEEN_8_u_RNO)) - (portRef A (instanceRef RASr2_RNIAFR1)) + (portRef B (instanceRef RCKEEN_8_u_0_0)) + (portRef A (instanceRef S_RNO_1)) )) (net InitReady (joined (portRef Q (instanceRef InitReady)) (portRef A (instanceRef UFMCLK_RNO_0)) (portRef B (instanceRef IS_0_sqmuxa_0_o2_0)) (portRef B (instanceRef nUFMCS_s_0_N_5_i_N_2L1)) + (portRef A (instanceRef nRCS_RNO_4)) (portRef B (instanceRef LEDEN_5_i_m2)) (portRef B (instanceRef n8MEGEN_5_i_m2)) (portRef B (instanceRef UFMCLK_r_i_a2_2_2)) @@ -974,76 +1022,79 @@ (portRef B (instanceRef InitReady_RNO)) (portRef D (instanceRef nRWE_RNO_4)) (portRef D (instanceRef Ready_RNO)) - (portRef C (instanceRef RCKEEN_8_u_RNO)) + (portRef C (instanceRef RCKEEN_8_u_0_0)) )) (net FWEr (joined (portRef Q (instanceRef FWEr)) - (portRef C (instanceRef nRCAS_RNO_0)) (portRef A (instanceRef nRWE_RNO)) + (portRef B (instanceRef nRCS_9_u_i_a2)) (portRef C (instanceRef nRowColSel_0_0_a3_0)) )) (net CASr3 (joined (portRef Q (instanceRef CASr3)) - (portRef B (instanceRef nRCAS_RNO_1)) + (portRef B (instanceRef nRCAS_RNO_0)) (portRef B (instanceRef nRWE_RNO_2)) + (portRef B (instanceRef nRCS_RNO_1)) (portRef A (instanceRef nRowColSel_0_0_a3_0)) - (portRef C (instanceRef nRCS_RNO_0)) )) (net (rename IS_0 "IS[0]") (joined (portRef Q (instanceRef IS_0)) - (portRef A (instanceRef IS_RNO_0)) - (portRef D (instanceRef nRRAS_RNO)) + (portRef A (instanceRef nRRAS_RNO)) (portRef A (instanceRef nRWE_RNO_5)) + (portRef A (instanceRef nRCS_RNO_5)) (portRef A (instanceRef IS_n1_0_x2)) (portRef A (instanceRef Ready_0_sqmuxa_0_o2)) (portRef A (instanceRef IS_RNO_2)) - (portRef A (instanceRef nRRAS_5_u_i)) + (portRef A (instanceRef RA10_RNO)) + (portRef A (instanceRef IS_RNO_0)) (portRef D (instanceRef IS_RNO_3)) - (portRef A (instanceRef IS_i_0)) )) (net (rename IS_3 "IS[3]") (joined (portRef Q (instanceRef IS_3)) + (portRef A (instanceRef un1_nRCAS_6_sqmuxa_i_o2)) + (portRef D (instanceRef nRCS_RNO_5)) (portRef B (instanceRef Ready_0_sqmuxa_0_a3_2)) - (portRef C (instanceRef un1_nRCAS_6_sqmuxa_i_o2)) - (portRef C (instanceRef RA10_RNO)) + (portRef B (instanceRef RA10_RNO)) (portRef A (instanceRef IS_RNO_3)) )) (net (rename IS_1 "IS[1]") (joined (portRef Q (instanceRef IS_1)) + (portRef C (instanceRef un1_nRCAS_6_sqmuxa_i_o2)) (portRef B (instanceRef nRWE_RNO_5)) + (portRef B (instanceRef nRCS_RNO_5)) (portRef B (instanceRef IS_n1_0_x2)) - (portRef A (instanceRef un1_nRCAS_6_sqmuxa_i_o2)) + (portRef A (instanceRef RA10_2_sqmuxa_0_o2)) (portRef B (instanceRef Ready_0_sqmuxa_0_o2)) (portRef B (instanceRef IS_RNO_2)) - (portRef A (instanceRef RA10_RNO)) (portRef C (instanceRef IS_RNO_3)) )) (net (rename IS_2 "IS[2]") (joined (portRef Q (instanceRef IS_2)) - (portRef C (instanceRef nRWE_RNO_5)) (portRef B (instanceRef un1_nRCAS_6_sqmuxa_i_o2)) + (portRef C (instanceRef nRWE_RNO_5)) + (portRef C (instanceRef nRCS_RNO_5)) + (portRef B (instanceRef RA10_2_sqmuxa_0_o2)) (portRef C (instanceRef Ready_0_sqmuxa_0_o2)) (portRef C (instanceRef IS_RNO_2)) - (portRef B (instanceRef RA10_RNO)) (portRef B (instanceRef IS_RNO_3)) )) (net (rename FS_5 "FS[5]") (joined (portRef Q (instanceRef FS_5)) (portRef A1 (instanceRef FS_cry_0_4)) - (portRef D (instanceRef un1_FS_14_i_a2_0_1)) - (portRef D (instanceRef un1_FS_13_i_a2_1)) (portRef A (instanceRef UFMSDI_ens2_i_o2)) + (portRef A (instanceRef un1_FS_13_i_a2_1)) + (portRef A (instanceRef un1_FS_14_i_a2_0_1)) )) (net (rename FS_6 "FS[6]") (joined (portRef Q (instanceRef FS_6)) (portRef A0 (instanceRef FS_cry_0_6)) (portRef A (instanceRef UFMSDI_ens2_i_a2_4_2)) - (portRef B (instanceRef un1_FS_13_i_a2_6)) + (portRef D (instanceRef un1_FS_13_i_a2_9_4)) )) (net (rename FS_7 "FS[7]") (joined (portRef Q (instanceRef FS_7)) (portRef A1 (instanceRef FS_cry_0_6)) - (portRef C (instanceRef un1_FS_13_i_a2_6)) + (portRef B (instanceRef un1_FS_13_i_a2_9_5)) (portRef B (instanceRef UFMSDI_ens2_i_o2)) )) (net (rename FS_8 "FS[8]") (joined @@ -1055,67 +1106,65 @@ (net (rename FS_9 "FS[9]") (joined (portRef Q (instanceRef FS_9)) (portRef A1 (instanceRef FS_cry_0_8)) + (portRef C (instanceRef un1_FS_13_i_a2_9_5)) (portRef C (instanceRef UFMSDI_ens2_i_o2)) - (portRef B (instanceRef un1_FS_13_i_a2_8)) )) (net (rename FS_0 "FS[0]") (joined (portRef Q (instanceRef FS_0)) (portRef A0 (instanceRef FS_cry_0_0)) - (portRef A (instanceRef un1_FS_14_i_a2_0_1)) - (portRef A (instanceRef un1_FS_13_i_a2_1)) + (portRef A (instanceRef un1_FS_13_i_a2_9_4)) )) (net (rename FS_1 "FS[1]") (joined (portRef Q (instanceRef FS_1)) (portRef A1 (instanceRef FS_cry_0_0)) - (portRef A (instanceRef un1_FS_13_i_a2_6)) - (portRef A (instanceRef UFMCLK_r_i_m2)) + (portRef A (instanceRef un1_FS_13_i_a2_9_5)) + (portRef B (instanceRef UFMCLK_RNO_1)) )) (net (rename FS_2 "FS[2]") (joined (portRef Q (instanceRef FS_2)) (portRef A0 (instanceRef FS_cry_0_2)) - (portRef B (instanceRef un1_FS_14_i_a2_0_1)) - (portRef B (instanceRef un1_FS_13_i_a2_1)) + (portRef B (instanceRef un1_FS_13_i_a2_9_4)) )) (net (rename FS_3 "FS[3]") (joined (portRef Q (instanceRef FS_3)) (portRef A1 (instanceRef FS_cry_0_2)) - (portRef C (instanceRef un1_FS_14_i_a2_0_1)) - (portRef C (instanceRef un1_FS_13_i_a2_1)) + (portRef C (instanceRef un1_FS_13_i_a2_9_4)) )) (net (rename FS_10 "FS[10]") (joined (portRef Q (instanceRef FS_10)) (portRef A0 (instanceRef FS_cry_0_10)) (portRef C (instanceRef UFMSDI_ens2_i_a2_4_2)) - (portRef D (instanceRef un1_FS_13_i_a2_6)) + (portRef D (instanceRef un1_FS_13_i_a2_9_5)) (portRef A (instanceRef InitReady3_0_a2)) (portRef A (instanceRef nUFMCS15_0_a2)) )) (net (rename FS_11 "FS[11]") (joined (portRef Q (instanceRef FS_11)) (portRef A1 (instanceRef FS_cry_0_10)) + (portRef B (instanceRef un1_FS_14_i_o2)) (portRef A (instanceRef InitReady3_0_a2_3)) (portRef D (instanceRef UFMSDI_ens2_i_a2_4_2)) - (portRef C (instanceRef UFMCLK_r_i_m2)) (portRef B (instanceRef nUFMCS15_0_a2)) - (portRef C (instanceRef un1_FS_13_i_a2_8)) + (portRef C (instanceRef UFMCLK_RNO_1)) )) (net (rename FS_12 "FS[12]") (joined (portRef Q (instanceRef FS_12)) (portRef A0 (instanceRef FS_cry_0_12)) + (portRef A (instanceRef UFMSDI_ens2_i_o2_0_3)) (portRef A (instanceRef InitReady3_0_a2_5)) - (portRef A (instanceRef UFMSDI_ens2_i_o2_0)) )) (net (rename FS_13 "FS[13]") (joined (portRef Q (instanceRef FS_13)) (portRef A1 (instanceRef FS_cry_0_12)) - (portRef A (instanceRef UFMSDI_ens2_i_o2_0_3)) - (portRef B (instanceRef InitReady3_0_a2_5)) + (portRef B (instanceRef InitReady3_0_a2)) + (portRef A (instanceRef UFMSDI_ens2_i_o2_0)) + (portRef A (instanceRef UFMCLK_r_i_a2_2_2)) )) (net (rename FS_14 "FS[14]") (joined (portRef Q (instanceRef FS_14)) (portRef A0 (instanceRef FS_cry_0_14)) - (portRef B (instanceRef InitReady3_0_a2_3)) (portRef B (instanceRef UFMSDI_ens2_i_o2_0_3)) + (portRef B (instanceRef InitReady3_0_a2_5)) )) (net (rename FS_15 "FS[15]") (joined (portRef Q (instanceRef FS_15)) @@ -1126,15 +1175,14 @@ (net (rename FS_16 "FS[16]") (joined (portRef Q (instanceRef FS_16)) (portRef A0 (instanceRef FS_cry_0_16)) - (portRef A (instanceRef UFMCLK_r_i_a2_2_2)) + (portRef D (instanceRef InitReady3_0_a2_5)) (portRef B (instanceRef UFMSDI_ens2_i_o2_0)) - (portRef B (instanceRef InitReady3_0_a2)) )) (net (rename FS_17 "FS[17]") (joined (portRef Q (instanceRef FS_17)) (portRef A1 (instanceRef FS_cry_0_16)) + (portRef B (instanceRef InitReady3_0_a2_3)) (portRef D (instanceRef UFMSDI_ens2_i_o2_0_3)) - (portRef D (instanceRef InitReady3_0_a2_5)) )) (net PHI2r2 (joined (portRef Q (instanceRef PHI2r2)) @@ -1148,11 +1196,11 @@ )) (net CASr2 (joined (portRef Q (instanceRef CASr2)) - (portRef A (instanceRef nRCAS_RNO_1)) + (portRef A (instanceRef nRCAS_RNO_0)) (portRef A (instanceRef nRWE_RNO_2)) - (portRef A (instanceRef RCKEEN_8_u_1_0)) + (portRef A (instanceRef nRCS_RNO_1)) + (portRef A (instanceRef RCKEEN_8_u_0_a3_0_0)) (portRef D (instanceRef CASr3)) - (portRef D (instanceRef nRCS_RNO_0)) )) (net CASr (joined (portRef Q (instanceRef CASr)) @@ -1169,31 +1217,31 @@ )) (net (rename Bank_0 "Bank[0]") (joined (portRef Q (instanceRef Bank_0)) - (portRef A (instanceRef C1WR_0_a2_0)) + (portRef A (instanceRef un1_Bank_1_4)) )) (net (rename Bank_1 "Bank[1]") (joined (portRef Q (instanceRef Bank_1)) - (portRef B (instanceRef C1WR_0_a2_0)) + (portRef B (instanceRef un1_Bank_1_4)) )) (net (rename Bank_3 "Bank[3]") (joined (portRef Q (instanceRef Bank_3)) - (portRef A (instanceRef C1WR_0_a2_0_10)) + (portRef C (instanceRef un1_Bank_1_4)) )) (net (rename Bank_4 "Bank[4]") (joined (portRef Q (instanceRef Bank_4)) - (portRef B (instanceRef C1WR_0_a2_0_10)) + (portRef D (instanceRef un1_Bank_1_4)) )) (net (rename Bank_5 "Bank[5]") (joined (portRef Q (instanceRef Bank_5)) - (portRef B (instanceRef C1WR_0_a2_0_11)) + (portRef B (instanceRef un1_Bank_1_5)) )) (net (rename Bank_6 "Bank[6]") (joined (portRef Q (instanceRef Bank_6)) - (portRef C (instanceRef C1WR_0_a2_0_11)) + (portRef C (instanceRef un1_Bank_1_5)) )) (net (rename Bank_7 "Bank[7]") (joined (portRef Q (instanceRef Bank_7)) - (portRef D (instanceRef C1WR_0_a2_0_11)) + (portRef D (instanceRef un1_Bank_1_5)) )) (net (rename RowA_0 "RowA[0]") (joined (portRef Q (instanceRef RowA_0)) @@ -1269,17 +1317,17 @@ )) (net nRowColSel (joined (portRef Q (instanceRef nRowColSel)) - (portRef B (instanceRef RDQML)) (portRef B (instanceRef RDQMH)) - (portRef C (instanceRef un9_RA_9)) + (portRef B (instanceRef RDQML)) + (portRef C (instanceRef un9_RA_0)) + (portRef C (instanceRef un9_RA_1)) + (portRef C (instanceRef un9_RA_2)) (portRef C (instanceRef un9_RA_7)) + (portRef C (instanceRef un9_RA_9)) (portRef C (instanceRef un9_RA_6)) (portRef C (instanceRef un9_RA_5)) (portRef C (instanceRef un9_RA_4)) (portRef C (instanceRef un9_RA_3)) - (portRef C (instanceRef un9_RA_2)) - (portRef C (instanceRef un9_RA_1)) - (portRef C (instanceRef un9_RA_0)) (portRef C (instanceRef un9_RA_8)) )) (net RASr3 (joined @@ -1289,13 +1337,13 @@ (net LEDEN (joined (portRef Q (instanceRef LEDEN)) (portRef B (instanceRef LED_pad_RNO)) - (portRef B (instanceRef XOR8MEG_3_u_0_a3_3)) - (portRef A (instanceRef CmdLEDEN_RNO)) + (portRef B (instanceRef CmdLEDEN_RNO)) + (portRef B (instanceRef XOR8MEG_3_u_0_a3_0_2)) )) (net CmdLEDEN (joined (portRef Q (instanceRef CmdLEDEN)) - (portRef B (instanceRef CmdLEDEN_4_u_i_a2)) (portRef A (instanceRef LEDEN_5_i_m2)) + (portRef A (instanceRef CmdLEDEN_4_u_i_0)) )) (net Cmdn8MEGEN (joined (portRef Q (instanceRef Cmdn8MEGEN)) @@ -1316,8 +1364,8 @@ (net (rename FS_4 "FS[4]") (joined (portRef Q (instanceRef FS_4)) (portRef A0 (instanceRef FS_cry_0_4)) - (portRef B (instanceRef UFMCLK_r_i_m2)) - (portRef A (instanceRef un1_FS_13_i_a2_8)) + (portRef A (instanceRef un1_FS_14_i_o2)) + (portRef D (instanceRef UFMCLK_RNO_1)) )) (net InitReady3 (joined (portRef Z (instanceRef InitReady3_0_a2)) @@ -1334,7 +1382,7 @@ (net XOR8MEG (joined (portRef Q (instanceRef XOR8MEG)) (portRef B (instanceRef RA11_2)) - (portRef A (instanceRef XOR8MEG_3_u_0_a3_0)) + (portRef B (instanceRef XOR8MEG_3_u_0_a3)) )) (net nRRAS_0_sqmuxa (joined (portRef Z (instanceRef nRowColSel_RNO)) @@ -1356,33 +1404,32 @@ )) (net nRCAS_0_sqmuxa_1 (joined (portRef Z (instanceRef nRCAS_0_sqmuxa_1_0_a3)) - (portRef B (instanceRef nRCAS_RNO)) + (portRef C (instanceRef nRCAS_RNO)) (portRef C (instanceRef nRWE_RNO)) )) (net XOR8MEG18 (joined - (portRef Z (instanceRef XOR8MEG18_0_a2)) - (portRef A (instanceRef CmdUFMCLK_1_sqmuxa_0_a2)) + (portRef Z (instanceRef XOR8MEG18)) (portRef A (instanceRef CmdSubmitted_1_sqmuxa_0_a2)) + (portRef A (instanceRef CmdUFMCLK_1_sqmuxa_0_a2)) (portRef SP (instanceRef CmdLEDEN)) (portRef SP (instanceRef Cmdn8MEGEN)) (portRef SP (instanceRef XOR8MEG)) )) (net CmdEnable (joined (portRef Q (instanceRef CmdEnable)) - (portRef A (instanceRef XOR8MEG18_0_a2)) - (portRef B (instanceRef CmdEnable_s_am)) - (portRef A (instanceRef CmdEnable_s_bm)) + (portRef B (instanceRef XOR8MEG18)) + (portRef A (instanceRef CmdEnable_s)) )) (net CmdEnable16 (joined - (portRef Z (instanceRef CmdEnable16_0_a2)) + (portRef Z (instanceRef CmdEnable16_0_a3)) (portRef D (instanceRef ADSubmitted_r)) - (portRef C0 (instanceRef CmdEnable_s)) + (portRef B (instanceRef CmdEnable_s_RNO)) (portRef A (instanceRef C1Submitted_RNO)) )) (net CmdEnable17 (joined - (portRef Z (instanceRef CmdEnable17_0_a2)) + (portRef Z (instanceRef CmdEnable17_0_a3)) (portRef C (instanceRef ADSubmitted_r)) - (portRef A (instanceRef CmdEnable_s_am)) + (portRef B (instanceRef CmdEnable_s)) )) (net CmdSubmitted_1_sqmuxa (joined (portRef Z (instanceRef CmdSubmitted_1_sqmuxa_0_a2)) @@ -1404,8 +1451,12 @@ )) (net ADSubmitted (joined (portRef Q (instanceRef ADSubmitted)) + (portRef A (instanceRef CmdEnable_0_sqmuxa)) (portRef A (instanceRef ADSubmitted_r)) - (portRef B (instanceRef CmdEnable_s_bm)) + )) + (net CmdEnable_0_sqmuxa (joined + (portRef Z (instanceRef CmdEnable_0_sqmuxa)) + (portRef D (instanceRef CmdEnable_s)) )) (net C1Submitted_RNO (joined (portRef Z (instanceRef C1Submitted_RNO)) @@ -1428,182 +1479,197 @@ (portRef D (instanceRef nRowColSel)) )) (net RCKEEN_8 (joined - (portRef Z (instanceRef RCKEEN_8_u)) + (portRef Z (instanceRef RCKEEN_8_u_0)) (portRef D (instanceRef RCKEEN)) )) - (net N_31 (joined + (net N_24 (joined (portRef Z (instanceRef un1_FS_14_i_0)) (portRef SP (instanceRef n8MEGEN)) )) - (net N_33 (joined + (net N_26 (joined (portRef Z (instanceRef un1_FS_13_i_0)) (portRef SP (instanceRef LEDEN)) )) - (net N_24 (joined - (portRef Z (instanceRef nRRAS_5_u_i)) - (portRef B (instanceRef nRCS_RNO)) - )) - (net N_41 (joined + (net un1_nRCAS_6_sqmuxa_i_0 (joined (portRef Z (instanceRef un1_nRCAS_6_sqmuxa_i_0)) - (portRef A (instanceRef nRCAS_RNO)) + (portRef B (instanceRef nRCAS_RNO_1)) )) (net (rename S_0_i_o2_1 "S_0_i_o2[1]") (joined (portRef Z (instanceRef S_0_i_o2_1)) (portRef A (instanceRef nRRAS_5_u_i_0)) (portRef B (instanceRef nRCAS_0_sqmuxa_1_0_a3)) (portRef D (instanceRef S_1)) - (portRef D (instanceRef RCKEEN_8_u_RNO)) + (portRef D (instanceRef RCKEEN_8_u_0_0)) )) - (net N_159 (joined - (portRef Z (instanceRef IS_0_sqmuxa_0_o2)) - (portRef D (instanceRef RA10_RNO)) + (net N_45 (joined + (portRef Z (instanceRef Cmdn8MEGEN_4_u_i_o2)) + (portRef D (instanceRef CmdLEDEN_4_u_i_0)) + (portRef D (instanceRef Cmdn8MEGEN_4_u_i_0)) )) - (net N_165 (joined + (net N_36 (joined + (portRef Z (instanceRef Cmdn8MEGEN_4_u_i_o2_0)) + (portRef B (instanceRef CmdSubmitted_1_sqmuxa_0_a2)) + (portRef B (instanceRef CmdUFMCLK_1_sqmuxa_0_a2)) + (portRef C (instanceRef Cmdn8MEGEN_4_u_i_o2)) + (portRef C (instanceRef Cmdn8MEGEN_4_u_i_a2_2)) + )) + (net N_154 (joined + (portRef Z (instanceRef un1_nRCAS_6_sqmuxa_i_o2)) + (portRef C (instanceRef nRRAS_RNO)) + (portRef B (instanceRef un1_nRCAS_6_sqmuxa_i_0)) + )) + (net N_148 (joined + (portRef Z (instanceRef IS_0_sqmuxa_0_o2_0)) + (portRef B (instanceRef nRRAS_RNO)) + (portRef A (instanceRef IS_0_sqmuxa_0_o2_0_RNIS63D)) + (portRef A (instanceRef un1_nRCAS_6_sqmuxa_i_0)) + (portRef C (instanceRef RA10_RNO)) + (portRef B (instanceRef IS_RNO_0)) + )) + (net N_151 (joined + (portRef Z (instanceRef RA10_2_sqmuxa_0_o2)) + (portRef D (instanceRef RA10)) + )) + (net N_160 (joined (portRef Z (instanceRef Ready_0_sqmuxa_0_o2)) (portRef B (instanceRef Ready_0_sqmuxa_0_a3)) (portRef C (instanceRef Ready_RNO)) )) - (net N_95_5 (joined - (portRef Z (instanceRef InitReady3_0_a2_5)) - (portRef D (instanceRef UFMCLK_r_i_a2_2_2)) - (portRef D (instanceRef InitReady3_0_a2)) - )) - (net N_95_3 (joined - (portRef Z (instanceRef InitReady3_0_a2_3)) - (portRef C (instanceRef UFMCLK_r_i_a2_2_2)) - (portRef C (instanceRef InitReady3_0_a2)) - )) - (net N_51 (joined - (portRef Z (instanceRef UFMSDI_ens2_i_o2_0)) - (portRef D (instanceRef UFMCLK_r_i_m2)) - (portRef D (instanceRef nUFMCS15_0_a2)) - (portRef C (instanceRef UFMSDI_en_ss0_0_a2_0)) - (portRef B (instanceRef UFMSDI_ens2_i_a0)) - )) - (net N_126 (joined - (portRef Z (instanceRef UFMSDI_ens2_i_o2)) - (portRef C (instanceRef UFMSDI_ens2_i_a0)) - )) - (net N_151 (joined - (portRef Z (instanceRef UFMSDI_en_ss0_0_a2_0)) - (portRef C (instanceRef UFMSDI_RNO_0)) - (portRef D (instanceRef un1_FS_13_i_a2_8)) - )) - (net N_137_8 (joined - (portRef Z (instanceRef un1_FS_13_i_a2_8)) - (portRef C (instanceRef un1_FS_13_i_0)) - (portRef C (instanceRef un1_FS_14_i_0)) - )) - (net N_129 (joined - (portRef Z (instanceRef UFMCLK_r_i_m2)) - (portRef D (instanceRef UFMCLK_RNO_0)) - )) - (net N_155 (joined - (portRef Z (instanceRef IS_0_sqmuxa_0_o2_0)) - (portRef C (instanceRef IS_RNO_0)) - (portRef B (instanceRef IS_0_sqmuxa_0_o2_0_RNIS63D)) - (portRef C (instanceRef nRRAS_RNO)) - (portRef A (instanceRef IS_0_sqmuxa_0_o2)) - (portRef A (instanceRef un1_nRCAS_6_sqmuxa_i_0)) - (portRef B (instanceRef nRRAS_5_u_i)) - )) - (net N_56_i (joined - (portRef Z (instanceRef IS_n1_0_x2)) - (portRef D (instanceRef IS_1)) - )) - (net N_160 (joined - (portRef Z (instanceRef un1_nRCAS_6_sqmuxa_i_o2)) - (portRef B (instanceRef nRRAS_RNO)) - (portRef B (instanceRef un1_nRCAS_6_sqmuxa_i_0)) - (portRef C (instanceRef nRRAS_5_u_i)) - )) - (net N_136 (joined - (portRef Z (instanceRef un1_FS_14_i_a2)) - (portRef A (instanceRef un1_FS_13_i_0)) - (portRef A (instanceRef un1_FS_14_i_0)) - )) - (net N_69 (joined - (portRef Z (instanceRef n8MEGEN_5_i_m2)) - (portRef D (instanceRef n8MEGEN)) - )) - (net N_70 (joined - (portRef Z (instanceRef LEDEN_5_i_m2)) - (portRef D (instanceRef LEDEN)) - )) - (net N_137_6 (joined - (portRef Z (instanceRef un1_FS_13_i_a2_6)) - (portRef B (instanceRef un1_FS_13_i_0)) - (portRef B (instanceRef un1_FS_14_i_0)) - )) - (net XOR8MEG_3 (joined - (portRef Z (instanceRef XOR8MEG_3_u_0_a3_3)) - (portRef D (instanceRef XOR8MEG)) - )) - (net CmdEnable16_1 (joined - (portRef Z (instanceRef CmdEnable16_0_a2_1)) - (portRef A (instanceRef CmdEnable16_0_a2_5)) - )) - (net N_43 (joined - (portRef Z (instanceRef CmdEnable17_0_o2)) - (portRef D (instanceRef CmdEnable17_0_a2_4)) - (portRef C (instanceRef Cmdn8MEGEN_4_u_i_0)) - )) - (net N_147 (joined - (portRef Z (instanceRef C1WR_0_a2_0)) - (portRef A (instanceRef un1_CMDWR)) - (portRef C (instanceRef CmdEnable16_0_a2)) - (portRef B (instanceRef C1WR_0_a2)) - (portRef D (instanceRef XOR8MEG18_0_a2)) - (portRef D (instanceRef CmdEnable17_0_a2)) - (portRef C (instanceRef C1Submitted_RNO)) - )) - (net CmdEnable16_4 (joined - (portRef Z (instanceRef CmdEnable16_0_a2_4)) - (portRef A (instanceRef CmdEnable16_0_a2_4_0)) - (portRef A (instanceRef Cmdn8MEGEN_4_u_i_0)) - )) - (net un1_Din_4 (joined - (portRef Z (instanceRef un1_Din_4)) - (portRef B (instanceRef XOR8MEG_3_u_0_a3_0)) - (portRef D (instanceRef XOR8MEG_3_u_0_a3_2)) - )) - (net N_171 (joined - (portRef Z (instanceRef XOR8MEG_3_u_0_a3_0)) - (portRef C (instanceRef XOR8MEG_3_u_0_a3_3)) - )) - (net N_128 (joined - (portRef Z (instanceRef Cmdn8MEGEN_4_u_i_o2_0)) - (portRef B (instanceRef CmdUFMCLK_1_sqmuxa_0_a2)) - (portRef A (instanceRef CmdLEDEN_4_u_i_a2)) - (portRef B (instanceRef CmdSubmitted_1_sqmuxa_0_a2)) - (portRef C (instanceRef CmdLEDEN_4_u_i_a2_0)) - (portRef C (instanceRef Cmdn8MEGEN_4_u_i_a2_2)) - (portRef D (instanceRef Cmdn8MEGEN_4_u_i_0)) - )) - (net N_152 (joined + (net N_95 (joined (portRef Z (instanceRef Cmdn8MEGEN_4_u_i_a2_2)) - (portRef D (instanceRef CmdLEDEN_RNO)) + (portRef C (instanceRef CmdLEDEN_RNO)) (portRef B (instanceRef Cmdn8MEGEN_RNO)) )) - (net N_132 (joined - (portRef Z (instanceRef CmdLEDEN_4_u_i_a2)) - (portRef B (instanceRef CmdLEDEN_RNO)) + (net N_184 (joined + (portRef Z (instanceRef RCKEEN_8_u_0_a2_0_m1_0_a2)) + (portRef B (instanceRef nRCS_RNO)) )) - (net N_133 (joined - (portRef Z (instanceRef CmdLEDEN_4_u_i_a2_0)) - (portRef C (instanceRef CmdLEDEN_RNO)) - )) - (net un1_CMDWR (joined - (portRef Z (instanceRef un1_CMDWR)) - (portRef C (instanceRef CmdEnable_s_am)) - )) - (net N_179 (joined + (net N_112 (joined (portRef Z (instanceRef nRowColSel_0_0_a3_0)) (portRef B (instanceRef nRowColSel_0_0)) )) - (net XOR8MEG_3_u_0_a3_2 (joined - (portRef Z (instanceRef XOR8MEG_3_u_0_a3_2)) - (portRef D (instanceRef XOR8MEG_3_u_0_a3_3)) + (net N_125 (joined + (portRef Z (instanceRef nRCS_9_u_i_a2)) + (portRef A (instanceRef nRCS_RNO)) + )) + (net N_69_i (joined + (portRef Z (instanceRef IS_n1_0_x2)) + (portRef D (instanceRef IS_1)) + )) + (net N_121 (joined + (portRef Z (instanceRef un1_CmdEnable20_0_a3)) + (portRef C (instanceRef CmdEnable_s_RNO)) + )) + (net CMDWR (joined + (portRef Z (instanceRef CMDWR)) + (portRef A (instanceRef XOR8MEG18)) + (portRef C (instanceRef un1_CmdEnable20_0_a3)) + )) + (net C1WR_7 (joined + (portRef Z (instanceRef C1WR_7)) + (portRef A (instanceRef CMDWR)) + (portRef B (instanceRef C1WR)) + )) + (net C1WR (joined + (portRef Z (instanceRef C1WR)) + (portRef D (instanceRef CmdEnable_0_sqmuxa)) + (portRef A (instanceRef CmdEnable16_0_a3)) + (portRef B (instanceRef un1_CmdEnable20_0_a3)) + (portRef B (instanceRef ADSubmitted_r_RNO)) + (portRef C (instanceRef C1Submitted_RNO)) + )) + (net ADWR_8 (joined + (portRef Z (instanceRef ADWR_8)) + (portRef A (instanceRef un1_CmdEnable20_0_a3_0_2)) + (portRef A (instanceRef ADWR)) + )) + (net ADWR (joined + (portRef Z (instanceRef ADWR)) + (portRef A (instanceRef CmdEnable17_0_a3)) + (portRef A (instanceRef un1_CmdEnable20_0_a3)) + (portRef A (instanceRef ADSubmitted_r_RNO)) + (portRef D (instanceRef C1Submitted_RNO)) + )) + (net N_166 (joined + (portRef Z (instanceRef XOR8MEG_3_u_0_a3)) + (portRef C (instanceRef XOR8MEG_3_u_0_a3_0_2)) + )) + (net N_163 (joined + (portRef Z (instanceRef XOR8MEG_3_u_0_o2_0)) + (portRef A (instanceRef XOR8MEG_3_u_0_a3_0_1)) + (portRef A (instanceRef XOR8MEG_3_u_0_a3)) + )) + (net N_180 (joined + (portRef Z (instanceRef CmdEnable17_0_a2)) + (portRef D (instanceRef un1_CmdEnable20_0_a3_0_2)) + (portRef D (instanceRef CmdEnable17_0_a3)) + )) + (net XOR8MEG_3 (joined + (portRef Z (instanceRef XOR8MEG_3_u_0_a3_0_2)) + (portRef D (instanceRef XOR8MEG)) + )) + (net N_156 (joined + (portRef Z (instanceRef CmdEnable17_0_o2)) + (portRef C (instanceRef un1_CmdEnable20_0_a3_0_2)) + (portRef C (instanceRef CmdEnable17_0_a3)) + )) + (net N_122_5 (joined + (portRef Z (instanceRef CmdEnable17_0_a3_4)) + (portRef B (instanceRef un1_CmdEnable20_0_a3_0_2)) + (portRef B (instanceRef CmdEnable17_0_a3)) + )) + (net N_133_5 (joined + (portRef Z (instanceRef InitReady3_0_a2_5)) + (portRef D (instanceRef InitReady3_0_a2)) + (portRef D (instanceRef UFMCLK_r_i_a2_2_2)) + )) + (net N_133_3 (joined + (portRef Z (instanceRef InitReady3_0_a2_3)) + (portRef C (instanceRef InitReady3_0_a2)) + (portRef C (instanceRef UFMCLK_r_i_a2_2_2)) + )) + (net N_128 (joined + (portRef Z (instanceRef UFMSDI_ens2_i_o2_0)) + (portRef D (instanceRef nUFMCS15_0_a2)) + (portRef C (instanceRef UFMSDI_en_ss0_0_a2_0)) + (portRef C (instanceRef UFMSDI_ens2_i_a0)) + (portRef A (instanceRef UFMCLK_RNO_1)) + )) + (net N_34 (joined + (portRef Z (instanceRef UFMSDI_ens2_i_o2)) + (portRef B (instanceRef UFMSDI_ens2_i_a0)) + )) + (net N_94 (joined + (portRef Z (instanceRef UFMSDI_en_ss0_0_a2_0)) + (portRef C (instanceRef UFMSDI_RNO_0)) + (portRef A (instanceRef un1_FS_13_i_0)) + (portRef A (instanceRef un1_FS_14_i_0)) + )) + (net N_43 (joined + (portRef Z (instanceRef un1_FS_14_i_o2)) + (portRef B (instanceRef un1_FS_13_i_a2_1)) + (portRef B (instanceRef un1_FS_14_i_a2_0_1)) + )) + (net N_129 (joined + (portRef Z (instanceRef UFMCLK_RNO_1)) + (portRef D (instanceRef UFMCLK_RNO_0)) + )) + (net N_134 (joined + (portRef Z (instanceRef un1_FS_14_i_a2)) + (portRef B (instanceRef un1_FS_13_i_0)) + (portRef B (instanceRef un1_FS_14_i_0)) + )) + (net N_48 (joined + (portRef Z (instanceRef n8MEGEN_5_i_m2)) + (portRef D (instanceRef n8MEGEN)) + )) + (net N_49 (joined + (portRef Z (instanceRef LEDEN_5_i_m2)) + (portRef D (instanceRef LEDEN)) + )) + (net XOR8MEG_3_u_0_a3_0_1 (joined + (portRef Z (instanceRef XOR8MEG_3_u_0_a3_0_1)) + (portRef D (instanceRef XOR8MEG_3_u_0_a3_0_2)) )) (net UFMCLK_r_i_a2_2_2 (joined (portRef Z (instanceRef UFMCLK_r_i_a2_2_2)) @@ -1618,13 +1684,20 @@ (portRef Z (instanceRef UFMSDI_ens2_i_a0)) (portRef B (instanceRef UFMSDI_RNO_0)) )) - (net RCKEEN_8_u_0_0 (joined - (portRef Z (instanceRef RCKEEN_8_u_RNO)) - (portRef B (instanceRef RCKEEN_8_u)) + (net ADWR_8_2 (joined + (portRef Z (instanceRef ADWR_8_2)) + (portRef A (instanceRef ADWR_8)) + (portRef A (instanceRef C1WR_7)) )) - (net RCKEEN_8_u_0_a2_1_out (joined - (portRef Z (instanceRef RCKEEN_8_u_0_a2_1_s)) - (portRef D (instanceRef nRCS_RNO)) + (net CmdLEDEN_4_u_i_a2_0_0 (joined + (portRef Z (instanceRef CmdLEDEN_4_u_i_a2_0_0)) + (portRef B (instanceRef CmdLEDEN_4_u_i_0)) + (portRef A (instanceRef Cmdn8MEGEN_4_u_i_0)) + )) + (net RCKEEN_8_u_0_1_a1_0 (joined + (portRef Z (instanceRef RCKEEN_8_u_0_1_a1_0)) + (portRef B (instanceRef RCKEEN_8_u_0_1_1)) + (portRef CD (instanceRef S_0)) )) (net nCRAS_c_i (joined (portRef Z (instanceRef nCRAS_pad_RNIBPVB)) @@ -1645,12 +1718,6 @@ (portRef CK (instanceRef RowA_1)) (portRef CK (instanceRef RowA_0)) )) - (net N_159_i (joined - (portRef Z (instanceRef IS_0_sqmuxa_0_o2_0_RNIS63D)) - (portRef SP (instanceRef IS_3)) - (portRef SP (instanceRef IS_2)) - (portRef SP (instanceRef IS_1)) - )) (net RD_1_i (joined (portRef Z (instanceRef nCCAS_pad_RNI01SJ)) (portRef T (instanceRef RD_pad_0)) @@ -1662,15 +1729,21 @@ (portRef T (instanceRef RD_pad_6)) (portRef T (instanceRef RD_pad_7)) )) - (net N_28_i (joined + (net N_153_i (joined + (portRef Z (instanceRef IS_0_sqmuxa_0_o2_0_RNIS63D)) + (portRef SP (instanceRef IS_3)) + (portRef SP (instanceRef IS_2)) + (portRef SP (instanceRef IS_1)) + )) + (net N_143_i (joined (portRef Z (instanceRef nRCS_RNO)) (portRef D (instanceRef nRCS)) )) - (net N_37_i (joined + (net N_46_i (joined (portRef Z (instanceRef nRCAS_RNO)) (portRef D (instanceRef nRCAS)) )) - (net N_24_i (joined + (net N_142_i (joined (portRef Z (instanceRef nRRAS_RNO)) (portRef D (instanceRef nRRAS)) )) @@ -1678,40 +1751,44 @@ (portRef Z (instanceRef nUFMCS_s_0_N_5_i)) (portRef D (instanceRef nUFMCS)) )) - (net N_39_i (joined + (net N_144_i (joined (portRef Z (instanceRef nRWE_RNO)) (portRef D (instanceRef nRWE)) )) - (net N_64_i_i (joined + (net N_77_i_i (joined (portRef Z (instanceRef IS_RNO_0)) (portRef D (instanceRef IS_0)) )) - (net N_61_i_i (joined + (net N_75_i_i (joined (portRef Z (instanceRef IS_RNO_3)) (portRef D (instanceRef IS_3)) )) - (net N_60_i_i (joined + (net N_74_i_i (joined (portRef Z (instanceRef IS_RNO_2)) (portRef D (instanceRef IS_2)) )) - (net N_177_i (joined - (portRef Z (instanceRef S_RNO_0)) - (portRef D (instanceRef S_0)) - )) - (net N_21_i (joined + (net N_14_i (joined (portRef Z (instanceRef CmdLEDEN_RNO)) (portRef D (instanceRef CmdLEDEN)) )) - (net N_19_i (joined + (net N_12_i (joined (portRef Z (instanceRef Cmdn8MEGEN_RNO)) (portRef D (instanceRef Cmdn8MEGEN)) )) - (net N_139_i (joined + (net un1_CmdEnable20_i (joined + (portRef Z (instanceRef CmdEnable_s_RNO)) + (portRef C (instanceRef CmdEnable_s)) + )) + (net N_137_i (joined (portRef Z (instanceRef PHI2r3_RNITCN41)) (portRef A (instanceRef nUFMCS_s_0_N_5_i)) (portRef A (instanceRef UFMCLK_RNO)) (portRef A (instanceRef UFMSDI_RNO)) )) + (net N_183_i (joined + (portRef Z (instanceRef ADSubmitted_r_RNO)) + (portRef B (instanceRef ADSubmitted_r)) + )) (net (rename FS_cry_0 "FS_cry[0]") (joined (portRef COUT0 (instanceRef FS_cry_0_0)) )) @@ -1847,29 +1924,49 @@ (portRef Z (instanceRef RA10_RNO)) (portRef PD (instanceRef RA10)) )) + (net ADWR_8_4 (joined + (portRef Z (instanceRef ADWR_8_4)) + (portRef B (instanceRef ADWR_8)) + )) (net Cmdn8MEGEN_4_u_i_0 (joined (portRef Z (instanceRef Cmdn8MEGEN_4_u_i_0)) (portRef A (instanceRef Cmdn8MEGEN_RNO)) )) + (net CmdLEDEN_4_u_i_0 (joined + (portRef Z (instanceRef CmdLEDEN_4_u_i_0)) + (portRef A (instanceRef CmdLEDEN_RNO)) + )) + (net RCKEEN_8_u_0_a3_0_0 (joined + (portRef Z (instanceRef RCKEEN_8_u_0_a3_0_0)) + (portRef C (instanceRef RCKEEN_8_u_0_1_1)) + )) + (net un1_Bank_1_4 (joined + (portRef Z (instanceRef un1_Bank_1_4)) + (portRef C (instanceRef C1WR_7)) + (portRef C (instanceRef ADWR)) + )) + (net un1_Bank_1_5 (joined + (portRef Z (instanceRef un1_Bank_1_5)) + (portRef D (instanceRef C1WR_7)) + (portRef D (instanceRef ADWR)) + )) + (net un1_CmdEnable20_0_a3_0_2 (joined + (portRef Z (instanceRef un1_CmdEnable20_0_a3_0_2)) + (portRef D (instanceRef CmdEnable_s_RNO)) + )) (net UFMSDI_ens2_i_o2_0_3 (joined (portRef Z (instanceRef UFMSDI_ens2_i_o2_0_3)) (portRef C (instanceRef UFMSDI_ens2_i_o2_0)) )) - (net C1WR_0_a2_0_3 (joined - (portRef Z (instanceRef C1WR_0_a2_0_3)) - (portRef C (instanceRef C1WR_0_a2_0_10)) + (net un1_FS_13_i_a2_9_4 (joined + (portRef Z (instanceRef un1_FS_13_i_a2_9_4)) + (portRef C (instanceRef un1_FS_13_i_a2_1)) + (portRef C (instanceRef un1_FS_14_i_a2_0_1)) )) - (net C1WR_0_a2_0_4 (joined - (portRef Z (instanceRef C1WR_0_a2_0_4)) - (portRef D (instanceRef C1WR_0_a2_0_10)) - )) - (net C1WR_0_a2_0_10 (joined - (portRef Z (instanceRef C1WR_0_a2_0_10)) - (portRef C (instanceRef C1WR_0_a2_0)) - )) - (net C1WR_0_a2_0_11 (joined - (portRef Z (instanceRef C1WR_0_a2_0_11)) - (portRef D (instanceRef C1WR_0_a2_0)) + (net un1_FS_13_i_a2_9_5 (joined + (portRef Z (instanceRef un1_FS_13_i_a2_9_5)) + (portRef D (instanceRef un1_FS_13_i_a2_1)) + (portRef D (instanceRef un1_FS_14_i_a2_0_1)) )) (net Ready_0_sqmuxa_0_a3_2 (joined (portRef Z (instanceRef Ready_0_sqmuxa_0_a3_2)) @@ -1880,43 +1977,68 @@ (portRef Z (instanceRef UFMSDI_ens2_i_a2_4_2)) (portRef D (instanceRef UFMSDI_ens2_i_a0)) )) - (net CmdEnable16_0_a2_4 (joined - (portRef Z (instanceRef CmdEnable16_0_a2_4_0)) - (portRef A (instanceRef CmdEnable16_0_a2)) + (net RCKEEN_8_u_0_0 (joined + (portRef Z (instanceRef RCKEEN_8_u_0_0)) + (portRef B (instanceRef RCKEEN_8_u_0)) )) - (net CmdEnable16_0_a2_5 (joined - (portRef Z (instanceRef CmdEnable16_0_a2_5)) - (portRef B (instanceRef CmdEnable16_0_a2)) + (net C1WR_2_0 (joined + (portRef Z (instanceRef C1WR_2_0)) + (portRef A (instanceRef C1WR)) + )) + (net CMDWR_2 (joined + (portRef Z (instanceRef CMDWR_2)) + (portRef B (instanceRef CMDWR)) )) (net nRRAS_5_u_i_0 (joined (portRef Z (instanceRef nRRAS_5_u_i_0)) - (portRef A (instanceRef nRRAS_RNO)) - (portRef D (instanceRef nRRAS_5_u_i)) - )) - (net CmdEnable17_0_a2_3 (joined - (portRef Z (instanceRef CmdEnable17_0_a2_3)) - (portRef A (instanceRef CmdEnable17_0_a2)) - )) - (net CmdEnable17_0_a2_4 (joined - (portRef Z (instanceRef CmdEnable17_0_a2_4)) - (portRef B (instanceRef CmdEnable17_0_a2)) - )) - (net un1_FS_13_i_a2_1 (joined - (portRef Z (instanceRef un1_FS_13_i_a2_1)) - (portRef D (instanceRef un1_FS_13_i_0)) + (portRef D (instanceRef nRRAS_RNO)) )) (net un1_FS_14_i_a2_0_1 (joined (portRef Z (instanceRef un1_FS_14_i_a2_0_1)) - (portRef D (instanceRef un1_FS_14_i_0)) + (portRef C (instanceRef un1_FS_14_i_0)) + )) + (net un1_FS_13_i_a2_1 (joined + (portRef Z (instanceRef un1_FS_13_i_a2_1)) + (portRef C (instanceRef un1_FS_13_i_0)) + )) + (net CmdEnable16_0_a3_4 (joined + (portRef Z (instanceRef CmdEnable16_0_a3_4)) + (portRef C (instanceRef CmdEnable_0_sqmuxa)) + (portRef B (instanceRef CmdEnable16_0_a3)) + )) + (net CmdEnable16_0_a3_5 (joined + (portRef Z (instanceRef CmdEnable16_0_a3_5)) + (portRef B (instanceRef CmdEnable_0_sqmuxa)) + (portRef C (instanceRef CmdEnable16_0_a3)) )) (net (rename FS_cry_0_COUT1_16 "FS_cry_0_COUT1[16]") (joined (portRef COUT1 (instanceRef FS_cry_0_16)) )) - (net RCKEEN_8_u_1 (joined - (portRef Z (instanceRef RCKEEN_8_u_1_0)) - (portRef C (instanceRef RCKEEN_8_u)) + (net RCKEEN_8_u_0_1_1 (joined + (portRef Z (instanceRef RCKEEN_8_u_0_1_1)) + (portRef C (instanceRef RCKEEN_8_u_0)) )) - (net N_28_i_1 (joined + (net g3 (joined + (portRef Z (instanceRef nRCS_RNO_5)) + (portRef D (instanceRef nRCS_RNO_2)) + )) + (net N_9 (joined + (portRef Z (instanceRef nRCS_RNO_2)) + (portRef B (instanceRef nRCS_RNO_0)) + )) + (net g0_i_a5_1 (joined + (portRef Z (instanceRef nRCS_RNO_3)) + (portRef D (instanceRef nRCS_RNO_0)) + )) + (net g0_i_a5_1_2 (joined + (portRef Z (instanceRef nRCS_RNO_1)) + (portRef D (instanceRef nRCS_RNO)) + )) + (net g0_i_a5_2_1 (joined + (portRef Z (instanceRef nRCS_RNO_4)) + (portRef C (instanceRef nRCS_RNO_2)) + )) + (net g0_i_0 (joined (portRef Z (instanceRef nRCS_RNO_0)) (portRef C (instanceRef nRCS_RNO)) )) @@ -1936,29 +2058,31 @@ (portRef Z (instanceRef nRWE_RNO_0)) (portRef B (instanceRef nRWE_RNO)) )) - (net g0_1 (joined - (portRef Z (instanceRef nRCAS_RNO_0)) - (portRef D (instanceRef nRCAS_RNO)) - )) - (net g4_0_0_0 (joined - (portRef Z (instanceRef nRCAS_RNO_1)) - (portRef D (instanceRef nRCAS_RNO_0)) - )) (net CBR_fast (joined (portRef Q (instanceRef CBR_fast)) - (portRef A (instanceRef nRCAS_RNO_0)) + (portRef A (instanceRef nRWE_RNO_0)) + (portRef A (instanceRef RCKEEN_8_u_0_a2_0_m1_0_a2)) (portRef A (instanceRef nRCAS_0_sqmuxa_1_0_a3)) )) (net FWEr_fast (joined (portRef Q (instanceRef FWEr_fast)) - (portRef C (instanceRef RCKEEN_8_u_1_0)) - (portRef A (instanceRef nRCS_RNO_0)) + (portRef D (instanceRef nRCAS_RNO_0)) + (portRef D (instanceRef nRCS_RNO_1)) + (portRef A (instanceRef RCKEEN_8_u_0_1_1)) )) (net Ready_fast (joined (portRef Q (instanceRef Ready_fast)) (portRef B (instanceRef Ready_fast_RNO)) (portRef A (instanceRef Ready_fast_RNI29NA)) )) + (net G_1_0 (joined + (portRef Z (instanceRef nRCAS_RNO_0)) + (portRef A (instanceRef nRCAS_RNO)) + )) + (net G_1_1 (joined + (portRef Z (instanceRef nRCAS_RNO_1)) + (portRef B (instanceRef nRCAS_RNO)) + )) (net UFMSDI_r_xx_mm_1 (joined (portRef Z (instanceRef UFMSDI_RNO_0)) (portRef D (instanceRef UFMSDI_RNO)) @@ -2066,11 +2190,10 @@ )) (net (rename MAin_c_0 "MAin_c[0]") (joined (portRef O (instanceRef MAin_pad_0)) - (portRef B (instanceRef un1_CMDWR)) (portRef A (instanceRef un9_RA_0)) - (portRef D (instanceRef CmdEnable16_0_a2_4_0)) - (portRef B (instanceRef XOR8MEG18_0_a2)) - (portRef C (instanceRef CmdEnable17_0_a2)) + (portRef A (instanceRef ADWR_8_4)) + (portRef A (instanceRef C1WR_2_0)) + (portRef C (instanceRef CMDWR)) (portRef D (instanceRef RowA_0)) )) (net (rename MAin_0 "MAin[0]") (joined @@ -2079,14 +2202,11 @@ )) (net (rename MAin_c_1 "MAin_c[1]") (joined (portRef O (instanceRef MAin_pad_1)) - (portRef C (instanceRef un1_CMDWR)) (portRef A (instanceRef un9_RA_1)) - (portRef C (instanceRef CmdEnable17_0_a2_4)) - (portRef D (instanceRef CmdEnable16_0_a2_5)) - (portRef A (instanceRef C1WR_0_a2)) - (portRef C (instanceRef XOR8MEG18_0_a2)) + (portRef B (instanceRef ADWR_8_4)) + (portRef A (instanceRef CMDWR_2)) + (portRef B (instanceRef C1WR_2_0)) (portRef D (instanceRef RowA_1)) - (portRef D (instanceRef C1Submitted_RNO)) )) (net (rename MAin_1 "MAin[1]") (joined (portRef (member main 8)) @@ -2095,7 +2215,9 @@ (net (rename MAin_c_2 "MAin_c[2]") (joined (portRef O (instanceRef MAin_pad_2)) (portRef A (instanceRef un9_RA_2)) - (portRef A (instanceRef C1WR_0_a2_0_3)) + (portRef B (instanceRef CMDWR_2)) + (portRef C (instanceRef ADWR_8)) + (portRef C (instanceRef C1WR)) (portRef D (instanceRef RowA_2)) )) (net (rename MAin_2 "MAin[2]") (joined @@ -2105,7 +2227,9 @@ (net (rename MAin_c_3 "MAin_c[3]") (joined (portRef O (instanceRef MAin_pad_3)) (portRef A (instanceRef un9_RA_3)) - (portRef B (instanceRef C1WR_0_a2_0_3)) + (portRef C (instanceRef CMDWR_2)) + (portRef C (instanceRef C1WR_2_0)) + (portRef D (instanceRef ADWR_8)) (portRef D (instanceRef RowA_3)) )) (net (rename MAin_3 "MAin[3]") (joined @@ -2115,7 +2239,9 @@ (net (rename MAin_c_4 "MAin_c[4]") (joined (portRef O (instanceRef MAin_pad_4)) (portRef A (instanceRef un9_RA_4)) - (portRef A (instanceRef C1WR_0_a2_0_4)) + (portRef C (instanceRef ADWR_8_4)) + (portRef D (instanceRef CMDWR_2)) + (portRef D (instanceRef C1WR_2_0)) (portRef D (instanceRef RowA_4)) )) (net (rename MAin_4 "MAin[4]") (joined @@ -2125,7 +2251,8 @@ (net (rename MAin_c_5 "MAin_c[5]") (joined (portRef O (instanceRef MAin_pad_5)) (portRef A (instanceRef un9_RA_5)) - (portRef B (instanceRef C1WR_0_a2_0_4)) + (portRef D (instanceRef ADWR_8_4)) + (portRef B (instanceRef C1WR_7)) (portRef D (instanceRef RowA_5)) )) (net (rename MAin_5 "MAin[5]") (joined @@ -2134,8 +2261,8 @@ )) (net (rename MAin_c_6 "MAin_c[6]") (joined (portRef O (instanceRef MAin_pad_6)) + (portRef A (instanceRef ADWR_8_2)) (portRef A (instanceRef un9_RA_6)) - (portRef C (instanceRef C1WR_0_a2_0_4)) (portRef D (instanceRef RowA_6)) )) (net (rename MAin_6 "MAin[6]") (joined @@ -2144,8 +2271,8 @@ )) (net (rename MAin_c_7 "MAin_c[7]") (joined (portRef O (instanceRef MAin_pad_7)) + (portRef B (instanceRef ADWR_8_2)) (portRef A (instanceRef un9_RA_7)) - (portRef D (instanceRef C1WR_0_a2_0_4)) (portRef D (instanceRef RowA_7)) )) (net (rename MAin_7 "MAin[7]") (joined @@ -2163,8 +2290,8 @@ )) (net (rename MAin_c_9 "MAin_c[9]") (joined (portRef O (instanceRef MAin_pad_9)) - (portRef A (instanceRef RDQML)) (portRef A (instanceRef RDQMH)) + (portRef A (instanceRef RDQML)) (portRef A (instanceRef un9_RA_9)) (portRef D (instanceRef RowA_9)) )) @@ -2190,9 +2317,10 @@ )) (net (rename Din_c_0 "Din_c[0]") (joined (portRef O (instanceRef Din_pad_0)) - (portRef B (instanceRef CmdEnable17_0_a2_3)) - (portRef A (instanceRef CmdEnable16_0_a2_4)) - (portRef A (instanceRef XOR8MEG_3_u_0_a3_2)) + (portRef D (instanceRef XOR8MEG_3_u_0_a3_0_1)) + (portRef A (instanceRef CmdEnable17_0_a2)) + (portRef A (instanceRef CmdEnable16_0_a3_4)) + (portRef C (instanceRef Cmdn8MEGEN_4_u_i_0)) (portRef D (instanceRef Bank_0)) (portRef D (instanceRef CmdUFMSDI)) (portRef D (instanceRef WRD_0)) @@ -2203,10 +2331,10 @@ )) (net (rename Din_c_1 "Din_c[1]") (joined (portRef O (instanceRef Din_pad_1)) - (portRef A (instanceRef CmdEnable17_0_a2_3)) - (portRef B (instanceRef CmdEnable16_0_a2_4_0)) - (portRef A (instanceRef CmdLEDEN_4_u_i_a2_0)) - (portRef A (instanceRef XOR8MEG_3_u_0_a3_3)) + (portRef A (instanceRef CmdEnable16_0_a3_5)) + (portRef A (instanceRef CmdEnable17_0_a3_4)) + (portRef C (instanceRef CmdLEDEN_4_u_i_0)) + (portRef A (instanceRef XOR8MEG_3_u_0_a3_0_2)) (portRef D (instanceRef Bank_1)) (portRef D (instanceRef CmdUFMCLK)) (portRef D (instanceRef WRD_1)) @@ -2217,9 +2345,9 @@ )) (net (rename Din_c_2 "Din_c[2]") (joined (portRef O (instanceRef Din_pad_2)) - (portRef A (instanceRef CmdEnable17_0_a2_4)) - (portRef B (instanceRef CmdEnable16_0_a2_5)) - (portRef B (instanceRef XOR8MEG_3_u_0_a3_2)) + (portRef C (instanceRef XOR8MEG_3_u_0_a3_0_1)) + (portRef B (instanceRef CmdEnable17_0_a2)) + (portRef B (instanceRef CmdEnable16_0_a3_5)) (portRef D (instanceRef Bank_2)) (portRef D (instanceRef CmdUFMCS)) (portRef D (instanceRef WRD_2)) @@ -2230,13 +2358,13 @@ )) (net (rename Din_c_3 "Din_c[3]") (joined (portRef O (instanceRef Din_pad_3)) - (portRef D (instanceRef CmdUFMCLK_1_sqmuxa_0_a2)) - (portRef D (instanceRef CmdLEDEN_4_u_i_a2)) (portRef D (instanceRef CmdSubmitted_1_sqmuxa_0_a2)) - (portRef A (instanceRef CmdEnable17_0_o2)) - (portRef C (instanceRef CmdEnable16_0_a2_4_0)) + (portRef D (instanceRef CmdUFMCLK_1_sqmuxa_0_a2)) + (portRef B (instanceRef XOR8MEG_3_u_0_a3_0_1)) + (portRef C (instanceRef CmdEnable16_0_a3_5)) + (portRef B (instanceRef CmdEnable17_0_a3_4)) + (portRef A (instanceRef Cmdn8MEGEN_4_u_i_o2)) (portRef A (instanceRef Cmdn8MEGEN_4_u_i_a2_2)) - (portRef C (instanceRef XOR8MEG_3_u_0_a3_2)) (portRef D (instanceRef Bank_3)) (portRef D (instanceRef WRD_3)) )) @@ -2246,9 +2374,10 @@ )) (net (rename Din_c_4 "Din_c[4]") (joined (portRef O (instanceRef Din_pad_4)) - (portRef D (instanceRef CmdEnable17_0_a2_3)) - (portRef A (instanceRef CmdEnable16_0_a2_1)) - (portRef A (instanceRef un1_Din_4)) + (portRef D (instanceRef XOR8MEG_3_u_0_o2_0)) + (portRef D (instanceRef CmdLEDEN_4_u_i_a2_0_0)) + (portRef A (instanceRef CmdEnable17_0_o2)) + (portRef D (instanceRef CmdEnable16_0_a3_5)) (portRef A (instanceRef Cmdn8MEGEN_4_u_i_o2_0)) (portRef D (instanceRef Bank_4)) (portRef D (instanceRef WRD_4)) @@ -2259,13 +2388,13 @@ )) (net (rename Din_c_5 "Din_c[5]") (joined (portRef O (instanceRef Din_pad_5)) - (portRef C (instanceRef CmdUFMCLK_1_sqmuxa_0_a2)) - (portRef C (instanceRef CmdLEDEN_4_u_i_a2)) (portRef C (instanceRef CmdSubmitted_1_sqmuxa_0_a2)) - (portRef B (instanceRef CmdEnable17_0_o2)) - (portRef B (instanceRef CmdEnable16_0_a2_4)) - (portRef B (instanceRef un1_Din_4)) - (portRef B (instanceRef CmdLEDEN_4_u_i_a2_0)) + (portRef C (instanceRef CmdUFMCLK_1_sqmuxa_0_a2)) + (portRef B (instanceRef XOR8MEG_3_u_0_o2_0)) + (portRef A (instanceRef CmdLEDEN_4_u_i_a2_0_0)) + (portRef B (instanceRef CmdEnable16_0_a3_4)) + (portRef C (instanceRef CmdEnable17_0_a3_4)) + (portRef B (instanceRef Cmdn8MEGEN_4_u_i_o2)) (portRef B (instanceRef Cmdn8MEGEN_4_u_i_a2_2)) (portRef D (instanceRef Bank_5)) (portRef D (instanceRef WRD_5)) @@ -2276,11 +2405,12 @@ )) (net (rename Din_c_6 "Din_c[6]") (joined (portRef O (instanceRef Din_pad_6)) - (portRef C (instanceRef un1_Din_4)) - (portRef A (instanceRef RA11_2)) + (portRef C (instanceRef XOR8MEG_3_u_0_o2_0)) + (portRef C (instanceRef CmdLEDEN_4_u_i_a2_0_0)) + (portRef B (instanceRef CmdEnable17_0_o2)) + (portRef C (instanceRef CmdEnable16_0_a3_4)) (portRef B (instanceRef Cmdn8MEGEN_4_u_i_o2_0)) - (portRef B (instanceRef CmdEnable17_0_a2_4)) - (portRef C (instanceRef CmdEnable16_0_a2_5)) + (portRef A (instanceRef RA11_2)) (portRef D (instanceRef Bank_6)) (portRef D (instanceRef WRD_6)) )) @@ -2290,10 +2420,11 @@ )) (net (rename Din_c_7 "Din_c[7]") (joined (portRef O (instanceRef Din_pad_7)) - (portRef C (instanceRef CmdEnable17_0_a2_3)) - (portRef B (instanceRef CmdEnable16_0_a2_1)) - (portRef D (instanceRef un1_Din_4)) + (portRef A (instanceRef XOR8MEG_3_u_0_o2_0)) + (portRef B (instanceRef CmdLEDEN_4_u_i_a2_0_0)) + (portRef D (instanceRef CmdEnable16_0_a3_4)) (portRef C (instanceRef Cmdn8MEGEN_4_u_i_o2_0)) + (portRef D (instanceRef CmdEnable17_0_a3_4)) (portRef D (instanceRef Bank_7)) (portRef D (instanceRef WRD_7)) )) @@ -2344,7 +2475,7 @@ )) (net nCRAS_c (joined (portRef O (instanceRef nCRAS_pad)) - (portRef C (instanceRef LED_pad_RNO)) + (portRef D (instanceRef LED_pad_RNO)) (portRef A (instanceRef nCRAS_pad_RNIBPVB)) (portRef A (instanceRef RASr_RNO)) )) @@ -2354,8 +2485,10 @@ )) (net nFWE_c (joined (portRef O (instanceRef nFWE_pad)) - (portRef C (instanceRef C1WR_0_a2_0_3)) (portRef B (instanceRef nCCAS_pad_RNI01SJ)) + (portRef D (instanceRef CMDWR)) + (portRef B (instanceRef ADWR)) + (portRef D (instanceRef C1WR)) (portRef A (instanceRef nFWE_pad_RNI420B)) )) (net nFWE (joined @@ -2612,6 +2745,7 @@ )) (net RCKE_c (joined (portRef Q (instanceRef RCKE)) + (portRef B (instanceRef nRCS_RNO_3)) (portRef C (instanceRef nRRAS_5_u_i_0)) (portRef I (instanceRef RCKE_pad)) (portRef C (instanceRef nRWE_RNO_3)) @@ -2696,19 +2830,19 @@ (portRef UFMSDO) (portRef I (instanceRef UFMSDO_pad)) )) - (net N_460_0 (joined + (net N_428_0 (joined (portRef Z (instanceRef CmdSubmitted_RNO)) (portRef D (instanceRef CmdSubmitted)) )) - (net N_461_0 (joined + (net N_429_0 (joined (portRef Z (instanceRef InitReady_RNO)) (portRef D (instanceRef InitReady)) )) - (net N_462_0 (joined + (net N_430_0 (joined (portRef Z (instanceRef Ready_RNO)) (portRef D (instanceRef Ready)) )) - (net N_463_0 (joined + (net N_431_0 (joined (portRef Z (instanceRef Ready_fast_RNO)) (portRef D (instanceRef Ready_fast)) )) @@ -2751,14 +2885,9 @@ (portRef CD (instanceRef RowA_1)) (portRef CD (instanceRef RowA_0)) )) - (net (rename IS_i_0 "IS_i[0]") (joined - (portRef Z (instanceRef IS_i_0)) - (portRef D (instanceRef RA10)) - )) (net RASr2_i (joined - (portRef Z (instanceRef RASr2_RNIAFR1)) + (portRef Z (instanceRef S_RNO_1)) (portRef CD (instanceRef S_1)) - (portRef CD (instanceRef S_0)) )) (net nRWE_RNO_4 (joined (portRef Z (instanceRef nRWE_RNO_4)) @@ -2768,14 +2897,6 @@ (portRef Z (instanceRef nRWE_RNO_3)) (portRef ALUT (instanceRef nRWE_RNO_1)) )) - (net CmdEnable_s_am (joined - (portRef Z (instanceRef CmdEnable_s_am)) - (portRef BLUT (instanceRef CmdEnable_s)) - )) - (net CmdEnable_s_bm (joined - (portRef Z (instanceRef CmdEnable_s_bm)) - (portRef ALUT (instanceRef CmdEnable_s)) - )) ) (property orig_inst_of (string "RAM2GS")) ) diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.jed b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.jed index a8a596c..56a7053 100644 --- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.jed +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.jed @@ -6,7 +6,7 @@ NOTE Readback: Off* NOTE Security: Off* NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation * NOTE All Rights Reserved * -NOTE DATE CREATED: Thu Sep 21 05:38:46 2023 * +NOTE DATE CREATED: Sat Jan 06 06:25:24 2024 * NOTE DESIGN NAME: RAM2GS * NOTE DEVICE NAME: LCMXO640C-3TQFP100 * NOTE PIN ASSIGNMENTS * @@ -97,1649 +97,1649 @@ L000000 11111111111111111111111110111111111111111111111011111111111111111111101111001011 11111101111011111111111111111111101111111111111111111110111111111111111111111011 1111111111111111111011110010100100110101110111001010010011010111011111111111 -11111111111111111111111111111111111111111111111111111111111111111111111111111111 -11111111111111111111111111111111111111111111111111111111111111111111111111111111 -1111111111111111111111111111111111111111111111111111111111111111111111111111 -11111111111111111111111111111111111111111111111100111111111111111111111111111111 -11001111111011111111111111111111011111111111111111111111111111111111111111111110 +11111111111111111111111111111111111111111111111111111111111111111101111111111111 +11111111011111111111111111111111111111111111111111111111111111111111111111111111 1111111111111111111111111111111111111111111111111111111111111111111111111111 11111111111111111111111111111111111111111111111111111111111111111111111111111111 -11111111111101111111011111111111101111111111111111111111111111111111111111111110 +11111111111111111111111111111111111011111111111111111111111111111111111111110111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +00111111111111111111111111111111111011111111111111111111111111111111111111111011 1111111111111111111111111111111111111111111111111111111111111111111111111111 11111111111111111111111111111111111111111111111111111111111111111111111111111111 11111111111111111111111111111111111111111111111111111111111111111111111111111111 1111111111111111111111111101111111111111111111111111111111111111111111111111 -11111111111111111111111111111111111111111111111111111111111111111111111111111111 -11111111111111111111011111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111101111111111111 +11111111011111111111111111111111111111111111111111111111111111111111111111111111 1111111111111111111111111111111111111111111111111111111111111111111111111111 11111111111111111111111111111111111111111111111111111111111111111111111111111111 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11111111111011111111111111111111101111111111111111111110111100110001001111001011 -1100110001001111011001110011000100111100100111001010010011110111101111111111 +1100110001001111011001110011000100111100100111001010010011110111011111111111 * -C573C* +C51D4* N User Electronic Signature Data* U00000000000000000000000000000000* -47CC +46DD diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mrp b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mrp index eb21316..e3c279e 100644 --- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mrp +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mrp @@ -15,18 +15,18 @@ Target Vendor: LATTICE Target Device: LCMXO640CTQFP100 Target Performance: 3 Mapper: mj5g00, version: Diamond (64-bit) 3.12.1.454 -Mapped on: 09/21/23 05:38:31 +Mapped on: 01/06/24 06:25:09 Design Summary -------------- Number of PFU registers: 92 out of 640 (14%) - Number of SLICEs: 69 out of 320 (22%) - SLICEs as Logic/ROM: 69 out of 320 (22%) + Number of SLICEs: 76 out of 320 (24%) + SLICEs as Logic/ROM: 76 out of 320 (24%) SLICEs as RAM: 0 out of 192 (0%) SLICEs as Carry: 9 out of 320 (3%) - Number of LUT4s: 137 out of 640 (21%) - Number used as logic LUTs: 119 + Number of LUT4s: 151 out of 640 (24%) + Number used as logic LUTs: 133 Number used as distributed RAM: 0 Number used as ripple logic: 18 Number used as shift registers: 0 @@ -49,37 +49,38 @@ Design Summary Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS ) Number of Clock Enables: 5 Net XOR8MEG18: 3 loads, 3 LSLICEs - Net N_31: 1 loads, 1 LSLICEs - Net N_33: 1 loads, 1 LSLICEs - Net N_159_i: 2 loads, 2 LSLICEs + Net N_24: 1 loads, 1 LSLICEs + Net N_26: 1 loads, 1 LSLICEs + Net N_153_i: 2 loads, 2 LSLICEs Net CmdUFMCLK_1_sqmuxa: 2 loads, 2 LSLICEs - Number of LSRs: 4 + Number of LSRs: 5 Net RA10s_i: 1 loads, 1 LSLICEs Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs - Net RASr2: 2 loads, 2 LSLICEs + Net RASr2: 1 loads, 1 LSLICEs Net Ready_fast: 7 loads, 7 LSLICEs + Net RCKEEN_8_u_0_1_a1_0: 1 loads, 1 LSLICEs Number of nets driven by tri-state buffers: 0 - Top 10 highest fanout non-clock nets: Page 1 -Design: RAM2GS Date: 09/21/23 05:38:31 +Design: RAM2GS Date: 01/06/24 06:25:09 Design Summary (cont) --------------------- - Net InitReady: 16 loads - Net Ready: 16 loads - Net S[1]: 13 loads - Net CO0: 12 loads + Top 10 highest fanout non-clock nets: + Net Ready: 18 loads + Net InitReady: 17 loads + Net S[1]: 17 loads + Net CO0: 16 loads + Net RASr2: 13 loads Net nRowColSel: 12 loads - Net RASr2: 11 loads Net Din_c[5]: 10 loads Net Din_c[3]: 9 loads Net IS[0]: 9 loads - Net MAin_c[1]: 8 loads + Net IS[1]: 8 loads @@ -125,17 +126,17 @@ IO (PIO) Attributes | nRWE | OUTPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | RCKE | OUTPUT | LVCMOS33 | | | -+---------------------+-----------+-----------+------------+------------+ Page 2 -Design: RAM2GS Date: 09/21/23 05:38:31 +Design: RAM2GS Date: 01/06/24 06:25:09 IO (PIO) Attributes (cont) -------------------------- ++---------------------+-----------+-----------+------------+------------+ | RCLK | INPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | nRCS | OUTPUT | LVCMOS33 | | | @@ -191,17 +192,17 @@ IO (PIO) Attributes (cont) | nCCAS | INPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | Dout[7] | OUTPUT | LVCMOS33 | | | -+---------------------+-----------+-----------+------------+------------+ Page 3 -Design: RAM2GS Date: 09/21/23 05:38:31 +Design: RAM2GS Date: 01/06/24 06:25:09 IO (PIO) Attributes (cont) -------------------------- ++---------------------+-----------+-----------+------------+------------+ | Dout[6] | OUTPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | Dout[5] | OUTPUT | LVCMOS33 | | | @@ -258,13 +259,12 @@ IO (PIO) Attributes (cont) - Page 4 -Design: RAM2GS Date: 09/21/23 05:38:31 +Design: RAM2GS Date: 01/06/24 06:25:09 Removed logic ------------- @@ -275,7 +275,6 @@ Signal nFWE_c_i was merged into signal nFWE_c Signal nCRAS_c_i_0 was merged into signal nCRAS_c Signal nCCAS_c_i was merged into signal nCCAS_c Signal Ready_fast_i was merged into signal Ready_fast -Signal IS_i[0] was merged into signal IS[0] Signal RASr2_i was merged into signal RASr2 Signal XOR8MEG.CN was merged into signal PHI2_c Signal GND undriven or does not drive anything - clipped. @@ -295,8 +294,7 @@ Block nFWE_pad_RNI420B was optimized away. Block RASr_RNO was optimized away. Block nCCAS_pad_RNISUR8 was optimized away. Block Ready_fast_RNI29NA was optimized away. -Block IS_i[0] was optimized away. -Block RASr2_RNIAFR1 was optimized away. +Block S_RNO[1] was optimized away. Block XOR8MEG.CN was optimized away. Block GND was optimized away. Block VCC was optimized away. @@ -325,6 +323,8 @@ Run Time and Memory Usage + + Page 5 diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.pad b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.pad index 9f4fec4..5d64465 100644 --- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.pad +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.pad @@ -6,7 +6,7 @@ Performance Grade: 3 PACKAGE: TQFP100 Package Status: Final Version 1.17 -Thu Sep 21 05:38:41 2023 +Sat Jan 06 06:25:19 2024 Pinout by Port Name: +-----------+----------+---------------+-------+----------------------------------+ @@ -349,5 +349,5 @@ Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Thu Sep 21 05:38:41 2023 +Sat Jan 06 06:25:19 2024 diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.prf b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.prf index 942577e..04ed1fa 100644 --- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.prf +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.prf @@ -1,5 +1,5 @@ SCHEMATIC START ; -# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Thu Sep 21 05:38:31 2023 +# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Sat Jan 06 06:25:10 2024 SYSCONFIG INBUF=ON CONFIG_SECURE=OFF ; LOCATE COMP "RD[0]" SITE "64" ; diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.srr b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.srr index 2c8659c..b0e4d15 100644 --- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.srr +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.srr @@ -3,7 +3,7 @@ #OS: Windows 8 6.2 #Hostname: ZANEMACWIN11 -# Thu Sep 21 05:38:18 2023 +# Sat Jan 6 06:25:00 2024 #Implementation: impl1 @@ -50,19 +50,22 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-SPI.v" (library work) Verilog syntax check successful! + +Compiler output is up to date. No re-compile necessary + Selecting top level module RAM2GS @N: CG364 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work. Running optimization stage 1 on RAM2GS ....... -Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB) +Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 100MB) Running optimization stage 2 on RAM2GS ....... -Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 100MB) +Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB) -At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 96MB peak: 97MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Sep 21 05:38:19 2023 +# Sat Jan 6 06:25:00 2024 ###########################################################] ###########################################################[ @@ -89,7 +92,7 @@ At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Sep 21 05:38:19 2023 +# Sat Jan 6 06:25:00 2024 ###########################################################] @@ -104,7 +107,7 @@ At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Sep 21 05:38:19 2023 +# Sat Jan 6 06:25:00 2024 ###########################################################] ###########################################################[ @@ -125,18 +128,17 @@ Implementation : impl1 Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ @N|Running in 64-bit mode +File \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Sep 21 05:38:21 2023 +# Sat Jan 6 06:25:01 2024 ###########################################################] -Premap Report - -# Thu Sep 21 05:38:21 2023 +# Sat Jan 6 06:25:02 2024 Copyright (C) 1994-2021 Synopsys, Inc. @@ -170,13 +172,13 @@ See clock summary report "\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_ Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) -Start loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB) +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB) -Finished loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 151MB) +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 151MB) @N: FX493 |Applying initial value "0" on instance InitReady. @W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. @@ -186,7 +188,6 @@ Finished loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h @N: FX493 |Applying initial value "0" on instance CmdLEDEN. @N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN. @N: FX493 |Applying initial value "1" on instance nRCS. -@N: FX493 |Applying initial value "0" on instance LEDEN. @N: FX493 |Applying initial value "0" on instance n8MEGEN. @N: FX493 |Applying initial value "1" on instance nRRAS. @N: FX493 |Applying initial value "0" on instance CmdUFMCLK. @@ -202,20 +203,20 @@ Finished loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h @N: FX493 |Applying initial value "0" on instance CmdEnable. @N: FX493 |Applying initial value "1" on instance nRWE. -Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) +Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) -Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) +Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) -Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 181MB peak: 181MB) +Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) -Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 181MB peak: 181MB) +Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) @N: FX1184 |Applying syn_allowed_resources blockrams=0 on top level netlist RAM2GS -Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 181MB peak: 181MB) +Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) @@ -282,25 +283,23 @@ Clock Tree ID Driving Element Drive Element Type Fanout Sample I @N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. -Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB) +Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB) -Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB) +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB) -Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB) +Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB) Pre-mapping successful! -At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 98MB peak: 184MB) +At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 184MB) -Process took 0h:00m:02s realtime, 0h:00m:01s cputime -# Thu Sep 21 05:38:23 2023 +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Sat Jan 6 06:25:03 2024 ###########################################################] -Map & Optimize Report - -# Thu Sep 21 05:38:24 2023 +# Sat Jan 6 06:25:03 2024 Copyright (C) 1994-2021 Synopsys, Inc. @@ -319,29 +318,29 @@ Implementation : impl1 Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @ -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB) +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB) @N: MF916 |Option synthesis_strategy=base is enabled. @N: MF248 |Running in 64-bit mode. @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 140MB) +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB) -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 140MB) +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB) -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB) +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB) -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 147MB) +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB) -Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 179MB peak: 179MB) +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 178MB peak: 178MB) -Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) +Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB) @N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":147:4:147:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] @N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":134:4:134:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] @@ -354,7 +353,7 @@ Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00 Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 184MB peak: 184MB) -Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB) +Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 185MB peak: 185MB) Available hyper_sources - for debug and ip models @@ -367,10 +366,10 @@ Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CP Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 187MB) -Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 187MB) +Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB) -Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 188MB) +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB) Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB) @@ -380,51 +379,48 @@ Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:0 Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ - 1 0h:00m:01s -3.26ns 127 / 89 - 2 0h:00m:01s -3.23ns 123 / 89 - 3 0h:00m:01s -3.23ns 123 / 89 - 4 0h:00m:01s -3.23ns 123 / 89 - 5 0h:00m:01s -3.23ns 124 / 89 - 6 0h:00m:01s -3.23ns 124 / 89 -@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 7 loads 1 time to improve timing. -@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing. -@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":147:4:147:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 15 loads 1 time to improve timing. + 1 0h:00m:01s -4.01ns 133 / 89 + 2 0h:00m:01s -3.96ns 131 / 89 +@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 8 loads 1 time to improve timing. +@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 7 loads 1 time to improve timing. +@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":147:4:147:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 19 loads 1 time to improve timing. Timing driven replication report Added 3 Registers via timing driven replication Added 1 LUTs via timing driven replication - 7 0h:00m:02s -2.99ns 128 / 92 + 3 0h:00m:02s -3.08ns 143 / 92 + 4 0h:00m:02s -3.08ns 141 / 92 - 8 0h:00m:02s -2.99ns 127 / 92 - 9 0h:00m:02s -3.09ns 127 / 92 - 10 0h:00m:02s -3.19ns 127 / 92 - 11 0h:00m:02s -3.19ns 127 / 92 - 12 0h:00m:02s -3.19ns 127 / 92 + 5 0h:00m:02s -3.08ns 140 / 92 + 6 0h:00m:02s -3.19ns 140 / 92 + 7 0h:00m:02s -3.19ns 140 / 92 + 8 0h:00m:02s -3.19ns 140 / 92 + 9 0h:00m:02s -3.19ns 140 / 92 -Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 190MB) +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 191MB) -Finished restoring hierarchy (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 190MB) +Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 191MB) -Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 154MB peak: 191MB) +Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 155MB peak: 192MB) Writing Analyst data base \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_m.srm -Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 191MB peak: 191MB) +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 192MB peak: 192MB) Writing EDIF Netlist and constraint files @N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.edi @N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF -Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 196MB peak: 196MB) +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 197MB peak: 197MB) -Finished Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 196MB peak: 196MB) +Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 197MB peak: 197MB) -Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 194MB peak: 196MB) +Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 195MB peak: 197MB) @N: MT615 |Found clock RCLK with period 16.00ns @N: MT615 |Found clock PHI2 with period 350.00ns @@ -433,7 +429,7 @@ Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:0 ##### START OF TIMING REPORT #####[ -# Timing report written on Thu Sep 21 05:38:29 2023 +# Timing report written on Sat Jan 6 06:25:08 2024 # @@ -466,8 +462,8 @@ nCRAS 2.9 MHz 0.6 MHz 350.000 1613.150 -3.60 Estimated period and frequency reported as NA means no slack depends directly on the clock waveform -@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. @W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small. +@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. @W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. @W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small. @W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small. @@ -481,10 +477,10 @@ Clocks | rise to rise | fall to fall | rise to --------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack --------------------------------------------------------------------------------------------------------------- -RCLK RCLK | 16.000 7.560 | No paths - | No paths - | No paths - +RCLK RCLK | 16.000 7.464 | No paths - | No paths - | No paths - RCLK PHI2 | 2.000 -1.216 | No paths - | 1.000 -2.312 | No paths - PHI2 RCLK | No paths - | No paths - | No paths - | 1.000 -3.705 -PHI2 PHI2 | No paths - | 350.000 343.998 | 175.000 166.500 | 175.000 171.784 +PHI2 PHI2 | No paths - | 350.000 344.094 | 175.000 165.215 | 175.000 171.784 nCRAS RCLK | No paths - | No paths - | No paths - | 1.000 -3.609 =============================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. @@ -518,10 +514,10 @@ CmdUFMCS PHI2 FD1P3AX Q CmdUFMCS 1.348 CmdUFMSDI PHI2 FD1P3AX Q CmdUFMSDI 1.348 -3.297 CmdLEDEN PHI2 FD1P3AX Q CmdLEDEN 1.456 -2.216 Cmdn8MEGEN PHI2 FD1P3AX Q Cmdn8MEGEN 1.456 -2.216 -Bank[2] PHI2 FD1S3AX Q Bank[2] 1.348 166.500 -Bank[3] PHI2 FD1S3AX Q Bank[3] 1.348 166.500 -Bank[4] PHI2 FD1S3AX Q Bank[4] 1.348 166.500 -Bank[5] PHI2 FD1S3AX Q Bank[5] 1.348 166.500 +Bank[0] PHI2 FD1S3AX Q Bank[0] 1.348 165.215 +Bank[1] PHI2 FD1S3AX Q Bank[1] 1.348 165.215 +Bank[2] PHI2 FD1S3AX Q Bank[2] 1.348 165.215 +Bank[3] PHI2 FD1S3AX Q Bank[3] 1.348 165.215 ======================================================================================= @@ -535,13 +531,13 @@ Instance Reference Type Pin Net Time UFMCLK PHI2 FD1S3AX D UFMCLK_RNO -0.003 -3.705 UFMSDI PHI2 FD1S3AX D UFMSDI_RNO -0.003 -3.705 nUFMCS PHI2 FD1S3AY D nUFMCS_s_0_N_5_i -0.003 -3.705 -LEDEN PHI2 FD1P3AX SP N_33 0.806 -2.800 -n8MEGEN PHI2 FD1P3AX SP N_31 0.806 -2.800 -LEDEN PHI2 FD1P3AX D N_70 -0.003 -2.216 -n8MEGEN PHI2 FD1P3AX D N_69 -0.003 -2.216 -CmdSubmitted PHI2 FD1S3AX D N_460_0 173.997 166.500 -ADSubmitted PHI2 FD1S3AX D ADSubmitted_r 173.997 167.797 -C1Submitted PHI2 FD1S3AX D C1Submitted_RNO 173.997 167.797 +LEDEN PHI2 FD1P3AX SP N_26 0.806 -2.800 +n8MEGEN PHI2 FD1P3AX SP N_24 0.806 -2.800 +LEDEN PHI2 FD1P3AX D N_49 -0.003 -2.216 +n8MEGEN PHI2 FD1P3AX D N_48 -0.003 -2.216 +CmdEnable PHI2 FD1S3AX D CmdEnable_s 173.997 165.215 +CmdSubmitted PHI2 FD1S3AX D N_428_0 173.997 165.311 +ADSubmitted PHI2 FD1S3AX D ADSubmitted_r 173.997 166.404 ============================================================================================ @@ -573,7 +569,7 @@ CmdSubmitted FD1S3AX Q Out 1.552 1.552 r - CmdSubmitted Net - - - - 3 PHI2r3_RNITCN41 ORCALUT4 A In 0.000 1.552 r - PHI2r3_RNITCN41 ORCALUT4 Z Out 1.393 2.945 r - -N_139_i Net - - - - 3 +N_137_i Net - - - - 3 UFMCLK_RNO ORCALUT4 A In 0.000 2.945 r - UFMCLK_RNO ORCALUT4 Z Out 0.757 3.702 r - UFMCLK_RNO Net - - - - 1 @@ -604,7 +600,7 @@ CmdSubmitted FD1S3AX Q Out 1.552 1.552 r - CmdSubmitted Net - - - - 3 PHI2r3_RNITCN41 ORCALUT4 A In 0.000 1.552 r - PHI2r3_RNITCN41 ORCALUT4 Z Out 1.393 2.945 r - -N_139_i Net - - - - 3 +N_137_i Net - - - - 3 nUFMCS_s_0_N_5_i ORCALUT4 A In 0.000 2.945 r - nUFMCS_s_0_N_5_i ORCALUT4 Z Out 0.757 3.702 r - nUFMCS_s_0_N_5_i Net - - - - 1 @@ -635,7 +631,7 @@ CmdSubmitted FD1S3AX Q Out 1.552 1.552 r - CmdSubmitted Net - - - - 3 PHI2r3_RNITCN41 ORCALUT4 A In 0.000 1.552 r - PHI2r3_RNITCN41 ORCALUT4 Z Out 1.393 2.945 r - -N_139_i Net - - - - 3 +N_137_i Net - - - - 3 UFMSDI_RNO ORCALUT4 A In 0.000 2.945 r - UFMSDI_RNO ORCALUT4 Z Out 0.757 3.702 r - UFMSDI_RNO Net - - - - 1 @@ -654,21 +650,21 @@ Detailed Report for Clock: RCLK Starting Points with Worst Slack ******************************** - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------ -LEDEN RCLK FD1P3AX Q LEDEN 1.552 -2.312 -n8MEGEN RCLK FD1P3AX Q n8MEGEN 1.456 -2.216 -FS[13] RCLK FD1S3AX Q FS[13] 1.552 7.560 -FS[14] RCLK FD1S3AX Q FS[14] 1.552 7.560 -FS[15] RCLK FD1S3AX Q FS[15] 1.552 7.560 -FS[17] RCLK FD1S3AX Q FS[17] 1.552 7.560 -S[1] RCLK FD1S3IX Q S[1] 1.768 8.533 -S[0] RCLK FD1S3IX Q CO0 1.756 8.545 -FS[16] RCLK FD1S3AX Q FS[16] 1.612 8.689 -FS[12] RCLK FD1S3AX Q FS[12] 1.552 8.749 -============================================================================= + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------- +LEDEN RCLK FD1P3AX Q LEDEN 1.552 -2.312 +n8MEGEN RCLK FD1P3AX Q n8MEGEN 1.456 -2.216 +FS[12] RCLK FD1S3AX Q FS[12] 1.552 7.464 +FS[14] RCLK FD1S3AX Q FS[14] 1.552 7.464 +FS[15] RCLK FD1S3AX Q FS[15] 1.552 7.464 +FS[17] RCLK FD1S3AX Q FS[17] 1.552 7.464 +InitReady RCLK FD1S3AX Q InitReady 1.792 8.569 +S[1] RCLK FD1S3IX Q S[1] 1.792 8.569 +S[0] RCLK FD1S3IX Q CO0 1.780 8.581 +FS[13] RCLK FD1S3AX Q FS[13] 1.612 8.593 +================================================================================ Ending Points with Worst Slack @@ -678,16 +674,16 @@ Ending Points with Worst Slack Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------- -CmdLEDEN RCLK FD1P3AX D N_21_i -0.003 -2.312 +CmdLEDEN RCLK FD1P3AX D N_14_i -0.003 -2.312 XOR8MEG RCLK FD1P3AX D XOR8MEG_3 -0.003 -2.312 -Cmdn8MEGEN RCLK FD1P3AX D N_19_i -0.003 -2.216 +Cmdn8MEGEN RCLK FD1P3AX D N_12_i -0.003 -2.216 RA11 RCLK FD1S3IX D RA11_2 0.997 -1.216 -UFMSDI RCLK FD1S3AX D UFMSDI_RNO 14.997 7.560 +UFMSDI RCLK FD1S3AX D UFMSDI_RNO 14.997 7.464 UFMCLK RCLK FD1S3AX D UFMCLK_RNO 14.997 7.668 -LEDEN RCLK FD1P3AX SP N_33 15.806 8.261 -n8MEGEN RCLK FD1P3AX SP N_31 15.806 8.261 -nRCS RCLK FD1S3AY D N_28_i 14.997 8.533 +nRCAS RCLK FD1S3AY D N_46_i 14.997 8.569 nUFMCS RCLK FD1S3AY D nUFMCS_s_0_N_5_i 14.997 8.653 +nRCS RCLK FD1S3AY D N_143_i 14.997 8.881 +LEDEN RCLK FD1P3AX SP N_26 15.806 9.463 ========================================================================================= @@ -717,9 +713,9 @@ Name Type Name Dir Delay Time Fan Out(s --------------------------------------------------------------------------------- LEDEN FD1P3AX Q Out 1.552 1.552 r - LEDEN Net - - - - 3 -CmdLEDEN_RNO ORCALUT4 A In 0.000 1.552 r - +CmdLEDEN_RNO ORCALUT4 B In 0.000 1.552 r - CmdLEDEN_RNO ORCALUT4 Z Out 0.757 2.309 r - -N_21_i Net - - - - 1 +N_14_i Net - - - - 1 CmdLEDEN FD1P3AX D In 0.000 2.309 r - ================================================================================= @@ -740,16 +736,16 @@ Path information for path number 2: The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK The end point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------- -LEDEN FD1P3AX Q Out 1.552 1.552 r - -LEDEN Net - - - - 3 -XOR8MEG_3_u_0_a3_3 ORCALUT4 B In 0.000 1.552 r - -XOR8MEG_3_u_0_a3_3 ORCALUT4 Z Out 0.757 2.309 f - -XOR8MEG_3 Net - - - - 1 -XOR8MEG FD1P3AX D In 0.000 2.309 f - -===================================================================================== +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------------- +LEDEN FD1P3AX Q Out 1.552 1.552 r - +LEDEN Net - - - - 3 +XOR8MEG_3_u_0_a3_0_2 ORCALUT4 B In 0.000 1.552 r - +XOR8MEG_3_u_0_a3_0_2 ORCALUT4 Z Out 0.757 2.309 f - +XOR8MEG_3 Net - - - - 1 +XOR8MEG FD1P3AX D In 0.000 2.309 f - +======================================================================================= Path information for path number 3: @@ -775,7 +771,7 @@ n8MEGEN FD1P3AX Q Out 1.456 1.456 r - n8MEGEN Net - - - - 2 Cmdn8MEGEN_RNO ORCALUT4 C In 0.000 1.456 r - Cmdn8MEGEN_RNO ORCALUT4 Z Out 0.757 2.213 r - -N_19_i Net - - - - 1 +N_12_i Net - - - - 1 Cmdn8MEGEN FD1P3AX D In 0.000 2.213 r - ================================================================================= @@ -795,10 +791,10 @@ Starting Points with Worst Slack Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------- -CBR nCRAS FD1S3AX Q CBR 1.660 -3.609 -CBR_fast nCRAS FD1S3AX Q CBR_fast 1.456 -3.513 +CBR_fast nCRAS FD1S3AX Q CBR_fast 1.552 -3.609 +CBR nCRAS FD1S3AX Q CBR 1.612 -3.561 FWEr nCRAS FD1S3AX Q FWEr 1.552 -3.501 -FWEr_fast nCRAS FD1S3AX Q FWEr_fast 1.456 -3.405 +FWEr_fast nCRAS FD1S3AX Q FWEr_fast 1.552 -3.501 ================================================================================ @@ -809,11 +805,11 @@ Ending Points with Worst Slack Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------- -nRWE nCRAS FD1S3AY D N_39_i -0.003 -3.609 -nRowColSel nCRAS FD1S3IX D nRowColSel_0_0 -0.003 -3.609 -nRCAS nCRAS FD1S3AY D N_37_i -0.003 -3.513 -RCKEEN nCRAS FD1S3AX D RCKEEN_8 -0.003 -3.405 -nRCS nCRAS FD1S3AY D N_28_i -0.003 -3.405 +nRCAS nCRAS FD1S3AY D N_46_i -0.003 -3.609 +nRWE nCRAS FD1S3AY D N_144_i -0.003 -3.609 +nRowColSel nCRAS FD1S3IX D nRowColSel_0_0 -0.003 -3.561 +RCKEEN nCRAS FD1S3AX D RCKEEN_8 -0.003 -3.501 +nRCS nCRAS FD1S3AY D N_143_i -0.003 -3.501 ======================================================================================= @@ -833,24 +829,24 @@ Path information for path number 1: = Slack (non-critical) : -3.609 Number of logic level(s): 2 - Starting point: CBR / Q - Ending point: nRWE / D + Starting point: CBR_fast / Q + Ending point: nRCAS / D The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------- -CBR FD1S3AX Q Out 1.660 1.660 r - -CBR Net - - - - 5 -nRWE_RNO_0 ORCALUT4 A In 0.000 1.660 r - -nRWE_RNO_0 ORCALUT4 Z Out 1.189 2.849 f - -G_17_1 Net - - - - 1 -nRWE_RNO ORCALUT4 B In 0.000 2.849 f - -nRWE_RNO ORCALUT4 Z Out 0.757 3.606 r - -N_39_i Net - - - - 1 -nRWE FD1S3AY D In 0.000 3.606 r - -================================================================================= +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +---------------------------------------------------------------------------------------- +CBR_fast FD1S3AX Q Out 1.552 1.552 r - +CBR_fast Net - - - - 3 +nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 A In 0.000 1.552 r - +nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 Z Out 1.297 2.849 r - +nRCAS_0_sqmuxa_1 Net - - - - 2 +nRCAS_RNO ORCALUT4 C In 0.000 2.849 r - +nRCAS_RNO ORCALUT4 Z Out 0.757 3.606 f - +N_46_i Net - - - - 1 +nRCAS FD1S3AY D In 0.000 3.606 f - +======================================================================================== Path information for path number 2: @@ -864,24 +860,24 @@ Path information for path number 2: = Slack (non-critical) : -3.609 Number of logic level(s): 2 - Starting point: CBR / Q - Ending point: nRowColSel / D + Starting point: CBR_fast / Q + Ending point: nRWE / D The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------- -CBR FD1S3AX Q Out 1.660 1.660 r - -CBR Net - - - - 5 -nRowColSel_0_0_a3_0 ORCALUT4 B In 0.000 1.660 r - -nRowColSel_0_0_a3_0 ORCALUT4 Z Out 1.189 2.849 f - -N_179 Net - - - - 1 -nRowColSel_0_0 ORCALUT4 B In 0.000 2.849 f - -nRowColSel_0_0 ORCALUT4 Z Out 0.757 3.606 f - -nRowColSel_0_0 Net - - - - 1 -nRowColSel FD1S3IX D In 0.000 3.606 f - -====================================================================================== +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +---------------------------------------------------------------------------------------- +CBR_fast FD1S3AX Q Out 1.552 1.552 r - +CBR_fast Net - - - - 3 +nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 A In 0.000 1.552 r - +nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 Z Out 1.297 2.849 r - +nRCAS_0_sqmuxa_1 Net - - - - 2 +nRWE_RNO ORCALUT4 C In 0.000 2.849 r - +nRWE_RNO ORCALUT4 Z Out 0.757 3.606 r - +N_144_i Net - - - - 1 +nRWE FD1S3AY D In 0.000 3.606 r - +======================================================================================== Path information for path number 3: @@ -890,29 +886,29 @@ Path information for path number 3: + Clock delay at ending point: 0.000 (ideal) = Required time: -0.003 - - Propagation time: 3.510 + - Propagation time: 3.558 - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : -3.513 + = Slack (non-critical) : -3.561 Number of logic level(s): 2 - Starting point: CBR_fast / Q + Starting point: CBR / Q Ending point: nRCAS / D The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------- -CBR_fast FD1S3AX Q Out 1.456 1.456 r - -CBR_fast Net - - - - 2 -nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 A In 0.000 1.456 r - -nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 Z Out 1.297 2.753 r - -nRCAS_0_sqmuxa_1 Net - - - - 2 -nRCAS_RNO ORCALUT4 B In 0.000 2.753 r - -nRCAS_RNO ORCALUT4 Z Out 0.757 3.510 f - -N_37_i Net - - - - 1 -nRCAS FD1S3AY D In 0.000 3.510 f - -======================================================================================== +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------- +CBR FD1S3AX Q Out 1.612 1.612 r - +CBR Net - - - - 4 +nRCAS_RNO_1 ORCALUT4 A In 0.000 1.612 r - +nRCAS_RNO_1 ORCALUT4 Z Out 1.189 2.801 f - +G_1_1 Net - - - - 1 +nRCAS_RNO ORCALUT4 B In 0.000 2.801 f - +nRCAS_RNO ORCALUT4 Z Out 0.757 3.558 r - +N_46_i Net - - - - 1 +nRCAS FD1S3AY D In 0.000 3.558 r - +================================================================================= @@ -920,10 +916,10 @@ nRCAS FD1S3AY D In 0.000 3.510 f - Timing exceptions that could not be applied -Finished final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 195MB peak: 196MB) +Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 196MB peak: 197MB) -Finished timing report (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 195MB peak: 196MB) +Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 196MB peak: 197MB) --------------------------------------- Resource Usage Report @@ -944,18 +940,18 @@ FD1S3IX: 14 FD1S3JX: 3 GSR: 1 IB: 26 -INV: 8 +INV: 7 OB: 33 -ORCALUT4: 119 -PFUMX: 2 +ORCALUT4: 133 +PFUMX: 1 PUR: 1 VHI: 1 VLO: 1 Mapper successful! -At Mapper Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 78MB peak: 196MB) +At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 78MB peak: 197MB) -Process took 0h:00m:05s realtime, 0h:00m:04s cputime -# Thu Sep 21 05:38:29 2023 +Process took 0h:00m:04s realtime, 0h:00m:04s cputime +# Sat Jan 6 06:25:08 2024 ###########################################################] diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.tw1 b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.tw1 index f797186..8e5647c 100644 --- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.tw1 +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.tw1 @@ -13,7 +13,7 @@ Setup and Hold Report -------------------------------------------------------------------------------- Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 -Thu Sep 21 05:38:32 2023 +Sat Jan 06 06:25:10 2024 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -38,46 +38,48 @@ BLOCK RESETPATHS ================================================================================ Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ; - 129 items scored, 0 timing errors detected. + 168 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- -Passed: The following path meets requirements by 162.619ns (weighted slack = 325.238ns) +Passed: The following path meets requirements by 160.807ns (weighted slack = 321.614ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank[2] (from PHI2_c +) - Destination: FF Data in CmdSubmitted (to PHI2_c -) + Source: FF Q Bank[6] (from PHI2_c +) + Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 9.621ns (25.1% logic, 74.9% route), 6 logic levels. + Delay: 11.433ns (24.4% logic, 75.6% route), 7 logic levels. Constraint Details: - 9.621ns physical path delay SLICE_71 to SLICE_22 meets + 11.433ns physical path delay SLICE_75 to SLICE_20 meets 172.414ns delay constraint less - 0.174ns DIN_SET requirement (totaling 172.240ns) by 162.619ns + 0.174ns DIN_SET requirement (totaling 172.240ns) by 160.807ns Physical Path Details: - Data path SLICE_71 to SLICE_22: + Data path SLICE_75 to SLICE_20: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 SLICE_71.CLK to SLICE_71.Q0 SLICE_71 (from PHI2_c) -ROUTE 1 e 1.441 SLICE_71.Q0 to SLICE_56.A1 Bank[2] -CTOF_DEL --- 0.371 SLICE_56.A1 to SLICE_56.F1 SLICE_56 -ROUTE 1 e 1.441 SLICE_56.F1 to SLICE_70.D1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 SLICE_70.D1 to SLICE_70.F1 SLICE_70 -ROUTE 6 e 1.441 SLICE_70.F1 to SLICE_67.D0 N_147 -CTOF_DEL --- 0.371 SLICE_67.D0 to SLICE_67.F0 SLICE_67 -ROUTE 5 e 1.441 SLICE_67.F0 to SLICE_82.A0 XOR8MEG18 -CTOF_DEL --- 0.371 SLICE_82.A0 to SLICE_82.F0 SLICE_82 -ROUTE 1 e 1.441 SLICE_82.F0 to SLICE_22.A0 CmdSubmitted_1_sqmuxa -CTOF_DEL --- 0.371 SLICE_22.A0 to SLICE_22.F0 SLICE_22 -ROUTE 1 e 0.001 SLICE_22.F0 to SLICE_22.DI0 N_460_0 (to PHI2_c) +REG_DEL --- 0.560 SLICE_75.CLK to SLICE_75.Q0 SLICE_75 (from PHI2_c) +ROUTE 1 e 1.441 SLICE_75.Q0 to SLICE_77.C1 Bank[6] +CTOF_DEL --- 0.371 SLICE_77.C1 to SLICE_77.F1 SLICE_77 +ROUTE 2 e 1.441 SLICE_77.F1 to SLICE_79.D0 un1_Bank_1_5 +CTOF_DEL --- 0.371 SLICE_79.D0 to SLICE_79.F0 SLICE_79 +ROUTE 2 e 1.441 SLICE_79.F0 to SLICE_76.B0 C1WR_7 +CTOF_DEL --- 0.371 SLICE_76.B0 to SLICE_76.F0 SLICE_76 +ROUTE 5 e 1.441 SLICE_76.F0 to SLICE_70.B0 C1WR +CTOF_DEL --- 0.371 SLICE_70.B0 to SLICE_70.F0 SLICE_70 +ROUTE 1 e 1.441 SLICE_70.F0 to SLICE_14.C1 N_121 +CTOF_DEL --- 0.371 SLICE_14.C1 to SLICE_14.F1 SLICE_14 +ROUTE 1 e 1.441 SLICE_14.F1 to SLICE_20.C0 un1_CmdEnable20_i +CTOF_DEL --- 0.371 SLICE_20.C0 to SLICE_20.F0 SLICE_20 +ROUTE 1 e 0.001 SLICE_20.F0 to SLICE_20.DI0 CmdEnable_s (to PHI2_c) -------- - 9.621 (25.1% logic, 74.9% route), 6 logic levels. + 11.433 (24.4% logic, 75.6% route), 7 logic levels. -Report: 51.046MHz is the maximum frequency for this preference. +Report: 43.077MHz is the maximum frequency for this preference. ================================================================================ @@ -118,46 +120,46 @@ Report: 400.000MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; - 388 items scored, 0 timing errors detected. + 392 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- -Passed: The following path meets requirements by 4.695ns +Passed: The following path meets requirements by 6.198ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[17] (from RCLK_c +) - Destination: FF Data in LEDEN (to RCLK_c +) + Destination: FF Data in UFMSDI (to RCLK_c +) - Delay: 11.061ns (21.8% logic, 78.2% route), 6 logic levels. + Delay: 9.621ns (25.1% logic, 74.9% route), 6 logic levels. Constraint Details: - 11.061ns physical path delay SLICE_1 to SLICE_33 meets + 9.621ns physical path delay SLICE_1 to SLICE_52 meets 16.000ns delay constraint less - 0.244ns CE_SET requirement (totaling 15.756ns) by 4.695ns + 0.181ns DIN_SET requirement (totaling 15.819ns) by 6.198ns Physical Path Details: - Data path SLICE_1 to SLICE_33: + Data path SLICE_1 to SLICE_52: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.560 SLICE_1.CLK to SLICE_1.Q1 SLICE_1 (from RCLK_c) -ROUTE 3 e 1.441 SLICE_1.Q1 to SLICE_81.D1 FS[17] -CTOF_DEL --- 0.371 SLICE_81.D1 to SLICE_81.F1 SLICE_81 -ROUTE 1 e 1.441 SLICE_81.F1 to SLICE_72.C1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 SLICE_72.C1 to SLICE_72.F1 SLICE_72 -ROUTE 4 e 1.441 SLICE_72.F1 to SLICE_58.C1 N_51 +ROUTE 3 e 1.441 SLICE_1.Q1 to SLICE_86.D1 FS[17] +CTOF_DEL --- 0.371 SLICE_86.D1 to SLICE_86.F1 SLICE_86 +ROUTE 1 e 1.441 SLICE_86.F1 to SLICE_69.C1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.371 SLICE_69.C1 to SLICE_69.F1 SLICE_69 +ROUTE 4 e 1.441 SLICE_69.F1 to SLICE_58.C1 N_128 CTOF_DEL --- 0.371 SLICE_58.C1 to SLICE_58.F1 SLICE_58 -ROUTE 2 e 1.441 SLICE_58.F1 to SLICE_87.D0 N_151 -CTOF_DEL --- 0.371 SLICE_87.D0 to SLICE_87.F0 SLICE_87 -ROUTE 2 e 1.441 SLICE_87.F0 to SLICE_69.C0 N_137_8 -CTOF_DEL --- 0.371 SLICE_69.C0 to SLICE_69.F0 SLICE_69 -ROUTE 1 e 1.441 SLICE_69.F0 to SLICE_33.CE N_33 (to RCLK_c) +ROUTE 3 e 1.441 SLICE_58.F1 to SLICE_55.C0 N_94 +CTOF_DEL --- 0.371 SLICE_55.C0 to SLICE_55.F0 SLICE_55 +ROUTE 1 e 1.441 SLICE_55.F0 to SLICE_52.D0 UFMSDI_r_xx_mm_1 +CTOF_DEL --- 0.371 SLICE_52.D0 to SLICE_52.F0 SLICE_52 +ROUTE 1 e 0.001 SLICE_52.F0 to SLICE_52.DI0 UFMSDI_RNO (to RCLK_c) -------- - 11.061 (21.8% logic, 78.2% route), 6 logic levels. + 9.621 (25.1% logic, 74.9% route), 6 logic levels. -Report: 88.456MHz is the maximum frequency for this preference. +Report: 102.020MHz is the maximum frequency for this preference. Report Summary -------------- @@ -165,13 +167,13 @@ Report Summary Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | -FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 51.046 MHz| 6 +FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 43.077 MHz| 7 | | | FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 400.000 MHz| 0 | | | FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 400.000 MHz| 0 | | | -FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 88.456 MHz| 6 +FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 102.020 MHz| 6 | | | ---------------------------------------------------------------------------- @@ -226,11 +228,11 @@ Timing summary (Setup): Timing errors: 0 Score: 0 Cumulative negative slack: 0 -Constraints cover 517 paths, 4 nets, and 395 connections (62.40% coverage) +Constraints cover 560 paths, 4 nets, and 424 connections (62.26% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 -Thu Sep 21 05:38:32 2023 +Sat Jan 06 06:25:10 2024 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -255,7 +257,7 @@ BLOCK RESETPATHS ================================================================================ Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ; - 129 items scored, 0 timing errors detected. + 168 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- @@ -301,7 +303,7 @@ Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ; ================================================================================ Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; - 388 items scored, 0 timing errors detected. + 392 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- @@ -316,17 +318,17 @@ Passed: The following path meets requirements by 0.342ns Constraint Details: - 0.325ns physical path delay SLICE_75 to SLICE_75 meets + 0.325ns physical path delay SLICE_74 to SLICE_74 meets -0.017ns M_HLD and 0.000ns delay constraint requirement (totaling -0.017ns) by 0.342ns Physical Path Details: - Data path SLICE_75 to SLICE_75: + Data path SLICE_74 to SLICE_74: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.126 SLICE_75.CLK to SLICE_75.Q0 SLICE_75 (from RCLK_c) -ROUTE 1 e 0.199 SLICE_75.Q0 to SLICE_75.M1 CASr (to RCLK_c) +REG_DEL --- 0.126 SLICE_74.CLK to SLICE_74.Q0 SLICE_74 (from RCLK_c) +ROUTE 1 e 0.199 SLICE_74.Q0 to SLICE_74.M1 CASr (to RCLK_c) -------- 0.325 (38.8% logic, 61.2% route), 1 logic levels. @@ -397,7 +399,7 @@ Timing summary (Hold): Timing errors: 0 Score: 0 Cumulative negative slack: 0 -Constraints cover 517 paths, 4 nets, and 395 connections (62.40% coverage) +Constraints cover 560 paths, 4 nets, and 424 connections (62.26% coverage) diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.twr b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.twr index c9692a3..cc499c6 100644 --- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.twr +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.twr @@ -13,7 +13,7 @@ Setup and Hold Report -------------------------------------------------------------------------------- Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 -Thu Sep 21 05:38:42 2023 +Sat Jan 06 06:25:20 2024 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -38,530 +38,549 @@ BLOCK RESETPATHS ================================================================================ Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ; - 129 items scored, 0 timing errors detected. + 168 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- -Passed: The following path meets requirements by 160.663ns (weighted slack = 321.326ns) +Passed: The following path meets requirements by 161.315ns (weighted slack = 322.630ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank[7] (from PHI2_c +) - Destination: FF Data in CmdSubmitted (to PHI2_c -) - - Delay: 11.577ns (20.9% logic, 79.1% route), 6 logic levels. - - Constraint Details: - - 11.577ns physical path delay SLICE_77 to SLICE_22 meets - 172.414ns delay constraint less - 0.000ns skew and - 0.174ns DIN_SET requirement (totaling 172.240ns) by 160.663ns - - Physical Path Details: - - Data path SLICE_77 to SLICE_22: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R7C2B.CLK to R7C2B.Q1 SLICE_77 (from PHI2_c) -ROUTE 1 2.505 R7C2B.Q1 to R4C9B.A1 Bank[7] -CTOF_DEL --- 0.371 R4C9B.A1 to R4C9B.F1 SLICE_56 -ROUTE 1 2.155 R4C9B.F1 to R7C2A.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R7C2A.B1 to R7C2A.F1 SLICE_70 -ROUTE 6 1.545 R7C2A.F1 to R7C5D.A0 N_147 -CTOF_DEL --- 0.371 R7C5D.A0 to R7C5D.F0 SLICE_67 -ROUTE 5 0.867 R7C5D.F0 to R7C5C.C0 XOR8MEG18 -CTOF_DEL --- 0.371 R7C5C.C0 to R7C5C.F0 SLICE_82 -ROUTE 1 2.090 R7C5C.F0 to R8C9D.D0 CmdSubmitted_1_sqmuxa -CTOF_DEL --- 0.371 R8C9D.D0 to R8C9D.F0 SLICE_22 -ROUTE 1 0.000 R8C9D.F0 to R8C9D.DI0 N_460_0 (to PHI2_c) - -------- - 11.577 (20.9% logic, 79.1% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_77: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R7C2B.CLK PHI2_c - -------- - 3.682 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_22: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R8C9D.CLK PHI2_c - -------- - 3.682 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 161.013ns (weighted slack = 322.026ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank[6] (from PHI2_c +) - Destination: FF Data in CmdSubmitted (to PHI2_c -) - - Delay: 11.227ns (21.5% logic, 78.5% route), 6 logic levels. - - Constraint Details: - - 11.227ns physical path delay SLICE_77 to SLICE_22 meets - 172.414ns delay constraint less - 0.000ns skew and - 0.174ns DIN_SET requirement (totaling 172.240ns) by 161.013ns - - Physical Path Details: - - Data path SLICE_77 to SLICE_22: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R7C2B.CLK to R7C2B.Q0 SLICE_77 (from PHI2_c) -ROUTE 1 2.155 R7C2B.Q0 to R4C9B.B1 Bank[6] -CTOF_DEL --- 0.371 R4C9B.B1 to R4C9B.F1 SLICE_56 -ROUTE 1 2.155 R4C9B.F1 to R7C2A.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R7C2A.B1 to R7C2A.F1 SLICE_70 -ROUTE 6 1.545 R7C2A.F1 to R7C5D.A0 N_147 -CTOF_DEL --- 0.371 R7C5D.A0 to R7C5D.F0 SLICE_67 -ROUTE 5 0.867 R7C5D.F0 to R7C5C.C0 XOR8MEG18 -CTOF_DEL --- 0.371 R7C5C.C0 to R7C5C.F0 SLICE_82 -ROUTE 1 2.090 R7C5C.F0 to R8C9D.D0 CmdSubmitted_1_sqmuxa -CTOF_DEL --- 0.371 R8C9D.D0 to R8C9D.F0 SLICE_22 -ROUTE 1 0.000 R8C9D.F0 to R8C9D.DI0 N_460_0 (to PHI2_c) - -------- - 11.227 (21.5% logic, 78.5% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_77: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R7C2B.CLK PHI2_c - -------- - 3.682 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_22: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R8C9D.CLK PHI2_c - -------- - 3.682 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 161.212ns (weighted slack = 322.424ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank[2] (from PHI2_c +) - Destination: FF Data in CmdSubmitted (to PHI2_c -) - - Delay: 11.028ns (21.9% logic, 78.1% route), 6 logic levels. - - Constraint Details: - - 11.028ns physical path delay SLICE_71 to SLICE_22 meets - 172.414ns delay constraint less - 0.000ns skew and - 0.174ns DIN_SET requirement (totaling 172.240ns) by 161.212ns - - Physical Path Details: - - Data path SLICE_71 to SLICE_22: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R7C4A.CLK to R7C4A.Q0 SLICE_71 (from PHI2_c) -ROUTE 1 1.956 R7C4A.Q0 to R4C9B.C1 Bank[2] -CTOF_DEL --- 0.371 R4C9B.C1 to R4C9B.F1 SLICE_56 -ROUTE 1 2.155 R4C9B.F1 to R7C2A.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R7C2A.B1 to R7C2A.F1 SLICE_70 -ROUTE 6 1.545 R7C2A.F1 to R7C5D.A0 N_147 -CTOF_DEL --- 0.371 R7C5D.A0 to R7C5D.F0 SLICE_67 -ROUTE 5 0.867 R7C5D.F0 to R7C5C.C0 XOR8MEG18 -CTOF_DEL --- 0.371 R7C5C.C0 to R7C5C.F0 SLICE_82 -ROUTE 1 2.090 R7C5C.F0 to R8C9D.D0 CmdSubmitted_1_sqmuxa -CTOF_DEL --- 0.371 R8C9D.D0 to R8C9D.F0 SLICE_22 -ROUTE 1 0.000 R8C9D.F0 to R8C9D.DI0 N_460_0 (to PHI2_c) - -------- - 11.028 (21.9% logic, 78.1% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_71: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R7C4A.CLK PHI2_c - -------- - 3.682 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_22: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R8C9D.CLK PHI2_c - -------- - 3.682 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 161.405ns (weighted slack = 322.810ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank[5] (from PHI2_c +) - Destination: FF Data in CmdSubmitted (to PHI2_c -) - - Delay: 10.835ns (22.3% logic, 77.7% route), 6 logic levels. - - Constraint Details: - - 10.835ns physical path delay SLICE_76 to SLICE_22 meets - 172.414ns delay constraint less - 0.000ns skew and - 0.174ns DIN_SET requirement (totaling 172.240ns) by 161.405ns - - Physical Path Details: - - Data path SLICE_76 to SLICE_22: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R7C4C.CLK to R7C4C.Q1 SLICE_76 (from PHI2_c) -ROUTE 1 1.763 R7C4C.Q1 to R4C9B.D1 Bank[5] -CTOF_DEL --- 0.371 R4C9B.D1 to R4C9B.F1 SLICE_56 -ROUTE 1 2.155 R4C9B.F1 to R7C2A.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R7C2A.B1 to R7C2A.F1 SLICE_70 -ROUTE 6 1.545 R7C2A.F1 to R7C5D.A0 N_147 -CTOF_DEL --- 0.371 R7C5D.A0 to R7C5D.F0 SLICE_67 -ROUTE 5 0.867 R7C5D.F0 to R7C5C.C0 XOR8MEG18 -CTOF_DEL --- 0.371 R7C5C.C0 to R7C5C.F0 SLICE_82 -ROUTE 1 2.090 R7C5C.F0 to R8C9D.D0 CmdSubmitted_1_sqmuxa -CTOF_DEL --- 0.371 R8C9D.D0 to R8C9D.F0 SLICE_22 -ROUTE 1 0.000 R8C9D.F0 to R8C9D.DI0 N_460_0 (to PHI2_c) - -------- - 10.835 (22.3% logic, 77.7% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_76: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R7C4C.CLK PHI2_c - -------- - 3.682 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_22: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R8C9D.CLK PHI2_c - -------- - 3.682 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 161.733ns (weighted slack = 323.466ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank[7] (from PHI2_c +) + Source: FF Q Bank[4] (from PHI2_c +) Destination: FF Data in CmdUFMSDI (to PHI2_c -) - Delay: 10.416ns (19.6% logic, 80.4% route), 5 logic levels. + Delay: 10.834ns (22.3% logic, 77.7% route), 6 logic levels. Constraint Details: - 10.416ns physical path delay SLICE_77 to SLICE_74 meets + 10.834ns physical path delay SLICE_93 to SLICE_88 meets 172.414ns delay constraint less 0.000ns skew and - 0.265ns CE_SET requirement (totaling 172.149ns) by 161.733ns + 0.265ns CE_SET requirement (totaling 172.149ns) by 161.315ns Physical Path Details: - Data path SLICE_77 to SLICE_74: + Data path SLICE_93 to SLICE_88: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R7C2B.CLK to R7C2B.Q1 SLICE_77 (from PHI2_c) -ROUTE 1 2.505 R7C2B.Q1 to R4C9B.A1 Bank[7] -CTOF_DEL --- 0.371 R4C9B.A1 to R4C9B.F1 SLICE_56 -ROUTE 1 2.155 R4C9B.F1 to R7C2A.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R7C2A.B1 to R7C2A.F1 SLICE_70 -ROUTE 6 1.545 R7C2A.F1 to R7C5D.A0 N_147 -CTOF_DEL --- 0.371 R7C5D.A0 to R7C5D.F0 SLICE_67 -ROUTE 5 0.528 R7C5D.F0 to R7C5D.C1 XOR8MEG18 -CTOF_DEL --- 0.371 R7C5D.C1 to R7C5D.F1 SLICE_67 -ROUTE 2 1.639 R7C5D.F1 to R8C7D.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) +REG_DEL --- 0.560 R2C4C.CLK to R2C4C.Q0 SLICE_93 (from PHI2_c) +ROUTE 1 2.104 R2C4C.Q0 to R7C5A.B0 Bank[4] +CTOF_DEL --- 0.371 R7C5A.B0 to R7C5A.F0 SLICE_100 +ROUTE 2 1.032 R7C5A.F0 to R8C5C.A0 un1_Bank_1_4 +CTOF_DEL --- 0.371 R8C5C.A0 to R8C5C.F0 SLICE_79 +ROUTE 2 1.503 R8C5C.F0 to R7C6B.A1 C1WR_7 +CTOF_DEL --- 0.371 R7C6B.A1 to R7C6B.F1 SLICE_70 +ROUTE 2 0.710 R7C6B.F1 to R9C6A.D0 CMDWR +CTOF_DEL --- 0.371 R9C6A.D0 to R9C6A.F0 SLICE_73 +ROUTE 5 1.398 R9C6A.F0 to R9C8C.C1 XOR8MEG18 +CTOF_DEL --- 0.371 R9C8C.C1 to R9C8C.F1 SLICE_85 +ROUTE 2 1.672 R9C8C.F1 to R9C7A.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) -------- - 10.416 (19.6% logic, 80.4% route), 5 logic levels. + 10.834 (22.3% logic, 77.7% route), 6 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_77: + Source Clock Path PHI2 to SLICE_93: Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R7C2B.CLK PHI2_c +ROUTE 15 3.682 39.PADDI to R2C4C.CLK PHI2_c -------- 3.682 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_74: + Destination Clock Path PHI2 to SLICE_88: Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R8C7D.CLK PHI2_c +ROUTE 15 3.682 39.PADDI to R9C7A.CLK PHI2_c -------- 3.682 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 162.083ns (weighted slack = 324.166ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank[6] (from PHI2_c +) - Destination: FF Data in CmdUFMSDI (to PHI2_c -) - - Delay: 10.066ns (20.3% logic, 79.7% route), 5 logic levels. - - Constraint Details: - - 10.066ns physical path delay SLICE_77 to SLICE_74 meets - 172.414ns delay constraint less - 0.000ns skew and - 0.265ns CE_SET requirement (totaling 172.149ns) by 162.083ns - - Physical Path Details: - - Data path SLICE_77 to SLICE_74: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R7C2B.CLK to R7C2B.Q0 SLICE_77 (from PHI2_c) -ROUTE 1 2.155 R7C2B.Q0 to R4C9B.B1 Bank[6] -CTOF_DEL --- 0.371 R4C9B.B1 to R4C9B.F1 SLICE_56 -ROUTE 1 2.155 R4C9B.F1 to R7C2A.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R7C2A.B1 to R7C2A.F1 SLICE_70 -ROUTE 6 1.545 R7C2A.F1 to R7C5D.A0 N_147 -CTOF_DEL --- 0.371 R7C5D.A0 to R7C5D.F0 SLICE_67 -ROUTE 5 0.528 R7C5D.F0 to R7C5D.C1 XOR8MEG18 -CTOF_DEL --- 0.371 R7C5D.C1 to R7C5D.F1 SLICE_67 -ROUTE 2 1.639 R7C5D.F1 to R8C7D.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) - -------- - 10.066 (20.3% logic, 79.7% route), 5 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_77: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R7C2B.CLK PHI2_c - -------- - 3.682 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_74: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R8C7D.CLK PHI2_c - -------- - 3.682 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 162.194ns (weighted slack = 324.388ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank[7] (from PHI2_c +) - Destination: FF Data in CmdUFMCS (to PHI2_c -) - FF CmdUFMCLK - - Delay: 9.955ns (20.5% logic, 79.5% route), 5 logic levels. - - Constraint Details: - - 9.955ns physical path delay SLICE_77 to SLICE_73 meets - 172.414ns delay constraint less - 0.000ns skew and - 0.265ns CE_SET requirement (totaling 172.149ns) by 162.194ns - - Physical Path Details: - - Data path SLICE_77 to SLICE_73: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R7C2B.CLK to R7C2B.Q1 SLICE_77 (from PHI2_c) -ROUTE 1 2.505 R7C2B.Q1 to R4C9B.A1 Bank[7] -CTOF_DEL --- 0.371 R4C9B.A1 to R4C9B.F1 SLICE_56 -ROUTE 1 2.155 R4C9B.F1 to R7C2A.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R7C2A.B1 to R7C2A.F1 SLICE_70 -ROUTE 6 1.545 R7C2A.F1 to R7C5D.A0 N_147 -CTOF_DEL --- 0.371 R7C5D.A0 to R7C5D.F0 SLICE_67 -ROUTE 5 0.528 R7C5D.F0 to R7C5D.C1 XOR8MEG18 -CTOF_DEL --- 0.371 R7C5D.C1 to R7C5D.F1 SLICE_67 -ROUTE 2 1.178 R7C5D.F1 to R7C8A.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) - -------- - 9.955 (20.5% logic, 79.5% route), 5 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_77: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R7C2B.CLK PHI2_c - -------- - 3.682 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_73: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R7C8A.CLK PHI2_c - -------- - 3.682 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 162.282ns (weighted slack = 324.564ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank[2] (from PHI2_c +) - Destination: FF Data in CmdUFMSDI (to PHI2_c -) - - Delay: 9.867ns (20.7% logic, 79.3% route), 5 logic levels. - - Constraint Details: - - 9.867ns physical path delay SLICE_71 to SLICE_74 meets - 172.414ns delay constraint less - 0.000ns skew and - 0.265ns CE_SET requirement (totaling 172.149ns) by 162.282ns - - Physical Path Details: - - Data path SLICE_71 to SLICE_74: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R7C4A.CLK to R7C4A.Q0 SLICE_71 (from PHI2_c) -ROUTE 1 1.956 R7C4A.Q0 to R4C9B.C1 Bank[2] -CTOF_DEL --- 0.371 R4C9B.C1 to R4C9B.F1 SLICE_56 -ROUTE 1 2.155 R4C9B.F1 to R7C2A.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R7C2A.B1 to R7C2A.F1 SLICE_70 -ROUTE 6 1.545 R7C2A.F1 to R7C5D.A0 N_147 -CTOF_DEL --- 0.371 R7C5D.A0 to R7C5D.F0 SLICE_67 -ROUTE 5 0.528 R7C5D.F0 to R7C5D.C1 XOR8MEG18 -CTOF_DEL --- 0.371 R7C5D.C1 to R7C5D.F1 SLICE_67 -ROUTE 2 1.639 R7C5D.F1 to R8C7D.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) - -------- - 9.867 (20.7% logic, 79.3% route), 5 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_71: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R7C4A.CLK PHI2_c - -------- - 3.682 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_74: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R8C7D.CLK PHI2_c - -------- - 3.682 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 162.475ns (weighted slack = 324.950ns) +Passed: The following path meets requirements by 161.760ns (weighted slack = 323.520ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Bank[5] (from PHI2_c +) Destination: FF Data in CmdUFMSDI (to PHI2_c -) - Delay: 9.674ns (21.1% logic, 78.9% route), 5 logic levels. + Delay: 10.389ns (23.2% logic, 76.8% route), 6 logic levels. Constraint Details: - 9.674ns physical path delay SLICE_76 to SLICE_74 meets + 10.389ns physical path delay SLICE_93 to SLICE_88 meets 172.414ns delay constraint less 0.000ns skew and - 0.265ns CE_SET requirement (totaling 172.149ns) by 162.475ns + 0.265ns CE_SET requirement (totaling 172.149ns) by 161.760ns Physical Path Details: - Data path SLICE_76 to SLICE_74: + Data path SLICE_93 to SLICE_88: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R7C4C.CLK to R7C4C.Q1 SLICE_76 (from PHI2_c) -ROUTE 1 1.763 R7C4C.Q1 to R4C9B.D1 Bank[5] -CTOF_DEL --- 0.371 R4C9B.D1 to R4C9B.F1 SLICE_56 -ROUTE 1 2.155 R4C9B.F1 to R7C2A.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R7C2A.B1 to R7C2A.F1 SLICE_70 -ROUTE 6 1.545 R7C2A.F1 to R7C5D.A0 N_147 -CTOF_DEL --- 0.371 R7C5D.A0 to R7C5D.F0 SLICE_67 -ROUTE 5 0.528 R7C5D.F0 to R7C5D.C1 XOR8MEG18 -CTOF_DEL --- 0.371 R7C5D.C1 to R7C5D.F1 SLICE_67 -ROUTE 2 1.639 R7C5D.F1 to R8C7D.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) +REG_DEL --- 0.560 R2C4C.CLK to R2C4C.Q1 SLICE_93 (from PHI2_c) +ROUTE 1 1.979 R2C4C.Q1 to R8C5A.A1 Bank[5] +CTOF_DEL --- 0.371 R8C5A.A1 to R8C5A.F1 SLICE_77 +ROUTE 2 0.712 R8C5A.F1 to R8C5C.B0 un1_Bank_1_5 +CTOF_DEL --- 0.371 R8C5C.B0 to R8C5C.F0 SLICE_79 +ROUTE 2 1.503 R8C5C.F0 to R7C6B.A1 C1WR_7 +CTOF_DEL --- 0.371 R7C6B.A1 to R7C6B.F1 SLICE_70 +ROUTE 2 0.710 R7C6B.F1 to R9C6A.D0 CMDWR +CTOF_DEL --- 0.371 R9C6A.D0 to R9C6A.F0 SLICE_73 +ROUTE 5 1.398 R9C6A.F0 to R9C8C.C1 XOR8MEG18 +CTOF_DEL --- 0.371 R9C8C.C1 to R9C8C.F1 SLICE_85 +ROUTE 2 1.672 R9C8C.F1 to R9C7A.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) -------- - 9.674 (21.1% logic, 78.9% route), 5 logic levels. + 10.389 (23.2% logic, 76.8% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.682 39.PADDI to R2C4C.CLK PHI2_c + -------- + 3.682 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_88: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.682 39.PADDI to R9C7A.CLK PHI2_c + -------- + 3.682 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 161.922ns (weighted slack = 323.844ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank[4] (from PHI2_c +) + Destination: FF Data in CmdEnable (to PHI2_c -) + + Delay: 10.318ns (27.0% logic, 73.0% route), 7 logic levels. + + Constraint Details: + + 10.318ns physical path delay SLICE_93 to SLICE_20 meets + 172.414ns delay constraint less + 0.000ns skew and + 0.174ns DIN_SET requirement (totaling 172.240ns) by 161.922ns + + Physical Path Details: + + Data path SLICE_93 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C4C.CLK to R2C4C.Q0 SLICE_93 (from PHI2_c) +ROUTE 1 2.104 R2C4C.Q0 to R7C5A.B0 Bank[4] +CTOF_DEL --- 0.371 R7C5A.B0 to R7C5A.F0 SLICE_100 +ROUTE 2 1.032 R7C5A.F0 to R8C5C.A0 un1_Bank_1_4 +CTOF_DEL --- 0.371 R8C5C.A0 to R8C5C.F0 SLICE_79 +ROUTE 2 0.320 R8C5C.F0 to R8C5B.D0 C1WR_7 +CTOF_DEL --- 0.371 R8C5B.D0 to R8C5B.F0 SLICE_76 +ROUTE 5 2.032 R8C5B.F0 to R7C6B.B0 C1WR +CTOF_DEL --- 0.371 R7C6B.B0 to R7C6B.F0 SLICE_70 +ROUTE 1 1.086 R7C6B.F0 to R8C6C.B1 N_121 +CTOF_DEL --- 0.371 R8C6C.B1 to R8C6C.F1 SLICE_14 +ROUTE 1 0.958 R8C6C.F1 to R8C6A.A0 un1_CmdEnable20_i +CTOF_DEL --- 0.371 R8C6A.A0 to R8C6A.F0 SLICE_20 +ROUTE 1 0.000 R8C6A.F0 to R8C6A.DI0 CmdEnable_s (to PHI2_c) + -------- + 10.318 (27.0% logic, 73.0% route), 7 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.682 39.PADDI to R2C4C.CLK PHI2_c + -------- + 3.682 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.682 39.PADDI to R8C6A.CLK PHI2_c + -------- + 3.682 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.174ns (weighted slack = 324.348ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank[3] (from PHI2_c +) + Destination: FF Data in CmdUFMSDI (to PHI2_c -) + + Delay: 9.975ns (24.2% logic, 75.8% route), 6 logic levels. + + Constraint Details: + + 9.975ns physical path delay SLICE_79 to SLICE_88 meets + 172.414ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 172.149ns) by 162.174ns + + Physical Path Details: + + Data path SLICE_79 to SLICE_88: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R8C5C.CLK to R8C5C.Q1 SLICE_79 (from PHI2_c) +ROUTE 1 1.245 R8C5C.Q1 to R7C5A.C0 Bank[3] +CTOF_DEL --- 0.371 R7C5A.C0 to R7C5A.F0 SLICE_100 +ROUTE 2 1.032 R7C5A.F0 to R8C5C.A0 un1_Bank_1_4 +CTOF_DEL --- 0.371 R8C5C.A0 to R8C5C.F0 SLICE_79 +ROUTE 2 1.503 R8C5C.F0 to R7C6B.A1 C1WR_7 +CTOF_DEL --- 0.371 R7C6B.A1 to R7C6B.F1 SLICE_70 +ROUTE 2 0.710 R7C6B.F1 to R9C6A.D0 CMDWR +CTOF_DEL --- 0.371 R9C6A.D0 to R9C6A.F0 SLICE_73 +ROUTE 5 1.398 R9C6A.F0 to R9C8C.C1 XOR8MEG18 +CTOF_DEL --- 0.371 R9C8C.C1 to R9C8C.F1 SLICE_85 +ROUTE 2 1.672 R9C8C.F1 to R9C7A.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) + -------- + 9.975 (24.2% logic, 75.8% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_79: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.682 39.PADDI to R8C5C.CLK PHI2_c + -------- + 3.682 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_88: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.682 39.PADDI to R9C7A.CLK PHI2_c + -------- + 3.682 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.258ns (weighted slack = 324.516ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank[4] (from PHI2_c +) + Destination: FF Data in CmdEnable (to PHI2_c -) + + Delay: 9.982ns (27.9% logic, 72.1% route), 7 logic levels. + + Constraint Details: + + 9.982ns physical path delay SLICE_93 to SLICE_20 meets + 172.414ns delay constraint less + 0.000ns skew and + 0.174ns DIN_SET requirement (totaling 172.240ns) by 162.258ns + + Physical Path Details: + + Data path SLICE_93 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C4C.CLK to R2C4C.Q0 SLICE_93 (from PHI2_c) +ROUTE 1 2.104 R2C4C.Q0 to R7C5A.B0 Bank[4] +CTOF_DEL --- 0.371 R7C5A.B0 to R7C5A.F0 SLICE_100 +ROUTE 2 1.032 R7C5A.F0 to R8C5C.A0 un1_Bank_1_4 +CTOF_DEL --- 0.371 R8C5C.A0 to R8C5C.F0 SLICE_79 +ROUTE 2 1.503 R8C5C.F0 to R7C6B.A1 C1WR_7 +CTOF_DEL --- 0.371 R7C6B.A1 to R7C6B.F1 SLICE_70 +ROUTE 2 0.513 R7C6B.F1 to R7C6B.C0 CMDWR +CTOF_DEL --- 0.371 R7C6B.C0 to R7C6B.F0 SLICE_70 +ROUTE 1 1.086 R7C6B.F0 to R8C6C.B1 N_121 +CTOF_DEL --- 0.371 R8C6C.B1 to R8C6C.F1 SLICE_14 +ROUTE 1 0.958 R8C6C.F1 to R8C6A.A0 un1_CmdEnable20_i +CTOF_DEL --- 0.371 R8C6A.A0 to R8C6A.F0 SLICE_20 +ROUTE 1 0.000 R8C6A.F0 to R8C6A.DI0 CmdEnable_s (to PHI2_c) + -------- + 9.982 (27.9% logic, 72.1% route), 7 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.682 39.PADDI to R2C4C.CLK PHI2_c + -------- + 3.682 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.682 39.PADDI to R8C6A.CLK PHI2_c + -------- + 3.682 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.324ns (weighted slack = 324.648ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank[4] (from PHI2_c +) + Destination: FF Data in CmdUFMCS (to PHI2_c -) + FF CmdUFMCLK + + Delay: 9.825ns (24.6% logic, 75.4% route), 6 logic levels. + + Constraint Details: + + 9.825ns physical path delay SLICE_93 to SLICE_85 meets + 172.414ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 172.149ns) by 162.324ns + + Physical Path Details: + + Data path SLICE_93 to SLICE_85: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C4C.CLK to R2C4C.Q0 SLICE_93 (from PHI2_c) +ROUTE 1 2.104 R2C4C.Q0 to R7C5A.B0 Bank[4] +CTOF_DEL --- 0.371 R7C5A.B0 to R7C5A.F0 SLICE_100 +ROUTE 2 1.032 R7C5A.F0 to R8C5C.A0 un1_Bank_1_4 +CTOF_DEL --- 0.371 R8C5C.A0 to R8C5C.F0 SLICE_79 +ROUTE 2 1.503 R8C5C.F0 to R7C6B.A1 C1WR_7 +CTOF_DEL --- 0.371 R7C6B.A1 to R7C6B.F1 SLICE_70 +ROUTE 2 0.710 R7C6B.F1 to R9C6A.D0 CMDWR +CTOF_DEL --- 0.371 R9C6A.D0 to R9C6A.F0 SLICE_73 +ROUTE 5 1.398 R9C6A.F0 to R9C8C.C1 XOR8MEG18 +CTOF_DEL --- 0.371 R9C8C.C1 to R9C8C.F1 SLICE_85 +ROUTE 2 0.663 R9C8C.F1 to R9C8C.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) + -------- + 9.825 (24.6% logic, 75.4% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.682 39.PADDI to R2C4C.CLK PHI2_c + -------- + 3.682 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_85: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.682 39.PADDI to R9C8C.CLK PHI2_c + -------- + 3.682 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.367ns (weighted slack = 324.734ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank[5] (from PHI2_c +) + Destination: FF Data in CmdEnable (to PHI2_c -) + + Delay: 9.873ns (28.2% logic, 71.8% route), 7 logic levels. + + Constraint Details: + + 9.873ns physical path delay SLICE_93 to SLICE_20 meets + 172.414ns delay constraint less + 0.000ns skew and + 0.174ns DIN_SET requirement (totaling 172.240ns) by 162.367ns + + Physical Path Details: + + Data path SLICE_93 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C4C.CLK to R2C4C.Q1 SLICE_93 (from PHI2_c) +ROUTE 1 1.979 R2C4C.Q1 to R8C5A.A1 Bank[5] +CTOF_DEL --- 0.371 R8C5A.A1 to R8C5A.F1 SLICE_77 +ROUTE 2 0.712 R8C5A.F1 to R8C5C.B0 un1_Bank_1_5 +CTOF_DEL --- 0.371 R8C5C.B0 to R8C5C.F0 SLICE_79 +ROUTE 2 0.320 R8C5C.F0 to R8C5B.D0 C1WR_7 +CTOF_DEL --- 0.371 R8C5B.D0 to R8C5B.F0 SLICE_76 +ROUTE 5 2.032 R8C5B.F0 to R7C6B.B0 C1WR +CTOF_DEL --- 0.371 R7C6B.B0 to R7C6B.F0 SLICE_70 +ROUTE 1 1.086 R7C6B.F0 to R8C6C.B1 N_121 +CTOF_DEL --- 0.371 R8C6C.B1 to R8C6C.F1 SLICE_14 +ROUTE 1 0.958 R8C6C.F1 to R8C6A.A0 un1_CmdEnable20_i +CTOF_DEL --- 0.371 R8C6A.A0 to R8C6A.F0 SLICE_20 +ROUTE 1 0.000 R8C6A.F0 to R8C6A.DI0 CmdEnable_s (to PHI2_c) + -------- + 9.873 (28.2% logic, 71.8% route), 7 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.682 39.PADDI to R2C4C.CLK PHI2_c + -------- + 3.682 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.682 39.PADDI to R8C6A.CLK PHI2_c + -------- + 3.682 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.387ns (weighted slack = 324.774ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank[0] (from PHI2_c +) + Destination: FF Data in CmdUFMSDI (to PHI2_c -) + + Delay: 9.762ns (24.7% logic, 75.3% route), 6 logic levels. + + Constraint Details: + + 9.762ns physical path delay SLICE_76 to SLICE_88 meets + 172.414ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 172.149ns) by 162.387ns + + Physical Path Details: + + Data path SLICE_76 to SLICE_88: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R8C5B.CLK to R8C5B.Q0 SLICE_76 (from PHI2_c) +ROUTE 1 1.032 R8C5B.Q0 to R7C5A.A0 Bank[0] +CTOF_DEL --- 0.371 R7C5A.A0 to R7C5A.F0 SLICE_100 +ROUTE 2 1.032 R7C5A.F0 to R8C5C.A0 un1_Bank_1_4 +CTOF_DEL --- 0.371 R8C5C.A0 to R8C5C.F0 SLICE_79 +ROUTE 2 1.503 R8C5C.F0 to R7C6B.A1 C1WR_7 +CTOF_DEL --- 0.371 R7C6B.A1 to R7C6B.F1 SLICE_70 +ROUTE 2 0.710 R7C6B.F1 to R9C6A.D0 CMDWR +CTOF_DEL --- 0.371 R9C6A.D0 to R9C6A.F0 SLICE_73 +ROUTE 5 1.398 R9C6A.F0 to R9C8C.C1 XOR8MEG18 +CTOF_DEL --- 0.371 R9C8C.C1 to R9C8C.F1 SLICE_85 +ROUTE 2 1.672 R9C8C.F1 to R9C7A.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) + -------- + 9.762 (24.7% logic, 75.3% route), 6 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_76: Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R7C4C.CLK PHI2_c +ROUTE 15 3.682 39.PADDI to R8C5B.CLK PHI2_c -------- 3.682 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_74: + Destination Clock Path PHI2 to SLICE_88: Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R8C7D.CLK PHI2_c +ROUTE 15 3.682 39.PADDI to R9C7A.CLK PHI2_c -------- 3.682 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 162.544ns (weighted slack = 325.088ns) +Passed: The following path meets requirements by 162.647ns (weighted slack = 325.294ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank[6] (from PHI2_c +) - Destination: FF Data in CmdUFMCS (to PHI2_c -) - FF CmdUFMCLK + Source: FF Q Bank[7] (from PHI2_c +) + Destination: FF Data in CmdUFMSDI (to PHI2_c -) - Delay: 9.605ns (21.3% logic, 78.7% route), 5 logic levels. + Delay: 9.502ns (25.4% logic, 74.6% route), 6 logic levels. Constraint Details: - 9.605ns physical path delay SLICE_77 to SLICE_73 meets + 9.502ns physical path delay SLICE_75 to SLICE_88 meets 172.414ns delay constraint less 0.000ns skew and - 0.265ns CE_SET requirement (totaling 172.149ns) by 162.544ns + 0.265ns CE_SET requirement (totaling 172.149ns) by 162.647ns Physical Path Details: - Data path SLICE_77 to SLICE_73: + Data path SLICE_75 to SLICE_88: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R7C2B.CLK to R7C2B.Q0 SLICE_77 (from PHI2_c) -ROUTE 1 2.155 R7C2B.Q0 to R4C9B.B1 Bank[6] -CTOF_DEL --- 0.371 R4C9B.B1 to R4C9B.F1 SLICE_56 -ROUTE 1 2.155 R4C9B.F1 to R7C2A.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R7C2A.B1 to R7C2A.F1 SLICE_70 -ROUTE 6 1.545 R7C2A.F1 to R7C5D.A0 N_147 -CTOF_DEL --- 0.371 R7C5D.A0 to R7C5D.F0 SLICE_67 -ROUTE 5 0.528 R7C5D.F0 to R7C5D.C1 XOR8MEG18 -CTOF_DEL --- 0.371 R7C5D.C1 to R7C5D.F1 SLICE_67 -ROUTE 2 1.178 R7C5D.F1 to R7C8A.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) +REG_DEL --- 0.560 R8C6D.CLK to R8C6D.Q1 SLICE_75 (from PHI2_c) +ROUTE 1 1.092 R8C6D.Q1 to R8C5A.B1 Bank[7] +CTOF_DEL --- 0.371 R8C5A.B1 to R8C5A.F1 SLICE_77 +ROUTE 2 0.712 R8C5A.F1 to R8C5C.B0 un1_Bank_1_5 +CTOF_DEL --- 0.371 R8C5C.B0 to R8C5C.F0 SLICE_79 +ROUTE 2 1.503 R8C5C.F0 to R7C6B.A1 C1WR_7 +CTOF_DEL --- 0.371 R7C6B.A1 to R7C6B.F1 SLICE_70 +ROUTE 2 0.710 R7C6B.F1 to R9C6A.D0 CMDWR +CTOF_DEL --- 0.371 R9C6A.D0 to R9C6A.F0 SLICE_73 +ROUTE 5 1.398 R9C6A.F0 to R9C8C.C1 XOR8MEG18 +CTOF_DEL --- 0.371 R9C8C.C1 to R9C8C.F1 SLICE_85 +ROUTE 2 1.672 R9C8C.F1 to R9C7A.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) -------- - 9.605 (21.3% logic, 78.7% route), 5 logic levels. + 9.502 (25.4% logic, 74.6% route), 6 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_77: + Source Clock Path PHI2 to SLICE_75: Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R7C2B.CLK PHI2_c +ROUTE 15 3.682 39.PADDI to R8C6D.CLK PHI2_c -------- 3.682 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_73: + Destination Clock Path PHI2 to SLICE_88: Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R7C8A.CLK PHI2_c +ROUTE 15 3.682 39.PADDI to R9C7A.CLK PHI2_c -------- 3.682 (0.0% logic, 100.0% route), 0 logic levels. -Report: 42.550MHz is the maximum frequency for this preference. + +Passed: The following path meets requirements by 162.703ns (weighted slack = 325.406ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank[5] (from PHI2_c +) + Destination: FF Data in CmdEnable (to PHI2_c -) + + Delay: 9.537ns (29.2% logic, 70.8% route), 7 logic levels. + + Constraint Details: + + 9.537ns physical path delay SLICE_93 to SLICE_20 meets + 172.414ns delay constraint less + 0.000ns skew and + 0.174ns DIN_SET requirement (totaling 172.240ns) by 162.703ns + + Physical Path Details: + + Data path SLICE_93 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C4C.CLK to R2C4C.Q1 SLICE_93 (from PHI2_c) +ROUTE 1 1.979 R2C4C.Q1 to R8C5A.A1 Bank[5] +CTOF_DEL --- 0.371 R8C5A.A1 to R8C5A.F1 SLICE_77 +ROUTE 2 0.712 R8C5A.F1 to R8C5C.B0 un1_Bank_1_5 +CTOF_DEL --- 0.371 R8C5C.B0 to R8C5C.F0 SLICE_79 +ROUTE 2 1.503 R8C5C.F0 to R7C6B.A1 C1WR_7 +CTOF_DEL --- 0.371 R7C6B.A1 to R7C6B.F1 SLICE_70 +ROUTE 2 0.513 R7C6B.F1 to R7C6B.C0 CMDWR +CTOF_DEL --- 0.371 R7C6B.C0 to R7C6B.F0 SLICE_70 +ROUTE 1 1.086 R7C6B.F0 to R8C6C.B1 N_121 +CTOF_DEL --- 0.371 R8C6C.B1 to R8C6C.F1 SLICE_14 +ROUTE 1 0.958 R8C6C.F1 to R8C6A.A0 un1_CmdEnable20_i +CTOF_DEL --- 0.371 R8C6A.A0 to R8C6A.F0 SLICE_20 +ROUTE 1 0.000 R8C6A.F0 to R8C6A.DI0 CmdEnable_s (to PHI2_c) + -------- + 9.537 (29.2% logic, 70.8% route), 7 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.682 39.PADDI to R2C4C.CLK PHI2_c + -------- + 3.682 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.682 39.PADDI to R8C6A.CLK PHI2_c + -------- + 3.682 (0.0% logic, 100.0% route), 0 logic levels. + +Report: 45.049MHz is the maximum frequency for this preference. ================================================================================ @@ -602,105 +621,154 @@ Report: 400.000MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; - 388 items scored, 0 timing errors detected. + 392 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- -Passed: The following path meets requirements by 7.336ns +Passed: The following path meets requirements by 7.529ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[15] (from RCLK_c +) - Destination: FF Data in n8MEGEN (to RCLK_c +) + Destination: FF Data in UFMCLK (to RCLK_c +) - Delay: 8.420ns (28.7% logic, 71.3% route), 6 logic levels. + Delay: 8.290ns (29.1% logic, 70.9% route), 6 logic levels. Constraint Details: - 8.420ns physical path delay SLICE_2 to SLICE_58 meets + 8.290ns physical path delay SLICE_2 to SLICE_51 meets 16.000ns delay constraint less 0.000ns skew and - 0.244ns CE_SET requirement (totaling 15.756ns) by 7.336ns + 0.181ns DIN_SET requirement (totaling 15.819ns) by 7.529ns Physical Path Details: - Data path SLICE_2 to SLICE_58: + Data path SLICE_2 to SLICE_51: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C5D.CLK to R8C5D.Q1 SLICE_2 (from RCLK_c) -ROUTE 3 1.571 R8C5D.Q1 to R7C6A.B1 FS[15] -CTOF_DEL --- 0.371 R7C6A.B1 to R7C6A.F1 SLICE_81 -ROUTE 1 0.626 R7C6A.F1 to R7C6D.D1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 R7C6D.D1 to R7C6D.F1 SLICE_72 -ROUTE 4 0.657 R7C6D.F1 to R7C6B.D1 N_51 -CTOF_DEL --- 0.371 R7C6B.D1 to R7C6B.F1 SLICE_58 -ROUTE 2 1.169 R7C6B.F1 to R8C7B.D0 N_151 -CTOF_DEL --- 0.371 R8C7B.D0 to R8C7B.F0 SLICE_87 -ROUTE 2 0.909 R8C7B.F0 to R8C6C.C0 N_137_8 -CTOF_DEL --- 0.371 R8C6C.C0 to R8C6C.F0 SLICE_68 -ROUTE 1 1.073 R8C6C.F0 to R7C6B.CE N_31 (to RCLK_c) +REG_DEL --- 0.560 R10C4D.CLK to R10C4D.Q1 SLICE_2 (from RCLK_c) +ROUTE 3 1.116 R10C4D.Q1 to R10C5C.B1 FS[15] +CTOF_DEL --- 0.371 R10C5C.B1 to R10C5C.F1 SLICE_86 +ROUTE 1 1.026 R10C5C.F1 to R10C6D.A1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.371 R10C6D.A1 to R10C6D.F1 SLICE_69 +ROUTE 4 1.689 R10C6D.F1 to R10C6D.B0 N_128 +CTOF_DEL --- 0.371 R10C6D.B0 to R10C6D.F0 SLICE_69 +ROUTE 1 1.547 R10C6D.F0 to R10C9C.B1 N_129 +CTOF_DEL --- 0.371 R10C9C.B1 to R10C9C.F1 SLICE_51 +ROUTE 1 0.497 R10C9C.F1 to R10C9C.C0 UFMCLK_r_i_m4_xx_mm_1 +CTOF_DEL --- 0.371 R10C9C.C0 to R10C9C.F0 SLICE_51 +ROUTE 1 0.000 R10C9C.F0 to R10C9C.DI0 UFMCLK_RNO (to RCLK_c) -------- - 8.420 (28.7% logic, 71.3% route), 6 logic levels. + 8.290 (29.1% logic, 70.9% route), 6 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_2: Name Fanout Delay (ns) Site Resource -ROUTE 32 1.425 86.PADDI to R8C5D.CLK RCLK_c +ROUTE 32 1.425 86.PADDI to R10C4D.CLK RCLK_c -------- 1.425 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_58: + Destination Clock Path RCLK to SLICE_51: Name Fanout Delay (ns) Site Resource -ROUTE 32 1.425 86.PADDI to R7C6B.CLK RCLK_c +ROUTE 32 1.425 86.PADDI to R10C9C.CLK RCLK_c -------- 1.425 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 7.342ns +Passed: The following path meets requirements by 7.597ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS[15] (from RCLK_c +) + Source: FF Q FS[12] (from RCLK_c +) + Destination: FF Data in UFMCLK (to RCLK_c +) + + Delay: 8.222ns (29.4% logic, 70.6% route), 6 logic levels. + + Constraint Details: + + 8.222ns physical path delay SLICE_3 to SLICE_51 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.181ns DIN_SET requirement (totaling 15.819ns) by 7.597ns + + Physical Path Details: + + Data path SLICE_3 to SLICE_51: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R10C4C.CLK to R10C4C.Q0 SLICE_3 (from RCLK_c) +ROUTE 3 1.048 R10C4C.Q0 to R10C5C.A1 FS[12] +CTOF_DEL --- 0.371 R10C5C.A1 to R10C5C.F1 SLICE_86 +ROUTE 1 1.026 R10C5C.F1 to R10C6D.A1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.371 R10C6D.A1 to R10C6D.F1 SLICE_69 +ROUTE 4 1.689 R10C6D.F1 to R10C6D.B0 N_128 +CTOF_DEL --- 0.371 R10C6D.B0 to R10C6D.F0 SLICE_69 +ROUTE 1 1.547 R10C6D.F0 to R10C9C.B1 N_129 +CTOF_DEL --- 0.371 R10C9C.B1 to R10C9C.F1 SLICE_51 +ROUTE 1 0.497 R10C9C.F1 to R10C9C.C0 UFMCLK_r_i_m4_xx_mm_1 +CTOF_DEL --- 0.371 R10C9C.C0 to R10C9C.F0 SLICE_51 +ROUTE 1 0.000 R10C9C.F0 to R10C9C.DI0 UFMCLK_RNO (to RCLK_c) + -------- + 8.222 (29.4% logic, 70.6% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 1.425 86.PADDI to R10C4C.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_51: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 1.425 86.PADDI to R10C9C.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 7.653ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[4] (from RCLK_c +) Destination: FF Data in LEDEN (to RCLK_c +) - Delay: 8.414ns (28.7% logic, 71.3% route), 6 logic levels. + Delay: 8.103ns (20.6% logic, 79.4% route), 4 logic levels. Constraint Details: - 8.414ns physical path delay SLICE_2 to SLICE_33 meets + 8.103ns physical path delay SLICE_7 to SLICE_33 meets 16.000ns delay constraint less 0.000ns skew and - 0.244ns CE_SET requirement (totaling 15.756ns) by 7.342ns + 0.244ns CE_SET requirement (totaling 15.756ns) by 7.653ns Physical Path Details: - Data path SLICE_2 to SLICE_33: + Data path SLICE_7 to SLICE_33: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C5D.CLK to R8C5D.Q1 SLICE_2 (from RCLK_c) -ROUTE 3 1.571 R8C5D.Q1 to R7C6A.B1 FS[15] -CTOF_DEL --- 0.371 R7C6A.B1 to R7C6A.F1 SLICE_81 -ROUTE 1 0.626 R7C6A.F1 to R7C6D.D1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 R7C6D.D1 to R7C6D.F1 SLICE_72 -ROUTE 4 0.657 R7C6D.F1 to R7C6B.D1 N_51 -CTOF_DEL --- 0.371 R7C6B.D1 to R7C6B.F1 SLICE_58 -ROUTE 2 1.169 R7C6B.F1 to R8C7B.D0 N_151 -CTOF_DEL --- 0.371 R8C7B.D0 to R8C7B.F0 SLICE_87 -ROUTE 2 0.716 R8C7B.F0 to R8C6B.D0 N_137_8 -CTOF_DEL --- 0.371 R8C6B.D0 to R8C6B.F0 SLICE_69 -ROUTE 1 1.260 R8C6B.F0 to R9C9B.CE N_33 (to RCLK_c) +REG_DEL --- 0.560 R10C3C.CLK to R10C3C.Q0 SLICE_7 (from RCLK_c) +ROUTE 3 2.172 R10C3C.Q0 to R4C9B.D1 FS[4] +CTOF_DEL --- 0.371 R4C9B.D1 to R4C9B.F1 SLICE_56 +ROUTE 2 2.098 R4C9B.F1 to R9C5A.D1 N_43 +CTOF_DEL --- 0.371 R9C5A.D1 to R9C5A.F1 SLICE_72 +ROUTE 1 0.626 R9C5A.F1 to R9C5A.D0 un1_FS_13_i_a2_1 +CTOF_DEL --- 0.371 R9C5A.D0 to R9C5A.F0 SLICE_72 +ROUTE 1 1.534 R9C5A.F0 to R9C9B.CE N_26 (to RCLK_c) -------- - 8.414 (28.7% logic, 71.3% route), 6 logic levels. + 8.103 (20.6% logic, 79.4% route), 4 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_2: + Source Clock Path RCLK to SLICE_7: Name Fanout Delay (ns) Site Resource -ROUTE 32 1.425 86.PADDI to R8C5D.CLK RCLK_c +ROUTE 32 1.425 86.PADDI to R10C3C.CLK RCLK_c -------- 1.425 (0.0% logic, 100.0% route), 0 logic levels. @@ -712,267 +780,55 @@ ROUTE 32 1.425 86.PADDI to R9C9B.CLK RCLK_c 1.425 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 7.396ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[13] (from RCLK_c +) - Destination: FF Data in n8MEGEN (to RCLK_c +) - - Delay: 8.360ns (28.9% logic, 71.1% route), 6 logic levels. - - Constraint Details: - - 8.360ns physical path delay SLICE_3 to SLICE_58 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.244ns CE_SET requirement (totaling 15.756ns) by 7.396ns - - Physical Path Details: - - Data path SLICE_3 to SLICE_58: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C5C.CLK to R8C5C.Q1 SLICE_3 (from RCLK_c) -ROUTE 3 1.511 R8C5C.Q1 to R7C6A.A1 FS[13] -CTOF_DEL --- 0.371 R7C6A.A1 to R7C6A.F1 SLICE_81 -ROUTE 1 0.626 R7C6A.F1 to R7C6D.D1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 R7C6D.D1 to R7C6D.F1 SLICE_72 -ROUTE 4 0.657 R7C6D.F1 to R7C6B.D1 N_51 -CTOF_DEL --- 0.371 R7C6B.D1 to R7C6B.F1 SLICE_58 -ROUTE 2 1.169 R7C6B.F1 to R8C7B.D0 N_151 -CTOF_DEL --- 0.371 R8C7B.D0 to R8C7B.F0 SLICE_87 -ROUTE 2 0.909 R8C7B.F0 to R8C6C.C0 N_137_8 -CTOF_DEL --- 0.371 R8C6C.C0 to R8C6C.F0 SLICE_68 -ROUTE 1 1.073 R8C6C.F0 to R7C6B.CE N_31 (to RCLK_c) - -------- - 8.360 (28.9% logic, 71.1% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_3: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 1.425 86.PADDI to R8C5C.CLK RCLK_c - -------- - 1.425 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_58: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 1.425 86.PADDI to R7C6B.CLK RCLK_c - -------- - 1.425 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 7.402ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[13] (from RCLK_c +) - Destination: FF Data in LEDEN (to RCLK_c +) - - Delay: 8.354ns (28.9% logic, 71.1% route), 6 logic levels. - - Constraint Details: - - 8.354ns physical path delay SLICE_3 to SLICE_33 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.244ns CE_SET requirement (totaling 15.756ns) by 7.402ns - - Physical Path Details: - - Data path SLICE_3 to SLICE_33: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C5C.CLK to R8C5C.Q1 SLICE_3 (from RCLK_c) -ROUTE 3 1.511 R8C5C.Q1 to R7C6A.A1 FS[13] -CTOF_DEL --- 0.371 R7C6A.A1 to R7C6A.F1 SLICE_81 -ROUTE 1 0.626 R7C6A.F1 to R7C6D.D1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 R7C6D.D1 to R7C6D.F1 SLICE_72 -ROUTE 4 0.657 R7C6D.F1 to R7C6B.D1 N_51 -CTOF_DEL --- 0.371 R7C6B.D1 to R7C6B.F1 SLICE_58 -ROUTE 2 1.169 R7C6B.F1 to R8C7B.D0 N_151 -CTOF_DEL --- 0.371 R8C7B.D0 to R8C7B.F0 SLICE_87 -ROUTE 2 0.716 R8C7B.F0 to R8C6B.D0 N_137_8 -CTOF_DEL --- 0.371 R8C6B.D0 to R8C6B.F0 SLICE_69 -ROUTE 1 1.260 R8C6B.F0 to R9C9B.CE N_33 (to RCLK_c) - -------- - 8.354 (28.9% logic, 71.1% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_3: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 1.425 86.PADDI to R8C5C.CLK RCLK_c - -------- - 1.425 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_33: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 1.425 86.PADDI to R9C9B.CLK RCLK_c - -------- - 1.425 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 7.475ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[15] (from RCLK_c +) - Destination: FF Data in UFMSDI (to RCLK_c +) - - Delay: 8.344ns (28.9% logic, 71.1% route), 6 logic levels. - - Constraint Details: - - 8.344ns physical path delay SLICE_2 to SLICE_52 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.181ns DIN_SET requirement (totaling 15.819ns) by 7.475ns - - Physical Path Details: - - Data path SLICE_2 to SLICE_52: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C5D.CLK to R8C5D.Q1 SLICE_2 (from RCLK_c) -ROUTE 3 1.571 R8C5D.Q1 to R7C6A.B1 FS[15] -CTOF_DEL --- 0.371 R7C6A.B1 to R7C6A.F1 SLICE_81 -ROUTE 1 0.626 R7C6A.F1 to R7C6D.D1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 R7C6D.D1 to R7C6D.F1 SLICE_72 -ROUTE 4 0.657 R7C6D.F1 to R7C6B.D1 N_51 -CTOF_DEL --- 0.371 R7C6B.D1 to R7C6B.F1 SLICE_58 -ROUTE 2 1.919 R7C6B.F1 to R8C7B.B1 N_151 -CTOF_DEL --- 0.371 R8C7B.B1 to R8C7B.F1 SLICE_87 -ROUTE 1 1.156 R8C7B.F1 to R9C9C.D0 UFMSDI_r_xx_mm_1 -CTOF_DEL --- 0.371 R9C9C.D0 to R9C9C.F0 SLICE_52 -ROUTE 1 0.000 R9C9C.F0 to R9C9C.DI0 UFMSDI_RNO (to RCLK_c) - -------- - 8.344 (28.9% logic, 71.1% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_2: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 1.425 86.PADDI to R8C5D.CLK RCLK_c - -------- - 1.425 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_52: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 1.425 86.PADDI to R9C9C.CLK RCLK_c - -------- - 1.425 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 7.535ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[13] (from RCLK_c +) - Destination: FF Data in UFMSDI (to RCLK_c +) - - Delay: 8.284ns (29.2% logic, 70.8% route), 6 logic levels. - - Constraint Details: - - 8.284ns physical path delay SLICE_3 to SLICE_52 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.181ns DIN_SET requirement (totaling 15.819ns) by 7.535ns - - Physical Path Details: - - Data path SLICE_3 to SLICE_52: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C5C.CLK to R8C5C.Q1 SLICE_3 (from RCLK_c) -ROUTE 3 1.511 R8C5C.Q1 to R7C6A.A1 FS[13] -CTOF_DEL --- 0.371 R7C6A.A1 to R7C6A.F1 SLICE_81 -ROUTE 1 0.626 R7C6A.F1 to R7C6D.D1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 R7C6D.D1 to R7C6D.F1 SLICE_72 -ROUTE 4 0.657 R7C6D.F1 to R7C6B.D1 N_51 -CTOF_DEL --- 0.371 R7C6B.D1 to R7C6B.F1 SLICE_58 -ROUTE 2 1.919 R7C6B.F1 to R8C7B.B1 N_151 -CTOF_DEL --- 0.371 R8C7B.B1 to R8C7B.F1 SLICE_87 -ROUTE 1 1.156 R8C7B.F1 to R9C9C.D0 UFMSDI_r_xx_mm_1 -CTOF_DEL --- 0.371 R9C9C.D0 to R9C9C.F0 SLICE_52 -ROUTE 1 0.000 R9C9C.F0 to R9C9C.DI0 UFMSDI_RNO (to RCLK_c) - -------- - 8.284 (29.2% logic, 70.8% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_3: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 1.425 86.PADDI to R8C5C.CLK RCLK_c - -------- - 1.425 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_52: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 1.425 86.PADDI to R9C9C.CLK RCLK_c - -------- - 1.425 (0.0% logic, 100.0% route), 0 logic levels. - - Passed: The following path meets requirements by 7.721ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[14] (from RCLK_c +) - Destination: FF Data in n8MEGEN (to RCLK_c +) + Destination: FF Data in UFMCLK (to RCLK_c +) - Delay: 8.035ns (30.1% logic, 69.9% route), 6 logic levels. + Delay: 8.098ns (29.8% logic, 70.2% route), 6 logic levels. Constraint Details: - 8.035ns physical path delay SLICE_2 to SLICE_58 meets + 8.098ns physical path delay SLICE_2 to SLICE_51 meets 16.000ns delay constraint less 0.000ns skew and - 0.244ns CE_SET requirement (totaling 15.756ns) by 7.721ns + 0.181ns DIN_SET requirement (totaling 15.819ns) by 7.721ns Physical Path Details: - Data path SLICE_2 to SLICE_58: + Data path SLICE_2 to SLICE_51: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C5D.CLK to R8C5D.Q0 SLICE_2 (from RCLK_c) -ROUTE 3 1.186 R8C5D.Q0 to R7C6A.D1 FS[14] -CTOF_DEL --- 0.371 R7C6A.D1 to R7C6A.F1 SLICE_81 -ROUTE 1 0.626 R7C6A.F1 to R7C6D.D1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 R7C6D.D1 to R7C6D.F1 SLICE_72 -ROUTE 4 0.657 R7C6D.F1 to R7C6B.D1 N_51 -CTOF_DEL --- 0.371 R7C6B.D1 to R7C6B.F1 SLICE_58 -ROUTE 2 1.169 R7C6B.F1 to R8C7B.D0 N_151 -CTOF_DEL --- 0.371 R8C7B.D0 to R8C7B.F0 SLICE_87 -ROUTE 2 0.909 R8C7B.F0 to R8C6C.C0 N_137_8 -CTOF_DEL --- 0.371 R8C6C.C0 to R8C6C.F0 SLICE_68 -ROUTE 1 1.073 R8C6C.F0 to R7C6B.CE N_31 (to RCLK_c) +REG_DEL --- 0.560 R10C4D.CLK to R10C4D.Q0 SLICE_2 (from RCLK_c) +ROUTE 3 0.924 R10C4D.Q0 to R10C5C.C1 FS[14] +CTOF_DEL --- 0.371 R10C5C.C1 to R10C5C.F1 SLICE_86 +ROUTE 1 1.026 R10C5C.F1 to R10C6D.A1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.371 R10C6D.A1 to R10C6D.F1 SLICE_69 +ROUTE 4 1.689 R10C6D.F1 to R10C6D.B0 N_128 +CTOF_DEL --- 0.371 R10C6D.B0 to R10C6D.F0 SLICE_69 +ROUTE 1 1.547 R10C6D.F0 to R10C9C.B1 N_129 +CTOF_DEL --- 0.371 R10C9C.B1 to R10C9C.F1 SLICE_51 +ROUTE 1 0.497 R10C9C.F1 to R10C9C.C0 UFMCLK_r_i_m4_xx_mm_1 +CTOF_DEL --- 0.371 R10C9C.C0 to R10C9C.F0 SLICE_51 +ROUTE 1 0.000 R10C9C.F0 to R10C9C.DI0 UFMCLK_RNO (to RCLK_c) -------- - 8.035 (30.1% logic, 69.9% route), 6 logic levels. + 8.098 (29.8% logic, 70.2% route), 6 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_2: Name Fanout Delay (ns) Site Resource -ROUTE 32 1.425 86.PADDI to R8C5D.CLK RCLK_c +ROUTE 32 1.425 86.PADDI to R10C4D.CLK RCLK_c -------- 1.425 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_58: + Destination Clock Path RCLK to SLICE_51: Name Fanout Delay (ns) Site Resource -ROUTE 32 1.425 86.PADDI to R7C6B.CLK RCLK_c +ROUTE 32 1.425 86.PADDI to R10C9C.CLK RCLK_c -------- 1.425 (0.0% logic, 100.0% route), 0 logic levels. @@ -981,10 +837,10 @@ Passed: The following path meets requirements by 7.727ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS[14] (from RCLK_c +) + Source: FF Q FS[15] (from RCLK_c +) Destination: FF Data in LEDEN (to RCLK_c +) - Delay: 8.029ns (30.1% logic, 69.9% route), 6 logic levels. + Delay: 8.029ns (25.5% logic, 74.5% route), 5 logic levels. Constraint Details: @@ -998,27 +854,25 @@ Passed: The following path meets requirements by 7.727ns Data path SLICE_2 to SLICE_33: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C5D.CLK to R8C5D.Q0 SLICE_2 (from RCLK_c) -ROUTE 3 1.186 R8C5D.Q0 to R7C6A.D1 FS[14] -CTOF_DEL --- 0.371 R7C6A.D1 to R7C6A.F1 SLICE_81 -ROUTE 1 0.626 R7C6A.F1 to R7C6D.D1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 R7C6D.D1 to R7C6D.F1 SLICE_72 -ROUTE 4 0.657 R7C6D.F1 to R7C6B.D1 N_51 -CTOF_DEL --- 0.371 R7C6B.D1 to R7C6B.F1 SLICE_58 -ROUTE 2 1.169 R7C6B.F1 to R8C7B.D0 N_151 -CTOF_DEL --- 0.371 R8C7B.D0 to R8C7B.F0 SLICE_87 -ROUTE 2 0.716 R8C7B.F0 to R8C6B.D0 N_137_8 -CTOF_DEL --- 0.371 R8C6B.D0 to R8C6B.F0 SLICE_69 -ROUTE 1 1.260 R8C6B.F0 to R9C9B.CE N_33 (to RCLK_c) +REG_DEL --- 0.560 R10C4D.CLK to R10C4D.Q1 SLICE_2 (from RCLK_c) +ROUTE 3 1.116 R10C4D.Q1 to R10C5C.B1 FS[15] +CTOF_DEL --- 0.371 R10C5C.B1 to R10C5C.F1 SLICE_86 +ROUTE 1 1.026 R10C5C.F1 to R10C6D.A1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.371 R10C6D.A1 to R10C6D.F1 SLICE_69 +ROUTE 4 1.201 R10C6D.F1 to R9C7B.D1 N_128 +CTOF_DEL --- 0.371 R9C7B.D1 to R9C7B.F1 SLICE_58 +ROUTE 3 1.108 R9C7B.F1 to R9C5A.B0 N_94 +CTOF_DEL --- 0.371 R9C5A.B0 to R9C5A.F0 SLICE_72 +ROUTE 1 1.534 R9C5A.F0 to R9C9B.CE N_26 (to RCLK_c) -------- - 8.029 (30.1% logic, 69.9% route), 6 logic levels. + 8.029 (25.5% logic, 74.5% route), 5 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_2: Name Fanout Delay (ns) Site Resource -ROUTE 32 1.425 86.PADDI to R8C5D.CLK RCLK_c +ROUTE 32 1.425 86.PADDI to R10C4D.CLK RCLK_c -------- 1.425 (0.0% logic, 100.0% route), 0 logic levels. @@ -1030,48 +884,148 @@ ROUTE 32 1.425 86.PADDI to R9C9B.CLK RCLK_c 1.425 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 7.860ns +Passed: The following path meets requirements by 7.795ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS[14] (from RCLK_c +) - Destination: FF Data in UFMSDI (to RCLK_c +) + Source: FF Q FS[12] (from RCLK_c +) + Destination: FF Data in LEDEN (to RCLK_c +) - Delay: 7.959ns (30.3% logic, 69.7% route), 6 logic levels. + Delay: 7.961ns (25.7% logic, 74.3% route), 5 logic levels. Constraint Details: - 7.959ns physical path delay SLICE_2 to SLICE_52 meets + 7.961ns physical path delay SLICE_3 to SLICE_33 meets 16.000ns delay constraint less 0.000ns skew and - 0.181ns DIN_SET requirement (totaling 15.819ns) by 7.860ns + 0.244ns CE_SET requirement (totaling 15.756ns) by 7.795ns + + Physical Path Details: + + Data path SLICE_3 to SLICE_33: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R10C4C.CLK to R10C4C.Q0 SLICE_3 (from RCLK_c) +ROUTE 3 1.048 R10C4C.Q0 to R10C5C.A1 FS[12] +CTOF_DEL --- 0.371 R10C5C.A1 to R10C5C.F1 SLICE_86 +ROUTE 1 1.026 R10C5C.F1 to R10C6D.A1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.371 R10C6D.A1 to R10C6D.F1 SLICE_69 +ROUTE 4 1.201 R10C6D.F1 to R9C7B.D1 N_128 +CTOF_DEL --- 0.371 R9C7B.D1 to R9C7B.F1 SLICE_58 +ROUTE 3 1.108 R9C7B.F1 to R9C5A.B0 N_94 +CTOF_DEL --- 0.371 R9C5A.B0 to R9C5A.F0 SLICE_72 +ROUTE 1 1.534 R9C5A.F0 to R9C9B.CE N_26 (to RCLK_c) + -------- + 7.961 (25.7% logic, 74.3% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 1.425 86.PADDI to R10C4C.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_33: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 1.425 86.PADDI to R9C9B.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 7.823ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[11] (from RCLK_c +) + Destination: FF Data in LEDEN (to RCLK_c +) + + Delay: 7.933ns (21.1% logic, 78.9% route), 4 logic levels. + + Constraint Details: + + 7.933ns physical path delay SLICE_4 to SLICE_33 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.244ns CE_SET requirement (totaling 15.756ns) by 7.823ns + + Physical Path Details: + + Data path SLICE_4 to SLICE_33: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R10C4B.CLK to R10C4B.Q1 SLICE_4 (from RCLK_c) +ROUTE 6 2.002 R10C4B.Q1 to R4C9B.C1 FS[11] +CTOF_DEL --- 0.371 R4C9B.C1 to R4C9B.F1 SLICE_56 +ROUTE 2 2.098 R4C9B.F1 to R9C5A.D1 N_43 +CTOF_DEL --- 0.371 R9C5A.D1 to R9C5A.F1 SLICE_72 +ROUTE 1 0.626 R9C5A.F1 to R9C5A.D0 un1_FS_13_i_a2_1 +CTOF_DEL --- 0.371 R9C5A.D0 to R9C5A.F0 SLICE_72 +ROUTE 1 1.534 R9C5A.F0 to R9C9B.CE N_26 (to RCLK_c) + -------- + 7.933 (21.1% logic, 78.9% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_4: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 1.425 86.PADDI to R10C4B.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_33: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 1.425 86.PADDI to R9C9B.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 7.864ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[15] (from RCLK_c +) + Destination: FF Data in UFMSDI (to RCLK_c +) + + Delay: 7.955ns (30.4% logic, 69.6% route), 6 logic levels. + + Constraint Details: + + 7.955ns physical path delay SLICE_2 to SLICE_52 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.181ns DIN_SET requirement (totaling 15.819ns) by 7.864ns Physical Path Details: Data path SLICE_2 to SLICE_52: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C5D.CLK to R8C5D.Q0 SLICE_2 (from RCLK_c) -ROUTE 3 1.186 R8C5D.Q0 to R7C6A.D1 FS[14] -CTOF_DEL --- 0.371 R7C6A.D1 to R7C6A.F1 SLICE_81 -ROUTE 1 0.626 R7C6A.F1 to R7C6D.D1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 R7C6D.D1 to R7C6D.F1 SLICE_72 -ROUTE 4 0.657 R7C6D.F1 to R7C6B.D1 N_51 -CTOF_DEL --- 0.371 R7C6B.D1 to R7C6B.F1 SLICE_58 -ROUTE 2 1.919 R7C6B.F1 to R8C7B.B1 N_151 -CTOF_DEL --- 0.371 R8C7B.B1 to R8C7B.F1 SLICE_87 -ROUTE 1 1.156 R8C7B.F1 to R9C9C.D0 UFMSDI_r_xx_mm_1 -CTOF_DEL --- 0.371 R9C9C.D0 to R9C9C.F0 SLICE_52 +REG_DEL --- 0.560 R10C4D.CLK to R10C4D.Q1 SLICE_2 (from RCLK_c) +ROUTE 3 1.116 R10C4D.Q1 to R10C5C.B1 FS[15] +CTOF_DEL --- 0.371 R10C5C.B1 to R10C5C.F1 SLICE_86 +ROUTE 1 1.026 R10C5C.F1 to R10C6D.A1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.371 R10C6D.A1 to R10C6D.F1 SLICE_69 +ROUTE 4 1.201 R10C6D.F1 to R9C7B.D1 N_128 +CTOF_DEL --- 0.371 R9C7B.D1 to R9C7B.F1 SLICE_58 +ROUTE 3 1.171 R9C7B.F1 to R10C9A.D0 N_94 +CTOF_DEL --- 0.371 R10C9A.D0 to R10C9A.F0 SLICE_55 +ROUTE 1 1.026 R10C9A.F0 to R9C9C.A0 UFMSDI_r_xx_mm_1 +CTOF_DEL --- 0.371 R9C9C.A0 to R9C9C.F0 SLICE_52 ROUTE 1 0.000 R9C9C.F0 to R9C9C.DI0 UFMSDI_RNO (to RCLK_c) -------- - 7.959 (30.3% logic, 69.7% route), 6 logic levels. + 7.955 (30.4% logic, 69.6% route), 6 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_2: Name Fanout Delay (ns) Site Resource -ROUTE 32 1.425 86.PADDI to R8C5D.CLK RCLK_c +ROUTE 32 1.425 86.PADDI to R10C4D.CLK RCLK_c -------- 1.425 (0.0% logic, 100.0% route), 0 logic levels. @@ -1083,59 +1037,110 @@ ROUTE 32 1.425 86.PADDI to R9C9C.CLK RCLK_c 1.425 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 7.998ns +Passed: The following path meets requirements by 7.884ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS[17] (from RCLK_c +) - Destination: FF Data in n8MEGEN (to RCLK_c +) + Source: FF Q FS[15] (from RCLK_c +) + Destination: FF Data in UFMSDI (to RCLK_c +) - Delay: 7.758ns (31.1% logic, 68.9% route), 6 logic levels. + Delay: 7.935ns (30.4% logic, 69.6% route), 6 logic levels. Constraint Details: - 7.758ns physical path delay SLICE_1 to SLICE_58 meets + 7.935ns physical path delay SLICE_2 to SLICE_52 meets 16.000ns delay constraint less 0.000ns skew and - 0.244ns CE_SET requirement (totaling 15.756ns) by 7.998ns + 0.181ns DIN_SET requirement (totaling 15.819ns) by 7.884ns Physical Path Details: - Data path SLICE_1 to SLICE_58: + Data path SLICE_2 to SLICE_52: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C6A.CLK to R8C6A.Q1 SLICE_1 (from RCLK_c) -ROUTE 3 0.909 R8C6A.Q1 to R7C6A.C1 FS[17] -CTOF_DEL --- 0.371 R7C6A.C1 to R7C6A.F1 SLICE_81 -ROUTE 1 0.626 R7C6A.F1 to R7C6D.D1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 R7C6D.D1 to R7C6D.F1 SLICE_72 -ROUTE 4 0.657 R7C6D.F1 to R7C6B.D1 N_51 -CTOF_DEL --- 0.371 R7C6B.D1 to R7C6B.F1 SLICE_58 -ROUTE 2 1.169 R7C6B.F1 to R8C7B.D0 N_151 -CTOF_DEL --- 0.371 R8C7B.D0 to R8C7B.F0 SLICE_87 -ROUTE 2 0.909 R8C7B.F0 to R8C6C.C0 N_137_8 -CTOF_DEL --- 0.371 R8C6C.C0 to R8C6C.F0 SLICE_68 -ROUTE 1 1.073 R8C6C.F0 to R7C6B.CE N_31 (to RCLK_c) +REG_DEL --- 0.560 R10C4D.CLK to R10C4D.Q1 SLICE_2 (from RCLK_c) +ROUTE 3 1.116 R10C4D.Q1 to R10C5C.B1 FS[15] +CTOF_DEL --- 0.371 R10C5C.B1 to R10C5C.F1 SLICE_86 +ROUTE 1 1.026 R10C5C.F1 to R10C6D.A1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.371 R10C6D.A1 to R10C6D.F1 SLICE_69 +ROUTE 4 0.865 R10C6D.F1 to R10C6A.C1 N_128 +CTOF_DEL --- 0.371 R10C6A.C1 to R10C6A.F1 SLICE_32 +ROUTE 1 1.487 R10C6A.F1 to R10C9A.A0 UFMSDI_ens2_i_a0 +CTOF_DEL --- 0.371 R10C9A.A0 to R10C9A.F0 SLICE_55 +ROUTE 1 1.026 R10C9A.F0 to R9C9C.A0 UFMSDI_r_xx_mm_1 +CTOF_DEL --- 0.371 R9C9C.A0 to R9C9C.F0 SLICE_52 +ROUTE 1 0.000 R9C9C.F0 to R9C9C.DI0 UFMSDI_RNO (to RCLK_c) -------- - 7.758 (31.1% logic, 68.9% route), 6 logic levels. + 7.935 (30.4% logic, 69.6% route), 6 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_1: + Source Clock Path RCLK to SLICE_2: Name Fanout Delay (ns) Site Resource -ROUTE 32 1.425 86.PADDI to R8C6A.CLK RCLK_c +ROUTE 32 1.425 86.PADDI to R10C4D.CLK RCLK_c -------- 1.425 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_58: + Destination Clock Path RCLK to SLICE_52: Name Fanout Delay (ns) Site Resource -ROUTE 32 1.425 86.PADDI to R7C6B.CLK RCLK_c +ROUTE 32 1.425 86.PADDI to R9C9C.CLK RCLK_c -------- 1.425 (0.0% logic, 100.0% route), 0 logic levels. -Report: 115.420MHz is the maximum frequency for this preference. + +Passed: The following path meets requirements by 7.919ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[14] (from RCLK_c +) + Destination: FF Data in LEDEN (to RCLK_c +) + + Delay: 7.837ns (26.1% logic, 73.9% route), 5 logic levels. + + Constraint Details: + + 7.837ns physical path delay SLICE_2 to SLICE_33 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.244ns CE_SET requirement (totaling 15.756ns) by 7.919ns + + Physical Path Details: + + Data path SLICE_2 to SLICE_33: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R10C4D.CLK to R10C4D.Q0 SLICE_2 (from RCLK_c) +ROUTE 3 0.924 R10C4D.Q0 to R10C5C.C1 FS[14] +CTOF_DEL --- 0.371 R10C5C.C1 to R10C5C.F1 SLICE_86 +ROUTE 1 1.026 R10C5C.F1 to R10C6D.A1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.371 R10C6D.A1 to R10C6D.F1 SLICE_69 +ROUTE 4 1.201 R10C6D.F1 to R9C7B.D1 N_128 +CTOF_DEL --- 0.371 R9C7B.D1 to R9C7B.F1 SLICE_58 +ROUTE 3 1.108 R9C7B.F1 to R9C5A.B0 N_94 +CTOF_DEL --- 0.371 R9C5A.B0 to R9C5A.F0 SLICE_72 +ROUTE 1 1.534 R9C5A.F0 to R9C9B.CE N_26 (to RCLK_c) + -------- + 7.837 (26.1% logic, 73.9% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_2: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 1.425 86.PADDI to R10C4D.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_33: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 1.425 86.PADDI to R9C9B.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + +Report: 118.050MHz is the maximum frequency for this preference. Report Summary -------------- @@ -1143,13 +1148,13 @@ Report Summary Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | -FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 42.550 MHz| 6 +FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 45.049 MHz| 6 | | | FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 400.000 MHz| 0 | | | FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 400.000 MHz| 0 | | | -FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 115.420 MHz| 6 +FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 118.050 MHz| 6 | | | ---------------------------------------------------------------------------- @@ -1204,11 +1209,11 @@ Timing summary (Setup): Timing errors: 0 Score: 0 Cumulative negative slack: 0 -Constraints cover 517 paths, 4 nets, and 421 connections (66.51% coverage) +Constraints cover 560 paths, 4 nets, and 450 connections (66.08% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 -Thu Sep 21 05:38:43 2023 +Sat Jan 06 06:25:20 2024 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -1233,51 +1238,51 @@ BLOCK RESETPATHS ================================================================================ Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ; - 129 items scored, 0 timing errors detected. + 168 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- -Passed: The following path meets requirements by 0.358ns +Passed: The following path meets requirements by 0.360ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q ADSubmitted (from PHI2_c -) - Destination: FF Data in ADSubmitted (to PHI2_c -) + Source: FF Q CmdEnable (from PHI2_c -) + Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 0.339ns (62.2% logic, 37.8% route), 2 logic levels. + Delay: 0.341ns (61.9% logic, 38.1% route), 2 logic levels. Constraint Details: - 0.339ns physical path delay SLICE_9 to SLICE_9 meets + 0.341ns physical path delay SLICE_20 to SLICE_20 meets -0.019ns DIN_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.358ns + 0.000ns skew requirement (totaling -0.019ns) by 0.360ns Physical Path Details: - Data path SLICE_9 to SLICE_9: + Data path SLICE_20 to SLICE_20: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R6C2A.CLK to R6C2A.Q0 SLICE_9 (from PHI2_c) -ROUTE 2 0.128 R6C2A.Q0 to R6C2A.D0 ADSubmitted -CTOF_DEL --- 0.074 R6C2A.D0 to R6C2A.F0 SLICE_9 -ROUTE 1 0.000 R6C2A.F0 to R6C2A.DI0 ADSubmitted_r (to PHI2_c) +REG_DEL --- 0.137 R8C6A.CLK to R8C6A.Q0 SLICE_20 (from PHI2_c) +ROUTE 2 0.130 R8C6A.Q0 to R8C6A.D0 CmdEnable +CTOF_DEL --- 0.074 R8C6A.D0 to R8C6A.F0 SLICE_20 +ROUTE 1 0.000 R8C6A.F0 to R8C6A.DI0 CmdEnable_s (to PHI2_c) -------- - 0.339 (62.2% logic, 37.8% route), 2 logic levels. + 0.341 (61.9% logic, 38.1% route), 2 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_9: + Source Clock Path PHI2 to SLICE_20: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R6C2A.CLK PHI2_c +ROUTE 15 0.907 39.PADDI to R8C6A.CLK PHI2_c -------- 0.907 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_9: + Destination Clock Path PHI2 to SLICE_20: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R6C2A.CLK PHI2_c +ROUTE 15 0.907 39.PADDI to R8C6A.CLK PHI2_c -------- 0.907 (0.0% logic, 100.0% route), 0 logic levels. @@ -1303,10 +1308,10 @@ Passed: The following path meets requirements by 0.361ns Data path SLICE_14 to SLICE_14: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R7C3C.CLK to R7C3C.Q0 SLICE_14 (from PHI2_c) -ROUTE 2 0.131 R7C3C.Q0 to R7C3C.A0 C1Submitted -CTOF_DEL --- 0.074 R7C3C.A0 to R7C3C.F0 SLICE_14 -ROUTE 1 0.000 R7C3C.F0 to R7C3C.DI0 C1Submitted_RNO (to PHI2_c) +REG_DEL --- 0.137 R8C6C.CLK to R8C6C.Q0 SLICE_14 (from PHI2_c) +ROUTE 2 0.131 R8C6C.Q0 to R8C6C.A0 C1Submitted +CTOF_DEL --- 0.074 R8C6C.A0 to R8C6C.F0 SLICE_14 +ROUTE 1 0.000 R8C6C.F0 to R8C6C.DI0 C1Submitted_RNO (to PHI2_c) -------- 0.342 (61.7% logic, 38.3% route), 2 logic levels. @@ -1315,14 +1320,59 @@ ROUTE 1 0.000 R7C3C.F0 to R7C3C.DI0 C1Submitted_RNO (to P Source Clock Path PHI2 to SLICE_14: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R7C3C.CLK PHI2_c +ROUTE 15 0.907 39.PADDI to R8C6C.CLK PHI2_c -------- 0.907 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_14: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R7C3C.CLK PHI2_c +ROUTE 15 0.907 39.PADDI to R8C6C.CLK PHI2_c + -------- + 0.907 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.361ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q ADSubmitted (from PHI2_c -) + Destination: FF Data in ADSubmitted (to PHI2_c -) + + Delay: 0.342ns (61.7% logic, 38.3% route), 2 logic levels. + + Constraint Details: + + 0.342ns physical path delay SLICE_9 to SLICE_9 meets + -0.019ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.361ns + + Physical Path Details: + + Data path SLICE_9 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R8C6B.CLK to R8C6B.Q0 SLICE_9 (from PHI2_c) +ROUTE 2 0.131 R8C6B.Q0 to R8C6B.A0 ADSubmitted +CTOF_DEL --- 0.074 R8C6B.A0 to R8C6B.F0 SLICE_9 +ROUTE 1 0.000 R8C6B.F0 to R8C6B.DI0 ADSubmitted_r (to PHI2_c) + -------- + 0.342 (61.7% logic, 38.3% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 0.907 39.PADDI to R8C6B.CLK PHI2_c + -------- + 0.907 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 0.907 39.PADDI to R8C6B.CLK PHI2_c -------- 0.907 (0.0% logic, 100.0% route), 0 logic levels. @@ -1348,10 +1398,10 @@ Passed: The following path meets requirements by 0.364ns Data path SLICE_22 to SLICE_22: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R8C9D.CLK to R8C9D.Q0 SLICE_22 (from PHI2_c) -ROUTE 3 0.134 R8C9D.Q0 to R8C9D.A0 CmdSubmitted -CTOF_DEL --- 0.074 R8C9D.A0 to R8C9D.F0 SLICE_22 -ROUTE 1 0.000 R8C9D.F0 to R8C9D.DI0 N_460_0 (to PHI2_c) +REG_DEL --- 0.137 R9C6B.CLK to R9C6B.Q0 SLICE_22 (from PHI2_c) +ROUTE 3 0.134 R9C6B.Q0 to R9C6B.A0 CmdSubmitted +CTOF_DEL --- 0.074 R9C6B.A0 to R9C6B.F0 SLICE_22 +ROUTE 1 0.000 R9C6B.F0 to R9C6B.DI0 N_428_0 (to PHI2_c) -------- 0.345 (61.2% logic, 38.8% route), 2 logic levels. @@ -1360,333 +1410,294 @@ ROUTE 1 0.000 R8C9D.F0 to R8C9D.DI0 N_460_0 (to PHI2_c) Source Clock Path PHI2 to SLICE_22: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R8C9D.CLK PHI2_c +ROUTE 15 0.907 39.PADDI to R9C6B.CLK PHI2_c -------- 0.907 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_22: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R8C9D.CLK PHI2_c +ROUTE 15 0.907 39.PADDI to R9C6B.CLK PHI2_c -------- 0.907 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 0.411ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CmdEnable (from PHI2_c -) - Destination: FF Data in CmdEnable (to PHI2_c -) - - Delay: 0.392ns (65.8% logic, 34.2% route), 2 logic levels. - - Constraint Details: - - 0.392ns physical path delay SLICE_20 to SLICE_20 meets - -0.019ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.411ns - - Physical Path Details: - - Data path SLICE_20 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R6C2D.CLK to R6C2D.Q0 SLICE_20 (from PHI2_c) -ROUTE 3 0.134 R6C2D.Q0 to R6C2D.D1 CmdEnable -CTOOFX_DEL --- 0.121 R6C2D.D1 to R6C2D.OFX0 SLICE_20 -ROUTE 1 0.000 R6C2D.OFX0 to R6C2D.DI0 CmdEnable_s (to PHI2_c) - -------- - 0.392 (65.8% logic, 34.2% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R6C2D.CLK PHI2_c - -------- - 0.907 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R6C2D.CLK PHI2_c - -------- - 0.907 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.415ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CmdEnable (from PHI2_c -) - Destination: FF Data in CmdEnable (to PHI2_c -) - - Delay: 0.396ns (66.2% logic, 33.8% route), 2 logic levels. - - Constraint Details: - - 0.396ns physical path delay SLICE_20 to SLICE_20 meets - -0.019ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.415ns - - Physical Path Details: - - Data path SLICE_20 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R6C2D.CLK to R6C2D.Q0 SLICE_20 (from PHI2_c) -ROUTE 3 0.134 R6C2D.Q0 to R6C2D.A0 CmdEnable -CTOOFX_DEL --- 0.125 R6C2D.A0 to R6C2D.OFX0 SLICE_20 -ROUTE 1 0.000 R6C2D.OFX0 to R6C2D.DI0 CmdEnable_s (to PHI2_c) - -------- - 0.396 (66.2% logic, 33.8% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R6C2D.CLK PHI2_c - -------- - 0.907 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R6C2D.CLK PHI2_c - -------- - 0.907 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.471ns +Passed: The following path meets requirements by 0.572ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ADSubmitted (from PHI2_c -) Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 0.452ns (57.1% logic, 42.9% route), 2 logic levels. + Delay: 0.553ns (51.5% logic, 48.5% route), 3 logic levels. Constraint Details: - 0.452ns physical path delay SLICE_9 to SLICE_20 meets + 0.553ns physical path delay SLICE_9 to SLICE_20 meets -0.019ns DIN_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.471ns + 0.000ns skew requirement (totaling -0.019ns) by 0.572ns Physical Path Details: Data path SLICE_9 to SLICE_20: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R6C2A.CLK to R6C2A.Q0 SLICE_9 (from PHI2_c) -ROUTE 2 0.194 R6C2A.Q0 to R6C2D.A1 ADSubmitted -CTOOFX_DEL --- 0.121 R6C2D.A1 to R6C2D.OFX0 SLICE_20 -ROUTE 1 0.000 R6C2D.OFX0 to R6C2D.DI0 CmdEnable_s (to PHI2_c) +REG_DEL --- 0.137 R8C6B.CLK to R8C6B.Q0 SLICE_9 (from PHI2_c) +ROUTE 2 0.130 R8C6B.Q0 to R8C6A.D1 ADSubmitted +CTOF_DEL --- 0.074 R8C6A.D1 to R8C6A.F1 SLICE_20 +ROUTE 1 0.138 R8C6A.F1 to R8C6A.B0 CmdEnable_0_sqmuxa +CTOF_DEL --- 0.074 R8C6A.B0 to R8C6A.F0 SLICE_20 +ROUTE 1 0.000 R8C6A.F0 to R8C6A.DI0 CmdEnable_s (to PHI2_c) -------- - 0.452 (57.1% logic, 42.9% route), 2 logic levels. + 0.553 (51.5% logic, 48.5% route), 3 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_9: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R6C2A.CLK PHI2_c +ROUTE 15 0.907 39.PADDI to R8C6B.CLK PHI2_c -------- 0.907 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_20: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R6C2D.CLK PHI2_c +ROUTE 15 0.907 39.PADDI to R8C6A.CLK PHI2_c -------- 0.907 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 0.611ns +Passed: The following path meets requirements by 0.597ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Cmdn8MEGEN (from PHI2_c -) Destination: FF Data in Cmdn8MEGEN (to PHI2_c -) - Delay: 0.592ns (48.1% logic, 51.9% route), 3 logic levels. + Delay: 0.578ns (49.3% logic, 50.7% route), 3 logic levels. Constraint Details: - 0.592ns physical path delay SLICE_26 to SLICE_26 meets + 0.578ns physical path delay SLICE_26 to SLICE_26 meets -0.019ns DIN_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.611ns + 0.000ns skew requirement (totaling -0.019ns) by 0.597ns Physical Path Details: Data path SLICE_26 to SLICE_26: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R7C5B.CLK to R7C5B.Q0 SLICE_26 (from PHI2_c) -ROUTE 2 0.208 R7C5B.Q0 to R7C5B.B1 Cmdn8MEGEN -CTOF_DEL --- 0.074 R7C5B.B1 to R7C5B.F1 SLICE_26 -ROUTE 1 0.099 R7C5B.F1 to R7C5B.C0 Cmdn8MEGEN_4_u_i_0 -CTOF_DEL --- 0.074 R7C5B.C0 to R7C5B.F0 SLICE_26 -ROUTE 1 0.000 R7C5B.F0 to R7C5B.DI0 N_19_i (to PHI2_c) +REG_DEL --- 0.137 R9C7D.CLK to R9C7D.Q0 SLICE_26 (from PHI2_c) +ROUTE 2 0.194 R9C7D.Q0 to R9C7D.A1 Cmdn8MEGEN +CTOF_DEL --- 0.074 R9C7D.A1 to R9C7D.F1 SLICE_26 +ROUTE 1 0.099 R9C7D.F1 to R9C7D.C0 Cmdn8MEGEN_4_u_i_0 +CTOF_DEL --- 0.074 R9C7D.C0 to R9C7D.F0 SLICE_26 +ROUTE 1 0.000 R9C7D.F0 to R9C7D.DI0 N_12_i (to PHI2_c) -------- - 0.592 (48.1% logic, 51.9% route), 3 logic levels. + 0.578 (49.3% logic, 50.7% route), 3 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_26: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R7C5B.CLK PHI2_c +ROUTE 15 0.907 39.PADDI to R9C7D.CLK PHI2_c -------- 0.907 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_26: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R7C5B.CLK PHI2_c +ROUTE 15 0.907 39.PADDI to R9C7D.CLK PHI2_c -------- 0.907 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 0.634ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q C1Submitted (from PHI2_c -) - Destination: FF Data in CmdEnable (to PHI2_c -) - - Delay: 0.615ns (42.6% logic, 57.4% route), 2 logic levels. - - Constraint Details: - - 0.615ns physical path delay SLICE_14 to SLICE_20 meets - -0.019ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.634ns - - Physical Path Details: - - Data path SLICE_14 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R7C3C.CLK to R7C3C.Q0 SLICE_14 (from PHI2_c) -ROUTE 2 0.353 R7C3C.Q0 to R6C2D.C0 C1Submitted -CTOOFX_DEL --- 0.125 R6C2D.C0 to R6C2D.OFX0 SLICE_20 -ROUTE 1 0.000 R6C2D.OFX0 to R6C2D.DI0 CmdEnable_s (to PHI2_c) - -------- - 0.615 (42.6% logic, 57.4% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_14: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R7C3C.CLK PHI2_c - -------- - 0.907 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R6C2D.CLK PHI2_c - -------- - 0.907 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.665ns +Passed: The following path meets requirements by 0.599ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CmdLEDEN (from PHI2_c -) Destination: FF Data in CmdLEDEN (to PHI2_c -) - Delay: 0.646ns (44.1% logic, 55.9% route), 3 logic levels. + Delay: 0.580ns (49.1% logic, 50.9% route), 3 logic levels. Constraint Details: - 0.646ns physical path delay SLICE_21 to SLICE_21 meets + 0.580ns physical path delay SLICE_21 to SLICE_21 meets -0.019ns DIN_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.665ns + 0.000ns skew requirement (totaling -0.019ns) by 0.599ns Physical Path Details: Data path SLICE_21 to SLICE_21: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R7C5A.CLK to R7C5A.Q0 SLICE_21 (from PHI2_c) -ROUTE 2 0.169 R7C5A.Q0 to R7C5C.C1 CmdLEDEN -CTOF_DEL --- 0.074 R7C5C.C1 to R7C5C.F1 SLICE_82 -ROUTE 1 0.192 R7C5C.F1 to R7C5A.A0 N_132 -CTOF_DEL --- 0.074 R7C5A.A0 to R7C5A.F0 SLICE_21 -ROUTE 1 0.000 R7C5A.F0 to R7C5A.DI0 N_21_i (to PHI2_c) +REG_DEL --- 0.137 R9C8D.CLK to R9C8D.Q0 SLICE_21 (from PHI2_c) +ROUTE 2 0.196 R9C8D.Q0 to R9C8D.A1 CmdLEDEN +CTOF_DEL --- 0.074 R9C8D.A1 to R9C8D.F1 SLICE_21 +ROUTE 1 0.099 R9C8D.F1 to R9C8D.C0 CmdLEDEN_4_u_i_0 +CTOF_DEL --- 0.074 R9C8D.C0 to R9C8D.F0 SLICE_21 +ROUTE 1 0.000 R9C8D.F0 to R9C8D.DI0 N_14_i (to PHI2_c) -------- - 0.646 (44.1% logic, 55.9% route), 3 logic levels. + 0.580 (49.1% logic, 50.9% route), 3 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_21: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R7C5A.CLK PHI2_c +ROUTE 15 0.907 39.PADDI to R9C8D.CLK PHI2_c -------- 0.907 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_21: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R7C5A.CLK PHI2_c +ROUTE 15 0.907 39.PADDI to R9C8D.CLK PHI2_c -------- 0.907 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 0.723ns +Passed: The following path meets requirements by 0.626ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q C1Submitted (from PHI2_c -) + Destination: FF Data in CmdEnable (to PHI2_c -) + + Delay: 0.607ns (47.0% logic, 53.0% route), 3 logic levels. + + Constraint Details: + + 0.607ns physical path delay SLICE_14 to SLICE_20 meets + -0.019ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.626ns + + Physical Path Details: + + Data path SLICE_14 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R8C6C.CLK to R8C6C.Q0 SLICE_14 (from PHI2_c) +ROUTE 2 0.130 R8C6C.Q0 to R8C6C.D1 C1Submitted +CTOF_DEL --- 0.074 R8C6C.D1 to R8C6C.F1 SLICE_14 +ROUTE 1 0.192 R8C6C.F1 to R8C6A.A0 un1_CmdEnable20_i +CTOF_DEL --- 0.074 R8C6A.A0 to R8C6A.F0 SLICE_20 +ROUTE 1 0.000 R8C6A.F0 to R8C6A.DI0 CmdEnable_s (to PHI2_c) + -------- + 0.607 (47.0% logic, 53.0% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 0.907 39.PADDI to R8C6C.CLK PHI2_c + -------- + 0.907 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 0.907 39.PADDI to R8C6A.CLK PHI2_c + -------- + 0.907 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.638ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q XOR8MEG (from PHI2_c -) + Destination: FF Data in XOR8MEG (to PHI2_c -) + + Delay: 0.619ns (46.0% logic, 54.0% route), 3 logic levels. + + Constraint Details: + + 0.619ns physical path delay SLICE_57 to SLICE_57 meets + -0.019ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.638ns + + Physical Path Details: + + Data path SLICE_57 to SLICE_57: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R9C8A.CLK to R9C8A.Q0 SLICE_57 (from PHI2_c) +ROUTE 2 0.196 R9C8A.Q0 to R9C8A.A1 XOR8MEG +CTOF_DEL --- 0.074 R9C8A.A1 to R9C8A.F1 SLICE_57 +ROUTE 1 0.138 R9C8A.F1 to R9C8A.B0 N_166 +CTOF_DEL --- 0.074 R9C8A.B0 to R9C8A.F0 SLICE_57 +ROUTE 1 0.000 R9C8A.F0 to R9C8A.DI0 XOR8MEG_3 (to PHI2_c) + -------- + 0.619 (46.0% logic, 54.0% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_57: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 0.907 39.PADDI to R9C8A.CLK PHI2_c + -------- + 0.907 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_57: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 0.907 39.PADDI to R9C8A.CLK PHI2_c + -------- + 0.907 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.659ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CmdEnable (from PHI2_c -) Destination: FF Data in CmdLEDEN (to PHI2_c -) - Delay: 0.700ns (30.1% logic, 69.9% route), 2 logic levels. + Delay: 0.636ns (33.2% logic, 66.8% route), 2 logic levels. Constraint Details: - 0.700ns physical path delay SLICE_20 to SLICE_21 meets + 0.636ns physical path delay SLICE_20 to SLICE_21 meets -0.023ns CE_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.023ns) by 0.723ns + 0.000ns skew requirement (totaling -0.023ns) by 0.659ns Physical Path Details: Data path SLICE_20 to SLICE_21: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R6C2D.CLK to R6C2D.Q0 SLICE_20 (from PHI2_c) -ROUTE 3 0.348 R6C2D.Q0 to R7C5D.B0 CmdEnable -CTOF_DEL --- 0.074 R7C5D.B0 to R7C5D.F0 SLICE_67 -ROUTE 5 0.141 R7C5D.F0 to R7C5A.CE XOR8MEG18 (to PHI2_c) +REG_DEL --- 0.137 R8C6A.CLK to R8C6A.Q0 SLICE_20 (from PHI2_c) +ROUTE 2 0.183 R8C6A.Q0 to R9C6A.C0 CmdEnable +CTOF_DEL --- 0.074 R9C6A.C0 to R9C6A.F0 SLICE_73 +ROUTE 5 0.242 R9C6A.F0 to R9C8D.CE XOR8MEG18 (to PHI2_c) -------- - 0.700 (30.1% logic, 69.9% route), 2 logic levels. + 0.636 (33.2% logic, 66.8% route), 2 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_20: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R6C2D.CLK PHI2_c +ROUTE 15 0.907 39.PADDI to R8C6A.CLK PHI2_c -------- 0.907 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_21: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R7C5A.CLK PHI2_c +ROUTE 15 0.907 39.PADDI to R9C8D.CLK PHI2_c -------- 0.907 (0.0% logic, 100.0% route), 0 logic levels. @@ -1705,7 +1716,7 @@ Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ; ================================================================================ Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; - 388 items scored, 0 timing errors detected. + 392 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- @@ -1720,78 +1731,163 @@ Passed: The following path meets requirements by 0.273ns Constraint Details: - 0.256ns physical path delay SLICE_75 to SLICE_75 meets + 0.256ns physical path delay SLICE_74 to SLICE_74 meets -0.017ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.017ns) by 0.273ns Physical Path Details: - Data path SLICE_75 to SLICE_75: + Data path SLICE_74 to SLICE_74: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.126 R7C4B.CLK to R7C4B.Q0 SLICE_75 (from RCLK_c) -ROUTE 1 0.130 R7C4B.Q0 to R7C4B.M1 CASr (to RCLK_c) +REG_DEL --- 0.126 R8C7B.CLK to R8C7B.Q0 SLICE_74 (from RCLK_c) +ROUTE 1 0.130 R8C7B.Q0 to R8C7B.M1 CASr (to RCLK_c) -------- 0.256 (49.2% logic, 50.8% route), 1 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_75: + Source Clock Path RCLK to SLICE_74: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R7C4B.CLK RCLK_c +ROUTE 32 0.351 86.PADDI to R8C7B.CLK RCLK_c -------- 0.351 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_75: + Destination Clock Path RCLK to SLICE_74: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R7C4B.CLK RCLK_c +ROUTE 32 0.351 86.PADDI to R8C7B.CLK RCLK_c -------- 0.351 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 0.301ns +Passed: The following path meets requirements by 0.277ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS[17] (from RCLK_c +) - Destination: FF Data in FS[17] (to RCLK_c +) - FF FS[16] + Source: FF Q PHI2r2 (from RCLK_c +) + Destination: FF Data in PHI2r3 (to RCLK_c +) - Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels. + Delay: 0.260ns (48.5% logic, 51.5% route), 1 logic levels. Constraint Details: - 0.257ns physical path delay SLICE_1 to SLICE_1 meets - -0.044ns LUT_HLD and + 0.260ns physical path delay SLICE_41 to SLICE_43 meets + -0.017ns M_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.044ns) by 0.301ns + 0.000ns skew requirement (totaling -0.017ns) by 0.277ns Physical Path Details: - Data path SLICE_1 to SLICE_1: + Data path SLICE_41 to SLICE_43: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.126 R8C6A.CLK to R8C6A.Q1 SLICE_1 (from RCLK_c) -ROUTE 3 0.131 R8C6A.Q1 to R8C6A.A1 FS[17] (to RCLK_c) +REG_DEL --- 0.126 R4C6C.CLK to R4C6C.Q1 SLICE_41 (from RCLK_c) +ROUTE 3 0.134 R4C6C.Q1 to R4C6A.M1 PHI2r2 (to RCLK_c) -------- - 0.257 (49.0% logic, 51.0% route), 1 logic levels. + 0.260 (48.5% logic, 51.5% route), 1 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_1: + Source Clock Path RCLK to SLICE_41: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R8C6A.CLK RCLK_c +ROUTE 32 0.351 86.PADDI to R4C6C.CLK RCLK_c -------- 0.351 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_1: + Destination Clock Path RCLK to SLICE_43: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R8C6A.CLK RCLK_c +ROUTE 32 0.351 86.PADDI to R4C6A.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.277ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RASr (from RCLK_c +) + Destination: FF Data in RASr2 (to RCLK_c +) + + Delay: 0.260ns (48.5% logic, 51.5% route), 1 logic levels. + + Constraint Details: + + 0.260ns physical path delay SLICE_95 to SLICE_95 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.277ns + + Physical Path Details: + + Data path SLICE_95 to SLICE_95: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R3C5D.CLK to R3C5D.Q0 SLICE_95 (from RCLK_c) +ROUTE 2 0.134 R3C5D.Q0 to R3C5D.M1 RASr (to RCLK_c) + -------- + 0.260 (48.5% logic, 51.5% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_95: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 0.351 86.PADDI to R3C5D.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_95: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 0.351 86.PADDI to R3C5D.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.284ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RASr2 (from RCLK_c +) + Destination: FF Data in S[0] (to RCLK_c +) + + Delay: 0.267ns (47.2% logic, 52.8% route), 1 logic levels. + + Constraint Details: + + 0.267ns physical path delay SLICE_95 to SLICE_68 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.284ns + + Physical Path Details: + + Data path SLICE_95 to SLICE_68: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R3C5D.CLK to R3C5D.Q1 SLICE_95 (from RCLK_c) +ROUTE 13 0.141 R3C5D.Q1 to R3C5C.M0 RASr2 (to RCLK_c) + -------- + 0.267 (47.2% logic, 52.8% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_95: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 0.351 86.PADDI to R3C5D.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_68: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 0.351 86.PADDI to R3C5C.CLK RCLK_c -------- 0.351 (0.0% logic, 100.0% route), 0 logic levels. @@ -1819,8 +1915,8 @@ Passed: The following path meets requirements by 0.301ns Data path SLICE_2 to SLICE_2: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.126 R8C5D.CLK to R8C5D.Q1 SLICE_2 (from RCLK_c) -ROUTE 3 0.131 R8C5D.Q1 to R8C5D.A1 FS[15] (to RCLK_c) +REG_DEL --- 0.126 R10C4D.CLK to R10C4D.Q1 SLICE_2 (from RCLK_c) +ROUTE 3 0.131 R10C4D.Q1 to R10C4D.A1 FS[15] (to RCLK_c) -------- 0.257 (49.0% logic, 51.0% route), 1 logic levels. @@ -1829,14 +1925,14 @@ ROUTE 3 0.131 R8C5D.Q1 to R8C5D.A1 FS[15] (to RCLK_c) Source Clock Path RCLK to SLICE_2: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R8C5D.CLK RCLK_c +ROUTE 32 0.351 86.PADDI to R10C4D.CLK RCLK_c -------- 0.351 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_2: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R8C5D.CLK RCLK_c +ROUTE 32 0.351 86.PADDI to R10C4D.CLK RCLK_c -------- 0.351 (0.0% logic, 100.0% route), 0 logic levels. @@ -1864,8 +1960,8 @@ Passed: The following path meets requirements by 0.301ns Data path SLICE_3 to SLICE_3: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.126 R8C5C.CLK to R8C5C.Q1 SLICE_3 (from RCLK_c) -ROUTE 3 0.131 R8C5C.Q1 to R8C5C.A1 FS[13] (to RCLK_c) +REG_DEL --- 0.126 R10C4C.CLK to R10C4C.Q1 SLICE_3 (from RCLK_c) +ROUTE 4 0.131 R10C4C.Q1 to R10C4C.A1 FS[13] (to RCLK_c) -------- 0.257 (49.0% logic, 51.0% route), 1 logic levels. @@ -1874,14 +1970,104 @@ ROUTE 3 0.131 R8C5C.Q1 to R8C5C.A1 FS[13] (to RCLK_c) Source Clock Path RCLK to SLICE_3: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R8C5C.CLK RCLK_c +ROUTE 32 0.351 86.PADDI to R10C4C.CLK RCLK_c -------- 0.351 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_3: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R8C5C.CLK RCLK_c +ROUTE 32 0.351 86.PADDI to R10C4C.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.301ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[9] (from RCLK_c +) + Destination: FF Data in FS_cry_0[8] (to RCLK_c +) + FF FS[9] + FF FS[8] + + Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels. + + Constraint Details: + + 0.257ns physical path delay SLICE_5 to SLICE_5 meets + -0.044ns LUT_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.044ns) by 0.301ns + + Physical Path Details: + + Data path SLICE_5 to SLICE_5: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R10C4A.CLK to R10C4A.Q1 SLICE_5 (from RCLK_c) +ROUTE 3 0.131 R10C4A.Q1 to R10C4A.A1 FS[9] (to RCLK_c) + -------- + 0.257 (49.0% logic, 51.0% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_5: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 0.351 86.PADDI to R10C4A.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_5: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 0.351 86.PADDI to R10C4A.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.301ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[7] (from RCLK_c +) + Destination: FF Data in FS_cry_0[6] (to RCLK_c +) + FF FS[7] + FF FS[6] + + Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels. + + Constraint Details: + + 0.257ns physical path delay SLICE_6 to SLICE_6 meets + -0.044ns LUT_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.044ns) by 0.301ns + + Physical Path Details: + + Data path SLICE_6 to SLICE_6: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R10C3D.CLK to R10C3D.Q1 SLICE_6 (from RCLK_c) +ROUTE 3 0.131 R10C3D.Q1 to R10C3D.A1 FS[7] (to RCLK_c) + -------- + 0.257 (49.0% logic, 51.0% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_6: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 0.351 86.PADDI to R10C3D.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_6: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 0.351 86.PADDI to R10C3D.CLK RCLK_c -------- 0.351 (0.0% logic, 100.0% route), 0 logic levels. @@ -1909,8 +2095,8 @@ Passed: The following path meets requirements by 0.301ns Data path SLICE_7 to SLICE_7: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.126 R8C4C.CLK to R8C4C.Q1 SLICE_7 (from RCLK_c) -ROUTE 4 0.131 R8C4C.Q1 to R8C4C.A1 FS[5] (to RCLK_c) +REG_DEL --- 0.126 R10C3C.CLK to R10C3C.Q1 SLICE_7 (from RCLK_c) +ROUTE 4 0.131 R10C3C.Q1 to R10C3C.A1 FS[5] (to RCLK_c) -------- 0.257 (49.0% logic, 51.0% route), 1 logic levels. @@ -1919,14 +2105,14 @@ ROUTE 4 0.131 R8C4C.Q1 to R8C4C.A1 FS[5] (to RCLK_c) Source Clock Path RCLK to SLICE_7: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R8C4C.CLK RCLK_c +ROUTE 32 0.351 86.PADDI to R10C3C.CLK RCLK_c -------- 0.351 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_7: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R8C4C.CLK RCLK_c +ROUTE 32 0.351 86.PADDI to R10C3C.CLK RCLK_c -------- 0.351 (0.0% logic, 100.0% route), 0 logic levels. @@ -1954,8 +2140,8 @@ Passed: The following path meets requirements by 0.301ns Data path SLICE_8 to SLICE_8: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.126 R8C4B.CLK to R8C4B.Q1 SLICE_8 (from RCLK_c) -ROUTE 3 0.131 R8C4B.Q1 to R8C4B.A1 FS[3] (to RCLK_c) +REG_DEL --- 0.126 R10C3B.CLK to R10C3B.Q1 SLICE_8 (from RCLK_c) +ROUTE 2 0.131 R10C3B.Q1 to R10C3B.A1 FS[3] (to RCLK_c) -------- 0.257 (49.0% logic, 51.0% route), 1 logic levels. @@ -1964,194 +2150,14 @@ ROUTE 3 0.131 R8C4B.Q1 to R8C4B.A1 FS[3] (to RCLK_c) Source Clock Path RCLK to SLICE_8: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R8C4B.CLK RCLK_c +ROUTE 32 0.351 86.PADDI to R10C3B.CLK RCLK_c -------- 0.351 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_8: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R8C4B.CLK RCLK_c - -------- - 0.351 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.302ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[0] (from RCLK_c +) - Destination: FF Data in FS_cry_0[0] (to RCLK_c +) - FF FS[1] - FF FS[0] - - Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels. - - Constraint Details: - - 0.257ns physical path delay SLICE_0 to SLICE_0 meets - -0.045ns LUT_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.045ns) by 0.302ns - - Physical Path Details: - - Data path SLICE_0 to SLICE_0: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.126 R8C4A.CLK to R8C4A.Q0 SLICE_0 (from RCLK_c) -ROUTE 3 0.131 R8C4A.Q0 to R8C4A.A0 FS[0] (to RCLK_c) - -------- - 0.257 (49.0% logic, 51.0% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_0: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R8C4A.CLK RCLK_c - -------- - 0.351 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_0: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R8C4A.CLK RCLK_c - -------- - 0.351 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.302ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[10] (from RCLK_c +) - Destination: FF Data in FS_cry_0[10] (to RCLK_c +) - FF FS[11] - FF FS[10] - - Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels. - - Constraint Details: - - 0.257ns physical path delay SLICE_4 to SLICE_4 meets - -0.045ns LUT_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.045ns) by 0.302ns - - Physical Path Details: - - Data path SLICE_4 to SLICE_4: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.126 R8C5B.CLK to R8C5B.Q0 SLICE_4 (from RCLK_c) -ROUTE 5 0.131 R8C5B.Q0 to R8C5B.A0 FS[10] (to RCLK_c) - -------- - 0.257 (49.0% logic, 51.0% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_4: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R8C5B.CLK RCLK_c - -------- - 0.351 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_4: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R8C5B.CLK RCLK_c - -------- - 0.351 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.302ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[8] (from RCLK_c +) - Destination: FF Data in FS_cry_0[8] (to RCLK_c +) - FF FS[9] - FF FS[8] - - Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels. - - Constraint Details: - - 0.257ns physical path delay SLICE_5 to SLICE_5 meets - -0.045ns LUT_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.045ns) by 0.302ns - - Physical Path Details: - - Data path SLICE_5 to SLICE_5: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.126 R8C5A.CLK to R8C5A.Q0 SLICE_5 (from RCLK_c) -ROUTE 3 0.131 R8C5A.Q0 to R8C5A.A0 FS[8] (to RCLK_c) - -------- - 0.257 (49.0% logic, 51.0% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_5: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R8C5A.CLK RCLK_c - -------- - 0.351 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_5: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R8C5A.CLK RCLK_c - -------- - 0.351 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.302ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[6] (from RCLK_c +) - Destination: FF Data in FS_cry_0[6] (to RCLK_c +) - FF FS[7] - FF FS[6] - - Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels. - - Constraint Details: - - 0.257ns physical path delay SLICE_6 to SLICE_6 meets - -0.045ns LUT_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.045ns) by 0.302ns - - Physical Path Details: - - Data path SLICE_6 to SLICE_6: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.126 R8C4D.CLK to R8C4D.Q0 SLICE_6 (from RCLK_c) -ROUTE 3 0.131 R8C4D.Q0 to R8C4D.A0 FS[6] (to RCLK_c) - -------- - 0.257 (49.0% logic, 51.0% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_6: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R8C4D.CLK RCLK_c - -------- - 0.351 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_6: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R8C4D.CLK RCLK_c +ROUTE 32 0.351 86.PADDI to R10C3B.CLK RCLK_c -------- 0.351 (0.0% logic, 100.0% route), 0 logic levels. @@ -2222,7 +2228,7 @@ Timing summary (Hold): Timing errors: 0 Score: 0 Cumulative negative slack: 0 -Constraints cover 517 paths, 4 nets, and 421 connections (66.51% coverage) +Constraints cover 560 paths, 4 nets, and 450 connections (66.08% coverage) diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_bgn.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_bgn.html index 5fcac8c..9bb10a0 100644 --- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_bgn.html +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_bgn.html @@ -12,7 +12,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Thu Sep 21 05:38:46 2023 +Sat Jan 06 06:25:23 2024 Command: bitgen -w -g ES:No -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_cck.rpt b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_cck.rpt index fe15c3c..de47d6f 100644 --- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_cck.rpt +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_cck.rpt @@ -13,7 +13,7 @@ Hostname: ZANEMACWIN11 Implementation : impl1 -# Written on Thu Sep 21 05:38:23 2023 +# Written on Sat Jan 6 06:25:03 2024 ##### DESIGN INFO ####################################################### @@ -48,8 +48,8 @@ nCRAS RCLK | No paths | No paths | No p 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. -@W:"//mac/icloud/repos/ram2gs/cpld/ram2gs.sdc":2:0:2:0|Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. @W:"//mac/icloud/repos/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small. +@W:"//mac/icloud/repos/ram2gs/cpld/ram2gs.sdc":2:0:2:0|Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. @W:"//mac/icloud/repos/ram2gs/cpld/ram2gs.sdc":3:0:3:0|Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. @W:"//mac/icloud/repos/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small. @W:"//mac/icloud/repos/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small. diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_iotiming.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_iotiming.html index 45d0bd9..361efd0 100644 --- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_iotiming.html +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_iotiming.html @@ -38,7 +38,7 @@ Performance Hardware Data Status: Version 1.124. // Package: TQFP100 // ncd File: ram2gs_lcmxo640c_impl1.ncd // Version: Diamond (64-bit) 3.12.1.454 -// Written on Thu Sep 21 05:38:44 2023 +// Written on Sat Jan 06 06:25:22 2024 // M: Minimum Performance Grade // iotiming RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO640C/promote.xml @@ -50,98 +50,98 @@ Worst Case Results across Performance Grades (M, 5, 4, 3): Port Clock Edge Setup Performance_Grade Hold Performance_Grade ---------------------------------------------------------------------- -CROW[0] nCRAS F -0.012 M 2.299 3 -CROW[1] nCRAS F -0.094 M 2.568 3 -Din[0] PHI2 F 5.117 3 2.324 3 -Din[0] nCCAS F 1.863 3 -0.129 M -Din[1] PHI2 F 4.727 3 3.095 3 -Din[1] nCCAS F 0.973 3 0.261 3 -Din[2] PHI2 F 4.040 3 2.270 3 -Din[2] nCCAS F 1.372 3 -0.027 M -Din[3] PHI2 F 4.809 3 1.454 3 -Din[3] nCCAS F 0.916 3 0.298 3 -Din[4] PHI2 F 6.041 3 2.279 3 -Din[4] nCCAS F 1.531 3 -0.100 M -Din[5] PHI2 F 5.903 3 2.260 3 -Din[5] nCCAS F 2.338 3 -0.268 M -Din[6] PHI2 F 6.028 3 1.422 3 -Din[6] nCCAS F 1.099 3 0.266 3 -Din[7] PHI2 F 6.673 3 2.385 3 -Din[7] nCCAS F 0.940 3 0.417 3 -MAin[0] PHI2 F 4.543 3 0.820 3 -MAin[0] nCRAS F -0.219 M 3.000 3 -MAin[1] PHI2 F 4.179 3 1.515 3 -MAin[1] nCRAS F -0.122 M 2.681 3 -MAin[2] PHI2 F 9.178 3 -0.474 M -MAin[2] nCRAS F -0.219 M 3.000 3 -MAin[3] PHI2 F 9.642 3 -0.572 M -MAin[3] nCRAS F -0.200 M 2.949 3 -MAin[4] PHI2 F 9.311 3 -0.515 M -MAin[4] nCRAS F 0.454 3 1.905 3 -MAin[5] PHI2 F 8.033 3 -0.256 M -MAin[5] nCRAS F -0.214 M 2.985 3 -MAin[6] PHI2 F 8.467 3 -0.339 M -MAin[6] nCRAS F 0.019 3 2.253 3 -MAin[7] PHI2 F 8.283 3 -0.303 M -MAin[7] nCRAS F -0.200 M 2.949 3 -MAin[8] nCRAS F -0.239 M 3.098 3 -MAin[9] nCRAS F -0.200 M 2.952 3 +CROW[0] nCRAS F -0.112 M 2.651 3 +CROW[1] nCRAS F -0.021 M 2.351 3 +Din[0] PHI2 F 4.317 3 1.888 3 +Din[0] nCCAS F 1.401 3 -0.032 M +Din[1] PHI2 F 6.362 3 2.174 3 +Din[1] nCCAS F 0.920 3 0.293 3 +Din[2] PHI2 F 4.582 3 1.108 3 +Din[2] nCCAS F 1.367 3 -0.025 M +Din[3] PHI2 F 6.558 3 2.698 3 +Din[3] nCCAS F 0.619 3 0.544 3 +Din[4] PHI2 F 7.083 3 0.535 3 +Din[4] nCCAS F 0.558 3 0.857 3 +Din[5] PHI2 F 6.015 3 2.171 3 +Din[5] nCCAS F 0.035 3 1.300 3 +Din[6] PHI2 F 6.445 3 1.417 3 +Din[6] nCCAS F 1.089 3 0.272 3 +Din[7] PHI2 F 6.645 3 2.275 3 +Din[7] nCCAS F 0.961 3 0.396 3 +MAin[0] PHI2 F 7.871 3 -0.129 M +MAin[0] nCRAS F -0.325 M 3.376 3 +MAin[1] PHI2 F 8.822 3 -0.149 M +MAin[1] nCRAS F -0.467 M 3.889 3 +MAin[2] PHI2 F 7.393 3 0.809 3 +MAin[2] nCRAS F -0.468 M 3.890 3 +MAin[3] PHI2 F 8.567 3 -0.143 M +MAin[3] nCRAS F -0.148 M 2.780 3 +MAin[4] PHI2 F 9.168 3 -0.113 M +MAin[4] nCRAS F 0.492 3 1.836 3 +MAin[5] PHI2 F 7.300 3 0.076 3 +MAin[5] nCRAS F -0.108 M 2.641 3 +MAin[6] PHI2 F 8.643 3 -0.385 M +MAin[6] nCRAS F -0.216 M 2.988 3 +MAin[7] PHI2 F 7.923 3 -0.224 M +MAin[7] nCRAS F -0.325 M 3.376 3 +MAin[8] nCRAS F -0.328 M 3.387 3 +MAin[9] nCRAS F -0.352 M 3.481 3 PHI2 RCLK R 2.024 3 -0.115 M -UFMSDO RCLK R 2.747 3 -0.023 M -nCCAS RCLK R 1.461 3 0.049 3 -nCCAS nCRAS F 0.041 3 2.233 3 -nCRAS RCLK R 1.492 3 0.026 3 -nFWE PHI2 F 9.958 3 -0.643 M -nFWE nCRAS F -0.200 M 2.952 3 +UFMSDO RCLK R 2.286 3 -0.106 M +nCCAS RCLK R 3.326 3 -0.370 M +nCCAS nCRAS F 0.813 3 1.646 3 +nCRAS RCLK R 5.235 3 -0.614 M +nFWE PHI2 F 5.814 3 0.503 3 +nFWE nCRAS F 0.183 3 2.096 3 // Clock to Output Delay Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade ------------------------------------------------------------------------ -LED RCLK R 13.643 3 4.416 M -LED nCRAS F 18.132 3 5.318 M -RA[0] RCLK R 10.790 3 2.216 M -RA[0] nCRAS F 13.344 3 2.709 M +LED RCLK R 16.515 3 4.482 M +LED nCRAS F 17.585 3 5.197 M +RA[0] RCLK R 11.366 3 2.326 M +RA[0] nCRAS F 13.548 3 2.745 M RA[10] RCLK R 6.926 3 1.431 M RA[11] PHI2 R 9.183 3 1.867 M -RA[1] RCLK R 11.242 3 2.314 M -RA[1] nCRAS F 14.215 3 2.899 M -RA[2] RCLK R 10.691 3 2.207 M -RA[2] nCRAS F 13.021 3 2.641 M -RA[3] RCLK R 11.553 3 2.371 M -RA[3] nCRAS F 13.307 3 2.703 M -RA[4] RCLK R 10.653 3 2.186 M -RA[4] nCRAS F 12.915 3 2.624 M -RA[5] RCLK R 11.976 3 2.463 M -RA[5] nCRAS F 13.269 3 2.696 M -RA[6] RCLK R 9.986 3 2.078 M -RA[6] nCRAS F 12.404 3 2.531 M -RA[7] RCLK R 10.257 3 2.107 M -RA[7] nCRAS F 12.647 3 2.563 M -RA[8] RCLK R 11.577 3 2.383 M -RA[8] nCRAS F 13.570 3 2.740 M -RA[9] RCLK R 11.562 3 2.371 M -RA[9] nCRAS F 14.266 3 2.895 M -RBA[0] nCRAS F 10.698 3 2.157 M -RBA[1] nCRAS F 12.177 3 2.478 M +RA[1] RCLK R 9.283 3 1.909 M +RA[1] nCRAS F 12.064 3 2.463 M +RA[2] RCLK R 11.466 3 2.345 M +RA[2] nCRAS F 13.609 3 2.759 M +RA[3] RCLK R 10.239 3 2.114 M +RA[3] nCRAS F 12.115 3 2.471 M +RA[4] RCLK R 10.462 3 2.158 M +RA[4] nCRAS F 12.460 3 2.541 M +RA[5] RCLK R 11.714 3 2.410 M +RA[5] nCRAS F 14.027 3 2.856 M +RA[6] RCLK R 10.222 3 2.111 M +RA[6] nCRAS F 12.507 3 2.549 M +RA[7] RCLK R 10.118 3 2.066 M +RA[7] nCRAS F 13.612 3 2.768 M +RA[8] RCLK R 11.860 3 2.450 M +RA[8] nCRAS F 13.529 3 2.745 M +RA[9] RCLK R 11.723 3 2.414 M +RA[9] nCRAS F 14.189 3 2.884 M +RBA[0] nCRAS F 12.165 3 2.476 M +RBA[1] nCRAS F 10.690 3 2.155 M RCKE RCLK R 6.926 3 1.431 M -RDQMH RCLK R 11.068 3 2.337 M -RDQML RCLK R 11.619 3 2.421 M -RD[0] nCCAS F 8.787 3 1.927 M -RD[1] nCCAS F 8.785 3 1.927 M -RD[2] nCCAS F 8.076 3 1.799 M -RD[3] nCCAS F 9.246 3 2.027 M -RD[4] nCCAS F 9.626 3 2.112 M -RD[5] nCCAS F 9.183 3 2.015 M -RD[6] nCCAS F 8.537 3 1.898 M -RD[7] nCCAS F 9.704 3 2.117 M +RDQMH RCLK R 12.309 3 2.582 M +RDQML RCLK R 11.893 3 2.496 M +RD[0] nCCAS F 8.780 3 1.926 M +RD[1] nCCAS F 8.780 3 1.926 M +RD[2] nCCAS F 8.071 3 1.798 M +RD[3] nCCAS F 9.242 3 2.016 M +RD[4] nCCAS F 11.095 3 2.414 M +RD[5] nCCAS F 10.651 3 2.326 M +RD[6] nCCAS F 8.532 3 1.897 M +RD[7] nCCAS F 9.699 3 2.116 M UFMCLK RCLK R 8.800 3 1.847 M UFMSDI RCLK R 8.079 3 1.714 M nRCAS RCLK R 6.926 3 1.431 M -nRCS RCLK R 7.765 3 1.590 M -nRRAS RCLK R 8.554 3 1.749 M -nRWE RCLK R 8.704 3 1.789 M +nRCS RCLK R 6.926 3 1.431 M +nRRAS RCLK R 8.147 3 1.667 M +nRWE RCLK R 9.027 3 1.858 M nUFMCS RCLK R 9.262 3 1.937 M WARNING: you must also run trce with hold speed: 3 WARNING: you must also run trce with setup speed: M diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvo.sdf b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvo.sdf index 5a2857e..2f0ec63 100644 --- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvo.sdf +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvo.sdf @@ -1,7 +1,7 @@ (DELAYFILE (SDFVERSION "3.0") (DESIGN "RAM2GS") - (DATE "Thu Sep 21 05:38:32 2023") + (DATE "Sat Jan 06 06:25:11 2024") (VENDOR "Lattice") (PROGRAM "ldbanno") (VERSION "Diamond (64-bit) 3.12.1.454") @@ -172,8 +172,6 @@ (INSTANCE SLICE_9) (DELAY (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) - (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) @@ -196,6 +194,7 @@ (INSTANCE SLICE_14) (DELAY (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) @@ -215,40 +214,18 @@ ) ) (CELL - (CELLTYPE "SLICE_19") - (INSTANCE SLICE_19) + (CELLTYPE "SLICE_20") + (INSTANCE SLICE_20) (DELAY (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) - (IOPATH CLK Q0 (515:537:560)(515:537:560)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) - (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1000:1000:1000)) - (WIDTH (negedge CLK) (1000:1000:1000)) - ) - ) - (CELL - (CELLTYPE "SLICE_20") - (INSTANCE SLICE_20) - (DELAY - (ABSOLUTE - (IOPATH B1 OFX0 (496:555:615)(496:555:615)) - (IOPATH A1 OFX0 (496:555:615)(496:555:615)) - (IOPATH D0 OFX0 (508:569:631)(508:569:631)) - (IOPATH C0 OFX0 (508:569:631)(508:569:631)) - (IOPATH B0 OFX0 (508:569:631)(508:569:631)) - (IOPATH A0 OFX0 (508:569:631)(508:569:631)) - (IOPATH M0 OFX0 (405:453:501)(405:453:501)) (IOPATH CLK Q0 (560:586:613)(560:586:613)) ) ) @@ -265,10 +242,10 @@ (INSTANCE SLICE_21) (DELAY (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) @@ -335,7 +312,6 @@ (INSTANCE SLICE_29) (DELAY (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) @@ -343,10 +319,12 @@ (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) ) ) (TIMINGCHECK (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) ) (TIMINGCHECK (WIDTH (posedge CLK) (1000:1000:1000)) @@ -429,6 +407,7 @@ (INSTANCE SLICE_33) (DELAY (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) @@ -447,11 +426,35 @@ (WIDTH (negedge CLK) (1000:1000:1000)) ) ) + (CELL + (CELLTYPE "SLICE_38") + (INSTANCE SLICE_38) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) (CELL (CELLTYPE "SLICE_39") (INSTANCE SLICE_39) (DELAY (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH C0 F0 (301:336:371)(301:336:371)) @@ -500,7 +503,6 @@ (INSTANCE SLICE_42) (DELAY (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) @@ -607,12 +609,10 @@ (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (515:537:560)(515:537:560)) - (IOPATH CLK Q1 (515:537:560)(515:537:560)) ) ) (TIMINGCHECK (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) - (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) ) (TIMINGCHECK (WIDTH (posedge CLK) (1000:1000:1000)) @@ -633,12 +633,10 @@ (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (515:537:560)(515:537:560)) - (IOPATH CLK Q1 (515:537:560)(515:537:560)) ) ) (TIMINGCHECK (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) - (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) ) (TIMINGCHECK (WIDTH (posedge CLK) (1000:1000:1000)) @@ -671,11 +669,8 @@ (INSTANCE SLICE_56) (DELAY (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) - (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (560:586:613)(560:586:613)) @@ -696,8 +691,6 @@ (INSTANCE SLICE_57) (DELAY (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) - (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) @@ -744,7 +737,6 @@ (INSTANCE SLICE_59) (DELAY (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) @@ -768,7 +760,6 @@ (INSTANCE SLICE_60) (DELAY (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) @@ -906,6 +897,7 @@ (INSTANCE SLICE_66) (DELAY (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) @@ -913,26 +905,14 @@ (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) - (IOPATH CLK Q0 (560:586:613)(560:586:613)) - (IOPATH CLK Q1 (560:586:613)(560:586:613)) ) ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1000:1000:1000)) - (WIDTH (negedge CLK) (1000:1000:1000)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) - (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) - (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) - ) ) (CELL (CELLTYPE "SLICE_67") (INSTANCE SLICE_67) (DELAY (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) @@ -967,78 +947,21 @@ (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) ) ) + (TIMINGCHECK + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) ) (CELL (CELLTYPE "SLICE_69") (INSTANCE SLICE_69) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) - (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH D0 F0 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) - ) - ) - ) - (CELL - (CELLTYPE "SLICE_70") - (INSTANCE SLICE_70) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) - (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) - (IOPATH CLK Q0 (515:537:560)(515:537:560)) - (IOPATH CLK Q1 (515:537:560)(515:537:560)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) - (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1000:1000:1000)) - (WIDTH (negedge CLK) (1000:1000:1000)) - ) - ) - (CELL - (CELLTYPE "SLICE_71") - (INSTANCE SLICE_71) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) - (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH D0 F0 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) - (IOPATH CLK Q0 (515:537:560)(515:537:560)) - (IOPATH CLK Q1 (515:537:560)(515:537:560)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) - (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1000:1000:1000)) - (WIDTH (negedge CLK) (1000:1000:1000)) - ) - ) - (CELL - (CELLTYPE "SLICE_72") - (INSTANCE SLICE_72) (DELAY (ABSOLUTE (IOPATH C1 F1 (301:336:371)(301:336:371)) @@ -1062,6 +985,51 @@ (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) ) ) + (CELL + (CELLTYPE "SLICE_70") + (INSTANCE SLICE_70) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_71") + (INSTANCE SLICE_71) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_72") + (INSTANCE SLICE_72) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) (CELL (CELLTYPE "SLICE_73") (INSTANCE SLICE_73) @@ -1084,7 +1052,7 @@ (TIMINGCHECK (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) - (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) ) ) (CELL @@ -1098,23 +1066,25 @@ (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) - (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) ) ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) (TIMINGCHECK (WIDTH (posedge CLK) (1000:1000:1000)) (WIDTH (negedge CLK) (1000:1000:1000)) ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) - (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) - ) ) (CELL (CELLTYPE "SLICE_75") (INSTANCE SLICE_75) (DELAY (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) @@ -1139,6 +1109,8 @@ (INSTANCE SLICE_76) (DELAY (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) @@ -1161,6 +1133,36 @@ (CELL (CELLTYPE "SLICE_77") (INSTANCE SLICE_77) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_78") + (INSTANCE SLICE_78) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_79") + (INSTANCE SLICE_79) (DELAY (ABSOLUTE (IOPATH B1 F1 (301:336:371)(301:336:371)) @@ -1182,55 +1184,6 @@ (WIDTH (negedge CLK) (1000:1000:1000)) ) ) - (CELL - (CELLTYPE "SLICE_78") - (INSTANCE SLICE_78) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH D0 F0 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) - (IOPATH CLK Q0 (560:586:613)(560:586:613)) - (IOPATH CLK Q1 (560:586:613)(560:586:613)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1000:1000:1000)) - (WIDTH (negedge CLK) (1000:1000:1000)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) - (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) - ) - ) - (CELL - (CELLTYPE "SLICE_79") - (INSTANCE SLICE_79) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH D0 F0 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) - (IOPATH CLK Q0 (560:586:613)(560:586:613)) - (IOPATH CLK Q1 (560:586:613)(560:586:613)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1000:1000:1000)) - (WIDTH (negedge CLK) (1000:1000:1000)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) - (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) - ) - ) (CELL (CELLTYPE "SLICE_80") (INSTANCE SLICE_80) @@ -1242,19 +1195,8 @@ (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) - (IOPATH CLK Q0 (560:586:613)(560:586:613)) - (IOPATH CLK Q1 (560:586:613)(560:586:613)) ) ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1000:1000:1000)) - (WIDTH (negedge CLK) (1000:1000:1000)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) - (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) - (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) - ) ) (CELL (CELLTYPE "SLICE_81") @@ -1269,6 +1211,21 @@ (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_82") + (INSTANCE SLICE_82) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (560:586:613)(560:586:613)) (IOPATH CLK Q1 (560:586:613)(560:586:613)) ) @@ -1283,8 +1240,8 @@ ) ) (CELL - (CELLTYPE "SLICE_82") - (INSTANCE SLICE_82) + (CELLTYPE "SLICE_83") + (INSTANCE SLICE_83) (DELAY (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) @@ -1295,28 +1252,6 @@ (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) - (IOPATH CLK Q0 (515:537:560)(515:537:560)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1000:1000:1000)) - (WIDTH (negedge CLK) (1000:1000:1000)) - ) - ) - (CELL - (CELLTYPE "SLICE_83") - (INSTANCE SLICE_83) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (560:586:613)(560:586:613)) (IOPATH CLK Q1 (560:586:613)(560:586:613)) ) @@ -1344,12 +1279,64 @@ (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) ) ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) ) (CELL (CELLTYPE "SLICE_85") (INSTANCE SLICE_85) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_86") + (INSTANCE SLICE_86) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_87") + (INSTANCE SLICE_87) (DELAY (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) @@ -1374,8 +1361,82 @@ ) ) (CELL - (CELLTYPE "SLICE_86") - (INSTANCE SLICE_86) + (CELLTYPE "SLICE_88") + (INSTANCE SLICE_88) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_89") + (INSTANCE SLICE_89) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_90") + (INSTANCE SLICE_90) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_91") + (INSTANCE SLICE_91) (DELAY (ABSOLUTE (IOPATH B1 F1 (301:336:371)(301:336:371)) @@ -1387,8 +1448,8 @@ ) ) (CELL - (CELLTYPE "SLICE_87") - (INSTANCE SLICE_87) + (CELLTYPE "SLICE_92") + (INSTANCE SLICE_92) (DELAY (ABSOLUTE (IOPATH C1 F1 (301:336:371)(301:336:371)) @@ -1402,8 +1463,142 @@ ) ) (CELL - (CELLTYPE "SLICE_88") - (INSTANCE SLICE_88) + (CELLTYPE "SLICE_93") + (INSTANCE SLICE_93) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_94") + (INSTANCE SLICE_94) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_95") + (INSTANCE SLICE_95) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_96") + (INSTANCE SLICE_96) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_97") + (INSTANCE SLICE_97) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_98") + (INSTANCE SLICE_98) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_99") + (INSTANCE SLICE_99) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_100") + (INSTANCE SLICE_100) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_101") + (INSTANCE SLICE_101) (DELAY (ABSOLUTE (IOPATH C1 F1 (301:336:371)(301:336:371)) @@ -1422,97 +1617,6 @@ (TIMINGCHECK (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) - (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) - ) - ) - (CELL - (CELLTYPE "SLICE_89") - (INSTANCE SLICE_89) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) - ) - ) - ) - (CELL - (CELLTYPE "SLICE_90") - (INSTANCE SLICE_90) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) - ) - ) - ) - (CELL - (CELLTYPE "SLICE_91") - (INSTANCE SLICE_91) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) - ) - ) - ) - (CELL - (CELLTYPE "SLICE_92") - (INSTANCE SLICE_92) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) - ) - ) - ) - (CELL - (CELLTYPE "SLICE_93") - (INSTANCE SLICE_93) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) - ) - ) - ) - (CELL - (CELLTYPE "SLICE_94") - (INSTANCE SLICE_94) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) - (IOPATH CLK Q0 (515:537:560)(515:537:560)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) - (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1000:1000:1000)) - (WIDTH (negedge CLK) (1000:1000:1000)) ) ) (CELL @@ -2284,11 +2388,10 @@ (DELAY (ABSOLUTE (INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_0/Q1 SLICE_72/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_0/Q1 SLICE_84/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_69/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_89/A1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_0/Q0 SLICE_0/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_0/Q0 SLICE_68/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_0/Q0 SLICE_69/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q0 SLICE_94/A0 (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_0/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_1/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_2/CLK (0:0:0)(0:0:0)) @@ -2298,12 +2401,12 @@ (INTERCONNECT RCLK_I/PADDI SLICE_6/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_7/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_8/CLK (0:0:0)(0:0:0)) - (INTERCONNECT RCLK_I/PADDI SLICE_19/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_29/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_30/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_31/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_32/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_33/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_38/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_41/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_42/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_43/CLK (0:0:0)(0:0:0)) @@ -2318,94 +2421,87 @@ (INTERCONNECT RCLK_I/PADDI SLICE_62/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_63/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_64/CLK (0:0:0)(0:0:0)) - (INTERCONNECT RCLK_I/PADDI SLICE_75/CLK (0:0:0)(0:0:0)) - (INTERCONNECT RCLK_I/PADDI SLICE_82/CLK (0:0:0)(0:0:0)) - (INTERCONNECT RCLK_I/PADDI SLICE_94/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_68/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_74/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_95/CLK (0:0:0)(0:0:0)) (INTERCONNECT SLICE_0/FCO SLICE_8/FCI (0:0:0)(0:0:0)) (INTERCONNECT SLICE_1/Q1 SLICE_1/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q1 SLICE_81/D1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q1 SLICE_81/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q1 SLICE_80/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q1 SLICE_86/D1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q0 SLICE_66/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q0 SLICE_72/B1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q0 SLICE_74/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_69/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_86/D0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_2/FCO SLICE_1/FCI (0:0:0)(0:0:0)) (INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q1 SLICE_81/C1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q1 SLICE_81/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_86/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_86/C0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q0 SLICE_74/B1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q0 SLICE_81/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_86/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_86/B0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_3/FCO SLICE_2/FCI (0:0:0)(0:0:0)) (INTERCONNECT SLICE_3/Q1 SLICE_3/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q1 SLICE_81/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q1 SLICE_81/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_67/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_69/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_80/B0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_3/Q0 SLICE_3/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q0 SLICE_72/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q0 SLICE_81/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_86/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_86/A0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_4/FCO SLICE_3/FCI (0:0:0)(0:0:0)) (INTERCONNECT SLICE_4/Q1 SLICE_4/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q1 SLICE_56/B1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_4/Q1 SLICE_64/B1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/Q1 SLICE_72/C0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/Q1 SLICE_74/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/Q1 SLICE_84/D1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/Q1 SLICE_87/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q1 SLICE_69/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q1 SLICE_80/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q1 SLICE_94/D1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_4/Q0 SLICE_4/A0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_4/Q0 SLICE_64/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/Q0 SLICE_74/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/Q0 SLICE_84/C1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/Q0 SLICE_84/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q0 SLICE_80/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q0 SLICE_89/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q0 SLICE_94/C1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_5/FCO SLICE_4/FCI (0:0:0)(0:0:0)) (INTERCONNECT SLICE_5/Q1 SLICE_5/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_5/Q1 SLICE_56/C0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_5/Q1 SLICE_87/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_89/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_89/C0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_5/Q0 SLICE_5/A0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_5/Q0 SLICE_58/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_5/Q0 SLICE_84/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q0 SLICE_94/B1 (0:0:0)(0:0:0)) (INTERCONNECT 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MAin\[7\]_I/PADDI SLICE_88/M1 (0:0:0)(0:0:0)) - (INTERCONNECT MAin\[7\]_I/PADDI SLICE_91/A1 (0:0:0)(0:0:0)) - (INTERCONNECT MAin\[6\]_I/PADDI SLICE_71/C1 (0:0:0)(0:0:0)) - (INTERCONNECT MAin\[6\]_I/PADDI SLICE_88/M0 (0:0:0)(0:0:0)) - (INTERCONNECT MAin\[6\]_I/PADDI SLICE_92/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_71/F1 SLICE_71/D0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_88/F1 SLICE_71/C0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_76/Q0 SLICE_71/B0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_71/Q1 SLICE_71/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_81/F1 SLICE_72/C1 (0:0:0)(0:0:0)) - (INTERCONNECT MAin\[3\]_I/PADDI SLICE_72/M1 (0:0:0)(0:0:0)) - (INTERCONNECT MAin\[3\]_I/PADDI SLICE_88/B1 (0:0:0)(0:0:0)) - (INTERCONNECT MAin\[3\]_I/PADDI SLICE_93/A0 (0:0:0)(0:0:0)) - (INTERCONNECT MAin\[2\]_I/PADDI SLICE_72/M0 (0:0:0)(0:0:0)) - (INTERCONNECT MAin\[2\]_I/PADDI SLICE_88/A1 (0:0:0)(0:0:0)) - (INTERCONNECT MAin\[2\]_I/PADDI SLICE_92/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_72/Q0 SLICE_92/B0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_72/Q1 SLICE_93/B0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_74/Q0 SLICE_87/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_75/Q0 SLICE_75/M1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_77/F1 SLICE_77/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_79/F1 SLICE_79/D0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_79/Q0 RD\[0\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_79/Q1 RD\[1\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_80/F1 SLICE_80/D0 (0:0:0)(0:0:0)) - (INTERCONNECT MAin\[9\]_I/PADDI SLICE_80/M1 (0:0:0)(0:0:0)) - (INTERCONNECT MAin\[9\]_I/PADDI SLICE_86/A1 (0:0:0)(0:0:0)) - (INTERCONNECT MAin\[9\]_I/PADDI SLICE_86/A0 (0:0:0)(0:0:0)) - (INTERCONNECT MAin\[9\]_I/PADDI SLICE_89/A1 (0:0:0)(0:0:0)) - (INTERCONNECT MAin\[8\]_I/PADDI SLICE_80/M0 (0:0:0)(0:0:0)) - (INTERCONNECT MAin\[8\]_I/PADDI SLICE_89/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_80/Q0 SLICE_89/B0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_80/Q1 SLICE_86/B0 (0:0:0)(0:0:0)) - (INTERCONNECT nFWE_I/PADDI SLICE_81/M0 (0:0:0)(0:0:0)) - (INTERCONNECT nFWE_I/PADDI SLICE_81/M1 (0:0:0)(0:0:0)) - (INTERCONNECT nFWE_I/PADDI SLICE_88/C1 (0:0:0)(0:0:0)) - (INTERCONNECT nFWE_I/PADDI SLICE_88/B0 (0:0:0)(0:0:0)) - (INTERCONNECT CROW\[1\]_I/PADDI SLICE_83/M1 (0:0:0)(0:0:0)) - (INTERCONNECT CROW\[0\]_I/PADDI SLICE_83/M0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_83/Q0 RBA\[0\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_83/Q1 RBA\[1\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_85/Q0 RD\[2\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_85/Q1 RD\[3\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_86/F0 RA\[9\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_86/F1 RDQML_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_88/F0 RD\[0\]_I/PADDT (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_88/F0 RD\[7\]_I/PADDT (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_88/F0 RD\[6\]_I/PADDT (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_88/F0 RD\[5\]_I/PADDT (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_88/F0 RD\[4\]_I/PADDT (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_88/F0 RD\[3\]_I/PADDT (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_88/F0 RD\[2\]_I/PADDT (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_88/F0 RD\[1\]_I/PADDT (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_88/Q0 SLICE_92/B1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_88/Q1 SLICE_91/B1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_89/F0 RA\[8\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_89/F1 RDQMH_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_90/F0 RA\[0\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_91/F0 RA\[1\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_91/F1 RA\[7\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_92/F0 RA\[2\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_92/F1 RA\[6\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_93/F0 RA\[3\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_93/F1 RA\[5\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_94/Q0 RA\[10\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 SLICE_78/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/F1 SLICE_74/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/F1 SLICE_78/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_74/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_75/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_78/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_79/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_82/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_83/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_85/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/Q0 SLICE_77/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/Q1 SLICE_77/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_76/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_81/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_89/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_93/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_98/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/F1 SLICE_76/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/Q0 SLICE_100/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/Q1 SLICE_100/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93/Q1 SLICE_77/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/Q0 SLICE_77/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/F1 SLICE_77/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/F1 SLICE_79/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F0 SLICE_77/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F0 SLICE_79/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/F0 SLICE_77/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/F0 SLICE_78/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_79/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_81/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_89/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_99/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F1 SLICE_79/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F1 SLICE_81/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/Q1 SLICE_100/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/F1 SLICE_81/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/F1 SLICE_82/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/Q0 RD\[2\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/Q1 RD\[3\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_83/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_91/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_91/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_96/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[8\]_I/PADDI SLICE_83/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[8\]_I/PADDI SLICE_96/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/Q0 SLICE_96/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/Q1 SLICE_91/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/Q0 RD\[0\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/Q1 RD\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F1 SLICE_85/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F1 SLICE_88/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/Q0 SLICE_98/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/Q1 SLICE_99/B0 (0:0:0)(0:0:0)) + (INTERCONNECT CROW\[1\]_I/PADDI SLICE_90/M1 (0:0:0)(0:0:0)) + (INTERCONNECT CROW\[0\]_I/PADDI SLICE_90/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/Q0 RBA\[0\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/Q1 RBA\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/F0 RA\[9\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/F1 RDQMH_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93/Q0 SLICE_100/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93/F1 RA\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96/F0 RA\[8\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96/F1 RDQML_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97/F0 RA\[3\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97/F1 RA\[0\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/F0 RA\[4\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/F1 RA\[2\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99/F0 RA\[5\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99/F1 RA\[7\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F1 RD\[0\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F1 RD\[7\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F1 RD\[6\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F1 RD\[5\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F1 RD\[4\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F1 RD\[3\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F1 RD\[2\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F1 RD\[1\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/F1 RA\[6\]_I/PADDO (0:0:0)(0:0:0)) (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_I/PADDO (0:0:0)(0:0:0)) (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_I/PADDO (0:0:0)(0:0:0)) (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_I/PADDO (0:0:0)(0:0:0)) diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvo.vo b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvo.vo index fa6e92e..a4f7b55 100644 --- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvo.vo +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvo.vo @@ -2,8 +2,8 @@ // Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454 // ldbanno -n Verilog -o RAM2GS_LCMXO640C_impl1_mapvo.vo -w -neg -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd -// Netlist created on Thu Sep 21 05:38:31 2023 -// Netlist written on Thu Sep 21 05:38:32 2023 +// Netlist created on Sat Jan 06 06:25:09 2024 +// Netlist written on Sat Jan 06 06:25:11 2024 // Design is for device LCMXO640C // Design is for package TQFP100 // Design is for performance grade 3 @@ -28,45 +28,48 @@ module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, \FS_cry[15] , \FS[15] , \FS[14] , \FS_cry[13] , \FS[13] , \FS[12] , \FS_cry[11] , \FS[11] , \FS[10] , \FS_cry[9] , \FS[9] , \FS[8] , \FS_cry[7] , \FS[7] , \FS[6] , \FS_cry[5] , \FS[5] , \FS[4] , - \FS_cry[3] , \FS[3] , \FS[2] , N_147, \MAin_c[0] , CmdEnable17_0_a2_4, - CmdEnable17_0_a2_3, CmdEnable16, CmdEnable17, C1WR_0_a2, ADSubmitted, - ADSubmitted_r, PHI2_c, CmdEnable16_0_a2_5, CmdEnable16_0_a2_4, - \MAin_c[1] , C1Submitted, C1Submitted_RNO, \S[1] , RASr2, \IS[3] , - CO0, N_177_i, Ready_0_sqmuxa_0_a3_2, CmdEnable, un1_CMDWR, - CmdEnable_s, N_128, \Din_c[5] , \Din_c[3] , N_152, N_133, N_132, - LEDEN, N_21_i, XOR8MEG18, CmdLEDEN, PHI2r3, PHI2r2, InitReady, - CmdSubmitted, CmdSubmitted_1_sqmuxa, N_460_0, N_136, N_43, Cmdn8MEGEN, - CmdEnable16_4, n8MEGEN, Cmdn8MEGEN_4_u_i_0, N_19_i, nRRAS_5_u_i_0, - N_160, N_155, \IS[0] , Ready, N_64_i_i, N_24, \IS[2] , \IS[1] , - N_60_i_i, N_56_i, N_159_i, N_159, N_61_i_i, RA10s_i, - UFMSDI_ens2_i_a2_4_2, N_126, N_51, InitReady3, N_461_0, - UFMSDI_ens2_i_a0, nCRAS_c, CBR, UFMSDO_c, N_70, N_33, LED_c, - un1_Din_4, XOR8MEG, \Din_c[6] , RA11_2, Ready_fast, \RA_c[11] , N_171, - FWEr_fast, CASr2, RCKEEN_8_u_1, RCKEEN_8_u_0_0, RCKEEN_8, PHI2r, - RCKEEN, RASr3, RASr, RCKE_2, RCKE_c, m18_0_a3_3, \S_0_i_o2[1] , N_165, - N_462_0, Ready_0_sqmuxa, N_463_0, nRRAS_0_sqmuxa, N_129, - UFMCLK_r_i_a2_2_2, CmdUFMCLK, UFMCLK_r_i_m4_xx_mm_1, UFMCLK_c, - nUFMCS15, N_139_i, UFMCLK_RNO, UFMSDI_r_xx_mm_1, UFMSDI_c, UFMSDI_RNO, - nRowColSel, \RowA[4] , \MAin_c[4] , \Din_c[4] , nCCAS_c, \RA_c[4] , - \WRD[4] , \WRD[5] , \Bank[7] , \Bank[6] , \Bank[5] , \Bank[2] , - \Din_c[7] , \WRD[6] , C1WR_0_a2_0_11, \WRD[7] , \Din_c[2] , - \Din_c[0] , XOR8MEG_3_u_0_a3_2, \Din_c[1] , XOR8MEG_3, N_69, N_31, - N_151, g0_1, nRCAS_0_sqmuxa_1, N_41, N_37_i, nRCAS_c, CASr3, - RCKEEN_8_u_0_a2_1_out, N_28_i_1, N_28_i, nRCS_c, N_24_i, nRRAS_c, - CBR_fast, m18_0_a2_1, G_17_1, FWEr, N_39_i, nRWE_c, N_179, - nRowColSel_0_0, nUFMCS_s_0_N_5_i_N_2L1, nUFMCS_c, nUFMCS_s_0_N_5_i, - CmdUFMCS, N_95_5, N_95_3, \RowA[0] , \RowA[1] , \MAin_c[5] , - CmdUFMCLK_1_sqmuxa, \RowA[5] , un1_FS_14_i_a2_0_1, N_137_8, N_137_6, - un1_FS_13_i_a2_1, C1WR_0_a2_0_10, \Bank[1] , \Bank[0] , \MAin_c[7] , - \MAin_c[6] , C1WR_0_a2_0_4, C1WR_0_a2_0_3, \Bank[4] , \Bank[3] , - UFMSDI_ens2_i_o2_0_3, \MAin_c[3] , \MAin_c[2] , \RowA[2] , \RowA[3] , - CmdUFMSDI, CASr, CmdEnable16_1, m6_0_a2_2, \WRD[0] , \WRD[1] , - g4_0_0_0, \MAin_c[9] , \MAin_c[8] , \RowA[8] , \RowA[9] , nFWE_c, - \CROW_c[1] , \CROW_c[0] , \RBA_c[0] , \RBA_c[1] , \WRD[2] , \WRD[3] , - \RA_c[9] , RDQML_c, RD_1_i, \RowA[6] , \RowA[7] , \RA_c[8] , RDQMH_c, - \RA_c[0] , \RA_c[1] , \RA_c[7] , \RA_c[2] , \RA_c[6] , \RA_c[3] , - \RA_c[5] , \RA_c[10] , \RD_in[0] , \RD_in[7] , \RD_in[6] , \RD_in[5] , - \RD_in[4] , \RD_in[3] , \RD_in[2] , \RD_in[1] , VCCI, GNDI_TSALL; + \FS_cry[3] , \FS[3] , \FS[2] , C1WR, ADWR, CmdEnable16, CmdEnable17, + N_183_i, ADSubmitted, ADSubmitted_r, PHI2_c, un1_CmdEnable20_0_a3_0_2, + N_121, C1Submitted, C1Submitted_RNO, un1_CmdEnable20_i, + CmdEnable16_0_a3_4, CmdEnable16_0_a3_5, CmdEnable_0_sqmuxa, CmdEnable, + CmdEnable_s, N_45, \Din_c[1] , CmdLEDEN_4_u_i_a2_0_0, CmdLEDEN, N_95, + LEDEN, CmdLEDEN_4_u_i_0, N_14_i, XOR8MEG18, PHI2r3, PHI2r2, InitReady, + CmdSubmitted, CmdSubmitted_1_sqmuxa, N_428_0, N_134, \Din_c[0] , + Cmdn8MEGEN, n8MEGEN, Cmdn8MEGEN_4_u_i_0, N_12_i, \IS[2] , \IS[1] , + \IS[0] , Ready, N_148, N_77_i_i, CASr2, N_160, CASr3, N_74_i_i, + N_69_i, N_153_i, \IS[3] , N_75_i_i, RA10s_i, UFMSDI_ens2_i_a2_4_2, + N_128, N_34, InitReady3, N_429_0, UFMSDI_ens2_i_a0, nCRAS_c, CBR, + UFMSDO_c, N_49, N_26, LED_c, N_151, \RA_c[10] , g3, \Din_c[7] , + \Din_c[6] , \Din_c[4] , XOR8MEG, RA11_2, Ready_fast, \RA_c[11] , N_36, + RCKEEN_8_u_0_a3_0_0, FWEr_fast, \S[1] , CO0, RCKEEN_8_u_0_1_1, + RCKEEN_8_u_0_0, RCKEEN_8, PHI2r, RCKEEN, RCKE_c, RASr2, RASr3, RASr, + RCKE_2, g0_i_a5_1, \S_0_i_o2[1] , Ready_0_sqmuxa_0_a3_2, N_430_0, + Ready_0_sqmuxa, N_431_0, nRRAS_0_sqmuxa, N_129, UFMCLK_r_i_a2_2_2, + CmdUFMCLK, UFMCLK_r_i_m4_xx_mm_1, UFMCLK_c, nUFMCS15, N_137_i, + UFMCLK_RNO, UFMSDI_r_xx_mm_1, UFMSDI_c, UFMSDI_RNO, N_94, CmdUFMSDI, + \Din_c[5] , nCCAS_c, \WRD[4] , \WRD[5] , FWEr, N_125, \WRD[6] , N_43, + \WRD[7] , N_163, XOR8MEG_3_u_0_a3_0_1, N_166, XOR8MEG_3, N_48, N_24, + un1_nRCAS_6_sqmuxa_i_0, nRCAS_0_sqmuxa_1, G_1_1, G_1_0, N_46_i, + nRCAS_c, CBR_fast, g0_i_a5_1_2, g0_i_0, N_184, N_143_i, nRCS_c, + nRRAS_5_u_i_0, N_154, N_142_i, nRRAS_c, m18_0_a2_1, G_17_1, N_144_i, + nRWE_c, N_112, nRowColSel_0_0, nRowColSel, nUFMCS_s_0_N_5_i_N_2L1, + nUFMCS_c, nUFMCS_s_0_N_5_i, m18_0_a3_3, CmdUFMCS, N_133_5, N_133_3, + \MAin_c[3] , \MAin_c[2] , \RowA[2] , \RowA[3] , g0_i_a5_2_1, N_9, + RCKEEN_8_u_0_1_a1_0, UFMSDI_ens2_i_o2_0_3, \MAin_c[1] , \MAin_c[0] , + \RowA[0] , \RowA[1] , nFWE_c, CMDWR_2, C1WR_7, CMDWR, + un1_FS_13_i_a2_9_5, un1_FS_13_i_a2_9_4, un1_FS_14_i_a2_0_1, + un1_FS_13_i_a2_1, \Din_c[3] , \MAin_c[7] , \MAin_c[6] , \RowA[6] , + \RowA[7] , N_180, N_156, N_122_5, CASr, \Din_c[2] , \Bank[6] , + \Bank[7] , \MAin_c[4] , C1WR_2_0, \Bank[0] , \Bank[1] , \Bank[5] , + \Bank[2] , un1_Bank_1_5, un1_Bank_1_4, ADWR_8, \MAin_c[5] , ADWR_8_2, + \Bank[3] , ADWR_8_4, m6_0_a2_2, \WRD[2] , \WRD[3] , \MAin_c[9] , + \MAin_c[8] , \RowA[8] , \RowA[9] , \WRD[0] , \WRD[1] , + CmdUFMCLK_1_sqmuxa, \RowA[4] , \RowA[5] , \CROW_c[1] , \CROW_c[0] , + \RBA_c[0] , \RBA_c[1] , \RA_c[9] , RDQMH_c, \Bank[4] , \RA_c[1] , + \RA_c[8] , RDQML_c, \RA_c[3] , \RA_c[0] , \RA_c[4] , \RA_c[2] , + \RA_c[5] , \RA_c[7] , RD_1_i, \RA_c[6] , \RD_in[0] , \RD_in[7] , + \RD_in[6] , \RD_in[5] , \RD_in[4] , \RD_in[3] , \RD_in[2] , + \RD_in[1] , VCCI, GNDI_TSALL; SLICE_0 SLICE_0( .A1(\FS[1] ), .A0(\FS[0] ), .CLK(RCLK_c), .Q0(\FS[0] ), .Q1(\FS[1] ), .FCO(\FS_cry[1] )); @@ -86,213 +89,231 @@ module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, .Q0(\FS[4] ), .Q1(\FS[5] ), .FCO(\FS_cry[5] )); SLICE_8 SLICE_8( .A1(\FS[3] ), .A0(\FS[2] ), .CLK(RCLK_c), .FCI(\FS_cry[1] ), .Q0(\FS[2] ), .Q1(\FS[3] ), .FCO(\FS_cry[3] )); - SLICE_9 SLICE_9( .D1(N_147), .C1(\MAin_c[0] ), .B1(CmdEnable17_0_a2_4), - .A1(CmdEnable17_0_a2_3), .D0(CmdEnable16), .C0(CmdEnable17), - .B0(C1WR_0_a2), .A0(ADSubmitted), .DI0(ADSubmitted_r), .CLK(PHI2_c), - .F0(ADSubmitted_r), .Q0(ADSubmitted), .F1(CmdEnable17)); - SLICE_14 SLICE_14( .C1(N_147), .B1(CmdEnable16_0_a2_5), - .A1(CmdEnable16_0_a2_4), .D0(\MAin_c[1] ), .C0(N_147), .B0(C1Submitted), + SLICE_9 SLICE_9( .B1(C1WR), .A1(ADWR), .D0(CmdEnable16), .C0(CmdEnable17), + .B0(N_183_i), .A0(ADSubmitted), .DI0(ADSubmitted_r), .CLK(PHI2_c), + .F0(ADSubmitted_r), .Q0(ADSubmitted), .F1(N_183_i)); + SLICE_14 SLICE_14( .D1(un1_CmdEnable20_0_a3_0_2), .C1(N_121), + .B1(CmdEnable16), .A1(C1Submitted), .D0(ADWR), .C0(C1WR), .B0(C1Submitted), .A0(CmdEnable16), .DI0(C1Submitted_RNO), .CLK(PHI2_c), - .F0(C1Submitted_RNO), .Q0(C1Submitted), .F1(CmdEnable16)); - SLICE_19 SLICE_19( .D1(\S[1] ), .C1(RASr2), .B1(\IS[3] ), .A1(CO0), - .B0(\S[1] ), .A0(CO0), .DI0(N_177_i), .LSR(RASr2), .CLK(RCLK_c), - .F0(N_177_i), .Q0(CO0), .F1(Ready_0_sqmuxa_0_a3_2)); - SLICE_20 SLICE_20( .B1(ADSubmitted), .A1(CmdEnable), .D0(C1Submitted), - .C0(un1_CMDWR), .B0(CmdEnable), .A0(CmdEnable17), .DI0(CmdEnable_s), - .M0(CmdEnable16), .CLK(PHI2_c), .OFX0(CmdEnable_s), .Q0(CmdEnable)); - SLICE_21 SLICE_21( .C1(N_128), .B1(\Din_c[5] ), .A1(\Din_c[3] ), .D0(N_152), - .C0(N_133), .B0(N_132), .A0(LEDEN), .DI0(N_21_i), .CE(XOR8MEG18), - .CLK(PHI2_c), .F0(N_21_i), .Q0(CmdLEDEN), .F1(N_152)); + .F0(C1Submitted_RNO), .Q0(C1Submitted), .F1(un1_CmdEnable20_i)); + SLICE_20 SLICE_20( .D1(C1WR), .C1(CmdEnable16_0_a3_4), + .B1(CmdEnable16_0_a3_5), .A1(ADSubmitted), .D0(CmdEnable_0_sqmuxa), + .C0(un1_CmdEnable20_i), .B0(CmdEnable17), .A0(CmdEnable), + .DI0(CmdEnable_s), .CLK(PHI2_c), .F0(CmdEnable_s), .Q0(CmdEnable), + .F1(CmdEnable_0_sqmuxa)); + SLICE_21 SLICE_21( .D1(N_45), .C1(\Din_c[1] ), .B1(CmdLEDEN_4_u_i_a2_0_0), + .A1(CmdLEDEN), .C0(N_95), .B0(LEDEN), .A0(CmdLEDEN_4_u_i_0), .DI0(N_14_i), + .CE(XOR8MEG18), .CLK(PHI2_c), .F0(N_14_i), .Q0(CmdLEDEN), + .F1(CmdLEDEN_4_u_i_0)); SLICE_22 SLICE_22( .D1(PHI2r3), .C1(PHI2r2), .B1(InitReady), .A1(CmdSubmitted), .B0(CmdSubmitted), .A0(CmdSubmitted_1_sqmuxa), - .DI0(N_460_0), .CLK(PHI2_c), .F0(N_460_0), .Q0(CmdSubmitted), .F1(N_136)); - SLICE_26 SLICE_26( .D1(N_128), .C1(N_43), .B1(Cmdn8MEGEN), - .A1(CmdEnable16_4), .C0(n8MEGEN), .B0(N_152), .A0(Cmdn8MEGEN_4_u_i_0), - .DI0(N_19_i), .CE(XOR8MEG18), .CLK(PHI2_c), .F0(N_19_i), .Q0(Cmdn8MEGEN), - .F1(Cmdn8MEGEN_4_u_i_0)); - SLICE_29 SLICE_29( .D1(nRRAS_5_u_i_0), .C1(N_160), .B1(N_155), .A1(\IS[0] ), - .C0(N_155), .B0(Ready), .A0(\IS[0] ), .DI0(N_64_i_i), .CLK(RCLK_c), - .F0(N_64_i_i), .Q0(\IS[0] ), .F1(N_24)); + .DI0(N_428_0), .CLK(PHI2_c), .F0(N_428_0), .Q0(CmdSubmitted), .F1(N_134)); + SLICE_26 SLICE_26( .D1(N_45), .C1(\Din_c[0] ), .B1(Cmdn8MEGEN), + .A1(CmdLEDEN_4_u_i_a2_0_0), .C0(n8MEGEN), .B0(N_95), + .A0(Cmdn8MEGEN_4_u_i_0), .DI0(N_12_i), .CE(XOR8MEG18), .CLK(PHI2_c), + .F0(N_12_i), .Q0(Cmdn8MEGEN), .F1(Cmdn8MEGEN_4_u_i_0)); + SLICE_29 SLICE_29( .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), .C0(Ready), + .B0(N_148), .A0(\IS[0] ), .DI0(N_77_i_i), .M1(CASr2), .CLK(RCLK_c), + .F0(N_77_i_i), .Q0(\IS[0] ), .F1(N_160), .Q1(CASr3)); SLICE_30 SLICE_30( .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), .B0(\IS[1] ), - .A0(\IS[0] ), .DI1(N_60_i_i), .DI0(N_56_i), .CE(N_159_i), .CLK(RCLK_c), - .F0(N_56_i), .Q0(\IS[1] ), .F1(N_60_i_i), .Q1(\IS[2] )); - SLICE_31 SLICE_31( .D1(N_159), .C1(\IS[3] ), .B1(\IS[2] ), .A1(\IS[1] ), - .D0(\IS[0] ), .C0(\IS[1] ), .B0(\IS[2] ), .A0(\IS[3] ), .DI0(N_61_i_i), - .CE(N_159_i), .CLK(RCLK_c), .F0(N_61_i_i), .Q0(\IS[3] ), .F1(RA10s_i)); - SLICE_32 SLICE_32( .D1(UFMSDI_ens2_i_a2_4_2), .C1(N_126), .B1(N_51), - .A1(InitReady), .B0(InitReady), .A0(InitReady3), .DI0(N_461_0), - .CLK(RCLK_c), .F0(N_461_0), .Q0(InitReady), .F1(UFMSDI_ens2_i_a0)); - SLICE_33 SLICE_33( .C1(nCRAS_c), .B1(LEDEN), .A1(CBR), .C0(UFMSDO_c), - .B0(InitReady), .A0(CmdLEDEN), .DI0(N_70), .CE(N_33), .CLK(RCLK_c), - .F0(N_70), .Q0(LEDEN), .F1(LED_c)); - SLICE_39 SLICE_39( .B1(un1_Din_4), .A1(XOR8MEG), .C0(n8MEGEN), .B0(XOR8MEG), - .A0(\Din_c[6] ), .DI0(RA11_2), .LSR(Ready_fast), .CLK(PHI2_c), .F0(RA11_2), - .Q0(\RA_c[11] ), .F1(N_171)); - SLICE_41 SLICE_41( .D1(\S[1] ), .C1(FWEr_fast), .B1(CO0), .A1(CASr2), - .D0(Ready), .C0(RCKEEN_8_u_1), .B0(RCKEEN_8_u_0_0), .A0(CBR), + .A0(\IS[0] ), .DI1(N_74_i_i), .DI0(N_69_i), .CE(N_153_i), .CLK(RCLK_c), + .F0(N_69_i), .Q0(\IS[1] ), .F1(N_74_i_i), .Q1(\IS[2] )); + SLICE_31 SLICE_31( .D1(Ready), .C1(N_148), .B1(\IS[3] ), .A1(\IS[0] ), + .D0(\IS[0] ), .C0(\IS[1] ), .B0(\IS[2] ), .A0(\IS[3] ), .DI0(N_75_i_i), + .CE(N_153_i), .CLK(RCLK_c), .F0(N_75_i_i), .Q0(\IS[3] ), .F1(RA10s_i)); + SLICE_32 SLICE_32( .D1(UFMSDI_ens2_i_a2_4_2), .C1(N_128), .B1(N_34), + .A1(InitReady), .B0(InitReady), .A0(InitReady3), .DI0(N_429_0), + .CLK(RCLK_c), .F0(N_429_0), .Q0(InitReady), .F1(UFMSDI_ens2_i_a0)); + SLICE_33 SLICE_33( .D1(nCRAS_c), .C1(Ready), .B1(LEDEN), .A1(CBR), + .C0(UFMSDO_c), .B0(InitReady), .A0(CmdLEDEN), .DI0(N_49), .CE(N_26), + .CLK(RCLK_c), .F0(N_49), .Q0(LEDEN), .F1(LED_c)); + SLICE_38 SLICE_38( .D1(\IS[3] ), .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), + .B0(\IS[2] ), .A0(\IS[1] ), .DI0(N_151), .LSR(RA10s_i), .CLK(RCLK_c), + .F0(N_151), .Q0(\RA_c[10] ), .F1(g3)); + SLICE_39 SLICE_39( .C1(\Din_c[7] ), .B1(\Din_c[6] ), .A1(\Din_c[4] ), + .C0(n8MEGEN), .B0(XOR8MEG), .A0(\Din_c[6] ), .DI0(RA11_2), + .LSR(Ready_fast), .CLK(PHI2_c), .F0(RA11_2), .Q0(\RA_c[11] ), .F1(N_36)); + SLICE_41 SLICE_41( .D1(RCKEEN_8_u_0_a3_0_0), .C1(FWEr_fast), .B1(\S[1] ), + .A1(CO0), .D0(Ready), .C0(RCKEEN_8_u_0_1_1), .B0(RCKEEN_8_u_0_0), .A0(CBR), .DI0(RCKEEN_8), .M1(PHI2r), .CLK(RCLK_c), .F0(RCKEEN_8), .Q0(RCKEEN), - .F1(RCKEEN_8_u_1), .Q1(PHI2r2)); - SLICE_42 SLICE_42( .D1(RASr2), .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), - .D0(RCKEEN), .C0(RASr3), .B0(RASr2), .A0(RASr), .DI0(RCKE_2), .M1(PHI2_c), - .CLK(RCLK_c), .F0(RCKE_2), .Q0(RCKE_c), .F1(m18_0_a3_3), .Q1(PHI2r)); + .F1(RCKEEN_8_u_0_1_1), .Q1(PHI2r2)); + SLICE_42 SLICE_42( .C1(Ready), .B1(RCKE_c), .A1(RASr2), .D0(RCKEEN), + .C0(RASr3), .B0(RASr2), .A0(RASr), .DI0(RCKE_2), .M1(PHI2_c), .CLK(RCLK_c), + .F0(RCKE_2), .Q0(RCKE_c), .F1(g0_i_a5_1), .Q1(PHI2r)); SLICE_43 SLICE_43( .D1(\S_0_i_o2[1] ), .C1(InitReady), .B1(RASr2), - .A1(Ready), .D0(InitReady), .C0(N_165), .B0(Ready_0_sqmuxa_0_a3_2), - .A0(Ready), .DI0(N_462_0), .M1(PHI2r2), .CLK(RCLK_c), .F0(N_462_0), + .A1(Ready), .D0(InitReady), .C0(N_160), .B0(Ready_0_sqmuxa_0_a3_2), + .A0(Ready), .DI0(N_430_0), .M1(PHI2r2), .CLK(RCLK_c), .F0(N_430_0), .Q0(Ready), .F1(RCKEEN_8_u_0_0), .Q1(PHI2r3)); - SLICE_44 SLICE_44( .D1(Ready_0_sqmuxa_0_a3_2), .C1(Ready), .B1(N_165), - .A1(InitReady), .B0(Ready_fast), .A0(Ready_0_sqmuxa), .DI0(N_463_0), - .M1(nCRAS_c), .CLK(RCLK_c), .F0(N_463_0), .Q0(Ready_fast), - .F1(Ready_0_sqmuxa), .Q1(RASr)); + SLICE_44 SLICE_44( .D1(Ready_0_sqmuxa_0_a3_2), .C1(Ready), .B1(N_160), + .A1(InitReady), .B0(Ready_fast), .A0(Ready_0_sqmuxa), .DI0(N_431_0), + .M1(RASr2), .CLK(RCLK_c), .F0(N_431_0), .Q0(Ready_fast), + .F1(Ready_0_sqmuxa), .Q1(RASr3)); SLICE_50 SLICE_50( .C1(CO0), .B1(\S[1] ), .A1(Ready), .B0(\S[1] ), .A0(CO0), .DI0(\S_0_i_o2[1] ), .LSR(RASr2), .CLK(RCLK_c), .F0(\S_0_i_o2[1] ), .Q0(\S[1] ), .F1(nRRAS_0_sqmuxa)); SLICE_51 SLICE_51( .D1(N_129), .C1(UFMCLK_r_i_a2_2_2), .B1(CmdUFMCLK), .A1(InitReady), .D0(UFMCLK_r_i_m4_xx_mm_1), .C0(UFMCLK_c), .B0(nUFMCS15), - .A0(N_139_i), .DI0(UFMCLK_RNO), .M1(RASr), .CLK(RCLK_c), .F0(UFMCLK_RNO), - .Q0(UFMCLK_c), .F1(UFMCLK_r_i_m4_xx_mm_1), .Q1(RASr2)); + .A0(N_137_i), .DI0(UFMCLK_RNO), .CLK(RCLK_c), .F0(UFMCLK_RNO), + .Q0(UFMCLK_c), .F1(UFMCLK_r_i_m4_xx_mm_1)); SLICE_52 SLICE_52( .D1(PHI2r3), .C1(PHI2r2), .B1(InitReady), .A1(CmdSubmitted), .D0(UFMSDI_r_xx_mm_1), .C0(UFMSDI_c), .B0(nUFMCS15), - .A0(N_139_i), .DI0(UFMSDI_RNO), .M1(RASr2), .CLK(RCLK_c), .F0(UFMSDI_RNO), - .Q0(UFMSDI_c), .F1(N_139_i), .Q1(RASr3)); - SLICE_55 SLICE_55( .C0(nRowColSel), .B0(\RowA[4] ), .A0(\MAin_c[4] ), - .M1(\Din_c[5] ), .M0(\Din_c[4] ), .CLK(nCCAS_c), .F0(\RA_c[4] ), + .A0(N_137_i), .DI0(UFMSDI_RNO), .CLK(RCLK_c), .F0(UFMSDI_RNO), + .Q0(UFMSDI_c), .F1(N_137_i)); + SLICE_55 SLICE_55( .C0(N_94), .B0(UFMSDI_ens2_i_a0), .A0(CmdUFMSDI), + .M1(\Din_c[5] ), .M0(\Din_c[4] ), .CLK(nCCAS_c), .F0(UFMSDI_r_xx_mm_1), .Q0(\WRD[4] ), .Q1(\WRD[5] )); - SLICE_56 SLICE_56( .D1(\Bank[7] ), .C1(\Bank[6] ), .B1(\Bank[5] ), - .A1(\Bank[2] ), .C0(\FS[9] ), .B0(\FS[7] ), .A0(\FS[5] ), .M1(\Din_c[7] ), - .M0(\Din_c[6] ), .CLK(nCCAS_c), .F0(N_126), .Q0(\WRD[6] ), - .F1(C1WR_0_a2_0_11), .Q1(\WRD[7] )); - SLICE_57 SLICE_57( .D1(un1_Din_4), .C1(\Din_c[3] ), .B1(\Din_c[2] ), - .A1(\Din_c[0] ), .D0(XOR8MEG_3_u_0_a3_2), .C0(N_171), .B0(LEDEN), - .A0(\Din_c[1] ), .DI0(XOR8MEG_3), .CE(XOR8MEG18), .CLK(PHI2_c), - .F0(XOR8MEG_3), .Q0(XOR8MEG), .F1(XOR8MEG_3_u_0_a3_2)); - SLICE_58 SLICE_58( .C1(N_51), .B1(InitReady), .A1(\FS[8] ), .C0(UFMSDO_c), - .B0(InitReady), .A0(Cmdn8MEGEN), .DI0(N_69), .CE(N_31), .CLK(RCLK_c), - .F0(N_69), .Q0(n8MEGEN), .F1(N_151)); - SLICE_59 SLICE_59( .D1(\S[1] ), .C1(Ready), .B1(N_160), .A1(N_155), - .D0(g0_1), .C0(\S[1] ), .B0(nRCAS_0_sqmuxa_1), .A0(N_41), .DI0(N_37_i), - .CLK(RCLK_c), .F0(N_37_i), .Q0(nRCAS_c), .F1(N_41)); - SLICE_60 SLICE_60( .D1(CASr2), .C1(CASr3), .B1(CO0), .A1(FWEr_fast), - .D0(RCKEEN_8_u_0_a2_1_out), .C0(N_28_i_1), .B0(N_24), .A0(CBR), - .DI0(N_28_i), .CLK(RCLK_c), .F0(N_28_i), .Q0(nRCS_c), .F1(N_28_i_1)); + SLICE_56 SLICE_56( .B1(\FS[11] ), .A1(\FS[4] ), .B0(FWEr), .A0(CO0), + .M1(\Din_c[7] ), .M0(\Din_c[6] ), .CLK(nCCAS_c), .F0(N_125), .Q0(\WRD[6] ), + .F1(N_43), .Q1(\WRD[7] )); + SLICE_57 SLICE_57( .B1(XOR8MEG), .A1(N_163), .D0(XOR8MEG_3_u_0_a3_0_1), + .C0(N_166), .B0(LEDEN), .A0(\Din_c[1] ), .DI0(XOR8MEG_3), .CE(XOR8MEG18), + .CLK(PHI2_c), .F0(XOR8MEG_3), .Q0(XOR8MEG), .F1(N_166)); + SLICE_58 SLICE_58( .C1(N_128), .B1(InitReady), .A1(\FS[8] ), .C0(UFMSDO_c), + .B0(InitReady), .A0(Cmdn8MEGEN), .DI0(N_48), .CE(N_24), .CLK(RCLK_c), + .F0(N_48), .Q0(n8MEGEN), .F1(N_94)); + SLICE_59 SLICE_59( .C1(\S[1] ), .B1(un1_nRCAS_6_sqmuxa_i_0), .A1(CBR), + .D0(\S[1] ), .C0(nRCAS_0_sqmuxa_1), .B0(G_1_1), .A0(G_1_0), .DI0(N_46_i), + .CLK(RCLK_c), .F0(N_46_i), .Q0(nRCAS_c), .F1(G_1_1)); + SLICE_60 SLICE_60( .C1(\S[1] ), .B1(Ready), .A1(CBR_fast), .D0(g0_i_a5_1_2), + .C0(g0_i_0), .B0(N_184), .A0(N_125), .DI0(N_143_i), .CLK(RCLK_c), + .F0(N_143_i), .Q0(nRCS_c), .F1(N_184)); SLICE_61 SLICE_61( .D1(Ready), .C1(RCKE_c), .B1(RASr2), .A1(\S_0_i_o2[1] ), - .D0(\IS[0] ), .C0(N_155), .B0(N_160), .A0(nRRAS_5_u_i_0), .DI0(N_24_i), - .CLK(RCLK_c), .F0(N_24_i), .Q0(nRRAS_c), .F1(nRRAS_5_u_i_0)); + .D0(nRRAS_5_u_i_0), .C0(N_154), .B0(N_148), .A0(\IS[0] ), .DI0(N_142_i), + .CLK(RCLK_c), .F0(N_142_i), .Q0(nRRAS_c), .F1(nRRAS_5_u_i_0)); SLICE_62 SLICE_62( .D1(Ready), .C1(RASr2), .B1(\S_0_i_o2[1] ), .A1(CBR_fast), .D0(m18_0_a2_1), .C0(nRCAS_0_sqmuxa_1), .B0(G_17_1), .A0(FWEr), - .DI0(N_39_i), .CLK(RCLK_c), .F0(N_39_i), .Q0(nRWE_c), + .DI0(N_144_i), .CLK(RCLK_c), .F0(N_144_i), .Q0(nRWE_c), .F1(nRCAS_0_sqmuxa_1)); SLICE_63 SLICE_63( .D1(Ready), .C1(FWEr), .B1(CBR), .A1(CASr3), .D0(\S[1] ), - .C0(Ready), .B0(N_179), .A0(CO0), .DI0(nRowColSel_0_0), + .C0(Ready), .B0(N_112), .A0(CO0), .DI0(nRowColSel_0_0), .LSR(nRRAS_0_sqmuxa), .CLK(RCLK_c), .F0(nRowColSel_0_0), .Q0(nRowColSel), - .F1(N_179)); - SLICE_64 SLICE_64( .D1(N_51), .C1(InitReady), .B1(\FS[11] ), .A1(\FS[10] ), - .D0(nUFMCS_s_0_N_5_i_N_2L1), .C0(nUFMCS_c), .B0(nUFMCS15), .A0(N_139_i), + .F1(N_112)); + SLICE_64 SLICE_64( .D1(N_128), .C1(InitReady), .B1(\FS[11] ), .A1(\FS[10] ), + .D0(nUFMCS_s_0_N_5_i_N_2L1), .C0(nUFMCS_c), .B0(nUFMCS15), .A0(N_137_i), .DI0(nUFMCS_s_0_N_5_i), .CLK(RCLK_c), .F0(nUFMCS_s_0_N_5_i), .Q0(nUFMCS_c), .F1(nUFMCS15)); nRWE_RNO_1_SLICE_65 \nRWE_RNO_1/SLICE_65 ( .D1(RASr2), .C1(RCKE_c), .B1(CO0), .A1(\S[1] ), .D0(InitReady), .C0(m18_0_a3_3), .B0(CO0), .A0(\S[1] ), .M0(Ready), .OFX0(m18_0_a2_1)); - SLICE_66 SLICE_66( .C1(UFMCLK_r_i_a2_2_2), .B1(InitReady), .A1(CmdUFMCS), - .D0(N_95_5), .C0(N_95_3), .B0(InitReady), .A0(\FS[16] ), .M1(\MAin_c[1] ), - .M0(\MAin_c[0] ), .LSR(Ready_fast), .CLK(nCRAS_c), .F0(UFMCLK_r_i_a2_2_2), - .Q0(\RowA[0] ), .F1(nUFMCS_s_0_N_5_i_N_2L1), .Q1(\RowA[1] )); - SLICE_67 SLICE_67( .D1(\Din_c[3] ), .C1(\Din_c[5] ), .B1(N_128), - .A1(XOR8MEG18), .D0(N_147), .C0(\MAin_c[1] ), .B0(\MAin_c[0] ), - .A0(CmdEnable), .M1(\MAin_c[5] ), .M0(\MAin_c[4] ), .LSR(Ready_fast), - .CLK(nCRAS_c), .F0(XOR8MEG18), .Q0(\RowA[4] ), .F1(CmdUFMCLK_1_sqmuxa), - .Q1(\RowA[5] )); - SLICE_68 SLICE_68( .D1(\FS[5] ), .C1(\FS[3] ), .B1(\FS[2] ), .A1(\FS[0] ), - .D0(un1_FS_14_i_a2_0_1), .C0(N_137_8), .B0(N_137_6), .A0(N_136), .F0(N_31), - .F1(un1_FS_14_i_a2_0_1)); - SLICE_69 SLICE_69( .D1(\FS[5] ), .C1(\FS[3] ), .B1(\FS[2] ), .A1(\FS[0] ), - .D0(un1_FS_13_i_a2_1), .C0(N_137_8), .B0(N_137_6), .A0(N_136), .F0(N_33), - .F1(un1_FS_13_i_a2_1)); - SLICE_70 SLICE_70( .D1(C1WR_0_a2_0_11), .C1(C1WR_0_a2_0_10), .B1(\Bank[1] ), - .A1(\Bank[0] ), .B0(N_147), .A0(\MAin_c[1] ), .M1(\Din_c[1] ), - .M0(\Din_c[0] ), .CLK(PHI2_c), .F0(C1WR_0_a2), .Q0(\Bank[0] ), .F1(N_147), - .Q1(\Bank[1] )); - SLICE_71 SLICE_71( .D1(\MAin_c[7] ), .C1(\MAin_c[6] ), .B1(\MAin_c[5] ), - .A1(\MAin_c[4] ), .D0(C1WR_0_a2_0_4), .C0(C1WR_0_a2_0_3), .B0(\Bank[4] ), - .A0(\Bank[3] ), .M1(\Din_c[3] ), .M0(\Din_c[2] ), .CLK(PHI2_c), - .F0(C1WR_0_a2_0_10), .Q0(\Bank[2] ), .F1(C1WR_0_a2_0_4), .Q1(\Bank[3] )); - SLICE_72 SLICE_72( .C1(UFMSDI_ens2_i_o2_0_3), .B1(\FS[16] ), .A1(\FS[12] ), - .D0(N_51), .C0(\FS[11] ), .B0(\FS[4] ), .A0(\FS[1] ), .M1(\MAin_c[3] ), - .M0(\MAin_c[2] ), .LSR(Ready_fast), .CLK(nCRAS_c), .F0(N_129), - .Q0(\RowA[2] ), .F1(N_51), .Q1(\RowA[3] )); - SLICE_73 SLICE_73( .D1(CO0), .C1(\S[1] ), .B1(InitReady), .A1(RASr2), - .B0(Ready), .A0(N_155), .M1(\Din_c[2] ), .M0(\Din_c[1] ), - .CE(CmdUFMCLK_1_sqmuxa), .CLK(PHI2_c), .F0(N_159), .Q0(CmdUFMCLK), - .F1(N_155), .Q1(CmdUFMCS)); - SLICE_74 SLICE_74( .B1(\FS[14] ), .A1(\FS[11] ), .D0(N_95_5), .C0(N_95_3), - .B0(\FS[16] ), .A0(\FS[10] ), .M0(\Din_c[0] ), .CE(CmdUFMCLK_1_sqmuxa), - .CLK(PHI2_c), .F0(InitReady3), .Q0(CmdUFMSDI), .F1(N_95_3)); - SLICE_75 SLICE_75( .C1(\Din_c[7] ), .B1(\Din_c[6] ), .A1(\Din_c[4] ), - .C0(N_128), .B0(\Din_c[5] ), .A0(\Din_c[1] ), .M1(CASr), .M0(nCCAS_c), - .CLK(RCLK_c), .F0(N_133), .Q0(CASr), .F1(N_128), .Q1(CASr2)); - SLICE_76 SLICE_76( .B1(\Din_c[5] ), .A1(\Din_c[0] ), .D0(\MAin_c[0] ), - .C0(\Din_c[3] ), .B0(\Din_c[1] ), .A0(CmdEnable16_4), .M1(\Din_c[5] ), - .M0(\Din_c[4] ), .CLK(PHI2_c), .F0(CmdEnable16_0_a2_4), .Q0(\Bank[4] ), - .F1(CmdEnable16_4), .Q1(\Bank[5] )); - SLICE_77 SLICE_77( .B1(\Din_c[7] ), .A1(\Din_c[4] ), .D0(\MAin_c[1] ), - .C0(\Din_c[6] ), .B0(\Din_c[2] ), .A0(CmdEnable16_1), .M1(\Din_c[7] ), - .M0(\Din_c[6] ), .CLK(PHI2_c), .F0(CmdEnable16_0_a2_5), .Q0(\Bank[6] ), - .F1(CmdEnable16_1), .Q1(\Bank[7] )); - SLICE_78 SLICE_78( .B1(\Din_c[5] ), .A1(\Din_c[3] ), .D0(N_43), - .C0(\MAin_c[1] ), .B0(\Din_c[6] ), .A0(\Din_c[2] ), .M1(nCCAS_c), - .M0(nCCAS_c), .CLK(nCRAS_c), .F0(CmdEnable17_0_a2_4), .Q0(CBR), .F1(N_43), - .Q1(CBR_fast)); - SLICE_79 SLICE_79( .C1(Ready), .B1(CASr3), .A1(CASr2), .D0(m6_0_a2_2), - .C0(\S[1] ), .B0(CO0), .A0(CBR), .M1(\Din_c[1] ), .M0(\Din_c[0] ), - .CLK(nCCAS_c), .F0(G_17_1), .Q0(\WRD[0] ), .F1(m6_0_a2_2), .Q1(\WRD[1] )); - SLICE_80 SLICE_80( .B1(CASr3), .A1(CASr2), .D0(g4_0_0_0), .C0(FWEr), - .B0(CO0), .A0(CBR_fast), .M1(\MAin_c[9] ), .M0(\MAin_c[8] ), - .LSR(Ready_fast), .CLK(nCRAS_c), .F0(g0_1), .Q0(\RowA[8] ), .F1(g4_0_0_0), + SLICE_66 SLICE_66( .D1(CO0), .C1(\S[1] ), .B1(InitReady), .A1(RASr2), + .D0(\S[1] ), .C0(Ready), .B0(N_154), .A0(N_148), + .F0(un1_nRCAS_6_sqmuxa_i_0), .F1(N_148)); + SLICE_67 SLICE_67( .C1(UFMCLK_r_i_a2_2_2), .B1(InitReady), .A1(CmdUFMCS), + .D0(N_133_5), .C0(N_133_3), .B0(InitReady), .A0(\FS[13] ), + .M1(\MAin_c[3] ), .M0(\MAin_c[2] ), .LSR(Ready_fast), .CLK(nCRAS_c), + .F0(UFMCLK_r_i_a2_2_2), .Q0(\RowA[2] ), .F1(nUFMCS_s_0_N_5_i_N_2L1), + .Q1(\RowA[3] )); + SLICE_68 SLICE_68( .D1(g3), .C1(g0_i_a5_2_1), .B1(RASr2), .A1(CO0), + .D0(g0_i_a5_1), .C0(\S[1] ), .B0(N_9), .A0(CO0), .M0(RASr2), + .LSR(RCKEEN_8_u_0_1_a1_0), .CLK(RCLK_c), .F0(g0_i_0), .Q0(CO0), .F1(N_9)); + SLICE_69 SLICE_69( .C1(UFMSDI_ens2_i_o2_0_3), .B1(\FS[16] ), .A1(\FS[13] ), + .D0(\FS[4] ), .C0(\FS[11] ), .B0(\FS[1] ), .A0(N_128), .M1(\MAin_c[1] ), + .M0(\MAin_c[0] ), .LSR(Ready_fast), .CLK(nCRAS_c), .F0(N_129), + .Q0(\RowA[0] ), .F1(N_128), .Q1(\RowA[1] )); + SLICE_70 SLICE_70( .D1(nFWE_c), .C1(\MAin_c[0] ), .B1(CMDWR_2), .A1(C1WR_7), + .C0(CMDWR), .B0(C1WR), .A0(ADWR), .F0(N_121), .F1(CMDWR)); + SLICE_71 SLICE_71( .D1(un1_FS_13_i_a2_9_5), .C1(un1_FS_13_i_a2_9_4), + .B1(N_43), .A1(\FS[5] ), .C0(un1_FS_14_i_a2_0_1), .B0(N_134), .A0(N_94), + .F0(N_24), .F1(un1_FS_14_i_a2_0_1)); + SLICE_72 SLICE_72( .D1(un1_FS_13_i_a2_9_5), .C1(un1_FS_13_i_a2_9_4), + .B1(N_43), .A1(\FS[5] ), .C0(un1_FS_13_i_a2_1), .B0(N_134), .A0(N_94), + .F0(N_26), .F1(un1_FS_13_i_a2_1)); + SLICE_73 SLICE_73( .D1(\Din_c[3] ), .C1(\Din_c[5] ), .B1(N_36), + .A1(XOR8MEG18), .B0(CmdEnable), .A0(CMDWR), .M1(\MAin_c[7] ), + .M0(\MAin_c[6] ), .LSR(Ready_fast), .CLK(nCRAS_c), .F0(XOR8MEG18), + .Q0(\RowA[6] ), .F1(CmdSubmitted_1_sqmuxa), .Q1(\RowA[7] )); + SLICE_74 SLICE_74( .B1(\Din_c[6] ), .A1(\Din_c[4] ), .D0(N_180), .C0(N_156), + .B0(N_122_5), .A0(ADWR), .M1(CASr), .M0(nCCAS_c), .CLK(RCLK_c), + .F0(CmdEnable17), .Q0(CASr), .F1(N_156), .Q1(CASr2)); + SLICE_75 SLICE_75( .D1(\Din_c[4] ), .C1(\Din_c[3] ), .B1(\Din_c[2] ), + .A1(\Din_c[1] ), .C0(CmdEnable16_0_a3_5), .B0(CmdEnable16_0_a3_4), + .A0(C1WR), .M1(\Din_c[7] ), .M0(\Din_c[6] ), .CLK(PHI2_c), + .F0(CmdEnable16), .Q0(\Bank[6] ), .F1(CmdEnable16_0_a3_5), .Q1(\Bank[7] )); + SLICE_76 SLICE_76( .D1(\MAin_c[4] ), .C1(\MAin_c[3] ), .B1(\MAin_c[1] ), + .A1(\MAin_c[0] ), .D0(nFWE_c), .C0(\MAin_c[2] ), .B0(C1WR_7), + .A0(C1WR_2_0), .M1(\Din_c[1] ), .M0(\Din_c[0] ), .CLK(PHI2_c), .F0(C1WR), + .Q0(\Bank[0] ), .F1(C1WR_2_0), .Q1(\Bank[1] )); + SLICE_77 SLICE_77( .D1(\Bank[7] ), .C1(\Bank[6] ), .B1(\Bank[5] ), + .A1(\Bank[2] ), .D0(un1_Bank_1_5), .C0(un1_Bank_1_4), .B0(nFWE_c), + .A0(ADWR_8), .F0(ADWR), .F1(un1_Bank_1_5)); + SLICE_78 SLICE_78( .B1(\Din_c[2] ), .A1(\Din_c[0] ), .D0(N_180), .C0(N_156), + .B0(N_122_5), .A0(ADWR_8), .F0(un1_CmdEnable20_0_a3_0_2), .F1(N_180)); + SLICE_79 SLICE_79( .B1(\MAin_c[7] ), .A1(\MAin_c[6] ), .D0(un1_Bank_1_5), + .C0(un1_Bank_1_4), .B0(\MAin_c[5] ), .A0(ADWR_8_2), .M1(\Din_c[3] ), + .M0(\Din_c[2] ), .CLK(PHI2_c), .F0(C1WR_7), .Q0(\Bank[2] ), .F1(ADWR_8_2), + .Q1(\Bank[3] )); + SLICE_80 SLICE_80( .B1(\FS[17] ), .A1(\FS[11] ), .D0(N_133_5), .C0(N_133_3), + .B0(\FS[13] ), .A0(\FS[10] ), .F0(InitReady3), .F1(N_133_3)); + SLICE_81 SLICE_81( .D1(\MAin_c[5] ), .C1(\MAin_c[4] ), .B1(\MAin_c[1] ), + .A1(\MAin_c[0] ), .D0(\MAin_c[3] ), .C0(\MAin_c[2] ), .B0(ADWR_8_4), + .A0(ADWR_8_2), .F0(ADWR_8), .F1(ADWR_8_4)); + SLICE_82 SLICE_82( .C1(Ready), .B1(CASr3), .A1(CASr2), .D0(m6_0_a2_2), + .C0(\S[1] ), .B0(CO0), .A0(CBR_fast), .M1(\Din_c[3] ), .M0(\Din_c[2] ), + .CLK(nCCAS_c), .F0(G_17_1), .Q0(\WRD[2] ), .F1(m6_0_a2_2), .Q1(\WRD[3] )); + SLICE_83 SLICE_83( .D1(\Din_c[4] ), .C1(\Din_c[6] ), .B1(\Din_c[5] ), + .A1(\Din_c[7] ), .D0(\Din_c[0] ), .C0(\Din_c[2] ), .B0(\Din_c[3] ), + .A0(N_163), .M1(\MAin_c[9] ), .M0(\MAin_c[8] ), .LSR(Ready_fast), + .CLK(nCRAS_c), .F0(XOR8MEG_3_u_0_a3_0_1), .Q0(\RowA[8] ), .F1(N_163), .Q1(\RowA[9] )); - SLICE_81 SLICE_81( .D1(\FS[17] ), .C1(\FS[15] ), .B1(\FS[14] ), - .A1(\FS[13] ), .D0(\FS[17] ), .C0(\FS[15] ), .B0(\FS[13] ), .A0(\FS[12] ), - .M1(nFWE_c), .M0(nFWE_c), .CLK(nCRAS_c), .F0(N_95_5), .Q0(FWEr), - .F1(UFMSDI_ens2_i_o2_0_3), .Q1(FWEr_fast)); - SLICE_82 SLICE_82( .D1(\Din_c[3] ), .C1(\Din_c[5] ), .B1(CmdLEDEN), - .A1(N_128), .D0(\Din_c[3] ), .C0(\Din_c[5] ), .B0(N_128), .A0(XOR8MEG18), - .M0(CASr2), .CLK(RCLK_c), .F0(CmdSubmitted_1_sqmuxa), .Q0(CASr3), - .F1(N_132)); - SLICE_83 SLICE_83( .C1(\IS[3] ), .B1(\IS[2] ), .A1(\IS[1] ), .C0(\IS[2] ), - .B0(\IS[1] ), .A0(\IS[0] ), .M1(\CROW_c[1] ), .M0(\CROW_c[0] ), - .LSR(Ready_fast), .CLK(nCRAS_c), .F0(N_165), .Q0(\RBA_c[0] ), .F1(N_160), + SLICE_84 SLICE_84( .D1(FWEr_fast), .C1(CO0), .B1(CASr3), .A1(CASr2), + .D0(FWEr_fast), .C0(CO0), .B0(CASr3), .A0(CASr2), .M1(\Din_c[1] ), + .M0(\Din_c[0] ), .CLK(nCCAS_c), .F0(g0_i_a5_1_2), .Q0(\WRD[0] ), + .F1(G_1_0), .Q1(\WRD[1] )); + SLICE_85 SLICE_85( .D1(\Din_c[3] ), .C1(\Din_c[5] ), .B1(N_36), + .A1(XOR8MEG18), .C0(N_36), .B0(\Din_c[5] ), .A0(\Din_c[3] ), + .M1(\Din_c[2] ), .M0(\Din_c[1] ), .CE(CmdUFMCLK_1_sqmuxa), .CLK(PHI2_c), + .F0(N_95), .Q0(CmdUFMCLK), .F1(CmdUFMCLK_1_sqmuxa), .Q1(CmdUFMCS)); + SLICE_86 SLICE_86( .D1(\FS[17] ), .C1(\FS[15] ), .B1(\FS[14] ), + .A1(\FS[12] ), .D0(\FS[16] ), .C0(\FS[15] ), .B0(\FS[14] ), .A0(\FS[12] ), + .F0(N_133_5), .F1(UFMSDI_ens2_i_o2_0_3)); + SLICE_87 SLICE_87( .D1(\Din_c[4] ), .C1(\Din_c[6] ), .B1(\Din_c[7] ), + .A1(\Din_c[5] ), .D0(\Din_c[7] ), .C0(\Din_c[6] ), .B0(\Din_c[5] ), + .A0(\Din_c[0] ), .M1(nCCAS_c), .M0(nCCAS_c), .CLK(nCRAS_c), + .F0(CmdEnable16_0_a3_4), .Q0(CBR), .F1(CmdLEDEN_4_u_i_a2_0_0), + .Q1(CBR_fast)); + SLICE_88 SLICE_88( .D1(\Din_c[7] ), .C1(\Din_c[5] ), .B1(\Din_c[3] ), + .A1(\Din_c[1] ), .C0(N_36), .B0(\Din_c[5] ), .A0(\Din_c[3] ), + .M0(\Din_c[0] ), .CE(CmdUFMCLK_1_sqmuxa), .CLK(PHI2_c), .F0(N_45), + .Q0(CmdUFMSDI), .F1(N_122_5)); + SLICE_89 SLICE_89( .D1(\FS[10] ), .C1(\FS[9] ), .B1(\FS[7] ), .A1(\FS[1] ), + .C0(\FS[9] ), .B0(\FS[7] ), .A0(\FS[5] ), .M1(\MAin_c[5] ), + .M0(\MAin_c[4] ), .LSR(Ready_fast), .CLK(nCRAS_c), .F0(N_34), + .Q0(\RowA[4] ), .F1(un1_FS_13_i_a2_9_5), .Q1(\RowA[5] )); + SLICE_90 SLICE_90( .B1(\S[1] ), .A1(CO0), .C0(\S[1] ), .B0(CO0), .A0(CASr2), + .M1(\CROW_c[1] ), .M0(\CROW_c[0] ), .LSR(Ready_fast), .CLK(nCRAS_c), + .F0(RCKEEN_8_u_0_a3_0_0), .Q0(\RBA_c[0] ), .F1(RCKEEN_8_u_0_1_a1_0), .Q1(\RBA_c[1] )); - SLICE_84 SLICE_84( .D1(\FS[11] ), .C1(\FS[10] ), .B1(\FS[8] ), .A1(\FS[6] ), - .D0(\FS[10] ), .C0(\FS[7] ), .B0(\FS[6] ), .A0(\FS[1] ), .F0(N_137_6), - .F1(UFMSDI_ens2_i_a2_4_2)); - SLICE_85 SLICE_85( .D1(\Din_c[4] ), .C1(\Din_c[7] ), .B1(\Din_c[0] ), - .A1(\Din_c[1] ), .D0(\Din_c[7] ), .C0(\Din_c[6] ), .B0(\Din_c[5] ), - .A0(\Din_c[4] ), .M1(\Din_c[3] ), .M0(\Din_c[2] ), .CLK(nCCAS_c), - .F0(un1_Din_4), .Q0(\WRD[2] ), .F1(CmdEnable17_0_a2_3), .Q1(\WRD[3] )); - SLICE_86 SLICE_86( .B1(nRowColSel), .A1(\MAin_c[9] ), .C0(nRowColSel), - .B0(\RowA[9] ), .A0(\MAin_c[9] ), .F0(\RA_c[9] ), .F1(RDQML_c)); - SLICE_87 SLICE_87( .C1(N_151), .B1(UFMSDI_ens2_i_a0), .A1(CmdUFMSDI), - .D0(N_151), .C0(\FS[11] ), .B0(\FS[9] ), .A0(\FS[4] ), .F0(N_137_8), - .F1(UFMSDI_r_xx_mm_1)); - SLICE_88 SLICE_88( .C1(nFWE_c), .B1(\MAin_c[3] ), .A1(\MAin_c[2] ), - .B0(nFWE_c), .A0(nCCAS_c), .M1(\MAin_c[7] ), .M0(\MAin_c[6] ), - .LSR(Ready_fast), .CLK(nCRAS_c), .F0(RD_1_i), .Q0(\RowA[6] ), - .F1(C1WR_0_a2_0_3), .Q1(\RowA[7] )); - SLICE_89 SLICE_89( .B1(nRowColSel), .A1(\MAin_c[9] ), .C0(nRowColSel), - .B0(\RowA[8] ), .A0(\MAin_c[8] ), .F0(\RA_c[8] ), .F1(RDQMH_c)); - SLICE_90 SLICE_90( .C1(\MAin_c[1] ), .B1(\MAin_c[0] ), .A1(N_147), - .C0(nRowColSel), .B0(\RowA[0] ), .A0(\MAin_c[0] ), .F0(\RA_c[0] ), - .F1(un1_CMDWR)); - SLICE_91 SLICE_91( .C1(nRowColSel), .B1(\RowA[7] ), .A1(\MAin_c[7] ), - .C0(nRowColSel), .B0(\RowA[1] ), .A0(\MAin_c[1] ), .F0(\RA_c[1] ), - .F1(\RA_c[7] )); - SLICE_92 SLICE_92( .C1(nRowColSel), .B1(\RowA[6] ), .A1(\MAin_c[6] ), - .C0(nRowColSel), .B0(\RowA[2] ), .A0(\MAin_c[2] ), .F0(\RA_c[2] ), - .F1(\RA_c[6] )); - SLICE_93 SLICE_93( .C1(nRowColSel), .B1(\RowA[5] ), .A1(\MAin_c[5] ), + SLICE_91 SLICE_91( .B1(nRowColSel), .A1(\MAin_c[9] ), .C0(nRowColSel), + .B0(\RowA[9] ), .A0(\MAin_c[9] ), .F0(\RA_c[9] ), .F1(RDQMH_c)); + SLICE_92 SLICE_92( .C1(\IS[1] ), .B1(\IS[2] ), .A1(\IS[3] ), .D0(RASr2), + .C0(\IS[2] ), .B0(\IS[1] ), .A0(\IS[0] ), .F0(m18_0_a3_3), .F1(N_154)); + SLICE_93 SLICE_93( .C1(nRowColSel), .B1(\RowA[1] ), .A1(\MAin_c[1] ), + .D0(\MAin_c[4] ), .C0(\MAin_c[3] ), .B0(\MAin_c[2] ), .A0(\MAin_c[1] ), + .M1(\Din_c[5] ), .M0(\Din_c[4] ), .CLK(PHI2_c), .F0(CMDWR_2), + .Q0(\Bank[4] ), .F1(\RA_c[1] ), .Q1(\Bank[5] )); + SLICE_94 SLICE_94( .D1(\FS[11] ), .C1(\FS[10] ), .B1(\FS[8] ), .A1(\FS[6] ), + .D0(\FS[6] ), .C0(\FS[3] ), .B0(\FS[2] ), .A0(\FS[0] ), + .F0(un1_FS_13_i_a2_9_4), .F1(UFMSDI_ens2_i_a2_4_2)); + SLICE_95 SLICE_95( .B1(\S[1] ), .A1(InitReady), .D0(\S[1] ), .C0(RASr2), + .B0(\IS[3] ), .A0(CO0), .M1(RASr), .M0(nCRAS_c), .CLK(RCLK_c), + .F0(Ready_0_sqmuxa_0_a3_2), .Q0(RASr), .F1(g0_i_a5_2_1), .Q1(RASr2)); + SLICE_96 SLICE_96( .B1(nRowColSel), .A1(\MAin_c[9] ), .C0(nRowColSel), + .B0(\RowA[8] ), .A0(\MAin_c[8] ), .F0(\RA_c[8] ), .F1(RDQML_c)); + SLICE_97 SLICE_97( .C1(nRowColSel), .B1(\RowA[0] ), .A1(\MAin_c[0] ), .C0(nRowColSel), .B0(\RowA[3] ), .A0(\MAin_c[3] ), .F0(\RA_c[3] ), - .F1(\RA_c[5] )); - SLICE_94 SLICE_94( .B1(N_155), .A1(Ready), .B0(\S[1] ), .A0(Ready), - .M0(\IS[0] ), .LSR(RA10s_i), .CLK(RCLK_c), .F0(RCKEEN_8_u_0_a2_1_out), - .Q0(\RA_c[10] ), .F1(N_159_i)); + .F1(\RA_c[0] )); + SLICE_98 SLICE_98( .C1(nRowColSel), .B1(\RowA[2] ), .A1(\MAin_c[2] ), + .C0(nRowColSel), .B0(\RowA[4] ), .A0(\MAin_c[4] ), .F0(\RA_c[4] ), + .F1(\RA_c[2] )); + SLICE_99 SLICE_99( .C1(nRowColSel), .B1(\RowA[7] ), .A1(\MAin_c[7] ), + .C0(nRowColSel), .B0(\RowA[5] ), .A0(\MAin_c[5] ), .F0(\RA_c[5] ), + .F1(\RA_c[7] )); + SLICE_100 SLICE_100( .B1(nFWE_c), .A1(nCCAS_c), .D0(\Bank[4] ), + .C0(\Bank[3] ), .B0(\Bank[1] ), .A0(\Bank[0] ), .F0(un1_Bank_1_4), + .F1(RD_1_i)); + SLICE_101 SLICE_101( .C1(nRowColSel), .B1(\RowA[6] ), .A1(\MAin_c[6] ), + .B0(Ready), .A0(N_148), .M1(nFWE_c), .M0(nFWE_c), .CLK(nCRAS_c), + .F0(N_153_i), .Q0(FWEr), .F1(\RA_c[6] ), .Q1(FWEr_fast)); RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .PADDT(RD_1_i), .PADDO(\WRD[0] ), .RD0(RD[0])); Dout_0_ \Dout[0]_I ( .PADDO(\RD_in[0] ), .Dout0(Dout[0])); @@ -660,21 +681,18 @@ module SLICE_8 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO ); endmodule -module SLICE_9 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, - F1 ); - wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly; +module SLICE_9 ( input B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly; - lut4 CmdEnable17_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut4 ADSubmitted_r_RNO( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); lut40002 ADSubmitted_r( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre ADSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); @@ -691,7 +709,7 @@ endmodule module lut4 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40002 ( input A, B, C, D, output Z ); @@ -704,19 +722,20 @@ module inverter ( input I, output Z ); INV INST1( .A(I), .Z(Z)); endmodule -module SLICE_14 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, - F1 ); - wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly; +module SLICE_14 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, + Q0, F1 ); + wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly; - lut40003 CmdEnable16_0_a2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); + lut40003 CmdEnable_s_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40004 C1Submitted_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre C1Submitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -734,83 +753,36 @@ endmodule module lut40003 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0203) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40004 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hAEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hAAAE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_19 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, - F1 ); - wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; +module SLICE_20 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, + Q0, F1 ); + wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly; - lut40005 Ready_0_sqmuxa_0_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40006 \S_RNO[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0007 \S[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + lut40005 CmdEnable_0_sqmuxa( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40006 CmdEnable_s( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdEnable( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40005 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40006 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module vmuxregsre0007 ( input D0, D1, SD, SP, CK, LSR, output Q ); - - FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module SLICE_20 ( input B1, A1, D0, C0, B0, A0, DI0, M0, CLK, output OFX0, Q0 ); - wire GNDI, \SLICE_20/SLICE_20_K1_H1 , \SLICE_20/CmdEnable_s/GATE_H0 , VCCI, - CLK_NOTIN, DI0_dly, CLK_dly; - - lut40008 SLICE_20_K1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(\SLICE_20/SLICE_20_K1_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40009 \CmdEnable_s/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(\SLICE_20/CmdEnable_s/GATE_H0 )); - vmuxregsre CmdEnable( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - selmux2 SLICE_20_K0K1MUX( .D0(\SLICE_20/CmdEnable_s/GATE_H0 ), - .D1(\SLICE_20/SLICE_20_K1_H1 ), .SD(M0), .Z(OFX0)); - - specify - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (D0 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); @@ -818,38 +790,33 @@ module SLICE_20 ( input B1, A1, D0, C0, B0, A0, DI0, M0, CLK, output OFX0, Q0 ); endmodule -module lut40008 ( input A, B, C, D, output Z ); +module lut40005 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40009 ( input A, B, C, D, output Z ); +module lut40006 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hAC8C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hFFCA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module selmux2 ( input D0, D1, SD, output Z ); - - MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z)); -endmodule - -module SLICE_21 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, +module SLICE_21 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; - lut40010 Cmdn8MEGEN_4_u_i_a2_2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40007 CmdLEDEN_4_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40008 CmdLEDEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40011 CmdLEDEN_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre CmdLEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); @@ -862,21 +829,21 @@ module SLICE_21 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, endmodule -module lut40010 ( input A, B, C, D, output Z ); +module lut40007 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h5D0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40011 ( input A, B, C, D, output Z ); +module lut40008 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0203) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h4545) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_22 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly; - lut40005 un1_FS_14_i_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40012 CmdSubmitted_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40009 un1_FS_14_i_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut4 CmdSubmitted_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre CmdSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); @@ -898,17 +865,17 @@ module SLICE_22 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); endmodule -module lut40012 ( input A, B, C, D, output Z ); +module lut40009 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_26 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; - lut40013 Cmdn8MEGEN_4_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40014 Cmdn8MEGEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40010 Cmdn8MEGEN_4_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40011 Cmdn8MEGEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre Cmdn8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); @@ -932,29 +899,30 @@ module SLICE_26 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, endmodule -module lut40013 ( input A, B, C, D, output Z ); +module lut40010 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h33AB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hB3A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40014 ( input A, B, C, D, output Z ); +module lut40011 ( input A, B, C, D, output Z ); ROM16X1 #(16'h5151) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_29 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, - F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly; +module SLICE_29 ( input C1, B1, A1, C0, B0, A0, DI0, M1, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; - lut40015 nRRAS_5_u_i( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40016 \IS_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40012 Ready_0_sqmuxa_0_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); + lut40013 \IS_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre CASr3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre \IS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -962,19 +930,21 @@ module SLICE_29 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module lut40015 ( input A, B, C, D, output Z ); +module lut40012 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hFF32) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40016 ( input A, B, C, D, output Z ); +module lut40013 ( input A, B, C, D, output Z ); ROM16X1 #(16'hA9A9) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule @@ -983,9 +953,9 @@ module SLICE_30 ( input C1, B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40017 \IS_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40014 \IS_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40018 IS_n1_0_x2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40015 IS_n1_0_x2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre \IS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1009,12 +979,12 @@ module SLICE_30 ( input C1, B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, endmodule -module lut40017 ( input A, B, C, D, output Z ); +module lut40014 ( input A, B, C, D, output Z ); ROM16X1 #(16'h7878) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40018 ( input A, B, C, D, output Z ); +module lut40015 ( input A, B, C, D, output Z ); ROM16X1 #(16'h6666) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule @@ -1023,8 +993,8 @@ module SLICE_31 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; - lut40019 RA10_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40020 \IS_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40016 RA10_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40017 \IS_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \IS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1048,12 +1018,12 @@ module SLICE_31 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output endmodule -module lut40019 ( input A, B, C, D, output Z ); +module lut40016 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hFFEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40020 ( input A, B, C, D, output Z ); +module lut40017 ( input A, B, C, D, output Z ); ROM16X1 #(16'h6AAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule @@ -1061,8 +1031,8 @@ endmodule module SLICE_32 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly; - lut40021 UFMSDI_ens2_i_a0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40012 InitReady_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40018 UFMSDI_ens2_i_a0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut4 InitReady_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre InitReady( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); @@ -1083,23 +1053,24 @@ module SLICE_32 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); endmodule -module lut40021 ( input A, B, C, D, output Z ); +module lut40018 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h4555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h5155) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_33 ( input C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, - F1 ); +module SLICE_33 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - lut40022 LED_pad_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40019 LED_pad_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40020 LEDEN_5_i_m2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40023 LEDEN_5_i_m2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre LEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -1115,28 +1086,68 @@ module SLICE_33 ( input C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, endmodule -module lut40022 ( input A, B, C, D, output Z ); +module lut40019 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hFBFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hFFBF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40023 ( input A, B, C, D, output Z ); +module lut40020 ( input A, B, C, D, output Z ); ROM16X1 #(16'h8B8B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_39 ( input B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); +module SLICE_38 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; + + lut40021 nRCS_RNO_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut4 RA10_2_sqmuxa_0_o2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 RA10( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40021 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0022 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3JY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module SLICE_39 ( input C1, B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, + F1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; - lut40024 XOR8MEG_3_u_0_a3_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40023 Cmdn8MEGEN_4_u_i_o2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40025 RA11_2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0007 RA11( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + lut40024 RA11_2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0025 RA11( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); @@ -1151,22 +1162,28 @@ module SLICE_39 ( input B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); endmodule -module lut40024 ( input A, B, C, D, output Z ); +module lut40023 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hFDFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40025 ( input A, B, C, D, output Z ); +module lut40024 ( input A, B, C, D, output Z ); ROM16X1 #(16'hC6C6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule +module vmuxregsre0025 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + module SLICE_41 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, DI0_dly, CLK_dly, M1_dly; - lut40026 RCKEEN_8_u_1_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40027 RCKEEN_8_u( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40026 RCKEEN_8_u_0_1_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40027 RCKEEN_8_u_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre PHI2r2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1195,29 +1212,28 @@ endmodule module lut40026 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h70CF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0CDC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40027 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hDCCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hCDCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_42 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output - F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, M1_dly; +module SLICE_42 ( input C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; - lut40028 nRWE_RNO_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40028 nRCS_RNO_3( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); lut40029 RCKE_2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre PHI2r( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre RCKE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -1237,7 +1253,7 @@ endmodule module lut40028 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hE0E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40029 ( input A, B, C, D, output Z ); @@ -1249,7 +1265,7 @@ module SLICE_43 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, DI0_dly, CLK_dly, M1_dly; - lut40030 RCKEEN_8_u_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40030 RCKEEN_8_u_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40031 Ready_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre PHI2r3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); @@ -1289,14 +1305,13 @@ endmodule module SLICE_44 ( input D1, C1, B1, A1, B0, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, M1_NOTIN, VCCI, DI0_dly, CLK_dly, M1_dly; + wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; - lut40028 Ready_0_sqmuxa_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40012 Ready_fast_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40032 Ready_0_sqmuxa_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut4 Ready_fast_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre RASr( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN)); + vmuxregsre RASr3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre Ready_fast( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); @@ -1318,13 +1333,18 @@ module SLICE_44 ( input D1, C1, B1, A1, B0, A0, DI0, M1, CLK, output F0, Q0, endmodule +module lut40032 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + module SLICE_50 ( input C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; - lut40032 nRowColSel_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40033 nRowColSel_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40012 \S_0_i_o2[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre0007 \S[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + lut4 \S_0_i_o2[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0025 \S[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); @@ -1344,23 +1364,21 @@ module SLICE_50 ( input C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); endmodule -module lut40032 ( input A, B, C, D, output Z ); +module lut40033 ( input A, B, C, D, output Z ); ROM16X1 #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output - F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, M1_dly; +module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, + Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly; - lut40033 UFMCLK_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40034 UFMCLK_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre RASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); + lut40034 UFMCLK_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40035 UFMCLK_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre UFMCLK( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -1372,37 +1390,33 @@ module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module lut40033 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'hF2F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40034 ( input A, B, C, D, output Z ); + ROM16X1 #(16'hF2F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40035 ( input A, B, C, D, output Z ); + ROM16X1 #(16'h1032) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output - F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, M1_dly; +module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, + Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly; - lut40035 PHI2r3_RNITCN41( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40036 UFMSDI_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre RASr3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); + lut40036 PHI2r3_RNITCN41( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40037 UFMSDI_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre UFMSDI( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -1414,21 +1428,19 @@ module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module lut40035 ( input A, B, C, D, output Z ); +module lut40036 ( input A, B, C, D, output Z ); ROM16X1 #(16'h3B33) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40036 ( input A, B, C, D, output Z ); +module lut40037 ( input A, B, C, D, output Z ); ROM16X1 #(16'h3210) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule @@ -1436,7 +1448,7 @@ endmodule module SLICE_55 ( input C0, B0, A0, M1, M0, CLK, output F0, Q0, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; - lut40037 \un9_RA[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40038 UFMSDI_RNO_0( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \WRD[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); @@ -1459,18 +1471,17 @@ module SLICE_55 ( input C0, B0, A0, M1, M0, CLK, output F0, Q0, Q1 ); endmodule -module lut40037 ( input A, B, C, D, output Z ); +module lut40038 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hACAC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h3232) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_56 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, - F1, Q1 ); +module SLICE_56 ( input B1, A1, B0, A0, M1, M0, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; - lut40038 C1WR_0_a2_0_11( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40039 UFMSDI_ens2_i_o2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40039 un1_FS_14_i_o2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); + lut40040 nRCS_9_u_i_a2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre \WRD[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1479,11 +1490,8 @@ module SLICE_56 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); @@ -1496,31 +1504,29 @@ module SLICE_56 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, endmodule -module lut40038 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40039 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h2C2C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output - F0, Q0, F1 ); - wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly; +module lut40040 ( input A, B, C, D, output Z ); - lut40005 XOR8MEG_3_u_0_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40040 XOR8MEG_3_u_0_a3_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + ROM16X1 #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_57 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; + + lut40041 XOR8MEG_3_u_0_a3( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 XOR8MEG_3_u_0_a3_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre XOR8MEG( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); @@ -1536,7 +1542,12 @@ module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output endmodule -module lut40040 ( input A, B, C, D, output Z ); +module lut40041 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40042 ( input A, B, C, D, output Z ); ROM16X1 #(16'hF7F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule @@ -1545,9 +1556,9 @@ module SLICE_58 ( input C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - lut40041 UFMSDI_en_ss0_0_a2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40043 UFMSDI_en_ss0_0_a2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40023 n8MEGEN_5_i_m2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40020 n8MEGEN_5_i_m2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre n8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1568,24 +1579,23 @@ module SLICE_58 ( input C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, endmodule -module lut40041 ( input A, B, C, D, output Z ); +module lut40043 ( input A, B, C, D, output Z ); ROM16X1 #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, - Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly; +module SLICE_59 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly; - lut40042 un1_nRCAS_6_sqmuxa_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40043 nRCAS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0044 nRCAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + lut40044 nRCAS_RNO_1( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40045 nRCAS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0046 nRCAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -1601,73 +1611,34 @@ module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, endmodule -module lut40042 ( input A, B, C, D, output Z ); +module lut40044 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0BFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h1313) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40043 ( input A, B, C, D, output Z ); +module lut40045 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h2232) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0703) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module vmuxregsre0044 ( input D0, D1, SD, SP, CK, LSR, output Q ); +module vmuxregsre0046 ( input D0, D1, SD, SP, CK, LSR, output Q ); FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); defparam INST01.GSR = "DISABLED"; endmodule -module SLICE_60 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, - Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly; +module SLICE_60 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly; - lut40045 nRCS_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40046 nRCS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0044 nRCS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + lut40047 RCKEEN_8_u_0_a2_0_m1_0_a2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40048 nRCS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0046 nRCS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40045 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'hE6EE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40046 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h3233) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_61 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, - Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly; - - lut40047 nRRAS_5_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40048 nRRAS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0044 nRRAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -1685,21 +1656,21 @@ endmodule module lut40047 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h5400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40048 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h5051) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0307) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, +module SLICE_61 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire VCCI, GNDI, DI0_dly, CLK_dly; - lut40049 nRCAS_0_sqmuxa_1_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40050 nRWE_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0044 nRWE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + lut40049 nRRAS_5_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40050 nRRAS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0046 nRRAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); @@ -1723,11 +1694,49 @@ endmodule module lut40049 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h5400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40050 ( input A, B, C, D, output Z ); + ROM16X1 #(16'h00CD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, + Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly; + + lut40051 nRCAS_0_sqmuxa_1_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40052 nRWE_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0046 nRWE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40051 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40052 ( input A, B, C, D, output Z ); + ROM16X1 #(16'hF4F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule @@ -1735,9 +1744,9 @@ module SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); wire VCCI, DI0_dly, CLK_dly, LSR_dly; - lut40051 nRowColSel_0_0_a3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40052 nRowColSel_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0007 nRowColSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + lut40053 nRowColSel_0_0_a3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40054 nRowColSel_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0025 nRowColSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1759,12 +1768,12 @@ module SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output endmodule -module lut40051 ( input A, B, C, D, output Z ); +module lut40053 ( input A, B, C, D, output Z ); ROM16X1 #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40052 ( input A, B, C, D, output Z ); +module lut40054 ( input A, B, C, D, output Z ); ROM16X1 #(16'hDCEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule @@ -1773,9 +1782,9 @@ module SLICE_64 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire VCCI, GNDI, DI0_dly, CLK_dly; - lut40053 nUFMCS15_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40054 nUFMCS_s_0_N_5_i( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0044 nUFMCS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + lut40055 nUFMCS15_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40056 nUFMCS_s_0_N_5_i( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0046 nUFMCS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); @@ -1797,12 +1806,12 @@ module SLICE_64 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, endmodule -module lut40053 ( input A, B, C, D, output Z ); +module lut40055 ( input A, B, C, D, output Z ); ROM16X1 #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40054 ( input A, B, C, D, output Z ); +module lut40056 ( input A, B, C, D, output Z ); ROM16X1 #(16'hDCFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule @@ -1812,9 +1821,9 @@ module nRWE_RNO_1_SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, output wire \nRWE_RNO_1/SLICE_65/nRWE_RNO_1/SLICE_65_K1_H1 , \nRWE_RNO_1/SLICE_65/nRWE_RNO_1/GATE_H0 ; - lut40055 \nRWE_RNO_1/SLICE_65_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40057 \nRWE_RNO_1/SLICE_65_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/SLICE_65_K1_H1 )); - lut40056 \nRWE_RNO_1/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40058 \nRWE_RNO_1/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/GATE_H0 )); selmux2 \nRWE_RNO_1/SLICE_65_K0K1MUX ( .D0(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/GATE_H0 ), @@ -1834,29 +1843,57 @@ module nRWE_RNO_1_SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, output endmodule -module lut40055 ( input A, B, C, D, output Z ); +module lut40057 ( input A, B, C, D, output Z ); ROM16X1 #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40056 ( input A, B, C, D, output Z ); +module lut40058 ( input A, B, C, D, output Z ); ROM16X1 #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_66 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output +module selmux2 ( input D0, D1, SD, output Z ); + + MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z)); +endmodule + +module SLICE_66 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40016 IS_0_sqmuxa_0_o2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40059 un1_nRCAS_6_sqmuxa_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40059 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0BFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_67 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - lut40057 nUFMCS_s_0_N_5_i_N_2L1( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40060 nUFMCS_s_0_N_5_i_N_2L1( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40049 UFMCLK_r_i_a2_2_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0007 \RowA[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + lut40051 UFMCLK_r_i_a2_2_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0025 \RowA[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0007 \RowA[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + vmuxregsre0025 \RowA[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify @@ -1878,84 +1915,21 @@ module SLICE_66 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output endmodule -module lut40057 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h0B0B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_67 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40058 CmdUFMCLK_1_sqmuxa_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40005 XOR8MEG18_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0059 \RowA[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0007 \RowA[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40058 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module vmuxregsre0059 ( input D0, D1, SD, SP, CK, LSR, output Q ); - - FL1P3JY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40053 un1_FS_14_i_a2_0_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40060 un1_FS_14_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - module lut40060 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hEAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0B0B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, LSR, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, M0_dly, CLK_dly, LSR_dly; - lut40061 un1_FS_13_i_a2_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40060 un1_FS_13_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40061 nRCS_RNO_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40027 nRCS_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0025 \S[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -1966,95 +1940,33 @@ module SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule module lut40061 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_70 ( input D1, C1, B1, A1, B0, A0, M1, M0, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; - - lut4 C1WR_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40062 C1WR_0_a2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \Bank[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \Bank[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40062 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_71 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, - Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly; - - lut4 C1WR_0_a2_0_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut4 C1WR_0_a2_0_10( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \Bank[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \Bank[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_72 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output +module SLICE_69 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - lut40063 UFMSDI_ens2_i_o2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40062 UFMSDI_ens2_i_o2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40064 UFMCLK_r_i_m2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0007 \RowA[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + lut40063 UFMCLK_RNO_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0025 \RowA[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0007 \RowA[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + vmuxregsre0025 \RowA[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify @@ -2076,29 +1988,97 @@ module SLICE_72 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output endmodule -module lut40063 ( input A, B, C, D, output Z ); +module lut40062 ( input A, B, C, D, output Z ); ROM16X1 #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40064 ( input A, B, C, D, output Z ); +module lut40063 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hAAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hD888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_73 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; +module SLICE_70 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; - lut40065 IS_0_sqmuxa_0_o2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40012 IS_0_sqmuxa_0_o2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40064 CMDWR( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40043 un1_CmdEnable20_0_a3( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre CmdUFMCS( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40064 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_71 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40053 un1_FS_14_i_a2_0_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40065 un1_FS_14_i_0( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40065 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hECEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_72 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40051 un1_FS_13_i_a2_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40065 un1_FS_13_i_0( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_73 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40066 CmdSubmitted_1_sqmuxa_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40041 XOR8MEG18( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0025 \RowA[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - vmuxregsre CmdUFMCLK( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0025 \RowA[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -2113,50 +2093,23 @@ module SLICE_73 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module lut40065 ( input A, B, C, D, output Z ); +module lut40066 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_74 ( input B1, A1, D0, C0, B0, A0, M0, CE, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; - - lut40062 InitReady3_0_a2_3( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut4 InitReady3_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre CmdUFMSDI( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - endspecify - -endmodule - -module SLICE_75 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, +module SLICE_74 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, M0_NOTIN, M1_dly, CLK_dly, M0_dly; - lut40066 Cmdn8MEGEN_4_u_i_o2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut4 CmdEnable17_0_o2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40041 CmdLEDEN_4_u_i_a2_0( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40009 CmdEnable17_0_a3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre CASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -2165,9 +2118,9 @@ module SLICE_75 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN)); specify - (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); @@ -2181,28 +2134,24 @@ module SLICE_75 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, endmodule -module lut40066 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'hFDFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_76 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, - Q1 ); +module SLICE_75 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; - lut40024 CmdEnable16_0_a2_4( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40055 CmdEnable16_0_a3_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40067 CmdEnable16_0_a3( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40067 CmdEnable16_0_a2_4_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \Bank[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + vmuxregsre \Bank[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \Bank[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + vmuxregsre \Bank[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); @@ -2218,20 +2167,88 @@ endmodule module lut40067 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_77 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, +module SLICE_76 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly; + + lut40061 C1WR_2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40064 C1WR( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \Bank[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \Bank[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_77 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40061 un1_Bank_1_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40051 ADWR( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_78 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40041 CmdEnable17_0_a2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40009 un1_CmdEnable20_0_a3_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_79 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; - lut40068 CmdEnable16_0_a2_1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40041 ADWR_8_2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40049 CmdEnable16_0_a2_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \Bank[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + lut40005 C1WR_7( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \Bank[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \Bank[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + vmuxregsre \Bank[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify @@ -2251,26 +2268,12 @@ module SLICE_77 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, endmodule -module lut40068 ( input A, B, C, D, output Z ); +module SLICE_80 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; - ROM16X1 #(16'h4444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_78 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, M1_NOTIN, VCCI, CLK_NOTIN, M0_NOTIN, M1_dly, CLK_dly, M0_dly; - - lut40069 CmdEnable17_0_o2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40041 InitReady3_0_a2_3( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40058 CmdEnable17_0_a2_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre CBR_fast( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); - inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - vmuxregsre CBR( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN)); + lut40005 InitReady3_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (B1 => F1) = (0:0:0,0:0:0); @@ -2279,6 +2282,123 @@ module SLICE_78 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40005 ADWR_8_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40005 ADWR_8( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_82 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40068 nRWE_RNO_2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40061 nRWE_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \WRD[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre \WRD[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module lut40068 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_83 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40021 XOR8MEG_3_u_0_o2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40053 XOR8MEG_3_u_0_a3_0_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0022 \RowA[9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0025 \RowA[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40069 nRCAS_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40051 nRCS_RNO_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \WRD[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre \WRD[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); @@ -2291,24 +2411,59 @@ endmodule module lut40069 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h200F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_79 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; +module SLICE_85 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; - lut40070 nRWE_RNO_2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40070 CmdUFMCLK_1_sqmuxa_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40071 Cmdn8MEGEN_4_u_i_a2_2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40038 nRWE_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \WRD[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + vmuxregsre CmdUFMCS( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - vmuxregsre \WRD[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + vmuxregsre CmdUFMCLK( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40070 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40071 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_86 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40021 UFMSDI_ens2_i_o2_0_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40005 InitReady3_0_a2_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -2316,72 +2471,23 @@ module SLICE_79 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); endspecify endmodule -module lut40070 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_80 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40024 nRCAS_RNO_1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40071 nRCAS_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0059 \RowA[9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0007 \RowA[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40071 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h4101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, +module SLICE_87 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, Q1 ); wire M1_NOTIN, VCCI, GNDI, CLK_NOTIN, M0_NOTIN, M1_dly, CLK_dly, M0_dly; - lut40072 UFMSDI_ens2_i_o2_0_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut4 InitReady3_0_a2_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre FWEr_fast( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), + lut40072 CmdLEDEN_4_u_i_a2_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40051 CmdEnable16_0_a3_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CBR_fast( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - vmuxregsre FWEr( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), + vmuxregsre CBR( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN)); @@ -2406,63 +2512,60 @@ endmodule module lut40072 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_82 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0, +module SLICE_88 ( input D1, C1, B1, A1, C0, B0, A0, M0, CE, CLK, output F0, Q0, F1 ); - wire VCCI, GNDI, M0_dly, CLK_dly; + wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; - lut40073 CmdLEDEN_4_u_i_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40074 CmdSubmitted_1_sqmuxa_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre CASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); + lut40061 CmdEnable17_0_a3_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40073 Cmdn8MEGEN_4_u_i_o2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CmdUFMSDI( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40073 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h3222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hF8F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40074 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h0222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_83 ( input C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, - Q0, F1, Q1 ); +module SLICE_89 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output + F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - lut40063 un1_nRCAS_6_sqmuxa_i_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40072 un1_FS_13_i_a2_9_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40074 UFMSDI_ens2_i_o2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40075 Ready_0_sqmuxa_0_o2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0007 \RBA[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + vmuxregsre0022 \RowA[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0007 \RBA[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + vmuxregsre0025 \RowA[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -2480,73 +2583,59 @@ module SLICE_83 ( input C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, endmodule +module lut40074 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h2C2C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_90 ( input B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40075 RCKEEN_8_u_0_1_a1_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40076 RCKEEN_8_u_0_a3_0_0( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0025 \RBA[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0025 \RBA[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + module lut40075 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40028 UFMSDI_ens2_i_a2_4_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40061 un1_FS_13_i_a2_6( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, - Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; - - lut40076 CmdEnable17_0_a2_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40053 un1_Din_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \WRD[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - vmuxregsre \WRD[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - endspecify - + ROM16X1 #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40076 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h7070) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_86 ( input B1, A1, C0, B0, A0, output F0, F1 ); +module SLICE_91 ( input B1, A1, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40069 RDQML( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40077 RDQMH( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40037 \un9_RA[9] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40078 \un9_RA[9] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); specify (B1 => F1) = (0:0:0,0:0:0); @@ -2558,44 +2647,220 @@ module SLICE_86 ( input B1, A1, C0, B0, A0, output F0, F1 ); endmodule -module SLICE_87 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40077 UFMSDI_RNO_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40049 un1_FS_13_i_a2_8( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - module lut40077 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h3232) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_88 ( input C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; +module lut40078 ( input A, B, C, D, output Z ); - lut40078 C1WR_0_a2_0_3( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + ROM16X1 #(16'hACAC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_92 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40062 un1_nRCAS_6_sqmuxa_i_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40012 nCCAS_pad_RNI01SJ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre0007 \RowA[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + lut40032 nRWE_RNO_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_93 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40078 \un9_RA[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40061 CMDWR_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \Bank[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \Bank[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_94 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40032 UFMSDI_ens2_i_a2_4_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40055 un1_FS_13_i_a2_9_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_95 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M0_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40075 nRCS_RNO_4( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40009 Ready_0_sqmuxa_0_a3_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre RASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre RASr( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_96 ( input B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40039 RDQML( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40078 \un9_RA[8] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_97 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40078 \un9_RA[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40078 \un9_RA[3] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_98 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40078 \un9_RA[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40078 \un9_RA[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_99 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40078 \un9_RA[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40078 \un9_RA[5] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_100 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut4 nCCAS_pad_RNI01SJ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40005 un1_Bank_1_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_101 ( input C1, B1, A1, B0, A0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, M1_NOTIN, VCCI, CLK_NOTIN, M0_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40078 \un9_RA[6] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40040 IS_0_sqmuxa_0_o2_0_RNIS63D( .A(A0), .B(B0), .C(GNDI), .D(GNDI), + .Z(F0)); + vmuxregsre FWEr_fast( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0007 \RowA[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + vmuxregsre FWEr( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -2609,146 +2874,10 @@ module SLICE_88 ( input C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, Q0, $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module lut40078 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_89 ( input B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40079 RDQMH( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40037 \un9_RA[8] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40079 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_90 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40080 un1_CMDWR( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40037 \un9_RA[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40080 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'hA8A8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_91 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40037 \un9_RA[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40037 \un9_RA[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module SLICE_92 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40037 \un9_RA[6] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40037 \un9_RA[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module SLICE_93 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40037 \un9_RA[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40037 \un9_RA[3] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module SLICE_94 ( input B1, A1, B0, A0, M0, LSR, CLK, output F0, Q0, F1 ); - wire GNDI, M0_NOTIN, VCCI, M0_dly, CLK_dly, LSR_dly; - - lut40081 IS_0_sqmuxa_0_o2_0_RNIS63D( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40062 RCKEEN_8_u_0_a2_1_s( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre0059 RA10( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40081 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module RD_0_ ( output PADDI, input PADDT, PADDO, inout RD0 ); mjiobuf \RD_pad[0] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD0), .PADI(RD0)); @@ -2771,7 +2900,7 @@ endmodule module Dout_0_ ( input PADDO, output Dout0 ); - mjiobuf0082 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0)); + mjiobuf0079 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0)); specify (PADDO => Dout0) = (0:0:0,0:0:0); @@ -2779,14 +2908,14 @@ module Dout_0_ ( input PADDO, output Dout0 ); endmodule -module mjiobuf0082 ( input I, output PAD ); +module mjiobuf0079 ( input I, output PAD ); OB INST5( .I(I), .O(PAD)); endmodule module PHI2 ( output PADDI, input PHI2 ); - mjiobuf0083 PHI2_pad( .Z(PADDI), .PAD(PHI2)); + mjiobuf0080 PHI2_pad( .Z(PADDI), .PAD(PHI2)); specify (PHI2 => PADDI) = (0:0:0,0:0:0); @@ -2796,14 +2925,14 @@ module PHI2 ( output PADDI, input PHI2 ); endmodule -module mjiobuf0083 ( output Z, input PAD ); +module mjiobuf0080 ( output Z, input PAD ); IB INST1( .I(PAD), .O(Z)); endmodule module UFMSDO ( output PADDI, input UFMSDO ); - mjiobuf0083 UFMSDO_pad( .Z(PADDI), .PAD(UFMSDO)); + mjiobuf0080 UFMSDO_pad( .Z(PADDI), .PAD(UFMSDO)); specify (UFMSDO => PADDI) = (0:0:0,0:0:0); @@ -2815,7 +2944,7 @@ endmodule module UFMSDI ( input PADDO, output UFMSDI ); - mjiobuf0084 UFMSDI_pad( .I(PADDO), .PAD(UFMSDI)); + mjiobuf0081 UFMSDI_pad( .I(PADDO), .PAD(UFMSDI)); specify (PADDO => UFMSDI) = (0:0:0,0:0:0); @@ -2823,14 +2952,14 @@ module UFMSDI ( input PADDO, output UFMSDI ); endmodule -module mjiobuf0084 ( input I, output PAD ); +module mjiobuf0081 ( input I, output PAD ); OB INST5( .I(I), .O(PAD)); endmodule module UFMCLK ( input PADDO, output UFMCLK ); - mjiobuf0084 UFMCLK_pad( .I(PADDO), .PAD(UFMCLK)); + mjiobuf0081 UFMCLK_pad( .I(PADDO), .PAD(UFMCLK)); specify (PADDO => UFMCLK) = (0:0:0,0:0:0); @@ -2840,7 +2969,7 @@ endmodule module nUFMCS ( input PADDO, output nUFMCS ); - mjiobuf0084 nUFMCS_pad( .I(PADDO), .PAD(nUFMCS)); + mjiobuf0081 nUFMCS_pad( .I(PADDO), .PAD(nUFMCS)); specify (PADDO => nUFMCS) = (0:0:0,0:0:0); @@ -2850,7 +2979,7 @@ endmodule module RDQML ( input PADDO, output RDQML ); - mjiobuf0084 RDQML_pad( .I(PADDO), .PAD(RDQML)); + mjiobuf0081 RDQML_pad( .I(PADDO), .PAD(RDQML)); specify (PADDO => RDQML) = (0:0:0,0:0:0); @@ -2860,7 +2989,7 @@ endmodule module RDQMH ( input PADDO, output RDQMH ); - mjiobuf0084 RDQMH_pad( .I(PADDO), .PAD(RDQMH)); + mjiobuf0081 RDQMH_pad( .I(PADDO), .PAD(RDQMH)); specify (PADDO => RDQMH) = (0:0:0,0:0:0); @@ -2870,7 +2999,7 @@ endmodule module nRCAS ( input PADDO, output nRCAS ); - mjiobuf0084 nRCAS_pad( .I(PADDO), .PAD(nRCAS)); + mjiobuf0081 nRCAS_pad( .I(PADDO), .PAD(nRCAS)); specify (PADDO => nRCAS) = (0:0:0,0:0:0); @@ -2880,7 +3009,7 @@ endmodule module nRRAS ( input PADDO, output nRRAS ); - mjiobuf0084 nRRAS_pad( .I(PADDO), .PAD(nRRAS)); + mjiobuf0081 nRRAS_pad( .I(PADDO), .PAD(nRRAS)); specify (PADDO => nRRAS) = (0:0:0,0:0:0); @@ -2890,7 +3019,7 @@ endmodule module nRWE ( input PADDO, output nRWE ); - mjiobuf0084 nRWE_pad( .I(PADDO), .PAD(nRWE)); + mjiobuf0081 nRWE_pad( .I(PADDO), .PAD(nRWE)); specify (PADDO => nRWE) = (0:0:0,0:0:0); @@ -2900,7 +3029,7 @@ endmodule module RCKE ( input PADDO, output RCKE ); - mjiobuf0084 RCKE_pad( .I(PADDO), .PAD(RCKE)); + mjiobuf0081 RCKE_pad( .I(PADDO), .PAD(RCKE)); specify (PADDO => RCKE) = (0:0:0,0:0:0); @@ -2910,7 +3039,7 @@ endmodule module RCLK ( output PADDI, input RCLK ); - mjiobuf0083 RCLK_pad( .Z(PADDI), .PAD(RCLK)); + mjiobuf0080 RCLK_pad( .Z(PADDI), .PAD(RCLK)); specify (RCLK => PADDI) = (0:0:0,0:0:0); @@ -2922,7 +3051,7 @@ endmodule module nRCS ( input PADDO, output nRCS ); - mjiobuf0084 nRCS_pad( .I(PADDO), .PAD(nRCS)); + mjiobuf0081 nRCS_pad( .I(PADDO), .PAD(nRCS)); specify (PADDO => nRCS) = (0:0:0,0:0:0); @@ -3030,7 +3159,7 @@ endmodule module RA_11_ ( input PADDO, output RA11 ); - mjiobuf0084 \RA_pad[11] ( .I(PADDO), .PAD(RA11)); + mjiobuf0081 \RA_pad[11] ( .I(PADDO), .PAD(RA11)); specify (PADDO => RA11) = (0:0:0,0:0:0); @@ -3040,7 +3169,7 @@ endmodule module RA_10_ ( input PADDO, output RA10 ); - mjiobuf0084 \RA_pad[10] ( .I(PADDO), .PAD(RA10)); + mjiobuf0081 \RA_pad[10] ( .I(PADDO), .PAD(RA10)); specify (PADDO => RA10) = (0:0:0,0:0:0); @@ -3050,7 +3179,7 @@ endmodule module RA_9_ ( input PADDO, output RA9 ); - mjiobuf0084 \RA_pad[9] ( .I(PADDO), .PAD(RA9)); + mjiobuf0081 \RA_pad[9] ( .I(PADDO), .PAD(RA9)); specify (PADDO => RA9) = (0:0:0,0:0:0); @@ -3060,7 +3189,7 @@ endmodule module RA_8_ ( input PADDO, output RA8 ); - mjiobuf0084 \RA_pad[8] ( .I(PADDO), .PAD(RA8)); + mjiobuf0081 \RA_pad[8] ( .I(PADDO), .PAD(RA8)); specify (PADDO => RA8) = (0:0:0,0:0:0); @@ -3070,7 +3199,7 @@ endmodule module RA_7_ ( input PADDO, output RA7 ); - mjiobuf0084 \RA_pad[7] ( .I(PADDO), .PAD(RA7)); + mjiobuf0081 \RA_pad[7] ( .I(PADDO), .PAD(RA7)); specify (PADDO => RA7) = (0:0:0,0:0:0); @@ -3080,7 +3209,7 @@ endmodule module RA_6_ ( input PADDO, output RA6 ); - mjiobuf0084 \RA_pad[6] ( .I(PADDO), .PAD(RA6)); + mjiobuf0081 \RA_pad[6] ( .I(PADDO), .PAD(RA6)); specify (PADDO => RA6) = (0:0:0,0:0:0); @@ -3090,7 +3219,7 @@ endmodule module RA_5_ ( input PADDO, output RA5 ); - mjiobuf0084 \RA_pad[5] ( .I(PADDO), .PAD(RA5)); + mjiobuf0081 \RA_pad[5] ( .I(PADDO), .PAD(RA5)); specify (PADDO => RA5) = (0:0:0,0:0:0); @@ -3100,7 +3229,7 @@ endmodule module RA_4_ ( input PADDO, output RA4 ); - mjiobuf0084 \RA_pad[4] ( .I(PADDO), .PAD(RA4)); + mjiobuf0081 \RA_pad[4] ( .I(PADDO), .PAD(RA4)); specify (PADDO => RA4) = (0:0:0,0:0:0); @@ -3110,7 +3239,7 @@ endmodule module RA_3_ ( input PADDO, output RA3 ); - mjiobuf0084 \RA_pad[3] ( .I(PADDO), .PAD(RA3)); + mjiobuf0081 \RA_pad[3] ( .I(PADDO), .PAD(RA3)); specify (PADDO => RA3) = (0:0:0,0:0:0); @@ -3120,7 +3249,7 @@ endmodule module RA_2_ ( input PADDO, output RA2 ); - mjiobuf0084 \RA_pad[2] ( .I(PADDO), .PAD(RA2)); + mjiobuf0081 \RA_pad[2] ( .I(PADDO), .PAD(RA2)); specify (PADDO => RA2) = (0:0:0,0:0:0); @@ -3130,7 +3259,7 @@ endmodule module RA_1_ ( input PADDO, output RA1 ); - mjiobuf0084 \RA_pad[1] ( .I(PADDO), .PAD(RA1)); + mjiobuf0081 \RA_pad[1] ( .I(PADDO), .PAD(RA1)); specify (PADDO => RA1) = (0:0:0,0:0:0); @@ -3140,7 +3269,7 @@ endmodule module RA_0_ ( input PADDO, output RA0 ); - mjiobuf0084 \RA_pad[0] ( .I(PADDO), .PAD(RA0)); + mjiobuf0081 \RA_pad[0] ( .I(PADDO), .PAD(RA0)); specify (PADDO => RA0) = (0:0:0,0:0:0); @@ -3150,7 +3279,7 @@ endmodule module RBA_1_ ( input PADDO, output RBA1 ); - mjiobuf0084 \RBA_pad[1] ( .I(PADDO), .PAD(RBA1)); + mjiobuf0081 \RBA_pad[1] ( .I(PADDO), .PAD(RBA1)); specify (PADDO => RBA1) = (0:0:0,0:0:0); @@ -3160,7 +3289,7 @@ endmodule module RBA_0_ ( input PADDO, output RBA0 ); - mjiobuf0084 \RBA_pad[0] ( .I(PADDO), .PAD(RBA0)); + mjiobuf0081 \RBA_pad[0] ( .I(PADDO), .PAD(RBA0)); specify (PADDO => RBA0) = (0:0:0,0:0:0); @@ -3170,7 +3299,7 @@ endmodule module LED ( input PADDO, output LED ); - mjiobuf0085 LED_pad( .I(PADDO), .PAD(LED)); + mjiobuf0082 LED_pad( .I(PADDO), .PAD(LED)); specify (PADDO => LED) = (0:0:0,0:0:0); @@ -3178,14 +3307,14 @@ module LED ( input PADDO, output LED ); endmodule -module mjiobuf0085 ( input I, output PAD ); +module mjiobuf0082 ( input I, output PAD ); OB INST5( .I(I), .O(PAD)); endmodule module nFWE ( output PADDI, input nFWE ); - mjiobuf0083 nFWE_pad( .Z(PADDI), .PAD(nFWE)); + mjiobuf0080 nFWE_pad( .Z(PADDI), .PAD(nFWE)); specify (nFWE => PADDI) = (0:0:0,0:0:0); @@ -3197,7 +3326,7 @@ endmodule module nCRAS ( output PADDI, input nCRAS ); - mjiobuf0083 nCRAS_pad( .Z(PADDI), .PAD(nCRAS)); + mjiobuf0080 nCRAS_pad( .Z(PADDI), .PAD(nCRAS)); specify (nCRAS => PADDI) = (0:0:0,0:0:0); @@ -3209,7 +3338,7 @@ endmodule module nCCAS ( output PADDI, input nCCAS ); - mjiobuf0083 nCCAS_pad( .Z(PADDI), .PAD(nCCAS)); + mjiobuf0080 nCCAS_pad( .Z(PADDI), .PAD(nCCAS)); specify (nCCAS => PADDI) = (0:0:0,0:0:0); @@ -3221,7 +3350,7 @@ endmodule module Dout_7_ ( input PADDO, output Dout7 ); - mjiobuf0082 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7)); + mjiobuf0079 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7)); specify (PADDO => Dout7) = (0:0:0,0:0:0); @@ -3231,7 +3360,7 @@ endmodule module Dout_6_ ( input PADDO, output Dout6 ); - mjiobuf0082 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6)); + mjiobuf0079 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6)); specify (PADDO => Dout6) = (0:0:0,0:0:0); @@ -3241,7 +3370,7 @@ endmodule module Dout_5_ ( input PADDO, output Dout5 ); - mjiobuf0082 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5)); + mjiobuf0079 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5)); specify (PADDO => Dout5) = (0:0:0,0:0:0); @@ -3251,7 +3380,7 @@ endmodule module Dout_4_ ( input PADDO, output Dout4 ); - mjiobuf0082 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4)); + mjiobuf0079 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4)); specify (PADDO => Dout4) = (0:0:0,0:0:0); @@ -3261,7 +3390,7 @@ endmodule module Dout_3_ ( input PADDO, output Dout3 ); - mjiobuf0082 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3)); + mjiobuf0079 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3)); specify (PADDO => Dout3) = (0:0:0,0:0:0); @@ -3271,7 +3400,7 @@ endmodule module Dout_2_ ( input PADDO, output Dout2 ); - mjiobuf0082 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2)); + mjiobuf0079 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2)); specify (PADDO => Dout2) = (0:0:0,0:0:0); @@ -3281,7 +3410,7 @@ endmodule module Dout_1_ ( input PADDO, output Dout1 ); - mjiobuf0082 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1)); + mjiobuf0079 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1)); specify (PADDO => Dout1) = (0:0:0,0:0:0); @@ -3291,7 +3420,7 @@ endmodule module Din_7_ ( output PADDI, input Din7 ); - mjiobuf0083 \Din_pad[7] ( .Z(PADDI), .PAD(Din7)); + mjiobuf0080 \Din_pad[7] ( .Z(PADDI), .PAD(Din7)); specify (Din7 => PADDI) = (0:0:0,0:0:0); @@ -3303,7 +3432,7 @@ endmodule module Din_6_ ( output PADDI, input Din6 ); - mjiobuf0083 \Din_pad[6] ( .Z(PADDI), .PAD(Din6)); + mjiobuf0080 \Din_pad[6] ( .Z(PADDI), .PAD(Din6)); specify (Din6 => PADDI) = (0:0:0,0:0:0); @@ -3315,7 +3444,7 @@ endmodule module Din_5_ ( output PADDI, input Din5 ); - mjiobuf0083 \Din_pad[5] ( .Z(PADDI), .PAD(Din5)); + mjiobuf0080 \Din_pad[5] ( .Z(PADDI), .PAD(Din5)); specify (Din5 => PADDI) = (0:0:0,0:0:0); @@ -3327,7 +3456,7 @@ endmodule module Din_4_ ( output PADDI, input Din4 ); - mjiobuf0083 \Din_pad[4] ( .Z(PADDI), .PAD(Din4)); + mjiobuf0080 \Din_pad[4] ( .Z(PADDI), .PAD(Din4)); specify (Din4 => PADDI) = (0:0:0,0:0:0); @@ -3339,7 +3468,7 @@ endmodule module Din_3_ ( output PADDI, input Din3 ); - mjiobuf0083 \Din_pad[3] ( .Z(PADDI), .PAD(Din3)); + mjiobuf0080 \Din_pad[3] ( .Z(PADDI), .PAD(Din3)); specify (Din3 => PADDI) = (0:0:0,0:0:0); @@ -3351,7 +3480,7 @@ endmodule module Din_2_ ( output PADDI, input Din2 ); - mjiobuf0083 \Din_pad[2] ( .Z(PADDI), .PAD(Din2)); + mjiobuf0080 \Din_pad[2] ( .Z(PADDI), .PAD(Din2)); specify (Din2 => PADDI) = (0:0:0,0:0:0); @@ -3363,7 +3492,7 @@ endmodule module Din_1_ ( output PADDI, input Din1 ); - mjiobuf0083 \Din_pad[1] ( .Z(PADDI), .PAD(Din1)); + mjiobuf0080 \Din_pad[1] ( .Z(PADDI), .PAD(Din1)); specify (Din1 => PADDI) = (0:0:0,0:0:0); @@ -3375,7 +3504,7 @@ endmodule module Din_0_ ( output PADDI, input Din0 ); - mjiobuf0083 \Din_pad[0] ( .Z(PADDI), .PAD(Din0)); + mjiobuf0080 \Din_pad[0] ( .Z(PADDI), .PAD(Din0)); specify (Din0 => PADDI) = (0:0:0,0:0:0); @@ -3387,7 +3516,7 @@ endmodule module CROW_1_ ( output PADDI, input CROW1 ); - mjiobuf0083 \CROW_pad[1] ( .Z(PADDI), .PAD(CROW1)); + mjiobuf0080 \CROW_pad[1] ( .Z(PADDI), .PAD(CROW1)); specify (CROW1 => PADDI) = (0:0:0,0:0:0); @@ -3399,7 +3528,7 @@ endmodule module CROW_0_ ( output PADDI, input CROW0 ); - mjiobuf0083 \CROW_pad[0] ( .Z(PADDI), .PAD(CROW0)); + mjiobuf0080 \CROW_pad[0] ( .Z(PADDI), .PAD(CROW0)); specify (CROW0 => PADDI) = (0:0:0,0:0:0); @@ -3411,7 +3540,7 @@ endmodule module MAin_9_ ( output PADDI, input MAin9 ); - mjiobuf0083 \MAin_pad[9] ( .Z(PADDI), .PAD(MAin9)); + mjiobuf0080 \MAin_pad[9] ( .Z(PADDI), .PAD(MAin9)); specify (MAin9 => PADDI) = (0:0:0,0:0:0); @@ -3423,7 +3552,7 @@ endmodule module MAin_8_ ( output PADDI, input MAin8 ); - mjiobuf0083 \MAin_pad[8] ( .Z(PADDI), .PAD(MAin8)); + mjiobuf0080 \MAin_pad[8] ( .Z(PADDI), .PAD(MAin8)); specify (MAin8 => PADDI) = (0:0:0,0:0:0); @@ -3435,7 +3564,7 @@ endmodule module MAin_7_ ( output PADDI, input MAin7 ); - mjiobuf0083 \MAin_pad[7] ( .Z(PADDI), .PAD(MAin7)); + mjiobuf0080 \MAin_pad[7] ( .Z(PADDI), .PAD(MAin7)); specify (MAin7 => PADDI) = (0:0:0,0:0:0); @@ -3447,7 +3576,7 @@ endmodule module MAin_6_ ( output PADDI, input MAin6 ); - mjiobuf0083 \MAin_pad[6] ( .Z(PADDI), .PAD(MAin6)); + mjiobuf0080 \MAin_pad[6] ( .Z(PADDI), .PAD(MAin6)); specify (MAin6 => PADDI) = (0:0:0,0:0:0); @@ -3459,7 +3588,7 @@ endmodule module MAin_5_ ( output PADDI, input MAin5 ); - mjiobuf0083 \MAin_pad[5] ( .Z(PADDI), .PAD(MAin5)); + mjiobuf0080 \MAin_pad[5] ( .Z(PADDI), .PAD(MAin5)); specify (MAin5 => PADDI) = (0:0:0,0:0:0); @@ -3471,7 +3600,7 @@ endmodule module MAin_4_ ( output PADDI, input MAin4 ); - mjiobuf0083 \MAin_pad[4] ( .Z(PADDI), .PAD(MAin4)); + mjiobuf0080 \MAin_pad[4] ( .Z(PADDI), .PAD(MAin4)); specify (MAin4 => PADDI) = (0:0:0,0:0:0); @@ -3483,7 +3612,7 @@ endmodule module MAin_3_ ( output PADDI, input MAin3 ); - mjiobuf0083 \MAin_pad[3] ( .Z(PADDI), .PAD(MAin3)); + mjiobuf0080 \MAin_pad[3] ( .Z(PADDI), .PAD(MAin3)); specify (MAin3 => PADDI) = (0:0:0,0:0:0); @@ -3495,7 +3624,7 @@ endmodule module MAin_2_ ( output PADDI, input MAin2 ); - mjiobuf0083 \MAin_pad[2] ( .Z(PADDI), .PAD(MAin2)); + mjiobuf0080 \MAin_pad[2] ( .Z(PADDI), .PAD(MAin2)); specify (MAin2 => PADDI) = (0:0:0,0:0:0); @@ -3507,7 +3636,7 @@ endmodule module MAin_1_ ( output PADDI, input MAin1 ); - mjiobuf0083 \MAin_pad[1] ( .Z(PADDI), .PAD(MAin1)); + mjiobuf0080 \MAin_pad[1] ( .Z(PADDI), .PAD(MAin1)); specify (MAin1 => PADDI) = (0:0:0,0:0:0); @@ -3519,7 +3648,7 @@ endmodule module MAin_0_ ( output PADDI, input MAin0 ); - mjiobuf0083 \MAin_pad[0] ( .Z(PADDI), .PAD(MAin0)); + mjiobuf0080 \MAin_pad[0] ( .Z(PADDI), .PAD(MAin0)); specify (MAin0 => PADDI) = (0:0:0,0:0:0); diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mrp.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mrp.html index 9b206c4..bfb6c3c 100644 --- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mrp.html +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mrp.html @@ -23,17 +23,17 @@ Target Vendor: LATTICE Target Device: LCMXO640CTQFP100 Target Performance: 3 Mapper: mj5g00, version: Diamond (64-bit) 3.12.1.454 -Mapped on: 09/21/23 05:38:31 +Mapped on: 01/06/24 06:25:09 Design Summary Number of PFU registers: 92 out of 640 (14%) - Number of SLICEs: 69 out of 320 (22%) - SLICEs as Logic/ROM: 69 out of 320 (22%) + Number of SLICEs: 76 out of 320 (24%) + SLICEs as Logic/ROM: 76 out of 320 (24%) SLICEs as RAM: 0 out of 192 (0%) SLICEs as Carry: 9 out of 320 (3%) - Number of LUT4s: 137 out of 640 (21%) - Number used as logic LUTs: 119 + Number of LUT4s: 151 out of 640 (24%) + Number used as logic LUTs: 133 Number used as distributed RAM: 0 Number used as ripple logic: 18 Number used as shift registers: 0 @@ -56,28 +56,29 @@ Mapped on: 09/21/23 05:38:31 Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS ) Number of Clock Enables: 5 Net XOR8MEG18: 3 loads, 3 LSLICEs - Net N_31: 1 loads, 1 LSLICEs - Net N_33: 1 loads, 1 LSLICEs - Net N_159_i: 2 loads, 2 LSLICEs + Net N_24: 1 loads, 1 LSLICEs + Net N_26: 1 loads, 1 LSLICEs + Net N_153_i: 2 loads, 2 LSLICEs Net CmdUFMCLK_1_sqmuxa: 2 loads, 2 LSLICEs - Number of LSRs: 4 + Number of LSRs: 5 Net RA10s_i: 1 loads, 1 LSLICEs Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs - Net RASr2: 2 loads, 2 LSLICEs + Net RASr2: 1 loads, 1 LSLICEs Net Ready_fast: 7 loads, 7 LSLICEs + Net RCKEEN_8_u_0_1_a1_0: 1 loads, 1 LSLICEs Number of nets driven by tri-state buffers: 0 - Top 10 highest fanout non-clock nets: - Net InitReady: 16 loads - Net Ready: 16 loads - Net S[1]: 13 loads - Net CO0: 12 loads + Top 10 highest fanout non-clock nets: + Net Ready: 18 loads + Net InitReady: 17 loads + Net S[1]: 17 loads + Net CO0: 16 loads + Net RASr2: 13 loads Net nRowColSel: 12 loads - Net RASr2: 11 loads Net Din_c[5]: 10 loads Net Din_c[3]: 9 loads Net IS[0]: 9 loads - Net MAin_c[1]: 8 loads + Net IS[1]: 8 loads @@ -126,8 +127,8 @@ Mapped on: 09/21/23 05:38:31 | nRWE | OUTPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | RCKE | OUTPUT | LVCMOS33 | | | -+---------------------+-----------+-----------+------------+------------+ ++---------------------+-----------+-----------+------------+------------+ | RCLK | INPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | nRCS | OUTPUT | LVCMOS33 | | | @@ -183,8 +184,8 @@ Mapped on: 09/21/23 05:38:31 | nCCAS | INPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | Dout[7] | OUTPUT | LVCMOS33 | | | -+---------------------+-----------+-----------+------------+------------+ ++---------------------+-----------+-----------+------------+------------+ | Dout[6] | OUTPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | Dout[5] | OUTPUT | LVCMOS33 | | | @@ -243,7 +244,6 @@ Mapped on: 09/21/23 05:38:31 - Removed logic Block GSR_INST undriven or does not drive anything - clipped. @@ -252,7 +252,6 @@ Signal nFWE_c_i was merged into signal nFWE_c Signal nCRAS_c_i_0 was merged into signal nCRAS_c Signal nCCAS_c_i was merged into signal nCCAS_c Signal Ready_fast_i was merged into signal Ready_fast -Signal IS_i[0] was merged into signal IS[0] Signal RASr2_i was merged into signal RASr2 Signal XOR8MEG.CN was merged into signal PHI2_c Signal GND undriven or does not drive anything - clipped. @@ -272,8 +271,7 @@ Block nFWE_pad_RNI420B was optimized away. Block RASr_RNO was optimized away. Block nCCAS_pad_RNISUR8 was optimized away. Block Ready_fast_RNI29NA was optimized away. -Block IS_i[0] was optimized away. -Block RASr2_RNIAFR1 was optimized away. +Block S_RNO[1] was optimized away. Block XOR8MEG.CN was optimized away. Block GND was optimized away. Block VCC was optimized away. @@ -304,6 +302,8 @@ Block VCC was optimized away. + + Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_pad.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_pad.html index 0d6d53a..b0b7eb2 100644 --- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_pad.html +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_pad.html @@ -14,7 +14,7 @@ Performance Grade: 3 PACKAGE: TQFP100 Package Status: Final Version 1.17 -Thu Sep 21 05:38:41 2023 +Sat Jan 06 06:25:19 2024 Pinout by Port Name: +-----------+----------+---------------+-------+----------------------------------+ @@ -358,7 +358,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Thu Sep 21 05:38:41 2023 +Sat Jan 06 06:25:19 2024 diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_par.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_par.html index 930c9e0..1795003 100644 --- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_par.html +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_par.html @@ -12,7 +12,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Thu Sep 21 05:38:33 2023 +Sat Jan 06 06:25:12 2024 C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO640C_impl1.p2t RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir @@ -26,17 +26,17 @@ Preference file: RAM2GS_LCMXO640C_impl1.prf. Level/ Number Worst Timing Worst Timing Run NCD Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status ---------- -------- ----- ------ ----------- ----------- ---- ------ -5_1 * 0 7.336 0 0.273 0 09 Completed +5_1 * 0 7.529 0 0.273 0 08 Completed * : Design saved. -Total (real) run time for 1-seed: 9 secs +Total (real) run time for 1-seed: 8 secs par done! Note: user must run 'Trace' for timing closure signoff. Lattice Place and Route Report for Design "RAM2GS_LCMXO640C_impl1_map.ncd" -Thu Sep 21 05:38:33 2023 +Sat Jan 06 06:25:12 2024 Best Par Run @@ -65,12 +65,12 @@ Ignore Preference Error(s): True PIO (prelim) 67/159 42% used 67/74 90% bonded - SLICE 69/320 21% used + SLICE 76/320 23% used -Number of Signals: 251 -Number of Connections: 633 +Number of Signals: 266 +Number of Connections: 681 Pin Constraint Summary: 67 out of 67 pins locked (100% locked). @@ -84,18 +84,18 @@ The following 1 signal is selected to use the secondary clock routing resources: No signal is selected as Global Set/Reset. Starting Placer Phase 0. -......... +....... Finished Placer Phase 0. REAL time: 0 secs Starting Placer Phase 1. -............. -Placer score = 956294. -Finished Placer Phase 1. REAL time: 7 secs +............... +Placer score = 758162. +Finished Placer Phase 1. REAL time: 6 secs Starting Placer Phase 2. . -Placer score = 953137 -Finished Placer Phase 2. REAL time: 8 secs +Placer score = 756179 +Finished Placer Phase 2. REAL time: 7 secs @@ -132,11 +132,11 @@ I/O Bank Usage Summary: | 3 | 18 / 21 ( 85%) | 3.3V | - | - | +----------+----------------+------------+------------+------------+ -Total placer CPU time: 7 secs +Total placer CPU time: 6 secs Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd. -0 connections routed; 633 unrouted. +0 connections routed; 681 unrouted. Starting router resource preassignment WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew. WARNING - par: The driver of secondary clock net nCRAS_c is not placed on one of the PIO sites dedicated for secondary clocks. This secondary clock will be routed through general routing resource and may suffer from excessive delay or skew. @@ -144,9 +144,9 @@ WARNING - par: The driver of secondary clock net nCRAS_c is not placed on one of WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. Signal=nCCAS_c loads=8 clock_loads=4 -Completed router resource preassignment. Real time: 8 secs +Completed router resource preassignment. Real time: 7 secs -Start NBR router at 05:38:41 09/21/23 +Start NBR router at 06:25:19 01/06/24 ***************************************************************** Info: NBR allows conflicts(one node used by more than one signal) @@ -161,44 +161,50 @@ Note: NBR uses a different method to calculate timing slacks. The your design. ***************************************************************** -Start NBR special constraint process at 05:38:41 09/21/23 +Start NBR special constraint process at 06:25:19 01/06/24 -Start NBR section for initial routing at 05:38:41 09/21/23 +Start NBR section for initial routing at 06:25:19 01/06/24 Level 1, iteration 1 -1(0.00%) conflict; 548(86.57%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 7.325ns/0.000ns; real time: 8 secs +0(0.00%) conflict; 596(87.52%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack<setup>: 7.600ns/0.000ns; real time: 7 secs Level 2, iteration 1 -1(0.00%) conflict; 543(85.78%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 7.532ns/0.000ns; real time: 8 secs +0(0.00%) conflict; 592(86.93%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack<setup>: 7.684ns/0.000ns; real time: 7 secs Level 3, iteration 1 -0(0.00%) conflict; 542(85.62%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 7.449ns/0.000ns; real time: 8 secs +0(0.00%) conflict; 592(86.93%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack<setup>: 7.684ns/0.000ns; real time: 7 secs Level 4, iteration 1 8(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 7.336ns/0.000ns; real time: 8 secs +Estimated worst slack/total negative slack<setup>: 7.653ns/0.000ns; real time: 7 secs Info: Initial congestion level at 75% usage is 0 Info: Initial congestion area at 75% usage is 0 (0.00%) -Start NBR section for normal routing at 05:38:41 09/21/23 +Start NBR section for normal routing at 06:25:19 01/06/24 Level 4, iteration 1 -5(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 7.336ns/0.000ns; real time: 8 secs +2(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack<setup>: 7.653ns/0.000ns; real time: 7 secs Level 4, iteration 2 1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 7.336ns/0.000ns; real time: 8 secs +Estimated worst slack/total negative slack<setup>: 7.653ns/0.000ns; real time: 7 secs Level 4, iteration 3 +1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack<setup>: 7.653ns/0.000ns; real time: 7 secs +Level 4, iteration 4 +1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack<setup>: 7.653ns/0.000ns; real time: 7 secs +Level 4, iteration 5 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 7.336ns/0.000ns; real time: 9 secs +Estimated worst slack/total negative slack<setup>: 7.529ns/0.000ns; real time: 7 secs -Start NBR section for setup/hold timing optimization with effort level 3 at 05:38:42 09/21/23 +Start NBR section for setup/hold timing optimization with effort level 3 at 06:25:19 01/06/24 -Start NBR section for re-routing at 05:38:42 09/21/23 +Start NBR section for re-routing at 06:25:20 01/06/24 Level 4, iteration 1 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 7.336ns/0.000ns; real time: 9 secs +Estimated worst slack/total negative slack<setup>: 7.529ns/0.000ns; real time: 8 secs -Start NBR section for post-routing at 05:38:42 09/21/23 +Start NBR section for post-routing at 06:25:20 01/06/24 End NBR router with 0 unrouted connection @@ -206,7 +212,7 @@ NBR Summary ----------- Number of unrouted connections : 0 (0.00%) Number of connections with timing violations : 0 (0.00%) - Estimated worst slack<setup> : 7.336ns + Estimated worst slack<setup> : 7.529ns Timing score<setup> : 0 ----------- Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. @@ -216,10 +222,10 @@ Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. Signal=nCCAS_c loads=8 clock_loads=4 -Total CPU time 8 secs -Total REAL time: 9 secs +Total CPU time 7 secs +Total REAL time: 8 secs Completely routed. -End of route. 633 routed (100.00%); 0 unrouted. +End of route. 681 routed (100.00%); 0 unrouted. Hold time timing score: 0, hold timing errors: 0 @@ -233,14 +239,14 @@ All signals are completely routed. PAR_SUMMARY::Run status = Completed PAR_SUMMARY::Number of unrouted conns = 0 -PAR_SUMMARY::Worst slack<setup/<ns>> = 7.336 +PAR_SUMMARY::Worst slack<setup/<ns>> = 7.529 PAR_SUMMARY::Timing score<setup/<ns>> = 0.000 PAR_SUMMARY::Worst slack<hold /<ns>> = 0.273 PAR_SUMMARY::Timing score<hold /<ns>> = 0.000 PAR_SUMMARY::Number of errors = 0 Total CPU time to completion: 8 secs -Total REAL time to completion: 9 secs +Total REAL time to completion: 8 secs par done! diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_scck.rpt b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_scck.rpt index c89ff37..0e32176 100644 --- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_scck.rpt +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_scck.rpt @@ -13,7 +13,7 @@ Hostname: ZANEMACWIN11 Implementation : impl1 -# Written on Thu Sep 21 05:38:22 2023 +# Written on Sat Jan 6 06:25:02 2024 ##### FILES SYNTAX CHECKED ############################################## Constraint File(s): "\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc" diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_summary.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_summary.html index 3429a2e..5b5a3e7 100644 --- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_summary.html +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_summary.html @@ -62,7 +62,7 @@ Updated: -2023/09/21 05:38:50 +2024/01/06 06:25:27 Implementation Location: diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_synplify.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_synplify.html index f3a7e3f..758b553 100644 --- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_synplify.html +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_synplify.html @@ -12,7 +12,7 @@ #OS: Windows 8 6.2 #Hostname: ZANEMACWIN11 -# Thu Sep 21 05:38:18 2023 +# Sat Jan 6 06:25:00 2024 #Implementation: impl1 @@ -59,19 +59,22 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-SPI.v" (library work) Verilog syntax check successful! + +Compiler output is up to date. No re-compile necessary + Selecting top level module RAM2GS @N: CG364 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work. Running optimization stage 1 on RAM2GS ....... -Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB) +Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 100MB) Running optimization stage 2 on RAM2GS ....... -Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 100MB) +Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB) -At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 96MB peak: 97MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Sep 21 05:38:19 2023 +# Sat Jan 6 06:25:00 2024 ###########################################################] ###########################################################[ @@ -98,7 +101,7 @@ At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Sep 21 05:38:19 2023 +# Sat Jan 6 06:25:00 2024 ###########################################################] @@ -113,7 +116,7 @@ At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Sep 21 05:38:19 2023 +# Sat Jan 6 06:25:00 2024 ###########################################################] ###########################################################[ @@ -134,18 +137,17 @@ Implementation : impl1 Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ @N|Running in 64-bit mode +File \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Sep 21 05:38:21 2023 +# Sat Jan 6 06:25:01 2024 ###########################################################] -Premap Report - -# Thu Sep 21 05:38:21 2023 +# Sat Jan 6 06:25:02 2024 Copyright (C) 1994-2021 Synopsys, Inc. @@ -179,13 +181,13 @@ See clock summary report "\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_ Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) -Start loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB) +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB) -Finished loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 151MB) +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 151MB) @N: FX493 |Applying initial value "0" on instance InitReady. @W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. @@ -195,7 +197,6 @@ Finished loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h @N: FX493 |Applying initial value "0" on instance CmdLEDEN. @N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN. @N: FX493 |Applying initial value "1" on instance nRCS. -@N: FX493 |Applying initial value "0" on instance LEDEN. @N: FX493 |Applying initial value "0" on instance n8MEGEN. @N: FX493 |Applying initial value "1" on instance nRRAS. @N: FX493 |Applying initial value "0" on instance CmdUFMCLK. @@ -211,20 +212,20 @@ Finished loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h @N: FX493 |Applying initial value "0" on instance CmdEnable. @N: FX493 |Applying initial value "1" on instance nRWE. -Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) +Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) -Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) +Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) -Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 181MB peak: 181MB) +Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) -Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 181MB peak: 181MB) +Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) @N: FX1184 |Applying syn_allowed_resources blockrams=0 on top level netlist RAM2GS -Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 181MB peak: 181MB) +Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) @@ -291,25 +292,23 @@ Clock Tree ID Driving Element Drive Element Type Fanout Sample I @N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. -Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB) +Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB) -Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB) +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB) -Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB) +Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB) Pre-mapping successful! -At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 98MB peak: 184MB) +At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 184MB) -Process took 0h:00m:02s realtime, 0h:00m:01s cputime -# Thu Sep 21 05:38:23 2023 +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Sat Jan 6 06:25:03 2024 ###########################################################] -Map & Optimize Report - -# Thu Sep 21 05:38:24 2023 +# Sat Jan 6 06:25:03 2024 Copyright (C) 1994-2021 Synopsys, Inc. @@ -328,29 +327,29 @@ Implementation : impl1 Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @ -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB) +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB) @N: MF916 |Option synthesis_strategy=base is enabled. @N: MF248 |Running in 64-bit mode. @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 140MB) +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB) -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 140MB) +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB) -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB) +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB) -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 147MB) +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB) -Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 179MB peak: 179MB) +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 178MB peak: 178MB) -Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) +Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB) @N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":147:4:147:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] @N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":134:4:134:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] @@ -363,7 +362,7 @@ Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00 Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 184MB peak: 184MB) -Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB) +Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 185MB peak: 185MB) Available hyper_sources - for debug and ip models @@ -376,10 +375,10 @@ Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CP Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 187MB) -Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 187MB) +Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB) -Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 188MB) +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB) Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB) @@ -389,51 +388,48 @@ Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:0 Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ - 1 0h:00m:01s -3.26ns 127 / 89 - 2 0h:00m:01s -3.23ns 123 / 89 - 3 0h:00m:01s -3.23ns 123 / 89 - 4 0h:00m:01s -3.23ns 123 / 89 - 5 0h:00m:01s -3.23ns 124 / 89 - 6 0h:00m:01s -3.23ns 124 / 89 -@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 7 loads 1 time to improve timing. -@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing. -@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":147:4:147:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 15 loads 1 time to improve timing. + 1 0h:00m:01s -4.01ns 133 / 89 + 2 0h:00m:01s -3.96ns 131 / 89 +@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 8 loads 1 time to improve timing. +@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 7 loads 1 time to improve timing. +@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":147:4:147:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 19 loads 1 time to improve timing. Timing driven replication report Added 3 Registers via timing driven replication Added 1 LUTs via timing driven replication - 7 0h:00m:02s -2.99ns 128 / 92 + 3 0h:00m:02s -3.08ns 143 / 92 + 4 0h:00m:02s -3.08ns 141 / 92 - 8 0h:00m:02s -2.99ns 127 / 92 - 9 0h:00m:02s -3.09ns 127 / 92 - 10 0h:00m:02s -3.19ns 127 / 92 - 11 0h:00m:02s -3.19ns 127 / 92 - 12 0h:00m:02s -3.19ns 127 / 92 + 5 0h:00m:02s -3.08ns 140 / 92 + 6 0h:00m:02s -3.19ns 140 / 92 + 7 0h:00m:02s -3.19ns 140 / 92 + 8 0h:00m:02s -3.19ns 140 / 92 + 9 0h:00m:02s -3.19ns 140 / 92 -Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 190MB) +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 191MB) -Finished restoring hierarchy (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 190MB) +Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 191MB) -Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 154MB peak: 191MB) +Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 155MB peak: 192MB) Writing Analyst data base \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_m.srm -Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 191MB peak: 191MB) +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 192MB peak: 192MB) Writing EDIF Netlist and constraint files @N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.edi @N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF -Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 196MB peak: 196MB) +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 197MB peak: 197MB) -Finished Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 196MB peak: 196MB) +Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 197MB peak: 197MB) -Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 194MB peak: 196MB) +Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 195MB peak: 197MB) @N: MT615 |Found clock RCLK with period 16.00ns @N: MT615 |Found clock PHI2 with period 350.00ns @@ -442,7 +438,7 @@ Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:0 ##### START OF TIMING REPORT #####[ -# Timing report written on Thu Sep 21 05:38:29 2023 +# Timing report written on Sat Jan 6 06:25:08 2024 # @@ -475,8 +471,8 @@ nCRAS 2.9 MHz 0.6 MHz 350.000 1613.150 -3.60 Estimated period and frequency reported as NA means no slack depends directly on the clock waveform -@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. @W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small. +@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. @W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. @W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small. @W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small. @@ -490,10 +486,10 @@ Clocks | rise to rise | fall to fall | rise to --------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack --------------------------------------------------------------------------------------------------------------- -RCLK RCLK | 16.000 7.560 | No paths - | No paths - | No paths - +RCLK RCLK | 16.000 7.464 | No paths - | No paths - | No paths - RCLK PHI2 | 2.000 -1.216 | No paths - | 1.000 -2.312 | No paths - PHI2 RCLK | No paths - | No paths - | No paths - | 1.000 -3.705 -PHI2 PHI2 | No paths - | 350.000 343.998 | 175.000 166.500 | 175.000 171.784 +PHI2 PHI2 | No paths - | 350.000 344.094 | 175.000 165.215 | 175.000 171.784 nCRAS RCLK | No paths - | No paths - | No paths - | 1.000 -3.609 =============================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. @@ -527,10 +523,10 @@ CmdUFMCS PHI2 FD1P3AX Q CmdUFMCS 1.348 CmdUFMSDI PHI2 FD1P3AX Q CmdUFMSDI 1.348 -3.297 CmdLEDEN PHI2 FD1P3AX Q CmdLEDEN 1.456 -2.216 Cmdn8MEGEN PHI2 FD1P3AX Q Cmdn8MEGEN 1.456 -2.216 -Bank[2] PHI2 FD1S3AX Q Bank[2] 1.348 166.500 -Bank[3] PHI2 FD1S3AX Q Bank[3] 1.348 166.500 -Bank[4] PHI2 FD1S3AX Q Bank[4] 1.348 166.500 -Bank[5] PHI2 FD1S3AX Q Bank[5] 1.348 166.500 +Bank[0] PHI2 FD1S3AX Q Bank[0] 1.348 165.215 +Bank[1] PHI2 FD1S3AX Q Bank[1] 1.348 165.215 +Bank[2] PHI2 FD1S3AX Q Bank[2] 1.348 165.215 +Bank[3] PHI2 FD1S3AX Q Bank[3] 1.348 165.215 ======================================================================================= @@ -544,13 +540,13 @@ Instance Reference Type Pin Net Time UFMCLK PHI2 FD1S3AX D UFMCLK_RNO -0.003 -3.705 UFMSDI PHI2 FD1S3AX D UFMSDI_RNO -0.003 -3.705 nUFMCS PHI2 FD1S3AY D nUFMCS_s_0_N_5_i -0.003 -3.705 -LEDEN PHI2 FD1P3AX SP N_33 0.806 -2.800 -n8MEGEN PHI2 FD1P3AX SP N_31 0.806 -2.800 -LEDEN PHI2 FD1P3AX D N_70 -0.003 -2.216 -n8MEGEN PHI2 FD1P3AX D N_69 -0.003 -2.216 -CmdSubmitted PHI2 FD1S3AX D N_460_0 173.997 166.500 -ADSubmitted PHI2 FD1S3AX D ADSubmitted_r 173.997 167.797 -C1Submitted PHI2 FD1S3AX D C1Submitted_RNO 173.997 167.797 +LEDEN PHI2 FD1P3AX SP N_26 0.806 -2.800 +n8MEGEN PHI2 FD1P3AX SP N_24 0.806 -2.800 +LEDEN PHI2 FD1P3AX D N_49 -0.003 -2.216 +n8MEGEN PHI2 FD1P3AX D N_48 -0.003 -2.216 +CmdEnable PHI2 FD1S3AX D CmdEnable_s 173.997 165.215 +CmdSubmitted PHI2 FD1S3AX D N_428_0 173.997 165.311 +ADSubmitted PHI2 FD1S3AX D ADSubmitted_r 173.997 166.404 ============================================================================================ @@ -582,7 +578,7 @@ CmdSubmitted FD1S3AX Q Out 1.552 1.552 r - CmdSubmitted Net - - - - 3 PHI2r3_RNITCN41 ORCALUT4 A In 0.000 1.552 r - PHI2r3_RNITCN41 ORCALUT4 Z Out 1.393 2.945 r - -N_139_i Net - - - - 3 +N_137_i Net - - - - 3 UFMCLK_RNO ORCALUT4 A In 0.000 2.945 r - UFMCLK_RNO ORCALUT4 Z Out 0.757 3.702 r - UFMCLK_RNO Net - - - - 1 @@ -613,7 +609,7 @@ CmdSubmitted FD1S3AX Q Out 1.552 1.552 r - CmdSubmitted Net - - - - 3 PHI2r3_RNITCN41 ORCALUT4 A In 0.000 1.552 r - PHI2r3_RNITCN41 ORCALUT4 Z Out 1.393 2.945 r - -N_139_i Net - - - - 3 +N_137_i Net - - - - 3 nUFMCS_s_0_N_5_i ORCALUT4 A In 0.000 2.945 r - nUFMCS_s_0_N_5_i ORCALUT4 Z Out 0.757 3.702 r - nUFMCS_s_0_N_5_i Net - - - - 1 @@ -644,7 +640,7 @@ CmdSubmitted FD1S3AX Q Out 1.552 1.552 r - CmdSubmitted Net - - - - 3 PHI2r3_RNITCN41 ORCALUT4 A In 0.000 1.552 r - PHI2r3_RNITCN41 ORCALUT4 Z Out 1.393 2.945 r - -N_139_i Net - - - - 3 +N_137_i Net - - - - 3 UFMSDI_RNO ORCALUT4 A In 0.000 2.945 r - UFMSDI_RNO ORCALUT4 Z Out 0.757 3.702 r - UFMSDI_RNO Net - - - - 1 @@ -663,21 +659,21 @@ Detailed Report for Clock: RCLK Starting Points with Worst Slack ******************************** - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------ -LEDEN RCLK FD1P3AX Q LEDEN 1.552 -2.312 -n8MEGEN RCLK FD1P3AX Q n8MEGEN 1.456 -2.216 -FS[13] RCLK FD1S3AX Q FS[13] 1.552 7.560 -FS[14] RCLK FD1S3AX Q FS[14] 1.552 7.560 -FS[15] RCLK FD1S3AX Q FS[15] 1.552 7.560 -FS[17] RCLK FD1S3AX Q FS[17] 1.552 7.560 -S[1] RCLK FD1S3IX Q S[1] 1.768 8.533 -S[0] RCLK FD1S3IX Q CO0 1.756 8.545 -FS[16] RCLK FD1S3AX Q FS[16] 1.612 8.689 -FS[12] RCLK FD1S3AX Q FS[12] 1.552 8.749 -============================================================================= + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------- +LEDEN RCLK FD1P3AX Q LEDEN 1.552 -2.312 +n8MEGEN RCLK FD1P3AX Q n8MEGEN 1.456 -2.216 +FS[12] RCLK FD1S3AX Q FS[12] 1.552 7.464 +FS[14] RCLK FD1S3AX Q FS[14] 1.552 7.464 +FS[15] RCLK FD1S3AX Q FS[15] 1.552 7.464 +FS[17] RCLK FD1S3AX Q FS[17] 1.552 7.464 +InitReady RCLK FD1S3AX Q InitReady 1.792 8.569 +S[1] RCLK FD1S3IX Q S[1] 1.792 8.569 +S[0] RCLK FD1S3IX Q CO0 1.780 8.581 +FS[13] RCLK FD1S3AX Q FS[13] 1.612 8.593 +================================================================================ Ending Points with Worst Slack @@ -687,16 +683,16 @@ Ending Points with Worst Slack Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------- -CmdLEDEN RCLK FD1P3AX D N_21_i -0.003 -2.312 +CmdLEDEN RCLK FD1P3AX D N_14_i -0.003 -2.312 XOR8MEG RCLK FD1P3AX D XOR8MEG_3 -0.003 -2.312 -Cmdn8MEGEN RCLK FD1P3AX D N_19_i -0.003 -2.216 +Cmdn8MEGEN RCLK FD1P3AX D N_12_i -0.003 -2.216 RA11 RCLK FD1S3IX D RA11_2 0.997 -1.216 -UFMSDI RCLK FD1S3AX D UFMSDI_RNO 14.997 7.560 +UFMSDI RCLK FD1S3AX D UFMSDI_RNO 14.997 7.464 UFMCLK RCLK FD1S3AX D UFMCLK_RNO 14.997 7.668 -LEDEN RCLK FD1P3AX SP N_33 15.806 8.261 -n8MEGEN RCLK FD1P3AX SP N_31 15.806 8.261 -nRCS RCLK FD1S3AY D N_28_i 14.997 8.533 +nRCAS RCLK FD1S3AY D N_46_i 14.997 8.569 nUFMCS RCLK FD1S3AY D nUFMCS_s_0_N_5_i 14.997 8.653 +nRCS RCLK FD1S3AY D N_143_i 14.997 8.881 +LEDEN RCLK FD1P3AX SP N_26 15.806 9.463 ========================================================================================= @@ -726,9 +722,9 @@ Name Type Name Dir Delay Time Fan Out(s --------------------------------------------------------------------------------- LEDEN FD1P3AX Q Out 1.552 1.552 r - LEDEN Net - - - - 3 -CmdLEDEN_RNO ORCALUT4 A In 0.000 1.552 r - +CmdLEDEN_RNO ORCALUT4 B In 0.000 1.552 r - CmdLEDEN_RNO ORCALUT4 Z Out 0.757 2.309 r - -N_21_i Net - - - - 1 +N_14_i Net - - - - 1 CmdLEDEN FD1P3AX D In 0.000 2.309 r - ================================================================================= @@ -749,16 +745,16 @@ Path information for path number 2: The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK The end point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------- -LEDEN FD1P3AX Q Out 1.552 1.552 r - -LEDEN Net - - - - 3 -XOR8MEG_3_u_0_a3_3 ORCALUT4 B In 0.000 1.552 r - -XOR8MEG_3_u_0_a3_3 ORCALUT4 Z Out 0.757 2.309 f - -XOR8MEG_3 Net - - - - 1 -XOR8MEG FD1P3AX D In 0.000 2.309 f - -===================================================================================== +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------------- +LEDEN FD1P3AX Q Out 1.552 1.552 r - +LEDEN Net - - - - 3 +XOR8MEG_3_u_0_a3_0_2 ORCALUT4 B In 0.000 1.552 r - +XOR8MEG_3_u_0_a3_0_2 ORCALUT4 Z Out 0.757 2.309 f - +XOR8MEG_3 Net - - - - 1 +XOR8MEG FD1P3AX D In 0.000 2.309 f - +======================================================================================= Path information for path number 3: @@ -784,7 +780,7 @@ n8MEGEN FD1P3AX Q Out 1.456 1.456 r - n8MEGEN Net - - - - 2 Cmdn8MEGEN_RNO ORCALUT4 C In 0.000 1.456 r - Cmdn8MEGEN_RNO ORCALUT4 Z Out 0.757 2.213 r - -N_19_i Net - - - - 1 +N_12_i Net - - - - 1 Cmdn8MEGEN FD1P3AX D In 0.000 2.213 r - ================================================================================= @@ -804,10 +800,10 @@ Starting Points with Worst Slack Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------- -CBR nCRAS FD1S3AX Q CBR 1.660 -3.609 -CBR_fast nCRAS FD1S3AX Q CBR_fast 1.456 -3.513 +CBR_fast nCRAS FD1S3AX Q CBR_fast 1.552 -3.609 +CBR nCRAS FD1S3AX Q CBR 1.612 -3.561 FWEr nCRAS FD1S3AX Q FWEr 1.552 -3.501 -FWEr_fast nCRAS FD1S3AX Q FWEr_fast 1.456 -3.405 +FWEr_fast nCRAS FD1S3AX Q FWEr_fast 1.552 -3.501 ================================================================================ @@ -818,11 +814,11 @@ Ending Points with Worst Slack Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------- -nRWE nCRAS FD1S3AY D N_39_i -0.003 -3.609 -nRowColSel nCRAS FD1S3IX D nRowColSel_0_0 -0.003 -3.609 -nRCAS nCRAS FD1S3AY D N_37_i -0.003 -3.513 -RCKEEN nCRAS FD1S3AX D RCKEEN_8 -0.003 -3.405 -nRCS nCRAS FD1S3AY D N_28_i -0.003 -3.405 +nRCAS nCRAS FD1S3AY D N_46_i -0.003 -3.609 +nRWE nCRAS FD1S3AY D N_144_i -0.003 -3.609 +nRowColSel nCRAS FD1S3IX D nRowColSel_0_0 -0.003 -3.561 +RCKEEN nCRAS FD1S3AX D RCKEEN_8 -0.003 -3.501 +nRCS nCRAS FD1S3AY D N_143_i -0.003 -3.501 ======================================================================================= @@ -842,24 +838,24 @@ Path information for path number 1: = Slack (non-critical) : -3.609 Number of logic level(s): 2 - Starting point: CBR / Q - Ending point: nRWE / D + Starting point: CBR_fast / Q + Ending point: nRCAS / D The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------- -CBR FD1S3AX Q Out 1.660 1.660 r - -CBR Net - - - - 5 -nRWE_RNO_0 ORCALUT4 A In 0.000 1.660 r - -nRWE_RNO_0 ORCALUT4 Z Out 1.189 2.849 f - -G_17_1 Net - - - - 1 -nRWE_RNO ORCALUT4 B In 0.000 2.849 f - -nRWE_RNO ORCALUT4 Z Out 0.757 3.606 r - -N_39_i Net - - - - 1 -nRWE FD1S3AY D In 0.000 3.606 r - -================================================================================= +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +---------------------------------------------------------------------------------------- +CBR_fast FD1S3AX Q Out 1.552 1.552 r - +CBR_fast Net - - - - 3 +nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 A In 0.000 1.552 r - +nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 Z Out 1.297 2.849 r - +nRCAS_0_sqmuxa_1 Net - - - - 2 +nRCAS_RNO ORCALUT4 C In 0.000 2.849 r - +nRCAS_RNO ORCALUT4 Z Out 0.757 3.606 f - +N_46_i Net - - - - 1 +nRCAS FD1S3AY D In 0.000 3.606 f - +======================================================================================== Path information for path number 2: @@ -873,24 +869,24 @@ Path information for path number 2: = Slack (non-critical) : -3.609 Number of logic level(s): 2 - Starting point: CBR / Q - Ending point: nRowColSel / D + Starting point: CBR_fast / Q + Ending point: nRWE / D The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------- -CBR FD1S3AX Q Out 1.660 1.660 r - -CBR Net - - - - 5 -nRowColSel_0_0_a3_0 ORCALUT4 B In 0.000 1.660 r - -nRowColSel_0_0_a3_0 ORCALUT4 Z Out 1.189 2.849 f - -N_179 Net - - - - 1 -nRowColSel_0_0 ORCALUT4 B In 0.000 2.849 f - -nRowColSel_0_0 ORCALUT4 Z Out 0.757 3.606 f - -nRowColSel_0_0 Net - - - - 1 -nRowColSel FD1S3IX D In 0.000 3.606 f - -====================================================================================== +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +---------------------------------------------------------------------------------------- +CBR_fast FD1S3AX Q Out 1.552 1.552 r - +CBR_fast Net - - - - 3 +nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 A In 0.000 1.552 r - +nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 Z Out 1.297 2.849 r - +nRCAS_0_sqmuxa_1 Net - - - - 2 +nRWE_RNO ORCALUT4 C In 0.000 2.849 r - +nRWE_RNO ORCALUT4 Z Out 0.757 3.606 r - +N_144_i Net - - - - 1 +nRWE FD1S3AY D In 0.000 3.606 r - +======================================================================================== Path information for path number 3: @@ -899,29 +895,29 @@ Path information for path number 3: + Clock delay at ending point: 0.000 (ideal) = Required time: -0.003 - - Propagation time: 3.510 + - Propagation time: 3.558 - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : -3.513 + = Slack (non-critical) : -3.561 Number of logic level(s): 2 - Starting point: CBR_fast / Q + Starting point: CBR / Q Ending point: nRCAS / D The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------- -CBR_fast FD1S3AX Q Out 1.456 1.456 r - -CBR_fast Net - - - - 2 -nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 A In 0.000 1.456 r - -nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 Z Out 1.297 2.753 r - -nRCAS_0_sqmuxa_1 Net - - - - 2 -nRCAS_RNO ORCALUT4 B In 0.000 2.753 r - -nRCAS_RNO ORCALUT4 Z Out 0.757 3.510 f - -N_37_i Net - - - - 1 -nRCAS FD1S3AY D In 0.000 3.510 f - -======================================================================================== +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------- +CBR FD1S3AX Q Out 1.612 1.612 r - +CBR Net - - - - 4 +nRCAS_RNO_1 ORCALUT4 A In 0.000 1.612 r - +nRCAS_RNO_1 ORCALUT4 Z Out 1.189 2.801 f - +G_1_1 Net - - - - 1 +nRCAS_RNO ORCALUT4 B In 0.000 2.801 f - +nRCAS_RNO ORCALUT4 Z Out 0.757 3.558 r - +N_46_i Net - - - - 1 +nRCAS FD1S3AY D In 0.000 3.558 r - +================================================================================= @@ -929,10 +925,10 @@ nRCAS FD1S3AY D In 0.000 3.510 f - Timing exceptions that could not be applied -Finished final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 195MB peak: 196MB) +Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 196MB peak: 197MB) -Finished timing report (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 195MB peak: 196MB) +Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 196MB peak: 197MB) --------------------------------------- Resource Usage Report @@ -953,19 +949,19 @@ FD1S3IX: 14 FD1S3JX: 3 GSR: 1 IB: 26 -INV: 8 +INV: 7 OB: 33 -ORCALUT4: 119 -PFUMX: 2 +ORCALUT4: 133 +PFUMX: 1 PUR: 1 VHI: 1 VLO: 1 Mapper successful! -At Mapper Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 78MB peak: 196MB) +At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 78MB peak: 197MB) -Process took 0h:00m:05s realtime, 0h:00m:04s cputime -# Thu Sep 21 05:38:29 2023 +Process took 0h:00m:04s realtime, 0h:00m:04s cputime +# Sat Jan 6 06:25:08 2024 ###########################################################] diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_tw1.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_tw1.html index efd895d..c75f629 100644 --- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_tw1.html +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_tw1.html @@ -22,7 +22,7 @@ Setup and Hold Report -------------------------------------------------------------------------------- Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 -Thu Sep 21 05:38:32 2023 +Sat Jan 06 06:25:10 2024 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -41,8 +41,8 @@ Report level: verbose report, limited to 1 item per preference Preference Summary -
  • FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)
    • 129 items scored, 0 timing errors detected. -Report: 51.046MHz is the maximum frequency for this preference. +
  • FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)
    • 168 items scored, 0 timing errors detected. +Report: 43.077MHz is the maximum frequency for this preference.
  • FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)
    • 0 items scored, 0 timing errors detected. Report: 400.000MHz is the maximum frequency for this preference. @@ -50,8 +50,8 @@ Report: 400.000MHz is the maximum frequency for this preference.
  • FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)
    • 0 items scored, 0 timing errors detected. Report: 400.000MHz is the maximum frequency for this preference. -
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    • 388 items scored, 0 timing errors detected. -Report: 88.456MHz is the maximum frequency for this preference. +
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    • 392 items scored, 0 timing errors detected. +Report: 102.020MHz is the maximum frequency for this preference. BLOCK ASYNCPATHS BLOCK RESETPATHS @@ -61,46 +61,48 @@ BLOCK RESETPATHS ================================================================================ Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ; - 129 items scored, 0 timing errors detected. + 168 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- -Passed: The following path meets requirements by 162.619ns (weighted slack = 325.238ns) +Passed: The following path meets requirements by 160.807ns (weighted slack = 321.614ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank[2] (from PHI2_c +) - Destination: FF Data in CmdSubmitted (to PHI2_c -) + Source: FF Q Bank[6] (from PHI2_c +) + Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 9.621ns (25.1% logic, 74.9% route), 6 logic levels. + Delay: 11.433ns (24.4% logic, 75.6% route), 7 logic levels. Constraint Details: - 9.621ns physical path delay SLICE_71 to SLICE_22 meets + 11.433ns physical path delay SLICE_75 to SLICE_20 meets 172.414ns delay constraint less - 0.174ns DIN_SET requirement (totaling 172.240ns) by 162.619ns + 0.174ns DIN_SET requirement (totaling 172.240ns) by 160.807ns Physical Path Details: - Data path SLICE_71 to SLICE_22: + Data path SLICE_75 to SLICE_20: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 SLICE_71.CLK to SLICE_71.Q0 SLICE_71 (from PHI2_c) -ROUTE 1 e 1.441 SLICE_71.Q0 to SLICE_56.A1 Bank[2] -CTOF_DEL --- 0.371 SLICE_56.A1 to SLICE_56.F1 SLICE_56 -ROUTE 1 e 1.441 SLICE_56.F1 to SLICE_70.D1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 SLICE_70.D1 to SLICE_70.F1 SLICE_70 -ROUTE 6 e 1.441 SLICE_70.F1 to SLICE_67.D0 N_147 -CTOF_DEL --- 0.371 SLICE_67.D0 to SLICE_67.F0 SLICE_67 -ROUTE 5 e 1.441 SLICE_67.F0 to SLICE_82.A0 XOR8MEG18 -CTOF_DEL --- 0.371 SLICE_82.A0 to SLICE_82.F0 SLICE_82 -ROUTE 1 e 1.441 SLICE_82.F0 to SLICE_22.A0 CmdSubmitted_1_sqmuxa -CTOF_DEL --- 0.371 SLICE_22.A0 to SLICE_22.F0 SLICE_22 -ROUTE 1 e 0.001 SLICE_22.F0 to SLICE_22.DI0 N_460_0 (to PHI2_c) +REG_DEL --- 0.560 SLICE_75.CLK to SLICE_75.Q0 SLICE_75 (from PHI2_c) +ROUTE 1 e 1.441 SLICE_75.Q0 to SLICE_77.C1 Bank[6] +CTOF_DEL --- 0.371 SLICE_77.C1 to SLICE_77.F1 SLICE_77 +ROUTE 2 e 1.441 SLICE_77.F1 to SLICE_79.D0 un1_Bank_1_5 +CTOF_DEL --- 0.371 SLICE_79.D0 to SLICE_79.F0 SLICE_79 +ROUTE 2 e 1.441 SLICE_79.F0 to SLICE_76.B0 C1WR_7 +CTOF_DEL --- 0.371 SLICE_76.B0 to SLICE_76.F0 SLICE_76 +ROUTE 5 e 1.441 SLICE_76.F0 to SLICE_70.B0 C1WR +CTOF_DEL --- 0.371 SLICE_70.B0 to SLICE_70.F0 SLICE_70 +ROUTE 1 e 1.441 SLICE_70.F0 to SLICE_14.C1 N_121 +CTOF_DEL --- 0.371 SLICE_14.C1 to SLICE_14.F1 SLICE_14 +ROUTE 1 e 1.441 SLICE_14.F1 to SLICE_20.C0 un1_CmdEnable20_i +CTOF_DEL --- 0.371 SLICE_20.C0 to SLICE_20.F0 SLICE_20 +ROUTE 1 e 0.001 SLICE_20.F0 to SLICE_20.DI0 CmdEnable_s (to PHI2_c) -------- - 9.621 (25.1% logic, 74.9% route), 6 logic levels. + 11.433 (24.4% logic, 75.6% route), 7 logic levels. -Report: 51.046MHz is the maximum frequency for this preference. +Report: 43.077MHz is the maximum frequency for this preference. ================================================================================ @@ -141,46 +143,46 @@ Report: 400.000MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; - 388 items scored, 0 timing errors detected. + 392 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- -Passed: The following path meets requirements by 4.695ns +Passed: The following path meets requirements by 6.198ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[17] (from RCLK_c +) - Destination: FF Data in LEDEN (to RCLK_c +) + Destination: FF Data in UFMSDI (to RCLK_c +) - Delay: 11.061ns (21.8% logic, 78.2% route), 6 logic levels. + Delay: 9.621ns (25.1% logic, 74.9% route), 6 logic levels. Constraint Details: - 11.061ns physical path delay SLICE_1 to SLICE_33 meets + 9.621ns physical path delay SLICE_1 to SLICE_52 meets 16.000ns delay constraint less - 0.244ns CE_SET requirement (totaling 15.756ns) by 4.695ns + 0.181ns DIN_SET requirement (totaling 15.819ns) by 6.198ns Physical Path Details: - Data path SLICE_1 to SLICE_33: + Data path SLICE_1 to SLICE_52: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.560 SLICE_1.CLK to SLICE_1.Q1 SLICE_1 (from RCLK_c) -ROUTE 3 e 1.441 SLICE_1.Q1 to SLICE_81.D1 FS[17] -CTOF_DEL --- 0.371 SLICE_81.D1 to SLICE_81.F1 SLICE_81 -ROUTE 1 e 1.441 SLICE_81.F1 to SLICE_72.C1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 SLICE_72.C1 to SLICE_72.F1 SLICE_72 -ROUTE 4 e 1.441 SLICE_72.F1 to SLICE_58.C1 N_51 +ROUTE 3 e 1.441 SLICE_1.Q1 to SLICE_86.D1 FS[17] +CTOF_DEL --- 0.371 SLICE_86.D1 to SLICE_86.F1 SLICE_86 +ROUTE 1 e 1.441 SLICE_86.F1 to SLICE_69.C1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.371 SLICE_69.C1 to SLICE_69.F1 SLICE_69 +ROUTE 4 e 1.441 SLICE_69.F1 to SLICE_58.C1 N_128 CTOF_DEL --- 0.371 SLICE_58.C1 to SLICE_58.F1 SLICE_58 -ROUTE 2 e 1.441 SLICE_58.F1 to SLICE_87.D0 N_151 -CTOF_DEL --- 0.371 SLICE_87.D0 to SLICE_87.F0 SLICE_87 -ROUTE 2 e 1.441 SLICE_87.F0 to SLICE_69.C0 N_137_8 -CTOF_DEL --- 0.371 SLICE_69.C0 to SLICE_69.F0 SLICE_69 -ROUTE 1 e 1.441 SLICE_69.F0 to SLICE_33.CE N_33 (to RCLK_c) +ROUTE 3 e 1.441 SLICE_58.F1 to SLICE_55.C0 N_94 +CTOF_DEL --- 0.371 SLICE_55.C0 to SLICE_55.F0 SLICE_55 +ROUTE 1 e 1.441 SLICE_55.F0 to SLICE_52.D0 UFMSDI_r_xx_mm_1 +CTOF_DEL --- 0.371 SLICE_52.D0 to SLICE_52.F0 SLICE_52 +ROUTE 1 e 0.001 SLICE_52.F0 to SLICE_52.DI0 UFMSDI_RNO (to RCLK_c) -------- - 11.061 (21.8% logic, 78.2% route), 6 logic levels. + 9.621 (25.1% logic, 74.9% route), 6 logic levels. -Report: 88.456MHz is the maximum frequency for this preference. +Report: 102.020MHz is the maximum frequency for this preference. Report Summary -------------- @@ -188,13 +190,13 @@ Report: 88.456MHz is the maximum frequency for this preference. Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | -FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 51.046 MHz| 6 +FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 43.077 MHz| 7 | | | FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 400.000 MHz| 0 | | | FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 400.000 MHz| 0 | | | -FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 88.456 MHz| 6 +FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 102.020 MHz| 6 | | | ---------------------------------------------------------------------------- @@ -249,11 +251,11 @@ Clock Domain: PHI2_c Source: PHI2.PAD Loads: 15 Timing errors: 0 Score: 0 Cumulative negative slack: 0 -Constraints cover 517 paths, 4 nets, and 395 connections (62.40% coverage) +Constraints cover 560 paths, 4 nets, and 424 connections (62.26% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 -Thu Sep 21 05:38:32 2023 +Sat Jan 06 06:25:10 2024 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -272,13 +274,13 @@ Report level: verbose report, limited to 1 item per preference Preference Summary -
  • FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)
    • 129 items scored, 0 timing errors detected. +
  • FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)
    • 168 items scored, 0 timing errors detected.
  • FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)
    • 0 items scored, 0 timing errors detected.
  • FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)
    • 0 items scored, 0 timing errors detected. -
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    • 388 items scored, 0 timing errors detected. +
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    • 392 items scored, 0 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS @@ -288,7 +290,7 @@ BLOCK RESETPATHS ================================================================================ Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ; - 129 items scored, 0 timing errors detected. + 168 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- @@ -334,7 +336,7 @@ ROUTE 1 e 0.001 SLICE_14.F0 to SLICE_14.DI0 C1Submitted_RNO (to P ================================================================================ Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; - 388 items scored, 0 timing errors detected. + 392 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- @@ -349,17 +351,17 @@ Passed: The following path meets requirements by 0.342ns Constraint Details: - 0.325ns physical path delay SLICE_75 to SLICE_75 meets + 0.325ns physical path delay SLICE_74 to SLICE_74 meets -0.017ns M_HLD and 0.000ns delay constraint requirement (totaling -0.017ns) by 0.342ns Physical Path Details: - Data path SLICE_75 to SLICE_75: + Data path SLICE_74 to SLICE_74: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.126 SLICE_75.CLK to SLICE_75.Q0 SLICE_75 (from RCLK_c) -ROUTE 1 e 0.199 SLICE_75.Q0 to SLICE_75.M1 CASr (to RCLK_c) +REG_DEL --- 0.126 SLICE_74.CLK to SLICE_74.Q0 SLICE_74 (from RCLK_c) +ROUTE 1 e 0.199 SLICE_74.Q0 to SLICE_74.M1 CASr (to RCLK_c) -------- 0.325 (38.8% logic, 61.2% route), 1 logic levels. @@ -430,7 +432,7 @@ Clock Domain: PHI2_c Source: PHI2.PAD Loads: 15 Timing errors: 0 Score: 0 Cumulative negative slack: 0 -Constraints cover 517 paths, 4 nets, and 395 connections (62.40% coverage) +Constraints cover 560 paths, 4 nets, and 424 connections (62.26% coverage) diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_twr.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_twr.html index efa9b5f..d97c5e0 100644 --- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_twr.html +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_twr.html @@ -22,7 +22,7 @@ Setup and Hold Report -------------------------------------------------------------------------------- Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 -Thu Sep 21 05:38:42 2023 +Sat Jan 06 06:25:20 2024 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -41,8 +41,8 @@ Report level: verbose report, limited to 10 items per preference Preference Summary -
  • FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)
    • 129 items scored, 0 timing errors detected. -Report: 42.550MHz is the maximum frequency for this preference. +
  • FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)
    • 168 items scored, 0 timing errors detected. +Report: 45.049MHz is the maximum frequency for this preference.
  • FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)
    • 0 items scored, 0 timing errors detected. Report: 400.000MHz is the maximum frequency for this preference. @@ -50,8 +50,8 @@ Report: 400.000MHz is the maximum frequency for this preference.
  • FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)
    • 0 items scored, 0 timing errors detected. Report: 400.000MHz is the maximum frequency for this preference. -
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    • 388 items scored, 0 timing errors detected. -Report: 115.420MHz is the maximum frequency for this preference. +
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    • 392 items scored, 0 timing errors detected. +Report: 118.050MHz is the maximum frequency for this preference. BLOCK ASYNCPATHS BLOCK RESETPATHS @@ -61,530 +61,549 @@ BLOCK RESETPATHS ================================================================================ Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ; - 129 items scored, 0 timing errors detected. + 168 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- -Passed: The following path meets requirements by 160.663ns (weighted slack = 321.326ns) +Passed: The following path meets requirements by 161.315ns (weighted slack = 322.630ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank[7] (from PHI2_c +) - Destination: FF Data in CmdSubmitted (to PHI2_c -) - - Delay: 11.577ns (20.9% logic, 79.1% route), 6 logic levels. - - Constraint Details: - - 11.577ns physical path delay SLICE_77 to SLICE_22 meets - 172.414ns delay constraint less - 0.000ns skew and - 0.174ns DIN_SET requirement (totaling 172.240ns) by 160.663ns - - Physical Path Details: - - Data path SLICE_77 to SLICE_22: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R7C2B.CLK to R7C2B.Q1 SLICE_77 (from PHI2_c) -ROUTE 1 2.505 R7C2B.Q1 to R4C9B.A1 Bank[7] -CTOF_DEL --- 0.371 R4C9B.A1 to R4C9B.F1 SLICE_56 -ROUTE 1 2.155 R4C9B.F1 to R7C2A.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R7C2A.B1 to R7C2A.F1 SLICE_70 -ROUTE 6 1.545 R7C2A.F1 to R7C5D.A0 N_147 -CTOF_DEL --- 0.371 R7C5D.A0 to R7C5D.F0 SLICE_67 -ROUTE 5 0.867 R7C5D.F0 to R7C5C.C0 XOR8MEG18 -CTOF_DEL --- 0.371 R7C5C.C0 to R7C5C.F0 SLICE_82 -ROUTE 1 2.090 R7C5C.F0 to R8C9D.D0 CmdSubmitted_1_sqmuxa -CTOF_DEL --- 0.371 R8C9D.D0 to R8C9D.F0 SLICE_22 -ROUTE 1 0.000 R8C9D.F0 to R8C9D.DI0 N_460_0 (to PHI2_c) - -------- - 11.577 (20.9% logic, 79.1% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_77: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R7C2B.CLK PHI2_c - -------- - 3.682 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_22: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R8C9D.CLK PHI2_c - -------- - 3.682 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 161.013ns (weighted slack = 322.026ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank[6] (from PHI2_c +) - Destination: FF Data in CmdSubmitted (to PHI2_c -) - - Delay: 11.227ns (21.5% logic, 78.5% route), 6 logic levels. - - Constraint Details: - - 11.227ns physical path delay SLICE_77 to SLICE_22 meets - 172.414ns delay constraint less - 0.000ns skew and - 0.174ns DIN_SET requirement (totaling 172.240ns) by 161.013ns - - Physical Path Details: - - Data path SLICE_77 to SLICE_22: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R7C2B.CLK to R7C2B.Q0 SLICE_77 (from PHI2_c) -ROUTE 1 2.155 R7C2B.Q0 to R4C9B.B1 Bank[6] -CTOF_DEL --- 0.371 R4C9B.B1 to R4C9B.F1 SLICE_56 -ROUTE 1 2.155 R4C9B.F1 to R7C2A.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R7C2A.B1 to R7C2A.F1 SLICE_70 -ROUTE 6 1.545 R7C2A.F1 to R7C5D.A0 N_147 -CTOF_DEL --- 0.371 R7C5D.A0 to R7C5D.F0 SLICE_67 -ROUTE 5 0.867 R7C5D.F0 to R7C5C.C0 XOR8MEG18 -CTOF_DEL --- 0.371 R7C5C.C0 to R7C5C.F0 SLICE_82 -ROUTE 1 2.090 R7C5C.F0 to R8C9D.D0 CmdSubmitted_1_sqmuxa -CTOF_DEL --- 0.371 R8C9D.D0 to R8C9D.F0 SLICE_22 -ROUTE 1 0.000 R8C9D.F0 to R8C9D.DI0 N_460_0 (to PHI2_c) - -------- - 11.227 (21.5% logic, 78.5% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_77: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R7C2B.CLK PHI2_c - -------- - 3.682 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_22: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R8C9D.CLK PHI2_c - -------- - 3.682 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 161.212ns (weighted slack = 322.424ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank[2] (from PHI2_c +) - Destination: FF Data in CmdSubmitted (to PHI2_c -) - - Delay: 11.028ns (21.9% logic, 78.1% route), 6 logic levels. - - Constraint Details: - - 11.028ns physical path delay SLICE_71 to SLICE_22 meets - 172.414ns delay constraint less - 0.000ns skew and - 0.174ns DIN_SET requirement (totaling 172.240ns) by 161.212ns - - Physical Path Details: - - Data path SLICE_71 to SLICE_22: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R7C4A.CLK to R7C4A.Q0 SLICE_71 (from PHI2_c) -ROUTE 1 1.956 R7C4A.Q0 to R4C9B.C1 Bank[2] -CTOF_DEL --- 0.371 R4C9B.C1 to R4C9B.F1 SLICE_56 -ROUTE 1 2.155 R4C9B.F1 to R7C2A.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R7C2A.B1 to R7C2A.F1 SLICE_70 -ROUTE 6 1.545 R7C2A.F1 to R7C5D.A0 N_147 -CTOF_DEL --- 0.371 R7C5D.A0 to R7C5D.F0 SLICE_67 -ROUTE 5 0.867 R7C5D.F0 to R7C5C.C0 XOR8MEG18 -CTOF_DEL --- 0.371 R7C5C.C0 to R7C5C.F0 SLICE_82 -ROUTE 1 2.090 R7C5C.F0 to R8C9D.D0 CmdSubmitted_1_sqmuxa -CTOF_DEL --- 0.371 R8C9D.D0 to R8C9D.F0 SLICE_22 -ROUTE 1 0.000 R8C9D.F0 to R8C9D.DI0 N_460_0 (to PHI2_c) - -------- - 11.028 (21.9% logic, 78.1% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_71: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R7C4A.CLK PHI2_c - -------- - 3.682 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_22: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R8C9D.CLK PHI2_c - -------- - 3.682 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 161.405ns (weighted slack = 322.810ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank[5] (from PHI2_c +) - Destination: FF Data in CmdSubmitted (to PHI2_c -) - - Delay: 10.835ns (22.3% logic, 77.7% route), 6 logic levels. - - Constraint Details: - - 10.835ns physical path delay SLICE_76 to SLICE_22 meets - 172.414ns delay constraint less - 0.000ns skew and - 0.174ns DIN_SET requirement (totaling 172.240ns) by 161.405ns - - Physical Path Details: - - Data path SLICE_76 to SLICE_22: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R7C4C.CLK to R7C4C.Q1 SLICE_76 (from PHI2_c) -ROUTE 1 1.763 R7C4C.Q1 to R4C9B.D1 Bank[5] -CTOF_DEL --- 0.371 R4C9B.D1 to R4C9B.F1 SLICE_56 -ROUTE 1 2.155 R4C9B.F1 to R7C2A.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R7C2A.B1 to R7C2A.F1 SLICE_70 -ROUTE 6 1.545 R7C2A.F1 to R7C5D.A0 N_147 -CTOF_DEL --- 0.371 R7C5D.A0 to R7C5D.F0 SLICE_67 -ROUTE 5 0.867 R7C5D.F0 to R7C5C.C0 XOR8MEG18 -CTOF_DEL --- 0.371 R7C5C.C0 to R7C5C.F0 SLICE_82 -ROUTE 1 2.090 R7C5C.F0 to R8C9D.D0 CmdSubmitted_1_sqmuxa -CTOF_DEL --- 0.371 R8C9D.D0 to R8C9D.F0 SLICE_22 -ROUTE 1 0.000 R8C9D.F0 to R8C9D.DI0 N_460_0 (to PHI2_c) - -------- - 10.835 (22.3% logic, 77.7% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_76: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R7C4C.CLK PHI2_c - -------- - 3.682 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_22: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R8C9D.CLK PHI2_c - -------- - 3.682 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 161.733ns (weighted slack = 323.466ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank[7] (from PHI2_c +) + Source: FF Q Bank[4] (from PHI2_c +) Destination: FF Data in CmdUFMSDI (to PHI2_c -) - Delay: 10.416ns (19.6% logic, 80.4% route), 5 logic levels. + Delay: 10.834ns (22.3% logic, 77.7% route), 6 logic levels. Constraint Details: - 10.416ns physical path delay SLICE_77 to SLICE_74 meets + 10.834ns physical path delay SLICE_93 to SLICE_88 meets 172.414ns delay constraint less 0.000ns skew and - 0.265ns CE_SET requirement (totaling 172.149ns) by 161.733ns + 0.265ns CE_SET requirement (totaling 172.149ns) by 161.315ns Physical Path Details: - Data path SLICE_77 to SLICE_74: + Data path SLICE_93 to SLICE_88: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R7C2B.CLK to R7C2B.Q1 SLICE_77 (from PHI2_c) -ROUTE 1 2.505 R7C2B.Q1 to R4C9B.A1 Bank[7] -CTOF_DEL --- 0.371 R4C9B.A1 to R4C9B.F1 SLICE_56 -ROUTE 1 2.155 R4C9B.F1 to R7C2A.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R7C2A.B1 to R7C2A.F1 SLICE_70 -ROUTE 6 1.545 R7C2A.F1 to R7C5D.A0 N_147 -CTOF_DEL --- 0.371 R7C5D.A0 to R7C5D.F0 SLICE_67 -ROUTE 5 0.528 R7C5D.F0 to R7C5D.C1 XOR8MEG18 -CTOF_DEL --- 0.371 R7C5D.C1 to R7C5D.F1 SLICE_67 -ROUTE 2 1.639 R7C5D.F1 to R8C7D.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) +REG_DEL --- 0.560 R2C4C.CLK to R2C4C.Q0 SLICE_93 (from PHI2_c) +ROUTE 1 2.104 R2C4C.Q0 to R7C5A.B0 Bank[4] +CTOF_DEL --- 0.371 R7C5A.B0 to R7C5A.F0 SLICE_100 +ROUTE 2 1.032 R7C5A.F0 to R8C5C.A0 un1_Bank_1_4 +CTOF_DEL --- 0.371 R8C5C.A0 to R8C5C.F0 SLICE_79 +ROUTE 2 1.503 R8C5C.F0 to R7C6B.A1 C1WR_7 +CTOF_DEL --- 0.371 R7C6B.A1 to R7C6B.F1 SLICE_70 +ROUTE 2 0.710 R7C6B.F1 to R9C6A.D0 CMDWR +CTOF_DEL --- 0.371 R9C6A.D0 to R9C6A.F0 SLICE_73 +ROUTE 5 1.398 R9C6A.F0 to R9C8C.C1 XOR8MEG18 +CTOF_DEL --- 0.371 R9C8C.C1 to R9C8C.F1 SLICE_85 +ROUTE 2 1.672 R9C8C.F1 to R9C7A.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) -------- - 10.416 (19.6% logic, 80.4% route), 5 logic levels. + 10.834 (22.3% logic, 77.7% route), 6 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_77: + Source Clock Path PHI2 to SLICE_93: Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R7C2B.CLK PHI2_c +ROUTE 15 3.682 39.PADDI to R2C4C.CLK PHI2_c -------- 3.682 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_74: + Destination Clock Path PHI2 to SLICE_88: Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R8C7D.CLK PHI2_c +ROUTE 15 3.682 39.PADDI to R9C7A.CLK PHI2_c -------- 3.682 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 162.083ns (weighted slack = 324.166ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank[6] (from PHI2_c +) - Destination: FF Data in CmdUFMSDI (to PHI2_c -) - - Delay: 10.066ns (20.3% logic, 79.7% route), 5 logic levels. - - Constraint Details: - - 10.066ns physical path delay SLICE_77 to SLICE_74 meets - 172.414ns delay constraint less - 0.000ns skew and - 0.265ns CE_SET requirement (totaling 172.149ns) by 162.083ns - - Physical Path Details: - - Data path SLICE_77 to SLICE_74: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R7C2B.CLK to R7C2B.Q0 SLICE_77 (from PHI2_c) -ROUTE 1 2.155 R7C2B.Q0 to R4C9B.B1 Bank[6] -CTOF_DEL --- 0.371 R4C9B.B1 to R4C9B.F1 SLICE_56 -ROUTE 1 2.155 R4C9B.F1 to R7C2A.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R7C2A.B1 to R7C2A.F1 SLICE_70 -ROUTE 6 1.545 R7C2A.F1 to R7C5D.A0 N_147 -CTOF_DEL --- 0.371 R7C5D.A0 to R7C5D.F0 SLICE_67 -ROUTE 5 0.528 R7C5D.F0 to R7C5D.C1 XOR8MEG18 -CTOF_DEL --- 0.371 R7C5D.C1 to R7C5D.F1 SLICE_67 -ROUTE 2 1.639 R7C5D.F1 to R8C7D.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) - -------- - 10.066 (20.3% logic, 79.7% route), 5 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_77: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R7C2B.CLK PHI2_c - -------- - 3.682 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_74: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R8C7D.CLK PHI2_c - -------- - 3.682 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 162.194ns (weighted slack = 324.388ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank[7] (from PHI2_c +) - Destination: FF Data in CmdUFMCS (to PHI2_c -) - FF CmdUFMCLK - - Delay: 9.955ns (20.5% logic, 79.5% route), 5 logic levels. - - Constraint Details: - - 9.955ns physical path delay SLICE_77 to SLICE_73 meets - 172.414ns delay constraint less - 0.000ns skew and - 0.265ns CE_SET requirement (totaling 172.149ns) by 162.194ns - - Physical Path Details: - - Data path SLICE_77 to SLICE_73: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R7C2B.CLK to R7C2B.Q1 SLICE_77 (from PHI2_c) -ROUTE 1 2.505 R7C2B.Q1 to R4C9B.A1 Bank[7] -CTOF_DEL --- 0.371 R4C9B.A1 to R4C9B.F1 SLICE_56 -ROUTE 1 2.155 R4C9B.F1 to R7C2A.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R7C2A.B1 to R7C2A.F1 SLICE_70 -ROUTE 6 1.545 R7C2A.F1 to R7C5D.A0 N_147 -CTOF_DEL --- 0.371 R7C5D.A0 to R7C5D.F0 SLICE_67 -ROUTE 5 0.528 R7C5D.F0 to R7C5D.C1 XOR8MEG18 -CTOF_DEL --- 0.371 R7C5D.C1 to R7C5D.F1 SLICE_67 -ROUTE 2 1.178 R7C5D.F1 to R7C8A.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) - -------- - 9.955 (20.5% logic, 79.5% route), 5 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_77: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R7C2B.CLK PHI2_c - -------- - 3.682 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_73: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R7C8A.CLK PHI2_c - -------- - 3.682 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 162.282ns (weighted slack = 324.564ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank[2] (from PHI2_c +) - Destination: FF Data in CmdUFMSDI (to PHI2_c -) - - Delay: 9.867ns (20.7% logic, 79.3% route), 5 logic levels. - - Constraint Details: - - 9.867ns physical path delay SLICE_71 to SLICE_74 meets - 172.414ns delay constraint less - 0.000ns skew and - 0.265ns CE_SET requirement (totaling 172.149ns) by 162.282ns - - Physical Path Details: - - Data path SLICE_71 to SLICE_74: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R7C4A.CLK to R7C4A.Q0 SLICE_71 (from PHI2_c) -ROUTE 1 1.956 R7C4A.Q0 to R4C9B.C1 Bank[2] -CTOF_DEL --- 0.371 R4C9B.C1 to R4C9B.F1 SLICE_56 -ROUTE 1 2.155 R4C9B.F1 to R7C2A.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R7C2A.B1 to R7C2A.F1 SLICE_70 -ROUTE 6 1.545 R7C2A.F1 to R7C5D.A0 N_147 -CTOF_DEL --- 0.371 R7C5D.A0 to R7C5D.F0 SLICE_67 -ROUTE 5 0.528 R7C5D.F0 to R7C5D.C1 XOR8MEG18 -CTOF_DEL --- 0.371 R7C5D.C1 to R7C5D.F1 SLICE_67 -ROUTE 2 1.639 R7C5D.F1 to R8C7D.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) - -------- - 9.867 (20.7% logic, 79.3% route), 5 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_71: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R7C4A.CLK PHI2_c - -------- - 3.682 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_74: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R8C7D.CLK PHI2_c - -------- - 3.682 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 162.475ns (weighted slack = 324.950ns) +Passed: The following path meets requirements by 161.760ns (weighted slack = 323.520ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Bank[5] (from PHI2_c +) Destination: FF Data in CmdUFMSDI (to PHI2_c -) - Delay: 9.674ns (21.1% logic, 78.9% route), 5 logic levels. + Delay: 10.389ns (23.2% logic, 76.8% route), 6 logic levels. Constraint Details: - 9.674ns physical path delay SLICE_76 to SLICE_74 meets + 10.389ns physical path delay SLICE_93 to SLICE_88 meets 172.414ns delay constraint less 0.000ns skew and - 0.265ns CE_SET requirement (totaling 172.149ns) by 162.475ns + 0.265ns CE_SET requirement (totaling 172.149ns) by 161.760ns Physical Path Details: - Data path SLICE_76 to SLICE_74: + Data path SLICE_93 to SLICE_88: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R7C4C.CLK to R7C4C.Q1 SLICE_76 (from PHI2_c) -ROUTE 1 1.763 R7C4C.Q1 to R4C9B.D1 Bank[5] -CTOF_DEL --- 0.371 R4C9B.D1 to R4C9B.F1 SLICE_56 -ROUTE 1 2.155 R4C9B.F1 to R7C2A.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R7C2A.B1 to R7C2A.F1 SLICE_70 -ROUTE 6 1.545 R7C2A.F1 to R7C5D.A0 N_147 -CTOF_DEL --- 0.371 R7C5D.A0 to R7C5D.F0 SLICE_67 -ROUTE 5 0.528 R7C5D.F0 to R7C5D.C1 XOR8MEG18 -CTOF_DEL --- 0.371 R7C5D.C1 to R7C5D.F1 SLICE_67 -ROUTE 2 1.639 R7C5D.F1 to R8C7D.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) +REG_DEL --- 0.560 R2C4C.CLK to R2C4C.Q1 SLICE_93 (from PHI2_c) +ROUTE 1 1.979 R2C4C.Q1 to R8C5A.A1 Bank[5] +CTOF_DEL --- 0.371 R8C5A.A1 to R8C5A.F1 SLICE_77 +ROUTE 2 0.712 R8C5A.F1 to R8C5C.B0 un1_Bank_1_5 +CTOF_DEL --- 0.371 R8C5C.B0 to R8C5C.F0 SLICE_79 +ROUTE 2 1.503 R8C5C.F0 to R7C6B.A1 C1WR_7 +CTOF_DEL --- 0.371 R7C6B.A1 to R7C6B.F1 SLICE_70 +ROUTE 2 0.710 R7C6B.F1 to R9C6A.D0 CMDWR +CTOF_DEL --- 0.371 R9C6A.D0 to R9C6A.F0 SLICE_73 +ROUTE 5 1.398 R9C6A.F0 to R9C8C.C1 XOR8MEG18 +CTOF_DEL --- 0.371 R9C8C.C1 to R9C8C.F1 SLICE_85 +ROUTE 2 1.672 R9C8C.F1 to R9C7A.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) -------- - 9.674 (21.1% logic, 78.9% route), 5 logic levels. + 10.389 (23.2% logic, 76.8% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.682 39.PADDI to R2C4C.CLK PHI2_c + -------- + 3.682 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_88: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.682 39.PADDI to R9C7A.CLK PHI2_c + -------- + 3.682 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 161.922ns (weighted slack = 323.844ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank[4] (from PHI2_c +) + Destination: FF Data in CmdEnable (to PHI2_c -) + + Delay: 10.318ns (27.0% logic, 73.0% route), 7 logic levels. + + Constraint Details: + + 10.318ns physical path delay SLICE_93 to SLICE_20 meets + 172.414ns delay constraint less + 0.000ns skew and + 0.174ns DIN_SET requirement (totaling 172.240ns) by 161.922ns + + Physical Path Details: + + Data path SLICE_93 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C4C.CLK to R2C4C.Q0 SLICE_93 (from PHI2_c) +ROUTE 1 2.104 R2C4C.Q0 to R7C5A.B0 Bank[4] +CTOF_DEL --- 0.371 R7C5A.B0 to R7C5A.F0 SLICE_100 +ROUTE 2 1.032 R7C5A.F0 to R8C5C.A0 un1_Bank_1_4 +CTOF_DEL --- 0.371 R8C5C.A0 to R8C5C.F0 SLICE_79 +ROUTE 2 0.320 R8C5C.F0 to R8C5B.D0 C1WR_7 +CTOF_DEL --- 0.371 R8C5B.D0 to R8C5B.F0 SLICE_76 +ROUTE 5 2.032 R8C5B.F0 to R7C6B.B0 C1WR +CTOF_DEL --- 0.371 R7C6B.B0 to R7C6B.F0 SLICE_70 +ROUTE 1 1.086 R7C6B.F0 to R8C6C.B1 N_121 +CTOF_DEL --- 0.371 R8C6C.B1 to R8C6C.F1 SLICE_14 +ROUTE 1 0.958 R8C6C.F1 to R8C6A.A0 un1_CmdEnable20_i +CTOF_DEL --- 0.371 R8C6A.A0 to R8C6A.F0 SLICE_20 +ROUTE 1 0.000 R8C6A.F0 to R8C6A.DI0 CmdEnable_s (to PHI2_c) + -------- + 10.318 (27.0% logic, 73.0% route), 7 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.682 39.PADDI to R2C4C.CLK PHI2_c + -------- + 3.682 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.682 39.PADDI to R8C6A.CLK PHI2_c + -------- + 3.682 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.174ns (weighted slack = 324.348ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank[3] (from PHI2_c +) + Destination: FF Data in CmdUFMSDI (to PHI2_c -) + + Delay: 9.975ns (24.2% logic, 75.8% route), 6 logic levels. + + Constraint Details: + + 9.975ns physical path delay SLICE_79 to SLICE_88 meets + 172.414ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 172.149ns) by 162.174ns + + Physical Path Details: + + Data path SLICE_79 to SLICE_88: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R8C5C.CLK to R8C5C.Q1 SLICE_79 (from PHI2_c) +ROUTE 1 1.245 R8C5C.Q1 to R7C5A.C0 Bank[3] +CTOF_DEL --- 0.371 R7C5A.C0 to R7C5A.F0 SLICE_100 +ROUTE 2 1.032 R7C5A.F0 to R8C5C.A0 un1_Bank_1_4 +CTOF_DEL --- 0.371 R8C5C.A0 to R8C5C.F0 SLICE_79 +ROUTE 2 1.503 R8C5C.F0 to R7C6B.A1 C1WR_7 +CTOF_DEL --- 0.371 R7C6B.A1 to R7C6B.F1 SLICE_70 +ROUTE 2 0.710 R7C6B.F1 to R9C6A.D0 CMDWR +CTOF_DEL --- 0.371 R9C6A.D0 to R9C6A.F0 SLICE_73 +ROUTE 5 1.398 R9C6A.F0 to R9C8C.C1 XOR8MEG18 +CTOF_DEL --- 0.371 R9C8C.C1 to R9C8C.F1 SLICE_85 +ROUTE 2 1.672 R9C8C.F1 to R9C7A.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) + -------- + 9.975 (24.2% logic, 75.8% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_79: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.682 39.PADDI to R8C5C.CLK PHI2_c + -------- + 3.682 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_88: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.682 39.PADDI to R9C7A.CLK PHI2_c + -------- + 3.682 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.258ns (weighted slack = 324.516ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank[4] (from PHI2_c +) + Destination: FF Data in CmdEnable (to PHI2_c -) + + Delay: 9.982ns (27.9% logic, 72.1% route), 7 logic levels. + + Constraint Details: + + 9.982ns physical path delay SLICE_93 to SLICE_20 meets + 172.414ns delay constraint less + 0.000ns skew and + 0.174ns DIN_SET requirement (totaling 172.240ns) by 162.258ns + + Physical Path Details: + + Data path SLICE_93 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C4C.CLK to R2C4C.Q0 SLICE_93 (from PHI2_c) +ROUTE 1 2.104 R2C4C.Q0 to R7C5A.B0 Bank[4] +CTOF_DEL --- 0.371 R7C5A.B0 to R7C5A.F0 SLICE_100 +ROUTE 2 1.032 R7C5A.F0 to R8C5C.A0 un1_Bank_1_4 +CTOF_DEL --- 0.371 R8C5C.A0 to R8C5C.F0 SLICE_79 +ROUTE 2 1.503 R8C5C.F0 to R7C6B.A1 C1WR_7 +CTOF_DEL --- 0.371 R7C6B.A1 to R7C6B.F1 SLICE_70 +ROUTE 2 0.513 R7C6B.F1 to R7C6B.C0 CMDWR +CTOF_DEL --- 0.371 R7C6B.C0 to R7C6B.F0 SLICE_70 +ROUTE 1 1.086 R7C6B.F0 to R8C6C.B1 N_121 +CTOF_DEL --- 0.371 R8C6C.B1 to R8C6C.F1 SLICE_14 +ROUTE 1 0.958 R8C6C.F1 to R8C6A.A0 un1_CmdEnable20_i +CTOF_DEL --- 0.371 R8C6A.A0 to R8C6A.F0 SLICE_20 +ROUTE 1 0.000 R8C6A.F0 to R8C6A.DI0 CmdEnable_s (to PHI2_c) + -------- + 9.982 (27.9% logic, 72.1% route), 7 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.682 39.PADDI to R2C4C.CLK PHI2_c + -------- + 3.682 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.682 39.PADDI to R8C6A.CLK PHI2_c + -------- + 3.682 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.324ns (weighted slack = 324.648ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank[4] (from PHI2_c +) + Destination: FF Data in CmdUFMCS (to PHI2_c -) + FF CmdUFMCLK + + Delay: 9.825ns (24.6% logic, 75.4% route), 6 logic levels. + + Constraint Details: + + 9.825ns physical path delay SLICE_93 to SLICE_85 meets + 172.414ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 172.149ns) by 162.324ns + + Physical Path Details: + + Data path SLICE_93 to SLICE_85: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C4C.CLK to R2C4C.Q0 SLICE_93 (from PHI2_c) +ROUTE 1 2.104 R2C4C.Q0 to R7C5A.B0 Bank[4] +CTOF_DEL --- 0.371 R7C5A.B0 to R7C5A.F0 SLICE_100 +ROUTE 2 1.032 R7C5A.F0 to R8C5C.A0 un1_Bank_1_4 +CTOF_DEL --- 0.371 R8C5C.A0 to R8C5C.F0 SLICE_79 +ROUTE 2 1.503 R8C5C.F0 to R7C6B.A1 C1WR_7 +CTOF_DEL --- 0.371 R7C6B.A1 to R7C6B.F1 SLICE_70 +ROUTE 2 0.710 R7C6B.F1 to R9C6A.D0 CMDWR +CTOF_DEL --- 0.371 R9C6A.D0 to R9C6A.F0 SLICE_73 +ROUTE 5 1.398 R9C6A.F0 to R9C8C.C1 XOR8MEG18 +CTOF_DEL --- 0.371 R9C8C.C1 to R9C8C.F1 SLICE_85 +ROUTE 2 0.663 R9C8C.F1 to R9C8C.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) + -------- + 9.825 (24.6% logic, 75.4% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.682 39.PADDI to R2C4C.CLK PHI2_c + -------- + 3.682 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_85: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.682 39.PADDI to R9C8C.CLK PHI2_c + -------- + 3.682 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.367ns (weighted slack = 324.734ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank[5] (from PHI2_c +) + Destination: FF Data in CmdEnable (to PHI2_c -) + + Delay: 9.873ns (28.2% logic, 71.8% route), 7 logic levels. + + Constraint Details: + + 9.873ns physical path delay SLICE_93 to SLICE_20 meets + 172.414ns delay constraint less + 0.000ns skew and + 0.174ns DIN_SET requirement (totaling 172.240ns) by 162.367ns + + Physical Path Details: + + Data path SLICE_93 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C4C.CLK to R2C4C.Q1 SLICE_93 (from PHI2_c) +ROUTE 1 1.979 R2C4C.Q1 to R8C5A.A1 Bank[5] +CTOF_DEL --- 0.371 R8C5A.A1 to R8C5A.F1 SLICE_77 +ROUTE 2 0.712 R8C5A.F1 to R8C5C.B0 un1_Bank_1_5 +CTOF_DEL --- 0.371 R8C5C.B0 to R8C5C.F0 SLICE_79 +ROUTE 2 0.320 R8C5C.F0 to R8C5B.D0 C1WR_7 +CTOF_DEL --- 0.371 R8C5B.D0 to R8C5B.F0 SLICE_76 +ROUTE 5 2.032 R8C5B.F0 to R7C6B.B0 C1WR +CTOF_DEL --- 0.371 R7C6B.B0 to R7C6B.F0 SLICE_70 +ROUTE 1 1.086 R7C6B.F0 to R8C6C.B1 N_121 +CTOF_DEL --- 0.371 R8C6C.B1 to R8C6C.F1 SLICE_14 +ROUTE 1 0.958 R8C6C.F1 to R8C6A.A0 un1_CmdEnable20_i +CTOF_DEL --- 0.371 R8C6A.A0 to R8C6A.F0 SLICE_20 +ROUTE 1 0.000 R8C6A.F0 to R8C6A.DI0 CmdEnable_s (to PHI2_c) + -------- + 9.873 (28.2% logic, 71.8% route), 7 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.682 39.PADDI to R2C4C.CLK PHI2_c + -------- + 3.682 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.682 39.PADDI to R8C6A.CLK PHI2_c + -------- + 3.682 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 162.387ns (weighted slack = 324.774ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank[0] (from PHI2_c +) + Destination: FF Data in CmdUFMSDI (to PHI2_c -) + + Delay: 9.762ns (24.7% logic, 75.3% route), 6 logic levels. + + Constraint Details: + + 9.762ns physical path delay SLICE_76 to SLICE_88 meets + 172.414ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 172.149ns) by 162.387ns + + Physical Path Details: + + Data path SLICE_76 to SLICE_88: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R8C5B.CLK to R8C5B.Q0 SLICE_76 (from PHI2_c) +ROUTE 1 1.032 R8C5B.Q0 to R7C5A.A0 Bank[0] +CTOF_DEL --- 0.371 R7C5A.A0 to R7C5A.F0 SLICE_100 +ROUTE 2 1.032 R7C5A.F0 to R8C5C.A0 un1_Bank_1_4 +CTOF_DEL --- 0.371 R8C5C.A0 to R8C5C.F0 SLICE_79 +ROUTE 2 1.503 R8C5C.F0 to R7C6B.A1 C1WR_7 +CTOF_DEL --- 0.371 R7C6B.A1 to R7C6B.F1 SLICE_70 +ROUTE 2 0.710 R7C6B.F1 to R9C6A.D0 CMDWR +CTOF_DEL --- 0.371 R9C6A.D0 to R9C6A.F0 SLICE_73 +ROUTE 5 1.398 R9C6A.F0 to R9C8C.C1 XOR8MEG18 +CTOF_DEL --- 0.371 R9C8C.C1 to R9C8C.F1 SLICE_85 +ROUTE 2 1.672 R9C8C.F1 to R9C7A.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) + -------- + 9.762 (24.7% logic, 75.3% route), 6 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_76: Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R7C4C.CLK PHI2_c +ROUTE 15 3.682 39.PADDI to R8C5B.CLK PHI2_c -------- 3.682 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_74: + Destination Clock Path PHI2 to SLICE_88: Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R8C7D.CLK PHI2_c +ROUTE 15 3.682 39.PADDI to R9C7A.CLK PHI2_c -------- 3.682 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 162.544ns (weighted slack = 325.088ns) +Passed: The following path meets requirements by 162.647ns (weighted slack = 325.294ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank[6] (from PHI2_c +) - Destination: FF Data in CmdUFMCS (to PHI2_c -) - FF CmdUFMCLK + Source: FF Q Bank[7] (from PHI2_c +) + Destination: FF Data in CmdUFMSDI (to PHI2_c -) - Delay: 9.605ns (21.3% logic, 78.7% route), 5 logic levels. + Delay: 9.502ns (25.4% logic, 74.6% route), 6 logic levels. Constraint Details: - 9.605ns physical path delay SLICE_77 to SLICE_73 meets + 9.502ns physical path delay SLICE_75 to SLICE_88 meets 172.414ns delay constraint less 0.000ns skew and - 0.265ns CE_SET requirement (totaling 172.149ns) by 162.544ns + 0.265ns CE_SET requirement (totaling 172.149ns) by 162.647ns Physical Path Details: - Data path SLICE_77 to SLICE_73: + Data path SLICE_75 to SLICE_88: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R7C2B.CLK to R7C2B.Q0 SLICE_77 (from PHI2_c) -ROUTE 1 2.155 R7C2B.Q0 to R4C9B.B1 Bank[6] -CTOF_DEL --- 0.371 R4C9B.B1 to R4C9B.F1 SLICE_56 -ROUTE 1 2.155 R4C9B.F1 to R7C2A.B1 C1WR_0_a2_0_11 -CTOF_DEL --- 0.371 R7C2A.B1 to R7C2A.F1 SLICE_70 -ROUTE 6 1.545 R7C2A.F1 to R7C5D.A0 N_147 -CTOF_DEL --- 0.371 R7C5D.A0 to R7C5D.F0 SLICE_67 -ROUTE 5 0.528 R7C5D.F0 to R7C5D.C1 XOR8MEG18 -CTOF_DEL --- 0.371 R7C5D.C1 to R7C5D.F1 SLICE_67 -ROUTE 2 1.178 R7C5D.F1 to R7C8A.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) +REG_DEL --- 0.560 R8C6D.CLK to R8C6D.Q1 SLICE_75 (from PHI2_c) +ROUTE 1 1.092 R8C6D.Q1 to R8C5A.B1 Bank[7] +CTOF_DEL --- 0.371 R8C5A.B1 to R8C5A.F1 SLICE_77 +ROUTE 2 0.712 R8C5A.F1 to R8C5C.B0 un1_Bank_1_5 +CTOF_DEL --- 0.371 R8C5C.B0 to R8C5C.F0 SLICE_79 +ROUTE 2 1.503 R8C5C.F0 to R7C6B.A1 C1WR_7 +CTOF_DEL --- 0.371 R7C6B.A1 to R7C6B.F1 SLICE_70 +ROUTE 2 0.710 R7C6B.F1 to R9C6A.D0 CMDWR +CTOF_DEL --- 0.371 R9C6A.D0 to R9C6A.F0 SLICE_73 +ROUTE 5 1.398 R9C6A.F0 to R9C8C.C1 XOR8MEG18 +CTOF_DEL --- 0.371 R9C8C.C1 to R9C8C.F1 SLICE_85 +ROUTE 2 1.672 R9C8C.F1 to R9C7A.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) -------- - 9.605 (21.3% logic, 78.7% route), 5 logic levels. + 9.502 (25.4% logic, 74.6% route), 6 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_77: + Source Clock Path PHI2 to SLICE_75: Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R7C2B.CLK PHI2_c +ROUTE 15 3.682 39.PADDI to R8C6D.CLK PHI2_c -------- 3.682 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_73: + Destination Clock Path PHI2 to SLICE_88: Name Fanout Delay (ns) Site Resource -ROUTE 15 3.682 39.PADDI to R7C8A.CLK PHI2_c +ROUTE 15 3.682 39.PADDI to R9C7A.CLK PHI2_c -------- 3.682 (0.0% logic, 100.0% route), 0 logic levels. -Report: 42.550MHz is the maximum frequency for this preference. + +Passed: The following path meets requirements by 162.703ns (weighted slack = 325.406ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank[5] (from PHI2_c +) + Destination: FF Data in CmdEnable (to PHI2_c -) + + Delay: 9.537ns (29.2% logic, 70.8% route), 7 logic levels. + + Constraint Details: + + 9.537ns physical path delay SLICE_93 to SLICE_20 meets + 172.414ns delay constraint less + 0.000ns skew and + 0.174ns DIN_SET requirement (totaling 172.240ns) by 162.703ns + + Physical Path Details: + + Data path SLICE_93 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C4C.CLK to R2C4C.Q1 SLICE_93 (from PHI2_c) +ROUTE 1 1.979 R2C4C.Q1 to R8C5A.A1 Bank[5] +CTOF_DEL --- 0.371 R8C5A.A1 to R8C5A.F1 SLICE_77 +ROUTE 2 0.712 R8C5A.F1 to R8C5C.B0 un1_Bank_1_5 +CTOF_DEL --- 0.371 R8C5C.B0 to R8C5C.F0 SLICE_79 +ROUTE 2 1.503 R8C5C.F0 to R7C6B.A1 C1WR_7 +CTOF_DEL --- 0.371 R7C6B.A1 to R7C6B.F1 SLICE_70 +ROUTE 2 0.513 R7C6B.F1 to R7C6B.C0 CMDWR +CTOF_DEL --- 0.371 R7C6B.C0 to R7C6B.F0 SLICE_70 +ROUTE 1 1.086 R7C6B.F0 to R8C6C.B1 N_121 +CTOF_DEL --- 0.371 R8C6C.B1 to R8C6C.F1 SLICE_14 +ROUTE 1 0.958 R8C6C.F1 to R8C6A.A0 un1_CmdEnable20_i +CTOF_DEL --- 0.371 R8C6A.A0 to R8C6A.F0 SLICE_20 +ROUTE 1 0.000 R8C6A.F0 to R8C6A.DI0 CmdEnable_s (to PHI2_c) + -------- + 9.537 (29.2% logic, 70.8% route), 7 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.682 39.PADDI to R2C4C.CLK PHI2_c + -------- + 3.682 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 3.682 39.PADDI to R8C6A.CLK PHI2_c + -------- + 3.682 (0.0% logic, 100.0% route), 0 logic levels. + +Report: 45.049MHz is the maximum frequency for this preference. ================================================================================ @@ -625,105 +644,154 @@ Report: 400.000MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; - 388 items scored, 0 timing errors detected. + 392 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- -Passed: The following path meets requirements by 7.336ns +Passed: The following path meets requirements by 7.529ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[15] (from RCLK_c +) - Destination: FF Data in n8MEGEN (to RCLK_c +) + Destination: FF Data in UFMCLK (to RCLK_c +) - Delay: 8.420ns (28.7% logic, 71.3% route), 6 logic levels. + Delay: 8.290ns (29.1% logic, 70.9% route), 6 logic levels. Constraint Details: - 8.420ns physical path delay SLICE_2 to SLICE_58 meets + 8.290ns physical path delay SLICE_2 to SLICE_51 meets 16.000ns delay constraint less 0.000ns skew and - 0.244ns CE_SET requirement (totaling 15.756ns) by 7.336ns + 0.181ns DIN_SET requirement (totaling 15.819ns) by 7.529ns Physical Path Details: - Data path SLICE_2 to SLICE_58: + Data path SLICE_2 to SLICE_51: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C5D.CLK to R8C5D.Q1 SLICE_2 (from RCLK_c) -ROUTE 3 1.571 R8C5D.Q1 to R7C6A.B1 FS[15] -CTOF_DEL --- 0.371 R7C6A.B1 to R7C6A.F1 SLICE_81 -ROUTE 1 0.626 R7C6A.F1 to R7C6D.D1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 R7C6D.D1 to R7C6D.F1 SLICE_72 -ROUTE 4 0.657 R7C6D.F1 to R7C6B.D1 N_51 -CTOF_DEL --- 0.371 R7C6B.D1 to R7C6B.F1 SLICE_58 -ROUTE 2 1.169 R7C6B.F1 to R8C7B.D0 N_151 -CTOF_DEL --- 0.371 R8C7B.D0 to R8C7B.F0 SLICE_87 -ROUTE 2 0.909 R8C7B.F0 to R8C6C.C0 N_137_8 -CTOF_DEL --- 0.371 R8C6C.C0 to R8C6C.F0 SLICE_68 -ROUTE 1 1.073 R8C6C.F0 to R7C6B.CE N_31 (to RCLK_c) +REG_DEL --- 0.560 R10C4D.CLK to R10C4D.Q1 SLICE_2 (from RCLK_c) +ROUTE 3 1.116 R10C4D.Q1 to R10C5C.B1 FS[15] +CTOF_DEL --- 0.371 R10C5C.B1 to R10C5C.F1 SLICE_86 +ROUTE 1 1.026 R10C5C.F1 to R10C6D.A1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.371 R10C6D.A1 to R10C6D.F1 SLICE_69 +ROUTE 4 1.689 R10C6D.F1 to R10C6D.B0 N_128 +CTOF_DEL --- 0.371 R10C6D.B0 to R10C6D.F0 SLICE_69 +ROUTE 1 1.547 R10C6D.F0 to R10C9C.B1 N_129 +CTOF_DEL --- 0.371 R10C9C.B1 to R10C9C.F1 SLICE_51 +ROUTE 1 0.497 R10C9C.F1 to R10C9C.C0 UFMCLK_r_i_m4_xx_mm_1 +CTOF_DEL --- 0.371 R10C9C.C0 to R10C9C.F0 SLICE_51 +ROUTE 1 0.000 R10C9C.F0 to R10C9C.DI0 UFMCLK_RNO (to RCLK_c) -------- - 8.420 (28.7% logic, 71.3% route), 6 logic levels. + 8.290 (29.1% logic, 70.9% route), 6 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_2: Name Fanout Delay (ns) Site Resource -ROUTE 32 1.425 86.PADDI to R8C5D.CLK RCLK_c +ROUTE 32 1.425 86.PADDI to R10C4D.CLK RCLK_c -------- 1.425 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_58: + Destination Clock Path RCLK to SLICE_51: Name Fanout Delay (ns) Site Resource -ROUTE 32 1.425 86.PADDI to R7C6B.CLK RCLK_c +ROUTE 32 1.425 86.PADDI to R10C9C.CLK RCLK_c -------- 1.425 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 7.342ns +Passed: The following path meets requirements by 7.597ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS[15] (from RCLK_c +) + Source: FF Q FS[12] (from RCLK_c +) + Destination: FF Data in UFMCLK (to RCLK_c +) + + Delay: 8.222ns (29.4% logic, 70.6% route), 6 logic levels. + + Constraint Details: + + 8.222ns physical path delay SLICE_3 to SLICE_51 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.181ns DIN_SET requirement (totaling 15.819ns) by 7.597ns + + Physical Path Details: + + Data path SLICE_3 to SLICE_51: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R10C4C.CLK to R10C4C.Q0 SLICE_3 (from RCLK_c) +ROUTE 3 1.048 R10C4C.Q0 to R10C5C.A1 FS[12] +CTOF_DEL --- 0.371 R10C5C.A1 to R10C5C.F1 SLICE_86 +ROUTE 1 1.026 R10C5C.F1 to R10C6D.A1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.371 R10C6D.A1 to R10C6D.F1 SLICE_69 +ROUTE 4 1.689 R10C6D.F1 to R10C6D.B0 N_128 +CTOF_DEL --- 0.371 R10C6D.B0 to R10C6D.F0 SLICE_69 +ROUTE 1 1.547 R10C6D.F0 to R10C9C.B1 N_129 +CTOF_DEL --- 0.371 R10C9C.B1 to R10C9C.F1 SLICE_51 +ROUTE 1 0.497 R10C9C.F1 to R10C9C.C0 UFMCLK_r_i_m4_xx_mm_1 +CTOF_DEL --- 0.371 R10C9C.C0 to R10C9C.F0 SLICE_51 +ROUTE 1 0.000 R10C9C.F0 to R10C9C.DI0 UFMCLK_RNO (to RCLK_c) + -------- + 8.222 (29.4% logic, 70.6% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 1.425 86.PADDI to R10C4C.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_51: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 1.425 86.PADDI to R10C9C.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 7.653ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[4] (from RCLK_c +) Destination: FF Data in LEDEN (to RCLK_c +) - Delay: 8.414ns (28.7% logic, 71.3% route), 6 logic levels. + Delay: 8.103ns (20.6% logic, 79.4% route), 4 logic levels. Constraint Details: - 8.414ns physical path delay SLICE_2 to SLICE_33 meets + 8.103ns physical path delay SLICE_7 to SLICE_33 meets 16.000ns delay constraint less 0.000ns skew and - 0.244ns CE_SET requirement (totaling 15.756ns) by 7.342ns + 0.244ns CE_SET requirement (totaling 15.756ns) by 7.653ns Physical Path Details: - Data path SLICE_2 to SLICE_33: + Data path SLICE_7 to SLICE_33: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C5D.CLK to R8C5D.Q1 SLICE_2 (from RCLK_c) -ROUTE 3 1.571 R8C5D.Q1 to R7C6A.B1 FS[15] -CTOF_DEL --- 0.371 R7C6A.B1 to R7C6A.F1 SLICE_81 -ROUTE 1 0.626 R7C6A.F1 to R7C6D.D1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 R7C6D.D1 to R7C6D.F1 SLICE_72 -ROUTE 4 0.657 R7C6D.F1 to R7C6B.D1 N_51 -CTOF_DEL --- 0.371 R7C6B.D1 to R7C6B.F1 SLICE_58 -ROUTE 2 1.169 R7C6B.F1 to R8C7B.D0 N_151 -CTOF_DEL --- 0.371 R8C7B.D0 to R8C7B.F0 SLICE_87 -ROUTE 2 0.716 R8C7B.F0 to R8C6B.D0 N_137_8 -CTOF_DEL --- 0.371 R8C6B.D0 to R8C6B.F0 SLICE_69 -ROUTE 1 1.260 R8C6B.F0 to R9C9B.CE N_33 (to RCLK_c) +REG_DEL --- 0.560 R10C3C.CLK to R10C3C.Q0 SLICE_7 (from RCLK_c) +ROUTE 3 2.172 R10C3C.Q0 to R4C9B.D1 FS[4] +CTOF_DEL --- 0.371 R4C9B.D1 to R4C9B.F1 SLICE_56 +ROUTE 2 2.098 R4C9B.F1 to R9C5A.D1 N_43 +CTOF_DEL --- 0.371 R9C5A.D1 to R9C5A.F1 SLICE_72 +ROUTE 1 0.626 R9C5A.F1 to R9C5A.D0 un1_FS_13_i_a2_1 +CTOF_DEL --- 0.371 R9C5A.D0 to R9C5A.F0 SLICE_72 +ROUTE 1 1.534 R9C5A.F0 to R9C9B.CE N_26 (to RCLK_c) -------- - 8.414 (28.7% logic, 71.3% route), 6 logic levels. + 8.103 (20.6% logic, 79.4% route), 4 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_2: + Source Clock Path RCLK to SLICE_7: Name Fanout Delay (ns) Site Resource -ROUTE 32 1.425 86.PADDI to R8C5D.CLK RCLK_c +ROUTE 32 1.425 86.PADDI to R10C3C.CLK RCLK_c -------- 1.425 (0.0% logic, 100.0% route), 0 logic levels. @@ -735,267 +803,55 @@ ROUTE 32 1.425 86.PADDI to R9C9B.CLK RCLK_c 1.425 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 7.396ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[13] (from RCLK_c +) - Destination: FF Data in n8MEGEN (to RCLK_c +) - - Delay: 8.360ns (28.9% logic, 71.1% route), 6 logic levels. - - Constraint Details: - - 8.360ns physical path delay SLICE_3 to SLICE_58 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.244ns CE_SET requirement (totaling 15.756ns) by 7.396ns - - Physical Path Details: - - Data path SLICE_3 to SLICE_58: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C5C.CLK to R8C5C.Q1 SLICE_3 (from RCLK_c) -ROUTE 3 1.511 R8C5C.Q1 to R7C6A.A1 FS[13] -CTOF_DEL --- 0.371 R7C6A.A1 to R7C6A.F1 SLICE_81 -ROUTE 1 0.626 R7C6A.F1 to R7C6D.D1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 R7C6D.D1 to R7C6D.F1 SLICE_72 -ROUTE 4 0.657 R7C6D.F1 to R7C6B.D1 N_51 -CTOF_DEL --- 0.371 R7C6B.D1 to R7C6B.F1 SLICE_58 -ROUTE 2 1.169 R7C6B.F1 to R8C7B.D0 N_151 -CTOF_DEL --- 0.371 R8C7B.D0 to R8C7B.F0 SLICE_87 -ROUTE 2 0.909 R8C7B.F0 to R8C6C.C0 N_137_8 -CTOF_DEL --- 0.371 R8C6C.C0 to R8C6C.F0 SLICE_68 -ROUTE 1 1.073 R8C6C.F0 to R7C6B.CE N_31 (to RCLK_c) - -------- - 8.360 (28.9% logic, 71.1% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_3: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 1.425 86.PADDI to R8C5C.CLK RCLK_c - -------- - 1.425 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_58: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 1.425 86.PADDI to R7C6B.CLK RCLK_c - -------- - 1.425 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 7.402ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[13] (from RCLK_c +) - Destination: FF Data in LEDEN (to RCLK_c +) - - Delay: 8.354ns (28.9% logic, 71.1% route), 6 logic levels. - - Constraint Details: - - 8.354ns physical path delay SLICE_3 to SLICE_33 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.244ns CE_SET requirement (totaling 15.756ns) by 7.402ns - - Physical Path Details: - - Data path SLICE_3 to SLICE_33: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C5C.CLK to R8C5C.Q1 SLICE_3 (from RCLK_c) -ROUTE 3 1.511 R8C5C.Q1 to R7C6A.A1 FS[13] -CTOF_DEL --- 0.371 R7C6A.A1 to R7C6A.F1 SLICE_81 -ROUTE 1 0.626 R7C6A.F1 to R7C6D.D1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 R7C6D.D1 to R7C6D.F1 SLICE_72 -ROUTE 4 0.657 R7C6D.F1 to R7C6B.D1 N_51 -CTOF_DEL --- 0.371 R7C6B.D1 to R7C6B.F1 SLICE_58 -ROUTE 2 1.169 R7C6B.F1 to R8C7B.D0 N_151 -CTOF_DEL --- 0.371 R8C7B.D0 to R8C7B.F0 SLICE_87 -ROUTE 2 0.716 R8C7B.F0 to R8C6B.D0 N_137_8 -CTOF_DEL --- 0.371 R8C6B.D0 to R8C6B.F0 SLICE_69 -ROUTE 1 1.260 R8C6B.F0 to R9C9B.CE N_33 (to RCLK_c) - -------- - 8.354 (28.9% logic, 71.1% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_3: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 1.425 86.PADDI to R8C5C.CLK RCLK_c - -------- - 1.425 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_33: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 1.425 86.PADDI to R9C9B.CLK RCLK_c - -------- - 1.425 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 7.475ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[15] (from RCLK_c +) - Destination: FF Data in UFMSDI (to RCLK_c +) - - Delay: 8.344ns (28.9% logic, 71.1% route), 6 logic levels. - - Constraint Details: - - 8.344ns physical path delay SLICE_2 to SLICE_52 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.181ns DIN_SET requirement (totaling 15.819ns) by 7.475ns - - Physical Path Details: - - Data path SLICE_2 to SLICE_52: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C5D.CLK to R8C5D.Q1 SLICE_2 (from RCLK_c) -ROUTE 3 1.571 R8C5D.Q1 to R7C6A.B1 FS[15] -CTOF_DEL --- 0.371 R7C6A.B1 to R7C6A.F1 SLICE_81 -ROUTE 1 0.626 R7C6A.F1 to R7C6D.D1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 R7C6D.D1 to R7C6D.F1 SLICE_72 -ROUTE 4 0.657 R7C6D.F1 to R7C6B.D1 N_51 -CTOF_DEL --- 0.371 R7C6B.D1 to R7C6B.F1 SLICE_58 -ROUTE 2 1.919 R7C6B.F1 to R8C7B.B1 N_151 -CTOF_DEL --- 0.371 R8C7B.B1 to R8C7B.F1 SLICE_87 -ROUTE 1 1.156 R8C7B.F1 to R9C9C.D0 UFMSDI_r_xx_mm_1 -CTOF_DEL --- 0.371 R9C9C.D0 to R9C9C.F0 SLICE_52 -ROUTE 1 0.000 R9C9C.F0 to R9C9C.DI0 UFMSDI_RNO (to RCLK_c) - -------- - 8.344 (28.9% logic, 71.1% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_2: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 1.425 86.PADDI to R8C5D.CLK RCLK_c - -------- - 1.425 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_52: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 1.425 86.PADDI to R9C9C.CLK RCLK_c - -------- - 1.425 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 7.535ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[13] (from RCLK_c +) - Destination: FF Data in UFMSDI (to RCLK_c +) - - Delay: 8.284ns (29.2% logic, 70.8% route), 6 logic levels. - - Constraint Details: - - 8.284ns physical path delay SLICE_3 to SLICE_52 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.181ns DIN_SET requirement (totaling 15.819ns) by 7.535ns - - Physical Path Details: - - Data path SLICE_3 to SLICE_52: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C5C.CLK to R8C5C.Q1 SLICE_3 (from RCLK_c) -ROUTE 3 1.511 R8C5C.Q1 to R7C6A.A1 FS[13] -CTOF_DEL --- 0.371 R7C6A.A1 to R7C6A.F1 SLICE_81 -ROUTE 1 0.626 R7C6A.F1 to R7C6D.D1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 R7C6D.D1 to R7C6D.F1 SLICE_72 -ROUTE 4 0.657 R7C6D.F1 to R7C6B.D1 N_51 -CTOF_DEL --- 0.371 R7C6B.D1 to R7C6B.F1 SLICE_58 -ROUTE 2 1.919 R7C6B.F1 to R8C7B.B1 N_151 -CTOF_DEL --- 0.371 R8C7B.B1 to R8C7B.F1 SLICE_87 -ROUTE 1 1.156 R8C7B.F1 to R9C9C.D0 UFMSDI_r_xx_mm_1 -CTOF_DEL --- 0.371 R9C9C.D0 to R9C9C.F0 SLICE_52 -ROUTE 1 0.000 R9C9C.F0 to R9C9C.DI0 UFMSDI_RNO (to RCLK_c) - -------- - 8.284 (29.2% logic, 70.8% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_3: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 1.425 86.PADDI to R8C5C.CLK RCLK_c - -------- - 1.425 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_52: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 1.425 86.PADDI to R9C9C.CLK RCLK_c - -------- - 1.425 (0.0% logic, 100.0% route), 0 logic levels. - - Passed: The following path meets requirements by 7.721ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[14] (from RCLK_c +) - Destination: FF Data in n8MEGEN (to RCLK_c +) + Destination: FF Data in UFMCLK (to RCLK_c +) - Delay: 8.035ns (30.1% logic, 69.9% route), 6 logic levels. + Delay: 8.098ns (29.8% logic, 70.2% route), 6 logic levels. Constraint Details: - 8.035ns physical path delay SLICE_2 to SLICE_58 meets + 8.098ns physical path delay SLICE_2 to SLICE_51 meets 16.000ns delay constraint less 0.000ns skew and - 0.244ns CE_SET requirement (totaling 15.756ns) by 7.721ns + 0.181ns DIN_SET requirement (totaling 15.819ns) by 7.721ns Physical Path Details: - Data path SLICE_2 to SLICE_58: + Data path SLICE_2 to SLICE_51: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C5D.CLK to R8C5D.Q0 SLICE_2 (from RCLK_c) -ROUTE 3 1.186 R8C5D.Q0 to R7C6A.D1 FS[14] -CTOF_DEL --- 0.371 R7C6A.D1 to R7C6A.F1 SLICE_81 -ROUTE 1 0.626 R7C6A.F1 to R7C6D.D1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 R7C6D.D1 to R7C6D.F1 SLICE_72 -ROUTE 4 0.657 R7C6D.F1 to R7C6B.D1 N_51 -CTOF_DEL --- 0.371 R7C6B.D1 to R7C6B.F1 SLICE_58 -ROUTE 2 1.169 R7C6B.F1 to R8C7B.D0 N_151 -CTOF_DEL --- 0.371 R8C7B.D0 to R8C7B.F0 SLICE_87 -ROUTE 2 0.909 R8C7B.F0 to R8C6C.C0 N_137_8 -CTOF_DEL --- 0.371 R8C6C.C0 to R8C6C.F0 SLICE_68 -ROUTE 1 1.073 R8C6C.F0 to R7C6B.CE N_31 (to RCLK_c) +REG_DEL --- 0.560 R10C4D.CLK to R10C4D.Q0 SLICE_2 (from RCLK_c) +ROUTE 3 0.924 R10C4D.Q0 to R10C5C.C1 FS[14] +CTOF_DEL --- 0.371 R10C5C.C1 to R10C5C.F1 SLICE_86 +ROUTE 1 1.026 R10C5C.F1 to R10C6D.A1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.371 R10C6D.A1 to R10C6D.F1 SLICE_69 +ROUTE 4 1.689 R10C6D.F1 to R10C6D.B0 N_128 +CTOF_DEL --- 0.371 R10C6D.B0 to R10C6D.F0 SLICE_69 +ROUTE 1 1.547 R10C6D.F0 to R10C9C.B1 N_129 +CTOF_DEL --- 0.371 R10C9C.B1 to R10C9C.F1 SLICE_51 +ROUTE 1 0.497 R10C9C.F1 to R10C9C.C0 UFMCLK_r_i_m4_xx_mm_1 +CTOF_DEL --- 0.371 R10C9C.C0 to R10C9C.F0 SLICE_51 +ROUTE 1 0.000 R10C9C.F0 to R10C9C.DI0 UFMCLK_RNO (to RCLK_c) -------- - 8.035 (30.1% logic, 69.9% route), 6 logic levels. + 8.098 (29.8% logic, 70.2% route), 6 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_2: Name Fanout Delay (ns) Site Resource -ROUTE 32 1.425 86.PADDI to R8C5D.CLK RCLK_c +ROUTE 32 1.425 86.PADDI to R10C4D.CLK RCLK_c -------- 1.425 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_58: + Destination Clock Path RCLK to SLICE_51: Name Fanout Delay (ns) Site Resource -ROUTE 32 1.425 86.PADDI to R7C6B.CLK RCLK_c +ROUTE 32 1.425 86.PADDI to R10C9C.CLK RCLK_c -------- 1.425 (0.0% logic, 100.0% route), 0 logic levels. @@ -1004,10 +860,10 @@ Passed: The following path meets requirements by 7.727ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS[14] (from RCLK_c +) + Source: FF Q FS[15] (from RCLK_c +) Destination: FF Data in LEDEN (to RCLK_c +) - Delay: 8.029ns (30.1% logic, 69.9% route), 6 logic levels. + Delay: 8.029ns (25.5% logic, 74.5% route), 5 logic levels. Constraint Details: @@ -1021,27 +877,25 @@ Passed: The following path meets requirements by 7.727ns Data path SLICE_2 to SLICE_33: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C5D.CLK to R8C5D.Q0 SLICE_2 (from RCLK_c) -ROUTE 3 1.186 R8C5D.Q0 to R7C6A.D1 FS[14] -CTOF_DEL --- 0.371 R7C6A.D1 to R7C6A.F1 SLICE_81 -ROUTE 1 0.626 R7C6A.F1 to R7C6D.D1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 R7C6D.D1 to R7C6D.F1 SLICE_72 -ROUTE 4 0.657 R7C6D.F1 to R7C6B.D1 N_51 -CTOF_DEL --- 0.371 R7C6B.D1 to R7C6B.F1 SLICE_58 -ROUTE 2 1.169 R7C6B.F1 to R8C7B.D0 N_151 -CTOF_DEL --- 0.371 R8C7B.D0 to R8C7B.F0 SLICE_87 -ROUTE 2 0.716 R8C7B.F0 to R8C6B.D0 N_137_8 -CTOF_DEL --- 0.371 R8C6B.D0 to R8C6B.F0 SLICE_69 -ROUTE 1 1.260 R8C6B.F0 to R9C9B.CE N_33 (to RCLK_c) +REG_DEL --- 0.560 R10C4D.CLK to R10C4D.Q1 SLICE_2 (from RCLK_c) +ROUTE 3 1.116 R10C4D.Q1 to R10C5C.B1 FS[15] +CTOF_DEL --- 0.371 R10C5C.B1 to R10C5C.F1 SLICE_86 +ROUTE 1 1.026 R10C5C.F1 to R10C6D.A1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.371 R10C6D.A1 to R10C6D.F1 SLICE_69 +ROUTE 4 1.201 R10C6D.F1 to R9C7B.D1 N_128 +CTOF_DEL --- 0.371 R9C7B.D1 to R9C7B.F1 SLICE_58 +ROUTE 3 1.108 R9C7B.F1 to R9C5A.B0 N_94 +CTOF_DEL --- 0.371 R9C5A.B0 to R9C5A.F0 SLICE_72 +ROUTE 1 1.534 R9C5A.F0 to R9C9B.CE N_26 (to RCLK_c) -------- - 8.029 (30.1% logic, 69.9% route), 6 logic levels. + 8.029 (25.5% logic, 74.5% route), 5 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_2: Name Fanout Delay (ns) Site Resource -ROUTE 32 1.425 86.PADDI to R8C5D.CLK RCLK_c +ROUTE 32 1.425 86.PADDI to R10C4D.CLK RCLK_c -------- 1.425 (0.0% logic, 100.0% route), 0 logic levels. @@ -1053,48 +907,148 @@ ROUTE 32 1.425 86.PADDI to R9C9B.CLK RCLK_c 1.425 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 7.860ns +Passed: The following path meets requirements by 7.795ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS[14] (from RCLK_c +) - Destination: FF Data in UFMSDI (to RCLK_c +) + Source: FF Q FS[12] (from RCLK_c +) + Destination: FF Data in LEDEN (to RCLK_c +) - Delay: 7.959ns (30.3% logic, 69.7% route), 6 logic levels. + Delay: 7.961ns (25.7% logic, 74.3% route), 5 logic levels. Constraint Details: - 7.959ns physical path delay SLICE_2 to SLICE_52 meets + 7.961ns physical path delay SLICE_3 to SLICE_33 meets 16.000ns delay constraint less 0.000ns skew and - 0.181ns DIN_SET requirement (totaling 15.819ns) by 7.860ns + 0.244ns CE_SET requirement (totaling 15.756ns) by 7.795ns + + Physical Path Details: + + Data path SLICE_3 to SLICE_33: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R10C4C.CLK to R10C4C.Q0 SLICE_3 (from RCLK_c) +ROUTE 3 1.048 R10C4C.Q0 to R10C5C.A1 FS[12] +CTOF_DEL --- 0.371 R10C5C.A1 to R10C5C.F1 SLICE_86 +ROUTE 1 1.026 R10C5C.F1 to R10C6D.A1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.371 R10C6D.A1 to R10C6D.F1 SLICE_69 +ROUTE 4 1.201 R10C6D.F1 to R9C7B.D1 N_128 +CTOF_DEL --- 0.371 R9C7B.D1 to R9C7B.F1 SLICE_58 +ROUTE 3 1.108 R9C7B.F1 to R9C5A.B0 N_94 +CTOF_DEL --- 0.371 R9C5A.B0 to R9C5A.F0 SLICE_72 +ROUTE 1 1.534 R9C5A.F0 to R9C9B.CE N_26 (to RCLK_c) + -------- + 7.961 (25.7% logic, 74.3% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 1.425 86.PADDI to R10C4C.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_33: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 1.425 86.PADDI to R9C9B.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 7.823ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[11] (from RCLK_c +) + Destination: FF Data in LEDEN (to RCLK_c +) + + Delay: 7.933ns (21.1% logic, 78.9% route), 4 logic levels. + + Constraint Details: + + 7.933ns physical path delay SLICE_4 to SLICE_33 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.244ns CE_SET requirement (totaling 15.756ns) by 7.823ns + + Physical Path Details: + + Data path SLICE_4 to SLICE_33: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R10C4B.CLK to R10C4B.Q1 SLICE_4 (from RCLK_c) +ROUTE 6 2.002 R10C4B.Q1 to R4C9B.C1 FS[11] +CTOF_DEL --- 0.371 R4C9B.C1 to R4C9B.F1 SLICE_56 +ROUTE 2 2.098 R4C9B.F1 to R9C5A.D1 N_43 +CTOF_DEL --- 0.371 R9C5A.D1 to R9C5A.F1 SLICE_72 +ROUTE 1 0.626 R9C5A.F1 to R9C5A.D0 un1_FS_13_i_a2_1 +CTOF_DEL --- 0.371 R9C5A.D0 to R9C5A.F0 SLICE_72 +ROUTE 1 1.534 R9C5A.F0 to R9C9B.CE N_26 (to RCLK_c) + -------- + 7.933 (21.1% logic, 78.9% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_4: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 1.425 86.PADDI to R10C4B.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_33: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 1.425 86.PADDI to R9C9B.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 7.864ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[15] (from RCLK_c +) + Destination: FF Data in UFMSDI (to RCLK_c +) + + Delay: 7.955ns (30.4% logic, 69.6% route), 6 logic levels. + + Constraint Details: + + 7.955ns physical path delay SLICE_2 to SLICE_52 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.181ns DIN_SET requirement (totaling 15.819ns) by 7.864ns Physical Path Details: Data path SLICE_2 to SLICE_52: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C5D.CLK to R8C5D.Q0 SLICE_2 (from RCLK_c) -ROUTE 3 1.186 R8C5D.Q0 to R7C6A.D1 FS[14] -CTOF_DEL --- 0.371 R7C6A.D1 to R7C6A.F1 SLICE_81 -ROUTE 1 0.626 R7C6A.F1 to R7C6D.D1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 R7C6D.D1 to R7C6D.F1 SLICE_72 -ROUTE 4 0.657 R7C6D.F1 to R7C6B.D1 N_51 -CTOF_DEL --- 0.371 R7C6B.D1 to R7C6B.F1 SLICE_58 -ROUTE 2 1.919 R7C6B.F1 to R8C7B.B1 N_151 -CTOF_DEL --- 0.371 R8C7B.B1 to R8C7B.F1 SLICE_87 -ROUTE 1 1.156 R8C7B.F1 to R9C9C.D0 UFMSDI_r_xx_mm_1 -CTOF_DEL --- 0.371 R9C9C.D0 to R9C9C.F0 SLICE_52 +REG_DEL --- 0.560 R10C4D.CLK to R10C4D.Q1 SLICE_2 (from RCLK_c) +ROUTE 3 1.116 R10C4D.Q1 to R10C5C.B1 FS[15] +CTOF_DEL --- 0.371 R10C5C.B1 to R10C5C.F1 SLICE_86 +ROUTE 1 1.026 R10C5C.F1 to R10C6D.A1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.371 R10C6D.A1 to R10C6D.F1 SLICE_69 +ROUTE 4 1.201 R10C6D.F1 to R9C7B.D1 N_128 +CTOF_DEL --- 0.371 R9C7B.D1 to R9C7B.F1 SLICE_58 +ROUTE 3 1.171 R9C7B.F1 to R10C9A.D0 N_94 +CTOF_DEL --- 0.371 R10C9A.D0 to R10C9A.F0 SLICE_55 +ROUTE 1 1.026 R10C9A.F0 to R9C9C.A0 UFMSDI_r_xx_mm_1 +CTOF_DEL --- 0.371 R9C9C.A0 to R9C9C.F0 SLICE_52 ROUTE 1 0.000 R9C9C.F0 to R9C9C.DI0 UFMSDI_RNO (to RCLK_c) -------- - 7.959 (30.3% logic, 69.7% route), 6 logic levels. + 7.955 (30.4% logic, 69.6% route), 6 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_2: Name Fanout Delay (ns) Site Resource -ROUTE 32 1.425 86.PADDI to R8C5D.CLK RCLK_c +ROUTE 32 1.425 86.PADDI to R10C4D.CLK RCLK_c -------- 1.425 (0.0% logic, 100.0% route), 0 logic levels. @@ -1106,59 +1060,110 @@ ROUTE 32 1.425 86.PADDI to R9C9C.CLK RCLK_c 1.425 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 7.998ns +Passed: The following path meets requirements by 7.884ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS[17] (from RCLK_c +) - Destination: FF Data in n8MEGEN (to RCLK_c +) + Source: FF Q FS[15] (from RCLK_c +) + Destination: FF Data in UFMSDI (to RCLK_c +) - Delay: 7.758ns (31.1% logic, 68.9% route), 6 logic levels. + Delay: 7.935ns (30.4% logic, 69.6% route), 6 logic levels. Constraint Details: - 7.758ns physical path delay SLICE_1 to SLICE_58 meets + 7.935ns physical path delay SLICE_2 to SLICE_52 meets 16.000ns delay constraint less 0.000ns skew and - 0.244ns CE_SET requirement (totaling 15.756ns) by 7.998ns + 0.181ns DIN_SET requirement (totaling 15.819ns) by 7.884ns Physical Path Details: - Data path SLICE_1 to SLICE_58: + Data path SLICE_2 to SLICE_52: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C6A.CLK to R8C6A.Q1 SLICE_1 (from RCLK_c) -ROUTE 3 0.909 R8C6A.Q1 to R7C6A.C1 FS[17] -CTOF_DEL --- 0.371 R7C6A.C1 to R7C6A.F1 SLICE_81 -ROUTE 1 0.626 R7C6A.F1 to R7C6D.D1 UFMSDI_ens2_i_o2_0_3 -CTOF_DEL --- 0.371 R7C6D.D1 to R7C6D.F1 SLICE_72 -ROUTE 4 0.657 R7C6D.F1 to R7C6B.D1 N_51 -CTOF_DEL --- 0.371 R7C6B.D1 to R7C6B.F1 SLICE_58 -ROUTE 2 1.169 R7C6B.F1 to R8C7B.D0 N_151 -CTOF_DEL --- 0.371 R8C7B.D0 to R8C7B.F0 SLICE_87 -ROUTE 2 0.909 R8C7B.F0 to R8C6C.C0 N_137_8 -CTOF_DEL --- 0.371 R8C6C.C0 to R8C6C.F0 SLICE_68 -ROUTE 1 1.073 R8C6C.F0 to R7C6B.CE N_31 (to RCLK_c) +REG_DEL --- 0.560 R10C4D.CLK to R10C4D.Q1 SLICE_2 (from RCLK_c) +ROUTE 3 1.116 R10C4D.Q1 to R10C5C.B1 FS[15] +CTOF_DEL --- 0.371 R10C5C.B1 to R10C5C.F1 SLICE_86 +ROUTE 1 1.026 R10C5C.F1 to R10C6D.A1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.371 R10C6D.A1 to R10C6D.F1 SLICE_69 +ROUTE 4 0.865 R10C6D.F1 to R10C6A.C1 N_128 +CTOF_DEL --- 0.371 R10C6A.C1 to R10C6A.F1 SLICE_32 +ROUTE 1 1.487 R10C6A.F1 to R10C9A.A0 UFMSDI_ens2_i_a0 +CTOF_DEL --- 0.371 R10C9A.A0 to R10C9A.F0 SLICE_55 +ROUTE 1 1.026 R10C9A.F0 to R9C9C.A0 UFMSDI_r_xx_mm_1 +CTOF_DEL --- 0.371 R9C9C.A0 to R9C9C.F0 SLICE_52 +ROUTE 1 0.000 R9C9C.F0 to R9C9C.DI0 UFMSDI_RNO (to RCLK_c) -------- - 7.758 (31.1% logic, 68.9% route), 6 logic levels. + 7.935 (30.4% logic, 69.6% route), 6 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_1: + Source Clock Path RCLK to SLICE_2: Name Fanout Delay (ns) Site Resource -ROUTE 32 1.425 86.PADDI to R8C6A.CLK RCLK_c +ROUTE 32 1.425 86.PADDI to R10C4D.CLK RCLK_c -------- 1.425 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_58: + Destination Clock Path RCLK to SLICE_52: Name Fanout Delay (ns) Site Resource -ROUTE 32 1.425 86.PADDI to R7C6B.CLK RCLK_c +ROUTE 32 1.425 86.PADDI to R9C9C.CLK RCLK_c -------- 1.425 (0.0% logic, 100.0% route), 0 logic levels. -Report: 115.420MHz is the maximum frequency for this preference. + +Passed: The following path meets requirements by 7.919ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[14] (from RCLK_c +) + Destination: FF Data in LEDEN (to RCLK_c +) + + Delay: 7.837ns (26.1% logic, 73.9% route), 5 logic levels. + + Constraint Details: + + 7.837ns physical path delay SLICE_2 to SLICE_33 meets + 16.000ns delay constraint less + 0.000ns skew and + 0.244ns CE_SET requirement (totaling 15.756ns) by 7.919ns + + Physical Path Details: + + Data path SLICE_2 to SLICE_33: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R10C4D.CLK to R10C4D.Q0 SLICE_2 (from RCLK_c) +ROUTE 3 0.924 R10C4D.Q0 to R10C5C.C1 FS[14] +CTOF_DEL --- 0.371 R10C5C.C1 to R10C5C.F1 SLICE_86 +ROUTE 1 1.026 R10C5C.F1 to R10C6D.A1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.371 R10C6D.A1 to R10C6D.F1 SLICE_69 +ROUTE 4 1.201 R10C6D.F1 to R9C7B.D1 N_128 +CTOF_DEL --- 0.371 R9C7B.D1 to R9C7B.F1 SLICE_58 +ROUTE 3 1.108 R9C7B.F1 to R9C5A.B0 N_94 +CTOF_DEL --- 0.371 R9C5A.B0 to R9C5A.F0 SLICE_72 +ROUTE 1 1.534 R9C5A.F0 to R9C9B.CE N_26 (to RCLK_c) + -------- + 7.837 (26.1% logic, 73.9% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_2: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 1.425 86.PADDI to R10C4D.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_33: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 1.425 86.PADDI to R9C9B.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + +Report: 118.050MHz is the maximum frequency for this preference. Report Summary -------------- @@ -1166,13 +1171,13 @@ Report: 115.420MHz is the maximum frequency for this preference. Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | -FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 42.550 MHz| 6 +FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 45.049 MHz| 6 | | | FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 400.000 MHz| 0 | | | FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 400.000 MHz| 0 | | | -FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 115.420 MHz| 6 +FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 118.050 MHz| 6 | | | ---------------------------------------------------------------------------- @@ -1227,11 +1232,11 @@ Clock Domain: PHI2_c Source: PHI2.PAD Loads: 15 Timing errors: 0 Score: 0 Cumulative negative slack: 0 -Constraints cover 517 paths, 4 nets, and 421 connections (66.51% coverage) +Constraints cover 560 paths, 4 nets, and 450 connections (66.08% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 -Thu Sep 21 05:38:43 2023 +Sat Jan 06 06:25:20 2024 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -1250,13 +1255,13 @@ Report level: verbose report, limited to 10 items per preference Preference Summary -
  • FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)
    • 129 items scored, 0 timing errors detected. +
  • FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)
    • 168 items scored, 0 timing errors detected.
  • FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)
    • 0 items scored, 0 timing errors detected.
  • FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)
    • 0 items scored, 0 timing errors detected. -
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    • 388 items scored, 0 timing errors detected. +
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    • 392 items scored, 0 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS @@ -1266,51 +1271,51 @@ BLOCK RESETPATHS ================================================================================ Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ; - 129 items scored, 0 timing errors detected. + 168 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- -Passed: The following path meets requirements by 0.358ns +Passed: The following path meets requirements by 0.360ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q ADSubmitted (from PHI2_c -) - Destination: FF Data in ADSubmitted (to PHI2_c -) + Source: FF Q CmdEnable (from PHI2_c -) + Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 0.339ns (62.2% logic, 37.8% route), 2 logic levels. + Delay: 0.341ns (61.9% logic, 38.1% route), 2 logic levels. Constraint Details: - 0.339ns physical path delay SLICE_9 to SLICE_9 meets + 0.341ns physical path delay SLICE_20 to SLICE_20 meets -0.019ns DIN_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.358ns + 0.000ns skew requirement (totaling -0.019ns) by 0.360ns Physical Path Details: - Data path SLICE_9 to SLICE_9: + Data path SLICE_20 to SLICE_20: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R6C2A.CLK to R6C2A.Q0 SLICE_9 (from PHI2_c) -ROUTE 2 0.128 R6C2A.Q0 to R6C2A.D0 ADSubmitted -CTOF_DEL --- 0.074 R6C2A.D0 to R6C2A.F0 SLICE_9 -ROUTE 1 0.000 R6C2A.F0 to R6C2A.DI0 ADSubmitted_r (to PHI2_c) +REG_DEL --- 0.137 R8C6A.CLK to R8C6A.Q0 SLICE_20 (from PHI2_c) +ROUTE 2 0.130 R8C6A.Q0 to R8C6A.D0 CmdEnable +CTOF_DEL --- 0.074 R8C6A.D0 to R8C6A.F0 SLICE_20 +ROUTE 1 0.000 R8C6A.F0 to R8C6A.DI0 CmdEnable_s (to PHI2_c) -------- - 0.339 (62.2% logic, 37.8% route), 2 logic levels. + 0.341 (61.9% logic, 38.1% route), 2 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_9: + Source Clock Path PHI2 to SLICE_20: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R6C2A.CLK PHI2_c +ROUTE 15 0.907 39.PADDI to R8C6A.CLK PHI2_c -------- 0.907 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_9: + Destination Clock Path PHI2 to SLICE_20: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R6C2A.CLK PHI2_c +ROUTE 15 0.907 39.PADDI to R8C6A.CLK PHI2_c -------- 0.907 (0.0% logic, 100.0% route), 0 logic levels. @@ -1336,10 +1341,10 @@ Passed: The following path meets requirements by 0.361ns Data path SLICE_14 to SLICE_14: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R7C3C.CLK to R7C3C.Q0 SLICE_14 (from PHI2_c) -ROUTE 2 0.131 R7C3C.Q0 to R7C3C.A0 C1Submitted -CTOF_DEL --- 0.074 R7C3C.A0 to R7C3C.F0 SLICE_14 -ROUTE 1 0.000 R7C3C.F0 to R7C3C.DI0 C1Submitted_RNO (to PHI2_c) +REG_DEL --- 0.137 R8C6C.CLK to R8C6C.Q0 SLICE_14 (from PHI2_c) +ROUTE 2 0.131 R8C6C.Q0 to R8C6C.A0 C1Submitted +CTOF_DEL --- 0.074 R8C6C.A0 to R8C6C.F0 SLICE_14 +ROUTE 1 0.000 R8C6C.F0 to R8C6C.DI0 C1Submitted_RNO (to PHI2_c) -------- 0.342 (61.7% logic, 38.3% route), 2 logic levels. @@ -1348,14 +1353,59 @@ ROUTE 1 0.000 R7C3C.F0 to R7C3C.DI0 C1Submitted_RNO (to P Source Clock Path PHI2 to SLICE_14: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R7C3C.CLK PHI2_c +ROUTE 15 0.907 39.PADDI to R8C6C.CLK PHI2_c -------- 0.907 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_14: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R7C3C.CLK PHI2_c +ROUTE 15 0.907 39.PADDI to R8C6C.CLK PHI2_c + -------- + 0.907 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.361ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q ADSubmitted (from PHI2_c -) + Destination: FF Data in ADSubmitted (to PHI2_c -) + + Delay: 0.342ns (61.7% logic, 38.3% route), 2 logic levels. + + Constraint Details: + + 0.342ns physical path delay SLICE_9 to SLICE_9 meets + -0.019ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.361ns + + Physical Path Details: + + Data path SLICE_9 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R8C6B.CLK to R8C6B.Q0 SLICE_9 (from PHI2_c) +ROUTE 2 0.131 R8C6B.Q0 to R8C6B.A0 ADSubmitted +CTOF_DEL --- 0.074 R8C6B.A0 to R8C6B.F0 SLICE_9 +ROUTE 1 0.000 R8C6B.F0 to R8C6B.DI0 ADSubmitted_r (to PHI2_c) + -------- + 0.342 (61.7% logic, 38.3% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 0.907 39.PADDI to R8C6B.CLK PHI2_c + -------- + 0.907 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 0.907 39.PADDI to R8C6B.CLK PHI2_c -------- 0.907 (0.0% logic, 100.0% route), 0 logic levels. @@ -1381,10 +1431,10 @@ Passed: The following path meets requirements by 0.364ns Data path SLICE_22 to SLICE_22: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R8C9D.CLK to R8C9D.Q0 SLICE_22 (from PHI2_c) -ROUTE 3 0.134 R8C9D.Q0 to R8C9D.A0 CmdSubmitted -CTOF_DEL --- 0.074 R8C9D.A0 to R8C9D.F0 SLICE_22 -ROUTE 1 0.000 R8C9D.F0 to R8C9D.DI0 N_460_0 (to PHI2_c) +REG_DEL --- 0.137 R9C6B.CLK to R9C6B.Q0 SLICE_22 (from PHI2_c) +ROUTE 3 0.134 R9C6B.Q0 to R9C6B.A0 CmdSubmitted +CTOF_DEL --- 0.074 R9C6B.A0 to R9C6B.F0 SLICE_22 +ROUTE 1 0.000 R9C6B.F0 to R9C6B.DI0 N_428_0 (to PHI2_c) -------- 0.345 (61.2% logic, 38.8% route), 2 logic levels. @@ -1393,333 +1443,294 @@ ROUTE 1 0.000 R8C9D.F0 to R8C9D.DI0 N_460_0 (to PHI2_c) Source Clock Path PHI2 to SLICE_22: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R8C9D.CLK PHI2_c +ROUTE 15 0.907 39.PADDI to R9C6B.CLK PHI2_c -------- 0.907 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_22: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R8C9D.CLK PHI2_c +ROUTE 15 0.907 39.PADDI to R9C6B.CLK PHI2_c -------- 0.907 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 0.411ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CmdEnable (from PHI2_c -) - Destination: FF Data in CmdEnable (to PHI2_c -) - - Delay: 0.392ns (65.8% logic, 34.2% route), 2 logic levels. - - Constraint Details: - - 0.392ns physical path delay SLICE_20 to SLICE_20 meets - -0.019ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.411ns - - Physical Path Details: - - Data path SLICE_20 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R6C2D.CLK to R6C2D.Q0 SLICE_20 (from PHI2_c) -ROUTE 3 0.134 R6C2D.Q0 to R6C2D.D1 CmdEnable -CTOOFX_DEL --- 0.121 R6C2D.D1 to R6C2D.OFX0 SLICE_20 -ROUTE 1 0.000 R6C2D.OFX0 to R6C2D.DI0 CmdEnable_s (to PHI2_c) - -------- - 0.392 (65.8% logic, 34.2% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R6C2D.CLK PHI2_c - -------- - 0.907 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R6C2D.CLK PHI2_c - -------- - 0.907 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.415ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CmdEnable (from PHI2_c -) - Destination: FF Data in CmdEnable (to PHI2_c -) - - Delay: 0.396ns (66.2% logic, 33.8% route), 2 logic levels. - - Constraint Details: - - 0.396ns physical path delay SLICE_20 to SLICE_20 meets - -0.019ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.415ns - - Physical Path Details: - - Data path SLICE_20 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R6C2D.CLK to R6C2D.Q0 SLICE_20 (from PHI2_c) -ROUTE 3 0.134 R6C2D.Q0 to R6C2D.A0 CmdEnable -CTOOFX_DEL --- 0.125 R6C2D.A0 to R6C2D.OFX0 SLICE_20 -ROUTE 1 0.000 R6C2D.OFX0 to R6C2D.DI0 CmdEnable_s (to PHI2_c) - -------- - 0.396 (66.2% logic, 33.8% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R6C2D.CLK PHI2_c - -------- - 0.907 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R6C2D.CLK PHI2_c - -------- - 0.907 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.471ns +Passed: The following path meets requirements by 0.572ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ADSubmitted (from PHI2_c -) Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 0.452ns (57.1% logic, 42.9% route), 2 logic levels. + Delay: 0.553ns (51.5% logic, 48.5% route), 3 logic levels. Constraint Details: - 0.452ns physical path delay SLICE_9 to SLICE_20 meets + 0.553ns physical path delay SLICE_9 to SLICE_20 meets -0.019ns DIN_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.471ns + 0.000ns skew requirement (totaling -0.019ns) by 0.572ns Physical Path Details: Data path SLICE_9 to SLICE_20: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R6C2A.CLK to R6C2A.Q0 SLICE_9 (from PHI2_c) -ROUTE 2 0.194 R6C2A.Q0 to R6C2D.A1 ADSubmitted -CTOOFX_DEL --- 0.121 R6C2D.A1 to R6C2D.OFX0 SLICE_20 -ROUTE 1 0.000 R6C2D.OFX0 to R6C2D.DI0 CmdEnable_s (to PHI2_c) +REG_DEL --- 0.137 R8C6B.CLK to R8C6B.Q0 SLICE_9 (from PHI2_c) +ROUTE 2 0.130 R8C6B.Q0 to R8C6A.D1 ADSubmitted +CTOF_DEL --- 0.074 R8C6A.D1 to R8C6A.F1 SLICE_20 +ROUTE 1 0.138 R8C6A.F1 to R8C6A.B0 CmdEnable_0_sqmuxa +CTOF_DEL --- 0.074 R8C6A.B0 to R8C6A.F0 SLICE_20 +ROUTE 1 0.000 R8C6A.F0 to R8C6A.DI0 CmdEnable_s (to PHI2_c) -------- - 0.452 (57.1% logic, 42.9% route), 2 logic levels. + 0.553 (51.5% logic, 48.5% route), 3 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_9: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R6C2A.CLK PHI2_c +ROUTE 15 0.907 39.PADDI to R8C6B.CLK PHI2_c -------- 0.907 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_20: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R6C2D.CLK PHI2_c +ROUTE 15 0.907 39.PADDI to R8C6A.CLK PHI2_c -------- 0.907 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 0.611ns +Passed: The following path meets requirements by 0.597ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Cmdn8MEGEN (from PHI2_c -) Destination: FF Data in Cmdn8MEGEN (to PHI2_c -) - Delay: 0.592ns (48.1% logic, 51.9% route), 3 logic levels. + Delay: 0.578ns (49.3% logic, 50.7% route), 3 logic levels. Constraint Details: - 0.592ns physical path delay SLICE_26 to SLICE_26 meets + 0.578ns physical path delay SLICE_26 to SLICE_26 meets -0.019ns DIN_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.611ns + 0.000ns skew requirement (totaling -0.019ns) by 0.597ns Physical Path Details: Data path SLICE_26 to SLICE_26: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R7C5B.CLK to R7C5B.Q0 SLICE_26 (from PHI2_c) -ROUTE 2 0.208 R7C5B.Q0 to R7C5B.B1 Cmdn8MEGEN -CTOF_DEL --- 0.074 R7C5B.B1 to R7C5B.F1 SLICE_26 -ROUTE 1 0.099 R7C5B.F1 to R7C5B.C0 Cmdn8MEGEN_4_u_i_0 -CTOF_DEL --- 0.074 R7C5B.C0 to R7C5B.F0 SLICE_26 -ROUTE 1 0.000 R7C5B.F0 to R7C5B.DI0 N_19_i (to PHI2_c) +REG_DEL --- 0.137 R9C7D.CLK to R9C7D.Q0 SLICE_26 (from PHI2_c) +ROUTE 2 0.194 R9C7D.Q0 to R9C7D.A1 Cmdn8MEGEN +CTOF_DEL --- 0.074 R9C7D.A1 to R9C7D.F1 SLICE_26 +ROUTE 1 0.099 R9C7D.F1 to R9C7D.C0 Cmdn8MEGEN_4_u_i_0 +CTOF_DEL --- 0.074 R9C7D.C0 to R9C7D.F0 SLICE_26 +ROUTE 1 0.000 R9C7D.F0 to R9C7D.DI0 N_12_i (to PHI2_c) -------- - 0.592 (48.1% logic, 51.9% route), 3 logic levels. + 0.578 (49.3% logic, 50.7% route), 3 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_26: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R7C5B.CLK PHI2_c +ROUTE 15 0.907 39.PADDI to R9C7D.CLK PHI2_c -------- 0.907 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_26: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R7C5B.CLK PHI2_c +ROUTE 15 0.907 39.PADDI to R9C7D.CLK PHI2_c -------- 0.907 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 0.634ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q C1Submitted (from PHI2_c -) - Destination: FF Data in CmdEnable (to PHI2_c -) - - Delay: 0.615ns (42.6% logic, 57.4% route), 2 logic levels. - - Constraint Details: - - 0.615ns physical path delay SLICE_14 to SLICE_20 meets - -0.019ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.634ns - - Physical Path Details: - - Data path SLICE_14 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R7C3C.CLK to R7C3C.Q0 SLICE_14 (from PHI2_c) -ROUTE 2 0.353 R7C3C.Q0 to R6C2D.C0 C1Submitted -CTOOFX_DEL --- 0.125 R6C2D.C0 to R6C2D.OFX0 SLICE_20 -ROUTE 1 0.000 R6C2D.OFX0 to R6C2D.DI0 CmdEnable_s (to PHI2_c) - -------- - 0.615 (42.6% logic, 57.4% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_14: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R7C3C.CLK PHI2_c - -------- - 0.907 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R6C2D.CLK PHI2_c - -------- - 0.907 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.665ns +Passed: The following path meets requirements by 0.599ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CmdLEDEN (from PHI2_c -) Destination: FF Data in CmdLEDEN (to PHI2_c -) - Delay: 0.646ns (44.1% logic, 55.9% route), 3 logic levels. + Delay: 0.580ns (49.1% logic, 50.9% route), 3 logic levels. Constraint Details: - 0.646ns physical path delay SLICE_21 to SLICE_21 meets + 0.580ns physical path delay SLICE_21 to SLICE_21 meets -0.019ns DIN_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.665ns + 0.000ns skew requirement (totaling -0.019ns) by 0.599ns Physical Path Details: Data path SLICE_21 to SLICE_21: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R7C5A.CLK to R7C5A.Q0 SLICE_21 (from PHI2_c) -ROUTE 2 0.169 R7C5A.Q0 to R7C5C.C1 CmdLEDEN -CTOF_DEL --- 0.074 R7C5C.C1 to R7C5C.F1 SLICE_82 -ROUTE 1 0.192 R7C5C.F1 to R7C5A.A0 N_132 -CTOF_DEL --- 0.074 R7C5A.A0 to R7C5A.F0 SLICE_21 -ROUTE 1 0.000 R7C5A.F0 to R7C5A.DI0 N_21_i (to PHI2_c) +REG_DEL --- 0.137 R9C8D.CLK to R9C8D.Q0 SLICE_21 (from PHI2_c) +ROUTE 2 0.196 R9C8D.Q0 to R9C8D.A1 CmdLEDEN +CTOF_DEL --- 0.074 R9C8D.A1 to R9C8D.F1 SLICE_21 +ROUTE 1 0.099 R9C8D.F1 to R9C8D.C0 CmdLEDEN_4_u_i_0 +CTOF_DEL --- 0.074 R9C8D.C0 to R9C8D.F0 SLICE_21 +ROUTE 1 0.000 R9C8D.F0 to R9C8D.DI0 N_14_i (to PHI2_c) -------- - 0.646 (44.1% logic, 55.9% route), 3 logic levels. + 0.580 (49.1% logic, 50.9% route), 3 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_21: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R7C5A.CLK PHI2_c +ROUTE 15 0.907 39.PADDI to R9C8D.CLK PHI2_c -------- 0.907 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_21: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R7C5A.CLK PHI2_c +ROUTE 15 0.907 39.PADDI to R9C8D.CLK PHI2_c -------- 0.907 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 0.723ns +Passed: The following path meets requirements by 0.626ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q C1Submitted (from PHI2_c -) + Destination: FF Data in CmdEnable (to PHI2_c -) + + Delay: 0.607ns (47.0% logic, 53.0% route), 3 logic levels. + + Constraint Details: + + 0.607ns physical path delay SLICE_14 to SLICE_20 meets + -0.019ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.626ns + + Physical Path Details: + + Data path SLICE_14 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R8C6C.CLK to R8C6C.Q0 SLICE_14 (from PHI2_c) +ROUTE 2 0.130 R8C6C.Q0 to R8C6C.D1 C1Submitted +CTOF_DEL --- 0.074 R8C6C.D1 to R8C6C.F1 SLICE_14 +ROUTE 1 0.192 R8C6C.F1 to R8C6A.A0 un1_CmdEnable20_i +CTOF_DEL --- 0.074 R8C6A.A0 to R8C6A.F0 SLICE_20 +ROUTE 1 0.000 R8C6A.F0 to R8C6A.DI0 CmdEnable_s (to PHI2_c) + -------- + 0.607 (47.0% logic, 53.0% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 0.907 39.PADDI to R8C6C.CLK PHI2_c + -------- + 0.907 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 0.907 39.PADDI to R8C6A.CLK PHI2_c + -------- + 0.907 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.638ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q XOR8MEG (from PHI2_c -) + Destination: FF Data in XOR8MEG (to PHI2_c -) + + Delay: 0.619ns (46.0% logic, 54.0% route), 3 logic levels. + + Constraint Details: + + 0.619ns physical path delay SLICE_57 to SLICE_57 meets + -0.019ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.638ns + + Physical Path Details: + + Data path SLICE_57 to SLICE_57: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R9C8A.CLK to R9C8A.Q0 SLICE_57 (from PHI2_c) +ROUTE 2 0.196 R9C8A.Q0 to R9C8A.A1 XOR8MEG +CTOF_DEL --- 0.074 R9C8A.A1 to R9C8A.F1 SLICE_57 +ROUTE 1 0.138 R9C8A.F1 to R9C8A.B0 N_166 +CTOF_DEL --- 0.074 R9C8A.B0 to R9C8A.F0 SLICE_57 +ROUTE 1 0.000 R9C8A.F0 to R9C8A.DI0 XOR8MEG_3 (to PHI2_c) + -------- + 0.619 (46.0% logic, 54.0% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_57: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 0.907 39.PADDI to R9C8A.CLK PHI2_c + -------- + 0.907 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_57: + + Name Fanout Delay (ns) Site Resource +ROUTE 15 0.907 39.PADDI to R9C8A.CLK PHI2_c + -------- + 0.907 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.659ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CmdEnable (from PHI2_c -) Destination: FF Data in CmdLEDEN (to PHI2_c -) - Delay: 0.700ns (30.1% logic, 69.9% route), 2 logic levels. + Delay: 0.636ns (33.2% logic, 66.8% route), 2 logic levels. Constraint Details: - 0.700ns physical path delay SLICE_20 to SLICE_21 meets + 0.636ns physical path delay SLICE_20 to SLICE_21 meets -0.023ns CE_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.023ns) by 0.723ns + 0.000ns skew requirement (totaling -0.023ns) by 0.659ns Physical Path Details: Data path SLICE_20 to SLICE_21: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.137 R6C2D.CLK to R6C2D.Q0 SLICE_20 (from PHI2_c) -ROUTE 3 0.348 R6C2D.Q0 to R7C5D.B0 CmdEnable -CTOF_DEL --- 0.074 R7C5D.B0 to R7C5D.F0 SLICE_67 -ROUTE 5 0.141 R7C5D.F0 to R7C5A.CE XOR8MEG18 (to PHI2_c) +REG_DEL --- 0.137 R8C6A.CLK to R8C6A.Q0 SLICE_20 (from PHI2_c) +ROUTE 2 0.183 R8C6A.Q0 to R9C6A.C0 CmdEnable +CTOF_DEL --- 0.074 R9C6A.C0 to R9C6A.F0 SLICE_73 +ROUTE 5 0.242 R9C6A.F0 to R9C8D.CE XOR8MEG18 (to PHI2_c) -------- - 0.700 (30.1% logic, 69.9% route), 2 logic levels. + 0.636 (33.2% logic, 66.8% route), 2 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_20: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R6C2D.CLK PHI2_c +ROUTE 15 0.907 39.PADDI to R8C6A.CLK PHI2_c -------- 0.907 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_21: Name Fanout Delay (ns) Site Resource -ROUTE 15 0.907 39.PADDI to R7C5A.CLK PHI2_c +ROUTE 15 0.907 39.PADDI to R9C8D.CLK PHI2_c -------- 0.907 (0.0% logic, 100.0% route), 0 logic levels. @@ -1738,7 +1749,7 @@ ROUTE 15 0.907 39.PADDI to R7C5A.CLK PHI2_c ================================================================================ Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; - 388 items scored, 0 timing errors detected. + 392 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- @@ -1753,78 +1764,163 @@ Passed: The following path meets requirements by 0.273ns Constraint Details: - 0.256ns physical path delay SLICE_75 to SLICE_75 meets + 0.256ns physical path delay SLICE_74 to SLICE_74 meets -0.017ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.017ns) by 0.273ns Physical Path Details: - Data path SLICE_75 to SLICE_75: + Data path SLICE_74 to SLICE_74: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.126 R7C4B.CLK to R7C4B.Q0 SLICE_75 (from RCLK_c) -ROUTE 1 0.130 R7C4B.Q0 to R7C4B.M1 CASr (to RCLK_c) +REG_DEL --- 0.126 R8C7B.CLK to R8C7B.Q0 SLICE_74 (from RCLK_c) +ROUTE 1 0.130 R8C7B.Q0 to R8C7B.M1 CASr (to RCLK_c) -------- 0.256 (49.2% logic, 50.8% route), 1 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_75: + Source Clock Path RCLK to SLICE_74: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R7C4B.CLK RCLK_c +ROUTE 32 0.351 86.PADDI to R8C7B.CLK RCLK_c -------- 0.351 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_75: + Destination Clock Path RCLK to SLICE_74: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R7C4B.CLK RCLK_c +ROUTE 32 0.351 86.PADDI to R8C7B.CLK RCLK_c -------- 0.351 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 0.301ns +Passed: The following path meets requirements by 0.277ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS[17] (from RCLK_c +) - Destination: FF Data in FS[17] (to RCLK_c +) - FF FS[16] + Source: FF Q PHI2r2 (from RCLK_c +) + Destination: FF Data in PHI2r3 (to RCLK_c +) - Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels. + Delay: 0.260ns (48.5% logic, 51.5% route), 1 logic levels. Constraint Details: - 0.257ns physical path delay SLICE_1 to SLICE_1 meets - -0.044ns LUT_HLD and + 0.260ns physical path delay SLICE_41 to SLICE_43 meets + -0.017ns M_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.044ns) by 0.301ns + 0.000ns skew requirement (totaling -0.017ns) by 0.277ns Physical Path Details: - Data path SLICE_1 to SLICE_1: + Data path SLICE_41 to SLICE_43: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.126 R8C6A.CLK to R8C6A.Q1 SLICE_1 (from RCLK_c) -ROUTE 3 0.131 R8C6A.Q1 to R8C6A.A1 FS[17] (to RCLK_c) +REG_DEL --- 0.126 R4C6C.CLK to R4C6C.Q1 SLICE_41 (from RCLK_c) +ROUTE 3 0.134 R4C6C.Q1 to R4C6A.M1 PHI2r2 (to RCLK_c) -------- - 0.257 (49.0% logic, 51.0% route), 1 logic levels. + 0.260 (48.5% logic, 51.5% route), 1 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_1: + Source Clock Path RCLK to SLICE_41: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R8C6A.CLK RCLK_c +ROUTE 32 0.351 86.PADDI to R4C6C.CLK RCLK_c -------- 0.351 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_1: + Destination Clock Path RCLK to SLICE_43: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R8C6A.CLK RCLK_c +ROUTE 32 0.351 86.PADDI to R4C6A.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.277ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RASr (from RCLK_c +) + Destination: FF Data in RASr2 (to RCLK_c +) + + Delay: 0.260ns (48.5% logic, 51.5% route), 1 logic levels. + + Constraint Details: + + 0.260ns physical path delay SLICE_95 to SLICE_95 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.277ns + + Physical Path Details: + + Data path SLICE_95 to SLICE_95: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R3C5D.CLK to R3C5D.Q0 SLICE_95 (from RCLK_c) +ROUTE 2 0.134 R3C5D.Q0 to R3C5D.M1 RASr (to RCLK_c) + -------- + 0.260 (48.5% logic, 51.5% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_95: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 0.351 86.PADDI to R3C5D.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_95: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 0.351 86.PADDI to R3C5D.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.284ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RASr2 (from RCLK_c +) + Destination: FF Data in S[0] (to RCLK_c +) + + Delay: 0.267ns (47.2% logic, 52.8% route), 1 logic levels. + + Constraint Details: + + 0.267ns physical path delay SLICE_95 to SLICE_68 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.284ns + + Physical Path Details: + + Data path SLICE_95 to SLICE_68: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R3C5D.CLK to R3C5D.Q1 SLICE_95 (from RCLK_c) +ROUTE 13 0.141 R3C5D.Q1 to R3C5C.M0 RASr2 (to RCLK_c) + -------- + 0.267 (47.2% logic, 52.8% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_95: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 0.351 86.PADDI to R3C5D.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_68: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 0.351 86.PADDI to R3C5C.CLK RCLK_c -------- 0.351 (0.0% logic, 100.0% route), 0 logic levels. @@ -1852,8 +1948,8 @@ Passed: The following path meets requirements by 0.301ns Data path SLICE_2 to SLICE_2: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.126 R8C5D.CLK to R8C5D.Q1 SLICE_2 (from RCLK_c) -ROUTE 3 0.131 R8C5D.Q1 to R8C5D.A1 FS[15] (to RCLK_c) +REG_DEL --- 0.126 R10C4D.CLK to R10C4D.Q1 SLICE_2 (from RCLK_c) +ROUTE 3 0.131 R10C4D.Q1 to R10C4D.A1 FS[15] (to RCLK_c) -------- 0.257 (49.0% logic, 51.0% route), 1 logic levels. @@ -1862,14 +1958,14 @@ ROUTE 3 0.131 R8C5D.Q1 to R8C5D.A1 FS[15] (to RCLK_c) Source Clock Path RCLK to SLICE_2: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R8C5D.CLK RCLK_c +ROUTE 32 0.351 86.PADDI to R10C4D.CLK RCLK_c -------- 0.351 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_2: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R8C5D.CLK RCLK_c +ROUTE 32 0.351 86.PADDI to R10C4D.CLK RCLK_c -------- 0.351 (0.0% logic, 100.0% route), 0 logic levels. @@ -1897,8 +1993,8 @@ Passed: The following path meets requirements by 0.301ns Data path SLICE_3 to SLICE_3: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.126 R8C5C.CLK to R8C5C.Q1 SLICE_3 (from RCLK_c) -ROUTE 3 0.131 R8C5C.Q1 to R8C5C.A1 FS[13] (to RCLK_c) +REG_DEL --- 0.126 R10C4C.CLK to R10C4C.Q1 SLICE_3 (from RCLK_c) +ROUTE 4 0.131 R10C4C.Q1 to R10C4C.A1 FS[13] (to RCLK_c) -------- 0.257 (49.0% logic, 51.0% route), 1 logic levels. @@ -1907,14 +2003,104 @@ ROUTE 3 0.131 R8C5C.Q1 to R8C5C.A1 FS[13] (to RCLK_c) Source Clock Path RCLK to SLICE_3: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R8C5C.CLK RCLK_c +ROUTE 32 0.351 86.PADDI to R10C4C.CLK RCLK_c -------- 0.351 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_3: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R8C5C.CLK RCLK_c +ROUTE 32 0.351 86.PADDI to R10C4C.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.301ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[9] (from RCLK_c +) + Destination: FF Data in FS_cry_0[8] (to RCLK_c +) + FF FS[9] + FF FS[8] + + Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels. + + Constraint Details: + + 0.257ns physical path delay SLICE_5 to SLICE_5 meets + -0.044ns LUT_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.044ns) by 0.301ns + + Physical Path Details: + + Data path SLICE_5 to SLICE_5: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R10C4A.CLK to R10C4A.Q1 SLICE_5 (from RCLK_c) +ROUTE 3 0.131 R10C4A.Q1 to R10C4A.A1 FS[9] (to RCLK_c) + -------- + 0.257 (49.0% logic, 51.0% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_5: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 0.351 86.PADDI to R10C4A.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_5: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 0.351 86.PADDI to R10C4A.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.301ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[7] (from RCLK_c +) + Destination: FF Data in FS_cry_0[6] (to RCLK_c +) + FF FS[7] + FF FS[6] + + Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels. + + Constraint Details: + + 0.257ns physical path delay SLICE_6 to SLICE_6 meets + -0.044ns LUT_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.044ns) by 0.301ns + + Physical Path Details: + + Data path SLICE_6 to SLICE_6: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R10C3D.CLK to R10C3D.Q1 SLICE_6 (from RCLK_c) +ROUTE 3 0.131 R10C3D.Q1 to R10C3D.A1 FS[7] (to RCLK_c) + -------- + 0.257 (49.0% logic, 51.0% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_6: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 0.351 86.PADDI to R10C3D.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_6: + + Name Fanout Delay (ns) Site Resource +ROUTE 32 0.351 86.PADDI to R10C3D.CLK RCLK_c -------- 0.351 (0.0% logic, 100.0% route), 0 logic levels. @@ -1942,8 +2128,8 @@ Passed: The following path meets requirements by 0.301ns Data path SLICE_7 to SLICE_7: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.126 R8C4C.CLK to R8C4C.Q1 SLICE_7 (from RCLK_c) -ROUTE 4 0.131 R8C4C.Q1 to R8C4C.A1 FS[5] (to RCLK_c) +REG_DEL --- 0.126 R10C3C.CLK to R10C3C.Q1 SLICE_7 (from RCLK_c) +ROUTE 4 0.131 R10C3C.Q1 to R10C3C.A1 FS[5] (to RCLK_c) -------- 0.257 (49.0% logic, 51.0% route), 1 logic levels. @@ -1952,14 +2138,14 @@ ROUTE 4 0.131 R8C4C.Q1 to R8C4C.A1 FS[5] (to RCLK_c) Source Clock Path RCLK to SLICE_7: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R8C4C.CLK RCLK_c +ROUTE 32 0.351 86.PADDI to R10C3C.CLK RCLK_c -------- 0.351 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_7: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R8C4C.CLK RCLK_c +ROUTE 32 0.351 86.PADDI to R10C3C.CLK RCLK_c -------- 0.351 (0.0% logic, 100.0% route), 0 logic levels. @@ -1987,8 +2173,8 @@ Passed: The following path meets requirements by 0.301ns Data path SLICE_8 to SLICE_8: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.126 R8C4B.CLK to R8C4B.Q1 SLICE_8 (from RCLK_c) -ROUTE 3 0.131 R8C4B.Q1 to R8C4B.A1 FS[3] (to RCLK_c) +REG_DEL --- 0.126 R10C3B.CLK to R10C3B.Q1 SLICE_8 (from RCLK_c) +ROUTE 2 0.131 R10C3B.Q1 to R10C3B.A1 FS[3] (to RCLK_c) -------- 0.257 (49.0% logic, 51.0% route), 1 logic levels. @@ -1997,194 +2183,14 @@ ROUTE 3 0.131 R8C4B.Q1 to R8C4B.A1 FS[3] (to RCLK_c) Source Clock Path RCLK to SLICE_8: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R8C4B.CLK RCLK_c +ROUTE 32 0.351 86.PADDI to R10C3B.CLK RCLK_c -------- 0.351 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_8: Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R8C4B.CLK RCLK_c - -------- - 0.351 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.302ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[0] (from RCLK_c +) - Destination: FF Data in FS_cry_0[0] (to RCLK_c +) - FF FS[1] - FF FS[0] - - Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels. - - Constraint Details: - - 0.257ns physical path delay SLICE_0 to SLICE_0 meets - -0.045ns LUT_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.045ns) by 0.302ns - - Physical Path Details: - - Data path SLICE_0 to SLICE_0: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.126 R8C4A.CLK to R8C4A.Q0 SLICE_0 (from RCLK_c) -ROUTE 3 0.131 R8C4A.Q0 to R8C4A.A0 FS[0] (to RCLK_c) - -------- - 0.257 (49.0% logic, 51.0% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_0: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R8C4A.CLK RCLK_c - -------- - 0.351 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_0: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R8C4A.CLK RCLK_c - -------- - 0.351 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.302ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[10] (from RCLK_c +) - Destination: FF Data in FS_cry_0[10] (to RCLK_c +) - FF FS[11] - FF FS[10] - - Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels. - - Constraint Details: - - 0.257ns physical path delay SLICE_4 to SLICE_4 meets - -0.045ns LUT_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.045ns) by 0.302ns - - Physical Path Details: - - Data path SLICE_4 to SLICE_4: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.126 R8C5B.CLK to R8C5B.Q0 SLICE_4 (from RCLK_c) -ROUTE 5 0.131 R8C5B.Q0 to R8C5B.A0 FS[10] (to RCLK_c) - -------- - 0.257 (49.0% logic, 51.0% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_4: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R8C5B.CLK RCLK_c - -------- - 0.351 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_4: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R8C5B.CLK RCLK_c - -------- - 0.351 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.302ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[8] (from RCLK_c +) - Destination: FF Data in FS_cry_0[8] (to RCLK_c +) - FF FS[9] - FF FS[8] - - Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels. - - Constraint Details: - - 0.257ns physical path delay SLICE_5 to SLICE_5 meets - -0.045ns LUT_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.045ns) by 0.302ns - - Physical Path Details: - - Data path SLICE_5 to SLICE_5: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.126 R8C5A.CLK to R8C5A.Q0 SLICE_5 (from RCLK_c) -ROUTE 3 0.131 R8C5A.Q0 to R8C5A.A0 FS[8] (to RCLK_c) - -------- - 0.257 (49.0% logic, 51.0% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_5: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R8C5A.CLK RCLK_c - -------- - 0.351 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_5: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R8C5A.CLK RCLK_c - -------- - 0.351 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.302ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[6] (from RCLK_c +) - Destination: FF Data in FS_cry_0[6] (to RCLK_c +) - FF FS[7] - FF FS[6] - - Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels. - - Constraint Details: - - 0.257ns physical path delay SLICE_6 to SLICE_6 meets - -0.045ns LUT_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.045ns) by 0.302ns - - Physical Path Details: - - Data path SLICE_6 to SLICE_6: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.126 R8C4D.CLK to R8C4D.Q0 SLICE_6 (from RCLK_c) -ROUTE 3 0.131 R8C4D.Q0 to R8C4D.A0 FS[6] (to RCLK_c) - -------- - 0.257 (49.0% logic, 51.0% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_6: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R8C4D.CLK RCLK_c - -------- - 0.351 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_6: - - Name Fanout Delay (ns) Site Resource -ROUTE 32 0.351 86.PADDI to R8C4D.CLK RCLK_c +ROUTE 32 0.351 86.PADDI to R10C3B.CLK RCLK_c -------- 0.351 (0.0% logic, 100.0% route), 0 logic levels. @@ -2255,7 +2261,7 @@ Clock Domain: PHI2_c Source: PHI2.PAD Loads: 15 Timing errors: 0 Score: 0 Cumulative negative slack: 0 -Constraints cover 517 paths, 4 nets, and 421 connections (66.51% coverage) +Constraints cover 560 paths, 4 nets, and 450 connections (66.08% coverage) diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_vo.sdf b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_vo.sdf index 0b7a1bb..18187a4 100644 --- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_vo.sdf +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_vo.sdf @@ -1,7 +1,7 @@ (DELAYFILE (SDFVERSION "3.0") (DESIGN "RAM2GS") - (DATE "Thu Sep 21 05:38:45 2023") + (DATE "Sat Jan 06 06:25:23 2024") (VENDOR "Lattice") (PROGRAM "ldbanno") (VERSION "Diamond (64-bit) 3.12.1.454") @@ -172,10 +172,8 @@ (INSTANCE SLICE_9) (DELAY (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) @@ -196,6 +194,7 @@ (INSTANCE SLICE_14) (DELAY (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) @@ -215,40 +214,18 @@ ) ) (CELL - (CELLTYPE "SLICE_19") - (INSTANCE SLICE_19) + (CELLTYPE "SLICE_20") + (INSTANCE SLICE_20) (DELAY (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) - (IOPATH CLK Q0 (515:537:560)(515:537:560)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) - (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1000:1000:1000)) - (WIDTH (negedge CLK) (1000:1000:1000)) - ) - ) - (CELL - (CELLTYPE "SLICE_20") - (INSTANCE SLICE_20) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (496:555:615)(496:555:615)) - (IOPATH A1 OFX0 (496:555:615)(496:555:615)) - (IOPATH D0 OFX0 (508:569:631)(508:569:631)) - (IOPATH C0 OFX0 (508:569:631)(508:569:631)) - (IOPATH B0 OFX0 (508:569:631)(508:569:631)) - (IOPATH A0 OFX0 (508:569:631)(508:569:631)) - (IOPATH M0 OFX0 (405:453:501)(405:453:501)) (IOPATH CLK Q0 (560:586:613)(560:586:613)) ) ) @@ -268,10 +245,10 @@ (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (560:586:613)(560:586:613)) ) ) @@ -293,7 +270,7 @@ (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (560:586:613)(560:586:613)) ) @@ -338,15 +315,16 @@ (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) ) ) (TIMINGCHECK (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) ) (TIMINGCHECK (WIDTH (posedge CLK) (1000:1000:1000)) @@ -359,7 +337,7 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) - (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) @@ -411,7 +389,7 @@ (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (515:537:560)(515:537:560)) ) @@ -431,6 +409,7 @@ (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) @@ -447,16 +426,40 @@ (WIDTH (negedge CLK) (1000:1000:1000)) ) ) + (CELL + (CELLTYPE "SLICE_38") + (INSTANCE SLICE_38) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) (CELL (CELLTYPE "SLICE_39") (INSTANCE SLICE_39) (DELAY (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (515:537:560)(515:537:560)) ) ) @@ -502,7 +505,6 @@ (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH C0 F0 (301:336:371)(301:336:371)) @@ -556,7 +558,7 @@ (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (515:537:560)(515:537:560)) (IOPATH CLK Q1 (515:537:560)(515:537:560)) @@ -578,8 +580,8 @@ (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (515:537:560)(515:537:560)) ) @@ -607,12 +609,10 @@ (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (515:537:560)(515:537:560)) - (IOPATH CLK Q1 (515:537:560)(515:537:560)) ) ) (TIMINGCHECK (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) - (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) ) (TIMINGCHECK (WIDTH (posedge CLK) (1000:1000:1000)) @@ -633,12 +633,10 @@ (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (515:537:560)(515:537:560)) - (IOPATH CLK Q1 (515:537:560)(515:537:560)) ) ) (TIMINGCHECK (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) - (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) ) (TIMINGCHECK (WIDTH (posedge CLK) (1000:1000:1000)) @@ -651,7 +649,7 @@ (DELAY (ABSOLUTE (IOPATH D0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (560:586:613)(560:586:613)) (IOPATH CLK Q1 (560:586:613)(560:586:613)) @@ -673,9 +671,6 @@ (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (560:586:613)(560:586:613)) @@ -696,9 +691,7 @@ (INSTANCE SLICE_57) (DELAY (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH C0 F0 (301:336:371)(301:336:371)) @@ -723,9 +716,9 @@ (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (515:537:560)(515:537:560)) ) @@ -747,7 +740,6 @@ (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) @@ -768,7 +760,6 @@ (INSTANCE SLICE_60) (DELAY (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) @@ -906,6 +897,7 @@ (INSTANCE SLICE_66) (DELAY (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) @@ -913,19 +905,8 @@ (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) - (IOPATH CLK Q0 (560:586:613)(560:586:613)) - (IOPATH CLK Q1 (560:586:613)(560:586:613)) ) ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1000:1000:1000)) - (WIDTH (negedge CLK) (1000:1000:1000)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) - (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) - (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) - ) ) (CELL (CELLTYPE "SLICE_67") @@ -935,7 +916,6 @@ (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) @@ -967,8 +947,17 @@ (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) ) ) + (TIMINGCHECK + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) ) (CELL (CELLTYPE "SLICE_69") @@ -976,78 +965,12 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) - (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) - ) - ) - ) - (CELL - (CELLTYPE "SLICE_70") - (INSTANCE SLICE_70) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) - (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH CLK Q0 (515:537:560)(515:537:560)) - (IOPATH CLK Q1 (515:537:560)(515:537:560)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) - (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1000:1000:1000)) - (WIDTH (negedge CLK) (1000:1000:1000)) - ) - ) - (CELL - (CELLTYPE "SLICE_71") - (INSTANCE SLICE_71) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) - (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH D0 F0 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) - (IOPATH CLK Q0 (515:537:560)(515:537:560)) - (IOPATH CLK Q1 (515:537:560)(515:537:560)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) - (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1000:1000:1000)) - (WIDTH (negedge CLK) (1000:1000:1000)) - ) - ) - (CELL - (CELLTYPE "SLICE_72") - (INSTANCE SLICE_72) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) - (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH D0 F0 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (560:586:613)(560:586:613)) (IOPATH CLK Q1 (560:586:613)(560:586:613)) ) @@ -1062,6 +985,51 @@ (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) ) ) + (CELL + (CELLTYPE "SLICE_70") + (INSTANCE SLICE_70) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_71") + (INSTANCE SLICE_71) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_72") + (INSTANCE SLICE_72) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + ) + ) + ) (CELL (CELLTYPE "SLICE_73") (INSTANCE SLICE_73) @@ -1071,8 +1039,8 @@ (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (560:586:613)(560:586:613)) (IOPATH CLK Q1 (560:586:613)(560:586:613)) ) @@ -1084,7 +1052,7 @@ (TIMINGCHECK (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) - (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) ) ) (CELL @@ -1092,34 +1060,36 @@ (INSTANCE SLICE_74) (DELAY (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) - (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) ) ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) (TIMINGCHECK (WIDTH (posedge CLK) (1000:1000:1000)) (WIDTH (negedge CLK) (1000:1000:1000)) ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) - (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) - ) ) (CELL (CELLTYPE "SLICE_75") (INSTANCE SLICE_75) (DELAY (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (515:537:560)(515:537:560)) (IOPATH CLK Q1 (515:537:560)(515:537:560)) @@ -1140,7 +1110,9 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) @@ -1161,6 +1133,36 @@ (CELL (CELLTYPE "SLICE_77") (INSTANCE SLICE_77) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_78") + (INSTANCE SLICE_78) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_79") + (INSTANCE SLICE_79) (DELAY (ABSOLUTE (IOPATH C1 F1 (301:336:371)(301:336:371)) @@ -1182,55 +1184,6 @@ (WIDTH (negedge CLK) (1000:1000:1000)) ) ) - (CELL - (CELLTYPE "SLICE_78") - (INSTANCE SLICE_78) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH D0 F0 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) - (IOPATH CLK Q0 (560:586:613)(560:586:613)) - (IOPATH CLK Q1 (560:586:613)(560:586:613)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1000:1000:1000)) - (WIDTH (negedge CLK) (1000:1000:1000)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) - (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) - ) - ) - (CELL - (CELLTYPE "SLICE_79") - (INSTANCE SLICE_79) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) - (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH D0 F0 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) - (IOPATH CLK Q0 (560:586:613)(560:586:613)) - (IOPATH CLK Q1 (560:586:613)(560:586:613)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1000:1000:1000)) - (WIDTH (negedge CLK) (1000:1000:1000)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) - (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) - ) - ) (CELL (CELLTYPE "SLICE_80") (INSTANCE SLICE_80) @@ -1242,19 +1195,8 @@ (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) - (IOPATH CLK Q0 (560:586:613)(560:586:613)) - (IOPATH CLK Q1 (560:586:613)(560:586:613)) ) ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1000:1000:1000)) - (WIDTH (negedge CLK) (1000:1000:1000)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) - (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) - (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) - ) ) (CELL (CELLTYPE "SLICE_81") @@ -1269,6 +1211,21 @@ (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_82") + (INSTANCE SLICE_82) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (560:586:613)(560:586:613)) (IOPATH CLK Q1 (560:586:613)(560:586:613)) ) @@ -1283,8 +1240,8 @@ ) ) (CELL - (CELLTYPE "SLICE_82") - (INSTANCE SLICE_82) + (CELLTYPE "SLICE_83") + (INSTANCE SLICE_83) (DELAY (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) @@ -1295,28 +1252,6 @@ (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) - (IOPATH CLK Q0 (515:537:560)(515:537:560)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1000:1000:1000)) - (WIDTH (negedge CLK) (1000:1000:1000)) - ) - ) - (CELL - (CELLTYPE "SLICE_83") - (INSTANCE SLICE_83) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH D0 F0 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (560:586:613)(560:586:613)) (IOPATH CLK Q1 (560:586:613)(560:586:613)) ) @@ -1344,12 +1279,64 @@ (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) ) ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) ) (CELL (CELLTYPE "SLICE_85") (INSTANCE SLICE_85) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_86") + (INSTANCE SLICE_86) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_87") + (INSTANCE SLICE_87) (DELAY (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) @@ -1374,43 +1361,41 @@ ) ) (CELL - (CELLTYPE "SLICE_86") - (INSTANCE SLICE_86) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) - (IOPATH A0 F0 (301:336:371)(301:336:371)) - ) - ) - ) - (CELL - (CELLTYPE "SLICE_87") - (INSTANCE SLICE_87) + (CELLTYPE "SLICE_88") + (INSTANCE SLICE_88) (DELAY (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) ) ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) ) (CELL - (CELLTYPE "SLICE_88") - (INSTANCE SLICE_88) + (CELLTYPE "SLICE_89") + (INSTANCE SLICE_89) (DELAY (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) (IOPATH CLK Q0 (560:586:613)(560:586:613)) (IOPATH CLK Q1 (560:586:613)(560:586:613)) ) @@ -1425,32 +1410,29 @@ (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) ) ) - (CELL - (CELLTYPE "SLICE_89") - (INSTANCE SLICE_89) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (301:336:371)(301:336:371)) - (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH D0 F0 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH B0 F0 (301:336:371)(301:336:371)) - ) - ) - ) (CELL (CELLTYPE "SLICE_90") (INSTANCE SLICE_90) (DELAY (ABSOLUTE (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH A1 F1 (301:336:371)(301:336:371)) - (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) ) ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) ) (CELL (CELLTYPE "SLICE_91") @@ -1458,11 +1440,10 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) - (IOPATH C1 F1 (301:336:371)(301:336:371)) - (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) - (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) ) ) ) @@ -1477,12 +1458,91 @@ (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH C0 F0 (301:336:371)(301:336:371)) (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) ) ) ) (CELL (CELLTYPE "SLICE_93") (INSTANCE SLICE_93) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_94") + (INSTANCE SLICE_94) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_95") + (INSTANCE SLICE_95) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_96") + (INSTANCE SLICE_96) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_97") + (INSTANCE SLICE_97) (DELAY (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) @@ -1495,25 +1555,69 @@ ) ) (CELL - (CELLTYPE "SLICE_94") - (INSTANCE SLICE_94) + (CELLTYPE "SLICE_98") + (INSTANCE SLICE_98) (DELAY (ABSOLUTE (IOPATH D1 F1 (301:336:371)(301:336:371)) (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) (IOPATH D0 F0 (301:336:371)(301:336:371)) (IOPATH C0 F0 (301:336:371)(301:336:371)) - (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) ) ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) - (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (CELL + (CELLTYPE "SLICE_99") + (INSTANCE SLICE_99) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_100") + (INSTANCE SLICE_100) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_101") + (INSTANCE SLICE_101) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) ) (TIMINGCHECK (WIDTH (posedge CLK) (1000:1000:1000)) (WIDTH (negedge CLK) (1000:1000:1000)) ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) ) (CELL (CELLTYPE "RD_0_") @@ -2284,11 +2388,10 @@ (DELAY (ABSOLUTE (INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (545:606:667)(545:606:667)) - (INTERCONNECT SLICE_0/Q1 SLICE_72/D0 (1405:1526:1647)(1405:1526:1647)) - (INTERCONNECT SLICE_0/Q1 SLICE_84/C0 (754:836:918)(754:836:918)) + (INTERCONNECT SLICE_0/Q1 SLICE_69/D0 (963:1075:1187)(963:1075:1187)) + (INTERCONNECT SLICE_0/Q1 SLICE_89/C1 (1157:1268:1379)(1157:1268:1379)) (INTERCONNECT SLICE_0/Q0 SLICE_0/A0 (530:591:652)(530:591:652)) - (INTERCONNECT SLICE_0/Q0 SLICE_68/C1 (743:826:909)(743:826:909)) - (INTERCONNECT SLICE_0/Q0 SLICE_69/C1 (743:826:909)(743:826:909)) + (INTERCONNECT SLICE_0/Q0 SLICE_94/C0 (1142:1253:1364)(1142:1253:1364)) (INTERCONNECT RCLK_I/PADDI SLICE_0/CLK (732:1078:1425)(732:1078:1425)) (INTERCONNECT RCLK_I/PADDI SLICE_1/CLK (732:1078:1425)(732:1078:1425)) (INTERCONNECT RCLK_I/PADDI SLICE_2/CLK (732:1078:1425)(732:1078:1425)) @@ -2298,12 +2401,12 @@ (INTERCONNECT RCLK_I/PADDI SLICE_6/CLK (732:1078:1425)(732:1078:1425)) (INTERCONNECT RCLK_I/PADDI SLICE_7/CLK (732:1078:1425)(732:1078:1425)) (INTERCONNECT RCLK_I/PADDI SLICE_8/CLK (732:1078:1425)(732:1078:1425)) - (INTERCONNECT RCLK_I/PADDI SLICE_19/CLK (732:1078:1425)(732:1078:1425)) (INTERCONNECT RCLK_I/PADDI SLICE_29/CLK (732:1078:1425)(732:1078:1425)) (INTERCONNECT RCLK_I/PADDI SLICE_30/CLK (732:1078:1425)(732:1078:1425)) (INTERCONNECT RCLK_I/PADDI SLICE_31/CLK (732:1078:1425)(732:1078:1425)) (INTERCONNECT RCLK_I/PADDI SLICE_32/CLK (732:1078:1425)(732:1078:1425)) (INTERCONNECT RCLK_I/PADDI SLICE_33/CLK (732:1078:1425)(732:1078:1425)) + (INTERCONNECT RCLK_I/PADDI SLICE_38/CLK (732:1078:1425)(732:1078:1425)) (INTERCONNECT RCLK_I/PADDI SLICE_41/CLK (732:1078:1425)(732:1078:1425)) (INTERCONNECT RCLK_I/PADDI SLICE_42/CLK (732:1078:1425)(732:1078:1425)) (INTERCONNECT RCLK_I/PADDI SLICE_43/CLK (732:1078:1425)(732:1078:1425)) @@ -2318,94 +2421,87 @@ (INTERCONNECT RCLK_I/PADDI SLICE_62/CLK (732:1078:1425)(732:1078:1425)) (INTERCONNECT RCLK_I/PADDI SLICE_63/CLK (732:1078:1425)(732:1078:1425)) (INTERCONNECT RCLK_I/PADDI SLICE_64/CLK (732:1078:1425)(732:1078:1425)) - (INTERCONNECT RCLK_I/PADDI SLICE_75/CLK (732:1078:1425)(732:1078:1425)) - (INTERCONNECT RCLK_I/PADDI SLICE_82/CLK (732:1078:1425)(732:1078:1425)) - (INTERCONNECT RCLK_I/PADDI SLICE_94/CLK (732:1078:1425)(732:1078:1425)) + (INTERCONNECT RCLK_I/PADDI SLICE_68/CLK (732:1078:1425)(732:1078:1425)) + (INTERCONNECT RCLK_I/PADDI SLICE_74/CLK (732:1078:1425)(732:1078:1425)) + (INTERCONNECT RCLK_I/PADDI SLICE_95/CLK (732:1078:1425)(732:1078:1425)) (INTERCONNECT SLICE_0/FCO SLICE_8/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q1 SLICE_1/A1 (530:591:652)(530:591:652)) - (INTERCONNECT SLICE_1/Q1 SLICE_81/C1 (743:826:909)(743:826:909)) - (INTERCONNECT SLICE_1/Q1 SLICE_81/C0 (743:826:909)(743:826:909)) + (INTERCONNECT SLICE_1/Q1 SLICE_1/A1 (545:606:667)(545:606:667)) + (INTERCONNECT SLICE_1/Q1 SLICE_80/C1 (696:773:850)(696:773:850)) + (INTERCONNECT SLICE_1/Q1 SLICE_86/D1 (541:599:657)(541:599:657)) (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (545:606:667)(545:606:667)) - (INTERCONNECT SLICE_1/Q0 SLICE_66/B0 (917:1024:1131)(917:1024:1131)) - (INTERCONNECT SLICE_1/Q0 SLICE_72/C1 (750:837:924)(750:837:924)) - (INTERCONNECT SLICE_1/Q0 SLICE_74/D0 (602:670:739)(602:670:739)) + (INTERCONNECT SLICE_1/Q0 SLICE_69/D1 (595:663:731)(595:663:731)) + (INTERCONNECT SLICE_1/Q0 SLICE_86/C0 (696:773:850)(696:773:850)) (INTERCONNECT SLICE_2/FCO SLICE_1/FCI (0:0:0)(0:0:0)) (INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (530:591:652)(530:591:652)) - (INTERCONNECT SLICE_2/Q1 SLICE_81/B1 (1309:1440:1571)(1309:1440:1571)) - (INTERCONNECT SLICE_2/Q1 SLICE_81/B0 (1309:1440:1571)(1309:1440:1571)) + (INTERCONNECT SLICE_2/Q1 SLICE_86/B1 (902:1009:1116)(902:1009:1116)) + (INTERCONNECT SLICE_2/Q1 SLICE_86/B0 (902:1009:1116)(902:1009:1116)) (INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (545:606:667)(545:606:667)) - (INTERCONNECT SLICE_2/Q0 SLICE_74/D1 (599:662:725)(599:662:725)) - (INTERCONNECT SLICE_2/Q0 SLICE_81/D1 (1002:1094:1186)(1002:1094:1186)) + (INTERCONNECT SLICE_2/Q0 SLICE_86/C1 (750:837:924)(750:837:924)) + (INTERCONNECT SLICE_2/Q0 SLICE_86/D0 (599:662:725)(599:662:725)) (INTERCONNECT SLICE_3/FCO SLICE_2/FCI (0:0:0)(0:0:0)) (INTERCONNECT SLICE_3/Q1 SLICE_3/A1 (530:591:652)(530:591:652)) - (INTERCONNECT SLICE_3/Q1 SLICE_81/A1 (1263:1387:1511)(1263:1387:1511)) - (INTERCONNECT SLICE_3/Q1 SLICE_81/A0 (1263:1387:1511)(1263:1387:1511)) - (INTERCONNECT SLICE_3/Q0 SLICE_3/A0 (545:606:667)(545:606:667)) - (INTERCONNECT SLICE_3/Q0 SLICE_72/A1 (1271:1394:1518)(1271:1394:1518)) - (INTERCONNECT SLICE_3/Q0 SLICE_81/D0 (963:1075:1187)(963:1075:1187)) + (INTERCONNECT SLICE_3/Q1 SLICE_67/A0 (862:958:1054)(862:958:1054)) + (INTERCONNECT SLICE_3/Q1 SLICE_69/B1 (1197:1334:1472)(1197:1334:1472)) + (INTERCONNECT SLICE_3/Q1 SLICE_80/A0 (862:958:1054)(862:958:1054)) + (INTERCONNECT SLICE_3/Q0 SLICE_3/A0 (530:591:652)(530:591:652)) + (INTERCONNECT SLICE_3/Q0 SLICE_86/A1 (857:952:1048)(857:952:1048)) + (INTERCONNECT SLICE_3/Q0 SLICE_86/A0 (857:952:1048)(857:952:1048)) (INTERCONNECT SLICE_4/FCO SLICE_3/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/Q1 SLICE_4/A1 (545:606:667)(545:606:667)) - (INTERCONNECT SLICE_4/Q1 SLICE_64/B1 (1823:1986:2149)(1823:1986:2149)) - (INTERCONNECT SLICE_4/Q1 SLICE_72/B0 (1823:1986:2149)(1823:1986:2149)) - (INTERCONNECT SLICE_4/Q1 SLICE_74/B1 (923:1026:1129)(923:1026:1129)) - (INTERCONNECT SLICE_4/Q1 SLICE_84/B1 (923:1026:1129)(923:1026:1129)) - (INTERCONNECT SLICE_4/Q1 SLICE_87/B0 (923:1026:1129)(923:1026:1129)) - (INTERCONNECT SLICE_4/Q0 SLICE_4/A0 (530:591:652)(530:591:652)) - (INTERCONNECT SLICE_4/Q0 SLICE_64/D1 (1404:1527:1650)(1404:1527:1650)) - (INTERCONNECT SLICE_4/Q0 SLICE_74/B0 (913:1016:1120)(913:1016:1120)) - (INTERCONNECT SLICE_4/Q0 SLICE_84/C1 (1560:1708:1856)(1560:1708:1856)) - (INTERCONNECT SLICE_4/Q0 SLICE_84/B0 (913:1016:1120)(913:1016:1120)) + (INTERCONNECT SLICE_4/Q1 SLICE_4/A1 (560:621:682)(560:621:682)) + (INTERCONNECT SLICE_4/Q1 SLICE_56/C1 (1699:1850:2002)(1699:1850:2002)) + (INTERCONNECT SLICE_4/Q1 SLICE_64/D1 (1429:1551:1674)(1429:1551:1674)) + (INTERCONNECT SLICE_4/Q1 SLICE_69/A0 (1181:1311:1442)(1181:1311:1442)) + (INTERCONNECT SLICE_4/Q1 SLICE_80/B1 (938:1041:1144)(938:1041:1144)) + (INTERCONNECT SLICE_4/Q1 SLICE_94/D1 (614:677:740)(614:677:740)) + (INTERCONNECT SLICE_4/Q0 SLICE_4/A0 (545:606:667)(545:606:667)) + (INTERCONNECT SLICE_4/Q0 SLICE_64/C1 (1973:2149:2326)(1973:2149:2326)) + (INTERCONNECT SLICE_4/Q0 SLICE_80/B0 (923:1026:1129)(923:1026:1129)) + (INTERCONNECT SLICE_4/Q0 SLICE_89/B1 (1729:1890:2051)(1729:1890:2051)) + (INTERCONNECT SLICE_4/Q0 SLICE_94/A1 (864:963:1063)(864:963:1063)) (INTERCONNECT SLICE_5/FCO SLICE_4/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_5/Q1 SLICE_5/A1 (545:606:667)(545:606:667)) - (INTERCONNECT SLICE_5/Q1 SLICE_56/C0 (2087:2267:2448)(2087:2267:2448)) - (INTERCONNECT SLICE_5/Q1 SLICE_87/C0 (754:836:918)(754:836:918)) - (INTERCONNECT SLICE_5/Q0 SLICE_5/A0 (530:591:652)(530:591:652)) - (INTERCONNECT SLICE_5/Q0 SLICE_58/C1 (1149:1260:1372)(1149:1260:1372)) - (INTERCONNECT SLICE_5/Q0 SLICE_84/D1 (1397:1518:1640)(1397:1518:1640)) + (INTERCONNECT SLICE_5/Q1 SLICE_5/A1 (530:591:652)(530:591:652)) + (INTERCONNECT SLICE_5/Q1 SLICE_89/A1 (857:952:1048)(857:952:1048)) + (INTERCONNECT SLICE_5/Q1 SLICE_89/A0 (857:952:1048)(857:952:1048)) + (INTERCONNECT SLICE_5/Q0 SLICE_5/A0 (545:606:667)(545:606:667)) + (INTERCONNECT SLICE_5/Q0 SLICE_58/B1 (1409:1541:1674)(1409:1541:1674)) + (INTERCONNECT SLICE_5/Q0 SLICE_94/C1 (754:836:918)(754:836:918)) (INTERCONNECT SLICE_6/FCO SLICE_5/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_6/Q1 SLICE_6/A1 (545:606:667)(545:606:667)) - (INTERCONNECT SLICE_6/Q1 SLICE_56/A0 (2201:2394:2587)(2201:2394:2587)) - (INTERCONNECT SLICE_6/Q1 SLICE_84/D0 (599:662:725)(599:662:725)) + (INTERCONNECT SLICE_6/Q1 SLICE_6/A1 (530:591:652)(530:591:652)) + (INTERCONNECT SLICE_6/Q1 SLICE_89/D1 (994:1086:1179)(994:1086:1179)) + (INTERCONNECT SLICE_6/Q1 SLICE_89/D0 (994:1086:1179)(994:1086:1179)) (INTERCONNECT SLICE_6/Q0 SLICE_6/A0 (530:591:652)(530:591:652)) - (INTERCONNECT SLICE_6/Q0 SLICE_84/A1 (1225:1371:1517)(1225:1371:1517)) - (INTERCONNECT SLICE_6/Q0 SLICE_84/A0 (1225:1371:1517)(1225:1371:1517)) + (INTERCONNECT SLICE_6/Q0 SLICE_94/B1 (1309:1440:1571)(1309:1440:1571)) + (INTERCONNECT SLICE_6/Q0 SLICE_94/B0 (1309:1440:1571)(1309:1440:1571)) (INTERCONNECT SLICE_7/FCO SLICE_6/FCI (0:0:0)(0:0:0)) (INTERCONNECT SLICE_7/Q1 SLICE_7/A1 (530:591:652)(530:591:652)) - (INTERCONNECT SLICE_7/Q1 SLICE_56/D0 (1803:1960:2118)(1803:1960:2118)) - (INTERCONNECT SLICE_7/Q1 SLICE_68/A1 (862:958:1054)(862:958:1054)) - (INTERCONNECT SLICE_7/Q1 SLICE_69/A1 (862:958:1054)(862:958:1054)) + (INTERCONNECT SLICE_7/Q1 SLICE_71/C1 (1153:1265:1378)(1153:1265:1378)) + (INTERCONNECT SLICE_7/Q1 SLICE_72/A1 (1267:1392:1517)(1267:1392:1517)) + (INTERCONNECT SLICE_7/Q1 SLICE_89/C0 (1146:1258:1370)(1146:1258:1370)) (INTERCONNECT SLICE_7/Q0 SLICE_7/A0 (545:606:667)(545:606:667)) - (INTERCONNECT SLICE_7/Q0 SLICE_72/A0 (1271:1394:1518)(1271:1394:1518)) - (INTERCONNECT SLICE_7/Q0 SLICE_87/A0 (1271:1394:1518)(1271:1394:1518)) + (INTERCONNECT SLICE_7/Q0 SLICE_56/D1 (1841:2006:2172)(1841:2006:2172)) + (INTERCONNECT SLICE_7/Q0 SLICE_69/C0 (1157:1268:1379)(1157:1268:1379)) (INTERCONNECT SLICE_8/FCO SLICE_7/FCI (0:0:0)(0:0:0)) (INTERCONNECT SLICE_8/Q1 SLICE_8/A1 (530:591:652)(530:591:652)) - (INTERCONNECT SLICE_8/Q1 SLICE_68/D1 (876:974:1072)(876:974:1072)) - (INTERCONNECT SLICE_8/Q1 SLICE_69/D1 (876:974:1072)(876:974:1072)) + (INTERCONNECT SLICE_8/Q1 SLICE_94/A0 (1217:1360:1504)(1217:1360:1504)) (INTERCONNECT SLICE_8/Q0 SLICE_8/A0 (530:591:652)(530:591:652)) - (INTERCONNECT SLICE_8/Q0 SLICE_68/B1 (903:1005:1108)(903:1005:1108)) - (INTERCONNECT SLICE_8/Q0 SLICE_69/B1 (903:1005:1108)(903:1005:1108)) - (INTERCONNECT SLICE_78/F0 SLICE_9/D1 (932:1044:1156)(932:1044:1156)) - (INTERCONNECT SLICE_70/F1 SLICE_9/C1 (769:851:933)(769:851:933)) - (INTERCONNECT SLICE_70/F1 SLICE_14/C1 (778:861:945)(778:861:945)) - (INTERCONNECT SLICE_70/F1 SLICE_14/C0 (778:861:945)(778:861:945)) - (INTERCONNECT SLICE_70/F1 SLICE_67/A0 (1295:1420:1545)(1295:1420:1545)) - (INTERCONNECT SLICE_70/F1 SLICE_70/B0 (606:674:742)(606:674:742)) - (INTERCONNECT SLICE_70/F1 SLICE_90/C1 (769:851:933)(769:851:933)) - (INTERCONNECT SLICE_85/F1 SLICE_9/B1 (2100:2300:2500)(2100:2300:2500)) - (INTERCONNECT MAin\[0\]_I/PADDI SLICE_9/A1 (1802:1995:2189)(1802:1995:2189)) - (INTERCONNECT MAin\[0\]_I/PADDI SLICE_66/M0 (1606:1757:1909)(1606:1757:1909)) - (INTERCONNECT MAin\[0\]_I/PADDI SLICE_67/C0 (2131:2353:2575)(2131:2353:2575)) - (INTERCONNECT MAin\[0\]_I/PADDI SLICE_76/D0 (2379:2611:2843)(2379:2611:2843)) - (INTERCONNECT MAin\[0\]_I/PADDI SLICE_90/B1 (1395:1576:1757)(1395:1576:1757)) - (INTERCONNECT MAin\[0\]_I/PADDI SLICE_90/B0 (1395:1576:1757)(1395:1576:1757)) - (INTERCONNECT SLICE_9/Q0 SLICE_9/D0 (517:575:634)(517:575:634)) - (INTERCONNECT SLICE_9/Q0 SLICE_20/A1 (786:876:966)(786:876:966)) - (INTERCONNECT SLICE_70/F0 SLICE_9/C0 (723:805:887)(723:805:887)) - (INTERCONNECT SLICE_9/F1 SLICE_9/B0 (576:644:712)(576:644:712)) - (INTERCONNECT SLICE_9/F1 SLICE_20/D0 (526:584:642)(526:584:642)) - (INTERCONNECT SLICE_14/F1 SLICE_9/A0 (1263:1387:1511)(1263:1387:1511)) - (INTERCONNECT SLICE_14/F1 SLICE_14/D0 (526:584:642)(526:584:642)) - (INTERCONNECT SLICE_14/F1 SLICE_20/M0 (1301:1429:1558)(1301:1429:1558)) + (INTERCONNECT SLICE_8/Q0 SLICE_94/D0 (987:1079:1171)(987:1079:1171)) + (INTERCONNECT SLICE_77/F0 SLICE_9/C1 (748:831:915)(748:831:915)) + (INTERCONNECT SLICE_77/F0 SLICE_14/C0 (748:831:915)(748:831:915)) + (INTERCONNECT SLICE_77/F0 SLICE_70/A0 (1217:1360:1504)(1217:1360:1504)) + (INTERCONNECT SLICE_77/F0 SLICE_74/C0 (748:831:915)(748:831:915)) + (INTERCONNECT SLICE_76/F0 SLICE_9/B1 (902:1006:1110)(902:1006:1110)) + (INTERCONNECT SLICE_76/F0 SLICE_14/B0 (902:1006:1110)(902:1006:1110)) + (INTERCONNECT SLICE_76/F0 SLICE_20/B1 (902:1006:1110)(902:1006:1110)) + (INTERCONNECT SLICE_76/F0 SLICE_70/B0 (1708:1870:2032)(1708:1870:2032)) + (INTERCONNECT SLICE_76/F0 SLICE_75/B0 (902:1006:1110)(902:1006:1110)) + (INTERCONNECT SLICE_74/F0 SLICE_9/D0 (580:648:716)(580:648:716)) + (INTERCONNECT SLICE_74/F0 SLICE_20/C0 (735:822:909)(735:822:909)) + (INTERCONNECT SLICE_75/F0 SLICE_9/C0 (696:773:850)(696:773:850)) + (INTERCONNECT SLICE_75/F0 SLICE_14/C1 (431:479:528)(431:479:528)) + (INTERCONNECT SLICE_75/F0 SLICE_14/D0 (276:305:335)(276:305:335)) + (INTERCONNECT SLICE_9/F1 SLICE_9/B0 (825:921:1018)(825:921:1018)) + (INTERCONNECT SLICE_9/Q0 SLICE_9/A0 (530:591:652)(530:591:652)) + (INTERCONNECT SLICE_9/Q0 SLICE_20/D1 (526:584:642)(526:584:642)) (INTERCONNECT SLICE_9/F0 SLICE_9/DI0 (0:0:0)(0:0:0)) (INTERCONNECT PHI2_I/PADDI SLICE_9/CLK (2497:3089:3682)(2497:3089:3682)) (INTERCONNECT PHI2_I/PADDI SLICE_14/CLK (2497:3089:3682)(2497:3089:3682)) @@ -2416,499 +2512,555 @@ (INTERCONNECT PHI2_I/PADDI SLICE_39/CLK (2497:3089:3682)(2497:3089:3682)) (INTERCONNECT PHI2_I/PADDI SLICE_42/M1 (2017:2199:2381)(2017:2199:2381)) (INTERCONNECT PHI2_I/PADDI SLICE_57/CLK (2497:3089:3682)(2497:3089:3682)) - (INTERCONNECT PHI2_I/PADDI SLICE_70/CLK (2497:3089:3682)(2497:3089:3682)) - (INTERCONNECT PHI2_I/PADDI SLICE_71/CLK (2497:3089:3682)(2497:3089:3682)) - (INTERCONNECT PHI2_I/PADDI SLICE_73/CLK (2497:3089:3682)(2497:3089:3682)) - (INTERCONNECT PHI2_I/PADDI SLICE_74/CLK (2497:3089:3682)(2497:3089:3682)) + (INTERCONNECT PHI2_I/PADDI SLICE_75/CLK (2497:3089:3682)(2497:3089:3682)) (INTERCONNECT PHI2_I/PADDI SLICE_76/CLK (2497:3089:3682)(2497:3089:3682)) - (INTERCONNECT PHI2_I/PADDI SLICE_77/CLK (2497:3089:3682)(2497:3089:3682)) - (INTERCONNECT SLICE_77/F0 SLICE_14/B1 (883:984:1086)(883:984:1086)) - (INTERCONNECT SLICE_76/F0 SLICE_14/A1 (837:931:1026)(837:931:1026)) - (INTERCONNECT MAin\[1\]_I/PADDI SLICE_14/B0 (1984:2189:2395)(1984:2189:2395)) - (INTERCONNECT MAin\[1\]_I/PADDI SLICE_66/M1 (1925:2114:2304)(1925:2114:2304)) - (INTERCONNECT MAin\[1\]_I/PADDI SLICE_67/D0 (1636:1793:1950)(1636:1793:1950)) - (INTERCONNECT MAin\[1\]_I/PADDI SLICE_70/C0 (2423:2682:2941)(2423:2682:2941)) - (INTERCONNECT MAin\[1\]_I/PADDI SLICE_77/D0 (2046:2232:2419)(2046:2232:2419)) - (INTERCONNECT MAin\[1\]_I/PADDI SLICE_78/D0 (1522:1684:1847)(1522:1684:1847)) - (INTERCONNECT MAin\[1\]_I/PADDI SLICE_90/A1 (2718:2965:3212)(2718:2965:3212)) - (INTERCONNECT MAin\[1\]_I/PADDI SLICE_91/B0 (2379:2611:2843)(2379:2611:2843)) + (INTERCONNECT PHI2_I/PADDI SLICE_79/CLK (2497:3089:3682)(2497:3089:3682)) + (INTERCONNECT PHI2_I/PADDI SLICE_85/CLK (2497:3089:3682)(2497:3089:3682)) + (INTERCONNECT PHI2_I/PADDI SLICE_88/CLK (2497:3089:3682)(2497:3089:3682)) + (INTERCONNECT PHI2_I/PADDI SLICE_93/CLK (2497:3089:3682)(2497:3089:3682)) + (INTERCONNECT SLICE_14/Q0 SLICE_14/D1 (526:584:642)(526:584:642)) (INTERCONNECT SLICE_14/Q0 SLICE_14/A0 (530:591:652)(530:591:652)) - (INTERCONNECT SLICE_14/Q0 SLICE_20/C0 (1431:1576:1722)(1431:1576:1722)) + (INTERCONNECT SLICE_70/F0 SLICE_14/B1 (883:984:1086)(883:984:1086)) + (INTERCONNECT SLICE_78/F0 SLICE_14/A1 (837:931:1026)(837:931:1026)) (INTERCONNECT SLICE_14/F0 SLICE_14/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_19/Q0 SLICE_19/D1 (571:629:687)(571:629:687)) - (INTERCONNECT SLICE_19/Q0 SLICE_19/A0 (575:636:697)(575:636:697)) - (INTERCONNECT SLICE_19/Q0 SLICE_41/D1 (632:700:769)(632:700:769)) - (INTERCONNECT SLICE_19/Q0 SLICE_50/C1 (808:893:978)(808:893:978)) - (INTERCONNECT SLICE_19/Q0 SLICE_50/C0 (808:893:978)(808:893:978)) - (INTERCONNECT SLICE_19/Q0 SLICE_60/C1 (1211:1325:1439)(1211:1325:1439)) - (INTERCONNECT SLICE_19/Q0 SLICE_63/B0 (968:1072:1177)(968:1072:1177)) - (INTERCONNECT SLICE_19/Q0 nRWE_RNO_1\/SLICE_65/B1 (1236:1372:1509)(1236:1372:1509)) - (INTERCONNECT SLICE_19/Q0 nRWE_RNO_1\/SLICE_65/B0 (1236:1372:1509)(1236:1372:1509)) - (INTERCONNECT SLICE_19/Q0 SLICE_73/B1 (947:1054:1161)(947:1054:1161)) - (INTERCONNECT SLICE_19/Q0 SLICE_79/D0 (653:719:785)(653:719:785)) - (INTERCONNECT SLICE_19/Q0 SLICE_80/A0 (922:1019:1117)(922:1019:1117)) - (INTERCONNECT SLICE_50/Q0 SLICE_19/C1 (788:872:957)(788:872:957)) - (INTERCONNECT SLICE_50/Q0 SLICE_19/C0 (788:872:957)(788:872:957)) - (INTERCONNECT SLICE_50/Q0 SLICE_41/A1 (1312:1438:1565)(1312:1438:1565)) - (INTERCONNECT SLICE_50/Q0 SLICE_50/A1 (839:930:1021)(839:930:1021)) - (INTERCONNECT SLICE_50/Q0 SLICE_50/A0 (560:621:682)(560:621:682)) - (INTERCONNECT SLICE_50/Q0 SLICE_59/C1 (1839:2035:2231)(1839:2035:2231)) - (INTERCONNECT SLICE_50/Q0 SLICE_59/B0 (1710:1891:2072)(1710:1891:2072)) - (INTERCONNECT SLICE_50/Q0 SLICE_63/A0 (839:930:1021)(839:930:1021)) - (INTERCONNECT SLICE_50/Q0 nRWE_RNO_1\/SLICE_65/A1 (1191:1322:1454)(1191:1322:1454)) - (INTERCONNECT SLICE_50/Q0 nRWE_RNO_1\/SLICE_65/D0 (633:698:764)(633:698:764)) - (INTERCONNECT SLICE_50/Q0 SLICE_73/D1 (1332:1461:1591)(1332:1461:1591)) - (INTERCONNECT SLICE_50/Q0 SLICE_79/A0 (839:930:1021)(839:930:1021)) - (INTERCONNECT SLICE_50/Q0 SLICE_94/C0 (2356:2575:2795)(2356:2575:2795)) - (INTERCONNECT SLICE_31/Q0 SLICE_19/B1 (863:960:1057)(863:960:1057)) - (INTERCONNECT SLICE_31/Q0 SLICE_31/A1 (810:899:989)(810:899:989)) - (INTERCONNECT SLICE_31/Q0 SLICE_31/C0 (696:773:850)(696:773:850)) - (INTERCONNECT SLICE_31/Q0 SLICE_83/B1 (863:960:1057)(863:960:1057)) - (INTERCONNECT SLICE_51/Q1 SLICE_19/A1 (1282:1411:1540)(1282:1411:1540)) - (INTERCONNECT SLICE_51/Q1 SLICE_19/LSR (1320:1453:1587)(1320:1453:1587)) - (INTERCONNECT SLICE_51/Q1 SLICE_42/A1 (1688:1854:2020)(1688:1854:2020)) - (INTERCONNECT SLICE_51/Q1 SLICE_42/A0 (1688:1854:2020)(1688:1854:2020)) - (INTERCONNECT SLICE_51/Q1 SLICE_43/B1 (1328:1464:1600)(1328:1464:1600)) - (INTERCONNECT SLICE_51/Q1 SLICE_50/LSR (1320:1453:1587)(1320:1453:1587)) - (INTERCONNECT SLICE_51/Q1 SLICE_52/M1 (889:990:1091)(889:990:1091)) - (INTERCONNECT SLICE_51/Q1 SLICE_61/B1 (1726:1896:2067)(1726:1896:2067)) - (INTERCONNECT SLICE_51/Q1 SLICE_62/A1 (2115:2317:2519)(2115:2317:2519)) - (INTERCONNECT SLICE_51/Q1 nRWE_RNO_1\/SLICE_65/D1 (582:647:712)(582:647:712)) - (INTERCONNECT SLICE_51/Q1 SLICE_73/C1 (1571:1716:1862)(1571:1716:1862)) - (INTERCONNECT SLICE_19/F0 SLICE_19/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_19/F1 SLICE_43/B0 (576:644:712)(576:644:712)) - (INTERCONNECT SLICE_19/F1 SLICE_44/B1 (1394:1526:1659)(1394:1526:1659)) - (INTERCONNECT SLICE_20/Q0 SLICE_20/D1 (541:599:657)(541:599:657)) - (INTERCONNECT SLICE_20/Q0 SLICE_20/A0 (545:606:667)(545:606:667)) - (INTERCONNECT SLICE_20/Q0 SLICE_67/B0 (1409:1541:1674)(1409:1541:1674)) - (INTERCONNECT SLICE_90/F1 SLICE_20/B0 (1286:1416:1547)(1286:1416:1547)) - (INTERCONNECT SLICE_20/OFX0 SLICE_20/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT Din\[5\]_I/PADDI SLICE_21/D1 (1673:1834:1995)(1673:1834:1995)) - (INTERCONNECT Din\[5\]_I/PADDI SLICE_55/M1 (2758:3009:3261)(2758:3009:3261)) - (INTERCONNECT Din\[5\]_I/PADDI SLICE_67/D1 (1673:1834:1995)(1673:1834:1995)) - (INTERCONNECT Din\[5\]_I/PADDI SLICE_75/A0 (1511:1671:1831)(1511:1671:1831)) - (INTERCONNECT Din\[5\]_I/PADDI SLICE_76/D1 (1242:1370:1499)(1242:1370:1499)) - (INTERCONNECT Din\[5\]_I/PADDI SLICE_76/M1 (1549:1713:1878)(1549:1713:1878)) - (INTERCONNECT Din\[5\]_I/PADDI SLICE_78/B1 (2391:2619:2848)(2391:2619:2848)) - (INTERCONNECT Din\[5\]_I/PADDI SLICE_82/D1 (1673:1834:1995)(1673:1834:1995)) - (INTERCONNECT Din\[5\]_I/PADDI SLICE_82/D0 (1673:1834:1995)(1673:1834:1995)) - (INTERCONNECT Din\[5\]_I/PADDI SLICE_85/A0 (1876:2059:2243)(1876:2059:2243)) - (INTERCONNECT Din\[3\]_I/PADDI SLICE_21/C1 (1790:1964:2139)(1790:1964:2139)) - (INTERCONNECT Din\[3\]_I/PADDI SLICE_57/C1 (2200:2404:2608)(2200:2404:2608)) - (INTERCONNECT Din\[3\]_I/PADDI SLICE_67/B1 (1930:2123:2316)(1930:2123:2316)) - (INTERCONNECT Din\[3\]_I/PADDI SLICE_71/M1 (2355:2576:2798)(2355:2576:2798)) - (INTERCONNECT Din\[3\]_I/PADDI SLICE_76/A0 (2606:2857:3109)(2606:2857:3109)) - (INTERCONNECT Din\[3\]_I/PADDI SLICE_78/C1 (1790:1964:2139)(1790:1964:2139)) - (INTERCONNECT Din\[3\]_I/PADDI SLICE_82/A1 (1904:2091:2278)(1904:2091:2278)) - (INTERCONNECT Din\[3\]_I/PADDI SLICE_82/A0 (1904:2091:2278)(1904:2091:2278)) - (INTERCONNECT Din\[3\]_I/PADDI SLICE_85/M1 (1922:2112:2303)(1922:2112:2303)) - (INTERCONNECT SLICE_75/F1 SLICE_21/B1 (931:1040:1149)(931:1040:1149)) - (INTERCONNECT SLICE_75/F1 SLICE_26/D1 (616:686:757)(616:686:757)) - (INTERCONNECT SLICE_75/F1 SLICE_67/A1 (864:963:1063)(864:963:1063)) - (INTERCONNECT SLICE_75/F1 SLICE_75/C0 (431:479:528)(431:479:528)) - (INTERCONNECT SLICE_75/F1 SLICE_82/B1 (931:1040:1149)(931:1040:1149)) - (INTERCONNECT SLICE_75/F1 SLICE_82/B0 (931:1040:1149)(931:1040:1149)) - (INTERCONNECT SLICE_21/F1 SLICE_21/D0 (526:584:642)(526:584:642)) - (INTERCONNECT SLICE_21/F1 SLICE_26/A0 (795:884:974)(795:884:974)) - (INTERCONNECT SLICE_33/Q0 SLICE_21/C0 (1644:1786:1929)(1644:1786:1929)) - (INTERCONNECT SLICE_33/Q0 SLICE_33/D1 (526:584:642)(526:584:642)) - (INTERCONNECT SLICE_33/Q0 SLICE_57/B0 (2611:2837:3063)(2611:2837:3063)) - (INTERCONNECT SLICE_75/F0 SLICE_21/B0 (883:984:1086)(883:984:1086)) - (INTERCONNECT SLICE_82/F1 SLICE_21/A0 (779:868:958)(779:868:958)) + (INTERCONNECT SLICE_14/F1 SLICE_20/A0 (779:868:958)(779:868:958)) + (INTERCONNECT SLICE_87/F0 SLICE_20/C1 (727:810:893)(727:810:893)) + (INTERCONNECT SLICE_87/F0 SLICE_75/C0 (727:810:893)(727:810:893)) + (INTERCONNECT SLICE_75/F1 SLICE_20/A1 (786:876:966)(786:876:966)) + (INTERCONNECT SLICE_75/F1 SLICE_75/A0 (786:876:966)(786:876:966)) + (INTERCONNECT SLICE_20/Q0 SLICE_20/D0 (526:584:642)(526:584:642)) + (INTERCONNECT SLICE_20/Q0 SLICE_73/C0 (739:821:903)(739:821:903)) + (INTERCONNECT SLICE_20/F1 SLICE_20/B0 (560:628:696)(560:628:696)) + (INTERCONNECT SLICE_20/F0 SLICE_20/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/F1 SLICE_21/D1 (572:636:700)(572:636:700)) + (INTERCONNECT SLICE_87/F1 SLICE_26/B1 (1694:1860:2027)(1694:1860:2027)) + (INTERCONNECT SLICE_88/F0 SLICE_21/C1 (739:821:903)(739:821:903)) + (INTERCONNECT SLICE_88/F0 SLICE_26/D1 (526:584:642)(526:584:642)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_21/B1 (1930:2123:2316)(1930:2123:2316)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_57/D0 (1969:2172:2375)(1969:2172:2375)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_75/C1 (2230:2444:2658)(2230:2444:2658)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_76/M1 (2414:2654:2895)(2414:2654:2895)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_84/M1 (1922:2112:2303)(1922:2112:2303)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_85/M0 (1679:1846:2013)(1679:1846:2013)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_88/C1 (2527:2778:3029)(2527:2778:3029)) + (INTERCONNECT SLICE_21/Q0 SLICE_21/A1 (795:884:974)(795:884:974)) + (INTERCONNECT SLICE_21/Q0 SLICE_33/D0 (584:647:710)(584:647:710)) + (INTERCONNECT SLICE_33/Q0 SLICE_21/D0 (587:655:724)(587:655:724)) + (INTERCONNECT SLICE_33/Q0 SLICE_33/A1 (795:884:974)(795:884:974)) + (INTERCONNECT SLICE_33/Q0 SLICE_57/A0 (1674:1838:2003)(1674:1838:2003)) + (INTERCONNECT SLICE_21/F1 SLICE_21/C0 (400:448:497)(400:448:497)) + (INTERCONNECT SLICE_85/F0 SLICE_21/B0 (576:644:712)(576:644:712)) + (INTERCONNECT SLICE_85/F0 SLICE_26/A0 (853:947:1042)(853:947:1042)) (INTERCONNECT SLICE_21/F0 SLICE_21/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_67/F0 SLICE_21/CE (573:634:695)(573:634:695)) - (INTERCONNECT SLICE_67/F0 SLICE_26/CE (573:634:695)(573:634:695)) - (INTERCONNECT SLICE_67/F0 SLICE_57/CE (906:1005:1104)(906:1005:1104)) - (INTERCONNECT SLICE_67/F0 SLICE_67/C1 (431:479:528)(431:479:528)) - (INTERCONNECT SLICE_67/F0 SLICE_82/C0 (710:788:867)(710:788:867)) - (INTERCONNECT SLICE_21/Q0 SLICE_33/B0 (1797:1958:2120)(1797:1958:2120)) - (INTERCONNECT SLICE_21/Q0 SLICE_82/C1 (681:758:835)(681:758:835)) - (INTERCONNECT SLICE_22/Q0 SLICE_22/D1 (541:599:657)(541:599:657)) + (INTERCONNECT SLICE_73/F0 SLICE_21/CE (980:1097:1214)(980:1097:1214)) + (INTERCONNECT SLICE_73/F0 SLICE_26/CE (1412:1546:1680)(1412:1546:1680)) + (INTERCONNECT SLICE_73/F0 SLICE_57/CE (980:1097:1214)(980:1097:1214)) + (INTERCONNECT SLICE_73/F0 SLICE_73/A1 (530:591:652)(530:591:652)) + (INTERCONNECT SLICE_73/F0 SLICE_85/C1 (1128:1263:1398)(1128:1263:1398)) + (INTERCONNECT SLICE_41/Q1 SLICE_22/D1 (1087:1183:1280)(1087:1183:1280)) + (INTERCONNECT SLICE_41/Q1 SLICE_43/M1 (544:603:663)(544:603:663)) + (INTERCONNECT SLICE_41/Q1 SLICE_52/C1 (2048:2221:2395)(2048:2221:2395)) + (INTERCONNECT SLICE_43/Q1 SLICE_22/C1 (1229:1343:1458)(1229:1343:1458)) + (INTERCONNECT SLICE_43/Q1 SLICE_52/B1 (1824:1996:2169)(1824:1996:2169)) + (INTERCONNECT SLICE_32/Q0 SLICE_22/B1 (938:1041:1144)(938:1041:1144)) + (INTERCONNECT SLICE_32/Q0 SLICE_32/A1 (825:914:1004)(825:914:1004)) + (INTERCONNECT SLICE_32/Q0 SLICE_32/A0 (560:621:682)(560:621:682)) + (INTERCONNECT SLICE_32/Q0 SLICE_33/A0 (1726:1883:2040)(1726:1883:2040)) + (INTERCONNECT SLICE_32/Q0 SLICE_43/D1 (1478:1613:1748)(1478:1613:1748)) + (INTERCONNECT SLICE_32/Q0 SLICE_43/D0 (1478:1613:1748)(1478:1613:1748)) + (INTERCONNECT SLICE_32/Q0 SLICE_44/B1 (1793:1966:2140)(1793:1966:2140)) + (INTERCONNECT SLICE_32/Q0 SLICE_51/C1 (2022:2196:2370)(2022:2196:2370)) + (INTERCONNECT SLICE_32/Q0 SLICE_52/A1 (1726:1883:2040)(1726:1883:2040)) + (INTERCONNECT SLICE_32/Q0 SLICE_58/C1 (1195:1309:1423)(1195:1309:1423)) + (INTERCONNECT SLICE_32/Q0 SLICE_58/C0 (1195:1309:1423)(1195:1309:1423)) + (INTERCONNECT SLICE_32/Q0 SLICE_64/A1 (2425:2646:2867)(2425:2646:2867)) + (INTERCONNECT SLICE_32/Q0 nRWE_RNO_1\/SLICE_65/B0 (2196:2398:2601)(2196:2398:2601)) + (INTERCONNECT SLICE_32/Q0 SLICE_66/C1 (1633:1787:1941)(1633:1787:1941)) + (INTERCONNECT SLICE_32/Q0 SLICE_67/C1 (773:856:939)(773:856:939)) + (INTERCONNECT SLICE_32/Q0 SLICE_67/C0 (773:856:939)(773:856:939)) + (INTERCONNECT SLICE_32/Q0 SLICE_95/B1 (2196:2398:2601)(2196:2398:2601)) + (INTERCONNECT SLICE_22/Q0 SLICE_22/A1 (810:899:989)(810:899:989)) (INTERCONNECT SLICE_22/Q0 SLICE_22/A0 (545:606:667)(545:606:667)) - (INTERCONNECT SLICE_22/Q0 SLICE_52/A1 (1157:1286:1415)(1157:1286:1415)) - (INTERCONNECT SLICE_43/Q1 SLICE_22/C1 (1016:1133:1251)(1016:1133:1251)) - (INTERCONNECT SLICE_43/Q1 SLICE_52/D1 (861:959:1058)(861:959:1058)) - (INTERCONNECT SLICE_41/Q1 SLICE_22/B1 (1300:1432:1564)(1300:1432:1564)) - (INTERCONNECT SLICE_41/Q1 SLICE_43/M1 (1695:1853:2012)(1695:1853:2012)) - (INTERCONNECT SLICE_41/Q1 SLICE_52/B1 (1703:1864:2025)(1703:1864:2025)) - (INTERCONNECT SLICE_32/Q0 SLICE_22/A1 (887:984:1081)(887:984:1081)) - (INTERCONNECT SLICE_32/Q0 SLICE_32/C1 (710:788:867)(710:788:867)) - (INTERCONNECT SLICE_32/Q0 SLICE_32/A0 (545:606:667)(545:606:667)) - (INTERCONNECT SLICE_32/Q0 SLICE_33/D0 (1042:1139:1236)(1042:1139:1236)) - (INTERCONNECT SLICE_32/Q0 SLICE_43/A1 (1714:1871:2028)(1714:1871:2028)) - (INTERCONNECT SLICE_32/Q0 SLICE_43/A0 (1714:1871:2028)(1714:1871:2028)) - (INTERCONNECT SLICE_32/Q0 SLICE_44/A1 (887:984:1081)(887:984:1081)) - (INTERCONNECT SLICE_32/Q0 SLICE_51/C1 (1197:1313:1429)(1197:1313:1429)) - (INTERCONNECT SLICE_32/Q0 SLICE_52/C1 (1197:1313:1429)(1197:1313:1429)) - (INTERCONNECT SLICE_32/Q0 SLICE_58/A1 (1714:1871:2028)(1714:1871:2028)) - (INTERCONNECT SLICE_32/Q0 SLICE_58/A0 (1714:1871:2028)(1714:1871:2028)) - (INTERCONNECT SLICE_32/Q0 SLICE_64/A1 (1311:1439:1568)(1311:1439:1568)) - (INTERCONNECT SLICE_32/Q0 nRWE_RNO_1\/SLICE_65/A0 (887:984:1081)(887:984:1081)) - (INTERCONNECT SLICE_32/Q0 SLICE_66/C1 (710:788:867)(710:788:867)) - (INTERCONNECT SLICE_32/Q0 SLICE_66/C0 (710:788:867)(710:788:867)) - (INTERCONNECT SLICE_32/Q0 SLICE_73/A1 (1304:1431:1559)(1304:1431:1559)) - (INTERCONNECT SLICE_82/F0 SLICE_22/D0 (1778:1934:2090)(1778:1934:2090)) + (INTERCONNECT SLICE_22/Q0 SLICE_52/D1 (963:1075:1187)(963:1075:1187)) + (INTERCONNECT SLICE_73/F1 SLICE_22/C0 (400:448:497)(400:448:497)) (INTERCONNECT SLICE_22/F0 SLICE_22/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_22/F1 SLICE_68/D0 (975:1068:1161)(975:1068:1161)) - (INTERCONNECT SLICE_22/F1 SLICE_69/B0 (1290:1421:1553)(1290:1421:1553)) - (INTERCONNECT SLICE_78/F1 SLICE_26/C1 (735:822:909)(735:822:909)) - (INTERCONNECT SLICE_78/F1 SLICE_78/B0 (576:644:712)(576:644:712)) - (INTERCONNECT SLICE_26/Q0 SLICE_26/B1 (841:937:1034)(841:937:1034)) - (INTERCONNECT SLICE_26/Q0 SLICE_58/B0 (899:1000:1102)(899:1000:1102)) - (INTERCONNECT SLICE_76/F1 SLICE_26/A1 (1348:1473:1599)(1348:1473:1599)) - (INTERCONNECT SLICE_76/F1 SLICE_76/C0 (416:464:513)(416:464:513)) - (INTERCONNECT SLICE_58/Q0 SLICE_26/D0 (580:648:716)(580:648:716)) - (INTERCONNECT SLICE_58/Q0 SLICE_39/A0 (2063:2250:2438)(2063:2250:2438)) + (INTERCONNECT SLICE_22/F1 SLICE_71/A0 (1658:1822:1987)(1658:1822:1987)) + (INTERCONNECT SLICE_22/F1 SLICE_72/C0 (726:813:901)(726:813:901)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_26/C1 (1377:1522:1668)(1377:1522:1668)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_76/M0 (1921:2109:2298)(1921:2109:2298)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_78/D1 (1222:1348:1475)(1222:1348:1475)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_83/A0 (2304:2520:2737)(2304:2520:2737)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_84/M0 (2342:2563:2784)(2342:2563:2784)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_87/C0 (2179:2380:2581)(2179:2380:2581)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_88/M0 (2434:2646:2858)(2434:2646:2858)) + (INTERCONNECT SLICE_26/Q0 SLICE_26/A1 (786:876:966)(786:876:966)) + (INTERCONNECT SLICE_26/Q0 SLICE_58/A0 (786:876:966)(786:876:966)) + (INTERCONNECT SLICE_58/Q0 SLICE_26/D0 (526:584:642)(526:584:642)) + (INTERCONNECT SLICE_58/Q0 SLICE_39/D0 (1482:1605:1728)(1482:1605:1728)) (INTERCONNECT SLICE_26/F1 SLICE_26/C0 (400:448:497)(400:448:497)) (INTERCONNECT SLICE_26/F0 SLICE_26/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_83/F1 SLICE_29/D1 (1406:1541:1676)(1406:1541:1676)) - (INTERCONNECT SLICE_83/F1 SLICE_59/A1 (2154:2337:2521)(2154:2337:2521)) - (INTERCONNECT SLICE_83/F1 SLICE_61/D0 (1695:1864:2034)(1695:1864:2034)) - (INTERCONNECT SLICE_73/F1 SLICE_29/C1 (1273:1392:1511)(1273:1392:1511)) - (INTERCONNECT SLICE_73/F1 SLICE_29/C0 (1273:1392:1511)(1273:1392:1511)) - (INTERCONNECT SLICE_73/F1 SLICE_59/B1 (1836:2003:2171)(1836:2003:2171)) - (INTERCONNECT SLICE_73/F1 SLICE_61/C0 (1273:1392:1511)(1273:1392:1511)) - (INTERCONNECT SLICE_73/F1 SLICE_73/B0 (576:644:712)(576:644:712)) - (INTERCONNECT SLICE_73/F1 SLICE_94/C1 (1680:1833:1986)(1680:1833:1986)) - (INTERCONNECT SLICE_61/F1 SLICE_29/B1 (841:937:1034)(841:937:1034)) - (INTERCONNECT SLICE_61/F1 SLICE_61/B0 (576:644:712)(576:644:712)) - (INTERCONNECT SLICE_29/Q0 SLICE_29/A1 (832:922:1012)(832:922:1012)) + (INTERCONNECT SLICE_30/Q0 SLICE_29/D1 (924:1022:1121)(924:1022:1121)) + (INTERCONNECT SLICE_30/Q0 SLICE_30/B1 (886:982:1079)(886:982:1079)) + (INTERCONNECT SLICE_30/Q0 SLICE_30/A0 (575:636:697)(575:636:697)) + (INTERCONNECT SLICE_30/Q0 SLICE_31/D0 (571:629:687)(571:629:687)) + (INTERCONNECT SLICE_30/Q0 SLICE_38/C1 (787:874:962)(787:874:962)) + (INTERCONNECT SLICE_30/Q0 SLICE_38/C0 (787:874:962)(787:874:962)) + (INTERCONNECT SLICE_30/Q0 SLICE_92/C1 (1079:1196:1314)(1079:1196:1314)) + (INTERCONNECT SLICE_30/Q0 SLICE_92/C0 (1079:1196:1314)(1079:1196:1314)) + (INTERCONNECT SLICE_29/Q0 SLICE_29/C1 (711:788:865)(711:788:865)) (INTERCONNECT SLICE_29/Q0 SLICE_29/A0 (560:621:682)(560:621:682)) - (INTERCONNECT SLICE_29/Q0 SLICE_30/D1 (623:687:752)(623:687:752)) - (INTERCONNECT SLICE_29/Q0 SLICE_30/D0 (623:687:752)(623:687:752)) - (INTERCONNECT SLICE_29/Q0 SLICE_31/A0 (1302:1427:1553)(1302:1427:1553)) - (INTERCONNECT SLICE_29/Q0 SLICE_42/B1 (1703:1883:2063)(1703:1883:2063)) - (INTERCONNECT SLICE_29/Q0 SLICE_61/A0 (832:922:1012)(832:922:1012)) - (INTERCONNECT SLICE_29/Q0 SLICE_83/D0 (1033:1127:1221)(1033:1127:1221)) - (INTERCONNECT SLICE_29/Q0 SLICE_94/M0 (2098:2304:2511)(2098:2304:2511)) - (INTERCONNECT SLICE_43/Q0 SLICE_29/B0 (1347:1503:1660)(1347:1503:1660)) - (INTERCONNECT SLICE_43/Q0 SLICE_41/B0 (948:1050:1153)(948:1050:1153)) - (INTERCONNECT SLICE_43/Q0 SLICE_43/D1 (578:636:695)(578:636:695)) - (INTERCONNECT SLICE_43/Q0 SLICE_43/D0 (578:636:695)(578:636:695)) - (INTERCONNECT SLICE_43/Q0 SLICE_44/D1 (633:697:761)(633:697:761)) - (INTERCONNECT SLICE_43/Q0 SLICE_50/D1 (632:700:769)(632:700:769)) - (INTERCONNECT SLICE_43/Q0 SLICE_59/D1 (1435:1582:1729)(1435:1582:1729)) - (INTERCONNECT SLICE_43/Q0 SLICE_61/C1 (1476:1647:1819)(1476:1647:1819)) - (INTERCONNECT SLICE_43/Q0 SLICE_62/B1 (2176:2379:2582)(2176:2379:2582)) - (INTERCONNECT SLICE_43/Q0 SLICE_63/C1 (801:890:980)(801:890:980)) - (INTERCONNECT SLICE_43/Q0 SLICE_63/C0 (801:890:980)(801:890:980)) - (INTERCONNECT SLICE_43/Q0 nRWE_RNO_1\/SLICE_65/M0 (640:705:770)(640:705:770)) - (INTERCONNECT SLICE_43/Q0 SLICE_73/A0 (1191:1321:1451)(1191:1321:1451)) - (INTERCONNECT SLICE_43/Q0 SLICE_79/C1 (801:890:980)(801:890:980)) - (INTERCONNECT SLICE_43/Q0 SLICE_94/D1 (2271:2465:2659)(2271:2465:2659)) - (INTERCONNECT SLICE_43/Q0 SLICE_94/D0 (2271:2465:2659)(2271:2465:2659)) + (INTERCONNECT SLICE_29/Q0 SLICE_30/D1 (633:698:764)(633:698:764)) + (INTERCONNECT SLICE_29/Q0 SLICE_30/D0 (633:698:764)(633:698:764)) + (INTERCONNECT SLICE_29/Q0 SLICE_31/A1 (902:999:1096)(902:999:1096)) + (INTERCONNECT SLICE_29/Q0 SLICE_31/A0 (902:999:1096)(902:999:1096)) + (INTERCONNECT SLICE_29/Q0 SLICE_38/D1 (1043:1138:1233)(1043:1138:1233)) + (INTERCONNECT SLICE_29/Q0 SLICE_61/B0 (1761:1923:2086)(1761:1923:2086)) + (INTERCONNECT SLICE_29/Q0 SLICE_92/A0 (1378:1503:1629)(1378:1503:1629)) + (INTERCONNECT SLICE_30/Q1 SLICE_29/B1 (948:1050:1153)(948:1050:1153)) + (INTERCONNECT SLICE_30/Q1 SLICE_30/A1 (575:636:697)(575:636:697)) + (INTERCONNECT SLICE_30/Q1 SLICE_31/C0 (726:803:880)(726:803:880)) + (INTERCONNECT SLICE_30/Q1 SLICE_38/A1 (902:997:1093)(902:997:1093)) + (INTERCONNECT SLICE_30/Q1 SLICE_38/A0 (902:997:1093)(902:997:1093)) + (INTERCONNECT SLICE_30/Q1 SLICE_92/A1 (902:997:1093)(902:997:1093)) + (INTERCONNECT SLICE_30/Q1 SLICE_92/B0 (1439:1571:1704)(1439:1571:1704)) + (INTERCONNECT SLICE_66/F1 SLICE_29/D0 (276:305:335)(276:305:335)) + (INTERCONNECT SLICE_66/F1 SLICE_31/C1 (758:841:924)(758:841:924)) + (INTERCONNECT SLICE_66/F1 SLICE_61/D0 (1416:1538:1661)(1416:1538:1661)) + (INTERCONNECT SLICE_66/F1 SLICE_66/C0 (431:479:528)(431:479:528)) + (INTERCONNECT SLICE_66/F1 SLICE_101/D0 (1416:1538:1661)(1416:1538:1661)) + (INTERCONNECT SLICE_43/Q0 SLICE_29/C0 (2039:2213:2388)(2039:2213:2388)) + (INTERCONNECT SLICE_43/Q0 SLICE_31/D1 (2161:2357:2554)(2161:2357:2554)) + (INTERCONNECT SLICE_43/Q0 SLICE_33/B1 (2999:3256:3514)(2999:3256:3514)) + (INTERCONNECT SLICE_43/Q0 SLICE_41/A0 (854:945:1036)(854:945:1036)) + (INTERCONNECT SLICE_43/Q0 SLICE_42/C1 (1212:1326:1441)(1212:1326:1441)) + (INTERCONNECT SLICE_43/Q0 SLICE_43/C1 (740:818:897)(740:818:897)) + (INTERCONNECT SLICE_43/Q0 SLICE_43/A0 (575:636:697)(575:636:697)) + (INTERCONNECT SLICE_43/Q0 SLICE_44/A1 (902:997:1093)(902:997:1093)) + (INTERCONNECT SLICE_43/Q0 SLICE_50/C1 (733:810:888)(733:810:888)) + (INTERCONNECT SLICE_43/Q0 SLICE_60/C1 (1615:1758:1902)(1615:1758:1902)) + (INTERCONNECT SLICE_43/Q0 SLICE_61/C1 (2437:2647:2858)(2437:2647:2858)) + (INTERCONNECT SLICE_43/Q0 SLICE_62/B1 (2158:2353:2549)(2158:2353:2549)) + (INTERCONNECT SLICE_43/Q0 SLICE_63/D1 (585:644:704)(585:644:704)) + (INTERCONNECT SLICE_43/Q0 SLICE_63/A0 (847:937:1027)(847:937:1027)) + (INTERCONNECT SLICE_43/Q0 nRWE_RNO_1\/SLICE_65/M0 (1781:1943:2105)(1781:1943:2105)) + (INTERCONNECT SLICE_43/Q0 SLICE_66/D0 (2173:2363:2553)(2173:2363:2553)) + (INTERCONNECT SLICE_43/Q0 SLICE_82/A1 (1708:1861:2015)(1708:1861:2015)) + (INTERCONNECT SLICE_43/Q0 SLICE_101/C0 (2437:2647:2858)(2437:2647:2858)) (INTERCONNECT SLICE_29/F0 SLICE_29/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_29/F1 SLICE_60/B0 (560:628:696)(560:628:696)) - (INTERCONNECT SLICE_30/Q1 SLICE_30/C1 (696:773:850)(696:773:850)) - (INTERCONNECT SLICE_30/Q1 SLICE_31/D1 (991:1107:1224)(991:1107:1224)) - (INTERCONNECT SLICE_30/Q1 SLICE_31/D0 (991:1107:1224)(991:1107:1224)) - (INTERCONNECT SLICE_30/Q1 SLICE_42/C1 (1560:1700:1840)(1560:1700:1840)) - (INTERCONNECT SLICE_30/Q1 SLICE_83/C1 (1146:1281:1417)(1146:1281:1417)) - (INTERCONNECT SLICE_30/Q1 SLICE_83/C0 (1146:1281:1417)(1146:1281:1417)) - (INTERCONNECT SLICE_30/Q0 SLICE_30/A1 (825:914:1004)(825:914:1004)) - (INTERCONNECT SLICE_30/Q0 SLICE_30/A0 (560:621:682)(560:621:682)) - (INTERCONNECT SLICE_30/Q0 SLICE_31/B1 (943:1046:1150)(943:1046:1150)) - (INTERCONNECT SLICE_30/Q0 SLICE_31/B0 (943:1046:1150)(943:1046:1150)) - (INTERCONNECT SLICE_30/Q0 SLICE_42/D1 (1109:1203:1297)(1109:1203:1297)) - (INTERCONNECT SLICE_30/Q0 SLICE_83/A1 (897:993:1090)(897:993:1090)) - (INTERCONNECT SLICE_30/Q0 SLICE_83/A0 (897:993:1090)(897:993:1090)) + (INTERCONNECT SLICE_74/Q1 SLICE_29/M1 (1795:1957:2119)(1795:1957:2119)) + (INTERCONNECT SLICE_74/Q1 SLICE_82/D1 (1502:1629:1757)(1502:1629:1757)) + (INTERCONNECT SLICE_74/Q1 SLICE_84/C1 (1657:1803:1950)(1657:1803:1950)) + (INTERCONNECT SLICE_74/Q1 SLICE_84/C0 (1657:1803:1950)(1657:1803:1950)) + (INTERCONNECT SLICE_74/Q1 SLICE_90/B0 (1835:2009:2183)(1835:2009:2183)) + (INTERCONNECT SLICE_29/F1 SLICE_43/C0 (1553:1704:1856)(1553:1704:1856)) + (INTERCONNECT SLICE_29/F1 SLICE_44/D1 (261:290:320)(261:290:320)) + (INTERCONNECT SLICE_29/Q1 SLICE_63/C1 (726:813:901)(726:813:901)) + (INTERCONNECT SLICE_29/Q1 SLICE_82/B1 (1722:1897:2072)(1722:1897:2072)) + (INTERCONNECT SLICE_29/Q1 SLICE_84/A1 (1676:1844:2012)(1676:1844:2012)) + (INTERCONNECT SLICE_29/Q1 SLICE_84/A0 (1676:1844:2012)(1676:1844:2012)) (INTERCONNECT SLICE_30/F1 SLICE_30/DI1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_30/F0 SLICE_30/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_94/F1 SLICE_30/CE (1885:2046:2208)(1885:2046:2208)) - (INTERCONNECT SLICE_94/F1 SLICE_31/CE (2184:2374:2565)(2184:2374:2565)) - (INTERCONNECT SLICE_73/F0 SLICE_31/C1 (723:805:887)(723:805:887)) + (INTERCONNECT SLICE_101/F0 SLICE_30/CE (947:1062:1178)(947:1062:1178)) + (INTERCONNECT SLICE_101/F0 SLICE_31/CE (947:1062:1178)(947:1062:1178)) + (INTERCONNECT SLICE_31/Q0 SLICE_31/B1 (863:960:1057)(863:960:1057)) + (INTERCONNECT SLICE_31/Q0 SLICE_31/B0 (863:960:1057)(863:960:1057)) + (INTERCONNECT SLICE_31/Q0 SLICE_38/B1 (918:1020:1123)(918:1020:1123)) + (INTERCONNECT SLICE_31/Q0 SLICE_92/D1 (1094:1188:1282)(1094:1188:1282)) + (INTERCONNECT SLICE_31/Q0 SLICE_95/A0 (1275:1399:1524)(1275:1399:1524)) (INTERCONNECT SLICE_31/F0 SLICE_31/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_31/F1 SLICE_94/LSR (1908:2070:2233)(1908:2070:2233)) - (INTERCONNECT SLICE_56/F0 SLICE_32/D1 (1374:1495:1616)(1374:1495:1616)) - (INTERCONNECT SLICE_84/F1 SLICE_32/B1 (1172:1308:1444)(1172:1308:1444)) - (INTERCONNECT SLICE_72/F1 SLICE_32/A1 (1239:1383:1527)(1239:1383:1527)) - (INTERCONNECT SLICE_72/F1 SLICE_58/D1 (541:599:657)(541:599:657)) - (INTERCONNECT SLICE_72/F1 SLICE_64/C1 (1575:1727:1879)(1575:1727:1879)) - (INTERCONNECT SLICE_72/F1 SLICE_72/C0 (431:479:528)(431:479:528)) - (INTERCONNECT SLICE_74/F0 SLICE_32/D0 (245:274:304)(245:274:304)) + (INTERCONNECT SLICE_31/F1 SLICE_38/LSR (1389:1522:1656)(1389:1522:1656)) + (INTERCONNECT SLICE_94/F1 SLICE_32/D1 (1260:1386:1513)(1260:1386:1513)) + (INTERCONNECT SLICE_69/F1 SLICE_32/C1 (711:788:865)(711:788:865)) + (INTERCONNECT SLICE_69/F1 SLICE_58/D1 (1017:1109:1201)(1017:1109:1201)) + (INTERCONNECT SLICE_69/F1 SLICE_64/B1 (1332:1462:1593)(1332:1462:1593)) + (INTERCONNECT SLICE_69/F1 SLICE_69/B0 (1424:1556:1689)(1424:1556:1689)) + (INTERCONNECT SLICE_89/F0 SLICE_32/B1 (1575:1740:1905)(1575:1740:1905)) + (INTERCONNECT SLICE_80/F0 SLICE_32/B0 (883:984:1086)(883:984:1086)) (INTERCONNECT SLICE_32/F0 SLICE_32/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_32/F1 SLICE_87/D1 (245:274:304)(245:274:304)) - (INTERCONNECT nCRAS_I/PADDI SLICE_33/C1 (1635:1825:2016)(1635:1825:2016)) - (INTERCONNECT nCRAS_I/PADDI SLICE_44/M1 (1526:1687:1849)(1526:1687:1849)) - (INTERCONNECT nCRAS_I/PADDI SLICE_66/CLK (3109:3772:4435)(3109:3772:4435)) - (INTERCONNECT nCRAS_I/PADDI SLICE_67/CLK (3109:3772:4435)(3109:3772:4435)) - (INTERCONNECT nCRAS_I/PADDI SLICE_72/CLK (3109:3772:4435)(3109:3772:4435)) - (INTERCONNECT nCRAS_I/PADDI SLICE_78/CLK (3109:3772:4435)(3109:3772:4435)) - (INTERCONNECT nCRAS_I/PADDI SLICE_80/CLK (3109:3772:4435)(3109:3772:4435)) - (INTERCONNECT nCRAS_I/PADDI SLICE_81/CLK (3109:3772:4435)(3109:3772:4435)) - (INTERCONNECT nCRAS_I/PADDI SLICE_83/CLK (3109:3772:4435)(3109:3772:4435)) - (INTERCONNECT nCRAS_I/PADDI SLICE_88/CLK (3109:3772:4435)(3109:3772:4435)) - (INTERCONNECT SLICE_78/Q0 SLICE_33/A1 (1758:1913:2068)(1758:1913:2068)) - (INTERCONNECT SLICE_78/Q0 SLICE_41/D0 (1892:2044:2197)(1892:2044:2197)) - (INTERCONNECT SLICE_78/Q0 SLICE_60/D0 (1405:1538:1671)(1405:1538:1671)) - (INTERCONNECT SLICE_78/Q0 SLICE_63/A1 (1634:1807:1981)(1634:1807:1981)) - (INTERCONNECT SLICE_78/Q0 SLICE_79/B0 (1969:2184:2399)(1969:2184:2399)) - (INTERCONNECT UFMSDO_I/PADDI SLICE_33/A0 (1377:1528:1680)(1377:1528:1680)) - (INTERCONNECT UFMSDO_I/PADDI SLICE_58/D0 (2317:2524:2731)(2317:2524:2731)) + (INTERCONNECT SLICE_32/F1 SLICE_55/A0 (1240:1363:1487)(1240:1363:1487)) + (INTERCONNECT SLICE_87/Q0 SLICE_33/D1 (1276:1402:1529)(1276:1402:1529)) + (INTERCONNECT SLICE_87/Q0 SLICE_41/D0 (1417:1553:1690)(1417:1553:1690)) + (INTERCONNECT SLICE_87/Q0 SLICE_59/D1 (1812:1975:2138)(1812:1975:2138)) + (INTERCONNECT SLICE_87/Q0 SLICE_63/A1 (1975:2177:2380)(1975:2177:2380)) + (INTERCONNECT nCRAS_I/PADDI SLICE_33/C1 (1628:1818:2008)(1628:1818:2008)) + (INTERCONNECT nCRAS_I/PADDI SLICE_67/CLK (3102:3764:4427)(3102:3764:4427)) + (INTERCONNECT nCRAS_I/PADDI SLICE_69/CLK (3102:3764:4427)(3102:3764:4427)) + (INTERCONNECT nCRAS_I/PADDI SLICE_73/CLK (3102:3764:4427)(3102:3764:4427)) + (INTERCONNECT nCRAS_I/PADDI SLICE_83/CLK (3102:3764:4427)(3102:3764:4427)) + (INTERCONNECT nCRAS_I/PADDI SLICE_87/CLK (3102:3764:4427)(3102:3764:4427)) + (INTERCONNECT nCRAS_I/PADDI SLICE_89/CLK (3102:3764:4427)(3102:3764:4427)) + (INTERCONNECT nCRAS_I/PADDI SLICE_90/CLK (3102:3764:4427)(3102:3764:4427)) + (INTERCONNECT nCRAS_I/PADDI SLICE_95/M0 (4041:4816:5592)(4041:4816:5592)) + (INTERCONNECT nCRAS_I/PADDI SLICE_101/CLK (3102:3764:4427)(3102:3764:4427)) + (INTERCONNECT UFMSDO_I/PADDI SLICE_33/B0 (1712:1905:2098)(1712:1905:2098)) + (INTERCONNECT UFMSDO_I/PADDI SLICE_58/D0 (1914:2092:2270)(1914:2092:2270)) (INTERCONNECT SLICE_33/F0 SLICE_33/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_69/F0 SLICE_33/CE (1070:1165:1260)(1070:1165:1260)) + (INTERCONNECT SLICE_72/F0 SLICE_33/CE (1278:1406:1534)(1278:1406:1534)) (INTERCONNECT SLICE_33/F1 LED_I/PADDO (646:731:817)(646:731:817)) - (INTERCONNECT SLICE_57/Q0 SLICE_39/D1 (1908:2070:2232)(1908:2070:2232)) - (INTERCONNECT SLICE_57/Q0 SLICE_39/D0 (1908:2070:2232)(1908:2070:2232)) - (INTERCONNECT SLICE_85/F0 SLICE_39/B1 (1792:1955:2118)(1792:1955:2118)) - (INTERCONNECT SLICE_85/F0 SLICE_57/D1 (1477:1601:1726)(1477:1601:1726)) - (INTERCONNECT Din\[6\]_I/PADDI SLICE_39/B0 (2577:2847:3118)(2577:2847:3118)) - (INTERCONNECT Din\[6\]_I/PADDI SLICE_56/M0 (2415:2652:2889)(2415:2652:2889)) - (INTERCONNECT Din\[6\]_I/PADDI SLICE_75/A1 (2528:2792:3057)(2528:2792:3057)) - (INTERCONNECT Din\[6\]_I/PADDI SLICE_77/B0 (2695:2961:3228)(2695:2961:3228)) - (INTERCONNECT Din\[6\]_I/PADDI SLICE_77/M0 (2387:2616:2845)(2387:2616:2845)) - (INTERCONNECT Din\[6\]_I/PADDI SLICE_78/C0 (2520:2764:3008)(2520:2764:3008)) - (INTERCONNECT Din\[6\]_I/PADDI SLICE_85/D0 (1973:2170:2368)(1973:2170:2368)) + (INTERCONNECT SLICE_38/F0 SLICE_38/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_38/Q0 RA\[10\]_I/PADDO (646:731:817)(646:731:817)) + (INTERCONNECT SLICE_38/F1 SLICE_68/A1 (837:931:1026)(837:931:1026)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_39/C1 (2125:2342:2560)(2125:2342:2560)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_39/C0 (2125:2342:2560)(2125:2342:2560)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_56/M0 (2404:2639:2875)(2404:2639:2875)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_74/C1 (2542:2790:3038)(2542:2790:3038)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_75/M0 (3097:3391:3685)(3097:3391:3685)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_83/B1 (3105:3401:3698)(3105:3401:3698)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_87/D1 (2380:2608:2836)(2380:2608:2836)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_87/D0 (2380:2608:2836)(2380:2608:2836)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_39/B1 (2288:2524:2760)(2288:2524:2760)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_56/M1 (2280:2513:2747)(2280:2513:2747)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_75/M1 (1534:1692:1851)(1534:1692:1851)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_83/D1 (1545:1706:1867)(1545:1706:1867)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_87/B1 (2270:2499:2728)(2270:2499:2728)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_87/B0 (2270:2499:2728)(2270:2499:2728)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_88/D1 (1545:1706:1867)(1545:1706:1867)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_39/A1 (2666:2932:3198)(2666:2932:3198)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_55/M0 (2280:2513:2747)(2280:2513:2747)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_74/A1 (2660:2921:3182)(2660:2921:3182)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_75/D1 (2794:3052:3311)(2794:3052:3311)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_83/C1 (2425:2678:2932)(2425:2678:2932)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_87/C1 (2820:3100:3380)(2820:3100:3380)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_93/M0 (3274:3586:3899)(3274:3586:3899)) + (INTERCONNECT SLICE_57/Q0 SLICE_39/B0 (1797:1958:2120)(1797:1958:2120)) + (INTERCONNECT SLICE_57/Q0 SLICE_57/A1 (795:884:974)(795:884:974)) (INTERCONNECT SLICE_39/F0 SLICE_39/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_44/Q0 SLICE_39/LSR (1723:1881:2040)(1723:1881:2040)) + (INTERCONNECT SLICE_44/Q0 SLICE_39/LSR (1409:1541:1674)(1409:1541:1674)) (INTERCONNECT SLICE_44/Q0 SLICE_44/A0 (545:606:667)(545:606:667)) - (INTERCONNECT SLICE_44/Q0 SLICE_66/LSR (910:1010:1110)(910:1010:1110)) - (INTERCONNECT SLICE_44/Q0 SLICE_67/LSR (1730:1889:2048)(1730:1889:2048)) - (INTERCONNECT SLICE_44/Q0 SLICE_72/LSR (1730:1889:2048)(1730:1889:2048)) - (INTERCONNECT SLICE_44/Q0 SLICE_80/LSR (1320:1449:1579)(1320:1449:1579)) - (INTERCONNECT SLICE_44/Q0 SLICE_83/LSR (910:1010:1110)(910:1010:1110)) - (INTERCONNECT SLICE_44/Q0 SLICE_88/LSR (1723:1881:2040)(1723:1881:2040)) + (INTERCONNECT SLICE_44/Q0 SLICE_67/LSR (1569:1707:1845)(1569:1707:1845)) + (INTERCONNECT SLICE_44/Q0 SLICE_69/LSR (1423:1556:1689)(1423:1556:1689)) + (INTERCONNECT SLICE_44/Q0 SLICE_73/LSR (1877:2052:2228)(1877:2052:2228)) + (INTERCONNECT SLICE_44/Q0 SLICE_83/LSR (2280:2484:2689)(2280:2484:2689)) + (INTERCONNECT SLICE_44/Q0 SLICE_89/LSR (1423:1556:1689)(1423:1556:1689)) + (INTERCONNECT SLICE_44/Q0 SLICE_90/LSR (1812:1973:2135)(1812:1973:2135)) (INTERCONNECT SLICE_39/Q0 RA\[11\]_I/PADDO (646:731:817)(646:731:817)) - (INTERCONNECT SLICE_39/F1 SLICE_57/A0 (2170:2363:2556)(2170:2363:2556)) - (INTERCONNECT SLICE_81/Q1 SLICE_41/C1 (2032:2205:2379)(2032:2205:2379)) - (INTERCONNECT SLICE_81/Q1 SLICE_60/B1 (1789:1953:2117)(1789:1953:2117)) - (INTERCONNECT SLICE_75/Q1 SLICE_41/B1 (1295:1427:1559)(1295:1427:1559)) - (INTERCONNECT SLICE_75/Q1 SLICE_60/A1 (2074:2266:2459)(2074:2266:2459)) - (INTERCONNECT SLICE_75/Q1 SLICE_79/B1 (1717:1887:2058)(1717:1887:2058)) - (INTERCONNECT SLICE_75/Q1 SLICE_80/C1 (1557:1708:1859)(1557:1708:1859)) - (INTERCONNECT SLICE_75/Q1 SLICE_82/M0 (884:984:1085)(884:984:1085)) + (INTERCONNECT SLICE_39/F1 SLICE_73/D1 (1506:1641:1776)(1506:1641:1776)) + (INTERCONNECT SLICE_39/F1 SLICE_85/B1 (2646:2887:3128)(2646:2887:3128)) + (INTERCONNECT SLICE_39/F1 SLICE_85/B0 (2646:2887:3128)(2646:2887:3128)) + (INTERCONNECT SLICE_39/F1 SLICE_88/B0 (2646:2887:3128)(2646:2887:3128)) + (INTERCONNECT SLICE_90/F0 SLICE_41/D1 (932:1044:1156)(932:1044:1156)) + (INTERCONNECT SLICE_68/Q0 SLICE_41/C1 (1194:1310:1426)(1194:1310:1426)) + (INTERCONNECT SLICE_68/Q0 SLICE_50/D1 (1039:1136:1233)(1039:1136:1233)) + (INTERCONNECT SLICE_68/Q0 SLICE_50/D0 (1039:1136:1233)(1039:1136:1233)) + (INTERCONNECT SLICE_68/Q0 SLICE_56/C0 (2021:2197:2373)(2021:2197:2373)) + (INTERCONNECT SLICE_68/Q0 SLICE_63/B0 (1354:1489:1625)(1354:1489:1625)) + (INTERCONNECT SLICE_68/Q0 nRWE_RNO_1\/SLICE_65/A1 (1725:1884:2043)(1725:1884:2043)) + (INTERCONNECT SLICE_68/Q0 nRWE_RNO_1\/SLICE_65/A0 (1725:1884:2043)(1725:1884:2043)) + (INTERCONNECT SLICE_68/Q0 SLICE_66/A1 (877:973:1069)(877:973:1069)) + (INTERCONNECT SLICE_68/Q0 SLICE_68/B1 (863:960:1057)(863:960:1057)) + (INTERCONNECT SLICE_68/Q0 SLICE_68/A0 (545:606:667)(545:606:667)) + (INTERCONNECT SLICE_68/Q0 SLICE_82/D0 (2572:2794:3016)(2572:2794:3016)) + (INTERCONNECT SLICE_68/Q0 SLICE_84/B1 (2598:2824:3050)(2598:2824:3050)) + (INTERCONNECT SLICE_68/Q0 SLICE_84/B0 (2598:2824:3050)(2598:2824:3050)) + (INTERCONNECT SLICE_68/Q0 SLICE_90/A1 (1287:1412:1538)(1287:1412:1538)) + (INTERCONNECT SLICE_68/Q0 SLICE_90/A0 (1287:1412:1538)(1287:1412:1538)) + (INTERCONNECT SLICE_68/Q0 SLICE_95/B0 (863:960:1057)(863:960:1057)) + (INTERCONNECT SLICE_101/Q1 SLICE_41/B1 (1985:2179:2374)(1985:2179:2374)) + (INTERCONNECT SLICE_101/Q1 SLICE_84/D1 (2194:2374:2554)(2194:2374:2554)) + (INTERCONNECT SLICE_101/Q1 SLICE_84/D0 (2194:2374:2554)(2194:2374:2554)) + (INTERCONNECT SLICE_50/Q0 SLICE_41/A1 (854:945:1036)(854:945:1036)) + (INTERCONNECT SLICE_50/Q0 SLICE_50/B1 (900:998:1096)(900:998:1096)) + (INTERCONNECT SLICE_50/Q0 SLICE_50/A0 (575:636:697)(575:636:697)) + (INTERCONNECT SLICE_50/Q0 SLICE_59/C1 (1611:1765:1920)(1611:1765:1920)) + (INTERCONNECT SLICE_50/Q0 SLICE_59/B0 (1479:1618:1757)(1479:1618:1757)) + (INTERCONNECT SLICE_50/Q0 SLICE_60/B1 (1771:1945:2119)(1771:1945:2119)) + (INTERCONNECT SLICE_50/Q0 SLICE_63/D0 (585:644:704)(585:644:704)) + (INTERCONNECT SLICE_50/Q0 nRWE_RNO_1\/SLICE_65/C1 (1309:1427:1546)(1309:1427:1546)) + (INTERCONNECT SLICE_50/Q0 nRWE_RNO_1\/SLICE_65/C0 (1309:1427:1546)(1309:1427:1546)) + (INTERCONNECT SLICE_50/Q0 SLICE_66/B1 (947:1054:1161)(947:1054:1161)) + (INTERCONNECT SLICE_50/Q0 SLICE_66/B0 (947:1054:1161)(947:1054:1161)) + (INTERCONNECT SLICE_50/Q0 SLICE_68/D0 (1011:1126:1242)(1011:1126:1242)) + (INTERCONNECT SLICE_50/Q0 SLICE_82/C0 (1301:1417:1533)(1301:1417:1533)) + (INTERCONNECT SLICE_50/Q0 SLICE_90/C1 (1729:1878:2027)(1729:1878:2027)) + (INTERCONNECT SLICE_50/Q0 SLICE_90/C0 (1729:1878:2027)(1729:1878:2027)) + (INTERCONNECT SLICE_50/Q0 SLICE_95/D1 (1011:1126:1242)(1011:1126:1242)) + (INTERCONNECT SLICE_50/Q0 SLICE_95/D0 (1011:1126:1242)(1011:1126:1242)) (INTERCONNECT SLICE_41/F1 SLICE_41/C0 (400:448:497)(400:448:497)) - (INTERCONNECT SLICE_43/F1 SLICE_41/A0 (833:932:1032)(833:932:1032)) + (INTERCONNECT SLICE_43/F1 SLICE_41/B0 (560:628:696)(560:628:696)) (INTERCONNECT SLICE_41/F0 SLICE_41/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_42/Q1 SLICE_41/M1 (1773:1932:2091)(1773:1932:2091)) - (INTERCONNECT SLICE_41/Q0 SLICE_42/B0 (1781:1942:2104)(1781:1942:2104)) - (INTERCONNECT SLICE_44/Q1 SLICE_42/D0 (1398:1530:1663)(1398:1530:1663)) - (INTERCONNECT SLICE_44/Q1 SLICE_51/M1 (1386:1516:1646)(1386:1516:1646)) - (INTERCONNECT SLICE_52/Q1 SLICE_42/C0 (1621:1763:1905)(1621:1763:1905)) - (INTERCONNECT SLICE_42/F0 SLICE_42/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_42/Q0 SLICE_61/A1 (1247:1371:1495)(1247:1371:1495)) - (INTERCONNECT SLICE_42/Q0 nRWE_RNO_1\/SLICE_65/C1 (2228:2432:2636)(2228:2432:2636)) + (INTERCONNECT SLICE_42/Q1 SLICE_41/M1 (1473:1597:1721)(1473:1597:1721)) + (INTERCONNECT SLICE_41/Q0 SLICE_42/B0 (1247:1397:1548)(1247:1397:1548)) + (INTERCONNECT SLICE_95/Q1 SLICE_42/D1 (1048:1143:1239)(1048:1143:1239)) + (INTERCONNECT SLICE_95/Q1 SLICE_42/D0 (1048:1143:1239)(1048:1143:1239)) + (INTERCONNECT SLICE_95/Q1 SLICE_43/A1 (2534:2754:2975)(2534:2754:2975)) + (INTERCONNECT SLICE_95/Q1 SLICE_44/M1 (945:1047:1149)(945:1047:1149)) + (INTERCONNECT SLICE_95/Q1 SLICE_50/LSR (1055:1151:1248)(1055:1151:1248)) + (INTERCONNECT SLICE_95/Q1 SLICE_61/B1 (1332:1462:1593)(1332:1462:1593)) + (INTERCONNECT SLICE_95/Q1 SLICE_62/D1 (1880:2048:2217)(1880:2048:2217)) + (INTERCONNECT SLICE_95/Q1 nRWE_RNO_1\/SLICE_65/D1 (1458:1583:1708)(1458:1583:1708)) + (INTERCONNECT SLICE_95/Q1 SLICE_66/D1 (638:704:770)(638:704:770)) + (INTERCONNECT SLICE_95/Q1 SLICE_68/C1 (718:795:873)(718:795:873)) + (INTERCONNECT SLICE_95/Q1 SLICE_68/M0 (574:633:693)(574:633:693)) + (INTERCONNECT SLICE_95/Q1 SLICE_92/D0 (638:704:770)(638:704:770)) + (INTERCONNECT SLICE_95/Q1 SLICE_95/C0 (718:795:873)(718:795:873)) + (INTERCONNECT SLICE_42/Q0 SLICE_42/A1 (810:899:989)(810:899:989)) + (INTERCONNECT SLICE_42/Q0 SLICE_61/A1 (1271:1394:1518)(1271:1394:1518)) + (INTERCONNECT SLICE_42/Q0 nRWE_RNO_1\/SLICE_65/B1 (1278:1428:1579)(1278:1428:1579)) (INTERCONNECT SLICE_42/Q0 RCKE_I/PADDO (646:731:817)(646:731:817)) - (INTERCONNECT SLICE_42/F1 nRWE_RNO_1\/SLICE_65/C0 (1537:1688:1840)(1537:1688:1840)) - (INTERCONNECT SLICE_50/F0 SLICE_43/C1 (750:837:924)(750:837:924)) - (INTERCONNECT SLICE_50/F0 SLICE_50/DI0 (31:31:31)(31:31:31)) - (INTERCONNECT SLICE_50/F0 SLICE_61/D1 (970:1082:1195)(970:1082:1195)) - (INTERCONNECT SLICE_50/F0 SLICE_62/C1 (1575:1727:1879)(1575:1727:1879)) - (INTERCONNECT SLICE_83/F0 SLICE_43/C0 (681:758:835)(681:758:835)) - (INTERCONNECT SLICE_83/F0 SLICE_44/C1 (739:821:903)(739:821:903)) + (INTERCONNECT SLICE_44/Q1 SLICE_42/C0 (1126:1237:1348)(1126:1237:1348)) + (INTERCONNECT SLICE_95/Q0 SLICE_42/A0 (1217:1360:1504)(1217:1360:1504)) + (INTERCONNECT SLICE_95/Q0 SLICE_95/M1 (544:603:663)(544:603:663)) + (INTERCONNECT SLICE_42/F0 SLICE_42/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_42/F1 SLICE_68/B0 (1697:1868:2039)(1697:1868:2039)) + (INTERCONNECT SLICE_50/F0 SLICE_43/B1 (606:674:742)(606:674:742)) + (INTERCONNECT SLICE_50/F0 SLICE_50/DI0 (46:46:46)(46:46:46)) + (INTERCONNECT SLICE_50/F0 SLICE_61/D1 (1109:1203:1297)(1109:1203:1297)) + (INTERCONNECT SLICE_50/F0 SLICE_62/C1 (1699:1850:2002)(1699:1850:2002)) + (INTERCONNECT SLICE_95/F0 SLICE_43/B0 (1302:1432:1563)(1302:1432:1563)) + (INTERCONNECT SLICE_95/F0 SLICE_44/C1 (735:822:909)(735:822:909)) (INTERCONNECT SLICE_43/F0 SLICE_43/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_44/F1 SLICE_44/B0 (560:628:696)(560:628:696)) + (INTERCONNECT SLICE_44/F1 SLICE_44/C0 (400:448:497)(400:448:497)) (INTERCONNECT SLICE_44/F0 SLICE_44/DI0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_50/F1 SLICE_63/LSR (528:587:647)(528:587:647)) - (INTERCONNECT SLICE_73/Q0 SLICE_51/D1 (1335:1476:1617)(1335:1476:1617)) - (INTERCONNECT SLICE_72/F0 SLICE_51/B1 (1781:1942:2104)(1781:1942:2104)) - (INTERCONNECT SLICE_66/F0 SLICE_51/A1 (1256:1379:1503)(1256:1379:1503)) - (INTERCONNECT SLICE_66/F0 SLICE_66/A1 (530:591:652)(530:591:652)) - (INTERCONNECT SLICE_52/F1 SLICE_51/D0 (877:975:1074)(877:975:1074)) + (INTERCONNECT SLICE_67/F0 SLICE_51/D1 (987:1079:1171)(987:1079:1171)) + (INTERCONNECT SLICE_67/F0 SLICE_67/B1 (841:937:1034)(841:937:1034)) + (INTERCONNECT SLICE_69/F0 SLICE_51/B1 (1286:1416:1547)(1286:1416:1547)) + (INTERCONNECT SLICE_85/Q0 SLICE_51/A1 (1240:1363:1487)(1240:1363:1487)) + (INTERCONNECT SLICE_52/F1 SLICE_51/D0 (876:974:1072)(876:974:1072)) (INTERCONNECT SLICE_52/F1 SLICE_52/C0 (416:464:513)(416:464:513)) - (INTERCONNECT SLICE_52/F1 SLICE_64/A0 (857:952:1048)(857:952:1048)) + (INTERCONNECT SLICE_52/F1 SLICE_64/A0 (1145:1274:1404)(1145:1274:1404)) (INTERCONNECT SLICE_51/F1 SLICE_51/C0 (400:448:497)(400:448:497)) - (INTERCONNECT SLICE_64/F1 SLICE_51/B0 (591:659:727)(591:659:727)) - (INTERCONNECT SLICE_64/F1 SLICE_52/A0 (868:962:1057)(868:962:1057)) - (INTERCONNECT SLICE_64/F1 SLICE_64/B0 (591:659:727)(591:659:727)) - (INTERCONNECT SLICE_51/Q0 SLICE_51/A0 (530:591:652)(530:591:652)) + (INTERCONNECT SLICE_51/Q0 SLICE_51/B0 (841:937:1034)(841:937:1034)) (INTERCONNECT SLICE_51/Q0 UFMCLK_I/PADDO (1184:1361:1538)(1184:1361:1538)) + (INTERCONNECT SLICE_64/F1 SLICE_51/A0 (810:899:989)(810:899:989)) + (INTERCONNECT SLICE_64/F1 SLICE_52/B0 (914:1015:1117)(914:1015:1117)) + (INTERCONNECT SLICE_64/F1 SLICE_64/C0 (431:479:528)(431:479:528)) (INTERCONNECT SLICE_51/F0 SLICE_51/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_87/F1 SLICE_52/D0 (932:1044:1156)(932:1044:1156)) - (INTERCONNECT SLICE_52/Q0 SLICE_52/B0 (825:921:1018)(825:921:1018)) + (INTERCONNECT SLICE_52/Q0 SLICE_52/D0 (510:568:626)(510:568:626)) (INTERCONNECT SLICE_52/Q0 UFMSDI_I/PADDO (646:731:817)(646:731:817)) + (INTERCONNECT SLICE_55/F0 SLICE_52/A0 (837:931:1026)(837:931:1026)) (INTERCONNECT SLICE_52/F0 SLICE_52/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_67/Q0 SLICE_55/D0 (1466:1589:1712)(1466:1589:1712)) - (INTERCONNECT SLICE_63/Q0 SLICE_55/B0 (2114:2313:2513)(2114:2313:2513)) - (INTERCONNECT SLICE_63/Q0 SLICE_86/A1 (1678:1840:2002)(1678:1840:2002)) - (INTERCONNECT SLICE_63/Q0 SLICE_86/A0 (1678:1840:2002)(1678:1840:2002)) - (INTERCONNECT SLICE_63/Q0 SLICE_89/D1 (2224:2421:2618)(2224:2421:2618)) - (INTERCONNECT SLICE_63/Q0 SLICE_89/D0 (2224:2421:2618)(2224:2421:2618)) - (INTERCONNECT SLICE_63/Q0 SLICE_90/A0 (1802:1970:2138)(1802:1970:2138)) - (INTERCONNECT SLICE_63/Q0 SLICE_91/D1 (1796:1956:2117)(1796:1956:2117)) - (INTERCONNECT SLICE_63/Q0 SLICE_91/C0 (1954:2134:2314)(1954:2134:2314)) - (INTERCONNECT SLICE_63/Q0 SLICE_92/D1 (2320:2504:2689)(2320:2504:2689)) - (INTERCONNECT SLICE_63/Q0 SLICE_92/D0 (2320:2504:2689)(2320:2504:2689)) - (INTERCONNECT SLICE_63/Q0 SLICE_93/B1 (2543:2782:3021)(2543:2782:3021)) - (INTERCONNECT SLICE_63/Q0 SLICE_93/B0 (2543:2782:3021)(2543:2782:3021)) - (INTERCONNECT MAin\[4\]_I/PADDI SLICE_55/A0 (2220:2446:2672)(2220:2446:2672)) - (INTERCONNECT MAin\[4\]_I/PADDI SLICE_67/M0 (2701:2972:3244)(2701:2972:3244)) - (INTERCONNECT MAin\[4\]_I/PADDI SLICE_71/A1 (2663:2930:3197)(2663:2930:3197)) - (INTERCONNECT Din\[4\]_I/PADDI SLICE_55/M0 (2067:2260:2454)(2067:2260:2454)) - (INTERCONNECT Din\[4\]_I/PADDI SLICE_75/C1 (1378:1524:1670)(1378:1524:1670)) - (INTERCONNECT Din\[4\]_I/PADDI SLICE_76/M0 (1530:1693:1856)(1530:1693:1856)) - (INTERCONNECT Din\[4\]_I/PADDI SLICE_77/A1 (2732:2985:3238)(2732:2985:3238)) - (INTERCONNECT Din\[4\]_I/PADDI SLICE_85/B1 (1973:2177:2381)(1973:2177:2381)) - (INTERCONNECT Din\[4\]_I/PADDI SLICE_85/B0 (1973:2177:2381)(1973:2177:2381)) - (INTERCONNECT nCCAS_I/PADDI SLICE_55/CLK (1242:1370:1498)(1242:1370:1498)) - (INTERCONNECT nCCAS_I/PADDI SLICE_56/CLK (2109:2309:2510)(2109:2309:2510)) - (INTERCONNECT nCCAS_I/PADDI SLICE_75/M0 (1503:1660:1818)(1503:1660:1818)) - (INTERCONNECT nCCAS_I/PADDI SLICE_78/M0 (2373:2602:2831)(2373:2602:2831)) - (INTERCONNECT nCCAS_I/PADDI SLICE_78/M1 (2373:2602:2831)(2373:2602:2831)) - (INTERCONNECT nCCAS_I/PADDI SLICE_79/CLK (1706:1877:2049)(1706:1877:2049)) - (INTERCONNECT nCCAS_I/PADDI SLICE_85/CLK (1706:1877:2049)(1706:1877:2049)) - (INTERCONNECT nCCAS_I/PADDI SLICE_88/D0 (2063:2255:2448)(2063:2255:2448)) - (INTERCONNECT SLICE_55/F0 RA\[4\]_I/PADDO (1288:1474:1660)(1288:1474:1660)) - (INTERCONNECT SLICE_55/Q0 RD\[4\]_I/PADDO (2378:2648:2918)(2378:2648:2918)) + (INTERCONNECT SLICE_58/F1 SLICE_55/D0 (987:1079:1171)(987:1079:1171)) + (INTERCONNECT SLICE_58/F1 SLICE_71/B0 (903:1005:1108)(903:1005:1108)) + (INTERCONNECT SLICE_58/F1 SLICE_72/B0 (903:1005:1108)(903:1005:1108)) + (INTERCONNECT SLICE_88/Q0 SLICE_55/C0 (1126:1237:1348)(1126:1237:1348)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_55/M1 (1837:2030:2224)(1837:2030:2224)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_73/B1 (1845:2041:2237)(1845:2041:2237)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_83/A1 (2237:2459:2682)(2237:2459:2682)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_85/A1 (2237:2459:2682)(2237:2459:2682)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_85/A0 (2237:2459:2682)(2237:2459:2682)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_87/A1 (2647:2899:3151)(2647:2899:3151)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_87/A0 (2647:2899:3151)(2647:2899:3151)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_88/A1 (2237:2459:2682)(2237:2459:2682)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_88/A0 (2237:2459:2682)(2237:2459:2682)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_93/M1 (1638:1799:1960)(1638:1799:1960)) + (INTERCONNECT nCCAS_I/PADDI SLICE_55/CLK (2508:2737:2966)(2508:2737:2966)) + (INTERCONNECT nCCAS_I/PADDI SLICE_56/CLK (2105:2305:2505)(2105:2305:2505)) + (INTERCONNECT nCCAS_I/PADDI SLICE_74/M0 (3052:3367:3683)(3052:3367:3683)) + (INTERCONNECT nCCAS_I/PADDI SLICE_82/CLK (1702:1873:2044)(1702:1873:2044)) + (INTERCONNECT nCCAS_I/PADDI SLICE_84/CLK (1702:1873:2044)(1702:1873:2044)) + (INTERCONNECT nCCAS_I/PADDI SLICE_87/M0 (2952:3274:3596)(2952:3274:3596)) + (INTERCONNECT nCCAS_I/PADDI SLICE_87/M1 (2952:3274:3596)(2952:3274:3596)) + (INTERCONNECT nCCAS_I/PADDI SLICE_100/D1 (1639:1800:1962)(1639:1800:1962)) + (INTERCONNECT SLICE_55/Q0 RD\[4\]_I/PADDO (2339:2629:2919)(2339:2629:2919)) (INTERCONNECT SLICE_55/Q1 RD\[5\]_I/PADDO (1982:2228:2475)(1982:2228:2475)) - (INTERCONNECT SLICE_76/Q1 SLICE_56/D1 (1498:1630:1763)(1498:1630:1763)) - (INTERCONNECT SLICE_71/Q0 SLICE_56/C1 (1653:1804:1956)(1653:1804:1956)) - (INTERCONNECT SLICE_77/Q0 SLICE_56/B1 (1813:1984:2155)(1813:1984:2155)) - (INTERCONNECT SLICE_77/Q1 SLICE_56/A1 (2138:2321:2505)(2138:2321:2505)) - (INTERCONNECT Din\[7\]_I/PADDI SLICE_56/M1 (2264:2497:2730)(2264:2497:2730)) - (INTERCONNECT Din\[7\]_I/PADDI SLICE_75/B1 (1828:2016:2205)(1828:2016:2205)) - (INTERCONNECT Din\[7\]_I/PADDI SLICE_77/C1 (1272:1412:1553)(1272:1412:1553)) - (INTERCONNECT Din\[7\]_I/PADDI SLICE_77/M1 (1424:1581:1739)(1424:1581:1739)) - (INTERCONNECT Din\[7\]_I/PADDI SLICE_85/C1 (2522:2767:3013)(2522:2767:3013)) - (INTERCONNECT Din\[7\]_I/PADDI SLICE_85/C0 (2522:2767:3013)(2522:2767:3013)) + (INTERCONNECT SLICE_101/Q0 SLICE_56/A0 (1351:1480:1610)(1351:1480:1610)) + (INTERCONNECT SLICE_101/Q0 SLICE_62/D0 (1798:1966:2135)(1798:1966:2135)) + (INTERCONNECT SLICE_101/Q0 SLICE_63/B1 (2203:2397:2592)(2203:2397:2592)) + (INTERCONNECT SLICE_56/F0 SLICE_60/B0 (883:984:1086)(883:984:1086)) (INTERCONNECT SLICE_56/Q0 RD\[6\]_I/PADDO (646:731:817)(646:731:817)) - (INTERCONNECT SLICE_56/F1 SLICE_70/B1 (1813:1984:2155)(1813:1984:2155)) + (INTERCONNECT SLICE_56/F1 SLICE_71/D1 (1785:1941:2098)(1785:1941:2098)) + (INTERCONNECT SLICE_56/F1 SLICE_72/D1 (1785:1941:2098)(1785:1941:2098)) (INTERCONNECT SLICE_56/Q1 RD\[7\]_I/PADDO (1532:1758:1984)(1532:1758:1984)) - (INTERCONNECT Din\[2\]_I/PADDI SLICE_57/B1 (1547:1713:1879)(1547:1713:1879)) - (INTERCONNECT Din\[2\]_I/PADDI SLICE_71/M0 (1539:1702:1866)(1539:1702:1866)) - (INTERCONNECT Din\[2\]_I/PADDI SLICE_73/M1 (1921:2109:2298)(1921:2109:2298)) - (INTERCONNECT Din\[2\]_I/PADDI SLICE_77/A0 (1904:2092:2280)(1904:2092:2280)) - (INTERCONNECT Din\[2\]_I/PADDI SLICE_78/A0 (1904:2092:2280)(1904:2092:2280)) - (INTERCONNECT Din\[2\]_I/PADDI SLICE_85/M0 (2324:2541:2759)(2324:2541:2759)) - (INTERCONNECT Din\[0\]_I/PADDI SLICE_57/A1 (1891:2077:2264)(1891:2077:2264)) - (INTERCONNECT Din\[0\]_I/PADDI SLICE_70/M0 (2325:2544:2764)(2325:2544:2764)) - (INTERCONNECT Din\[0\]_I/PADDI SLICE_74/M0 (1529:1691:1854)(1529:1691:1854)) - (INTERCONNECT Din\[0\]_I/PADDI SLICE_76/B1 (1937:2130:2324)(1937:2130:2324)) - (INTERCONNECT Din\[0\]_I/PADDI SLICE_79/M0 (2739:2994:3250)(2739:2994:3250)) - (INTERCONNECT Din\[0\]_I/PADDI SLICE_85/A1 (2297:2513:2729)(2297:2513:2729)) - (INTERCONNECT Din\[1\]_I/PADDI SLICE_57/D0 (1217:1343:1469)(1217:1343:1469)) - (INTERCONNECT Din\[1\]_I/PADDI SLICE_70/M1 (714:807:900)(714:807:900)) - (INTERCONNECT Din\[1\]_I/PADDI SLICE_73/M0 (1521:1678:1835)(1521:1678:1835)) - (INTERCONNECT Din\[1\]_I/PADDI SLICE_75/D0 (1217:1343:1469)(1217:1343:1469)) - (INTERCONNECT Din\[1\]_I/PADDI SLICE_76/B0 (1421:1579:1738)(1421:1579:1738)) - (INTERCONNECT Din\[1\]_I/PADDI SLICE_79/M1 (1959:2159:2360)(1959:2159:2360)) - (INTERCONNECT Din\[1\]_I/PADDI SLICE_85/D1 (1941:2140:2339)(1941:2140:2339)) - (INTERCONNECT SLICE_57/F1 SLICE_57/C0 (400:448:497)(400:448:497)) + (INTERCONNECT SLICE_83/F1 SLICE_57/C1 (416:464:513)(416:464:513)) + (INTERCONNECT SLICE_83/F1 SLICE_83/C0 (416:464:513)(416:464:513)) + (INTERCONNECT SLICE_83/F0 SLICE_57/C0 (400:448:497)(400:448:497)) + (INTERCONNECT SLICE_57/F1 SLICE_57/B0 (560:628:696)(560:628:696)) (INTERCONNECT SLICE_57/F0 SLICE_57/DI0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_58/F0 SLICE_58/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_68/F0 SLICE_58/CE (875:974:1073)(875:974:1073)) - (INTERCONNECT SLICE_58/F1 SLICE_87/B1 (1544:1731:1919)(1544:1731:1919)) - (INTERCONNECT SLICE_58/F1 SLICE_87/D0 (940:1054:1169)(940:1054:1169)) - (INTERCONNECT SLICE_59/F1 SLICE_59/D0 (510:568:626)(510:568:626)) - (INTERCONNECT SLICE_62/F1 SLICE_59/C0 (1669:1820:1972)(1669:1820:1972)) + (INTERCONNECT SLICE_71/F0 SLICE_58/CE (875:974:1073)(875:974:1073)) + (INTERCONNECT SLICE_66/F0 SLICE_59/B1 (1378:1510:1643)(1378:1510:1643)) + (INTERCONNECT SLICE_84/F1 SLICE_59/D0 (1335:1476:1617)(1335:1476:1617)) + (INTERCONNECT SLICE_59/F1 SLICE_59/C0 (400:448:497)(400:448:497)) + (INTERCONNECT SLICE_62/F1 SLICE_59/A0 (1637:1797:1957)(1637:1797:1957)) (INTERCONNECT SLICE_62/F1 SLICE_62/B0 (576:644:712)(576:644:712)) - (INTERCONNECT SLICE_80/F0 SLICE_59/A0 (1201:1344:1488)(1201:1344:1488)) (INTERCONNECT SLICE_59/F0 SLICE_59/DI0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_59/Q0 nRCAS_I/PADDO (646:731:817)(646:731:817)) - (INTERCONNECT SLICE_82/Q0 SLICE_60/D1 (1509:1643:1777)(1509:1643:1777)) - (INTERCONNECT SLICE_82/Q0 SLICE_63/D1 (1491:1617:1743)(1491:1617:1743)) - (INTERCONNECT SLICE_82/Q0 SLICE_79/D1 (1491:1617:1743)(1491:1617:1743)) - (INTERCONNECT SLICE_82/Q0 SLICE_80/B1 (2209:2402:2596)(2209:2402:2596)) - (INTERCONNECT SLICE_94/F0 SLICE_60/C0 (1529:1669:1809)(1529:1669:1809)) - (INTERCONNECT SLICE_60/F1 SLICE_60/A0 (779:868:958)(779:868:958)) + (INTERCONNECT SLICE_87/Q1 SLICE_60/A1 (1667:1831:1995)(1667:1831:1995)) + (INTERCONNECT SLICE_87/Q1 SLICE_62/A1 (1549:1708:1867)(1549:1708:1867)) + (INTERCONNECT SLICE_87/Q1 SLICE_82/A0 (1549:1708:1867)(1549:1708:1867)) + (INTERCONNECT SLICE_84/F0 SLICE_60/D0 (971:1063:1155)(971:1063:1155)) + (INTERCONNECT SLICE_60/F1 SLICE_60/C0 (400:448:497)(400:448:497)) + (INTERCONNECT SLICE_68/F0 SLICE_60/A0 (1735:1889:2044)(1735:1889:2044)) (INTERCONNECT SLICE_60/F0 SLICE_60/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_60/Q0 nRCS_I/PADDO (1291:1473:1656)(1291:1473:1656)) + (INTERCONNECT SLICE_60/Q0 nRCS_I/PADDO (646:731:817)(646:731:817)) + (INTERCONNECT SLICE_92/F1 SLICE_61/C0 (1234:1347:1460)(1234:1347:1460)) + (INTERCONNECT SLICE_92/F1 SLICE_66/A0 (795:884:974)(795:884:974)) + (INTERCONNECT SLICE_61/F1 SLICE_61/A0 (779:868:958)(779:868:958)) (INTERCONNECT SLICE_61/F0 SLICE_61/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_61/Q0 nRRAS_I/PADDO (1935:2190:2445)(1935:2190:2445)) - (INTERCONNECT SLICE_78/Q1 SLICE_62/D1 (1079:1173:1267)(1079:1173:1267)) - (INTERCONNECT SLICE_78/Q1 SLICE_80/C0 (1637:1779:1921)(1637:1779:1921)) - (INTERCONNECT SLICE_81/Q0 SLICE_62/D0 (1679:1834:1990)(1679:1834:1990)) - (INTERCONNECT SLICE_81/Q0 SLICE_63/B1 (1691:1860:2030)(1691:1860:2030)) - (INTERCONNECT SLICE_81/Q0 SLICE_80/D0 (1376:1507:1638)(1376:1507:1638)) - (INTERCONNECT nRWE_RNO_1\/SLICE_65/OFX0 SLICE_62/C0 (1653:1804:1956) - (1653:1804:1956)) - (INTERCONNECT SLICE_79/F0 SLICE_62/A0 (1651:1815:1979)(1651:1815:1979)) + (INTERCONNECT SLICE_61/Q0 nRRAS_I/PADDO (1600:1819:2038)(1600:1819:2038)) + (INTERCONNECT nRWE_RNO_1\/SLICE_65/OFX0 SLICE_62/C0 (1621:1763:1905) + (1621:1763:1905)) + (INTERCONNECT SLICE_82/F0 SLICE_62/A0 (1240:1363:1487)(1240:1363:1487)) (INTERCONNECT SLICE_62/F0 SLICE_62/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_62/Q0 nRWE_I/PADDO (2095:2345:2595)(2095:2345:2595)) - (INTERCONNECT SLICE_63/F1 SLICE_63/D0 (510:568:626)(510:568:626)) + (INTERCONNECT SLICE_62/Q0 nRWE_I/PADDO (2378:2648:2918)(2378:2648:2918)) + (INTERCONNECT SLICE_63/F1 SLICE_63/C0 (400:448:497)(400:448:497)) (INTERCONNECT SLICE_63/F0 SLICE_63/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63/Q0 SLICE_91/A1 (1801:1968:2136)(1801:1968:2136)) + (INTERCONNECT SLICE_63/Q0 SLICE_91/A0 (1801:1968:2136)(1801:1968:2136)) + (INTERCONNECT SLICE_63/Q0 SLICE_93/A1 (1635:1810:1986)(1635:1810:1986)) + (INTERCONNECT SLICE_63/Q0 SLICE_96/D1 (1942:2107:2273)(1942:2107:2273)) + (INTERCONNECT SLICE_63/Q0 SLICE_96/D0 (1942:2107:2273)(1942:2107:2273)) + (INTERCONNECT SLICE_63/Q0 SLICE_97/B1 (2807:3085:3364)(2807:3085:3364)) + (INTERCONNECT SLICE_63/Q0 SLICE_97/A0 (2469:2705:2942)(2469:2705:2942)) + (INTERCONNECT SLICE_63/Q0 SLICE_98/B1 (2515:2758:3002)(2515:2758:3002)) + (INTERCONNECT SLICE_63/Q0 SLICE_98/C0 (2647:2906:3165)(2647:2906:3165)) + (INTERCONNECT SLICE_63/Q0 SLICE_99/A1 (1628:1803:1978)(1628:1803:1978)) + (INTERCONNECT SLICE_63/Q0 SLICE_99/C0 (2341:2563:2786)(2341:2563:2786)) + (INTERCONNECT SLICE_63/Q0 SLICE_101/A1 (2455:2690:2925)(2455:2690:2925)) (INTERCONNECT SLICE_64/Q0 SLICE_64/D0 (526:584:642)(526:584:642)) (INTERCONNECT SLICE_64/Q0 nUFMCS_I/PADDO (1548:1774:2000)(1548:1774:2000)) - (INTERCONNECT SLICE_66/F1 SLICE_64/C0 (1529:1669:1809)(1529:1669:1809)) + (INTERCONNECT SLICE_67/F1 SLICE_64/B0 (1286:1416:1547)(1286:1416:1547)) (INTERCONNECT SLICE_64/F0 SLICE_64/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_73/Q1 SLICE_66/B1 (1247:1397:1548)(1247:1397:1548)) - (INTERCONNECT SLICE_81/F0 SLICE_66/D0 (1383:1512:1642)(1383:1512:1642)) - (INTERCONNECT SLICE_81/F0 SLICE_74/A0 (1652:1813:1974)(1652:1813:1974)) - (INTERCONNECT SLICE_74/F1 SLICE_66/A0 (795:884:974)(795:884:974)) - (INTERCONNECT SLICE_74/F1 SLICE_74/C0 (416:464:513)(416:464:513)) - (INTERCONNECT SLICE_66/Q0 SLICE_90/D0 (1375:1502:1629)(1375:1502:1629)) - (INTERCONNECT SLICE_66/Q1 SLICE_91/D0 (1901:2062:2224)(1901:2062:2224)) - (INTERCONNECT MAin\[5\]_I/PADDI SLICE_67/M1 (1621:1774:1928)(1621:1774:1928)) - (INTERCONNECT MAin\[5\]_I/PADDI SLICE_71/D1 (1614:1766:1919)(1614:1766:1919)) - (INTERCONNECT MAin\[5\]_I/PADDI SLICE_93/A1 (1908:2101:2294)(1908:2101:2294)) - (INTERCONNECT SLICE_67/F1 SLICE_73/CE (947:1062:1178)(947:1062:1178)) - (INTERCONNECT SLICE_67/F1 SLICE_74/CE (1350:1494:1639)(1350:1494:1639)) - (INTERCONNECT SLICE_67/Q1 SLICE_93/D1 (1063:1157:1251)(1063:1157:1251)) - (INTERCONNECT SLICE_87/F0 SLICE_68/C0 (735:822:909)(735:822:909)) - (INTERCONNECT SLICE_87/F0 SLICE_69/D0 (580:648:716)(580:648:716)) - (INTERCONNECT SLICE_68/F1 SLICE_68/B0 (825:921:1018)(825:921:1018)) - (INTERCONNECT SLICE_84/F0 SLICE_68/A0 (786:876:966)(786:876:966)) - (INTERCONNECT SLICE_84/F0 SLICE_69/A0 (786:876:966)(786:876:966)) - (INTERCONNECT SLICE_69/F1 SLICE_69/C0 (400:448:497)(400:448:497)) - (INTERCONNECT SLICE_70/Q0 SLICE_70/D1 (510:568:626)(510:568:626)) - (INTERCONNECT SLICE_71/F0 SLICE_70/C1 (723:805:887)(723:805:887)) - (INTERCONNECT SLICE_70/Q1 SLICE_70/A1 (514:575:636)(514:575:636)) - (INTERCONNECT MAin\[7\]_I/PADDI SLICE_71/C1 (1805:1987:2169)(1805:1987:2169)) - (INTERCONNECT MAin\[7\]_I/PADDI SLICE_88/M1 (1657:1821:1985)(1657:1821:1985)) - (INTERCONNECT MAin\[7\]_I/PADDI SLICE_91/B1 (2368:2598:2829)(2368:2598:2829)) - (INTERCONNECT MAin\[6\]_I/PADDI SLICE_71/B1 (1951:2152:2353)(1951:2152:2353)) - (INTERCONNECT MAin\[6\]_I/PADDI SLICE_88/M0 (2353:2581:2809)(2353:2581:2809)) - (INTERCONNECT MAin\[6\]_I/PADDI SLICE_92/C1 (3008:3283:3558)(3008:3283:3558)) - (INTERCONNECT SLICE_71/F1 SLICE_71/D0 (510:568:626)(510:568:626)) - (INTERCONNECT SLICE_71/Q1 SLICE_71/C0 (665:742:819)(665:742:819)) - (INTERCONNECT SLICE_76/Q0 SLICE_71/B0 (825:921:1018)(825:921:1018)) - (INTERCONNECT SLICE_88/F1 SLICE_71/A0 (1490:1668:1846)(1490:1668:1846)) - (INTERCONNECT SLICE_81/F1 SLICE_72/D1 (510:568:626)(510:568:626)) - (INTERCONNECT MAin\[3\]_I/PADDI SLICE_72/M1 (1657:1821:1985)(1657:1821:1985)) - (INTERCONNECT MAin\[3\]_I/PADDI SLICE_88/A1 (1919:2113:2308)(1919:2113:2308)) - (INTERCONNECT MAin\[3\]_I/PADDI SLICE_93/A0 (2322:2545:2769)(2322:2545:2769)) - (INTERCONNECT MAin\[2\]_I/PADDI SLICE_72/M0 (1606:1757:1909)(1606:1757:1909)) - (INTERCONNECT MAin\[2\]_I/PADDI SLICE_88/B1 (1519:1681:1844)(1519:1681:1844)) - (INTERCONNECT MAin\[2\]_I/PADDI SLICE_92/B0 (2326:2552:2779)(2326:2552:2779)) - (INTERCONNECT SLICE_72/Q0 SLICE_92/C0 (1653:1804:1956)(1653:1804:1956)) - (INTERCONNECT SLICE_72/Q1 SLICE_93/D0 (1466:1589:1712)(1466:1589:1712)) - (INTERCONNECT SLICE_74/Q0 SLICE_87/C1 (665:742:819)(665:742:819)) - (INTERCONNECT SLICE_75/Q0 SLICE_75/M1 (528:587:647)(528:587:647)) - (INTERCONNECT SLICE_77/F1 SLICE_77/C0 (400:448:497)(400:448:497)) - (INTERCONNECT SLICE_79/F1 SLICE_79/C0 (400:448:497)(400:448:497)) - (INTERCONNECT SLICE_79/Q0 RD\[0\]_I/PADDO (1164:1346:1528)(1164:1346:1528)) - (INTERCONNECT SLICE_79/Q1 RD\[1\]_I/PADDO (1165:1345:1526)(1165:1345:1526)) - (INTERCONNECT SLICE_80/F1 SLICE_80/B0 (560:628:696)(560:628:696)) - (INTERCONNECT MAin\[9\]_I/PADDI SLICE_80/M1 (1654:1819:1984)(1654:1819:1984)) - (INTERCONNECT MAin\[9\]_I/PADDI SLICE_86/C1 (1769:1940:2112)(1769:1940:2112)) - (INTERCONNECT MAin\[9\]_I/PADDI SLICE_86/C0 (1769:1940:2112)(1769:1940:2112)) - (INTERCONNECT MAin\[9\]_I/PADDI SLICE_89/C1 (2608:2849:3090)(2608:2849:3090)) - (INTERCONNECT MAin\[8\]_I/PADDI SLICE_80/M0 (1508:1668:1828)(1508:1668:1828)) - (INTERCONNECT MAin\[8\]_I/PADDI SLICE_89/C0 (3001:3275:3550)(3001:3275:3550)) - (INTERCONNECT SLICE_80/Q0 SLICE_89/B0 (1247:1397:1548)(1247:1397:1548)) - (INTERCONNECT SLICE_80/Q1 SLICE_86/B0 (1378:1510:1643)(1378:1510:1643)) - (INTERCONNECT nFWE_I/PADDI SLICE_81/M0 (1654:1819:1984)(1654:1819:1984)) - (INTERCONNECT nFWE_I/PADDI SLICE_81/M1 (1654:1819:1984)(1654:1819:1984)) - (INTERCONNECT nFWE_I/PADDI SLICE_88/C1 (2204:2414:2624)(2204:2414:2624)) - (INTERCONNECT nFWE_I/PADDI SLICE_88/C0 (2204:2414:2624)(2204:2414:2624)) - (INTERCONNECT CROW\[1\]_I/PADDI SLICE_83/M1 (2038:2228:2418)(2038:2228:2418)) - (INTERCONNECT CROW\[0\]_I/PADDI SLICE_83/M0 (2307:2528:2750)(2307:2528:2750)) - (INTERCONNECT SLICE_83/Q0 RBA\[0\]_I/PADDO (1165:1345:1526)(1165:1345:1526)) - (INTERCONNECT SLICE_83/Q1 RBA\[1\]_I/PADDO (2466:2735:3005)(2466:2735:3005)) - (INTERCONNECT SLICE_85/Q0 RD\[2\]_I/PADDO (646:731:817)(646:731:817)) - (INTERCONNECT SLICE_85/Q1 RD\[3\]_I/PADDO (1568:1777:1987)(1568:1777:1987)) - (INTERCONNECT SLICE_86/F0 RA\[9\]_I/PADDO (2477:2778:3080)(2477:2778:3080)) - (INTERCONNECT SLICE_86/F1 RDQML_I/PADDO (1532:1758:1984)(1532:1758:1984)) - (INTERCONNECT SLICE_88/F0 RD\[0\]_I/PADDT (1756:2001:2247)(1756:2001:2247)) - (INTERCONNECT SLICE_88/F0 RD\[7\]_I/PADDT (2571:2883:3195)(2571:2883:3195)) - (INTERCONNECT SLICE_88/F0 RD\[6\]_I/PADDT (2571:2883:3195)(2571:2883:3195)) - (INTERCONNECT SLICE_88/F0 RD\[5\]_I/PADDT (2538:2838:3139)(2538:2838:3139)) - (INTERCONNECT SLICE_88/F0 RD\[4\]_I/PADDT (2538:2838:3139)(2538:2838:3139)) - (INTERCONNECT SLICE_88/F0 RD\[3\]_I/PADDT (1741:1997:2254)(1741:1997:2254)) - (INTERCONNECT SLICE_88/F0 RD\[2\]_I/PADDT (1741:1997:2254)(1741:1997:2254)) - (INTERCONNECT SLICE_88/F0 RD\[1\]_I/PADDT (2098:2368:2638)(2098:2368:2638)) - (INTERCONNECT SLICE_88/Q0 SLICE_92/A1 (1735:1889:2044)(1735:1889:2044)) - (INTERCONNECT SLICE_88/Q1 SLICE_91/C1 (1218:1331:1444)(1218:1331:1444)) - (INTERCONNECT SLICE_89/F0 RA\[8\]_I/PADDO (1979:2229:2479)(1979:2229:2479)) - (INTERCONNECT SLICE_89/F1 RDQMH_I/PADDO (646:731:817)(646:731:817)) - (INTERCONNECT SLICE_90/F0 RA\[0\]_I/PADDO (1723:1947:2172)(1723:1947:2172)) - (INTERCONNECT SLICE_91/F0 RA\[1\]_I/PADDO (1971:2209:2448)(1971:2209:2448)) - (INTERCONNECT SLICE_91/F1 RA\[7\]_I/PADDO (1288:1474:1660)(1288:1474:1660)) - (INTERCONNECT SLICE_92/F0 RA\[2\]_I/PADDO (1168:1345:1522)(1168:1345:1522)) - (INTERCONNECT SLICE_92/F1 RA\[6\]_I/PADDO (646:731:817)(646:731:817)) - (INTERCONNECT SLICE_93/F0 RA\[3\]_I/PADDO (1610:1831:2052)(1610:1831:2052)) - (INTERCONNECT SLICE_93/F1 RA\[5\]_I/PADDO (1982:2228:2475)(1982:2228:2475)) - (INTERCONNECT SLICE_94/Q0 RA\[10\]_I/PADDO (646:731:817)(646:731:817)) + (INTERCONNECT SLICE_92/F0 nRWE_RNO_1\/SLICE_65/D0 (932:1044:1156)(932:1044:1156)) + (INTERCONNECT SLICE_85/Q1 SLICE_67/D1 (1352:1480:1609)(1352:1480:1609)) + (INTERCONNECT SLICE_80/F1 SLICE_67/D0 (261:290:320)(261:290:320)) + (INTERCONNECT SLICE_80/F1 SLICE_80/C0 (416:464:513)(416:464:513)) + (INTERCONNECT SLICE_86/F0 SLICE_67/B0 (576:644:712)(576:644:712)) + (INTERCONNECT SLICE_86/F0 SLICE_80/D0 (261:290:320)(261:290:320)) + (INTERCONNECT MAin\[3\]_I/PADDI SLICE_67/M1 (1818:2003:2188)(1818:2003:2188)) + (INTERCONNECT MAin\[3\]_I/PADDI SLICE_76/B1 (2243:2461:2679)(2243:2461:2679)) + (INTERCONNECT MAin\[3\]_I/PADDI SLICE_81/D0 (1928:2107:2287)(1928:2107:2287)) + (INTERCONNECT MAin\[3\]_I/PADDI SLICE_93/B0 (3058:3342:3627)(3058:3342:3627)) + (INTERCONNECT MAin\[3\]_I/PADDI SLICE_97/B0 (3461:3774:4088)(3461:3774:4088)) + (INTERCONNECT MAin\[2\]_I/PADDI SLICE_67/M0 (708:799:891)(708:799:891)) + (INTERCONNECT MAin\[2\]_I/PADDI SLICE_76/A0 (1487:1643:1799)(1487:1643:1799)) + (INTERCONNECT MAin\[2\]_I/PADDI SLICE_81/B0 (1533:1696:1859)(1533:1696:1859)) + (INTERCONNECT MAin\[2\]_I/PADDI SLICE_93/D0 (2064:2258:2453)(2064:2258:2453)) + (INTERCONNECT MAin\[2\]_I/PADDI SLICE_98/C1 (2622:2864:3107)(2622:2864:3107)) + (INTERCONNECT SLICE_67/Q0 SLICE_98/D1 (1778:1934:2090)(1778:1934:2090)) + (INTERCONNECT SLICE_67/Q1 SLICE_97/D0 (1498:1630:1763)(1498:1630:1763)) + (INTERCONNECT SLICE_95/F1 SLICE_68/D1 (245:274:304)(245:274:304)) + (INTERCONNECT SLICE_68/F1 SLICE_68/C0 (400:448:497)(400:448:497)) + (INTERCONNECT SLICE_90/F1 SLICE_68/LSR (1389:1522:1656)(1389:1522:1656)) + (INTERCONNECT SLICE_86/F1 SLICE_69/A1 (837:931:1026)(837:931:1026)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_69/M1 (709:801:894)(709:801:894)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_76/A1 (2194:2405:2617)(2194:2405:2617)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_81/A1 (2483:2729:2975)(2483:2729:2975)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_93/C1 (3297:3589:3882)(3297:3589:3882)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_93/C0 (3297:3589:3882)(3297:3589:3882)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_69/M0 (1222:1347:1473)(1222:1347:1473)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_70/B1 (2265:2502:2740)(2265:2502:2740)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_76/C1 (2113:2333:2554)(2113:2333:2554)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_81/B1 (2273:2513:2753)(2273:2513:2753)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_97/D1 (2085:2286:2488)(2085:2286:2488)) + (INTERCONNECT SLICE_69/Q0 SLICE_97/A1 (2086:2288:2491)(2086:2288:2491)) + (INTERCONNECT SLICE_69/Q1 SLICE_93/D1 (1466:1589:1712)(1466:1589:1712)) + (INTERCONNECT SLICE_93/F0 SLICE_70/D1 (1466:1589:1712)(1466:1589:1712)) + (INTERCONNECT nFWE_I/PADDI SLICE_70/C1 (1813:1997:2182)(1813:1997:2182)) + (INTERCONNECT nFWE_I/PADDI SLICE_76/B0 (1973:2177:2381)(1973:2177:2381)) + (INTERCONNECT nFWE_I/PADDI SLICE_77/D0 (1947:2147:2347)(1947:2147:2347)) + (INTERCONNECT nFWE_I/PADDI SLICE_100/B1 (2376:2609:2842)(2376:2609:2842)) + (INTERCONNECT nFWE_I/PADDI SLICE_101/M0 (2502:2734:2966)(2502:2734:2966)) + (INTERCONNECT nFWE_I/PADDI SLICE_101/M1 (2502:2734:2966)(2502:2734:2966)) + (INTERCONNECT SLICE_79/F0 SLICE_70/A1 (1256:1379:1503)(1256:1379:1503)) + (INTERCONNECT SLICE_79/F0 SLICE_76/D0 (261:290:320)(261:290:320)) + (INTERCONNECT SLICE_70/F1 SLICE_70/C0 (416:464:513)(416:464:513)) + (INTERCONNECT SLICE_70/F1 SLICE_73/D0 (584:647:710)(584:647:710)) + (INTERCONNECT SLICE_94/F0 SLICE_71/B1 (886:993:1100)(886:993:1100)) + (INTERCONNECT SLICE_94/F0 SLICE_72/B1 (886:993:1100)(886:993:1100)) + (INTERCONNECT SLICE_89/F1 SLICE_71/A1 (841:936:1032)(841:936:1032)) + (INTERCONNECT SLICE_89/F1 SLICE_72/C1 (1016:1133:1251)(1016:1133:1251)) + (INTERCONNECT SLICE_71/F1 SLICE_71/C0 (400:448:497)(400:448:497)) + (INTERCONNECT SLICE_72/F1 SLICE_72/D0 (510:568:626)(510:568:626)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_73/C1 (1370:1514:1659)(1370:1514:1659)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_75/A1 (2291:2512:2733)(2291:2512:2733)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_79/M1 (1111:1231:1352)(1111:1231:1352)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_82/M1 (1671:1836:2002)(1671:1836:2002)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_83/B0 (2382:2614:2846)(2382:2614:2846)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_85/D1 (2367:2598:2829)(2367:2598:2829)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_85/D0 (2367:2598:2829)(2367:2598:2829)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_88/B1 (2686:2955:3225)(2686:2955:3225)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_88/D0 (2082:2278:2475)(2082:2278:2475)) + (INTERCONNECT MAin\[7\]_I/PADDI SLICE_73/M1 (1222:1347:1473)(1222:1347:1473)) + (INTERCONNECT MAin\[7\]_I/PADDI SLICE_79/A1 (1919:2113:2308)(1919:2113:2308)) + (INTERCONNECT MAin\[7\]_I/PADDI SLICE_99/D1 (1650:1813:1976)(1650:1813:1976)) + (INTERCONNECT MAin\[6\]_I/PADDI SLICE_73/M0 (1610:1762:1914)(1610:1762:1914)) + (INTERCONNECT MAin\[6\]_I/PADDI SLICE_79/C1 (2571:2799:3028)(2571:2799:3028)) + (INTERCONNECT MAin\[6\]_I/PADDI SLICE_101/C1 (4248:4617:4987)(4248:4617:4987)) + (INTERCONNECT SLICE_73/Q0 SLICE_101/B1 (1813:1984:2155)(1813:1984:2155)) + (INTERCONNECT SLICE_73/Q1 SLICE_99/C1 (2056:2236:2417)(2056:2236:2417)) + (INTERCONNECT SLICE_74/F1 SLICE_74/D0 (526:584:642)(526:584:642)) + (INTERCONNECT SLICE_74/F1 SLICE_78/B0 (841:937:1034)(841:937:1034)) + (INTERCONNECT SLICE_78/F1 SLICE_74/B0 (576:644:712)(576:644:712)) + (INTERCONNECT SLICE_78/F1 SLICE_78/C0 (416:464:513)(416:464:513)) + (INTERCONNECT SLICE_88/F1 SLICE_74/A0 (1659:1825:1992)(1659:1825:1992)) + (INTERCONNECT SLICE_88/F1 SLICE_78/A0 (1659:1825:1992)(1659:1825:1992)) + (INTERCONNECT SLICE_74/Q0 SLICE_74/M1 (528:587:647)(528:587:647)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_75/B1 (1933:2126:2319)(1933:2126:2319)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_78/A1 (2297:2512:2728)(2297:2512:2728)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_79/M0 (2731:2979:3228)(2731:2979:3228)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_82/M0 (2314:2532:2750)(2314:2532:2750)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_83/D0 (2438:2651:2865)(2438:2651:2865)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_85/M1 (2745:2994:3244)(2745:2994:3244)) + (INTERCONNECT SLICE_75/Q0 SLICE_77/D1 (568:631:694)(568:631:694)) + (INTERCONNECT SLICE_75/Q1 SLICE_77/B1 (879:985:1092)(879:985:1092)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_76/D1 (2052:2243:2435)(2052:2243:2435)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_81/D1 (2052:2243:2435)(2052:2243:2435)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_89/M0 (2762:3018:3275)(2762:3018:3275)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_93/A0 (3574:3901:4228)(3574:3901:4228)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_98/A0 (3574:3901:4228)(3574:3901:4228)) + (INTERCONNECT SLICE_76/F1 SLICE_76/C0 (400:448:497)(400:448:497)) + (INTERCONNECT SLICE_76/Q0 SLICE_100/A0 (833:932:1032)(833:932:1032)) + (INTERCONNECT SLICE_76/Q1 SLICE_100/D0 (568:631:694)(568:631:694)) + (INTERCONNECT SLICE_79/Q0 SLICE_77/C1 (665:742:819)(665:742:819)) + (INTERCONNECT SLICE_93/Q1 SLICE_77/A1 (1651:1815:1979)(1651:1815:1979)) + (INTERCONNECT SLICE_100/F0 SLICE_77/C0 (727:810:893)(727:810:893)) + (INTERCONNECT SLICE_100/F0 SLICE_79/A0 (841:936:1032)(841:936:1032)) + (INTERCONNECT SLICE_77/F1 SLICE_77/B0 (576:644:712)(576:644:712)) + (INTERCONNECT SLICE_77/F1 SLICE_79/B0 (576:644:712)(576:644:712)) + (INTERCONNECT SLICE_81/F0 SLICE_77/A0 (795:884:974)(795:884:974)) + (INTERCONNECT SLICE_81/F0 SLICE_78/D0 (584:647:710)(584:647:710)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_79/D0 (1658:1823:1989)(1658:1823:1989)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_81/C1 (1813:1997:2182)(1813:1997:2182)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_89/M1 (1957:2156:2355)(1957:2156:2355)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_99/B0 (1954:2154:2354)(1954:2154:2354)) + (INTERCONNECT SLICE_79/F1 SLICE_79/C0 (416:464:513)(416:464:513)) + (INTERCONNECT SLICE_79/F1 SLICE_81/A0 (530:591:652)(530:591:652)) + (INTERCONNECT SLICE_79/Q1 SLICE_100/C0 (1012:1128:1245)(1012:1128:1245)) + (INTERCONNECT SLICE_81/F1 SLICE_81/C0 (400:448:497)(400:448:497)) + (INTERCONNECT SLICE_82/F1 SLICE_82/B0 (560:628:696)(560:628:696)) + (INTERCONNECT SLICE_82/Q0 RD\[2\]_I/PADDO (646:731:817)(646:731:817)) + (INTERCONNECT SLICE_82/Q1 RD\[3\]_I/PADDO (1529:1758:1988)(1529:1758:1988)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_83/M1 (1117:1239:1361)(1117:1239:1361)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_91/D1 (999:1126:1253)(999:1126:1253)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_91/D0 (999:1126:1253)(999:1126:1253)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_96/B1 (1022:1152:1283)(1022:1152:1283)) + (INTERCONNECT MAin\[8\]_I/PADDI SLICE_83/M0 (1211:1335:1459)(1211:1335:1459)) + (INTERCONNECT MAin\[8\]_I/PADDI SLICE_96/B0 (1922:2112:2303)(1922:2112:2303)) + (INTERCONNECT SLICE_83/Q0 SLICE_96/C0 (723:805:887)(723:805:887)) + (INTERCONNECT SLICE_83/Q1 SLICE_91/B0 (1286:1416:1547)(1286:1416:1547)) + (INTERCONNECT SLICE_84/Q0 RD\[0\]_I/PADDO (1165:1345:1526)(1165:1345:1526)) + (INTERCONNECT SLICE_84/Q1 RD\[1\]_I/PADDO (1165:1345:1526)(1165:1345:1526)) + (INTERCONNECT SLICE_85/F1 SLICE_85/CE (544:603:663)(544:603:663)) + (INTERCONNECT SLICE_85/F1 SLICE_88/CE (1405:1538:1672)(1405:1538:1672)) + (INTERCONNECT SLICE_89/Q0 SLICE_98/D0 (1785:1946:2108)(1785:1946:2108)) + (INTERCONNECT SLICE_89/Q1 SLICE_99/A0 (1735:1889:2044)(1735:1889:2044)) + (INTERCONNECT CROW\[1\]_I/PADDI SLICE_90/M1 (2247:2476:2705)(2247:2476:2705)) + (INTERCONNECT CROW\[0\]_I/PADDI SLICE_90/M0 (1947:2141:2335)(1947:2141:2335)) + (INTERCONNECT SLICE_90/Q0 RBA\[0\]_I/PADDO (2469:2735:3001)(2469:2735:3001)) + (INTERCONNECT SLICE_90/Q1 RBA\[1\]_I/PADDO (1165:1345:1526)(1165:1345:1526)) + (INTERCONNECT SLICE_91/F0 RA\[9\]_I/PADDO (2530:2818:3107)(2530:2818:3107)) + (INTERCONNECT SLICE_91/F1 RDQMH_I/PADDO (2066:2303:2540)(2066:2303:2540)) + (INTERCONNECT SLICE_93/Q0 SLICE_100/B0 (1781:1942:2104)(1781:1942:2104)) + (INTERCONNECT SLICE_93/F1 RA\[1\]_I/PADDO (646:731:817)(646:731:817)) + (INTERCONNECT SLICE_96/F0 RA\[8\]_I/PADDO (2530:2818:3107)(2530:2818:3107)) + (INTERCONNECT SLICE_96/F1 RDQML_I/PADDO (1568:1777:1987)(1568:1777:1987)) + (INTERCONNECT SLICE_97/F0 RA\[3\]_I/PADDO (646:731:817)(646:731:817)) + (INTERCONNECT SLICE_97/F1 RA\[0\]_I/PADDO (1168:1345:1522)(1168:1345:1522)) + (INTERCONNECT SLICE_98/F0 RA\[4\]_I/PADDO (646:731:817)(646:731:817)) + (INTERCONNECT SLICE_98/F1 RA\[2\]_I/PADDO (1532:1758:1984)(1532:1758:1984)) + (INTERCONNECT SLICE_99/F0 RA\[5\]_I/PADDO (1971:2209:2448)(1971:2209:2448)) + (INTERCONNECT SLICE_99/F1 RA\[7\]_I/PADDO (1288:1474:1660)(1288:1474:1660)) + (INTERCONNECT SLICE_100/F1 RD\[0\]_I/PADDT (3328:3701:4074)(3328:3701:4074)) + (INTERCONNECT SLICE_100/F1 RD\[7\]_I/PADDT (2932:3268:3604)(2932:3268:3604)) + (INTERCONNECT SLICE_100/F1 RD\[6\]_I/PADDT (2932:3268:3604)(2932:3268:3604)) + (INTERCONNECT SLICE_100/F1 RD\[5\]_I/PADDT (3745:4139:4534)(3745:4139:4534)) + (INTERCONNECT SLICE_100/F1 RD\[4\]_I/PADDT (3745:4139:4534)(3745:4139:4534)) + (INTERCONNECT SLICE_100/F1 RD\[3\]_I/PADDT (2522:2837:3152)(2522:2837:3152)) + (INTERCONNECT SLICE_100/F1 RD\[2\]_I/PADDT (2522:2837:3152)(2522:2837:3152)) + (INTERCONNECT SLICE_100/F1 RD\[1\]_I/PADDT (1725:1981:2238)(1725:1981:2238)) + (INTERCONNECT SLICE_101/F1 RA\[6\]_I/PADDO (646:731:817)(646:731:817)) (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_I/PADDO (2942:3272:3602)(2942:3272:3602)) (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_I/PADDO (2508:2805:3103)(2508:2805:3103)) (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_I/PADDO (2508:2805:3103)(2508:2805:3103)) diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_vo.vo b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_vo.vo index 8233f24..66c3568 100644 --- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_vo.vo +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_vo.vo @@ -2,8 +2,8 @@ // Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454 // ldbanno -n Verilog -o RAM2GS_LCMXO640C_impl1_vo.vo -w -neg -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd -// Netlist created on Thu Sep 21 05:38:31 2023 -// Netlist written on Thu Sep 21 05:38:45 2023 +// Netlist created on Sat Jan 06 06:25:09 2024 +// Netlist written on Sat Jan 06 06:25:23 2024 // Design is for device LCMXO640C // Design is for package TQFP100 // Design is for performance grade 3 @@ -28,45 +28,48 @@ module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, \FS_cry[15] , \FS[15] , \FS[14] , \FS_cry[13] , \FS[13] , \FS[12] , \FS_cry[11] , \FS[11] , \FS[10] , \FS_cry[9] , \FS[9] , \FS[8] , \FS_cry[7] , \FS[7] , \FS[6] , \FS_cry[5] , \FS[5] , \FS[4] , - \FS_cry[3] , \FS[3] , \FS[2] , CmdEnable17_0_a2_4, N_147, - CmdEnable17_0_a2_3, \MAin_c[0] , ADSubmitted, C1WR_0_a2, CmdEnable17, - CmdEnable16, ADSubmitted_r, PHI2_c, CmdEnable16_0_a2_5, - CmdEnable16_0_a2_4, \MAin_c[1] , C1Submitted, C1Submitted_RNO, CO0, - \S[1] , \IS[3] , RASr2, N_177_i, Ready_0_sqmuxa_0_a3_2, CmdEnable, - un1_CMDWR, CmdEnable_s, \Din_c[5] , \Din_c[3] , N_128, N_152, LEDEN, - N_133, N_132, N_21_i, XOR8MEG18, CmdLEDEN, CmdSubmitted, PHI2r3, - PHI2r2, InitReady, CmdSubmitted_1_sqmuxa, N_460_0, N_136, N_43, - Cmdn8MEGEN, CmdEnable16_4, n8MEGEN, Cmdn8MEGEN_4_u_i_0, N_19_i, N_160, - N_155, nRRAS_5_u_i_0, \IS[0] , Ready, N_64_i_i, N_24, \IS[2] , - \IS[1] , N_60_i_i, N_56_i, N_159_i, N_159, N_61_i_i, RA10s_i, N_126, - UFMSDI_ens2_i_a2_4_2, N_51, InitReady3, N_461_0, UFMSDI_ens2_i_a0, - nCRAS_c, CBR, UFMSDO_c, N_70, N_33, LED_c, XOR8MEG, un1_Din_4, - \Din_c[6] , RA11_2, Ready_fast, \RA_c[11] , N_171, FWEr_fast, CASr2, - RCKEEN_8_u_1, RCKEEN_8_u_0_0, RCKEEN_8, PHI2r, RCKEEN, RASr, RASr3, - RCKE_2, RCKE_c, m18_0_a3_3, \S_0_i_o2[1] , N_165, N_462_0, - Ready_0_sqmuxa, N_463_0, nRRAS_0_sqmuxa, CmdUFMCLK, N_129, - UFMCLK_r_i_a2_2_2, N_139_i, UFMCLK_r_i_m4_xx_mm_1, nUFMCS15, UFMCLK_c, - UFMCLK_RNO, UFMSDI_r_xx_mm_1, UFMSDI_c, UFMSDI_RNO, \RowA[4] , - nRowColSel, \MAin_c[4] , \Din_c[4] , nCCAS_c, \RA_c[4] , \WRD[4] , - \WRD[5] , \Bank[5] , \Bank[2] , \Bank[6] , \Bank[7] , \Din_c[7] , - \WRD[6] , C1WR_0_a2_0_11, \WRD[7] , \Din_c[2] , \Din_c[0] , - \Din_c[1] , XOR8MEG_3_u_0_a3_2, XOR8MEG_3, N_69, N_31, N_151, N_41, - nRCAS_0_sqmuxa_1, g0_1, N_37_i, nRCAS_c, CASr3, RCKEEN_8_u_0_a2_1_out, - N_28_i_1, N_28_i, nRCS_c, N_24_i, nRRAS_c, CBR_fast, FWEr, m18_0_a2_1, - G_17_1, N_39_i, nRWE_c, N_179, nRowColSel_0_0, nUFMCS_c, - nUFMCS_s_0_N_5_i_N_2L1, nUFMCS_s_0_N_5_i, CmdUFMCS, N_95_5, N_95_3, - \RowA[0] , \RowA[1] , \MAin_c[5] , CmdUFMCLK_1_sqmuxa, \RowA[5] , - N_137_8, un1_FS_14_i_a2_0_1, N_137_6, un1_FS_13_i_a2_1, \Bank[0] , - C1WR_0_a2_0_10, \Bank[1] , \MAin_c[7] , \MAin_c[6] , C1WR_0_a2_0_4, - \Bank[3] , \Bank[4] , C1WR_0_a2_0_3, UFMSDI_ens2_i_o2_0_3, - \MAin_c[3] , \MAin_c[2] , \RowA[2] , \RowA[3] , CmdUFMSDI, CASr, - CmdEnable16_1, m6_0_a2_2, \WRD[0] , \WRD[1] , g4_0_0_0, \MAin_c[9] , - \MAin_c[8] , \RowA[8] , \RowA[9] , nFWE_c, \CROW_c[1] , \CROW_c[0] , - \RBA_c[0] , \RBA_c[1] , \WRD[2] , \WRD[3] , \RA_c[9] , RDQML_c, - RD_1_i, \RowA[6] , \RowA[7] , \RA_c[8] , RDQMH_c, \RA_c[0] , - \RA_c[1] , \RA_c[7] , \RA_c[2] , \RA_c[6] , \RA_c[3] , \RA_c[5] , - \RA_c[10] , \RD_in[0] , \RD_in[7] , \RD_in[6] , \RD_in[5] , - \RD_in[4] , \RD_in[3] , \RD_in[2] , \RD_in[1] , VCCI, GNDI_TSALL; + \FS_cry[3] , \FS[3] , \FS[2] , ADWR, C1WR, CmdEnable17, CmdEnable16, + N_183_i, ADSubmitted, ADSubmitted_r, PHI2_c, C1Submitted, N_121, + un1_CmdEnable20_0_a3_0_2, C1Submitted_RNO, un1_CmdEnable20_i, + CmdEnable16_0_a3_4, CmdEnable16_0_a3_5, CmdEnable, CmdEnable_0_sqmuxa, + CmdEnable_s, CmdLEDEN_4_u_i_a2_0_0, N_45, \Din_c[1] , CmdLEDEN, LEDEN, + CmdLEDEN_4_u_i_0, N_95, N_14_i, XOR8MEG18, PHI2r2, PHI2r3, InitReady, + CmdSubmitted, CmdSubmitted_1_sqmuxa, N_428_0, N_134, \Din_c[0] , + Cmdn8MEGEN, n8MEGEN, Cmdn8MEGEN_4_u_i_0, N_12_i, \IS[1] , \IS[0] , + \IS[2] , N_148, Ready, N_77_i_i, CASr2, N_160, CASr3, N_74_i_i, + N_69_i, N_153_i, \IS[3] , N_75_i_i, RA10s_i, UFMSDI_ens2_i_a2_4_2, + N_128, N_34, InitReady3, N_429_0, UFMSDI_ens2_i_a0, CBR, nCRAS_c, + UFMSDO_c, N_49, N_26, LED_c, N_151, \RA_c[10] , g3, \Din_c[6] , + \Din_c[7] , \Din_c[4] , XOR8MEG, RA11_2, Ready_fast, \RA_c[11] , N_36, + RCKEEN_8_u_0_a3_0_0, CO0, FWEr_fast, \S[1] , RCKEEN_8_u_0_1_1, + RCKEEN_8_u_0_0, RCKEEN_8, PHI2r, RCKEEN, RASr2, RCKE_c, RASr3, RASr, + RCKE_2, g0_i_a5_1, \S_0_i_o2[1] , Ready_0_sqmuxa_0_a3_2, N_430_0, + Ready_0_sqmuxa, N_431_0, nRRAS_0_sqmuxa, UFMCLK_r_i_a2_2_2, N_129, + CmdUFMCLK, N_137_i, UFMCLK_r_i_m4_xx_mm_1, UFMCLK_c, nUFMCS15, + UFMCLK_RNO, UFMSDI_c, UFMSDI_r_xx_mm_1, UFMSDI_RNO, N_94, CmdUFMSDI, + \Din_c[5] , nCCAS_c, \WRD[4] , \WRD[5] , FWEr, N_125, \WRD[6] , N_43, + \WRD[7] , N_163, XOR8MEG_3_u_0_a3_0_1, N_166, XOR8MEG_3, N_48, N_24, + un1_nRCAS_6_sqmuxa_i_0, G_1_0, G_1_1, nRCAS_0_sqmuxa_1, N_46_i, + nRCAS_c, CBR_fast, g0_i_a5_1_2, N_184, g0_i_0, N_143_i, nRCS_c, N_154, + nRRAS_5_u_i_0, N_142_i, nRRAS_c, m18_0_a2_1, G_17_1, N_144_i, nRWE_c, + N_112, nRowColSel_0_0, nRowColSel, nUFMCS_c, nUFMCS_s_0_N_5_i_N_2L1, + nUFMCS_s_0_N_5_i, m18_0_a3_3, CmdUFMCS, N_133_3, N_133_5, \MAin_c[3] , + \MAin_c[2] , \RowA[2] , \RowA[3] , g0_i_a5_2_1, N_9, + RCKEEN_8_u_0_1_a1_0, UFMSDI_ens2_i_o2_0_3, \MAin_c[1] , \MAin_c[0] , + \RowA[0] , \RowA[1] , CMDWR_2, nFWE_c, C1WR_7, CMDWR, + un1_FS_13_i_a2_9_4, un1_FS_13_i_a2_9_5, un1_FS_14_i_a2_0_1, + un1_FS_13_i_a2_1, \Din_c[3] , \MAin_c[7] , \MAin_c[6] , \RowA[6] , + \RowA[7] , N_156, N_180, N_122_5, CASr, \Din_c[2] , \Bank[6] , + \Bank[7] , \MAin_c[4] , C1WR_2_0, \Bank[0] , \Bank[1] , \Bank[2] , + \Bank[5] , un1_Bank_1_4, un1_Bank_1_5, ADWR_8, \MAin_c[5] , ADWR_8_2, + \Bank[3] , ADWR_8_4, m6_0_a2_2, \WRD[2] , \WRD[3] , \MAin_c[9] , + \MAin_c[8] , \RowA[8] , \RowA[9] , \WRD[0] , \WRD[1] , + CmdUFMCLK_1_sqmuxa, \RowA[4] , \RowA[5] , \CROW_c[1] , \CROW_c[0] , + \RBA_c[0] , \RBA_c[1] , \RA_c[9] , RDQMH_c, \Bank[4] , \RA_c[1] , + \RA_c[8] , RDQML_c, \RA_c[3] , \RA_c[0] , \RA_c[4] , \RA_c[2] , + \RA_c[5] , \RA_c[7] , RD_1_i, \RA_c[6] , \RD_in[0] , \RD_in[7] , + \RD_in[6] , \RD_in[5] , \RD_in[4] , \RD_in[3] , \RD_in[2] , + \RD_in[1] , VCCI, GNDI_TSALL; SLICE_0 SLICE_0( .A1(\FS[1] ), .A0(\FS[0] ), .CLK(RCLK_c), .Q0(\FS[0] ), .Q1(\FS[1] ), .FCO(\FS_cry[1] )); @@ -86,211 +89,230 @@ module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, .Q0(\FS[4] ), .Q1(\FS[5] ), .FCO(\FS_cry[5] )); SLICE_8 SLICE_8( .A1(\FS[3] ), .A0(\FS[2] ), .CLK(RCLK_c), .FCI(\FS_cry[1] ), .Q0(\FS[2] ), .Q1(\FS[3] ), .FCO(\FS_cry[3] )); - SLICE_9 SLICE_9( .D1(CmdEnable17_0_a2_4), .C1(N_147), - .B1(CmdEnable17_0_a2_3), .A1(\MAin_c[0] ), .D0(ADSubmitted), - .C0(C1WR_0_a2), .B0(CmdEnable17), .A0(CmdEnable16), .DI0(ADSubmitted_r), - .CLK(PHI2_c), .F0(ADSubmitted_r), .Q0(ADSubmitted), .F1(CmdEnable17)); - SLICE_14 SLICE_14( .C1(N_147), .B1(CmdEnable16_0_a2_5), - .A1(CmdEnable16_0_a2_4), .D0(CmdEnable16), .C0(N_147), .B0(\MAin_c[1] ), + SLICE_9 SLICE_9( .C1(ADWR), .B1(C1WR), .D0(CmdEnable17), .C0(CmdEnable16), + .B0(N_183_i), .A0(ADSubmitted), .DI0(ADSubmitted_r), .CLK(PHI2_c), + .F0(ADSubmitted_r), .Q0(ADSubmitted), .F1(N_183_i)); + SLICE_14 SLICE_14( .D1(C1Submitted), .C1(CmdEnable16), .B1(N_121), + .A1(un1_CmdEnable20_0_a3_0_2), .D0(CmdEnable16), .C0(ADWR), .B0(C1WR), .A0(C1Submitted), .DI0(C1Submitted_RNO), .CLK(PHI2_c), - .F0(C1Submitted_RNO), .Q0(C1Submitted), .F1(CmdEnable16)); - SLICE_19 SLICE_19( .D1(CO0), .C1(\S[1] ), .B1(\IS[3] ), .A1(RASr2), - .C0(\S[1] ), .A0(CO0), .DI0(N_177_i), .LSR(RASr2), .CLK(RCLK_c), - .F0(N_177_i), .Q0(CO0), .F1(Ready_0_sqmuxa_0_a3_2)); - SLICE_20 SLICE_20( .D1(CmdEnable), .A1(ADSubmitted), .D0(CmdEnable17), - .C0(C1Submitted), .B0(un1_CMDWR), .A0(CmdEnable), .DI0(CmdEnable_s), - .M0(CmdEnable16), .CLK(PHI2_c), .OFX0(CmdEnable_s), .Q0(CmdEnable)); - SLICE_21 SLICE_21( .D1(\Din_c[5] ), .C1(\Din_c[3] ), .B1(N_128), .D0(N_152), - .C0(LEDEN), .B0(N_133), .A0(N_132), .DI0(N_21_i), .CE(XOR8MEG18), - .CLK(PHI2_c), .F0(N_21_i), .Q0(CmdLEDEN), .F1(N_152)); - SLICE_22 SLICE_22( .D1(CmdSubmitted), .C1(PHI2r3), .B1(PHI2r2), - .A1(InitReady), .D0(CmdSubmitted_1_sqmuxa), .A0(CmdSubmitted), - .DI0(N_460_0), .CLK(PHI2_c), .F0(N_460_0), .Q0(CmdSubmitted), .F1(N_136)); - SLICE_26 SLICE_26( .D1(N_128), .C1(N_43), .B1(Cmdn8MEGEN), - .A1(CmdEnable16_4), .D0(n8MEGEN), .C0(Cmdn8MEGEN_4_u_i_0), .A0(N_152), - .DI0(N_19_i), .CE(XOR8MEG18), .CLK(PHI2_c), .F0(N_19_i), .Q0(Cmdn8MEGEN), + .F0(C1Submitted_RNO), .Q0(C1Submitted), .F1(un1_CmdEnable20_i)); + SLICE_20 SLICE_20( .D1(ADSubmitted), .C1(CmdEnable16_0_a3_4), .B1(C1WR), + .A1(CmdEnable16_0_a3_5), .D0(CmdEnable), .C0(CmdEnable17), + .B0(CmdEnable_0_sqmuxa), .A0(un1_CmdEnable20_i), .DI0(CmdEnable_s), + .CLK(PHI2_c), .F0(CmdEnable_s), .Q0(CmdEnable), .F1(CmdEnable_0_sqmuxa)); + SLICE_21 SLICE_21( .D1(CmdLEDEN_4_u_i_a2_0_0), .C1(N_45), .B1(\Din_c[1] ), + .A1(CmdLEDEN), .D0(LEDEN), .C0(CmdLEDEN_4_u_i_0), .B0(N_95), .DI0(N_14_i), + .CE(XOR8MEG18), .CLK(PHI2_c), .F0(N_14_i), .Q0(CmdLEDEN), + .F1(CmdLEDEN_4_u_i_0)); + SLICE_22 SLICE_22( .D1(PHI2r2), .C1(PHI2r3), .B1(InitReady), + .A1(CmdSubmitted), .C0(CmdSubmitted_1_sqmuxa), .A0(CmdSubmitted), + .DI0(N_428_0), .CLK(PHI2_c), .F0(N_428_0), .Q0(CmdSubmitted), .F1(N_134)); + SLICE_26 SLICE_26( .D1(N_45), .C1(\Din_c[0] ), .B1(CmdLEDEN_4_u_i_a2_0_0), + .A1(Cmdn8MEGEN), .D0(n8MEGEN), .C0(Cmdn8MEGEN_4_u_i_0), .A0(N_95), + .DI0(N_12_i), .CE(XOR8MEG18), .CLK(PHI2_c), .F0(N_12_i), .Q0(Cmdn8MEGEN), .F1(Cmdn8MEGEN_4_u_i_0)); - SLICE_29 SLICE_29( .D1(N_160), .C1(N_155), .B1(nRRAS_5_u_i_0), .A1(\IS[0] ), - .C0(N_155), .B0(Ready), .A0(\IS[0] ), .DI0(N_64_i_i), .CLK(RCLK_c), - .F0(N_64_i_i), .Q0(\IS[0] ), .F1(N_24)); - SLICE_30 SLICE_30( .D1(\IS[0] ), .C1(\IS[2] ), .A1(\IS[1] ), .D0(\IS[0] ), - .A0(\IS[1] ), .DI1(N_60_i_i), .DI0(N_56_i), .CE(N_159_i), .CLK(RCLK_c), - .F0(N_56_i), .Q0(\IS[1] ), .F1(N_60_i_i), .Q1(\IS[2] )); - SLICE_31 SLICE_31( .D1(\IS[2] ), .C1(N_159), .B1(\IS[1] ), .A1(\IS[3] ), - .D0(\IS[2] ), .C0(\IS[3] ), .B0(\IS[1] ), .A0(\IS[0] ), .DI0(N_61_i_i), - .CE(N_159_i), .CLK(RCLK_c), .F0(N_61_i_i), .Q0(\IS[3] ), .F1(RA10s_i)); - SLICE_32 SLICE_32( .D1(N_126), .C1(InitReady), .B1(UFMSDI_ens2_i_a2_4_2), - .A1(N_51), .D0(InitReady3), .A0(InitReady), .DI0(N_461_0), .CLK(RCLK_c), - .F0(N_461_0), .Q0(InitReady), .F1(UFMSDI_ens2_i_a0)); - SLICE_33 SLICE_33( .D1(LEDEN), .C1(nCRAS_c), .A1(CBR), .D0(InitReady), - .B0(CmdLEDEN), .A0(UFMSDO_c), .DI0(N_70), .CE(N_33), .CLK(RCLK_c), - .F0(N_70), .Q0(LEDEN), .F1(LED_c)); - SLICE_39 SLICE_39( .D1(XOR8MEG), .B1(un1_Din_4), .D0(XOR8MEG), - .B0(\Din_c[6] ), .A0(n8MEGEN), .DI0(RA11_2), .LSR(Ready_fast), - .CLK(PHI2_c), .F0(RA11_2), .Q0(\RA_c[11] ), .F1(N_171)); - SLICE_41 SLICE_41( .D1(CO0), .C1(FWEr_fast), .B1(CASr2), .A1(\S[1] ), - .D0(CBR), .C0(RCKEEN_8_u_1), .B0(Ready), .A0(RCKEEN_8_u_0_0), - .DI0(RCKEEN_8), .M1(PHI2r), .CLK(RCLK_c), .F0(RCKEEN_8), .Q0(RCKEEN), - .F1(RCKEEN_8_u_1), .Q1(PHI2r2)); - SLICE_42 SLICE_42( .D1(\IS[1] ), .C1(\IS[2] ), .B1(\IS[0] ), .A1(RASr2), - .D0(RASr), .C0(RASr3), .B0(RCKEEN), .A0(RASr2), .DI0(RCKE_2), .M1(PHI2_c), - .CLK(RCLK_c), .F0(RCKE_2), .Q0(RCKE_c), .F1(m18_0_a3_3), .Q1(PHI2r)); - SLICE_43 SLICE_43( .D1(Ready), .C1(\S_0_i_o2[1] ), .B1(RASr2), - .A1(InitReady), .D0(Ready), .C0(N_165), .B0(Ready_0_sqmuxa_0_a3_2), - .A0(InitReady), .DI0(N_462_0), .M1(PHI2r2), .CLK(RCLK_c), .F0(N_462_0), + SLICE_29 SLICE_29( .D1(\IS[1] ), .C1(\IS[0] ), .B1(\IS[2] ), .D0(N_148), + .C0(Ready), .A0(\IS[0] ), .DI0(N_77_i_i), .M1(CASr2), .CLK(RCLK_c), + .F0(N_77_i_i), .Q0(\IS[0] ), .F1(N_160), .Q1(CASr3)); + SLICE_30 SLICE_30( .D1(\IS[0] ), .B1(\IS[1] ), .A1(\IS[2] ), .D0(\IS[0] ), + .A0(\IS[1] ), .DI1(N_74_i_i), .DI0(N_69_i), .CE(N_153_i), .CLK(RCLK_c), + .F0(N_69_i), .Q0(\IS[1] ), .F1(N_74_i_i), .Q1(\IS[2] )); + SLICE_31 SLICE_31( .D1(Ready), .C1(N_148), .B1(\IS[3] ), .A1(\IS[0] ), + .D0(\IS[1] ), .C0(\IS[2] ), .B0(\IS[3] ), .A0(\IS[0] ), .DI0(N_75_i_i), + .CE(N_153_i), .CLK(RCLK_c), .F0(N_75_i_i), .Q0(\IS[3] ), .F1(RA10s_i)); + SLICE_32 SLICE_32( .D1(UFMSDI_ens2_i_a2_4_2), .C1(N_128), .B1(N_34), + .A1(InitReady), .B0(InitReady3), .A0(InitReady), .DI0(N_429_0), + .CLK(RCLK_c), .F0(N_429_0), .Q0(InitReady), .F1(UFMSDI_ens2_i_a0)); + SLICE_33 SLICE_33( .D1(CBR), .C1(nCRAS_c), .B1(Ready), .A1(LEDEN), + .D0(CmdLEDEN), .B0(UFMSDO_c), .A0(InitReady), .DI0(N_49), .CE(N_26), + .CLK(RCLK_c), .F0(N_49), .Q0(LEDEN), .F1(LED_c)); + SLICE_38 SLICE_38( .D1(\IS[0] ), .C1(\IS[1] ), .B1(\IS[3] ), .A1(\IS[2] ), + .C0(\IS[1] ), .A0(\IS[2] ), .DI0(N_151), .LSR(RA10s_i), .CLK(RCLK_c), + .F0(N_151), .Q0(\RA_c[10] ), .F1(g3)); + SLICE_39 SLICE_39( .C1(\Din_c[6] ), .B1(\Din_c[7] ), .A1(\Din_c[4] ), + .D0(n8MEGEN), .C0(\Din_c[6] ), .B0(XOR8MEG), .DI0(RA11_2), + .LSR(Ready_fast), .CLK(PHI2_c), .F0(RA11_2), .Q0(\RA_c[11] ), .F1(N_36)); + SLICE_41 SLICE_41( .D1(RCKEEN_8_u_0_a3_0_0), .C1(CO0), .B1(FWEr_fast), + .A1(\S[1] ), .D0(CBR), .C0(RCKEEN_8_u_0_1_1), .B0(RCKEEN_8_u_0_0), + .A0(Ready), .DI0(RCKEEN_8), .M1(PHI2r), .CLK(RCLK_c), .F0(RCKEEN_8), + .Q0(RCKEEN), .F1(RCKEEN_8_u_0_1_1), .Q1(PHI2r2)); + SLICE_42 SLICE_42( .D1(RASr2), .C1(Ready), .A1(RCKE_c), .D0(RASr2), + .C0(RASr3), .B0(RCKEEN), .A0(RASr), .DI0(RCKE_2), .M1(PHI2_c), + .CLK(RCLK_c), .F0(RCKE_2), .Q0(RCKE_c), .F1(g0_i_a5_1), .Q1(PHI2r)); + SLICE_43 SLICE_43( .D1(InitReady), .C1(Ready), .B1(\S_0_i_o2[1] ), + .A1(RASr2), .D0(InitReady), .C0(N_160), .B0(Ready_0_sqmuxa_0_a3_2), + .A0(Ready), .DI0(N_430_0), .M1(PHI2r2), .CLK(RCLK_c), .F0(N_430_0), .Q0(Ready), .F1(RCKEEN_8_u_0_0), .Q1(PHI2r3)); - SLICE_44 SLICE_44( .D1(Ready), .C1(N_165), .B1(Ready_0_sqmuxa_0_a3_2), - .A1(InitReady), .B0(Ready_0_sqmuxa), .A0(Ready_fast), .DI0(N_463_0), - .M1(nCRAS_c), .CLK(RCLK_c), .F0(N_463_0), .Q0(Ready_fast), - .F1(Ready_0_sqmuxa), .Q1(RASr)); - SLICE_50 SLICE_50( .D1(Ready), .C1(CO0), .A1(\S[1] ), .C0(CO0), .A0(\S[1] ), + SLICE_44 SLICE_44( .D1(N_160), .C1(Ready_0_sqmuxa_0_a3_2), .B1(InitReady), + .A1(Ready), .C0(Ready_0_sqmuxa), .A0(Ready_fast), .DI0(N_431_0), + .M1(RASr2), .CLK(RCLK_c), .F0(N_431_0), .Q0(Ready_fast), + .F1(Ready_0_sqmuxa), .Q1(RASr3)); + SLICE_50 SLICE_50( .D1(CO0), .C1(Ready), .B1(\S[1] ), .D0(CO0), .A0(\S[1] ), .DI0(\S_0_i_o2[1] ), .LSR(RASr2), .CLK(RCLK_c), .F0(\S_0_i_o2[1] ), .Q0(\S[1] ), .F1(nRRAS_0_sqmuxa)); - SLICE_51 SLICE_51( .D1(CmdUFMCLK), .C1(InitReady), .B1(N_129), - .A1(UFMCLK_r_i_a2_2_2), .D0(N_139_i), .C0(UFMCLK_r_i_m4_xx_mm_1), - .B0(nUFMCS15), .A0(UFMCLK_c), .DI0(UFMCLK_RNO), .M1(RASr), .CLK(RCLK_c), - .F0(UFMCLK_RNO), .Q0(UFMCLK_c), .F1(UFMCLK_r_i_m4_xx_mm_1), .Q1(RASr2)); - SLICE_52 SLICE_52( .D1(PHI2r3), .C1(InitReady), .B1(PHI2r2), - .A1(CmdSubmitted), .D0(UFMSDI_r_xx_mm_1), .C0(N_139_i), .B0(UFMSDI_c), - .A0(nUFMCS15), .DI0(UFMSDI_RNO), .M1(RASr2), .CLK(RCLK_c), .F0(UFMSDI_RNO), - .Q0(UFMSDI_c), .F1(N_139_i), .Q1(RASr3)); - SLICE_55 SLICE_55( .D0(\RowA[4] ), .B0(nRowColSel), .A0(\MAin_c[4] ), - .M1(\Din_c[5] ), .M0(\Din_c[4] ), .CLK(nCCAS_c), .F0(\RA_c[4] ), + SLICE_51 SLICE_51( .D1(UFMCLK_r_i_a2_2_2), .C1(InitReady), .B1(N_129), + .A1(CmdUFMCLK), .D0(N_137_i), .C0(UFMCLK_r_i_m4_xx_mm_1), .B0(UFMCLK_c), + .A0(nUFMCS15), .DI0(UFMCLK_RNO), .CLK(RCLK_c), .F0(UFMCLK_RNO), + .Q0(UFMCLK_c), .F1(UFMCLK_r_i_m4_xx_mm_1)); + SLICE_52 SLICE_52( .D1(CmdSubmitted), .C1(PHI2r2), .B1(PHI2r3), + .A1(InitReady), .D0(UFMSDI_c), .C0(N_137_i), .B0(nUFMCS15), + .A0(UFMSDI_r_xx_mm_1), .DI0(UFMSDI_RNO), .CLK(RCLK_c), .F0(UFMSDI_RNO), + .Q0(UFMSDI_c), .F1(N_137_i)); + SLICE_55 SLICE_55( .D0(N_94), .C0(CmdUFMSDI), .A0(UFMSDI_ens2_i_a0), + .M1(\Din_c[5] ), .M0(\Din_c[4] ), .CLK(nCCAS_c), .F0(UFMSDI_r_xx_mm_1), .Q0(\WRD[4] ), .Q1(\WRD[5] )); - SLICE_56 SLICE_56( .D1(\Bank[5] ), .C1(\Bank[2] ), .B1(\Bank[6] ), - .A1(\Bank[7] ), .D0(\FS[5] ), .C0(\FS[9] ), .A0(\FS[7] ), .M1(\Din_c[7] ), - .M0(\Din_c[6] ), .CLK(nCCAS_c), .F0(N_126), .Q0(\WRD[6] ), - .F1(C1WR_0_a2_0_11), .Q1(\WRD[7] )); - SLICE_57 SLICE_57( .D1(un1_Din_4), .C1(\Din_c[3] ), .B1(\Din_c[2] ), - .A1(\Din_c[0] ), .D0(\Din_c[1] ), .C0(XOR8MEG_3_u_0_a3_2), .B0(LEDEN), - .A0(N_171), .DI0(XOR8MEG_3), .CE(XOR8MEG18), .CLK(PHI2_c), .F0(XOR8MEG_3), - .Q0(XOR8MEG), .F1(XOR8MEG_3_u_0_a3_2)); - SLICE_58 SLICE_58( .D1(N_51), .C1(\FS[8] ), .A1(InitReady), .D0(UFMSDO_c), - .B0(Cmdn8MEGEN), .A0(InitReady), .DI0(N_69), .CE(N_31), .CLK(RCLK_c), - .F0(N_69), .Q0(n8MEGEN), .F1(N_151)); - SLICE_59 SLICE_59( .D1(Ready), .C1(\S[1] ), .B1(N_155), .A1(N_160), - .D0(N_41), .C0(nRCAS_0_sqmuxa_1), .B0(\S[1] ), .A0(g0_1), .DI0(N_37_i), - .CLK(RCLK_c), .F0(N_37_i), .Q0(nRCAS_c), .F1(N_41)); - SLICE_60 SLICE_60( .D1(CASr3), .C1(CO0), .B1(FWEr_fast), .A1(CASr2), - .D0(CBR), .C0(RCKEEN_8_u_0_a2_1_out), .B0(N_24), .A0(N_28_i_1), - .DI0(N_28_i), .CLK(RCLK_c), .F0(N_28_i), .Q0(nRCS_c), .F1(N_28_i_1)); + SLICE_56 SLICE_56( .D1(\FS[4] ), .C1(\FS[11] ), .C0(CO0), .A0(FWEr), + .M1(\Din_c[7] ), .M0(\Din_c[6] ), .CLK(nCCAS_c), .F0(N_125), .Q0(\WRD[6] ), + .F1(N_43), .Q1(\WRD[7] )); + SLICE_57 SLICE_57( .C1(N_163), .A1(XOR8MEG), .D0(\Din_c[1] ), + .C0(XOR8MEG_3_u_0_a3_0_1), .B0(N_166), .A0(LEDEN), .DI0(XOR8MEG_3), + .CE(XOR8MEG18), .CLK(PHI2_c), .F0(XOR8MEG_3), .Q0(XOR8MEG), .F1(N_166)); + SLICE_58 SLICE_58( .D1(N_128), .C1(InitReady), .B1(\FS[8] ), .D0(UFMSDO_c), + .C0(InitReady), .A0(Cmdn8MEGEN), .DI0(N_48), .CE(N_24), .CLK(RCLK_c), + .F0(N_48), .Q0(n8MEGEN), .F1(N_94)); + SLICE_59 SLICE_59( .D1(CBR), .C1(\S[1] ), .B1(un1_nRCAS_6_sqmuxa_i_0), + .D0(G_1_0), .C0(G_1_1), .B0(\S[1] ), .A0(nRCAS_0_sqmuxa_1), .DI0(N_46_i), + .CLK(RCLK_c), .F0(N_46_i), .Q0(nRCAS_c), .F1(G_1_1)); + SLICE_60 SLICE_60( .C1(Ready), .B1(\S[1] ), .A1(CBR_fast), .D0(g0_i_a5_1_2), + .C0(N_184), .B0(N_125), .A0(g0_i_0), .DI0(N_143_i), .CLK(RCLK_c), + .F0(N_143_i), .Q0(nRCS_c), .F1(N_184)); SLICE_61 SLICE_61( .D1(\S_0_i_o2[1] ), .C1(Ready), .B1(RASr2), .A1(RCKE_c), - .D0(N_160), .C0(N_155), .B0(nRRAS_5_u_i_0), .A0(\IS[0] ), .DI0(N_24_i), - .CLK(RCLK_c), .F0(N_24_i), .Q0(nRRAS_c), .F1(nRRAS_5_u_i_0)); - SLICE_62 SLICE_62( .D1(CBR_fast), .C1(\S_0_i_o2[1] ), .B1(Ready), .A1(RASr2), + .D0(N_148), .C0(N_154), .B0(\IS[0] ), .A0(nRRAS_5_u_i_0), .DI0(N_142_i), + .CLK(RCLK_c), .F0(N_142_i), .Q0(nRRAS_c), .F1(nRRAS_5_u_i_0)); + SLICE_62 SLICE_62( .D1(RASr2), .C1(\S_0_i_o2[1] ), .B1(Ready), .A1(CBR_fast), .D0(FWEr), .C0(m18_0_a2_1), .B0(nRCAS_0_sqmuxa_1), .A0(G_17_1), - .DI0(N_39_i), .CLK(RCLK_c), .F0(N_39_i), .Q0(nRWE_c), + .DI0(N_144_i), .CLK(RCLK_c), .F0(N_144_i), .Q0(nRWE_c), .F1(nRCAS_0_sqmuxa_1)); - SLICE_63 SLICE_63( .D1(CASr3), .C1(Ready), .B1(FWEr), .A1(CBR), .D0(N_179), - .C0(Ready), .B0(CO0), .A0(\S[1] ), .DI0(nRowColSel_0_0), + SLICE_63 SLICE_63( .D1(Ready), .C1(CASr3), .B1(FWEr), .A1(CBR), .D0(\S[1] ), + .C0(N_112), .B0(CO0), .A0(Ready), .DI0(nRowColSel_0_0), .LSR(nRRAS_0_sqmuxa), .CLK(RCLK_c), .F0(nRowColSel_0_0), .Q0(nRowColSel), - .F1(N_179)); - SLICE_64 SLICE_64( .D1(\FS[10] ), .C1(N_51), .B1(\FS[11] ), .A1(InitReady), - .D0(nUFMCS_c), .C0(nUFMCS_s_0_N_5_i_N_2L1), .B0(nUFMCS15), .A0(N_139_i), + .F1(N_112)); + SLICE_64 SLICE_64( .D1(\FS[11] ), .C1(\FS[10] ), .B1(N_128), .A1(InitReady), + .D0(nUFMCS_c), .C0(nUFMCS15), .B0(nUFMCS_s_0_N_5_i_N_2L1), .A0(N_137_i), .DI0(nUFMCS_s_0_N_5_i), .CLK(RCLK_c), .F0(nUFMCS_s_0_N_5_i), .Q0(nUFMCS_c), .F1(nUFMCS15)); - nRWE_RNO_1_SLICE_65 \nRWE_RNO_1/SLICE_65 ( .D1(RASr2), .C1(RCKE_c), .B1(CO0), - .A1(\S[1] ), .D0(\S[1] ), .C0(m18_0_a3_3), .B0(CO0), .A0(InitReady), - .M0(Ready), .OFX0(m18_0_a2_1)); - SLICE_66 SLICE_66( .C1(InitReady), .B1(CmdUFMCS), .A1(UFMCLK_r_i_a2_2_2), - .D0(N_95_5), .C0(InitReady), .B0(\FS[16] ), .A0(N_95_3), .M1(\MAin_c[1] ), - .M0(\MAin_c[0] ), .LSR(Ready_fast), .CLK(nCRAS_c), .F0(UFMCLK_r_i_a2_2_2), - .Q0(\RowA[0] ), .F1(nUFMCS_s_0_N_5_i_N_2L1), .Q1(\RowA[1] )); - SLICE_67 SLICE_67( .D1(\Din_c[5] ), .C1(XOR8MEG18), .B1(\Din_c[3] ), - .A1(N_128), .D0(\MAin_c[1] ), .C0(\MAin_c[0] ), .B0(CmdEnable), .A0(N_147), - .M1(\MAin_c[5] ), .M0(\MAin_c[4] ), .LSR(Ready_fast), .CLK(nCRAS_c), - .F0(XOR8MEG18), .Q0(\RowA[4] ), .F1(CmdUFMCLK_1_sqmuxa), .Q1(\RowA[5] )); - SLICE_68 SLICE_68( .D1(\FS[3] ), .C1(\FS[0] ), .B1(\FS[2] ), .A1(\FS[5] ), - .D0(N_136), .C0(N_137_8), .B0(un1_FS_14_i_a2_0_1), .A0(N_137_6), .F0(N_31), - .F1(un1_FS_14_i_a2_0_1)); - SLICE_69 SLICE_69( .D1(\FS[3] ), .C1(\FS[0] ), .B1(\FS[2] ), .A1(\FS[5] ), - .D0(N_137_8), .C0(un1_FS_13_i_a2_1), .B0(N_136), .A0(N_137_6), .F0(N_33), - .F1(un1_FS_13_i_a2_1)); - SLICE_70 SLICE_70( .D1(\Bank[0] ), .C1(C1WR_0_a2_0_10), .B1(C1WR_0_a2_0_11), - .A1(\Bank[1] ), .C0(\MAin_c[1] ), .B0(N_147), .M1(\Din_c[1] ), - .M0(\Din_c[0] ), .CLK(PHI2_c), .F0(C1WR_0_a2), .Q0(\Bank[0] ), .F1(N_147), - .Q1(\Bank[1] )); - SLICE_71 SLICE_71( .D1(\MAin_c[5] ), .C1(\MAin_c[7] ), .B1(\MAin_c[6] ), - .A1(\MAin_c[4] ), .D0(C1WR_0_a2_0_4), .C0(\Bank[3] ), .B0(\Bank[4] ), - .A0(C1WR_0_a2_0_3), .M1(\Din_c[3] ), .M0(\Din_c[2] ), .CLK(PHI2_c), - .F0(C1WR_0_a2_0_10), .Q0(\Bank[2] ), .F1(C1WR_0_a2_0_4), .Q1(\Bank[3] )); - SLICE_72 SLICE_72( .D1(UFMSDI_ens2_i_o2_0_3), .C1(\FS[16] ), .A1(\FS[12] ), - .D0(\FS[1] ), .C0(N_51), .B0(\FS[11] ), .A0(\FS[4] ), .M1(\MAin_c[3] ), - .M0(\MAin_c[2] ), .LSR(Ready_fast), .CLK(nCRAS_c), .F0(N_129), - .Q0(\RowA[2] ), .F1(N_51), .Q1(\RowA[3] )); - SLICE_73 SLICE_73( .D1(\S[1] ), .C1(RASr2), .B1(CO0), .A1(InitReady), - .B0(N_155), .A0(Ready), .M1(\Din_c[2] ), .M0(\Din_c[1] ), - .CE(CmdUFMCLK_1_sqmuxa), .CLK(PHI2_c), .F0(N_159), .Q0(CmdUFMCLK), - .F1(N_155), .Q1(CmdUFMCS)); - SLICE_74 SLICE_74( .D1(\FS[14] ), .B1(\FS[11] ), .D0(\FS[16] ), .C0(N_95_3), - .B0(\FS[10] ), .A0(N_95_5), .M0(\Din_c[0] ), .CE(CmdUFMCLK_1_sqmuxa), - .CLK(PHI2_c), .F0(InitReady3), .Q0(CmdUFMSDI), .F1(N_95_3)); - SLICE_75 SLICE_75( .C1(\Din_c[4] ), .B1(\Din_c[7] ), .A1(\Din_c[6] ), - .D0(\Din_c[1] ), .C0(N_128), .A0(\Din_c[5] ), .M1(CASr), .M0(nCCAS_c), - .CLK(RCLK_c), .F0(N_133), .Q0(CASr), .F1(N_128), .Q1(CASr2)); - SLICE_76 SLICE_76( .D1(\Din_c[5] ), .B1(\Din_c[0] ), .D0(\MAin_c[0] ), - .C0(CmdEnable16_4), .B0(\Din_c[1] ), .A0(\Din_c[3] ), .M1(\Din_c[5] ), - .M0(\Din_c[4] ), .CLK(PHI2_c), .F0(CmdEnable16_0_a2_4), .Q0(\Bank[4] ), - .F1(CmdEnable16_4), .Q1(\Bank[5] )); - SLICE_77 SLICE_77( .C1(\Din_c[7] ), .A1(\Din_c[4] ), .D0(\MAin_c[1] ), - .C0(CmdEnable16_1), .B0(\Din_c[6] ), .A0(\Din_c[2] ), .M1(\Din_c[7] ), - .M0(\Din_c[6] ), .CLK(PHI2_c), .F0(CmdEnable16_0_a2_5), .Q0(\Bank[6] ), - .F1(CmdEnable16_1), .Q1(\Bank[7] )); - SLICE_78 SLICE_78( .C1(\Din_c[3] ), .B1(\Din_c[5] ), .D0(\MAin_c[1] ), - .C0(\Din_c[6] ), .B0(N_43), .A0(\Din_c[2] ), .M1(nCCAS_c), .M0(nCCAS_c), - .CLK(nCRAS_c), .F0(CmdEnable17_0_a2_4), .Q0(CBR), .F1(N_43), .Q1(CBR_fast)); - SLICE_79 SLICE_79( .D1(CASr3), .C1(Ready), .B1(CASr2), .D0(CO0), - .C0(m6_0_a2_2), .B0(CBR), .A0(\S[1] ), .M1(\Din_c[1] ), .M0(\Din_c[0] ), - .CLK(nCCAS_c), .F0(G_17_1), .Q0(\WRD[0] ), .F1(m6_0_a2_2), .Q1(\WRD[1] )); - SLICE_80 SLICE_80( .C1(CASr2), .B1(CASr3), .D0(FWEr), .C0(CBR_fast), - .B0(g4_0_0_0), .A0(CO0), .M1(\MAin_c[9] ), .M0(\MAin_c[8] ), - .LSR(Ready_fast), .CLK(nCRAS_c), .F0(g0_1), .Q0(\RowA[8] ), .F1(g4_0_0_0), + nRWE_RNO_1_SLICE_65 \nRWE_RNO_1/SLICE_65 ( .D1(RASr2), .C1(\S[1] ), + .B1(RCKE_c), .A1(CO0), .D0(m18_0_a3_3), .C0(\S[1] ), .B0(InitReady), + .A0(CO0), .M0(Ready), .OFX0(m18_0_a2_1)); + SLICE_66 SLICE_66( .D1(RASr2), .C1(InitReady), .B1(\S[1] ), .A1(CO0), + .D0(Ready), .C0(N_148), .B0(\S[1] ), .A0(N_154), + .F0(un1_nRCAS_6_sqmuxa_i_0), .F1(N_148)); + SLICE_67 SLICE_67( .D1(CmdUFMCS), .C1(InitReady), .B1(UFMCLK_r_i_a2_2_2), + .D0(N_133_3), .C0(InitReady), .B0(N_133_5), .A0(\FS[13] ), + .M1(\MAin_c[3] ), .M0(\MAin_c[2] ), .LSR(Ready_fast), .CLK(nCRAS_c), + .F0(UFMCLK_r_i_a2_2_2), .Q0(\RowA[2] ), .F1(nUFMCS_s_0_N_5_i_N_2L1), + .Q1(\RowA[3] )); + SLICE_68 SLICE_68( .D1(g0_i_a5_2_1), .C1(RASr2), .B1(CO0), .A1(g3), + .D0(\S[1] ), .C0(N_9), .B0(g0_i_a5_1), .A0(CO0), .M0(RASr2), + .LSR(RCKEEN_8_u_0_1_a1_0), .CLK(RCLK_c), .F0(g0_i_0), .Q0(CO0), .F1(N_9)); + SLICE_69 SLICE_69( .D1(\FS[16] ), .B1(\FS[13] ), .A1(UFMSDI_ens2_i_o2_0_3), + .D0(\FS[1] ), .C0(\FS[4] ), .B0(N_128), .A0(\FS[11] ), .M1(\MAin_c[1] ), + .M0(\MAin_c[0] ), .LSR(Ready_fast), .CLK(nCRAS_c), .F0(N_129), + .Q0(\RowA[0] ), .F1(N_128), .Q1(\RowA[1] )); + SLICE_70 SLICE_70( .D1(CMDWR_2), .C1(nFWE_c), .B1(\MAin_c[0] ), .A1(C1WR_7), + .C0(CMDWR), .B0(C1WR), .A0(ADWR), .F0(N_121), .F1(CMDWR)); + SLICE_71 SLICE_71( .D1(N_43), .C1(\FS[5] ), .B1(un1_FS_13_i_a2_9_4), + .A1(un1_FS_13_i_a2_9_5), .C0(un1_FS_14_i_a2_0_1), .B0(N_94), .A0(N_134), + .F0(N_24), .F1(un1_FS_14_i_a2_0_1)); + SLICE_72 SLICE_72( .D1(N_43), .C1(un1_FS_13_i_a2_9_5), + .B1(un1_FS_13_i_a2_9_4), .A1(\FS[5] ), .D0(un1_FS_13_i_a2_1), .C0(N_134), + .B0(N_94), .F0(N_26), .F1(un1_FS_13_i_a2_1)); + SLICE_73 SLICE_73( .D1(N_36), .C1(\Din_c[3] ), .B1(\Din_c[5] ), + .A1(XOR8MEG18), .D0(CMDWR), .C0(CmdEnable), .M1(\MAin_c[7] ), + .M0(\MAin_c[6] ), .LSR(Ready_fast), .CLK(nCRAS_c), .F0(XOR8MEG18), + .Q0(\RowA[6] ), .F1(CmdSubmitted_1_sqmuxa), .Q1(\RowA[7] )); + SLICE_74 SLICE_74( .C1(\Din_c[6] ), .A1(\Din_c[4] ), .D0(N_156), .C0(ADWR), + .B0(N_180), .A0(N_122_5), .M1(CASr), .M0(nCCAS_c), .CLK(RCLK_c), + .F0(CmdEnable17), .Q0(CASr), .F1(N_156), .Q1(CASr2)); + SLICE_75 SLICE_75( .D1(\Din_c[4] ), .C1(\Din_c[1] ), .B1(\Din_c[2] ), + .A1(\Din_c[3] ), .C0(CmdEnable16_0_a3_4), .B0(C1WR), + .A0(CmdEnable16_0_a3_5), .M1(\Din_c[7] ), .M0(\Din_c[6] ), .CLK(PHI2_c), + .F0(CmdEnable16), .Q0(\Bank[6] ), .F1(CmdEnable16_0_a3_5), .Q1(\Bank[7] )); + SLICE_76 SLICE_76( .D1(\MAin_c[4] ), .C1(\MAin_c[0] ), .B1(\MAin_c[3] ), + .A1(\MAin_c[1] ), .D0(C1WR_7), .C0(C1WR_2_0), .B0(nFWE_c), + .A0(\MAin_c[2] ), .M1(\Din_c[1] ), .M0(\Din_c[0] ), .CLK(PHI2_c), + .F0(C1WR), .Q0(\Bank[0] ), .F1(C1WR_2_0), .Q1(\Bank[1] )); + SLICE_77 SLICE_77( .D1(\Bank[6] ), .C1(\Bank[2] ), .B1(\Bank[7] ), + .A1(\Bank[5] ), .D0(nFWE_c), .C0(un1_Bank_1_4), .B0(un1_Bank_1_5), + .A0(ADWR_8), .F0(ADWR), .F1(un1_Bank_1_5)); + SLICE_78 SLICE_78( .D1(\Din_c[0] ), .A1(\Din_c[2] ), .D0(ADWR_8), .C0(N_180), + .B0(N_156), .A0(N_122_5), .F0(un1_CmdEnable20_0_a3_0_2), .F1(N_180)); + SLICE_79 SLICE_79( .C1(\MAin_c[6] ), .A1(\MAin_c[7] ), .D0(\MAin_c[5] ), + .C0(ADWR_8_2), .B0(un1_Bank_1_5), .A0(un1_Bank_1_4), .M1(\Din_c[3] ), + .M0(\Din_c[2] ), .CLK(PHI2_c), .F0(C1WR_7), .Q0(\Bank[2] ), .F1(ADWR_8_2), + .Q1(\Bank[3] )); + SLICE_80 SLICE_80( .C1(\FS[17] ), .B1(\FS[11] ), .D0(N_133_5), .C0(N_133_3), + .B0(\FS[10] ), .A0(\FS[13] ), .F0(InitReady3), .F1(N_133_3)); + SLICE_81 SLICE_81( .D1(\MAin_c[4] ), .C1(\MAin_c[5] ), .B1(\MAin_c[0] ), + .A1(\MAin_c[1] ), .D0(\MAin_c[3] ), .C0(ADWR_8_4), .B0(\MAin_c[2] ), + .A0(ADWR_8_2), .F0(ADWR_8), .F1(ADWR_8_4)); + SLICE_82 SLICE_82( .D1(CASr2), .B1(CASr3), .A1(Ready), .D0(CO0), .C0(\S[1] ), + .B0(m6_0_a2_2), .A0(CBR_fast), .M1(\Din_c[3] ), .M0(\Din_c[2] ), + .CLK(nCCAS_c), .F0(G_17_1), .Q0(\WRD[2] ), .F1(m6_0_a2_2), .Q1(\WRD[3] )); + SLICE_83 SLICE_83( .D1(\Din_c[7] ), .C1(\Din_c[4] ), .B1(\Din_c[6] ), + .A1(\Din_c[5] ), .D0(\Din_c[2] ), .C0(N_163), .B0(\Din_c[3] ), + .A0(\Din_c[0] ), .M1(\MAin_c[9] ), .M0(\MAin_c[8] ), .LSR(Ready_fast), + .CLK(nCRAS_c), .F0(XOR8MEG_3_u_0_a3_0_1), .Q0(\RowA[8] ), .F1(N_163), .Q1(\RowA[9] )); - SLICE_81 SLICE_81( .D1(\FS[14] ), .C1(\FS[17] ), .B1(\FS[15] ), - .A1(\FS[13] ), .D0(\FS[12] ), .C0(\FS[17] ), .B0(\FS[15] ), .A0(\FS[13] ), - .M1(nFWE_c), .M0(nFWE_c), .CLK(nCRAS_c), .F0(N_95_5), .Q0(FWEr), - .F1(UFMSDI_ens2_i_o2_0_3), .Q1(FWEr_fast)); - SLICE_82 SLICE_82( .D1(\Din_c[5] ), .C1(CmdLEDEN), .B1(N_128), - .A1(\Din_c[3] ), .D0(\Din_c[5] ), .C0(XOR8MEG18), .B0(N_128), - .A0(\Din_c[3] ), .M0(CASr2), .CLK(RCLK_c), .F0(CmdSubmitted_1_sqmuxa), - .Q0(CASr3), .F1(N_132)); - SLICE_83 SLICE_83( .C1(\IS[2] ), .B1(\IS[3] ), .A1(\IS[1] ), .D0(\IS[0] ), - .C0(\IS[2] ), .A0(\IS[1] ), .M1(\CROW_c[1] ), .M0(\CROW_c[0] ), - .LSR(Ready_fast), .CLK(nCRAS_c), .F0(N_165), .Q0(\RBA_c[0] ), .F1(N_160), + SLICE_84 SLICE_84( .D1(FWEr_fast), .C1(CASr2), .B1(CO0), .A1(CASr3), + .D0(FWEr_fast), .C0(CASr2), .B0(CO0), .A0(CASr3), .M1(\Din_c[1] ), + .M0(\Din_c[0] ), .CLK(nCCAS_c), .F0(g0_i_a5_1_2), .Q0(\WRD[0] ), + .F1(G_1_0), .Q1(\WRD[1] )); + SLICE_85 SLICE_85( .D1(\Din_c[3] ), .C1(XOR8MEG18), .B1(N_36), + .A1(\Din_c[5] ), .D0(\Din_c[3] ), .B0(N_36), .A0(\Din_c[5] ), + .M1(\Din_c[2] ), .M0(\Din_c[1] ), .CE(CmdUFMCLK_1_sqmuxa), .CLK(PHI2_c), + .F0(N_95), .Q0(CmdUFMCLK), .F1(CmdUFMCLK_1_sqmuxa), .Q1(CmdUFMCS)); + SLICE_86 SLICE_86( .D1(\FS[17] ), .C1(\FS[14] ), .B1(\FS[15] ), + .A1(\FS[12] ), .D0(\FS[14] ), .C0(\FS[16] ), .B0(\FS[15] ), .A0(\FS[12] ), + .F0(N_133_5), .F1(UFMSDI_ens2_i_o2_0_3)); + SLICE_87 SLICE_87( .D1(\Din_c[6] ), .C1(\Din_c[4] ), .B1(\Din_c[7] ), + .A1(\Din_c[5] ), .D0(\Din_c[6] ), .C0(\Din_c[0] ), .B0(\Din_c[7] ), + .A0(\Din_c[5] ), .M1(nCCAS_c), .M0(nCCAS_c), .CLK(nCRAS_c), + .F0(CmdEnable16_0_a3_4), .Q0(CBR), .F1(CmdLEDEN_4_u_i_a2_0_0), + .Q1(CBR_fast)); + SLICE_88 SLICE_88( .D1(\Din_c[7] ), .C1(\Din_c[1] ), .B1(\Din_c[3] ), + .A1(\Din_c[5] ), .D0(\Din_c[3] ), .B0(N_36), .A0(\Din_c[5] ), + .M0(\Din_c[0] ), .CE(CmdUFMCLK_1_sqmuxa), .CLK(PHI2_c), .F0(N_45), + .Q0(CmdUFMSDI), .F1(N_122_5)); + SLICE_89 SLICE_89( .D1(\FS[7] ), .C1(\FS[1] ), .B1(\FS[10] ), .A1(\FS[9] ), + .D0(\FS[7] ), .C0(\FS[5] ), .A0(\FS[9] ), .M1(\MAin_c[5] ), + .M0(\MAin_c[4] ), .LSR(Ready_fast), .CLK(nCRAS_c), .F0(N_34), + .Q0(\RowA[4] ), .F1(un1_FS_13_i_a2_9_5), .Q1(\RowA[5] )); + SLICE_90 SLICE_90( .C1(\S[1] ), .A1(CO0), .C0(\S[1] ), .B0(CASr2), .A0(CO0), + .M1(\CROW_c[1] ), .M0(\CROW_c[0] ), .LSR(Ready_fast), .CLK(nCRAS_c), + .F0(RCKEEN_8_u_0_a3_0_0), .Q0(\RBA_c[0] ), .F1(RCKEEN_8_u_0_1_a1_0), .Q1(\RBA_c[1] )); - SLICE_84 SLICE_84( .D1(\FS[8] ), .C1(\FS[10] ), .B1(\FS[11] ), .A1(\FS[6] ), - .D0(\FS[7] ), .C0(\FS[1] ), .B0(\FS[10] ), .A0(\FS[6] ), .F0(N_137_6), - .F1(UFMSDI_ens2_i_a2_4_2)); - SLICE_85 SLICE_85( .D1(\Din_c[1] ), .C1(\Din_c[7] ), .B1(\Din_c[4] ), - .A1(\Din_c[0] ), .D0(\Din_c[6] ), .C0(\Din_c[7] ), .B0(\Din_c[4] ), - .A0(\Din_c[5] ), .M1(\Din_c[3] ), .M0(\Din_c[2] ), .CLK(nCCAS_c), - .F0(un1_Din_4), .Q0(\WRD[2] ), .F1(CmdEnable17_0_a2_3), .Q1(\WRD[3] )); - SLICE_86 SLICE_86( .C1(\MAin_c[9] ), .A1(nRowColSel), .C0(\MAin_c[9] ), - .B0(\RowA[9] ), .A0(nRowColSel), .F0(\RA_c[9] ), .F1(RDQML_c)); - SLICE_87 SLICE_87( .D1(UFMSDI_ens2_i_a0), .C1(CmdUFMSDI), .B1(N_151), - .D0(N_151), .C0(\FS[9] ), .B0(\FS[11] ), .A0(\FS[4] ), .F0(N_137_8), - .F1(UFMSDI_r_xx_mm_1)); - SLICE_88 SLICE_88( .C1(nFWE_c), .B1(\MAin_c[2] ), .A1(\MAin_c[3] ), - .D0(nCCAS_c), .C0(nFWE_c), .M1(\MAin_c[7] ), .M0(\MAin_c[6] ), - .LSR(Ready_fast), .CLK(nCRAS_c), .F0(RD_1_i), .Q0(\RowA[6] ), - .F1(C1WR_0_a2_0_3), .Q1(\RowA[7] )); - SLICE_89 SLICE_89( .D1(nRowColSel), .C1(\MAin_c[9] ), .D0(nRowColSel), - .C0(\MAin_c[8] ), .B0(\RowA[8] ), .F0(\RA_c[8] ), .F1(RDQMH_c)); - SLICE_90 SLICE_90( .C1(N_147), .B1(\MAin_c[0] ), .A1(\MAin_c[1] ), - .D0(\RowA[0] ), .B0(\MAin_c[0] ), .A0(nRowColSel), .F0(\RA_c[0] ), - .F1(un1_CMDWR)); - SLICE_91 SLICE_91( .D1(nRowColSel), .C1(\RowA[7] ), .B1(\MAin_c[7] ), - .D0(\RowA[1] ), .C0(nRowColSel), .B0(\MAin_c[1] ), .F0(\RA_c[1] ), + SLICE_91 SLICE_91( .D1(\MAin_c[9] ), .A1(nRowColSel), .D0(\MAin_c[9] ), + .B0(\RowA[9] ), .A0(nRowColSel), .F0(\RA_c[9] ), .F1(RDQMH_c)); + SLICE_92 SLICE_92( .D1(\IS[3] ), .C1(\IS[1] ), .A1(\IS[2] ), .D0(RASr2), + .C0(\IS[1] ), .B0(\IS[2] ), .A0(\IS[0] ), .F0(m18_0_a3_3), .F1(N_154)); + SLICE_93 SLICE_93( .D1(\RowA[1] ), .C1(\MAin_c[1] ), .A1(nRowColSel), + .D0(\MAin_c[2] ), .C0(\MAin_c[1] ), .B0(\MAin_c[3] ), .A0(\MAin_c[4] ), + .M1(\Din_c[5] ), .M0(\Din_c[4] ), .CLK(PHI2_c), .F0(CMDWR_2), + .Q0(\Bank[4] ), .F1(\RA_c[1] ), .Q1(\Bank[5] )); + SLICE_94 SLICE_94( .D1(\FS[11] ), .C1(\FS[8] ), .B1(\FS[6] ), .A1(\FS[10] ), + .D0(\FS[2] ), .C0(\FS[0] ), .B0(\FS[6] ), .A0(\FS[3] ), + .F0(un1_FS_13_i_a2_9_4), .F1(UFMSDI_ens2_i_a2_4_2)); + SLICE_95 SLICE_95( .D1(\S[1] ), .B1(InitReady), .D0(\S[1] ), .C0(RASr2), + .B0(CO0), .A0(\IS[3] ), .M1(RASr), .M0(nCRAS_c), .CLK(RCLK_c), + .F0(Ready_0_sqmuxa_0_a3_2), .Q0(RASr), .F1(g0_i_a5_2_1), .Q1(RASr2)); + SLICE_96 SLICE_96( .D1(nRowColSel), .B1(\MAin_c[9] ), .D0(nRowColSel), + .C0(\RowA[8] ), .B0(\MAin_c[8] ), .F0(\RA_c[8] ), .F1(RDQML_c)); + SLICE_97 SLICE_97( .D1(\MAin_c[0] ), .B1(nRowColSel), .A1(\RowA[0] ), + .D0(\RowA[3] ), .B0(\MAin_c[3] ), .A0(nRowColSel), .F0(\RA_c[3] ), + .F1(\RA_c[0] )); + SLICE_98 SLICE_98( .D1(\RowA[2] ), .C1(\MAin_c[2] ), .B1(nRowColSel), + .D0(\RowA[4] ), .C0(nRowColSel), .A0(\MAin_c[4] ), .F0(\RA_c[4] ), + .F1(\RA_c[2] )); + SLICE_99 SLICE_99( .D1(\MAin_c[7] ), .C1(\RowA[7] ), .A1(nRowColSel), + .C0(nRowColSel), .B0(\MAin_c[5] ), .A0(\RowA[5] ), .F0(\RA_c[5] ), .F1(\RA_c[7] )); - SLICE_92 SLICE_92( .D1(nRowColSel), .C1(\MAin_c[6] ), .A1(\RowA[6] ), - .D0(nRowColSel), .C0(\RowA[2] ), .B0(\MAin_c[2] ), .F0(\RA_c[2] ), - .F1(\RA_c[6] )); - SLICE_93 SLICE_93( .D1(\RowA[5] ), .B1(nRowColSel), .A1(\MAin_c[5] ), - .D0(\RowA[3] ), .B0(nRowColSel), .A0(\MAin_c[3] ), .F0(\RA_c[3] ), - .F1(\RA_c[5] )); - SLICE_94 SLICE_94( .D1(Ready), .C1(N_155), .D0(Ready), .C0(\S[1] ), - .M0(\IS[0] ), .LSR(RA10s_i), .CLK(RCLK_c), .F0(RCKEEN_8_u_0_a2_1_out), - .Q0(\RA_c[10] ), .F1(N_159_i)); + SLICE_100 SLICE_100( .D1(nCCAS_c), .B1(nFWE_c), .D0(\Bank[1] ), + .C0(\Bank[3] ), .B0(\Bank[4] ), .A0(\Bank[0] ), .F0(un1_Bank_1_4), + .F1(RD_1_i)); + SLICE_101 SLICE_101( .C1(\MAin_c[6] ), .B1(\RowA[6] ), .A1(nRowColSel), + .D0(N_148), .C0(Ready), .M1(nFWE_c), .M0(nFWE_c), .CLK(nCRAS_c), + .F0(N_153_i), .Q0(FWEr), .F1(\RA_c[6] ), .Q1(FWEr_fast)); RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .PADDT(RD_1_i), .PADDO(\WRD[0] ), .RD0(RD[0])); Dout_0_ \Dout[0]_I ( .PADDO(\RD_in[0] ), .Dout0(Dout[0])); @@ -658,23 +680,20 @@ module SLICE_8 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO ); endmodule -module SLICE_9 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, - F1 ); - wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly; +module SLICE_9 ( input C1, B1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly; - lut4 CmdEnable17_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut4 ADSubmitted_r_RNO( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); lut40002 ADSubmitted_r( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre ADSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); @@ -689,12 +708,12 @@ endmodule module lut4 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hFCFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40002 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h4544) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0F02) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module inverter ( input I, output Z ); @@ -702,19 +721,20 @@ module inverter ( input I, output Z ); INV INST1( .A(I), .Z(Z)); endmodule -module SLICE_14 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, - F1 ); - wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly; +module SLICE_14 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, + Q0, F1 ); + wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly; - lut40003 CmdEnable16_0_a2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); + lut40003 CmdEnable_s_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40004 C1Submitted_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre C1Submitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -732,83 +752,36 @@ endmodule module lut40003 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0301) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40004 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hFF2A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hFF02) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_19 ( input D1, C1, B1, A1, C0, A0, DI0, LSR, CLK, output F0, Q0, - F1 ); - wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; +module SLICE_20 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, + Q0, F1 ); + wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly; - lut40005 Ready_0_sqmuxa_0_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40006 \S_RNO[0] ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0007 \S[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + lut40005 CmdEnable_0_sqmuxa( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40006 CmdEnable_s( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdEnable( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40005 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40006 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'hF5F5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module vmuxregsre0007 ( input D0, D1, SD, SP, CK, LSR, output Q ); - - FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module SLICE_20 ( input D1, A1, D0, C0, B0, A0, DI0, M0, CLK, output OFX0, Q0 ); - wire GNDI, \SLICE_20/SLICE_20_K1_H1 , \SLICE_20/CmdEnable_s/GATE_H0 , VCCI, - CLK_NOTIN, DI0_dly, CLK_dly; - - lut40008 SLICE_20_K1( .A(A1), .B(GNDI), .C(GNDI), .D(D1), - .Z(\SLICE_20/SLICE_20_K1_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40009 \CmdEnable_s/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(\SLICE_20/CmdEnable_s/GATE_H0 )); - vmuxregsre CmdEnable( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - selmux2 SLICE_20_K0K1MUX( .D0(\SLICE_20/CmdEnable_s/GATE_H0 ), - .D1(\SLICE_20/SLICE_20_K1_H1 ), .SD(M0), .Z(OFX0)); - - specify - (D1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (D0 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); @@ -816,28 +789,23 @@ module SLICE_20 ( input D1, A1, D0, C0, B0, A0, DI0, M0, CLK, output OFX0, Q0 ); endmodule -module lut40008 ( input A, B, C, D, output Z ); +module lut40005 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hFFAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40009 ( input A, B, C, D, output Z ); +module lut40006 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hEA22) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hFDEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module selmux2 ( input D0, D1, SD, output Z ); - - MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z)); -endmodule - -module SLICE_21 ( input D1, C1, B1, D0, C0, B0, A0, DI0, CE, CLK, output F0, +module SLICE_21 ( input D1, C1, B1, A1, D0, C0, B0, DI0, CE, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; - lut40010 Cmdn8MEGEN_4_u_i_a2_2( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40007 CmdLEDEN_4_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40008 CmdLEDEN_RNO( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40011 CmdLEDEN_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre CmdLEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -847,10 +815,10 @@ module SLICE_21 ( input D1, C1, B1, D0, C0, B0, A0, DI0, CE, CLK, output F0, (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); @@ -860,21 +828,21 @@ module SLICE_21 ( input D1, C1, B1, D0, C0, B0, A0, DI0, CE, CLK, output F0, endmodule -module lut40010 ( input A, B, C, D, output Z ); +module lut40007 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h7350) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40011 ( input A, B, C, D, output Z ); +module lut40008 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h1011) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0F03) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_22 ( input D1, C1, B1, A1, D0, A0, DI0, CLK, output F0, Q0, F1 ); +module SLICE_22 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly; - lut40012 un1_FS_14_i_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40013 CmdSubmitted_RNO( .A(A0), .B(GNDI), .C(GNDI), .D(D0), .Z(F0)); + lut40009 un1_FS_14_i_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40010 CmdSubmitted_RNO( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre CmdSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); @@ -886,7 +854,7 @@ module SLICE_22 ( input D1, C1, B1, A1, D0, A0, DI0, CLK, output F0, Q0, F1 ); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); @@ -896,22 +864,22 @@ module SLICE_22 ( input D1, C1, B1, A1, D0, A0, DI0, CLK, output F0, Q0, F1 ); endmodule -module lut40012 ( input A, B, C, D, output Z ); +module lut40009 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40013 ( input A, B, C, D, output Z ); +module lut40010 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hFFAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hFAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_26 ( input D1, C1, B1, A1, D0, C0, A0, DI0, CE, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; - lut40014 Cmdn8MEGEN_4_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40015 Cmdn8MEGEN_RNO( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + lut40011 Cmdn8MEGEN_4_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40012 Cmdn8MEGEN_RNO( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre Cmdn8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); @@ -935,60 +903,63 @@ module SLICE_26 ( input D1, C1, B1, A1, D0, C0, A0, DI0, CE, CLK, output F0, endmodule -module lut40014 ( input A, B, C, D, output Z ); +module lut40011 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h33AB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hD5C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40015 ( input A, B, C, D, output Z ); +module lut40012 ( input A, B, C, D, output Z ); ROM16X1 #(16'h0F05) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_29 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, - F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly; +module SLICE_29 ( input D1, C1, B1, D0, C0, A0, DI0, M1, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; - lut40016 nRRAS_5_u_i( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40017 \IS_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40013 Ready_0_sqmuxa_0_o2( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); + lut40014 \IS_RNO[0] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CASr3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre \IS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module lut40016 ( input A, B, C, D, output Z ); +module lut40013 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hCFCE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h3FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40017 ( input A, B, C, D, output Z ); +module lut40014 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hA9A9) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hAAA5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_30 ( input D1, C1, A1, D0, A0, DI1, DI0, CE, CLK, output F0, Q0, +module SLICE_30 ( input D1, B1, A1, D0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40018 \IS_RNO[2] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + lut40015 \IS_RNO[2] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40019 IS_n1_0_x2( .A(A0), .B(GNDI), .C(GNDI), .D(D0), .Z(F0)); + lut40016 IS_n1_0_x2( .A(A0), .B(GNDI), .C(GNDI), .D(D0), .Z(F0)); vmuxregsre \IS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -997,7 +968,7 @@ module SLICE_30 ( input D1, C1, A1, D0, A0, DI1, DI0, CE, CLK, output F0, Q0, specify (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); @@ -1012,12 +983,12 @@ module SLICE_30 ( input D1, C1, A1, D0, A0, DI1, DI0, CE, CLK, output F0, Q0, endmodule -module lut40018 ( input A, B, C, D, output Z ); +module lut40015 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h5AF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h66AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40019 ( input A, B, C, D, output Z ); +module lut40016 ( input A, B, C, D, output Z ); ROM16X1 #(16'h55AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule @@ -1026,8 +997,8 @@ module SLICE_31 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; - lut40020 RA10_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40021 \IS_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40017 RA10_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40018 \IS_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \IS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1051,21 +1022,21 @@ module SLICE_31 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output endmodule -module lut40020 ( input A, B, C, D, output Z ); +module lut40017 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hFFFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40021 ( input A, B, C, D, output Z ); +module lut40018 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h78F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h6CCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_32 ( input D1, C1, B1, A1, D0, A0, DI0, CLK, output F0, Q0, F1 ); +module SLICE_32 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly; - lut40022 UFMSDI_ens2_i_a0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40013 InitReady_RNO( .A(A0), .B(GNDI), .C(GNDI), .D(D0), .Z(F0)); + lut40019 UFMSDI_ens2_i_a0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40020 InitReady_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre InitReady( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); @@ -1076,7 +1047,7 @@ module SLICE_32 ( input D1, C1, B1, A1, D0, A0, DI0, CLK, output F0, Q0, F1 ); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); @@ -1086,18 +1057,23 @@ module SLICE_32 ( input D1, C1, B1, A1, D0, A0, DI0, CLK, output F0, Q0, F1 ); endmodule -module lut40022 ( input A, B, C, D, output Z ); +module lut40019 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0B0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h5155) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_33 ( input D1, C1, A1, D0, B0, A0, DI0, CE, CLK, output F0, Q0, - F1 ); +module lut40020 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_33 ( input D1, C1, B1, A1, D0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - lut40023 LED_pad_RNO( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + lut40021 LED_pad_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40022 LEDEN_5_i_m2( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40024 LEDEN_5_i_m2( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); vmuxregsre LEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1105,6 +1081,7 @@ module SLICE_33 ( input D1, C1, A1, D0, B0, A0, DI0, CE, CLK, output F0, Q0, specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); @@ -1118,33 +1095,73 @@ module SLICE_33 ( input D1, C1, A1, D0, B0, A0, DI0, CE, CLK, output F0, Q0, endmodule +module lut40021 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40022 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hBB11) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_38 ( input D1, C1, B1, A1, C0, A0, DI0, LSR, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; + + lut40023 nRCS_RNO_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40010 RA10_2_sqmuxa_0_o2( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0024 RA10( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + module lut40023 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hFAFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40024 ( input A, B, C, D, output Z ); +module vmuxregsre0024 ( input D0, D1, SD, SP, CK, LSR, output Q ); - ROM16X1 #(16'hCC55) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + FL1P3JY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; endmodule -module SLICE_39 ( input D1, B1, D0, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); +module SLICE_39 ( input C1, B1, A1, D0, C0, B0, DI0, LSR, CLK, output F0, Q0, + F1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; - lut40025 XOR8MEG_3_u_0_a3_0( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + lut40025 Cmdn8MEGEN_4_u_i_o2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40026 RA11_2( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); - vmuxregsre0007 RA11( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + lut40026 RA11_2( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0027 RA11( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify - (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); @@ -1156,20 +1173,26 @@ endmodule module lut40025 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h3300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hFDFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40026 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hBB44) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hCC3C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0027 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; endmodule module SLICE_41 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, DI0_dly, CLK_dly, M1_dly; - lut40027 RCKEEN_8_u_1_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40028 RCKEEN_8_u( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40028 RCKEEN_8_u_0_1_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40029 RCKEEN_8_u_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre PHI2r2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1196,33 +1219,32 @@ module SLICE_41 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output endmodule -module lut40027 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h75A5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40028 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hAAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h22AE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_42 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output - F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, M1_dly; +module lut40029 ( input A, B, C, D, output Z ); - lut40029 nRWE_RNO_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40030 RCKE_2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + ROM16X1 #(16'hCCCE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_42 ( input D1, C1, A1, D0, C0, B0, A0, DI0, M1, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; + + lut40030 nRCS_RNO_3( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40031 RCKE_2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre PHI2r( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre RCKE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); @@ -1238,22 +1260,22 @@ module SLICE_42 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output endmodule -module lut40029 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40030 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hDCD8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hF0A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40031 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hCCF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_43 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, DI0_dly, CLK_dly, M1_dly; - lut40031 RCKEEN_8_u_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40032 Ready_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40032 RCKEEN_8_u_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40033 Ready_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre PHI2r3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1280,26 +1302,25 @@ module SLICE_43 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output endmodule -module lut40031 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h03AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40032 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hFF08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h1F10) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_44 ( input D1, C1, B1, A1, B0, A0, DI0, M1, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, M1_NOTIN, VCCI, DI0_dly, CLK_dly, M1_dly; +module lut40033 ( input A, B, C, D, output Z ); - lut40033 Ready_0_sqmuxa_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40034 Ready_fast_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + ROM16X1 #(16'hAEAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_44 ( input D1, C1, B1, A1, C0, A0, DI0, M1, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; + + lut40034 Ready_0_sqmuxa_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40010 Ready_fast_RNO( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre RASr( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN)); + vmuxregsre RASr3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre Ready_fast( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); @@ -1309,7 +1330,7 @@ module SLICE_44 ( input D1, C1, B1, A1, B0, A0, DI0, M1, CLK, output F0, Q0, (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); @@ -1321,23 +1342,18 @@ module SLICE_44 ( input D1, C1, B1, A1, B0, A0, DI0, M1, CLK, output F0, Q0, endmodule -module lut40033 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40034 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_50 ( input D1, C1, A1, C0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); +module SLICE_50 ( input D1, C1, B1, D0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; - lut40035 nRowColSel_RNO( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + lut40035 nRowColSel_RNO( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40036 \S_0_i_o2[1] ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0007 \S[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + lut40036 \S_0_i_o2[1] ( .A(A0), .B(GNDI), .C(GNDI), .D(D0), .Z(F0)); + vmuxregsre0027 \S[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); @@ -1345,8 +1361,8 @@ module SLICE_50 ( input D1, C1, A1, C0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); @@ -1359,26 +1375,24 @@ endmodule module lut40035 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0500) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0030) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40036 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hFAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hFFAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output - F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, M1_dly; +module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, + Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly; lut40037 UFMCLK_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40038 UFMCLK_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre RASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre UFMCLK( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -1390,9 +1404,7 @@ module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify @@ -1401,26 +1413,24 @@ endmodule module lut40037 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hABFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hFF53) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40038 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0322) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0544) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output - F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, M1_dly; +module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, + Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly; lut40039 PHI2r3_RNITCN41( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40040 UFMSDI_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre RASr3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre UFMSDI( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -1432,9 +1442,7 @@ module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify @@ -1443,18 +1451,18 @@ endmodule module lut40039 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h2F0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h5D55) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40040 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h5404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h2320) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_55 ( input D0, B0, A0, M1, M0, CLK, output F0, Q0, Q1 ); +module SLICE_55 ( input D0, C0, A0, M1, M0, CLK, output F0, Q0, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; - lut40041 \un9_RA[4] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); + lut40041 UFMSDI_RNO_0( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \WRD[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); @@ -1465,7 +1473,7 @@ module SLICE_55 ( input D0, B0, A0, M1, M0, CLK, output F0, Q0, Q1 ); specify (D0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); @@ -1479,16 +1487,15 @@ endmodule module lut40041 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hBB88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h5550) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_56 ( input D1, C1, B1, A1, D0, C0, A0, M1, M0, CLK, output F0, Q0, - F1, Q1 ); +module SLICE_56 ( input D1, C1, C0, A0, M1, M0, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; - lut40042 C1WR_0_a2_0_11( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40043 UFMSDI_ens2_i_o2( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + lut40042 un1_FS_14_i_o2( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); + lut40043 nRCS_9_u_i_a2( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \WRD[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1499,9 +1506,6 @@ module SLICE_56 ( input D1, C1, B1, A1, D0, C0, A0, M1, M0, CLK, output F0, Q0, specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); @@ -1516,30 +1520,28 @@ endmodule module lut40042 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40043 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h5A0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0505) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output - F0, Q0, F1 ); - wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly; +module SLICE_57 ( input C1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; - lut40044 XOR8MEG_3_u_0_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40045 XOR8MEG_3_u_0_a3_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40044 XOR8MEG_3_u_0_a3( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40045 XOR8MEG_3_u_0_a3_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre XOR8MEG( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); @@ -1556,21 +1558,21 @@ endmodule module lut40044 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hA0A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40045 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hBAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hDCFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_58 ( input D1, C1, A1, D0, B0, A0, DI0, CE, CLK, output F0, Q0, +module SLICE_58 ( input D1, C1, B1, D0, C0, A0, DI0, CE, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - lut40046 UFMSDI_en_ss0_0_a2_0( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + lut40046 UFMSDI_en_ss0_0_a2_0( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40047 n8MEGEN_5_i_m2( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); + lut40047 n8MEGEN_5_i_m2( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); vmuxregsre n8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1578,9 +1580,9 @@ module SLICE_58 ( input D1, C1, A1, D0, B0, A0, DI0, CE, CLK, output F0, Q0, specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); @@ -1593,30 +1595,29 @@ endmodule module lut40046 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0005) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0003) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40047 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h88DD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hA0AF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, - Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly; +module SLICE_59 ( input D1, C1, B1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly; - lut40048 un1_nRCAS_6_sqmuxa_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40048 nRCAS_RNO_1( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); lut40049 nRCAS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0050 nRCAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); @@ -1631,12 +1632,12 @@ endmodule module lut40048 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0FDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0333) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40049 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0F04) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0545) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module vmuxregsre0050 ( input D0, D1, SD, SP, CK, LSR, output Q ); @@ -1645,19 +1646,18 @@ module vmuxregsre0050 ( input D0, D1, SD, SP, CK, LSR, output Q ); defparam INST01.GSR = "DISABLED"; endmodule -module SLICE_60 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, - Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly; +module SLICE_60 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly; - lut40051 nRCS_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40051 RCKEEN_8_u_0_a2_0_m1_0_a2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); lut40052 nRCS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0050 nRCS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -1675,12 +1675,12 @@ endmodule module lut40051 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hFC7C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40052 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h3323) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0515) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_61 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, @@ -1718,7 +1718,7 @@ endmodule module lut40054 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h3031) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h5501) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, @@ -1765,7 +1765,7 @@ module SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output lut40057 nRowColSel_0_0_a3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40058 nRowColSel_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0007 nRowColSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + vmuxregsre0027 nRowColSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1789,12 +1789,12 @@ endmodule module lut40057 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40058 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hFF60) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hF2F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_64 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, @@ -1832,7 +1832,7 @@ endmodule module lut40060 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hDFCE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hF7F2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module nRWE_RNO_1_SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, output @@ -1864,30 +1864,26 @@ endmodule module lut40061 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40062 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_66 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; +module selmux2 ( input D0, D1, SD, output Z ); - lut40063 nUFMCS_s_0_N_5_i_N_2L1( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40064 UFMCLK_r_i_a2_2_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0007 \RowA[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0007 \RowA[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z)); +endmodule + +module SLICE_66 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40063 IS_0_sqmuxa_0_o2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40064 un1_nRCAS_6_sqmuxa_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -1895,47 +1891,39 @@ module SLICE_66 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module lut40063 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h4545) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hEFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40064 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h33F5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_67 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; +module SLICE_67 ( input D1, C1, B1, D0, C0, B0, A0, M1, M0, LSR, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - lut40065 CmdUFMCLK_1_sqmuxa_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40066 XOR8MEG18_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0067 \RowA[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + lut40065 nUFMCS_s_0_N_5_i_N_2L1( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40055 UFMCLK_r_i_a2_2_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0027 \RowA[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0007 \RowA[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + vmuxregsre0027 \RowA[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); @@ -1953,24 +1941,19 @@ endmodule module lut40065 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h3303) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40066 ( input A, B, C, D, output Z ); +module SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, LSR, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, M0_dly, CLK_dly, LSR_dly; - ROM16X1 #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module vmuxregsre0067 ( input D0, D1, SD, SP, CK, LSR, output Q ); - - FL1P3JY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40068 un1_FS_14_i_a2_0_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40069 un1_FS_14_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40066 nRCS_RNO_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40067 nRCS_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0027 \S[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -1981,31 +1964,81 @@ module SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40066 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40067 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hF0F4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_69 ( input D1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40068 UFMSDI_ens2_i_o2_0( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40069 UFMCLK_RNO_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0027 \RowA[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0027 \RowA[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module lut40068 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hFFEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40069 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hFF80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hEC20) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_70 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; - lut40070 un1_FS_13_i_a2_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40071 un1_FS_13_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40070 CMDWR( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40071 un1_CmdEnable20_0_a3( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); @@ -2015,26 +2048,20 @@ endmodule module lut40070 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40071 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hECCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_70 ( input D1, C1, B1, A1, C0, B0, M1, M0, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; +module SLICE_71 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; - lut40072 C1WR_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40073 C1WR_0_a2( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40072 un1_FS_14_i_a2_0_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40073 un1_FS_14_i_0( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \Bank[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \Bank[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -2043,38 +2070,27 @@ module SLICE_70 ( input D1, C1, B1, A1, C0, B0, M1, M0, CLK, output F0, Q0, F1, (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); + (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule module lut40072 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40073 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hC0C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hEAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_71 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, - Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly; +module SLICE_72 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 ); + wire GNDI; - lut40074 C1WR_0_a2_0_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40075 C1WR_0_a2_0_10( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \Bank[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); + lut40074 un1_FS_13_i_a2_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40075 un1_FS_13_i_0( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \Bank[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -2084,50 +2100,42 @@ module SLICE_71 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); endspecify endmodule module lut40074 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40075 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hFCF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_72 ( input D1, C1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output - F0, Q0, F1, Q1 ); +module SLICE_73 ( input D1, C1, B1, A1, D0, C0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - lut40076 UFMSDI_ens2_i_o2_0( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + lut40076 CmdSubmitted_1_sqmuxa_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40077 XOR8MEG18( .A(GNDI), .B(GNDI), .C(C0), .D(D0), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40077 UFMCLK_r_i_m2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0007 \RowA[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + vmuxregsre0027 \RowA[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0007 \RowA[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + vmuxregsre0027 \RowA[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); @@ -2141,95 +2149,21 @@ endmodule module lut40076 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hFFFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h002A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40077 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hF808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hF000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_73 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40078 IS_0_sqmuxa_0_o2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40034 IS_0_sqmuxa_0_o2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre CmdUFMCS( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - vmuxregsre CmdUFMCLK( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - endspecify - -endmodule - -module lut40078 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'hFFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_74 ( input D1, B1, D0, C0, B0, A0, M0, CE, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; - - lut40079 InitReady3_0_a2_3( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40080 InitReady3_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre CmdUFMSDI( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - endspecify - -endmodule - -module lut40079 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'hCC00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40080 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_75 ( input C1, B1, A1, D0, C0, A0, M1, M0, CLK, output F0, Q0, F1, +module SLICE_74 ( input C1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, M0_NOTIN, M1_dly, CLK_dly, M0_dly; - lut40081 Cmdn8MEGEN_4_u_i_o2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40078 CmdEnable17_0_o2( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40082 CmdLEDEN_4_u_i_a2_0( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + lut40079 CmdEnable17_0_a3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre CASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -2239,49 +2173,9 @@ module SLICE_75 ( input C1, B1, A1, D0, C0, A0, M1, M0, CLK, output F0, Q0, F1, specify (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40081 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'hEFEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40082 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h0005) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_76 ( input D1, B1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; - - lut40083 CmdEnable16_0_a2_4( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40084 CmdEnable16_0_a2_4_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \Bank[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \Bank[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); @@ -2294,29 +2188,168 @@ module SLICE_76 ( input D1, B1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, endmodule -module lut40083 ( input A, B, C, D, output Z ); +module lut40078 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h00CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hFAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40084 ( input A, B, C, D, output Z ); +module lut40079 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_77 ( input C1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, - Q1 ); +module SLICE_75 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; - lut40085 CmdEnable16_0_a2_1( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1)); + lut40080 CmdEnable16_0_a3_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40081 CmdEnable16_0_a3( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40086 CmdEnable16_0_a2_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \Bank[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre \Bank[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40080 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40081 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_76 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly; + + lut40082 C1WR_2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40083 C1WR( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \Bank[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \Bank[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40082 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40083 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_77 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40084 un1_Bank_1_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40085 ADWR( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40084 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40085 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_78 ( input D1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40086 CmdEnable17_0_a2( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40087 un1_CmdEnable20_0_a3_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40086 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hAA00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40087 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_79 ( input C1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40044 ADWR_8_2( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40088 C1WR_7( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \Bank[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \Bank[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + specify (C1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -2334,163 +2367,83 @@ module SLICE_77 ( input C1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, endmodule -module lut40085 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h5050) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40086 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_78 ( input C1, B1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, M1_NOTIN, VCCI, CLK_NOTIN, M0_NOTIN, M1_dly, CLK_dly, M0_dly; - - lut40087 CmdEnable17_0_o2( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40088 CmdEnable17_0_a2_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre CBR_fast( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); - inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - vmuxregsre CBR( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - endspecify - -endmodule - -module lut40087 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h3F3F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40088 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_79 ( input D1, C1, B1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; +module SLICE_80 ( input C1, B1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; - lut40089 nRWE_RNO_2( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40089 InitReady3_0_a2_3( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40090 nRWE_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \WRD[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - vmuxregsre \WRD[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + lut40090 InitReady3_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); endspecify endmodule module lut40089 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h00C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hC0C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40090 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_80 ( input C1, B1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; +module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40091 nRCAS_RNO_1( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40092 nRCAS_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0067 \RowA[9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0007 \RowA[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + lut40091 ADWR_8_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40092 ADWR_8( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module lut40091 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h3030) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40092 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0805) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, - Q0, F1, Q1 ); - wire M1_NOTIN, VCCI, GNDI, CLK_NOTIN, M0_NOTIN, M1_dly, CLK_dly, M0_dly; +module SLICE_82 ( input D1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; - lut40093 UFMSDI_ens2_i_o2_0_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40094 InitReady3_0_a2_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre FWEr_fast( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); - inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN)); - vcc DRIVEVCC( .PWR1(VCCI)); + lut40093 nRWE_RNO_2( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); + lut40094 nRWE_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \WRD[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - vmuxregsre FWEr( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), + vmuxregsre \WRD[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); @@ -2509,24 +2462,28 @@ endmodule module lut40093 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h2200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40094 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_82 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0, - F1 ); - wire VCCI, GNDI, M0_dly, CLK_dly; +module SLICE_83 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - lut40095 CmdLEDEN_4_u_i_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40096 CmdSubmitted_1_sqmuxa_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre CASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(GNDI), .Q(Q0)); + lut40095 XOR8MEG_3_u_0_o2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40096 XOR8MEG_3_u_0_a3_0_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0024 \RowA[9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0027 \RowA[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -2538,46 +2495,6 @@ module SLICE_82 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0, (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40095 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h0E0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40096 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h1030) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_83 ( input C1, B1, A1, D0, C0, A0, M1, M0, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40097 un1_nRCAS_6_sqmuxa_i_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40098 Ready_0_sqmuxa_0_o2( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0007 \RBA[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0007 \RBA[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); @@ -2588,56 +2505,28 @@ module SLICE_83 ( input C1, B1, A1, D0, C0, A0, M1, M0, LSR, CLK, output F0, endmodule -module lut40097 ( input A, B, C, D, output Z ); +module lut40095 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40098 ( input A, B, C, D, output Z ); +module lut40096 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h5FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40099 UFMSDI_ens2_i_a2_4_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40100 un1_FS_13_i_a2_6( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40099 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40100 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, +module SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; - lut40101 CmdEnable17_0_a2_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40102 un1_Din_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \WRD[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + lut40097 nRCAS_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40098 nRCS_RNO_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \WRD[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - vmuxregsre \WRD[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + vmuxregsre \WRD[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify @@ -2659,26 +2548,70 @@ module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, endmodule -module lut40101 ( input A, B, C, D, output Z ); +module lut40097 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h4033) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40098 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_85 ( input D1, C1, B1, A1, D0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40099 CmdUFMCLK_1_sqmuxa_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40100 Cmdn8MEGEN_4_u_i_a2_2( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CmdUFMCS( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre CmdUFMCLK( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40099 ( input A, B, C, D, output Z ); ROM16X1 #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40102 ( input A, B, C, D, output Z ); +module lut40100 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0022) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_86 ( input C1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; +module SLICE_86 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40103 RDQML( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40104 \un9_RA[9] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40101 UFMSDI_ens2_i_o2_0_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40102 InitReady3_0_a2_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); @@ -2686,66 +2619,123 @@ module SLICE_86 ( input C1, A1, C0, B0, A0, output F0, F1 ); endmodule +module lut40101 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40102 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_87 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, + Q0, F1, Q1 ); + wire M1_NOTIN, VCCI, GNDI, CLK_NOTIN, M0_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40103 CmdLEDEN_4_u_i_a2_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40104 CmdEnable16_0_a3_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CBR_fast( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre CBR( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + module lut40103 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h5F5F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40104 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hE4E4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_87 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; +module SLICE_88 ( input D1, C1, B1, A1, D0, B0, A0, M0, CE, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; - lut40105 UFMSDI_RNO_0( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40105 CmdEnable17_0_a3_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40106 Cmdn8MEGEN_4_u_i_o2( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40106 un1_FS_13_i_a2_8( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdUFMSDI( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40105 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h00FC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40106 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hEECC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_88 ( input C1, B1, A1, D0, C0, M1, M0, LSR, CLK, output F0, Q0, - F1, Q1 ); +module SLICE_89 ( input D1, C1, B1, A1, D0, C0, A0, M1, M0, LSR, CLK, output + F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - lut40107 C1WR_0_a2_0_3( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40107 un1_FS_13_i_a2_9_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40108 UFMSDI_ens2_i_o2( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40108 nCCAS_pad_RNI01SJ( .A(GNDI), .B(GNDI), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0007 \RowA[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + vmuxregsre0024 \RowA[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0007 \RowA[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + vmuxregsre0027 \RowA[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); @@ -2759,51 +2749,65 @@ endmodule module lut40107 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40108 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hFFF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h55A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_89 ( input D1, C1, D0, C0, B0, output F0, F1 ); - wire GNDI; +module SLICE_90 ( input C1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - lut40109 RDQMH( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + lut40109 RCKEEN_8_u_0_1_a1_0( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40110 \un9_RA[8] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40110 RCKEEN_8_u_0_a3_0_0( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0027 \RBA[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0027 \RBA[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module lut40109 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hF0FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h0A0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40110 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hF0CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'h7070) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_90 ( input C1, B1, A1, D0, B0, A0, output F0, F1 ); +module SLICE_91 ( input D1, A1, D0, B0, A0, output F0, F1 ); wire GNDI; - lut40111 un1_CMDWR( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40111 RDQMH( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40112 \un9_RA[0] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); + lut40112 \un9_RA[9] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); + (D1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); @@ -2814,48 +2818,20 @@ endmodule module lut40111 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hE0E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hFF55) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40112 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hDD88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hEE44) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_91 ( input D1, C1, B1, D0, C0, B0, output F0, F1 ); +module SLICE_92 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40113 \un9_RA[7] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40113 un1_nRCAS_6_sqmuxa_i_o2( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40114 \un9_RA[1] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40113 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'hCCF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40114 ( input A, B, C, D, output Z ); - - ROM16X1 #(16'hCFC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_92 ( input D1, C1, A1, D0, C0, B0, output F0, F1 ); - wire GNDI; - - lut40115 \un9_RA[6] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40113 \un9_RA[2] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40114 nRWE_RNO_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -2864,21 +2840,159 @@ module SLICE_92 ( input D1, C1, A1, D0, C0, B0, output F0, F1 ); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40113 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFFFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40114 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_93 ( input D1, C1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40115 \un9_RA[1] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40116 CMDWR_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \Bank[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \Bank[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule module lut40115 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hF0AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hF5A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_93 ( input D1, B1, A1, D0, B0, A0, output F0, F1 ); +module lut40116 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_94 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40117 UFMSDI_ens2_i_a2_4_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40059 un1_FS_13_i_a2_9_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40117 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_95 ( input D1, B1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M0_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40118 nRCS_RNO_4( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40119 Ready_0_sqmuxa_0_a3_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre RASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre RASr( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40118 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h00CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40119 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_96 ( input D1, B1, D0, C0, B0, output F0, F1 ); wire GNDI; - lut40041 \un9_RA[5] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + lut40120 RDQML( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \un9_RA[3] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); + lut40121 \un9_RA[8] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40120 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h33FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40121 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hCCF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_97 ( input D1, B1, A1, D0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40122 \un9_RA[0] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40123 \un9_RA[3] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -2891,40 +3005,141 @@ module SLICE_93 ( input D1, B1, A1, D0, B0, A0, output F0, F1 ); endmodule -module SLICE_94 ( input D1, C1, D0, C0, M0, LSR, CLK, output F0, Q0, F1 ); - wire GNDI, M0_NOTIN, VCCI, M0_dly, CLK_dly, LSR_dly; +module lut40122 ( input A, B, C, D, output Z ); - lut40116 IS_0_sqmuxa_0_o2_0_RNIS63D( .A(GNDI), .B(GNDI), .C(C1), .D(D1), - .Z(F1)); + ROM16X1 #(16'hEE22) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40123 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hDD88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_98 ( input D1, C1, B1, D0, C0, A0, output F0, F1 ); + wire GNDI; + + lut40124 \un9_RA[2] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40117 RCKEEN_8_u_0_a2_1_s( .A(GNDI), .B(GNDI), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0067 RA10( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN)); - vcc DRIVEVCC( .PWR1(VCCI)); + lut40125 \un9_RA[4] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); + (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule -module lut40116 ( input A, B, C, D, output Z ); +module lut40124 ( input A, B, C, D, output Z ); - ROM16X1 #(16'h000F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hF3C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40117 ( input A, B, C, D, output Z ); +module lut40125 ( input A, B, C, D, output Z ); - ROM16X1 #(16'hF000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1 #(16'hAFA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_99 ( input D1, C1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40126 \un9_RA[7] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40127 \un9_RA[5] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40126 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFA50) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40127 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hCACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_100 ( input D1, B1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40128 nCCAS_pad_RNI01SJ( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40129 un1_Bank_1_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40128 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFFCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40129 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_101 ( input C1, B1, A1, D0, C0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, M1_NOTIN, VCCI, CLK_NOTIN, M0_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40130 \un9_RA[6] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40131 IS_0_sqmuxa_0_o2_0_RNIS63D( .A(GNDI), .B(GNDI), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre FWEr_fast( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre FWEr( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module lut40130 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hE4E4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40131 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h000F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RD_0_ ( output PADDI, input PADDT, PADDO, inout RD0 ); @@ -2949,7 +3164,7 @@ endmodule module Dout_0_ ( input PADDO, output Dout0 ); - mjiobuf0118 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0)); + mjiobuf0132 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0)); specify (PADDO => Dout0) = (0:0:0,0:0:0); @@ -2957,14 +3172,14 @@ module Dout_0_ ( input PADDO, output Dout0 ); endmodule -module mjiobuf0118 ( input I, output PAD ); +module mjiobuf0132 ( input I, output PAD ); OB INST5( .I(I), .O(PAD)); endmodule module PHI2 ( output PADDI, input PHI2 ); - mjiobuf0119 PHI2_pad( .Z(PADDI), .PAD(PHI2)); + mjiobuf0133 PHI2_pad( .Z(PADDI), .PAD(PHI2)); specify (PHI2 => PADDI) = (0:0:0,0:0:0); @@ -2974,14 +3189,14 @@ module PHI2 ( output PADDI, input PHI2 ); endmodule -module mjiobuf0119 ( output Z, input PAD ); +module mjiobuf0133 ( output Z, input PAD ); IB INST1( .I(PAD), .O(Z)); endmodule module UFMSDO ( output PADDI, input UFMSDO ); - mjiobuf0119 UFMSDO_pad( .Z(PADDI), .PAD(UFMSDO)); + mjiobuf0133 UFMSDO_pad( .Z(PADDI), .PAD(UFMSDO)); specify (UFMSDO => PADDI) = (0:0:0,0:0:0); @@ -2993,7 +3208,7 @@ endmodule module UFMSDI ( input PADDO, output UFMSDI ); - mjiobuf0120 UFMSDI_pad( .I(PADDO), .PAD(UFMSDI)); + mjiobuf0134 UFMSDI_pad( .I(PADDO), .PAD(UFMSDI)); specify (PADDO => UFMSDI) = (0:0:0,0:0:0); @@ -3001,14 +3216,14 @@ module UFMSDI ( input PADDO, output UFMSDI ); endmodule -module mjiobuf0120 ( input I, output PAD ); +module mjiobuf0134 ( input I, output PAD ); OB INST5( .I(I), .O(PAD)); endmodule module UFMCLK ( input PADDO, output UFMCLK ); - mjiobuf0120 UFMCLK_pad( .I(PADDO), .PAD(UFMCLK)); + mjiobuf0134 UFMCLK_pad( .I(PADDO), .PAD(UFMCLK)); specify (PADDO => UFMCLK) = (0:0:0,0:0:0); @@ -3018,7 +3233,7 @@ endmodule module nUFMCS ( input PADDO, output nUFMCS ); - mjiobuf0120 nUFMCS_pad( .I(PADDO), .PAD(nUFMCS)); + mjiobuf0134 nUFMCS_pad( .I(PADDO), .PAD(nUFMCS)); specify (PADDO => nUFMCS) = (0:0:0,0:0:0); @@ -3028,7 +3243,7 @@ endmodule module RDQML ( input PADDO, output RDQML ); - mjiobuf0120 RDQML_pad( .I(PADDO), .PAD(RDQML)); + mjiobuf0134 RDQML_pad( .I(PADDO), .PAD(RDQML)); specify (PADDO => RDQML) = (0:0:0,0:0:0); @@ -3038,7 +3253,7 @@ endmodule module RDQMH ( input PADDO, output RDQMH ); - mjiobuf0120 RDQMH_pad( .I(PADDO), .PAD(RDQMH)); + mjiobuf0134 RDQMH_pad( .I(PADDO), .PAD(RDQMH)); specify (PADDO => RDQMH) = (0:0:0,0:0:0); @@ -3048,7 +3263,7 @@ endmodule module nRCAS ( input PADDO, output nRCAS ); - mjiobuf0120 nRCAS_pad( .I(PADDO), .PAD(nRCAS)); + mjiobuf0134 nRCAS_pad( .I(PADDO), .PAD(nRCAS)); specify (PADDO => nRCAS) = (0:0:0,0:0:0); @@ -3058,7 +3273,7 @@ endmodule module nRRAS ( input PADDO, output nRRAS ); - mjiobuf0120 nRRAS_pad( .I(PADDO), .PAD(nRRAS)); + mjiobuf0134 nRRAS_pad( .I(PADDO), .PAD(nRRAS)); specify (PADDO => nRRAS) = (0:0:0,0:0:0); @@ -3068,7 +3283,7 @@ endmodule module nRWE ( input PADDO, output nRWE ); - mjiobuf0120 nRWE_pad( .I(PADDO), .PAD(nRWE)); + mjiobuf0134 nRWE_pad( .I(PADDO), .PAD(nRWE)); specify (PADDO => nRWE) = (0:0:0,0:0:0); @@ -3078,7 +3293,7 @@ endmodule module RCKE ( input PADDO, output RCKE ); - mjiobuf0120 RCKE_pad( .I(PADDO), .PAD(RCKE)); + mjiobuf0134 RCKE_pad( .I(PADDO), .PAD(RCKE)); specify (PADDO => RCKE) = (0:0:0,0:0:0); @@ -3088,7 +3303,7 @@ endmodule module RCLK ( output PADDI, input RCLK ); - mjiobuf0119 RCLK_pad( .Z(PADDI), .PAD(RCLK)); + mjiobuf0133 RCLK_pad( .Z(PADDI), .PAD(RCLK)); specify (RCLK => PADDI) = (0:0:0,0:0:0); @@ -3100,7 +3315,7 @@ endmodule module nRCS ( input PADDO, output nRCS ); - mjiobuf0120 nRCS_pad( .I(PADDO), .PAD(nRCS)); + mjiobuf0134 nRCS_pad( .I(PADDO), .PAD(nRCS)); specify (PADDO => nRCS) = (0:0:0,0:0:0); @@ -3208,7 +3423,7 @@ endmodule module RA_11_ ( input PADDO, output RA11 ); - mjiobuf0120 \RA_pad[11] ( .I(PADDO), .PAD(RA11)); + mjiobuf0134 \RA_pad[11] ( .I(PADDO), .PAD(RA11)); specify (PADDO => RA11) = (0:0:0,0:0:0); @@ -3218,7 +3433,7 @@ endmodule module RA_10_ ( input PADDO, output RA10 ); - mjiobuf0120 \RA_pad[10] ( .I(PADDO), .PAD(RA10)); + mjiobuf0134 \RA_pad[10] ( .I(PADDO), .PAD(RA10)); specify (PADDO => RA10) = (0:0:0,0:0:0); @@ -3228,7 +3443,7 @@ endmodule module RA_9_ ( input PADDO, output RA9 ); - mjiobuf0120 \RA_pad[9] ( .I(PADDO), .PAD(RA9)); + mjiobuf0134 \RA_pad[9] ( .I(PADDO), .PAD(RA9)); specify (PADDO => RA9) = (0:0:0,0:0:0); @@ -3238,7 +3453,7 @@ endmodule module RA_8_ ( input PADDO, output RA8 ); - mjiobuf0120 \RA_pad[8] ( .I(PADDO), .PAD(RA8)); + mjiobuf0134 \RA_pad[8] ( .I(PADDO), .PAD(RA8)); specify (PADDO => RA8) = (0:0:0,0:0:0); @@ -3248,7 +3463,7 @@ endmodule module RA_7_ ( input PADDO, output RA7 ); - mjiobuf0120 \RA_pad[7] ( .I(PADDO), .PAD(RA7)); + mjiobuf0134 \RA_pad[7] ( .I(PADDO), .PAD(RA7)); specify (PADDO => RA7) = (0:0:0,0:0:0); @@ -3258,7 +3473,7 @@ endmodule module RA_6_ ( input PADDO, output RA6 ); - mjiobuf0120 \RA_pad[6] ( .I(PADDO), .PAD(RA6)); + mjiobuf0134 \RA_pad[6] ( .I(PADDO), .PAD(RA6)); specify (PADDO => RA6) = (0:0:0,0:0:0); @@ -3268,7 +3483,7 @@ endmodule module RA_5_ ( input PADDO, output RA5 ); - mjiobuf0120 \RA_pad[5] ( .I(PADDO), .PAD(RA5)); + mjiobuf0134 \RA_pad[5] ( .I(PADDO), .PAD(RA5)); specify (PADDO => RA5) = (0:0:0,0:0:0); @@ -3278,7 +3493,7 @@ endmodule module RA_4_ ( input PADDO, output RA4 ); - mjiobuf0120 \RA_pad[4] ( .I(PADDO), .PAD(RA4)); + mjiobuf0134 \RA_pad[4] ( .I(PADDO), .PAD(RA4)); specify (PADDO => RA4) = (0:0:0,0:0:0); @@ -3288,7 +3503,7 @@ endmodule module RA_3_ ( input PADDO, output RA3 ); - mjiobuf0120 \RA_pad[3] ( .I(PADDO), .PAD(RA3)); + mjiobuf0134 \RA_pad[3] ( .I(PADDO), .PAD(RA3)); specify (PADDO => RA3) = (0:0:0,0:0:0); @@ -3298,7 +3513,7 @@ endmodule module RA_2_ ( input PADDO, output RA2 ); - mjiobuf0120 \RA_pad[2] ( .I(PADDO), .PAD(RA2)); + mjiobuf0134 \RA_pad[2] ( .I(PADDO), .PAD(RA2)); specify (PADDO => RA2) = (0:0:0,0:0:0); @@ -3308,7 +3523,7 @@ endmodule module RA_1_ ( input PADDO, output RA1 ); - mjiobuf0120 \RA_pad[1] ( .I(PADDO), .PAD(RA1)); + mjiobuf0134 \RA_pad[1] ( .I(PADDO), .PAD(RA1)); specify (PADDO => RA1) = (0:0:0,0:0:0); @@ -3318,7 +3533,7 @@ endmodule module RA_0_ ( input PADDO, output RA0 ); - mjiobuf0120 \RA_pad[0] ( .I(PADDO), .PAD(RA0)); + mjiobuf0134 \RA_pad[0] ( .I(PADDO), .PAD(RA0)); specify (PADDO => RA0) = (0:0:0,0:0:0); @@ -3328,7 +3543,7 @@ endmodule module RBA_1_ ( input PADDO, output RBA1 ); - mjiobuf0120 \RBA_pad[1] ( .I(PADDO), .PAD(RBA1)); + mjiobuf0134 \RBA_pad[1] ( .I(PADDO), .PAD(RBA1)); specify (PADDO => RBA1) = (0:0:0,0:0:0); @@ -3338,7 +3553,7 @@ endmodule module RBA_0_ ( input PADDO, output RBA0 ); - mjiobuf0120 \RBA_pad[0] ( .I(PADDO), .PAD(RBA0)); + mjiobuf0134 \RBA_pad[0] ( .I(PADDO), .PAD(RBA0)); specify (PADDO => RBA0) = (0:0:0,0:0:0); @@ -3348,7 +3563,7 @@ endmodule module LED ( input PADDO, output LED ); - mjiobuf0121 LED_pad( .I(PADDO), .PAD(LED)); + mjiobuf0135 LED_pad( .I(PADDO), .PAD(LED)); specify (PADDO => LED) = (0:0:0,0:0:0); @@ -3356,14 +3571,14 @@ module LED ( input PADDO, output LED ); endmodule -module mjiobuf0121 ( input I, output PAD ); +module mjiobuf0135 ( input I, output PAD ); OB INST5( .I(I), .O(PAD)); endmodule module nFWE ( output PADDI, input nFWE ); - mjiobuf0119 nFWE_pad( .Z(PADDI), .PAD(nFWE)); + mjiobuf0133 nFWE_pad( .Z(PADDI), .PAD(nFWE)); specify (nFWE => PADDI) = (0:0:0,0:0:0); @@ -3375,7 +3590,7 @@ endmodule module nCRAS ( output PADDI, input nCRAS ); - mjiobuf0119 nCRAS_pad( .Z(PADDI), .PAD(nCRAS)); + mjiobuf0133 nCRAS_pad( .Z(PADDI), .PAD(nCRAS)); specify (nCRAS => PADDI) = (0:0:0,0:0:0); @@ -3387,7 +3602,7 @@ endmodule module nCCAS ( output PADDI, input nCCAS ); - mjiobuf0119 nCCAS_pad( .Z(PADDI), .PAD(nCCAS)); + mjiobuf0133 nCCAS_pad( .Z(PADDI), .PAD(nCCAS)); specify (nCCAS => PADDI) = (0:0:0,0:0:0); @@ -3399,7 +3614,7 @@ endmodule module Dout_7_ ( input PADDO, output Dout7 ); - mjiobuf0118 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7)); + mjiobuf0132 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7)); specify (PADDO => Dout7) = (0:0:0,0:0:0); @@ -3409,7 +3624,7 @@ endmodule module Dout_6_ ( input PADDO, output Dout6 ); - mjiobuf0118 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6)); + mjiobuf0132 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6)); specify (PADDO => Dout6) = (0:0:0,0:0:0); @@ -3419,7 +3634,7 @@ endmodule module Dout_5_ ( input PADDO, output Dout5 ); - mjiobuf0118 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5)); + mjiobuf0132 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5)); specify (PADDO => Dout5) = (0:0:0,0:0:0); @@ -3429,7 +3644,7 @@ endmodule module Dout_4_ ( input PADDO, output Dout4 ); - mjiobuf0118 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4)); + mjiobuf0132 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4)); specify (PADDO => Dout4) = (0:0:0,0:0:0); @@ -3439,7 +3654,7 @@ endmodule module Dout_3_ ( input PADDO, output Dout3 ); - mjiobuf0118 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3)); + mjiobuf0132 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3)); specify (PADDO => Dout3) = (0:0:0,0:0:0); @@ -3449,7 +3664,7 @@ endmodule module Dout_2_ ( input PADDO, output Dout2 ); - mjiobuf0118 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2)); + mjiobuf0132 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2)); specify (PADDO => Dout2) = (0:0:0,0:0:0); @@ -3459,7 +3674,7 @@ endmodule module Dout_1_ ( input PADDO, output Dout1 ); - mjiobuf0118 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1)); + mjiobuf0132 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1)); specify (PADDO => Dout1) = (0:0:0,0:0:0); @@ -3469,7 +3684,7 @@ endmodule module Din_7_ ( output PADDI, input Din7 ); - mjiobuf0119 \Din_pad[7] ( .Z(PADDI), .PAD(Din7)); + mjiobuf0133 \Din_pad[7] ( .Z(PADDI), .PAD(Din7)); specify (Din7 => PADDI) = (0:0:0,0:0:0); @@ -3481,7 +3696,7 @@ endmodule module Din_6_ ( output PADDI, input Din6 ); - mjiobuf0119 \Din_pad[6] ( .Z(PADDI), .PAD(Din6)); + mjiobuf0133 \Din_pad[6] ( .Z(PADDI), .PAD(Din6)); specify (Din6 => PADDI) = (0:0:0,0:0:0); @@ -3493,7 +3708,7 @@ endmodule module Din_5_ ( output PADDI, input Din5 ); - mjiobuf0119 \Din_pad[5] ( .Z(PADDI), .PAD(Din5)); + mjiobuf0133 \Din_pad[5] ( .Z(PADDI), .PAD(Din5)); specify (Din5 => PADDI) = (0:0:0,0:0:0); @@ -3505,7 +3720,7 @@ endmodule module Din_4_ ( output PADDI, input Din4 ); - mjiobuf0119 \Din_pad[4] ( .Z(PADDI), .PAD(Din4)); + mjiobuf0133 \Din_pad[4] ( .Z(PADDI), .PAD(Din4)); specify (Din4 => PADDI) = (0:0:0,0:0:0); @@ -3517,7 +3732,7 @@ endmodule module Din_3_ ( output PADDI, input Din3 ); - mjiobuf0119 \Din_pad[3] ( .Z(PADDI), .PAD(Din3)); + mjiobuf0133 \Din_pad[3] ( .Z(PADDI), .PAD(Din3)); specify (Din3 => PADDI) = (0:0:0,0:0:0); @@ -3529,7 +3744,7 @@ endmodule module Din_2_ ( output PADDI, input Din2 ); - mjiobuf0119 \Din_pad[2] ( .Z(PADDI), .PAD(Din2)); + mjiobuf0133 \Din_pad[2] ( .Z(PADDI), .PAD(Din2)); specify (Din2 => PADDI) = (0:0:0,0:0:0); @@ -3541,7 +3756,7 @@ endmodule module Din_1_ ( output PADDI, input Din1 ); - mjiobuf0119 \Din_pad[1] ( .Z(PADDI), .PAD(Din1)); + mjiobuf0133 \Din_pad[1] ( .Z(PADDI), .PAD(Din1)); specify (Din1 => PADDI) = (0:0:0,0:0:0); @@ -3553,7 +3768,7 @@ endmodule module Din_0_ ( output PADDI, input Din0 ); - mjiobuf0119 \Din_pad[0] ( .Z(PADDI), .PAD(Din0)); + mjiobuf0133 \Din_pad[0] ( .Z(PADDI), .PAD(Din0)); specify (Din0 => PADDI) = (0:0:0,0:0:0); @@ -3565,7 +3780,7 @@ endmodule module CROW_1_ ( output PADDI, input CROW1 ); - mjiobuf0119 \CROW_pad[1] ( .Z(PADDI), .PAD(CROW1)); + mjiobuf0133 \CROW_pad[1] ( .Z(PADDI), .PAD(CROW1)); specify (CROW1 => PADDI) = (0:0:0,0:0:0); @@ -3577,7 +3792,7 @@ endmodule module CROW_0_ ( output PADDI, input CROW0 ); - mjiobuf0119 \CROW_pad[0] ( .Z(PADDI), .PAD(CROW0)); + mjiobuf0133 \CROW_pad[0] ( .Z(PADDI), .PAD(CROW0)); specify (CROW0 => PADDI) = (0:0:0,0:0:0); @@ -3589,7 +3804,7 @@ endmodule module MAin_9_ ( output PADDI, input MAin9 ); - mjiobuf0119 \MAin_pad[9] ( .Z(PADDI), .PAD(MAin9)); + mjiobuf0133 \MAin_pad[9] ( .Z(PADDI), .PAD(MAin9)); specify (MAin9 => PADDI) = (0:0:0,0:0:0); @@ -3601,7 +3816,7 @@ endmodule module MAin_8_ ( output PADDI, input MAin8 ); - mjiobuf0119 \MAin_pad[8] ( .Z(PADDI), .PAD(MAin8)); + mjiobuf0133 \MAin_pad[8] ( .Z(PADDI), .PAD(MAin8)); specify (MAin8 => PADDI) = (0:0:0,0:0:0); @@ -3613,7 +3828,7 @@ endmodule module MAin_7_ ( output PADDI, input MAin7 ); - mjiobuf0119 \MAin_pad[7] ( .Z(PADDI), .PAD(MAin7)); + mjiobuf0133 \MAin_pad[7] ( .Z(PADDI), .PAD(MAin7)); specify (MAin7 => PADDI) = (0:0:0,0:0:0); @@ -3625,7 +3840,7 @@ endmodule module MAin_6_ ( output PADDI, input MAin6 ); - mjiobuf0119 \MAin_pad[6] ( .Z(PADDI), .PAD(MAin6)); + mjiobuf0133 \MAin_pad[6] ( .Z(PADDI), .PAD(MAin6)); specify (MAin6 => PADDI) = (0:0:0,0:0:0); @@ -3637,7 +3852,7 @@ endmodule module MAin_5_ ( output PADDI, input MAin5 ); - mjiobuf0119 \MAin_pad[5] ( .Z(PADDI), .PAD(MAin5)); + mjiobuf0133 \MAin_pad[5] ( .Z(PADDI), .PAD(MAin5)); specify (MAin5 => PADDI) = (0:0:0,0:0:0); @@ -3649,7 +3864,7 @@ endmodule module MAin_4_ ( output PADDI, input MAin4 ); - mjiobuf0119 \MAin_pad[4] ( .Z(PADDI), .PAD(MAin4)); + mjiobuf0133 \MAin_pad[4] ( .Z(PADDI), .PAD(MAin4)); specify (MAin4 => PADDI) = (0:0:0,0:0:0); @@ -3661,7 +3876,7 @@ endmodule module MAin_3_ ( output PADDI, input MAin3 ); - mjiobuf0119 \MAin_pad[3] ( .Z(PADDI), .PAD(MAin3)); + mjiobuf0133 \MAin_pad[3] ( .Z(PADDI), .PAD(MAin3)); specify (MAin3 => PADDI) = (0:0:0,0:0:0); @@ -3673,7 +3888,7 @@ endmodule module MAin_2_ ( output PADDI, input MAin2 ); - mjiobuf0119 \MAin_pad[2] ( .Z(PADDI), .PAD(MAin2)); + mjiobuf0133 \MAin_pad[2] ( .Z(PADDI), .PAD(MAin2)); specify (MAin2 => PADDI) = (0:0:0,0:0:0); @@ -3685,7 +3900,7 @@ endmodule module MAin_1_ ( output PADDI, input MAin1 ); - mjiobuf0119 \MAin_pad[1] ( .Z(PADDI), .PAD(MAin1)); + mjiobuf0133 \MAin_pad[1] ( .Z(PADDI), .PAD(MAin1)); specify (MAin1 => PADDI) = (0:0:0,0:0:0); @@ -3697,7 +3912,7 @@ endmodule module MAin_0_ ( output PADDI, input MAin0 ); - mjiobuf0119 \MAin_pad[0] ( .Z(PADDI), .PAD(MAin0)); + mjiobuf0133 \MAin_pad[0] ( .Z(PADDI), .PAD(MAin0)); specify (MAin0 => PADDI) = (0:0:0,0:0:0); diff --git a/CPLD/LCMXO640C/impl1/hdla_gen_hierarchy.html b/CPLD/LCMXO640C/impl1/hdla_gen_hierarchy.html index 5ca6705..47c3612 100644 --- a/CPLD/LCMXO640C/impl1/hdla_gen_hierarchy.html +++ b/CPLD/LCMXO640C/impl1/hdla_gen_hierarchy.html @@ -2,8 +2,9 @@ Starting: parse design source files (VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v' (VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-SPI.v' +WARNING - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-SPI.v(23,47-23,52) (VERI-1875) identifier 'Ready' is used before its declaration INFO - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-SPI.v(1,8-1,14) (VERI-1018) compiling module 'RAM2GS' INFO - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-SPI.v(1,1-410,10) (VERI-9000) elaborating module 'RAM2GS' -Done: design load finished with (0) errors, and (0) warnings +Done: design load finished with (0) errors, and (1) warnings \ No newline at end of file diff --git a/CPLD/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1.ior b/CPLD/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1.ior index 9baf2c4..6cc2816 100644 --- a/CPLD/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1.ior +++ b/CPLD/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1.ior @@ -29,7 +29,7 @@ Performance Hardware Data Status: Version 1.124. // Package: TQFP100 // ncd File: ram2gs_lcmxo640c_impl1.ncd // Version: Diamond (64-bit) 3.12.1.454 -// Written on Thu Sep 21 05:38:44 2023 +// Written on Sat Jan 06 06:25:22 2024 // M: Minimum Performance Grade // iotiming RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO640C/promote.xml @@ -41,98 +41,98 @@ Worst Case Results across Performance Grades (M, 5, 4, 3): Port Clock Edge Setup Performance_Grade Hold Performance_Grade ---------------------------------------------------------------------- -CROW[0] nCRAS F -0.012 M 2.299 3 -CROW[1] nCRAS F -0.094 M 2.568 3 -Din[0] PHI2 F 5.117 3 2.324 3 -Din[0] nCCAS F 1.863 3 -0.129 M -Din[1] PHI2 F 4.727 3 3.095 3 -Din[1] nCCAS F 0.973 3 0.261 3 -Din[2] PHI2 F 4.040 3 2.270 3 -Din[2] nCCAS F 1.372 3 -0.027 M -Din[3] PHI2 F 4.809 3 1.454 3 -Din[3] nCCAS F 0.916 3 0.298 3 -Din[4] PHI2 F 6.041 3 2.279 3 -Din[4] nCCAS F 1.531 3 -0.100 M -Din[5] PHI2 F 5.903 3 2.260 3 -Din[5] nCCAS F 2.338 3 -0.268 M -Din[6] PHI2 F 6.028 3 1.422 3 -Din[6] nCCAS F 1.099 3 0.266 3 -Din[7] PHI2 F 6.673 3 2.385 3 -Din[7] nCCAS F 0.940 3 0.417 3 -MAin[0] PHI2 F 4.543 3 0.820 3 -MAin[0] nCRAS F -0.219 M 3.000 3 -MAin[1] PHI2 F 4.179 3 1.515 3 -MAin[1] nCRAS F -0.122 M 2.681 3 -MAin[2] PHI2 F 9.178 3 -0.474 M -MAin[2] nCRAS F -0.219 M 3.000 3 -MAin[3] PHI2 F 9.642 3 -0.572 M -MAin[3] nCRAS F -0.200 M 2.949 3 -MAin[4] PHI2 F 9.311 3 -0.515 M -MAin[4] nCRAS F 0.454 3 1.905 3 -MAin[5] PHI2 F 8.033 3 -0.256 M -MAin[5] nCRAS F -0.214 M 2.985 3 -MAin[6] PHI2 F 8.467 3 -0.339 M -MAin[6] nCRAS F 0.019 3 2.253 3 -MAin[7] PHI2 F 8.283 3 -0.303 M -MAin[7] nCRAS F -0.200 M 2.949 3 -MAin[8] nCRAS F -0.239 M 3.098 3 -MAin[9] nCRAS F -0.200 M 2.952 3 +CROW[0] nCRAS F -0.112 M 2.651 3 +CROW[1] nCRAS F -0.021 M 2.351 3 +Din[0] PHI2 F 4.317 3 1.888 3 +Din[0] nCCAS F 1.401 3 -0.032 M +Din[1] PHI2 F 6.362 3 2.174 3 +Din[1] nCCAS F 0.920 3 0.293 3 +Din[2] PHI2 F 4.582 3 1.108 3 +Din[2] nCCAS F 1.367 3 -0.025 M +Din[3] PHI2 F 6.558 3 2.698 3 +Din[3] nCCAS F 0.619 3 0.544 3 +Din[4] PHI2 F 7.083 3 0.535 3 +Din[4] nCCAS F 0.558 3 0.857 3 +Din[5] PHI2 F 6.015 3 2.171 3 +Din[5] nCCAS F 0.035 3 1.300 3 +Din[6] PHI2 F 6.445 3 1.417 3 +Din[6] nCCAS F 1.089 3 0.272 3 +Din[7] PHI2 F 6.645 3 2.275 3 +Din[7] nCCAS F 0.961 3 0.396 3 +MAin[0] PHI2 F 7.871 3 -0.129 M +MAin[0] nCRAS F -0.325 M 3.376 3 +MAin[1] PHI2 F 8.822 3 -0.149 M +MAin[1] nCRAS F -0.467 M 3.889 3 +MAin[2] PHI2 F 7.393 3 0.809 3 +MAin[2] nCRAS F -0.468 M 3.890 3 +MAin[3] PHI2 F 8.567 3 -0.143 M +MAin[3] nCRAS F -0.148 M 2.780 3 +MAin[4] PHI2 F 9.168 3 -0.113 M +MAin[4] nCRAS F 0.492 3 1.836 3 +MAin[5] PHI2 F 7.300 3 0.076 3 +MAin[5] nCRAS F -0.108 M 2.641 3 +MAin[6] PHI2 F 8.643 3 -0.385 M +MAin[6] nCRAS F -0.216 M 2.988 3 +MAin[7] PHI2 F 7.923 3 -0.224 M +MAin[7] nCRAS F -0.325 M 3.376 3 +MAin[8] nCRAS F -0.328 M 3.387 3 +MAin[9] nCRAS F -0.352 M 3.481 3 PHI2 RCLK R 2.024 3 -0.115 M -UFMSDO RCLK R 2.747 3 -0.023 M -nCCAS RCLK R 1.461 3 0.049 3 -nCCAS nCRAS F 0.041 3 2.233 3 -nCRAS RCLK R 1.492 3 0.026 3 -nFWE PHI2 F 9.958 3 -0.643 M -nFWE nCRAS F -0.200 M 2.952 3 +UFMSDO RCLK R 2.286 3 -0.106 M +nCCAS RCLK R 3.326 3 -0.370 M +nCCAS nCRAS F 0.813 3 1.646 3 +nCRAS RCLK R 5.235 3 -0.614 M +nFWE PHI2 F 5.814 3 0.503 3 +nFWE nCRAS F 0.183 3 2.096 3 // Clock to Output Delay Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade ------------------------------------------------------------------------ -LED RCLK R 13.643 3 4.416 M -LED nCRAS F 18.132 3 5.318 M -RA[0] RCLK R 10.790 3 2.216 M -RA[0] nCRAS F 13.344 3 2.709 M +LED RCLK R 16.515 3 4.482 M +LED nCRAS F 17.585 3 5.197 M +RA[0] RCLK R 11.366 3 2.326 M +RA[0] nCRAS F 13.548 3 2.745 M RA[10] RCLK R 6.926 3 1.431 M RA[11] PHI2 R 9.183 3 1.867 M -RA[1] RCLK R 11.242 3 2.314 M -RA[1] nCRAS F 14.215 3 2.899 M -RA[2] RCLK R 10.691 3 2.207 M -RA[2] nCRAS F 13.021 3 2.641 M -RA[3] RCLK R 11.553 3 2.371 M -RA[3] nCRAS F 13.307 3 2.703 M -RA[4] RCLK R 10.653 3 2.186 M -RA[4] nCRAS F 12.915 3 2.624 M -RA[5] RCLK R 11.976 3 2.463 M -RA[5] nCRAS F 13.269 3 2.696 M -RA[6] RCLK R 9.986 3 2.078 M -RA[6] nCRAS F 12.404 3 2.531 M -RA[7] RCLK R 10.257 3 2.107 M -RA[7] nCRAS F 12.647 3 2.563 M -RA[8] RCLK R 11.577 3 2.383 M -RA[8] nCRAS F 13.570 3 2.740 M -RA[9] RCLK R 11.562 3 2.371 M -RA[9] nCRAS F 14.266 3 2.895 M -RBA[0] nCRAS F 10.698 3 2.157 M -RBA[1] nCRAS F 12.177 3 2.478 M +RA[1] RCLK R 9.283 3 1.909 M +RA[1] nCRAS F 12.064 3 2.463 M +RA[2] RCLK R 11.466 3 2.345 M +RA[2] nCRAS F 13.609 3 2.759 M +RA[3] RCLK R 10.239 3 2.114 M +RA[3] nCRAS F 12.115 3 2.471 M +RA[4] RCLK R 10.462 3 2.158 M +RA[4] nCRAS F 12.460 3 2.541 M +RA[5] RCLK R 11.714 3 2.410 M +RA[5] nCRAS F 14.027 3 2.856 M +RA[6] RCLK R 10.222 3 2.111 M +RA[6] nCRAS F 12.507 3 2.549 M +RA[7] RCLK R 10.118 3 2.066 M +RA[7] nCRAS F 13.612 3 2.768 M +RA[8] RCLK R 11.860 3 2.450 M +RA[8] nCRAS F 13.529 3 2.745 M +RA[9] RCLK R 11.723 3 2.414 M +RA[9] nCRAS F 14.189 3 2.884 M +RBA[0] nCRAS F 12.165 3 2.476 M +RBA[1] nCRAS F 10.690 3 2.155 M RCKE RCLK R 6.926 3 1.431 M -RDQMH RCLK R 11.068 3 2.337 M -RDQML RCLK R 11.619 3 2.421 M -RD[0] nCCAS F 8.787 3 1.927 M -RD[1] nCCAS F 8.785 3 1.927 M -RD[2] nCCAS F 8.076 3 1.799 M -RD[3] nCCAS F 9.246 3 2.027 M -RD[4] nCCAS F 9.626 3 2.112 M -RD[5] nCCAS F 9.183 3 2.015 M -RD[6] nCCAS F 8.537 3 1.898 M -RD[7] nCCAS F 9.704 3 2.117 M +RDQMH RCLK R 12.309 3 2.582 M +RDQML RCLK R 11.893 3 2.496 M +RD[0] nCCAS F 8.780 3 1.926 M +RD[1] nCCAS F 8.780 3 1.926 M +RD[2] nCCAS F 8.071 3 1.798 M +RD[3] nCCAS F 9.242 3 2.016 M +RD[4] nCCAS F 11.095 3 2.414 M +RD[5] nCCAS F 10.651 3 2.326 M +RD[6] nCCAS F 8.532 3 1.897 M +RD[7] nCCAS F 9.699 3 2.116 M UFMCLK RCLK R 8.800 3 1.847 M UFMSDI RCLK R 8.079 3 1.714 M nRCAS RCLK R 6.926 3 1.431 M -nRCS RCLK R 7.765 3 1.590 M -nRRAS RCLK R 8.554 3 1.749 M -nRWE RCLK R 8.704 3 1.789 M +nRCS RCLK R 6.926 3 1.431 M +nRRAS RCLK R 8.147 3 1.667 M +nRWE RCLK R 9.027 3 1.858 M nUFMCS RCLK R 9.262 3 1.937 M WARNING: you must also run trce with hold speed: 3 WARNING: you must also run trce with setup speed: M diff --git a/CPLD/LCMXO640C/promote.xml b/CPLD/LCMXO640C/promote.xml index af7aa8c..0cb94a1 100644 --- a/CPLD/LCMXO640C/promote.xml +++ b/CPLD/LCMXO640C/promote.xml @@ -1,3 +1,3 @@ - + diff --git a/CPLD/MAXII/RAM2GS.qsf b/CPLD/MAXII/RAM2GS.qsf index 8995f70..cf84bf8 100644 --- a/CPLD/MAXII/RAM2GS.qsf +++ b/CPLD/MAXII/RAM2GS.qsf @@ -243,5 +243,5 @@ set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to RD set_global_assignment -name SDC_FILE ../RAM2GS.sdc set_global_assignment -name VERILOG_FILE "../RAM2GS-MAX.v" set_global_assignment -name QIP_FILE UFM.qip -set_global_assignment -name MIF_FILE ../RAM2GS.mif +set_global_assignment -name MIF_FILE ../RAM2GS-MAX.mif set_global_assignment -name SDC_FILE "../RAM2GS-MAX.sdc" diff --git a/CPLD/MAXII/RAM2GS.qws b/CPLD/MAXII/RAM2GS.qws index 69d8d37..a9b01ed 100644 Binary files a/CPLD/MAXII/RAM2GS.qws and b/CPLD/MAXII/RAM2GS.qws differ diff --git a/CPLD/MAXII/UFM.v b/CPLD/MAXII/UFM.v index 9f27eeb..37a1e5f 100644 --- a/CPLD/MAXII/UFM.v +++ b/CPLD/MAXII/UFM.v @@ -34,7 +34,7 @@ //https://fpgasoftware.intel.com/eula. -//altufm_none CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="MAX II" ERASE_TIME=500000000 LPM_FILE="D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/RAM2GS.mif" OSC_FREQUENCY=180000 PORT_ARCLKENA="PORT_UNUSED" PORT_DRCLKENA="PORT_UNUSED" PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 arclk ardin arshft busy drclk drdin drdout drshft erase osc oscena program rtpbusy +//altufm_none CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="MAX II" ERASE_TIME=500000000 LPM_FILE="D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/RAM2GS-MAX.mif" OSC_FREQUENCY=180000 PORT_ARCLKENA="PORT_UNUSED" PORT_DRCLKENA="PORT_UNUSED" PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 arclk ardin arshft busy drclk drdin drdout drshft erase osc oscena program rtpbusy //VERSION_BEGIN 19.1 cbx_a_gray2bin 2019:09:22:11:00:27:SJ cbx_a_graycounter 2019:09:22:11:00:27:SJ cbx_altufm_none 2019:09:22:11:00:28:SJ cbx_cycloneii 2019:09:22:11:00:28:SJ cbx_lpm_add_sub 2019:09:22:11:00:28:SJ cbx_lpm_compare 2019:09:22:11:00:28:SJ cbx_lpm_counter 2019:09:22:11:00:28:SJ cbx_lpm_decode 2019:09:22:11:00:28:SJ cbx_lpm_mux 2019:09:22:11:00:28:SJ cbx_maxii 2019:09:22:11:00:28:SJ cbx_mgl 2019:09:22:11:02:15:SJ cbx_nadder 2019:09:22:11:00:28:SJ cbx_stratix 2019:09:22:11:00:28:SJ cbx_stratixii 2019:09:22:11:00:28:SJ cbx_util_mgl 2019:09:22:11:00:28:SJ VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 @@ -118,7 +118,7 @@ module UFM_altufm_none_unv defparam maxii_ufm_block1.address_width = 9, maxii_ufm_block1.erase_time = 500000000, - maxii_ufm_block1.init_file = "RAM2GS.mif", + maxii_ufm_block1.init_file = "../RAM2GS-MAX.mif", maxii_ufm_block1.osc_sim_setting = 180000, maxii_ufm_block1.program_time = 1600000, maxii_ufm_block1.lpm_type = "maxii_ufm"; @@ -209,7 +209,7 @@ endmodule // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX II" // Retrieval info: CONSTANT: ERASE_TIME NUMERIC "500000000" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX II" -// Retrieval info: CONSTANT: LPM_FILE STRING "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\MAXII\RAM2GS.mif" +// Retrieval info: CONSTANT: LPM_FILE STRING "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\MAXII\RAM2GS-MAX.mif" // Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" // Retrieval info: CONSTANT: LPM_TYPE STRING "altufm_none" // Retrieval info: CONSTANT: OSC_FREQUENCY NUMERIC "180000" diff --git a/CPLD/MAXII/output_files/RAM2GS.asm.rpt b/CPLD/MAXII/output_files/RAM2GS.asm.rpt index e2d7300..81e797a 100644 --- a/CPLD/MAXII/output_files/RAM2GS.asm.rpt +++ b/CPLD/MAXII/output_files/RAM2GS.asm.rpt @@ -1,5 +1,5 @@ Assembler report for RAM2GS -Sat Sep 30 04:44:05 2023 +Sat Nov 11 04:34:48 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition @@ -10,7 +10,7 @@ Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Editio 2. Assembler Summary 3. Assembler Settings 4. Assembler Generated Files - 5. Assembler Device Options: /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pof + 5. Assembler Device Options: Y:/Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pof 6. Assembler Messages @@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Sat Sep 30 04:44:05 2023 ; +; Assembler Status ; Successful - Sat Nov 11 04:34:48 2023 ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; ; Family ; MAX II ; @@ -53,23 +53,23 @@ https://fpgasoftware.intel.com/eula. +--------+---------+---------------+ -+--------------------------------------------------+ -; Assembler Generated Files ; -+--------------------------------------------------+ -; File Name ; -+--------------------------------------------------+ -; /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pof ; -+--------------------------------------------------+ ++----------------------------------------------------+ +; Assembler Generated Files ; ++----------------------------------------------------+ +; File Name ; ++----------------------------------------------------+ +; Y:/Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pof ; ++----------------------------------------------------+ -+----------------------------------------------------------------------------+ -; Assembler Device Options: /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pof ; -+----------------+-----------------------------------------------------------+ -; Option ; Setting ; -+----------------+-----------------------------------------------------------+ -; JTAG usercode ; 0x00171B9B ; -; Checksum ; 0x00171E13 ; -+----------------+-----------------------------------------------------------+ ++------------------------------------------------------------------------------+ +; Assembler Device Options: Y:/Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pof ; ++----------------+-------------------------------------------------------------+ +; Option ; Setting ; ++----------------+-------------------------------------------------------------+ +; JTAG usercode ; 0x00171B9B ; +; Checksum ; 0x00171E13 ; ++----------------+-------------------------------------------------------------+ +--------------------+ @@ -78,13 +78,13 @@ https://fpgasoftware.intel.com/eula. Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition - Info: Processing started: Sat Sep 30 04:44:04 2023 + Info: Processing started: Sat Nov 11 04:34:47 2023 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 13095 megabytes - Info: Processing ended: Sat Sep 30 04:44:05 2023 + Info: Peak virtual memory: 13069 megabytes + Info: Processing ended: Sat Nov 11 04:34:48 2023 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/CPLD/MAXII/output_files/RAM2GS.done b/CPLD/MAXII/output_files/RAM2GS.done index 27c4db7..bb6cfa6 100644 --- a/CPLD/MAXII/output_files/RAM2GS.done +++ b/CPLD/MAXII/output_files/RAM2GS.done @@ -1 +1 @@ -Sat Sep 30 04:44:09 2023 +Sat Nov 11 04:34:52 2023 diff --git a/CPLD/MAXII/output_files/RAM2GS.fit.rpt b/CPLD/MAXII/output_files/RAM2GS.fit.rpt index cebdd9c..6e58399 100644 --- a/CPLD/MAXII/output_files/RAM2GS.fit.rpt +++ b/CPLD/MAXII/output_files/RAM2GS.fit.rpt @@ -1,5 +1,5 @@ Fitter report for RAM2GS -Sat Sep 30 04:44:02 2023 +Sat Nov 11 04:34:44 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition @@ -59,7 +59,7 @@ https://fpgasoftware.intel.com/eula. +-------------------------------------------------------------------------------------+ ; Fitter Summary ; +-----------------------+-------------------------------------------------------------+ -; Fitter Status ; Successful - Sat Sep 30 04:44:02 2023 ; +; Fitter Status ; Successful - Sat Nov 11 04:34:44 2023 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; @@ -131,20 +131,20 @@ https://fpgasoftware.intel.com/eula. ; Number detected on machine ; 4 ; ; Maximum allowed ; 4 ; ; ; ; -; Average used ; 1.04 ; +; Average used ; 1.02 ; ; Maximum used ; 4 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 1.5% ; -; Processors 3-4 ; 1.2% ; +; Processor 2 ; 0.7% ; +; Processors 3-4 ; 0.7% ; +----------------------------+-------------+ +--------------+ ; Pin-Out File ; +--------------+ -The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pin. +The pin-out file can be found in Y:/Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pin. +---------------------------------------------------------------------+ @@ -710,19 +710,19 @@ Info (332111): Found 6 clocks Info (332111): 350.000 PHI2 Info (332111): 16.000 RCLK Info (186079): Completed User Assigned Global Signals Promotion Operation -Info (186215): Automatically promoted signal "RCLK" to use Global clock in PIN 12 File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 41 -Info (186216): Automatically promoted some destinations of signal "PHI2" to use Global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 8 - Info (186217): Destination "PHI2r" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 14 -Info (186228): Pin "PHI2" drives global clock, but is not placed in a dedicated clock pin position File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 8 -Info (186216): Automatically promoted some destinations of signal "nCRAS" to use Global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11 - Info (186217): Destination "LED~0" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 22 - Info (186217): Destination "RASr" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 15 -Info (186228): Pin "nCRAS" drives global clock, but is not placed in a dedicated clock pin position File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11 -Info (186216): Automatically promoted some destinations of signal "nCCAS" to use Global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11 - Info (186217): Destination "CBR" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 18 - Info (186217): Destination "RD~16" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 60 - Info (186217): Destination "CASr" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 16 -Info (186228): Pin "nCCAS" drives global clock, but is not placed in a dedicated clock pin position File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11 +Info (186215): Automatically promoted signal "RCLK" to use Global clock in PIN 12 File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 41 +Info (186216): Automatically promoted some destinations of signal "PHI2" to use Global clock File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 8 + Info (186217): Destination "PHI2r" may be non-global or may not use global clock File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 14 +Info (186228): Pin "PHI2" drives global clock, but is not placed in a dedicated clock pin position File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 8 +Info (186216): Automatically promoted some destinations of signal "nCRAS" to use Global clock File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11 + Info (186217): Destination "LED~0" may be non-global or may not use global clock File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 22 + Info (186217): Destination "RASr" may be non-global or may not use global clock File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 15 +Info (186228): Pin "nCRAS" drives global clock, but is not placed in a dedicated clock pin position File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11 +Info (186216): Automatically promoted some destinations of signal "nCCAS" to use Global clock File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11 + Info (186217): Destination "CBR" may be non-global or may not use global clock File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 18 + Info (186217): Destination "RD~16" may be non-global or may not use global clock File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 60 + Info (186217): Destination "CASr" may be non-global or may not use global clock File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 16 +Info (186228): Pin "nCCAS" drives global clock, but is not placed in a dedicated clock pin position File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11 Info (186079): Completed Auto Global Promotion Operation Info (176234): Starting register packing Info (186468): Started processing fast register assignments @@ -734,26 +734,26 @@ Info (170189): Fitter placement preparation operations beginning Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful -Info (170192): Fitter placement operations ending: elapsed time is 00:00:01 +Info (170192): Fitter placement operations ending: elapsed time is 00:00:02 Info (170193): Fitter routing operations beginning Info (170195): Router estimated average interconnect usage is 20% of the available device resources Info (170196): Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info (170201): Optimizations that may affect the design's routability were skipped -Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 -Info (11888): Total time spent on timing analysis during the Fitter is 0.54 seconds. +Info (170194): Fitter routing operations ending: elapsed time is 00:00:01 +Info (11888): Total time spent on timing analysis during the Fitter is 1.63 seconds. Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 -Info (144001): Generated suppressed messages file /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg +Info (144001): Generated suppressed messages file Y:/Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg Info: Quartus Prime Fitter was successful. 0 errors, 1 warning - Info: Peak virtual memory: 13771 megabytes - Info: Processing ended: Sat Sep 30 04:44:02 2023 - Info: Elapsed time: 00:00:05 - Info: Total CPU time (on all processors): 00:00:04 + Info: Peak virtual memory: 13745 megabytes + Info: Processing ended: Sat Nov 11 04:34:45 2023 + Info: Elapsed time: 00:00:06 + Info: Total CPU time (on all processors): 00:00:03 +----------------------------+ ; Fitter Suppressed Messages ; +----------------------------+ -The suppressed messages can be found in /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg. +The suppressed messages can be found in Y:/Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg. diff --git a/CPLD/MAXII/output_files/RAM2GS.fit.summary b/CPLD/MAXII/output_files/RAM2GS.fit.summary index 455e016..81a9186 100644 --- a/CPLD/MAXII/output_files/RAM2GS.fit.summary +++ b/CPLD/MAXII/output_files/RAM2GS.fit.summary @@ -1,4 +1,4 @@ -Fitter Status : Successful - Sat Sep 30 04:44:02 2023 +Fitter Status : Successful - Sat Nov 11 04:34:44 2023 Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition Revision Name : RAM2GS Top-level Entity Name : RAM2GS diff --git a/CPLD/MAXII/output_files/RAM2GS.flow.rpt b/CPLD/MAXII/output_files/RAM2GS.flow.rpt index 656020a..50efc1d 100644 --- a/CPLD/MAXII/output_files/RAM2GS.flow.rpt +++ b/CPLD/MAXII/output_files/RAM2GS.flow.rpt @@ -1,5 +1,5 @@ Flow report for RAM2GS -Sat Sep 30 04:44:08 2023 +Sat Nov 11 04:34:51 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition @@ -41,7 +41,7 @@ https://fpgasoftware.intel.com/eula. +-------------------------------------------------------------------------------------+ ; Flow Summary ; +-----------------------+-------------------------------------------------------------+ -; Flow Status ; Successful - Sat Sep 30 04:44:05 2023 ; +; Flow Status ; Successful - Sat Nov 11 04:34:48 2023 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; @@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 09/30/2023 04:43:31 ; +; Start date & time ; 11/11/2023 04:34:01 ; ; Main task ; Compilation ; ; Revision Name ; RAM2GS ; +-------------------+---------------------+ @@ -71,7 +71,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------+------------------------------+---------------+-------------+------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +---------------------------------------+------------------------------+---------------+-------------+------------+ -; COMPILER_SIGNATURE_ID ; 121381084694.169606341108100 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 121381084694.169969524117992 ; -- ; -- ; -- ; ; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; ; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; ; NUM_PARALLEL_PROCESSORS ; 4 ; -- ; -- ; -- ; @@ -86,11 +86,11 @@ https://fpgasoftware.intel.com/eula. +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:26 ; 1.0 ; 13133 MB ; 00:00:44 ; -; Fitter ; 00:00:05 ; 1.0 ; 13771 MB ; 00:00:04 ; -; Assembler ; 00:00:01 ; 1.0 ; 13095 MB ; 00:00:01 ; -; Timing Analyzer ; 00:00:02 ; 1.0 ; 13092 MB ; 00:00:01 ; -; Total ; 00:00:34 ; -- ; -- ; 00:00:50 ; +; Analysis & Synthesis ; 00:00:37 ; 1.0 ; 13126 MB ; 00:00:42 ; +; Fitter ; 00:00:05 ; 1.0 ; 13745 MB ; 00:00:03 ; +; Assembler ; 00:00:02 ; 1.0 ; 13069 MB ; 00:00:01 ; +; Timing Analyzer ; 00:00:02 ; 1.0 ; 13065 MB ; 00:00:01 ; +; Total ; 00:00:46 ; -- ; -- ; 00:00:47 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/CPLD/MAXII/output_files/RAM2GS.jdi b/CPLD/MAXII/output_files/RAM2GS.jdi index c51e41b..1fa86e5 100644 --- a/CPLD/MAXII/output_files/RAM2GS.jdi +++ b/CPLD/MAXII/output_files/RAM2GS.jdi @@ -1,6 +1,6 @@ - + diff --git a/CPLD/MAXII/output_files/RAM2GS.map.rpt b/CPLD/MAXII/output_files/RAM2GS.map.rpt index a61e3c4..ab0e280 100644 --- a/CPLD/MAXII/output_files/RAM2GS.map.rpt +++ b/CPLD/MAXII/output_files/RAM2GS.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for RAM2GS -Sat Sep 30 04:43:56 2023 +Sat Nov 11 04:34:37 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition @@ -46,7 +46,7 @@ https://fpgasoftware.intel.com/eula. +-------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+-------------------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Sat Sep 30 04:43:56 2023 ; +; Analysis & Synthesis Status ; Successful - Sat Nov 11 04:34:37 2023 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; @@ -146,15 +146,15 @@ https://fpgasoftware.intel.com/eula. +----------------------------+-------------+ -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Source Files Read ; -+----------------------------------+-----------------+----------------------------------+-------------------------------------------------+---------+ -; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; -+----------------------------------+-----------------+----------------------------------+-------------------------------------------------+---------+ -; ../RAM2GS-MAX.v ; yes ; User Verilog HDL File ; //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v ; ; -; UFM.v ; yes ; User Wizard-Generated File ; //Mac/iCloud/Repos/RAM2GS/CPLD/MAXII/UFM.v ; ; -; ../RAM2GS.mif ; yes ; User Memory Initialization File ; //Mac/iCloud/Repos/RAM2GS/CPLD/MAXII/RAM2GS.mif ; ; -+----------------------------------+-----------------+----------------------------------+-------------------------------------------------+---------+ ++---------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+----------------------------------+-------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+----------------------------------+-------------------------------------+---------+ +; ../RAM2GS-MAX.v ; yes ; User Verilog HDL File ; Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v ; ; +; UFM.v ; yes ; User Wizard-Generated File ; Y:/Repos/RAM2GS/CPLD/MAXII/UFM.v ; ; +; ../RAM2GS-MAX.mif ; yes ; User Memory Initialization File ; Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.mif ; ; ++----------------------------------+-----------------+----------------------------------+-------------------------------------+---------+ +-----------------------------------------------------+ @@ -269,42 +269,42 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition - Info: Processing started: Sat Sep 30 04:43:30 2023 + Info: Processing started: Sat Nov 11 04:34:00 2023 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS Info (20032): Parallel compilation is enabled and will use up to 4 processors -Info (12021): Found 1 design units, including 1 entities, in source file //mac/icloud/repos/ram2gs/cpld/ram2gs-max.v - Info (12023): Found entity 1: RAM2GS File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 1 +Info (12021): Found 1 design units, including 1 entities, in source file /repos/ram2gs/cpld/ram2gs-max.v + Info (12023): Found entity 1: RAM2GS File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 1 Info (12021): Found 2 design units, including 2 entities, in source file ufm.v - Info (12023): Found entity 1: UFM_altufm_none_unv File: //Mac/iCloud/Repos/RAM2GS/CPLD/MAXII/UFM.v Line: 47 - Info (12023): Found entity 2: UFM File: //Mac/iCloud/Repos/RAM2GS/CPLD/MAXII/UFM.v Line: 150 + Info (12023): Found entity 1: UFM_altufm_none_unv File: Y:/Repos/RAM2GS/CPLD/MAXII/UFM.v Line: 47 + Info (12023): Found entity 2: UFM File: Y:/Repos/RAM2GS/CPLD/MAXII/UFM.v Line: 150 Info (12127): Elaborating entity "RAM2GS" for the top level hierarchy -Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 92 -Info (12128): Elaborating entity "UFM_altufm_none_unv" for hierarchy "UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component" File: //Mac/iCloud/Repos/RAM2GS/CPLD/MAXII/UFM.v Line: 201 -Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 -Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 -Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 -Warning (14632): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 -Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 -Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 -Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 -Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 +Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 92 +Info (12128): Elaborating entity "UFM_altufm_none_unv" for hierarchy "UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component" File: Y:/Repos/RAM2GS/CPLD/MAXII/UFM.v Line: 201 +Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 +Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 +Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 +Warning (14632): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 +Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 +Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 +Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 +Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 Info (21057): Implemented 260 device resources after synthesis - the final resource count might be different Info (21058): Implemented 25 input pins Info (21059): Implemented 30 output pins Info (21060): Implemented 8 bidirectional pins Info (21061): Implemented 196 logic cells Info (21070): Implemented 1 User Flash Memory blocks -Info (144001): Generated suppressed messages file /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg +Info (144001): Generated suppressed messages file Y:/Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 8 warnings - Info: Peak virtual memory: 13133 megabytes - Info: Processing ended: Sat Sep 30 04:43:56 2023 - Info: Elapsed time: 00:00:26 - Info: Total CPU time (on all processors): 00:00:44 + Info: Peak virtual memory: 13126 megabytes + Info: Processing ended: Sat Nov 11 04:34:37 2023 + Info: Elapsed time: 00:00:37 + Info: Total CPU time (on all processors): 00:00:42 +------------------------------------------+ ; Analysis & Synthesis Suppressed Messages ; +------------------------------------------+ -The suppressed messages can be found in /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg. +The suppressed messages can be found in Y:/Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg. diff --git a/CPLD/MAXII/output_files/RAM2GS.map.smsg b/CPLD/MAXII/output_files/RAM2GS.map.smsg index af9ed7c..7f1e460 100644 --- a/CPLD/MAXII/output_files/RAM2GS.map.smsg +++ b/CPLD/MAXII/output_files/RAM2GS.map.smsg @@ -1,3 +1,3 @@ -Warning (10273): Verilog HDL warning at RAM2GS-MAX.v(61): extended using "x" or "z" File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 61 -Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: //Mac/iCloud/Repos/RAM2GS/CPLD/MAXII/UFM.v Line: 73 -Warning (10463): Verilog HDL Declaration warning at UFM.v(173): "program" is SystemVerilog-2005 keyword File: //Mac/iCloud/Repos/RAM2GS/CPLD/MAXII/UFM.v Line: 173 +Warning (10273): Verilog HDL warning at RAM2GS-MAX.v(61): extended using "x" or "z" File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 61 +Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: Y:/Repos/RAM2GS/CPLD/MAXII/UFM.v Line: 73 +Warning (10463): Verilog HDL Declaration warning at UFM.v(173): "program" is SystemVerilog-2005 keyword File: Y:/Repos/RAM2GS/CPLD/MAXII/UFM.v Line: 173 diff --git a/CPLD/MAXII/output_files/RAM2GS.map.summary b/CPLD/MAXII/output_files/RAM2GS.map.summary index 4140741..9a2a664 100644 --- a/CPLD/MAXII/output_files/RAM2GS.map.summary +++ b/CPLD/MAXII/output_files/RAM2GS.map.summary @@ -1,4 +1,4 @@ -Analysis & Synthesis Status : Successful - Sat Sep 30 04:43:56 2023 +Analysis & Synthesis Status : Successful - Sat Nov 11 04:34:37 2023 Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition Revision Name : RAM2GS Top-level Entity Name : RAM2GS diff --git a/CPLD/MAXII/output_files/RAM2GS.sta.rpt b/CPLD/MAXII/output_files/RAM2GS.sta.rpt index 171193f..90a6e87 100644 --- a/CPLD/MAXII/output_files/RAM2GS.sta.rpt +++ b/CPLD/MAXII/output_files/RAM2GS.sta.rpt @@ -1,5 +1,5 @@ Timing Analyzer report for RAM2GS -Sat Sep 30 04:44:08 2023 +Sat Nov 11 04:34:51 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition @@ -88,7 +88,7 @@ https://fpgasoftware.intel.com/eula. ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 0.1% ; +; Processor 2 ; 0.0% ; +----------------------------+-------------+ @@ -97,8 +97,8 @@ https://fpgasoftware.intel.com/eula. +-------------------+--------+--------------------------+ ; SDC File Path ; Status ; Read at ; +-------------------+--------+--------------------------+ -; ../RAM2GS.sdc ; OK ; Sat Sep 30 04:44:07 2023 ; -; ../RAM2GS-MAX.sdc ; OK ; Sat Sep 30 04:44:07 2023 ; +; ../RAM2GS.sdc ; OK ; Sat Nov 11 04:34:51 2023 ; +; ../RAM2GS-MAX.sdc ; OK ; Sat Nov 11 04:34:51 2023 ; +-------------------+--------+--------------------------+ @@ -959,7 +959,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition - Info: Processing started: Sat Sep 30 04:44:06 2023 + Info: Processing started: Sat Nov 11 04:34:49 2023 Info: Command: quartus_sta RAM2GS-MAXII -c RAM2GS Info: qsta_default_script.tcl version: #1 Info (20032): Parallel compilation is enabled and will use up to 4 processors @@ -1003,8 +1003,8 @@ Info (332001): The selected device family is not supported by the report_metasta Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning - Info: Peak virtual memory: 13092 megabytes - Info: Processing ended: Sat Sep 30 04:44:08 2023 + Info: Peak virtual memory: 13065 megabytes + Info: Processing ended: Sat Nov 11 04:34:51 2023 Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:01 diff --git a/CPLD/MAXV/RAM2GS.mif b/CPLD/MAXV/RAM2GS.mif deleted file mode 100644 index 4b2ca5a..0000000 --- a/CPLD/MAXV/RAM2GS.mif +++ /dev/null @@ -1,28 +0,0 @@ --- Copyright (C) 2019 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and any partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details, at --- https://fpgasoftware.intel.com/eula. - --- Quartus Prime generated Memory Initialization File (.mif) - -WIDTH=16; -DEPTH=512; - -ADDRESS_RADIX=HEX; -DATA_RADIX=HEX; - -CONTENT BEGIN - [000..0FD] : 0000; - 0FE : 7FFF; - [0FF..1FF] : FFFF; -END; diff --git a/CPLD/MAXV/RAM2GS.qsf b/CPLD/MAXV/RAM2GS.qsf index 2da8e4f..d4c5d58 100644 --- a/CPLD/MAXV/RAM2GS.qsf +++ b/CPLD/MAXV/RAM2GS.qsf @@ -243,5 +243,5 @@ set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to RD set_global_assignment -name SDC_FILE ../RAM2GS.sdc set_global_assignment -name VERILOG_FILE "../RAM2GS-MAX.v" set_global_assignment -name QIP_FILE UFM.qip -set_global_assignment -name MIF_FILE ../RAM2GS.mif +set_global_assignment -name MIF_FILE ../RAM2GS-MAX.mif set_global_assignment -name SDC_FILE "../RAM2GS-MAX.sdc" diff --git a/CPLD/MAXV/RAM2GS.qws b/CPLD/MAXV/RAM2GS.qws index 69d8d37..a9b01ed 100644 Binary files a/CPLD/MAXV/RAM2GS.qws and b/CPLD/MAXV/RAM2GS.qws differ diff --git a/CPLD/MAXV/UFM.v b/CPLD/MAXV/UFM.v index b863c22..4fbbaf6 100644 --- a/CPLD/MAXV/UFM.v +++ b/CPLD/MAXV/UFM.v @@ -34,7 +34,7 @@ //https://fpgasoftware.intel.com/eula. -//altufm_none CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="MAX V" ERASE_TIME=500000000 LPM_FILE="RAM2GS.mif" OSC_FREQUENCY=180000 PORT_ARCLKENA="PORT_UNUSED" PORT_DRCLKENA="PORT_UNUSED" PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 arclk ardin arshft busy drclk drdin drdout drshft erase osc oscena program rtpbusy +//altufm_none CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="MAX V" ERASE_TIME=500000000 LPM_FILE="RAM2GS-MAX.mif" OSC_FREQUENCY=180000 PORT_ARCLKENA="PORT_UNUSED" PORT_DRCLKENA="PORT_UNUSED" PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 arclk ardin arshft busy drclk drdin drdout drshft erase osc oscena program rtpbusy //VERSION_BEGIN 19.1 cbx_a_gray2bin 2019:09:22:11:00:27:SJ cbx_a_graycounter 2019:09:22:11:00:27:SJ cbx_altufm_none 2019:09:22:11:00:28:SJ cbx_cycloneii 2019:09:22:11:00:28:SJ cbx_lpm_add_sub 2019:09:22:11:00:28:SJ cbx_lpm_compare 2019:09:22:11:00:28:SJ cbx_lpm_counter 2019:09:22:11:00:28:SJ cbx_lpm_decode 2019:09:22:11:00:28:SJ cbx_lpm_mux 2019:09:22:11:00:28:SJ cbx_maxii 2019:09:22:11:00:28:SJ cbx_mgl 2019:09:22:11:02:15:SJ cbx_nadder 2019:09:22:11:00:28:SJ cbx_stratix 2019:09:22:11:00:28:SJ cbx_stratixii 2019:09:22:11:00:28:SJ cbx_util_mgl 2019:09:22:11:00:28:SJ VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 @@ -118,7 +118,7 @@ module UFM_altufm_none_38r defparam maxii_ufm_block1.address_width = 9, maxii_ufm_block1.erase_time = 500000000, - maxii_ufm_block1.init_file = "RAM2GS.mif", + maxii_ufm_block1.init_file = "../RAM2GS-MAX.mif", maxii_ufm_block1.osc_sim_setting = 180000, maxii_ufm_block1.program_time = 1600000, maxii_ufm_block1.lpm_type = "maxv_ufm"; @@ -209,7 +209,7 @@ endmodule // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX V" // Retrieval info: CONSTANT: ERASE_TIME NUMERIC "500000000" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX V" -// Retrieval info: CONSTANT: LPM_FILE STRING "RAM2GS.mif" +// Retrieval info: CONSTANT: LPM_FILE STRING "RAM2GS-MAX.mif" // Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" // Retrieval info: CONSTANT: LPM_TYPE STRING "altufm_none" // Retrieval info: CONSTANT: OSC_FREQUENCY NUMERIC "180000" diff --git a/CPLD/MAXV/output_files/RAM2GS.asm.rpt b/CPLD/MAXV/output_files/RAM2GS.asm.rpt index 398b713..5c89a36 100644 --- a/CPLD/MAXV/output_files/RAM2GS.asm.rpt +++ b/CPLD/MAXV/output_files/RAM2GS.asm.rpt @@ -1,5 +1,5 @@ Assembler report for RAM2GS -Sat Sep 30 04:44:05 2023 +Sat Nov 11 04:34:48 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition @@ -10,7 +10,7 @@ Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Editio 2. Assembler Summary 3. Assembler Settings 4. Assembler Generated Files - 5. Assembler Device Options: /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pof + 5. Assembler Device Options: Y:/Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pof 6. Assembler Messages @@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Sat Sep 30 04:44:05 2023 ; +; Assembler Status ; Successful - Sat Nov 11 04:34:48 2023 ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; ; Family ; MAX V ; @@ -53,23 +53,23 @@ https://fpgasoftware.intel.com/eula. +--------+---------+---------------+ -+-------------------------------------------------+ -; Assembler Generated Files ; -+-------------------------------------------------+ -; File Name ; -+-------------------------------------------------+ -; /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pof ; -+-------------------------------------------------+ ++---------------------------------------------------+ +; Assembler Generated Files ; ++---------------------------------------------------+ +; File Name ; ++---------------------------------------------------+ +; Y:/Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pof ; ++---------------------------------------------------+ -+---------------------------------------------------------------------------+ -; Assembler Device Options: /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pof ; -+----------------+----------------------------------------------------------+ -; Option ; Setting ; -+----------------+----------------------------------------------------------+ -; JTAG usercode ; 0x00172723 ; -; Checksum ; 0x00172A9B ; -+----------------+----------------------------------------------------------+ ++-----------------------------------------------------------------------------+ +; Assembler Device Options: Y:/Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pof ; ++----------------+------------------------------------------------------------+ +; Option ; Setting ; ++----------------+------------------------------------------------------------+ +; JTAG usercode ; 0x00172723 ; +; Checksum ; 0x00172A9B ; ++----------------+------------------------------------------------------------+ +--------------------+ @@ -78,13 +78,13 @@ https://fpgasoftware.intel.com/eula. Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition - Info: Processing started: Sat Sep 30 04:44:04 2023 + Info: Processing started: Sat Nov 11 04:34:47 2023 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 13096 megabytes - Info: Processing ended: Sat Sep 30 04:44:05 2023 + Info: Peak virtual memory: 13071 megabytes + Info: Processing ended: Sat Nov 11 04:34:48 2023 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/CPLD/MAXV/output_files/RAM2GS.done b/CPLD/MAXV/output_files/RAM2GS.done index 27c4db7..bb6cfa6 100644 --- a/CPLD/MAXV/output_files/RAM2GS.done +++ b/CPLD/MAXV/output_files/RAM2GS.done @@ -1 +1 @@ -Sat Sep 30 04:44:09 2023 +Sat Nov 11 04:34:52 2023 diff --git a/CPLD/MAXV/output_files/RAM2GS.fit.rpt b/CPLD/MAXV/output_files/RAM2GS.fit.rpt index c4f7acb..a0ddaee 100644 --- a/CPLD/MAXV/output_files/RAM2GS.fit.rpt +++ b/CPLD/MAXV/output_files/RAM2GS.fit.rpt @@ -1,5 +1,5 @@ Fitter report for RAM2GS -Sat Sep 30 04:44:02 2023 +Sat Nov 11 04:34:46 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition @@ -59,7 +59,7 @@ https://fpgasoftware.intel.com/eula. +-------------------------------------------------------------------------------------+ ; Fitter Summary ; +-----------------------+-------------------------------------------------------------+ -; Fitter Status ; Successful - Sat Sep 30 04:44:02 2023 ; +; Fitter Status ; Successful - Sat Nov 11 04:34:46 2023 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; @@ -131,20 +131,20 @@ https://fpgasoftware.intel.com/eula. ; Number detected on machine ; 4 ; ; Maximum allowed ; 4 ; ; ; ; -; Average used ; 1.04 ; +; Average used ; 1.03 ; ; Maximum used ; 4 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 1.7% ; -; Processors 3-4 ; 1.3% ; +; Processor 2 ; 0.9% ; +; Processors 3-4 ; 0.9% ; +----------------------------+-------------+ +--------------+ ; Pin-Out File ; +--------------+ -The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pin. +The pin-out file can be found in Y:/Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pin. +---------------------------------------------------------------------+ @@ -711,19 +711,19 @@ Info (332111): Found 6 clocks Info (332111): 350.000 PHI2 Info (332111): 16.000 RCLK Info (186079): Completed User Assigned Global Signals Promotion Operation -Info (186215): Automatically promoted signal "RCLK" to use Global clock in PIN 12 File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 41 -Info (186216): Automatically promoted some destinations of signal "PHI2" to use Global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 8 - Info (186217): Destination "PHI2r" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 14 -Info (186228): Pin "PHI2" drives global clock, but is not placed in a dedicated clock pin position File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 8 -Info (186216): Automatically promoted some destinations of signal "nCRAS" to use Global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11 - Info (186217): Destination "LED~0" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 22 - Info (186217): Destination "RASr" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 15 -Info (186228): Pin "nCRAS" drives global clock, but is not placed in a dedicated clock pin position File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11 -Info (186216): Automatically promoted some destinations of signal "nCCAS" to use Global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11 - Info (186217): Destination "CBR" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 18 - Info (186217): Destination "RD~16" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 60 - Info (186217): Destination "CASr" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 16 -Info (186228): Pin "nCCAS" drives global clock, but is not placed in a dedicated clock pin position File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11 +Info (186215): Automatically promoted signal "RCLK" to use Global clock in PIN 12 File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 41 +Info (186216): Automatically promoted some destinations of signal "PHI2" to use Global clock File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 8 + Info (186217): Destination "PHI2r" may be non-global or may not use global clock File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 14 +Info (186228): Pin "PHI2" drives global clock, but is not placed in a dedicated clock pin position File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 8 +Info (186216): Automatically promoted some destinations of signal "nCRAS" to use Global clock File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11 + Info (186217): Destination "LED~0" may be non-global or may not use global clock File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 22 + Info (186217): Destination "RASr" may be non-global or may not use global clock File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 15 +Info (186228): Pin "nCRAS" drives global clock, but is not placed in a dedicated clock pin position File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11 +Info (186216): Automatically promoted some destinations of signal "nCCAS" to use Global clock File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11 + Info (186217): Destination "CBR" may be non-global or may not use global clock File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 18 + Info (186217): Destination "RD~16" may be non-global or may not use global clock File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 60 + Info (186217): Destination "CASr" may be non-global or may not use global clock File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 16 +Info (186228): Pin "nCCAS" drives global clock, but is not placed in a dedicated clock pin position File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11 Info (186079): Completed Auto Global Promotion Operation Info (176234): Starting register packing Info (186468): Started processing fast register assignments @@ -741,20 +741,20 @@ Info (170195): Router estimated average interconnect usage is 19% of the availab Info (170196): Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info (170201): Optimizations that may affect the design's routability were skipped -Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 -Info (11888): Total time spent on timing analysis during the Fitter is 0.58 seconds. +Info (170194): Fitter routing operations ending: elapsed time is 00:00:01 +Info (11888): Total time spent on timing analysis during the Fitter is 0.95 seconds. Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 -Info (144001): Generated suppressed messages file /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg +Info (144001): Generated suppressed messages file Y:/Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg Info: Quartus Prime Fitter was successful. 0 errors, 1 warning - Info: Peak virtual memory: 13772 megabytes - Info: Processing ended: Sat Sep 30 04:44:02 2023 - Info: Elapsed time: 00:00:04 - Info: Total CPU time (on all processors): 00:00:04 + Info: Peak virtual memory: 13744 megabytes + Info: Processing ended: Sat Nov 11 04:34:46 2023 + Info: Elapsed time: 00:00:06 + Info: Total CPU time (on all processors): 00:00:03 +----------------------------+ ; Fitter Suppressed Messages ; +----------------------------+ -The suppressed messages can be found in /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg. +The suppressed messages can be found in Y:/Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg. diff --git a/CPLD/MAXV/output_files/RAM2GS.fit.summary b/CPLD/MAXV/output_files/RAM2GS.fit.summary index 32f8976..3969a86 100644 --- a/CPLD/MAXV/output_files/RAM2GS.fit.summary +++ b/CPLD/MAXV/output_files/RAM2GS.fit.summary @@ -1,4 +1,4 @@ -Fitter Status : Successful - Sat Sep 30 04:44:02 2023 +Fitter Status : Successful - Sat Nov 11 04:34:46 2023 Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition Revision Name : RAM2GS Top-level Entity Name : RAM2GS diff --git a/CPLD/MAXV/output_files/RAM2GS.flow.rpt b/CPLD/MAXV/output_files/RAM2GS.flow.rpt index cbdab27..f8c64ac 100644 --- a/CPLD/MAXV/output_files/RAM2GS.flow.rpt +++ b/CPLD/MAXV/output_files/RAM2GS.flow.rpt @@ -1,5 +1,5 @@ Flow report for RAM2GS -Sat Sep 30 04:44:08 2023 +Sat Nov 11 04:34:51 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition @@ -41,7 +41,7 @@ https://fpgasoftware.intel.com/eula. +-------------------------------------------------------------------------------------+ ; Flow Summary ; +-----------------------+-------------------------------------------------------------+ -; Flow Status ; Successful - Sat Sep 30 04:44:05 2023 ; +; Flow Status ; Successful - Sat Nov 11 04:34:48 2023 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; @@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 09/30/2023 04:43:33 ; +; Start date & time ; 11/11/2023 04:34:04 ; ; Main task ; Compilation ; ; Revision Name ; RAM2GS ; +-------------------+---------------------+ @@ -71,7 +71,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------+------------------------------+---------------+-------------+------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +---------------------------------------+------------------------------+---------------+-------------+------------+ -; COMPILER_SIGNATURE_ID ; 121381084694.169606341306136 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 121381084694.169969524314084 ; -- ; -- ; -- ; ; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; ; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; ; NUM_PARALLEL_PROCESSORS ; 4 ; -- ; -- ; -- ; @@ -86,11 +86,11 @@ https://fpgasoftware.intel.com/eula. +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:25 ; 1.0 ; 13138 MB ; 00:00:41 ; -; Fitter ; 00:00:04 ; 1.0 ; 13772 MB ; 00:00:04 ; -; Assembler ; 00:00:01 ; 1.0 ; 13094 MB ; 00:00:01 ; -; Timing Analyzer ; 00:00:02 ; 1.0 ; 13092 MB ; 00:00:02 ; -; Total ; 00:00:32 ; -- ; -- ; 00:00:48 ; +; Analysis & Synthesis ; 00:00:36 ; 1.0 ; 13126 MB ; 00:00:41 ; +; Fitter ; 00:00:06 ; 1.0 ; 13744 MB ; 00:00:03 ; +; Assembler ; 00:00:01 ; 1.0 ; 13068 MB ; 00:00:01 ; +; Timing Analyzer ; 00:00:01 ; 1.0 ; 13067 MB ; 00:00:01 ; +; Total ; 00:00:44 ; -- ; -- ; 00:00:46 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/CPLD/MAXV/output_files/RAM2GS.jdi b/CPLD/MAXV/output_files/RAM2GS.jdi index 23099fd..df310c9 100644 --- a/CPLD/MAXV/output_files/RAM2GS.jdi +++ b/CPLD/MAXV/output_files/RAM2GS.jdi @@ -1,6 +1,6 @@ - + diff --git a/CPLD/MAXV/output_files/RAM2GS.map.rpt b/CPLD/MAXV/output_files/RAM2GS.map.rpt index 19bfaa7..17596bc 100644 --- a/CPLD/MAXV/output_files/RAM2GS.map.rpt +++ b/CPLD/MAXV/output_files/RAM2GS.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for RAM2GS -Sat Sep 30 04:43:57 2023 +Sat Nov 11 04:34:38 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition @@ -46,7 +46,7 @@ https://fpgasoftware.intel.com/eula. +-------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+-------------------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Sat Sep 30 04:43:57 2023 ; +; Analysis & Synthesis Status ; Successful - Sat Nov 11 04:34:38 2023 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; @@ -146,15 +146,15 @@ https://fpgasoftware.intel.com/eula. +----------------------------+-------------+ -+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Source Files Read ; -+----------------------------------+-----------------+----------------------------------+------------------------------------------------+---------+ -; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; -+----------------------------------+-----------------+----------------------------------+------------------------------------------------+---------+ -; ../RAM2GS-MAX.v ; yes ; User Verilog HDL File ; //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v ; ; -; UFM.v ; yes ; User Wizard-Generated File ; //Mac/iCloud/Repos/RAM2GS/CPLD/MAXV/UFM.v ; ; -; ../RAM2GS.mif ; yes ; User Memory Initialization File ; //Mac/iCloud/Repos/RAM2GS/CPLD/MAXV/RAM2GS.mif ; ; -+----------------------------------+-----------------+----------------------------------+------------------------------------------------+---------+ ++---------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+----------------------------------+-------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+----------------------------------+-------------------------------------+---------+ +; ../RAM2GS-MAX.v ; yes ; User Verilog HDL File ; Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v ; ; +; UFM.v ; yes ; User Wizard-Generated File ; Y:/Repos/RAM2GS/CPLD/MAXV/UFM.v ; ; +; ../RAM2GS-MAX.mif ; yes ; User Memory Initialization File ; Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.mif ; ; ++----------------------------------+-----------------+----------------------------------+-------------------------------------+---------+ +-----------------------------------------------------+ @@ -269,42 +269,42 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition - Info: Processing started: Sat Sep 30 04:43:32 2023 + Info: Processing started: Sat Nov 11 04:34:02 2023 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS Info (20032): Parallel compilation is enabled and will use up to 4 processors -Info (12021): Found 1 design units, including 1 entities, in source file //mac/icloud/repos/ram2gs/cpld/ram2gs-max.v - Info (12023): Found entity 1: RAM2GS File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 1 +Info (12021): Found 1 design units, including 1 entities, in source file /repos/ram2gs/cpld/ram2gs-max.v + Info (12023): Found entity 1: RAM2GS File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 1 Info (12021): Found 2 design units, including 2 entities, in source file ufm.v - Info (12023): Found entity 1: UFM_altufm_none_38r File: //Mac/iCloud/Repos/RAM2GS/CPLD/MAXV/UFM.v Line: 47 - Info (12023): Found entity 2: UFM File: //Mac/iCloud/Repos/RAM2GS/CPLD/MAXV/UFM.v Line: 150 + Info (12023): Found entity 1: UFM_altufm_none_38r File: Y:/Repos/RAM2GS/CPLD/MAXV/UFM.v Line: 47 + Info (12023): Found entity 2: UFM File: Y:/Repos/RAM2GS/CPLD/MAXV/UFM.v Line: 150 Info (12127): Elaborating entity "RAM2GS" for the top level hierarchy -Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 92 -Info (12128): Elaborating entity "UFM_altufm_none_38r" for hierarchy "UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component" File: //Mac/iCloud/Repos/RAM2GS/CPLD/MAXV/UFM.v Line: 201 -Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 -Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 -Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 -Warning (14632): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 -Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 -Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 -Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 -Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 +Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 92 +Info (12128): Elaborating entity "UFM_altufm_none_38r" for hierarchy "UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component" File: Y:/Repos/RAM2GS/CPLD/MAXV/UFM.v Line: 201 +Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 +Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 +Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 +Warning (14632): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 +Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 +Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 +Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 +Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 Info (21057): Implemented 260 device resources after synthesis - the final resource count might be different Info (21058): Implemented 25 input pins Info (21059): Implemented 30 output pins Info (21060): Implemented 8 bidirectional pins Info (21061): Implemented 196 logic cells Info (21070): Implemented 1 User Flash Memory blocks -Info (144001): Generated suppressed messages file /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg +Info (144001): Generated suppressed messages file Y:/Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 8 warnings - Info: Peak virtual memory: 13138 megabytes - Info: Processing ended: Sat Sep 30 04:43:57 2023 - Info: Elapsed time: 00:00:25 + Info: Peak virtual memory: 13126 megabytes + Info: Processing ended: Sat Nov 11 04:34:38 2023 + Info: Elapsed time: 00:00:36 Info: Total CPU time (on all processors): 00:00:41 +------------------------------------------+ ; Analysis & Synthesis Suppressed Messages ; +------------------------------------------+ -The suppressed messages can be found in /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg. +The suppressed messages can be found in Y:/Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg. diff --git a/CPLD/MAXV/output_files/RAM2GS.map.smsg b/CPLD/MAXV/output_files/RAM2GS.map.smsg index 2a02712..30cb276 100644 --- a/CPLD/MAXV/output_files/RAM2GS.map.smsg +++ b/CPLD/MAXV/output_files/RAM2GS.map.smsg @@ -1,3 +1,3 @@ -Warning (10273): Verilog HDL warning at RAM2GS-MAX.v(61): extended using "x" or "z" File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 61 -Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: //Mac/iCloud/Repos/RAM2GS/CPLD/MAXV/UFM.v Line: 73 -Warning (10463): Verilog HDL Declaration warning at UFM.v(173): "program" is SystemVerilog-2005 keyword File: //Mac/iCloud/Repos/RAM2GS/CPLD/MAXV/UFM.v Line: 173 +Warning (10273): Verilog HDL warning at RAM2GS-MAX.v(61): extended using "x" or "z" File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 61 +Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: Y:/Repos/RAM2GS/CPLD/MAXV/UFM.v Line: 73 +Warning (10463): Verilog HDL Declaration warning at UFM.v(173): "program" is SystemVerilog-2005 keyword File: Y:/Repos/RAM2GS/CPLD/MAXV/UFM.v Line: 173 diff --git a/CPLD/MAXV/output_files/RAM2GS.map.summary b/CPLD/MAXV/output_files/RAM2GS.map.summary index abbdfbe..f27a57b 100644 --- a/CPLD/MAXV/output_files/RAM2GS.map.summary +++ b/CPLD/MAXV/output_files/RAM2GS.map.summary @@ -1,4 +1,4 @@ -Analysis & Synthesis Status : Successful - Sat Sep 30 04:43:57 2023 +Analysis & Synthesis Status : Successful - Sat Nov 11 04:34:38 2023 Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition Revision Name : RAM2GS Top-level Entity Name : RAM2GS diff --git a/CPLD/MAXV/output_files/RAM2GS.sta.rpt b/CPLD/MAXV/output_files/RAM2GS.sta.rpt index c3b0165..1c01e03 100644 --- a/CPLD/MAXV/output_files/RAM2GS.sta.rpt +++ b/CPLD/MAXV/output_files/RAM2GS.sta.rpt @@ -1,5 +1,5 @@ Timing Analyzer report for RAM2GS -Sat Sep 30 04:44:08 2023 +Sat Nov 11 04:34:51 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition @@ -88,7 +88,7 @@ https://fpgasoftware.intel.com/eula. ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 0.0% ; +; Processor 2 ; 0.3% ; +----------------------------+-------------+ @@ -97,8 +97,8 @@ https://fpgasoftware.intel.com/eula. +-------------------+--------+--------------------------+ ; SDC File Path ; Status ; Read at ; +-------------------+--------+--------------------------+ -; ../RAM2GS.sdc ; OK ; Sat Sep 30 04:44:08 2023 ; -; ../RAM2GS-MAX.sdc ; OK ; Sat Sep 30 04:44:08 2023 ; +; ../RAM2GS.sdc ; OK ; Sat Nov 11 04:34:51 2023 ; +; ../RAM2GS-MAX.sdc ; OK ; Sat Nov 11 04:34:51 2023 ; +-------------------+--------+--------------------------+ @@ -959,7 +959,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition - Info: Processing started: Sat Sep 30 04:44:06 2023 + Info: Processing started: Sat Nov 11 04:34:50 2023 Info: Command: quartus_sta RAM2GS-MAXV -c RAM2GS Info: qsta_default_script.tcl version: #1 Info (20032): Parallel compilation is enabled and will use up to 4 processors @@ -1003,9 +1003,9 @@ Info (332001): The selected device family is not supported by the report_metasta Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning - Info: Peak virtual memory: 13092 megabytes - Info: Processing ended: Sat Sep 30 04:44:08 2023 - Info: Elapsed time: 00:00:02 - Info: Total CPU time (on all processors): 00:00:02 + Info: Peak virtual memory: 13067 megabytes + Info: Processing ended: Sat Nov 11 04:34:51 2023 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 diff --git a/CPLD/RAM2GS-LCMXO2.lpf b/CPLD/RAM2GS-LCMXO2.lpf index d999e58..fe72ab7 100644 --- a/CPLD/RAM2GS-LCMXO2.lpf +++ b/CPLD/RAM2GS-LCMXO2.lpf @@ -42,11 +42,11 @@ LOCATE COMP "RA[5]" SITE "70" ; LOCATE COMP "RA[6]" SITE "68" ; LOCATE COMP "RA[7]" SITE "75" ; LOCATE COMP "RA[8]" SITE "65" ; -LOCATE COMP "RA[9]" SITE "47" ; +LOCATE COMP "RA[9]" SITE "62" ; LOCATE COMP "RA[10]" SITE "64" ; LOCATE COMP "RA[11]" SITE "59" ; LOCATE COMP "RBA[0]" SITE "58" ; -LOCATE COMP "RBA[1]" SITE "60" ; +LOCATE COMP "RBA[1]" SITE "47" ; LOCATE COMP "RCKE" SITE "53" ; LOCATE COMP "RDQMH" SITE "51" ; LOCATE COMP "RDQML" SITE "48" ; @@ -164,6 +164,6 @@ OUTPUT PORT "RD[5]" LOAD 9.000000 pF ; OUTPUT PORT "RD[6]" LOAD 9.000000 pF ; OUTPUT PORT "RD[7]" LOAD 9.000000 pF ; LOCATE COMP "RCLK" SITE "63" ; -LOCATE COMP "RCLKout" SITE "62" ; +LOCATE COMP "RCLKout" SITE "60" ; IOBUF PORT "RCLKout" IO_TYPE=LVCMOS33 PULLMODE=NONE SLEWRATE=FAST DRIVE=24 ; OUTPUT PORT "RCLKout" LOAD 5.000000 pF ; diff --git a/CPLD/RAM2GS-LCMXO2.v b/CPLD/RAM2GS-LCMXO2.v index 36c5d59..25424d0 100644 --- a/CPLD/RAM2GS-LCMXO2.v +++ b/CPLD/RAM2GS-LCMXO2.v @@ -18,9 +18,9 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout, reg CBR; /* Activity LED */ - reg LEDEN = 0; + reg LEDEN; output LED; - assign LED = !(!nCRAS && !CBR && LEDEN); + assign LED = !(!nCRAS && !CBR && LEDEN && Ready); /* 65816 Data */ input [7:0] Din; @@ -38,13 +38,10 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout, reg XOR8MEG = 0; /* SDRAM Clock in/out */ - input RCLK; - output RCLKout; - ODDRXE rck( - .SCLK(RCLK), - .Q(RCLKout), - .D0(0), .D1(1), - .RST(0)); + input RCLK; + output RCLKout; + ODDRXE rclk_oddr(.D0(1'b0), .D1(1'b1), + .SCLK(RCLK), .RST(1'b0), .Q(RCLKout)); /* SDRAM */ reg RCKEEN; @@ -65,7 +62,7 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout, reg [7:0] WRD; inout [7:0] RD; assign RD[7:0] = (!nCCAS && !nFWE) ? WRD[7:0] : 8'bZ; - + /* UFM Interface */ reg wb_rst; reg wb_cyc_stb; @@ -86,7 +83,7 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout, .wb_dat_i(wb_dati), .wb_dat_o(wb_dato), .wb_ack_o(wb_ack), - .wbc_ufm_irq(ufm_irq)); + .wbc_ufm_irq(ufm_irq)); /* UFM Command Interface */ reg C1Submitted = 0; @@ -156,7 +153,7 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout, always @(posedge RCLK) begin // Wait ~4.178ms (at 62.5 MHz) before starting init sequence FS <= FS+18'h1; - if (FS[17:10] == 8'hFF) InitReady <= 1'b1; + if (FS[17:10]==8'hFF) InitReady <= 1'b1; end /* SDRAM CKE */ diff --git a/CPLD/MAXII/RAM2GS.mif b/CPLD/RAM2GS-MAX.mif similarity index 100% rename from CPLD/MAXII/RAM2GS.mif rename to CPLD/RAM2GS-MAX.mif diff --git a/CPLD/RAM2GS-SPI.v b/CPLD/RAM2GS-SPI.v index 4ba31d3..76975bc 100644 --- a/CPLD/RAM2GS-SPI.v +++ b/CPLD/RAM2GS-SPI.v @@ -18,9 +18,9 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout, reg CBR; /* Activity LED */ - reg LEDEN = 0; + reg LEDEN; output LED; - assign LED = !(!nCRAS && !CBR && LEDEN); + assign LED = !(!nCRAS && !CBR && LEDEN && Ready); /* 65816 Data */ input [7:0] Din; @@ -134,7 +134,7 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout, always @(posedge RCLK) begin // Wait ~4.178ms (at 62.5 MHz) before starting init sequence FS <= FS+18'h1; - if (FS[17:10] == 8'hFF) InitReady <= 1'b1; + if (FS[17:10]==8'hFF) InitReady <= 1'b1; end /* SDRAM CKE */