Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd. Design name: RAM2GS NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-640HC Package: TQFP100 Performance: 5 Package Status: Final Version 1.39. Performance Hardware Data Status: Final Version 34.4. Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd. Design name: RAM2GS NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-640HC Package: TQFP100 Performance: 6 Package Status: Final Version 1.39. Performance Hardware Data Status: Final Version 34.4. Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd. Design name: RAM2GS NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-640HC Package: TQFP100 Performance: M Package Status: Final Version 1.39. Performance Hardware Data Status: Final Version 34.4. // Design: RAM2GS // Package: TQFP100 // ncd File: ram2gs_lcmxo2_640hc_impl1.ncd // Version: Diamond (64-bit) 3.12.0.240.2 // Written on Sat Oct 09 01:19:25 2021 // M: Minimum Performance Grade // iotiming RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf -gui I/O Timing Report (All units are in ns) Worst Case Results across Performance Grades (M, 6, 5, 4): // Input Setup and Hold Times Port Clock Edge Setup Performance_Grade Hold Performance_Grade ---------------------------------------------------------------------- CROW[0] nCRAS F -0.195 M 1.729 4 CROW[1] nCRAS F -0.218 M 1.801 4 Din[0] PHI2 F 6.339 4 1.186 4 Din[0] nCCAS F 1.641 4 0.107 M Din[1] PHI2 F 6.084 4 1.570 4 Din[1] nCCAS F 0.198 4 1.314 4 Din[2] PHI2 F 3.778 4 1.771 4 Din[2] nCCAS F 0.075 4 1.431 4 Din[3] PHI2 F 4.331 4 1.705 4 Din[3] nCCAS F -0.116 M 1.722 4 Din[4] PHI2 F 6.176 4 1.711 4 Din[4] nCCAS F 1.065 4 0.575 4 Din[5] PHI2 F 4.684 4 1.261 4 Din[5] nCCAS F -0.081 M 1.625 4 Din[6] PHI2 F 5.243 4 0.356 4 Din[6] nCCAS F 1.414 4 0.309 4 Din[7] PHI2 F 6.602 4 1.175 4 Din[7] nCCAS F -0.286 M 2.137 4 MAin[0] PHI2 F 5.034 4 0.629 4 MAin[0] nCRAS F 1.094 4 0.380 4 MAin[1] PHI2 F 6.081 4 1.157 4 MAin[1] nCRAS F 0.544 4 0.877 4 MAin[2] PHI2 F 9.979 4 -0.319 M MAin[2] nCRAS F -0.050 M 1.401 4 MAin[3] PHI2 F 9.162 4 -0.219 M MAin[3] nCRAS F 1.032 4 0.440 4 MAin[4] PHI2 F 11.678 4 -0.770 M MAin[4] nCRAS F -0.150 M 1.620 4 MAin[5] PHI2 F 8.668 4 -0.081 M MAin[5] nCRAS F -0.050 M 1.401 4 MAin[6] PHI2 F 8.516 4 -0.025 M MAin[6] nCRAS F 1.003 4 0.478 4 MAin[7] PHI2 F 9.320 4 -0.061 M MAin[7] nCRAS F 1.001 4 0.478 4 MAin[8] nCRAS F -0.146 M 1.657 4 MAin[9] nCRAS F -0.360 M 2.140 4 PHI2 RCLK R 3.079 4 -0.602 M nCCAS RCLK R 3.574 4 -0.705 M nCCAS nCRAS F 3.232 4 -0.351 M nCRAS RCLK R 2.757 4 -0.470 M nFWE PHI2 F 5.913 4 0.723 4 nFWE nCRAS F 0.547 4 0.890 4 // Clock to Output Delay Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade ------------------------------------------------------------------------ LED RCLK R 10.062 4 3.164 M RA[0] RCLK R 10.645 4 3.471 M RA[0] nCRAS F 11.744 4 3.770 M RA[10] RCLK R 9.485 4 3.236 M RA[11] PHI2 R 11.513 4 3.824 M RA[1] RCLK R 10.921 4 3.549 M RA[1] nCRAS F 12.664 4 4.036 M RA[2] RCLK R 10.923 4 3.527 M RA[2] nCRAS F 12.463 4 3.984 M RA[3] RCLK R 11.178 4 3.615 M RA[3] nCRAS F 12.304 4 3.917 M RA[4] RCLK R 11.365 4 3.630 M RA[4] nCRAS F 13.243 4 4.179 M RA[5] RCLK R 11.365 4 3.630 M RA[5] nCRAS F 12.940 4 4.098 M RA[6] RCLK R 11.099 4 3.573 M RA[6] nCRAS F 12.162 4 3.870 M RA[7] RCLK R 10.948 4 3.552 M RA[7] nCRAS F 12.282 4 3.936 M RA[8] RCLK R 11.114 4 3.608 M RA[8] nCRAS F 12.909 4 4.116 M RA[9] RCLK R 11.005 4 3.561 M RA[9] nCRAS F 12.959 4 4.081 M RBA[0] nCRAS F 11.842 4 3.911 M RBA[1] nCRAS F 11.343 4 3.771 M RCKE RCLK R 9.884 4 3.362 M RDQMH RCLK R 10.941 4 3.559 M RDQML RCLK R 10.641 4 3.470 M RD[0] nCCAS F 12.628 4 4.413 M RD[1] nCCAS F 12.231 4 4.302 M RD[2] nCCAS F 12.231 4 4.302 M RD[3] nCCAS F 11.928 4 4.221 M RD[4] nCCAS F 12.427 4 4.361 M RD[5] nCCAS F 12.697 4 4.400 M RD[6] nCCAS F 12.427 4 4.361 M RD[7] nCCAS F 12.427 4 4.361 M nRCAS RCLK R 9.674 4 3.300 M nRCS RCLK R 9.674 4 3.300 M nRRAS RCLK R 9.797 4 3.322 M nRWE RCLK R 9.275 4 3.194 M WARNING: you must also run trce with hold speed: 4 WARNING: you must also run trce with setup speed: M