Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd. Design name: RAM2GS NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-640HC Package: TQFP100 Performance: 5 Package Status: Final Version 1.39. Performance Hardware Data Status: Final Version 34.4. Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd. Design name: RAM2GS NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-640HC Package: TQFP100 Performance: 6 Package Status: Final Version 1.39. Performance Hardware Data Status: Final Version 34.4. Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd. Design name: RAM2GS NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-640HC Package: TQFP100 Performance: M Package Status: Final Version 1.39. Performance Hardware Data Status: Final Version 34.4. // Design: RAM2GS // Package: TQFP100 // ncd File: ram2gs_lcmxo2_640hc_impl1.ncd // Version: Diamond (64-bit) 3.12.1.454 // Written on Sat Nov 18 02:06:14 2023 // M: Minimum Performance Grade // iotiming RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml I/O Timing Report (All units are in ns) Worst Case Results across Performance Grades (M, 6, 5, 4): // Input Setup and Hold Times Port Clock Edge Setup Performance_Grade Hold Performance_Grade ---------------------------------------------------------------------- CROW[0] nCRAS F 2.058 4 -0.092 M CROW[1] nCRAS F 2.269 4 -0.117 M Din[0] PHI2 F 7.415 4 3.636 4 Din[0] nCCAS F 2.760 4 -0.330 M Din[1] PHI2 F 6.384 4 3.516 4 Din[1] nCCAS F 1.112 4 0.128 4 Din[2] PHI2 F 6.717 4 3.516 4 Din[2] nCCAS F 0.113 4 0.982 4 Din[3] PHI2 F 5.806 4 3.516 4 Din[3] nCCAS F 1.105 4 0.134 4 Din[4] PHI2 F 6.853 4 3.516 4 Din[4] nCCAS F 1.538 4 -0.010 M Din[5] PHI2 F 7.478 4 3.516 4 Din[5] nCCAS F 0.714 4 0.460 4 Din[6] PHI2 F 5.667 4 3.636 4 Din[6] nCCAS F 1.504 4 -0.015 M Din[7] PHI2 F 5.567 4 3.636 4 Din[7] nCCAS F 1.063 4 0.194 4 MAin[0] PHI2 F 4.483 4 0.742 4 MAin[0] nCRAS F 1.204 4 0.334 4 MAin[1] PHI2 F 4.440 4 0.520 4 MAin[1] nCRAS F 1.245 4 0.313 4 MAin[2] PHI2 F 9.497 4 -0.729 M MAin[2] nCRAS F 0.758 4 0.714 4 MAin[3] PHI2 F 9.534 4 -0.752 M MAin[3] nCRAS F 0.454 4 0.874 4 MAin[4] PHI2 F 7.882 4 -0.326 M MAin[4] nCRAS F 0.832 4 0.632 4 MAin[5] PHI2 F 10.136 4 -0.894 M MAin[5] nCRAS F 0.830 4 0.632 4 MAin[6] PHI2 F 8.759 4 -0.555 M MAin[6] nCRAS F 1.259 4 0.268 4 MAin[7] PHI2 F 8.430 4 -0.434 M MAin[7] nCRAS F 0.881 4 0.510 4 MAin[8] nCRAS F 1.066 4 0.422 4 MAin[9] nCRAS F 0.723 4 0.746 4 PHI2 RCLK R -0.005 M 2.116 4 nCCAS RCLK R 3.614 4 -0.637 M nCCAS nCRAS F 3.629 4 -0.447 M nCRAS RCLK R 3.040 4 -0.485 M nFWE PHI2 F 8.830 4 -0.567 M nFWE nCRAS F 0.454 4 0.874 4 // Clock to Output Delay Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade ------------------------------------------------------------------------ LED RCLK R 11.284 4 2.893 M LED nCRAS F 11.111 4 3.244 M RA[0] RCLK R 10.888 4 3.313 M RA[0] nCRAS F 11.968 4 3.554 M RA[10] RCLK R 7.578 4 2.578 M RA[11] PHI2 R 9.098 4 3.021 M RA[1] RCLK R 11.272 4 3.408 M RA[1] nCRAS F 11.484 4 3.438 M RA[2] RCLK R 11.749 4 3.528 M RA[2] nCRAS F 11.267 4 3.385 M RA[3] RCLK R 11.291 4 3.431 M RA[3] nCRAS F 11.596 4 3.449 M RA[4] RCLK R 10.696 4 3.276 M RA[4] nCRAS F 11.720 4 3.503 M RA[5] RCLK R 11.228 4 3.401 M RA[5] nCRAS F 11.364 4 3.427 M RA[6] RCLK R 10.132 4 3.112 M RA[6] nCRAS F 10.958 4 3.284 M RA[7] RCLK R 11.404 4 3.446 M RA[7] nCRAS F 11.918 4 3.561 M RA[8] RCLK R 10.488 4 3.236 M RA[8] nCRAS F 11.512 4 3.463 M RA[9] RCLK R 10.941 4 3.329 M RA[9] nCRAS F 11.074 4 3.356 M RBA[0] nCRAS F 8.645 4 2.828 M RBA[1] nCRAS F 8.625 4 2.835 M RCKE RCLK R 9.454 4 3.006 M RCLKout RCLK R 6.857 4 1.980 M RDQMH RCLK R 9.846 4 3.033 M RDQML RCLK R 9.741 4 3.008 M RD[0] nCCAS F 8.761 4 2.984 M RD[1] nCCAS F 8.761 4 2.984 M RD[2] nCCAS F 8.761 4 2.984 M RD[3] nCCAS F 8.761 4 2.984 M RD[4] nCCAS F 8.761 4 2.984 M RD[5] nCCAS F 8.761 4 2.984 M RD[6] nCCAS F 8.761 4 2.984 M RD[7] nCCAS F 8.761 4 2.984 M nRCAS RCLK R 7.578 4 2.578 M nRCS RCLK R 7.578 4 2.578 M nRRAS RCLK R 7.578 4 2.578 M nRWE RCLK R 7.558 4 2.585 M WARNING: you must also run trce with hold speed: 4 WARNING: you must also run trce with setup speed: M