RAM2GS/CPLD/LCMXO2-1200HC/impl1/ram2gs_lcmxo2_1200hc_impl1_trce.asd
2023-08-15 05:05:47 -04:00

14 lines
294 B
Common Lisp

[ActiveSupport TRCE]
; Setup Analysis
Fmax_0 = 174.216 MHz (299.401 MHz);
Fmax_1 = 67.833 MHz (99.079 MHz);
Failed = 2 (Total 2);
Clock_ports = 4;
Clock_nets = 4;
; Hold Analysis
Fmax_0 = 0.304 ns (0.000 ns);
Fmax_1 = 0.379 ns (0.000 ns);
Failed = 0 (Total 2);
Clock_ports = 4;
Clock_nets = 4;