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RAM2GS/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_twr.html
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<HEAD><TITLE>Lattice TRACE Report</TITLE>
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<PRE><A name="Par_Twr"></A><B><U><big>Place & Route TRACE Report</big></U></B>
Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-640HC
Package: TQFP100
Performance: 4
Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
Setup and Hold Report
--------------------------------------------------------------------------------
<A name="Par_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2</big></U></B>
Sat Oct 09 01:19:23 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
<A name="ptwr_set_ri"></A><B><U><big>Report Information</big></U></B>
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
Design file: ram2gs_lcmxo2_640hc_impl1.ncd
Preference file: ram2gs_lcmxo2_640hc_impl1.prf
Device,speed: LCMXO2-640HC,4
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
<A name="ptwr_set_ps"></A><B><U><big>Preference Summary</big></U></B>
<LI><A href='#par_twr_pref_0_0' Target='right'>PERIOD NET "PHI2_c" 350.000000 ns (0 errors)</A></LI> 121 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_1' Target='right'>PERIOD NET "nCCAS_c" 350.000000 ns (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_2' Target='right'>PERIOD NET "nCRAS_c" 350.000000 ns (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_3' Target='right'>PERIOD NET "RCLK_c" 16.000000 ns (0 errors)</A></LI> 1409 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_4' Target='right'>CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_5' Target='right'>CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_6' Target='right'>CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_7' Target='right'>CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_8' Target='right'>CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_9' Target='right'>CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_10' Target='right'>CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_11' Target='right'>CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_12' Target='right'>CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_13' Target='right'>CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_14' Target='right'>CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_15' Target='right'>CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_16' Target='right'>CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_17' Target='right'>CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_18' Target='right'>CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_19' Target='right'>CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_20' Target='right'>CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_21' Target='right'>CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_22' Target='right'>CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_23' Target='right'>CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_24' Target='right'>CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_25' Target='right'>CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_26' Target='right'>CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_27' Target='right'>CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_28' Target='right'>CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_29' Target='right'>CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_30' Target='right'>CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_31' Target='right'>CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_32' Target='right'>CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_33' Target='right'>CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_34' Target='right'>CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_35' Target='right'>CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_36' Target='right'>CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_37' Target='right'>CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_38' Target='right'>CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_39' Target='right'>CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_40' Target='right'>CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
Derating parameters
-------------------
Voltage: 3.300 V
VCCIO Voltage:
3.135 V (Bank 0)
3.135 V (Bank 1)
3.135 V (Bank 2)
3.135 V (Bank 3)
2.375 V (Bank 4)
2.375 V (Bank 5)
2.375 V (Bank 6)
2.375 V (Bank 7)
================================================================================
<A name="par_twr_pref_0_0"></A>Preference: PERIOD NET "PHI2_c" 350.000000 ns ;
121 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 162.100ns (weighted slack = 324.200ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_i6 (from PHI2_c +)
Destination: FF Data in CmdLEDEN_545 (to PHI2_c -)
Delay: 12.593ns (31.1% logic, 68.9% route), 8 logic levels.
Constraint Details:
12.593ns physical path delay SLICE_151 to SLICE_20 meets
175.000ns delay constraint less
0.000ns skew and
0.307ns CE_SET requirement (totaling 174.693ns) by 162.100ns
Physical Path Details:
Data path SLICE_151 to SLICE_20:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R5C9B.CLK to R5C9B.Q0 SLICE_151 (from PHI2_c)
ROUTE 1 1.278 R5C9B.Q0 to R2C8B.C0 Bank_6
CTOF_DEL --- 0.495 R2C8B.C0 to R2C8B.F0 SLICE_158
ROUTE 1 1.535 R2C8B.F0 to R5C9D.B0 n4610
CTOF_DEL --- 0.495 R5C9D.B0 to R5C9D.F0 SLICE_139
ROUTE 2 1.086 R5C9D.F0 to R2C9D.C1 n4628
CTOF_DEL --- 0.495 R2C9D.C1 to R2C9D.F1 SLICE_114
ROUTE 4 0.788 R2C9D.F1 to R3C9D.C1 n2384
CTOF_DEL --- 0.495 R3C9D.C1 to R3C9D.F1 SLICE_130
ROUTE 2 0.995 R3C9D.F1 to R4C9B.A0 n4889
CTOF_DEL --- 0.495 R4C9B.A0 to R4C9B.F0 SLICE_21
ROUTE 4 1.474 R4C9B.F0 to R5C8D.B0 XOR8MEG_N_149
CTOF_DEL --- 0.495 R5C8D.B0 to R5C8D.F0 SLICE_112
ROUTE 1 0.436 R5C8D.F0 to R5C8D.C1 n4882
CTOF_DEL --- 0.495 R5C8D.C1 to R5C8D.F1 SLICE_112
ROUTE 2 1.084 R5C8D.F1 to R5C6A.CE PHI2_N_151_enable_5 (to PHI2_c)
--------
12.593 (31.1% logic, 68.9% route), 8 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_151:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.539 8.PADDI to R5C9B.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.539 8.PADDI to R5C6A.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 162.100ns (weighted slack = 324.200ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_i6 (from PHI2_c +)
Destination: FF Data in Cmdn8MEGEN_546 (to PHI2_c -)
Delay: 12.593ns (31.1% logic, 68.9% route), 8 logic levels.
Constraint Details:
12.593ns physical path delay SLICE_151 to SLICE_24 meets
175.000ns delay constraint less
0.000ns skew and
0.307ns CE_SET requirement (totaling 174.693ns) by 162.100ns
Physical Path Details:
Data path SLICE_151 to SLICE_24:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R5C9B.CLK to R5C9B.Q0 SLICE_151 (from PHI2_c)
ROUTE 1 1.278 R5C9B.Q0 to R2C8B.C0 Bank_6
CTOF_DEL --- 0.495 R2C8B.C0 to R2C8B.F0 SLICE_158
ROUTE 1 1.535 R2C8B.F0 to R5C9D.B0 n4610
CTOF_DEL --- 0.495 R5C9D.B0 to R5C9D.F0 SLICE_139
ROUTE 2 1.086 R5C9D.F0 to R2C9D.C1 n4628
CTOF_DEL --- 0.495 R2C9D.C1 to R2C9D.F1 SLICE_114
ROUTE 4 0.788 R2C9D.F1 to R3C9D.C1 n2384
CTOF_DEL --- 0.495 R3C9D.C1 to R3C9D.F1 SLICE_130
ROUTE 2 0.995 R3C9D.F1 to R4C9B.A0 n4889
CTOF_DEL --- 0.495 R4C9B.A0 to R4C9B.F0 SLICE_21
ROUTE 4 1.474 R4C9B.F0 to R5C8D.B0 XOR8MEG_N_149
CTOF_DEL --- 0.495 R5C8D.B0 to R5C8D.F0 SLICE_112
ROUTE 1 0.436 R5C8D.F0 to R5C8D.C1 n4882
CTOF_DEL --- 0.495 R5C8D.C1 to R5C8D.F1 SLICE_112
ROUTE 2 1.084 R5C8D.F1 to R5C6B.CE PHI2_N_151_enable_5 (to PHI2_c)
--------
12.593 (31.1% logic, 68.9% route), 8 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_151:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.539 8.PADDI to R5C9B.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_24:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.539 8.PADDI to R5C6B.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 162.374ns (weighted slack = 324.748ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_i4 (from PHI2_c +)
Destination: FF Data in CmdLEDEN_545 (to PHI2_c -)
Delay: 12.319ns (31.8% logic, 68.2% route), 8 logic levels.
Constraint Details:
12.319ns physical path delay SLICE_111 to SLICE_20 meets
175.000ns delay constraint less
0.000ns skew and
0.307ns CE_SET requirement (totaling 174.693ns) by 162.374ns
Physical Path Details:
Data path SLICE_111 to SLICE_20:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R2C8C.CLK to R2C8C.Q0 SLICE_111 (from PHI2_c)
ROUTE 1 1.004 R2C8C.Q0 to R2C8B.B0 Bank_4
CTOF_DEL --- 0.495 R2C8B.B0 to R2C8B.F0 SLICE_158
ROUTE 1 1.535 R2C8B.F0 to R5C9D.B0 n4610
CTOF_DEL --- 0.495 R5C9D.B0 to R5C9D.F0 SLICE_139
ROUTE 2 1.086 R5C9D.F0 to R2C9D.C1 n4628
CTOF_DEL --- 0.495 R2C9D.C1 to R2C9D.F1 SLICE_114
ROUTE 4 0.788 R2C9D.F1 to R3C9D.C1 n2384
CTOF_DEL --- 0.495 R3C9D.C1 to R3C9D.F1 SLICE_130
ROUTE 2 0.995 R3C9D.F1 to R4C9B.A0 n4889
CTOF_DEL --- 0.495 R4C9B.A0 to R4C9B.F0 SLICE_21
ROUTE 4 1.474 R4C9B.F0 to R5C8D.B0 XOR8MEG_N_149
CTOF_DEL --- 0.495 R5C8D.B0 to R5C8D.F0 SLICE_112
ROUTE 1 0.436 R5C8D.F0 to R5C8D.C1 n4882
CTOF_DEL --- 0.495 R5C8D.C1 to R5C8D.F1 SLICE_112
ROUTE 2 1.084 R5C8D.F1 to R5C6A.CE PHI2_N_151_enable_5 (to PHI2_c)
--------
12.319 (31.8% logic, 68.2% route), 8 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_111:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.539 8.PADDI to R2C8C.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.539 8.PADDI to R5C6A.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 162.374ns (weighted slack = 324.748ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_i4 (from PHI2_c +)
Destination: FF Data in Cmdn8MEGEN_546 (to PHI2_c -)
Delay: 12.319ns (31.8% logic, 68.2% route), 8 logic levels.
Constraint Details:
12.319ns physical path delay SLICE_111 to SLICE_24 meets
175.000ns delay constraint less
0.000ns skew and
0.307ns CE_SET requirement (totaling 174.693ns) by 162.374ns
Physical Path Details:
Data path SLICE_111 to SLICE_24:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R2C8C.CLK to R2C8C.Q0 SLICE_111 (from PHI2_c)
ROUTE 1 1.004 R2C8C.Q0 to R2C8B.B0 Bank_4
CTOF_DEL --- 0.495 R2C8B.B0 to R2C8B.F0 SLICE_158
ROUTE 1 1.535 R2C8B.F0 to R5C9D.B0 n4610
CTOF_DEL --- 0.495 R5C9D.B0 to R5C9D.F0 SLICE_139
ROUTE 2 1.086 R5C9D.F0 to R2C9D.C1 n4628
CTOF_DEL --- 0.495 R2C9D.C1 to R2C9D.F1 SLICE_114
ROUTE 4 0.788 R2C9D.F1 to R3C9D.C1 n2384
CTOF_DEL --- 0.495 R3C9D.C1 to R3C9D.F1 SLICE_130
ROUTE 2 0.995 R3C9D.F1 to R4C9B.A0 n4889
CTOF_DEL --- 0.495 R4C9B.A0 to R4C9B.F0 SLICE_21
ROUTE 4 1.474 R4C9B.F0 to R5C8D.B0 XOR8MEG_N_149
CTOF_DEL --- 0.495 R5C8D.B0 to R5C8D.F0 SLICE_112
ROUTE 1 0.436 R5C8D.F0 to R5C8D.C1 n4882
CTOF_DEL --- 0.495 R5C8D.C1 to R5C8D.F1 SLICE_112
ROUTE 2 1.084 R5C8D.F1 to R5C6B.CE PHI2_N_151_enable_5 (to PHI2_c)
--------
12.319 (31.8% logic, 68.2% route), 8 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_111:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.539 8.PADDI to R2C8C.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_24:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.539 8.PADDI to R5C6B.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 162.411ns (weighted slack = 324.822ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_i5 (from PHI2_c +)
Destination: FF Data in CmdLEDEN_545 (to PHI2_c -)
Delay: 12.282ns (31.9% logic, 68.1% route), 8 logic levels.
Constraint Details:
12.282ns physical path delay SLICE_111 to SLICE_20 meets
175.000ns delay constraint less
0.000ns skew and
0.307ns CE_SET requirement (totaling 174.693ns) by 162.411ns
Physical Path Details:
Data path SLICE_111 to SLICE_20:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R2C8C.CLK to R2C8C.Q1 SLICE_111 (from PHI2_c)
ROUTE 1 0.967 R2C8C.Q1 to R2C8B.A0 Bank_5
CTOF_DEL --- 0.495 R2C8B.A0 to R2C8B.F0 SLICE_158
ROUTE 1 1.535 R2C8B.F0 to R5C9D.B0 n4610
CTOF_DEL --- 0.495 R5C9D.B0 to R5C9D.F0 SLICE_139
ROUTE 2 1.086 R5C9D.F0 to R2C9D.C1 n4628
CTOF_DEL --- 0.495 R2C9D.C1 to R2C9D.F1 SLICE_114
ROUTE 4 0.788 R2C9D.F1 to R3C9D.C1 n2384
CTOF_DEL --- 0.495 R3C9D.C1 to R3C9D.F1 SLICE_130
ROUTE 2 0.995 R3C9D.F1 to R4C9B.A0 n4889
CTOF_DEL --- 0.495 R4C9B.A0 to R4C9B.F0 SLICE_21
ROUTE 4 1.474 R4C9B.F0 to R5C8D.B0 XOR8MEG_N_149
CTOF_DEL --- 0.495 R5C8D.B0 to R5C8D.F0 SLICE_112
ROUTE 1 0.436 R5C8D.F0 to R5C8D.C1 n4882
CTOF_DEL --- 0.495 R5C8D.C1 to R5C8D.F1 SLICE_112
ROUTE 2 1.084 R5C8D.F1 to R5C6A.CE PHI2_N_151_enable_5 (to PHI2_c)
--------
12.282 (31.9% logic, 68.1% route), 8 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_111:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.539 8.PADDI to R2C8C.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.539 8.PADDI to R5C6A.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 162.411ns (weighted slack = 324.822ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_i5 (from PHI2_c +)
Destination: FF Data in Cmdn8MEGEN_546 (to PHI2_c -)
Delay: 12.282ns (31.9% logic, 68.1% route), 8 logic levels.
Constraint Details:
12.282ns physical path delay SLICE_111 to SLICE_24 meets
175.000ns delay constraint less
0.000ns skew and
0.307ns CE_SET requirement (totaling 174.693ns) by 162.411ns
Physical Path Details:
Data path SLICE_111 to SLICE_24:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R2C8C.CLK to R2C8C.Q1 SLICE_111 (from PHI2_c)
ROUTE 1 0.967 R2C8C.Q1 to R2C8B.A0 Bank_5
CTOF_DEL --- 0.495 R2C8B.A0 to R2C8B.F0 SLICE_158
ROUTE 1 1.535 R2C8B.F0 to R5C9D.B0 n4610
CTOF_DEL --- 0.495 R5C9D.B0 to R5C9D.F0 SLICE_139
ROUTE 2 1.086 R5C9D.F0 to R2C9D.C1 n4628
CTOF_DEL --- 0.495 R2C9D.C1 to R2C9D.F1 SLICE_114
ROUTE 4 0.788 R2C9D.F1 to R3C9D.C1 n2384
CTOF_DEL --- 0.495 R3C9D.C1 to R3C9D.F1 SLICE_130
ROUTE 2 0.995 R3C9D.F1 to R4C9B.A0 n4889
CTOF_DEL --- 0.495 R4C9B.A0 to R4C9B.F0 SLICE_21
ROUTE 4 1.474 R4C9B.F0 to R5C8D.B0 XOR8MEG_N_149
CTOF_DEL --- 0.495 R5C8D.B0 to R5C8D.F0 SLICE_112
ROUTE 1 0.436 R5C8D.F0 to R5C8D.C1 n4882
CTOF_DEL --- 0.495 R5C8D.C1 to R5C8D.F1 SLICE_112
ROUTE 2 1.084 R5C8D.F1 to R5C6B.CE PHI2_N_151_enable_5 (to PHI2_c)
--------
12.282 (31.9% logic, 68.1% route), 8 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_111:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.539 8.PADDI to R2C8C.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_24:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.539 8.PADDI to R5C6B.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 163.336ns (weighted slack = 326.672ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_i6 (from PHI2_c +)
Destination: FF Data in CmdEnable_541 (to PHI2_c -)
Delay: 11.357ns (34.5% logic, 65.5% route), 8 logic levels.
Constraint Details:
11.357ns physical path delay SLICE_151 to SLICE_19 meets
175.000ns delay constraint less
0.000ns skew and
0.307ns CE_SET requirement (totaling 174.693ns) by 163.336ns
Physical Path Details:
Data path SLICE_151 to SLICE_19:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R5C9B.CLK to R5C9B.Q0 SLICE_151 (from PHI2_c)
ROUTE 1 1.278 R5C9B.Q0 to R2C8B.C0 Bank_6
CTOF_DEL --- 0.495 R2C8B.C0 to R2C8B.F0 SLICE_158
ROUTE 1 1.535 R2C8B.F0 to R5C9D.B0 n4610
CTOF_DEL --- 0.495 R5C9D.B0 to R5C9D.F0 SLICE_139
ROUTE 2 1.086 R5C9D.F0 to R2C9D.C1 n4628
CTOF_DEL --- 0.495 R2C9D.C1 to R2C9D.F1 SLICE_114
ROUTE 4 0.756 R2C9D.F1 to R2C9B.C1 n2384
CTOF_DEL --- 0.495 R2C9B.C1 to R2C9B.F1 SLICE_116
ROUTE 2 0.445 R2C9B.F1 to R2C9B.C0 n4888
CTOF_DEL --- 0.495 R2C9B.C0 to R2C9B.F0 SLICE_116
ROUTE 1 0.645 R2C9B.F0 to R3C9A.D1 n4624
CTOF_DEL --- 0.495 R3C9A.D1 to R3C9A.F1 SLICE_19
ROUTE 4 1.042 R3C9A.F1 to R3C9D.B0 C1Submitted_N_232
CTOF_DEL --- 0.495 R3C9D.B0 to R3C9D.F0 SLICE_130
ROUTE 1 0.653 R3C9D.F0 to R3C9A.CE PHI2_N_151_enable_1 (to PHI2_c)
--------
11.357 (34.5% logic, 65.5% route), 8 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_151:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.539 8.PADDI to R5C9B.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.539 8.PADDI to R3C9A.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 163.510ns (weighted slack = 327.020ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_i7 (from PHI2_c +)
Destination: FF Data in CmdLEDEN_545 (to PHI2_c -)
Delay: 11.183ns (35.0% logic, 65.0% route), 8 logic levels.
Constraint Details:
11.183ns physical path delay SLICE_151 to SLICE_20 meets
175.000ns delay constraint less
0.000ns skew and
0.307ns CE_SET requirement (totaling 174.693ns) by 163.510ns
Physical Path Details:
Data path SLICE_151 to SLICE_20:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R5C9B.CLK to R5C9B.Q1 SLICE_151 (from PHI2_c)
ROUTE 1 0.967 R5C9B.Q1 to R5C9D.A1 Bank_7
CTOF_DEL --- 0.495 R5C9D.A1 to R5C9D.F1 SLICE_139
ROUTE 1 0.436 R5C9D.F1 to R5C9D.C0 n4574
CTOF_DEL --- 0.495 R5C9D.C0 to R5C9D.F0 SLICE_139
ROUTE 2 1.086 R5C9D.F0 to R2C9D.C1 n4628
CTOF_DEL --- 0.495 R2C9D.C1 to R2C9D.F1 SLICE_114
ROUTE 4 0.788 R2C9D.F1 to R3C9D.C1 n2384
CTOF_DEL --- 0.495 R3C9D.C1 to R3C9D.F1 SLICE_130
ROUTE 2 0.995 R3C9D.F1 to R4C9B.A0 n4889
CTOF_DEL --- 0.495 R4C9B.A0 to R4C9B.F0 SLICE_21
ROUTE 4 1.474 R4C9B.F0 to R5C8D.B0 XOR8MEG_N_149
CTOF_DEL --- 0.495 R5C8D.B0 to R5C8D.F0 SLICE_112
ROUTE 1 0.436 R5C8D.F0 to R5C8D.C1 n4882
CTOF_DEL --- 0.495 R5C8D.C1 to R5C8D.F1 SLICE_112
ROUTE 2 1.084 R5C8D.F1 to R5C6A.CE PHI2_N_151_enable_5 (to PHI2_c)
--------
11.183 (35.0% logic, 65.0% route), 8 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_151:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.539 8.PADDI to R5C9B.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.539 8.PADDI to R5C6A.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 163.510ns (weighted slack = 327.020ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_i7 (from PHI2_c +)
Destination: FF Data in Cmdn8MEGEN_546 (to PHI2_c -)
Delay: 11.183ns (35.0% logic, 65.0% route), 8 logic levels.
Constraint Details:
11.183ns physical path delay SLICE_151 to SLICE_24 meets
175.000ns delay constraint less
0.000ns skew and
0.307ns CE_SET requirement (totaling 174.693ns) by 163.510ns
Physical Path Details:
Data path SLICE_151 to SLICE_24:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R5C9B.CLK to R5C9B.Q1 SLICE_151 (from PHI2_c)
ROUTE 1 0.967 R5C9B.Q1 to R5C9D.A1 Bank_7
CTOF_DEL --- 0.495 R5C9D.A1 to R5C9D.F1 SLICE_139
ROUTE 1 0.436 R5C9D.F1 to R5C9D.C0 n4574
CTOF_DEL --- 0.495 R5C9D.C0 to R5C9D.F0 SLICE_139
ROUTE 2 1.086 R5C9D.F0 to R2C9D.C1 n4628
CTOF_DEL --- 0.495 R2C9D.C1 to R2C9D.F1 SLICE_114
ROUTE 4 0.788 R2C9D.F1 to R3C9D.C1 n2384
CTOF_DEL --- 0.495 R3C9D.C1 to R3C9D.F1 SLICE_130
ROUTE 2 0.995 R3C9D.F1 to R4C9B.A0 n4889
CTOF_DEL --- 0.495 R4C9B.A0 to R4C9B.F0 SLICE_21
ROUTE 4 1.474 R4C9B.F0 to R5C8D.B0 XOR8MEG_N_149
CTOF_DEL --- 0.495 R5C8D.B0 to R5C8D.F0 SLICE_112
ROUTE 1 0.436 R5C8D.F0 to R5C8D.C1 n4882
CTOF_DEL --- 0.495 R5C8D.C1 to R5C8D.F1 SLICE_112
ROUTE 2 1.084 R5C8D.F1 to R5C6B.CE PHI2_N_151_enable_5 (to PHI2_c)
--------
11.183 (35.0% logic, 65.0% route), 8 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_151:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.539 8.PADDI to R5C9B.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_24:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.539 8.PADDI to R5C6B.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 163.610ns (weighted slack = 327.220ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_i4 (from PHI2_c +)
Destination: FF Data in CmdEnable_541 (to PHI2_c -)
Delay: 11.083ns (35.3% logic, 64.7% route), 8 logic levels.
Constraint Details:
11.083ns physical path delay SLICE_111 to SLICE_19 meets
175.000ns delay constraint less
0.000ns skew and
0.307ns CE_SET requirement (totaling 174.693ns) by 163.610ns
Physical Path Details:
Data path SLICE_111 to SLICE_19:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R2C8C.CLK to R2C8C.Q0 SLICE_111 (from PHI2_c)
ROUTE 1 1.004 R2C8C.Q0 to R2C8B.B0 Bank_4
CTOF_DEL --- 0.495 R2C8B.B0 to R2C8B.F0 SLICE_158
ROUTE 1 1.535 R2C8B.F0 to R5C9D.B0 n4610
CTOF_DEL --- 0.495 R5C9D.B0 to R5C9D.F0 SLICE_139
ROUTE 2 1.086 R5C9D.F0 to R2C9D.C1 n4628
CTOF_DEL --- 0.495 R2C9D.C1 to R2C9D.F1 SLICE_114
ROUTE 4 0.756 R2C9D.F1 to R2C9B.C1 n2384
CTOF_DEL --- 0.495 R2C9B.C1 to R2C9B.F1 SLICE_116
ROUTE 2 0.445 R2C9B.F1 to R2C9B.C0 n4888
CTOF_DEL --- 0.495 R2C9B.C0 to R2C9B.F0 SLICE_116
ROUTE 1 0.645 R2C9B.F0 to R3C9A.D1 n4624
CTOF_DEL --- 0.495 R3C9A.D1 to R3C9A.F1 SLICE_19
ROUTE 4 1.042 R3C9A.F1 to R3C9D.B0 C1Submitted_N_232
CTOF_DEL --- 0.495 R3C9D.B0 to R3C9D.F0 SLICE_130
ROUTE 1 0.653 R3C9D.F0 to R3C9A.CE PHI2_N_151_enable_1 (to PHI2_c)
--------
11.083 (35.3% logic, 64.7% route), 8 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_111:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.539 8.PADDI to R2C8C.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.539 8.PADDI to R3C9A.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Report: 25.800ns is the minimum period for this preference.
================================================================================
<A name="par_twr_pref_0_1"></A>Preference: PERIOD NET "nCCAS_c" 350.000000 ns ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 347.500ns
The internal maximum frequency of the following component is 400.000 MHz
Logical Details: Cell type Pin name Component name
Destination: SLICE CLK SLICE_122
Delay: 2.500ns -- based on Minimum Pulse Width
Report: 2.500ns is the minimum period for this preference.
================================================================================
<A name="par_twr_pref_0_2"></A>Preference: PERIOD NET "nCRAS_c" 350.000000 ns ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 347.500ns
The internal maximum frequency of the following component is 400.000 MHz
Logical Details: Cell type Pin name Component name
Destination: SLICE CLK SLICE_25
Delay: 2.500ns -- based on Minimum Pulse Width
Report: 2.500ns is the minimum period for this preference.
================================================================================
<A name="par_twr_pref_0_3"></A>Preference: PERIOD NET "RCLK_c" 16.000000 ns ;
1409 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.573ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS_972__i6 (from RCLK_c +)
Destination: FF Data in wb_adr_i4 (to RCLK_c +)
Delay: 12.261ns (37.8% logic, 62.2% route), 9 logic levels.
Constraint Details:
12.261ns physical path delay SLICE_6 to SLICE_70 meets
16.000ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 15.834ns) by 3.573ns
Physical Path Details:
Data path SLICE_6 to SLICE_70:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R6C6D.CLK to R6C6D.Q1 SLICE_6 (from RCLK_c)
ROUTE 21 1.808 R6C6D.Q1 to R3C7A.B1 FS_6
CTOF_DEL --- 0.495 R3C7A.B1 to R3C7A.F1 SLICE_98
ROUTE 4 1.021 R3C7A.F1 to R3C7D.B1 n4924
CTOF_DEL --- 0.495 R3C7D.B1 to R3C7D.F1 SLICE_93
ROUTE 1 1.001 R3C7D.F1 to R2C7D.B0 n98
CTOF_DEL --- 0.495 R2C7D.B0 to R2C7D.F0 SLICE_133
ROUTE 2 1.013 R2C7D.F0 to R2C7D.B1 n2199
CTOF_DEL --- 0.495 R2C7D.B1 to R2C7D.F1 SLICE_133
ROUTE 1 0.747 R2C7D.F1 to R2C7A.C1 n53
CTOOFX_DEL --- 0.721 R2C7A.C1 to R2C7A.OFX0 i29/SLICE_84
ROUTE 1 0.744 R2C7A.OFX0 to R2C6C.C1 n14_adj_3
CTOF_DEL --- 0.495 R2C6C.C1 to R2C6C.F1 SLICE_148
ROUTE 2 0.637 R2C6C.F1 to R2C5D.D0 n12_adj_8
CTOF_DEL --- 0.495 R2C5D.D0 to R2C5D.F0 SLICE_135
ROUTE 2 0.652 R2C5D.F0 to R2C3A.D1 n14_adj_7
CTOF_DEL --- 0.495 R2C3A.D1 to R2C3A.F1 SLICE_70
ROUTE 1 0.000 R2C3A.F1 to R2C3A.DI1 wb_adr_7_N_60_4 (to RCLK_c)
--------
12.261 (37.8% logic, 62.2% route), 9 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 52 2.019 63.PADDI to R6C6D.CLK RCLK_c
--------
2.019 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_70:
Name Fanout Delay (ns) Site Resource
ROUTE 52 2.019 63.PADDI to R2C3A.CLK RCLK_c
--------
2.019 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 3.573ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS_972__i6 (from RCLK_c +)
Destination: FF Data in wb_adr_i6 (to RCLK_c +)
Delay: 12.261ns (37.8% logic, 62.2% route), 9 logic levels.
Constraint Details:
12.261ns physical path delay SLICE_6 to SLICE_72 meets
16.000ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 15.834ns) by 3.573ns
Physical Path Details:
Data path SLICE_6 to SLICE_72:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R6C6D.CLK to R6C6D.Q1 SLICE_6 (from RCLK_c)
ROUTE 21 1.808 R6C6D.Q1 to R3C7A.B1 FS_6
CTOF_DEL --- 0.495 R3C7A.B1 to R3C7A.F1 SLICE_98
ROUTE 4 1.021 R3C7A.F1 to R3C7D.B1 n4924
CTOF_DEL --- 0.495 R3C7D.B1 to R3C7D.F1 SLICE_93
ROUTE 1 1.001 R3C7D.F1 to R2C7D.B0 n98
CTOF_DEL --- 0.495 R2C7D.B0 to R2C7D.F0 SLICE_133
ROUTE 2 1.013 R2C7D.F0 to R2C7D.B1 n2199
CTOF_DEL --- 0.495 R2C7D.B1 to R2C7D.F1 SLICE_133
ROUTE 1 0.747 R2C7D.F1 to R2C7A.C1 n53
CTOOFX_DEL --- 0.721 R2C7A.C1 to R2C7A.OFX0 i29/SLICE_84
ROUTE 1 0.744 R2C7A.OFX0 to R2C6C.C1 n14_adj_3
CTOF_DEL --- 0.495 R2C6C.C1 to R2C6C.F1 SLICE_148
ROUTE 2 0.637 R2C6C.F1 to R2C5D.D0 n12_adj_8
CTOF_DEL --- 0.495 R2C5D.D0 to R2C5D.F0 SLICE_135
ROUTE 2 0.652 R2C5D.F0 to R2C3D.D0 n14_adj_7
CTOF_DEL --- 0.495 R2C3D.D0 to R2C3D.F0 SLICE_72
ROUTE 1 0.000 R2C3D.F0 to R2C3D.DI0 wb_adr_7_N_60_6 (to RCLK_c)
--------
12.261 (37.8% logic, 62.2% route), 9 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 52 2.019 63.PADDI to R6C6D.CLK RCLK_c
--------
2.019 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_72:
Name Fanout Delay (ns) Site Resource
ROUTE 52 2.019 63.PADDI to R2C3D.CLK RCLK_c
--------
2.019 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 4.370ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS_972__i7 (from RCLK_c +)
Destination: FF Data in wb_adr_i4 (to RCLK_c +)
Delay: 11.464ns (36.1% logic, 63.9% route), 8 logic levels.
Constraint Details:
11.464ns physical path delay SLICE_5 to SLICE_70 meets
16.000ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 15.834ns) by 4.370ns
Physical Path Details:
Data path SLICE_5 to SLICE_70:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R6C7A.CLK to R6C7A.Q0 SLICE_5 (from RCLK_c)
ROUTE 25 2.442 R6C7A.Q0 to R2C8D.C1 FS_7
CTOF_DEL --- 0.495 R2C8D.C1 to R2C8D.F1 SLICE_143
ROUTE 2 1.427 R2C8D.F1 to R2C6A.B1 n4915
CTOF_DEL --- 0.495 R2C6A.B1 to R2C6A.F1 SLICE_113
ROUTE 5 0.672 R2C6A.F1 to R2C7D.D1 n4890
CTOF_DEL --- 0.495 R2C7D.D1 to R2C7D.F1 SLICE_133
ROUTE 1 0.747 R2C7D.F1 to R2C7A.C1 n53
CTOOFX_DEL --- 0.721 R2C7A.C1 to R2C7A.OFX0 i29/SLICE_84
ROUTE 1 0.744 R2C7A.OFX0 to R2C6C.C1 n14_adj_3
CTOF_DEL --- 0.495 R2C6C.C1 to R2C6C.F1 SLICE_148
ROUTE 2 0.637 R2C6C.F1 to R2C5D.D0 n12_adj_8
CTOF_DEL --- 0.495 R2C5D.D0 to R2C5D.F0 SLICE_135
ROUTE 2 0.652 R2C5D.F0 to R2C3A.D1 n14_adj_7
CTOF_DEL --- 0.495 R2C3A.D1 to R2C3A.F1 SLICE_70
ROUTE 1 0.000 R2C3A.F1 to R2C3A.DI1 wb_adr_7_N_60_4 (to RCLK_c)
--------
11.464 (36.1% logic, 63.9% route), 8 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_5:
Name Fanout Delay (ns) Site Resource
ROUTE 52 2.019 63.PADDI to R6C7A.CLK RCLK_c
--------
2.019 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_70:
Name Fanout Delay (ns) Site Resource
ROUTE 52 2.019 63.PADDI to R2C3A.CLK RCLK_c
--------
2.019 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 4.370ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS_972__i7 (from RCLK_c +)
Destination: FF Data in wb_adr_i6 (to RCLK_c +)
Delay: 11.464ns (36.1% logic, 63.9% route), 8 logic levels.
Constraint Details:
11.464ns physical path delay SLICE_5 to SLICE_72 meets
16.000ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 15.834ns) by 4.370ns
Physical Path Details:
Data path SLICE_5 to SLICE_72:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R6C7A.CLK to R6C7A.Q0 SLICE_5 (from RCLK_c)
ROUTE 25 2.442 R6C7A.Q0 to R2C8D.C1 FS_7
CTOF_DEL --- 0.495 R2C8D.C1 to R2C8D.F1 SLICE_143
ROUTE 2 1.427 R2C8D.F1 to R2C6A.B1 n4915
CTOF_DEL --- 0.495 R2C6A.B1 to R2C6A.F1 SLICE_113
ROUTE 5 0.672 R2C6A.F1 to R2C7D.D1 n4890
CTOF_DEL --- 0.495 R2C7D.D1 to R2C7D.F1 SLICE_133
ROUTE 1 0.747 R2C7D.F1 to R2C7A.C1 n53
CTOOFX_DEL --- 0.721 R2C7A.C1 to R2C7A.OFX0 i29/SLICE_84
ROUTE 1 0.744 R2C7A.OFX0 to R2C6C.C1 n14_adj_3
CTOF_DEL --- 0.495 R2C6C.C1 to R2C6C.F1 SLICE_148
ROUTE 2 0.637 R2C6C.F1 to R2C5D.D0 n12_adj_8
CTOF_DEL --- 0.495 R2C5D.D0 to R2C5D.F0 SLICE_135
ROUTE 2 0.652 R2C5D.F0 to R2C3D.D0 n14_adj_7
CTOF_DEL --- 0.495 R2C3D.D0 to R2C3D.F0 SLICE_72
ROUTE 1 0.000 R2C3D.F0 to R2C3D.DI0 wb_adr_7_N_60_6 (to RCLK_c)
--------
11.464 (36.1% logic, 63.9% route), 8 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_5:
Name Fanout Delay (ns) Site Resource
ROUTE 52 2.019 63.PADDI to R6C7A.CLK RCLK_c
--------
2.019 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_72:
Name Fanout Delay (ns) Site Resource
ROUTE 52 2.019 63.PADDI to R2C3D.CLK RCLK_c
--------
2.019 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 4.376ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS_972__i8 (from RCLK_c +)
Destination: FF Data in wb_adr_i4 (to RCLK_c +)
Delay: 11.458ns (40.5% logic, 59.5% route), 9 logic levels.
Constraint Details:
11.458ns physical path delay SLICE_5 to SLICE_70 meets
16.000ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 15.834ns) by 4.376ns
Physical Path Details:
Data path SLICE_5 to SLICE_70:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R6C7A.CLK to R6C7A.Q1 SLICE_5 (from RCLK_c)
ROUTE 23 1.005 R6C7A.Q1 to R3C7A.D1 FS_8
CTOF_DEL --- 0.495 R3C7A.D1 to R3C7A.F1 SLICE_98
ROUTE 4 1.021 R3C7A.F1 to R3C7D.B1 n4924
CTOF_DEL --- 0.495 R3C7D.B1 to R3C7D.F1 SLICE_93
ROUTE 1 1.001 R3C7D.F1 to R2C7D.B0 n98
CTOF_DEL --- 0.495 R2C7D.B0 to R2C7D.F0 SLICE_133
ROUTE 2 1.013 R2C7D.F0 to R2C7D.B1 n2199
CTOF_DEL --- 0.495 R2C7D.B1 to R2C7D.F1 SLICE_133
ROUTE 1 0.747 R2C7D.F1 to R2C7A.C1 n53
CTOOFX_DEL --- 0.721 R2C7A.C1 to R2C7A.OFX0 i29/SLICE_84
ROUTE 1 0.744 R2C7A.OFX0 to R2C6C.C1 n14_adj_3
CTOF_DEL --- 0.495 R2C6C.C1 to R2C6C.F1 SLICE_148
ROUTE 2 0.637 R2C6C.F1 to R2C5D.D0 n12_adj_8
CTOF_DEL --- 0.495 R2C5D.D0 to R2C5D.F0 SLICE_135
ROUTE 2 0.652 R2C5D.F0 to R2C3A.D1 n14_adj_7
CTOF_DEL --- 0.495 R2C3A.D1 to R2C3A.F1 SLICE_70
ROUTE 1 0.000 R2C3A.F1 to R2C3A.DI1 wb_adr_7_N_60_4 (to RCLK_c)
--------
11.458 (40.5% logic, 59.5% route), 9 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_5:
Name Fanout Delay (ns) Site Resource
ROUTE 52 2.019 63.PADDI to R6C7A.CLK RCLK_c
--------
2.019 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_70:
Name Fanout Delay (ns) Site Resource
ROUTE 52 2.019 63.PADDI to R2C3A.CLK RCLK_c
--------
2.019 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 4.376ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS_972__i8 (from RCLK_c +)
Destination: FF Data in wb_adr_i6 (to RCLK_c +)
Delay: 11.458ns (40.5% logic, 59.5% route), 9 logic levels.
Constraint Details:
11.458ns physical path delay SLICE_5 to SLICE_72 meets
16.000ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 15.834ns) by 4.376ns
Physical Path Details:
Data path SLICE_5 to SLICE_72:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R6C7A.CLK to R6C7A.Q1 SLICE_5 (from RCLK_c)
ROUTE 23 1.005 R6C7A.Q1 to R3C7A.D1 FS_8
CTOF_DEL --- 0.495 R3C7A.D1 to R3C7A.F1 SLICE_98
ROUTE 4 1.021 R3C7A.F1 to R3C7D.B1 n4924
CTOF_DEL --- 0.495 R3C7D.B1 to R3C7D.F1 SLICE_93
ROUTE 1 1.001 R3C7D.F1 to R2C7D.B0 n98
CTOF_DEL --- 0.495 R2C7D.B0 to R2C7D.F0 SLICE_133
ROUTE 2 1.013 R2C7D.F0 to R2C7D.B1 n2199
CTOF_DEL --- 0.495 R2C7D.B1 to R2C7D.F1 SLICE_133
ROUTE 1 0.747 R2C7D.F1 to R2C7A.C1 n53
CTOOFX_DEL --- 0.721 R2C7A.C1 to R2C7A.OFX0 i29/SLICE_84
ROUTE 1 0.744 R2C7A.OFX0 to R2C6C.C1 n14_adj_3
CTOF_DEL --- 0.495 R2C6C.C1 to R2C6C.F1 SLICE_148
ROUTE 2 0.637 R2C6C.F1 to R2C5D.D0 n12_adj_8
CTOF_DEL --- 0.495 R2C5D.D0 to R2C5D.F0 SLICE_135
ROUTE 2 0.652 R2C5D.F0 to R2C3D.D0 n14_adj_7
CTOF_DEL --- 0.495 R2C3D.D0 to R2C3D.F0 SLICE_72
ROUTE 1 0.000 R2C3D.F0 to R2C3D.DI0 wb_adr_7_N_60_6 (to RCLK_c)
--------
11.458 (40.5% logic, 59.5% route), 9 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_5:
Name Fanout Delay (ns) Site Resource
ROUTE 52 2.019 63.PADDI to R6C7A.CLK RCLK_c
--------
2.019 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_72:
Name Fanout Delay (ns) Site Resource
ROUTE 52 2.019 63.PADDI to R2C3D.CLK RCLK_c
--------
2.019 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 4.398ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS_972__i6 (from RCLK_c +)
Destination: FF Data in wb_adr_i4 (to RCLK_c +)
Delay: 11.436ns (40.6% logic, 59.4% route), 9 logic levels.
Constraint Details:
11.436ns physical path delay SLICE_6 to SLICE_70 meets
16.000ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 15.834ns) by 4.398ns
Physical Path Details:
Data path SLICE_6 to SLICE_70:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R6C6D.CLK to R6C6D.Q1 SLICE_6 (from RCLK_c)
ROUTE 21 1.551 R6C6D.Q1 to R3C7D.C0 FS_6
CTOF_DEL --- 0.495 R3C7D.C0 to R3C7D.F0 SLICE_93
ROUTE 3 0.453 R3C7D.F0 to R3C7D.C1 n53_adj_9
CTOF_DEL --- 0.495 R3C7D.C1 to R3C7D.F1 SLICE_93
ROUTE 1 1.001 R3C7D.F1 to R2C7D.B0 n98
CTOF_DEL --- 0.495 R2C7D.B0 to R2C7D.F0 SLICE_133
ROUTE 2 1.013 R2C7D.F0 to R2C7D.B1 n2199
CTOF_DEL --- 0.495 R2C7D.B1 to R2C7D.F1 SLICE_133
ROUTE 1 0.747 R2C7D.F1 to R2C7A.C1 n53
CTOOFX_DEL --- 0.721 R2C7A.C1 to R2C7A.OFX0 i29/SLICE_84
ROUTE 1 0.744 R2C7A.OFX0 to R2C6C.C1 n14_adj_3
CTOF_DEL --- 0.495 R2C6C.C1 to R2C6C.F1 SLICE_148
ROUTE 2 0.637 R2C6C.F1 to R2C5D.D0 n12_adj_8
CTOF_DEL --- 0.495 R2C5D.D0 to R2C5D.F0 SLICE_135
ROUTE 2 0.652 R2C5D.F0 to R2C3A.D1 n14_adj_7
CTOF_DEL --- 0.495 R2C3A.D1 to R2C3A.F1 SLICE_70
ROUTE 1 0.000 R2C3A.F1 to R2C3A.DI1 wb_adr_7_N_60_4 (to RCLK_c)
--------
11.436 (40.6% logic, 59.4% route), 9 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 52 2.019 63.PADDI to R6C6D.CLK RCLK_c
--------
2.019 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_70:
Name Fanout Delay (ns) Site Resource
ROUTE 52 2.019 63.PADDI to R2C3A.CLK RCLK_c
--------
2.019 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 4.398ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS_972__i6 (from RCLK_c +)
Destination: FF Data in wb_adr_i6 (to RCLK_c +)
Delay: 11.436ns (40.6% logic, 59.4% route), 9 logic levels.
Constraint Details:
11.436ns physical path delay SLICE_6 to SLICE_72 meets
16.000ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 15.834ns) by 4.398ns
Physical Path Details:
Data path SLICE_6 to SLICE_72:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R6C6D.CLK to R6C6D.Q1 SLICE_6 (from RCLK_c)
ROUTE 21 1.551 R6C6D.Q1 to R3C7D.C0 FS_6
CTOF_DEL --- 0.495 R3C7D.C0 to R3C7D.F0 SLICE_93
ROUTE 3 0.453 R3C7D.F0 to R3C7D.C1 n53_adj_9
CTOF_DEL --- 0.495 R3C7D.C1 to R3C7D.F1 SLICE_93
ROUTE 1 1.001 R3C7D.F1 to R2C7D.B0 n98
CTOF_DEL --- 0.495 R2C7D.B0 to R2C7D.F0 SLICE_133
ROUTE 2 1.013 R2C7D.F0 to R2C7D.B1 n2199
CTOF_DEL --- 0.495 R2C7D.B1 to R2C7D.F1 SLICE_133
ROUTE 1 0.747 R2C7D.F1 to R2C7A.C1 n53
CTOOFX_DEL --- 0.721 R2C7A.C1 to R2C7A.OFX0 i29/SLICE_84
ROUTE 1 0.744 R2C7A.OFX0 to R2C6C.C1 n14_adj_3
CTOF_DEL --- 0.495 R2C6C.C1 to R2C6C.F1 SLICE_148
ROUTE 2 0.637 R2C6C.F1 to R2C5D.D0 n12_adj_8
CTOF_DEL --- 0.495 R2C5D.D0 to R2C5D.F0 SLICE_135
ROUTE 2 0.652 R2C5D.F0 to R2C3D.D0 n14_adj_7
CTOF_DEL --- 0.495 R2C3D.D0 to R2C3D.F0 SLICE_72
ROUTE 1 0.000 R2C3D.F0 to R2C3D.DI0 wb_adr_7_N_60_6 (to RCLK_c)
--------
11.436 (40.6% logic, 59.4% route), 9 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 52 2.019 63.PADDI to R6C6D.CLK RCLK_c
--------
2.019 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_72:
Name Fanout Delay (ns) Site Resource
ROUTE 52 2.019 63.PADDI to R2C3D.CLK RCLK_c
--------
2.019 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 4.449ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS_972__i5 (from RCLK_c +)
Destination: FF Data in wb_adr_i4 (to RCLK_c +)
Delay: 11.385ns (40.7% logic, 59.3% route), 9 logic levels.
Constraint Details:
11.385ns physical path delay SLICE_6 to SLICE_70 meets
16.000ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 15.834ns) by 4.449ns
Physical Path Details:
Data path SLICE_6 to SLICE_70:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R6C6D.CLK to R6C6D.Q0 SLICE_6 (from RCLK_c)
ROUTE 21 1.500 R6C6D.Q0 to R3C7D.D0 FS_5
CTOF_DEL --- 0.495 R3C7D.D0 to R3C7D.F0 SLICE_93
ROUTE 3 0.453 R3C7D.F0 to R3C7D.C1 n53_adj_9
CTOF_DEL --- 0.495 R3C7D.C1 to R3C7D.F1 SLICE_93
ROUTE 1 1.001 R3C7D.F1 to R2C7D.B0 n98
CTOF_DEL --- 0.495 R2C7D.B0 to R2C7D.F0 SLICE_133
ROUTE 2 1.013 R2C7D.F0 to R2C7D.B1 n2199
CTOF_DEL --- 0.495 R2C7D.B1 to R2C7D.F1 SLICE_133
ROUTE 1 0.747 R2C7D.F1 to R2C7A.C1 n53
CTOOFX_DEL --- 0.721 R2C7A.C1 to R2C7A.OFX0 i29/SLICE_84
ROUTE 1 0.744 R2C7A.OFX0 to R2C6C.C1 n14_adj_3
CTOF_DEL --- 0.495 R2C6C.C1 to R2C6C.F1 SLICE_148
ROUTE 2 0.637 R2C6C.F1 to R2C5D.D0 n12_adj_8
CTOF_DEL --- 0.495 R2C5D.D0 to R2C5D.F0 SLICE_135
ROUTE 2 0.652 R2C5D.F0 to R2C3A.D1 n14_adj_7
CTOF_DEL --- 0.495 R2C3A.D1 to R2C3A.F1 SLICE_70
ROUTE 1 0.000 R2C3A.F1 to R2C3A.DI1 wb_adr_7_N_60_4 (to RCLK_c)
--------
11.385 (40.7% logic, 59.3% route), 9 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 52 2.019 63.PADDI to R6C6D.CLK RCLK_c
--------
2.019 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_70:
Name Fanout Delay (ns) Site Resource
ROUTE 52 2.019 63.PADDI to R2C3A.CLK RCLK_c
--------
2.019 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 4.449ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS_972__i5 (from RCLK_c +)
Destination: FF Data in wb_adr_i6 (to RCLK_c +)
Delay: 11.385ns (40.7% logic, 59.3% route), 9 logic levels.
Constraint Details:
11.385ns physical path delay SLICE_6 to SLICE_72 meets
16.000ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 15.834ns) by 4.449ns
Physical Path Details:
Data path SLICE_6 to SLICE_72:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R6C6D.CLK to R6C6D.Q0 SLICE_6 (from RCLK_c)
ROUTE 21 1.500 R6C6D.Q0 to R3C7D.D0 FS_5
CTOF_DEL --- 0.495 R3C7D.D0 to R3C7D.F0 SLICE_93
ROUTE 3 0.453 R3C7D.F0 to R3C7D.C1 n53_adj_9
CTOF_DEL --- 0.495 R3C7D.C1 to R3C7D.F1 SLICE_93
ROUTE 1 1.001 R3C7D.F1 to R2C7D.B0 n98
CTOF_DEL --- 0.495 R2C7D.B0 to R2C7D.F0 SLICE_133
ROUTE 2 1.013 R2C7D.F0 to R2C7D.B1 n2199
CTOF_DEL --- 0.495 R2C7D.B1 to R2C7D.F1 SLICE_133
ROUTE 1 0.747 R2C7D.F1 to R2C7A.C1 n53
CTOOFX_DEL --- 0.721 R2C7A.C1 to R2C7A.OFX0 i29/SLICE_84
ROUTE 1 0.744 R2C7A.OFX0 to R2C6C.C1 n14_adj_3
CTOF_DEL --- 0.495 R2C6C.C1 to R2C6C.F1 SLICE_148
ROUTE 2 0.637 R2C6C.F1 to R2C5D.D0 n12_adj_8
CTOF_DEL --- 0.495 R2C5D.D0 to R2C5D.F0 SLICE_135
ROUTE 2 0.652 R2C5D.F0 to R2C3D.D0 n14_adj_7
CTOF_DEL --- 0.495 R2C3D.D0 to R2C3D.F0 SLICE_72
ROUTE 1 0.000 R2C3D.F0 to R2C3D.DI0 wb_adr_7_N_60_6 (to RCLK_c)
--------
11.385 (40.7% logic, 59.3% route), 9 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 52 2.019 63.PADDI to R6C6D.CLK RCLK_c
--------
2.019 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_72:
Name Fanout Delay (ns) Site Resource
ROUTE 52 2.019 63.PADDI to R2C3D.CLK RCLK_c
--------
2.019 (0.0% logic, 100.0% route), 0 logic levels.
Report: 12.427ns is the minimum period for this preference.
================================================================================
<A name="par_twr_pref_0_4"></A>Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_5"></A>Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_6"></A>Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_7"></A>Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_8"></A>Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_9"></A>Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_10"></A>Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_11"></A>Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_12"></A>Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_13"></A>Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_14"></A>Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_15"></A>Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_16"></A>Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.015ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RA10_536 (from RCLK_c +)
Destination: Port Pad RA[10]
Data Path Delay: 6.334ns (71.9% logic, 28.1% route), 2 logic levels.
Clock Path Delay: 3.151ns (35.9% logic, 64.1% route), 1 logic levels.
Constraint Details:
3.151ns delay RCLK to SLICE_54 and
6.334ns delay SLICE_54 to RA[10] (totaling 9.485ns) meets
12.500ns offset RCLK to RA[10] by 3.015ns
Physical Path Details:
Clock path RCLK to SLICE_54:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK
ROUTE 52 2.019 63.PADDI to R4C11D.CLK RCLK_c
--------
3.151 (35.9% logic, 64.1% route), 1 logic levels.
Data path SLICE_54 to RA[10]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R4C11D.CLK to R4C11D.Q0 SLICE_54 (from RCLK_c)
ROUTE 1 1.777 R4C11D.Q0 to 64.PADDO n1975
DOPAD_DEL --- 4.105 64.PADDO to 64.PAD RA[10]
--------
6.334 (71.9% logic, 28.1% route), 2 logic levels.
Report: 9.485ns is the minimum offset for this preference.
================================================================================
<A name="par_twr_pref_0_17"></A>Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1.495ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_538 (from RCLK_c +)
Destination: Port Pad RA[9]
Data Path Delay: 7.854ns (64.3% logic, 35.7% route), 3 logic levels.
Clock Path Delay: 3.151ns (35.9% logic, 64.1% route), 1 logic levels.
Constraint Details:
3.151ns delay RCLK to SLICE_63 and
7.854ns delay SLICE_63 to RA[9] (totaling 11.005ns) meets
12.500ns offset RCLK to RA[9] by 1.495ns
Physical Path Details:
Clock path RCLK to SLICE_63:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK
ROUTE 52 2.019 63.PADDI to R5C10A.CLK RCLK_c
--------
3.151 (35.9% logic, 64.1% route), 1 logic levels.
Data path SLICE_63 to RA[9]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c)
ROUTE 12 1.016 R5C10A.Q0 to R5C9B.A0 nRowColSel
CTOF_DEL --- 0.495 R5C9B.A0 to R5C9B.F0 SLICE_151
ROUTE 1 1.786 R5C9B.F0 to 62.PADDO RA_c_9
DOPAD_DEL --- 4.105 62.PADDO to 62.PAD RA[9]
--------
7.854 (64.3% logic, 35.7% route), 3 logic levels.
Report: 11.005ns is the minimum offset for this preference.
================================================================================
<A name="par_twr_pref_0_18"></A>Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1.386ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_538 (from RCLK_c +)
Destination: Port Pad RA[8]
Data Path Delay: 7.963ns (63.4% logic, 36.6% route), 3 logic levels.
Clock Path Delay: 3.151ns (35.9% logic, 64.1% route), 1 logic levels.
Constraint Details:
3.151ns delay RCLK to SLICE_63 and
7.963ns delay SLICE_63 to RA[8] (totaling 11.114ns) meets
12.500ns offset RCLK to RA[8] by 1.386ns
Physical Path Details:
Clock path RCLK to SLICE_63:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK
ROUTE 52 2.019 63.PADDI to R5C10A.CLK RCLK_c
--------
3.151 (35.9% logic, 64.1% route), 1 logic levels.
Data path SLICE_63 to RA[8]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c)
ROUTE 12 1.053 R5C10A.Q0 to R4C10D.B1 nRowColSel
CTOF_DEL --- 0.495 R4C10D.B1 to R4C10D.F1 SLICE_163
ROUTE 1 1.858 R4C10D.F1 to 65.PADDO RA_c_8
DOPAD_DEL --- 4.105 65.PADDO to 65.PAD RA[8]
--------
7.963 (63.4% logic, 36.6% route), 3 logic levels.
Report: 11.114ns is the minimum offset for this preference.
================================================================================
<A name="par_twr_pref_0_19"></A>Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1.552ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_538 (from RCLK_c +)
Destination: Port Pad RA[7]
Data Path Delay: 7.797ns (64.8% logic, 35.2% route), 3 logic levels.
Clock Path Delay: 3.151ns (35.9% logic, 64.1% route), 1 logic levels.
Constraint Details:
3.151ns delay RCLK to SLICE_63 and
7.797ns delay SLICE_63 to RA[7] (totaling 10.948ns) meets
12.500ns offset RCLK to RA[7] by 1.552ns
Physical Path Details:
Clock path RCLK to SLICE_63:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK
ROUTE 52 2.019 63.PADDI to R5C10A.CLK RCLK_c
--------
3.151 (35.9% logic, 64.1% route), 1 logic levels.
Data path SLICE_63 to RA[7]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c)
ROUTE 12 1.017 R5C10A.Q0 to R2C10D.D1 nRowColSel
CTOF_DEL --- 0.495 R2C10D.D1 to R2C10D.F1 SLICE_155
ROUTE 1 1.728 R2C10D.F1 to 75.PADDO RA_c_7
DOPAD_DEL --- 4.105 75.PADDO to 75.PAD RA[7]
--------
7.797 (64.8% logic, 35.2% route), 3 logic levels.
Report: 10.948ns is the minimum offset for this preference.
================================================================================
<A name="par_twr_pref_0_20"></A>Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1.401ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_538 (from RCLK_c +)
Destination: Port Pad RA[6]
Data Path Delay: 7.948ns (63.6% logic, 36.4% route), 3 logic levels.
Clock Path Delay: 3.151ns (35.9% logic, 64.1% route), 1 logic levels.
Constraint Details:
3.151ns delay RCLK to SLICE_63 and
7.948ns delay SLICE_63 to RA[6] (totaling 11.099ns) meets
12.500ns offset RCLK to RA[6] by 1.401ns
Physical Path Details:
Clock path RCLK to SLICE_63:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK
ROUTE 52 2.019 63.PADDI to R5C10A.CLK RCLK_c
--------
3.151 (35.9% logic, 64.1% route), 1 logic levels.
Data path SLICE_63 to RA[6]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c)
ROUTE 12 1.053 R5C10A.Q0 to R4C10D.B0 nRowColSel
CTOF_DEL --- 0.495 R4C10D.B0 to R4C10D.F0 SLICE_163
ROUTE 1 1.843 R4C10D.F0 to 68.PADDO RA_c_6
DOPAD_DEL --- 4.105 68.PADDO to 68.PAD RA[6]
--------
7.948 (63.6% logic, 36.4% route), 3 logic levels.
Report: 11.099ns is the minimum offset for this preference.
================================================================================
<A name="par_twr_pref_0_21"></A>Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1.135ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_538 (from RCLK_c +)
Destination: Port Pad RA[5]
Data Path Delay: 8.214ns (61.5% logic, 38.5% route), 3 logic levels.
Clock Path Delay: 3.151ns (35.9% logic, 64.1% route), 1 logic levels.
Constraint Details:
3.151ns delay RCLK to SLICE_63 and
8.214ns delay SLICE_63 to RA[5] (totaling 11.365ns) meets
12.500ns offset RCLK to RA[5] by 1.135ns
Physical Path Details:
Clock path RCLK to SLICE_63:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK
ROUTE 52 2.019 63.PADDI to R5C10A.CLK RCLK_c
--------
3.151 (35.9% logic, 64.1% route), 1 logic levels.
Data path SLICE_63 to RA[5]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c)
ROUTE 12 1.310 R5C10A.Q0 to R2C9A.C1 nRowColSel
CTOF_DEL --- 0.495 R2C9A.C1 to R2C9A.F1 SLICE_157
ROUTE 1 1.852 R2C9A.F1 to 70.PADDO RA_c_5
DOPAD_DEL --- 4.105 70.PADDO to 70.PAD RA[5]
--------
8.214 (61.5% logic, 38.5% route), 3 logic levels.
Report: 11.365ns is the minimum offset for this preference.
================================================================================
<A name="par_twr_pref_0_22"></A>Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1.135ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_538 (from RCLK_c +)
Destination: Port Pad RA[4]
Data Path Delay: 8.214ns (61.5% logic, 38.5% route), 3 logic levels.
Clock Path Delay: 3.151ns (35.9% logic, 64.1% route), 1 logic levels.
Constraint Details:
3.151ns delay RCLK to SLICE_63 and
8.214ns delay SLICE_63 to RA[4] (totaling 11.365ns) meets
12.500ns offset RCLK to RA[4] by 1.135ns
Physical Path Details:
Clock path RCLK to SLICE_63:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK
ROUTE 52 2.019 63.PADDI to R5C10A.CLK RCLK_c
--------
3.151 (35.9% logic, 64.1% route), 1 logic levels.
Data path SLICE_63 to RA[4]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c)
ROUTE 12 1.310 R5C10A.Q0 to R2C8B.C1 nRowColSel
CTOF_DEL --- 0.495 R2C8B.C1 to R2C8B.F1 SLICE_158
ROUTE 1 1.852 R2C8B.F1 to 74.PADDO RA_c_4
DOPAD_DEL --- 4.105 74.PADDO to 74.PAD RA[4]
--------
8.214 (61.5% logic, 38.5% route), 3 logic levels.
Report: 11.365ns is the minimum offset for this preference.
================================================================================
<A name="par_twr_pref_0_23"></A>Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1.322ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_538 (from RCLK_c +)
Destination: Port Pad RA[3]
Data Path Delay: 8.027ns (62.9% logic, 37.1% route), 3 logic levels.
Clock Path Delay: 3.151ns (35.9% logic, 64.1% route), 1 logic levels.
Constraint Details:
3.151ns delay RCLK to SLICE_63 and
8.027ns delay SLICE_63 to RA[3] (totaling 11.178ns) meets
12.500ns offset RCLK to RA[3] by 1.322ns
Physical Path Details:
Clock path RCLK to SLICE_63:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK
ROUTE 52 2.019 63.PADDI to R5C10A.CLK RCLK_c
--------
3.151 (35.9% logic, 64.1% route), 1 logic levels.
Data path SLICE_63 to RA[3]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c)
ROUTE 12 0.990 R5C10A.Q0 to R3C10C.D0 nRowColSel
CTOF_DEL --- 0.495 R3C10C.D0 to R3C10C.F0 SLICE_162
ROUTE 1 1.985 R3C10C.F0 to 71.PADDO RA_c_3
DOPAD_DEL --- 4.105 71.PADDO to 71.PAD RA[3]
--------
8.027 (62.9% logic, 37.1% route), 3 logic levels.
Report: 11.178ns is the minimum offset for this preference.
================================================================================
<A name="par_twr_pref_0_24"></A>Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1.577ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_538 (from RCLK_c +)
Destination: Port Pad RA[2]
Data Path Delay: 7.772ns (65.0% logic, 35.0% route), 3 logic levels.
Clock Path Delay: 3.151ns (35.9% logic, 64.1% route), 1 logic levels.
Constraint Details:
3.151ns delay RCLK to SLICE_63 and
7.772ns delay SLICE_63 to RA[2] (totaling 10.923ns) meets
12.500ns offset RCLK to RA[2] by 1.577ns
Physical Path Details:
Clock path RCLK to SLICE_63:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK
ROUTE 52 2.019 63.PADDI to R5C10A.CLK RCLK_c
--------
3.151 (35.9% logic, 64.1% route), 1 logic levels.
Data path SLICE_63 to RA[2]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c)
ROUTE 12 0.796 R5C10A.Q0 to R5C9C.C0 nRowColSel
CTOF_DEL --- 0.495 R5C9C.C0 to R5C9C.F0 SLICE_161
ROUTE 1 1.924 R5C9C.F0 to 69.PADDO RA_c_2
DOPAD_DEL --- 4.105 69.PADDO to 69.PAD RA[2]
--------
7.772 (65.0% logic, 35.0% route), 3 logic levels.
Report: 10.923ns is the minimum offset for this preference.
================================================================================
<A name="par_twr_pref_0_25"></A>Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1.579ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_538 (from RCLK_c +)
Destination: Port Pad RA[1]
Data Path Delay: 7.770ns (65.0% logic, 35.0% route), 3 logic levels.
Clock Path Delay: 3.151ns (35.9% logic, 64.1% route), 1 logic levels.
Constraint Details:
3.151ns delay RCLK to SLICE_63 and
7.770ns delay SLICE_63 to RA[1] (totaling 10.921ns) meets
12.500ns offset RCLK to RA[1] by 1.579ns
Physical Path Details:
Clock path RCLK to SLICE_63:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK
ROUTE 52 2.019 63.PADDI to R5C10A.CLK RCLK_c
--------
3.151 (35.9% logic, 64.1% route), 1 logic levels.
Data path SLICE_63 to RA[1]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c)
ROUTE 12 0.990 R5C10A.Q0 to R3C10C.D1 nRowColSel
CTOF_DEL --- 0.495 R3C10C.D1 to R3C10C.F1 SLICE_162
ROUTE 1 1.728 R3C10C.F1 to 67.PADDO RA_c_1
DOPAD_DEL --- 4.105 67.PADDO to 67.PAD RA[1]
--------
7.770 (65.0% logic, 35.0% route), 3 logic levels.
Report: 10.921ns is the minimum offset for this preference.
================================================================================
<A name="par_twr_pref_0_26"></A>Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1.855ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_538 (from RCLK_c +)
Destination: Port Pad RA[0]
Data Path Delay: 7.494ns (67.4% logic, 32.6% route), 3 logic levels.
Clock Path Delay: 3.151ns (35.9% logic, 64.1% route), 1 logic levels.
Constraint Details:
3.151ns delay RCLK to SLICE_63 and
7.494ns delay SLICE_63 to RA[0] (totaling 10.645ns) meets
12.500ns offset RCLK to RA[0] by 1.855ns
Physical Path Details:
Clock path RCLK to SLICE_63:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK
ROUTE 52 2.019 63.PADDI to R5C10A.CLK RCLK_c
--------
3.151 (35.9% logic, 64.1% route), 1 logic levels.
Data path SLICE_63 to RA[0]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c)
ROUTE 12 1.017 R5C10A.Q0 to R3C10D.D1 nRowColSel
CTOF_DEL --- 0.495 R3C10D.D1 to R3C10D.F1 SLICE_159
ROUTE 1 1.425 R3C10D.F1 to 66.PADDO RA_c_0
DOPAD_DEL --- 4.105 66.PADDO to 66.PAD RA[0]
--------
7.494 (67.4% logic, 32.6% route), 3 logic levels.
Report: 10.645ns is the minimum offset for this preference.
================================================================================
<A name="par_twr_pref_0_27"></A>Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.826ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRCS_532 (from RCLK_c +)
Destination: Port Pad nRCS
Data Path Delay: 6.523ns (69.9% logic, 30.1% route), 2 logic levels.
Clock Path Delay: 3.151ns (35.9% logic, 64.1% route), 1 logic levels.
Constraint Details:
3.151ns delay RCLK to SLICE_59 and
6.523ns delay SLICE_59 to nRCS (totaling 9.674ns) meets
12.500ns offset RCLK to nRCS by 2.826ns
Physical Path Details:
Clock path RCLK to SLICE_59:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK
ROUTE 52 2.019 63.PADDI to R4C11B.CLK RCLK_c
--------
3.151 (35.9% logic, 64.1% route), 1 logic levels.
Data path SLICE_59 to nRCS:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R4C11B.CLK to R4C11B.Q0 SLICE_59 (from RCLK_c)
ROUTE 1 1.966 R4C11B.Q0 to 57.PADDO nRCS_c
DOPAD_DEL --- 4.105 57.PADDO to 57.PAD nRCS
--------
6.523 (69.9% logic, 30.1% route), 2 logic levels.
Report: 9.674ns is the minimum offset for this preference.
================================================================================
<A name="par_twr_pref_0_28"></A>Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.616ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RCKE_531 (from RCLK_c +)
Destination: Port Pad RCKE
Data Path Delay: 6.733ns (67.7% logic, 32.3% route), 2 logic levels.
Clock Path Delay: 3.151ns (35.9% logic, 64.1% route), 1 logic levels.
Constraint Details:
3.151ns delay RCLK to SLICE_35 and
6.733ns delay SLICE_35 to RCKE (totaling 9.884ns) meets
12.500ns offset RCLK to RCKE by 2.616ns
Physical Path Details:
Clock path RCLK to SLICE_35:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK
ROUTE 52 2.019 63.PADDI to R4C7B.CLK RCLK_c
--------
3.151 (35.9% logic, 64.1% route), 1 logic levels.
Data path SLICE_35 to RCKE:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R4C7B.CLK to R4C7B.Q0 SLICE_35 (from RCLK_c)
ROUTE 4 2.176 R4C7B.Q0 to 53.PADDO RCKE_c
DOPAD_DEL --- 4.105 53.PADDO to 53.PAD RCKE
--------
6.733 (67.7% logic, 32.3% route), 2 logic levels.
Report: 9.884ns is the minimum offset for this preference.
================================================================================
<A name="par_twr_pref_0_29"></A>Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.225ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRWE_535 (from RCLK_c +)
Destination: Port Pad nRWE
Data Path Delay: 6.124ns (74.4% logic, 25.6% route), 2 logic levels.
Clock Path Delay: 3.151ns (35.9% logic, 64.1% route), 1 logic levels.
Constraint Details:
3.151ns delay RCLK to SLICE_62 and
6.124ns delay SLICE_62 to nRWE (totaling 9.275ns) meets
12.500ns offset RCLK to nRWE by 3.225ns
Physical Path Details:
Clock path RCLK to SLICE_62:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK
ROUTE 52 2.019 63.PADDI to R5C11A.CLK RCLK_c
--------
3.151 (35.9% logic, 64.1% route), 1 logic levels.
Data path SLICE_62 to nRWE:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R5C11A.CLK to R5C11A.Q0 SLICE_62 (from RCLK_c)
ROUTE 1 1.567 R5C11A.Q0 to 49.PADDO nRWE_c
DOPAD_DEL --- 4.105 49.PADDO to 49.PAD nRWE
--------
6.124 (74.4% logic, 25.6% route), 2 logic levels.
Report: 9.275ns is the minimum offset for this preference.
================================================================================
<A name="par_twr_pref_0_30"></A>Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.703ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRRAS_533 (from RCLK_c +)
Destination: Port Pad nRRAS
Data Path Delay: 6.646ns (68.6% logic, 31.4% route), 2 logic levels.
Clock Path Delay: 3.151ns (35.9% logic, 64.1% route), 1 logic levels.
Constraint Details:
3.151ns delay RCLK to SLICE_60 and
6.646ns delay SLICE_60 to nRRAS (totaling 9.797ns) meets
12.500ns offset RCLK to nRRAS by 2.703ns
Physical Path Details:
Clock path RCLK to SLICE_60:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK
ROUTE 52 2.019 63.PADDI to R4C11A.CLK RCLK_c
--------
3.151 (35.9% logic, 64.1% route), 1 logic levels.
Data path SLICE_60 to nRRAS:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R4C11A.CLK to R4C11A.Q0 SLICE_60 (from RCLK_c)
ROUTE 1 2.089 R4C11A.Q0 to 54.PADDO nRRAS_c
DOPAD_DEL --- 4.105 54.PADDO to 54.PAD nRRAS
--------
6.646 (68.6% logic, 31.4% route), 2 logic levels.
Report: 9.797ns is the minimum offset for this preference.
================================================================================
<A name="par_twr_pref_0_31"></A>Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.826ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRCAS_534 (from RCLK_c +)
Destination: Port Pad nRCAS
Data Path Delay: 6.523ns (69.9% logic, 30.1% route), 2 logic levels.
Clock Path Delay: 3.151ns (35.9% logic, 64.1% route), 1 logic levels.
Constraint Details:
3.151ns delay RCLK to SLICE_57 and
6.523ns delay SLICE_57 to nRCAS (totaling 9.674ns) meets
12.500ns offset RCLK to nRCAS by 2.826ns
Physical Path Details:
Clock path RCLK to SLICE_57:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK
ROUTE 52 2.019 63.PADDI to R5C11B.CLK RCLK_c
--------
3.151 (35.9% logic, 64.1% route), 1 logic levels.
Data path SLICE_57 to nRCAS:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R5C11B.CLK to R5C11B.Q0 SLICE_57 (from RCLK_c)
ROUTE 1 1.966 R5C11B.Q0 to 52.PADDO nRCAS_c
DOPAD_DEL --- 4.105 52.PADDO to 52.PAD nRCAS
--------
6.523 (69.9% logic, 30.1% route), 2 logic levels.
Report: 9.674ns is the minimum offset for this preference.
================================================================================
<A name="par_twr_pref_0_32"></A>Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1.559ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_538 (from RCLK_c +)
Destination: Port Pad RDQMH
Data Path Delay: 7.790ns (64.9% logic, 35.1% route), 3 logic levels.
Clock Path Delay: 3.151ns (35.9% logic, 64.1% route), 1 logic levels.
Constraint Details:
3.151ns delay RCLK to SLICE_63 and
7.790ns delay SLICE_63 to RDQMH (totaling 10.941ns) meets
12.500ns offset RCLK to RDQMH by 1.559ns
Physical Path Details:
Clock path RCLK to SLICE_63:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK
ROUTE 52 2.019 63.PADDI to R5C10A.CLK RCLK_c
--------
3.151 (35.9% logic, 64.1% route), 1 logic levels.
Data path SLICE_63 to RDQMH:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c)
ROUTE 12 0.648 R5C10A.Q0 to R5C9B.D1 nRowColSel
CTOF_DEL --- 0.495 R5C9B.D1 to R5C9B.F1 SLICE_151
ROUTE 1 2.090 R5C9B.F1 to 51.PADDO RDQMH_c
DOPAD_DEL --- 4.105 51.PADDO to 51.PAD RDQMH
--------
7.790 (64.9% logic, 35.1% route), 3 logic levels.
Report: 10.941ns is the minimum offset for this preference.
================================================================================
<A name="par_twr_pref_0_33"></A>Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1.859ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_538 (from RCLK_c +)
Destination: Port Pad RDQML
Data Path Delay: 7.490ns (67.4% logic, 32.6% route), 3 logic levels.
Clock Path Delay: 3.151ns (35.9% logic, 64.1% route), 1 logic levels.
Constraint Details:
3.151ns delay RCLK to SLICE_63 and
7.490ns delay SLICE_63 to RDQML (totaling 10.641ns) meets
12.500ns offset RCLK to RDQML by 1.859ns
Physical Path Details:
Clock path RCLK to SLICE_63:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK
ROUTE 52 2.019 63.PADDI to R5C10A.CLK RCLK_c
--------
3.151 (35.9% logic, 64.1% route), 1 logic levels.
Data path SLICE_63 to RDQML:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c)
ROUTE 12 0.796 R5C10A.Q0 to R5C9C.C1 nRowColSel
CTOF_DEL --- 0.495 R5C9C.C1 to R5C9C.F1 SLICE_161
ROUTE 1 1.642 R5C9C.F1 to 48.PADDO RDQML_c
DOPAD_DEL --- 4.105 48.PADDO to 48.PAD RDQML
--------
7.490 (67.4% logic, 32.6% route), 3 logic levels.
Report: 10.641ns is the minimum offset for this preference.
================================================================================
<A name="par_twr_pref_0_34"></A>Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_35"></A>Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_36"></A>Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_37"></A>Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_38"></A>Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_39"></A>Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_40"></A>Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
<A name="ptwr_set_rs"></A><B><U><big>Report Summary</big></U></B>
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
PERIOD NET "PHI2_c" 350.000000 ns ; | 350.000 ns| 25.800 ns| 8
| | |
PERIOD NET "nCCAS_c" 350.000000 ns ; | 350.000 ns| 2.500 ns| 0
| | |
PERIOD NET "nCRAS_c" 350.000000 ns ; | 350.000 ns| 2.500 ns| 0
| | |
PERIOD NET "RCLK_c" 16.000000 ns ; | 16.000 ns| 12.427 ns| 9
| | |
CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[0]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[7]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[6]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[5]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[4]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[3]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[2]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[1]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 9.485 ns| 2
| | |
CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 11.005 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 11.114 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 10.948 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 11.099 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 11.365 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 11.365 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 11.178 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 10.923 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 10.921 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 10.645 ns| 3
| | |
CLOCK_TO_OUT PORT "nRCS" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 9.674 ns| 2
| | |
CLOCK_TO_OUT PORT "RCKE" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 9.884 ns| 2
| | |
CLOCK_TO_OUT PORT "nRWE" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 9.275 ns| 2
| | |
CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 9.797 ns| 2
| | |
CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 9.674 ns| 2
| | |
CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 10.941 ns| 3
| | |
CLOCK_TO_OUT PORT "RDQML" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 10.641 ns| 3
| | |
CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
----------------------------------------------------------------------------
All preferences were met.
<A name="ptwr_set_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
------------------------
Found 5 clocks:
Clock Domain: wb_clk Source: SLICE_73.Q0 Loads: 1
No transfer within this clock domain is found
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9
No transfer within this clock domain is found
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6
No transfer within this clock domain is found
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 52
Covered under: PERIOD NET "RCLK_c" 16.000000 ns ;
Data transfers from:
Clock Domain: wb_clk Source: SLICE_73.Q0
Covered under: PERIOD NET "RCLK_c" 16.000000 ns ; Transfers: 2
Clock Domain: nCRAS_c Source: nCRAS.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14
Covered under: PERIOD NET "PHI2_c" 350.000000 ns ;
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
<A name="ptwr_set_ts"></A><B><U><big>Timing summary (Setup):</big></U></B>
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 1548 paths, 9 nets, and 900 connections (79.58% coverage)
--------------------------------------------------------------------------------
<A name="Par_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2</big></U></B>
Sat Oct 09 01:19:24 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
<A name="ptwr_hold_ri"></A><B><U><big>Report Information</big></U></B>
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
Design file: ram2gs_lcmxo2_640hc_impl1.ncd
Preference file: ram2gs_lcmxo2_640hc_impl1.prf
Device,speed: LCMXO2-640HC,m
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
<A name="ptwr_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
<LI><A href='#par_twr_pref_1_0' Target='right'>PERIOD NET "PHI2_c" 350.000000 ns (0 errors)</A></LI> 121 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_1' Target='right'>PERIOD NET "nCCAS_c" 350.000000 ns (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_2' Target='right'>PERIOD NET "nCRAS_c" 350.000000 ns (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_3' Target='right'>PERIOD NET "RCLK_c" 16.000000 ns (0 errors)</A></LI> 1409 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_4' Target='right'>CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_5' Target='right'>CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_6' Target='right'>CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_7' Target='right'>CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_8' Target='right'>CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_9' Target='right'>CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_10' Target='right'>CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_11' Target='right'>CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_12' Target='right'>CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_13' Target='right'>CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_14' Target='right'>CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_15' Target='right'>CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_16' Target='right'>CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_17' Target='right'>CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_18' Target='right'>CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_19' Target='right'>CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_20' Target='right'>CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_21' Target='right'>CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_22' Target='right'>CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_23' Target='right'>CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_24' Target='right'>CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_25' Target='right'>CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_26' Target='right'>CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_27' Target='right'>CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_28' Target='right'>CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_29' Target='right'>CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_30' Target='right'>CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_31' Target='right'>CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_32' Target='right'>CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_33' Target='right'>CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_34' Target='right'>CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_35' Target='right'>CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_36' Target='right'>CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_37' Target='right'>CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_38' Target='right'>CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_39' Target='right'>CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_40' Target='right'>CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
Derating parameters
-------------------
Voltage: 3.300 V
VCCIO Voltage:
3.135 V (Bank 0)
3.135 V (Bank 1)
3.135 V (Bank 2)
3.135 V (Bank 3)
2.375 V (Bank 4)
2.375 V (Bank 5)
2.375 V (Bank 6)
2.375 V (Bank 7)
================================================================================
<A name="par_twr_pref_1_0"></A>Preference: PERIOD NET "PHI2_c" 350.000000 ns ;
121 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q C1Submitted_542 (from PHI2_c -)
Destination: FF Data in C1Submitted_542 (to PHI2_c -)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_15 to SLICE_15 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_15 to SLICE_15:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R3C9C.CLK to R3C9C.Q0 SLICE_15 (from PHI2_c)
ROUTE 2 0.132 R3C9C.Q0 to R3C9C.A0 C1Submitted
CTOF_DEL --- 0.101 R3C9C.A0 to R3C9C.F0 SLICE_15
ROUTE 1 0.000 R3C9C.F0 to R3C9C.DI0 n2549 (to PHI2_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_15:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.240 8.PADDI to R3C9C.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_15:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.240 8.PADDI to R3C9C.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.474ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable_541 (from PHI2_c -)
Destination: FF Data in CmdSubmitted_549 (to PHI2_c -)
Delay: 0.461ns (50.8% logic, 49.2% route), 2 logic levels.
Constraint Details:
0.461ns physical path delay SLICE_19 to SLICE_21 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.474ns
Physical Path Details:
Data path SLICE_19 to SLICE_21:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R3C9A.CLK to R3C9A.Q0 SLICE_19 (from PHI2_c)
ROUTE 1 0.224 R3C9A.Q0 to R4C9B.B0 CmdEnable
CTOF_DEL --- 0.101 R4C9B.B0 to R4C9B.F0 SLICE_21
ROUTE 4 0.003 R4C9B.F0 to R4C9B.DI0 XOR8MEG_N_149 (to PHI2_c)
--------
0.461 (50.8% logic, 49.2% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.240 8.PADDI to R3C9A.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_21:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.240 8.PADDI to R4C9B.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.538ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ADSubmitted_543 (from PHI2_c -)
Destination: FF Data in CmdEnable_541 (to PHI2_c -)
Delay: 0.510ns (45.9% logic, 54.1% route), 2 logic levels.
Constraint Details:
0.510ns physical path delay SLICE_10 to SLICE_19 meets
-0.028ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.028ns) by 0.538ns
Physical Path Details:
Data path SLICE_10 to SLICE_19:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R3C9B.CLK to R3C9B.Q0 SLICE_10 (from PHI2_c)
ROUTE 1 0.133 R3C9B.Q0 to R3C9D.D0 ADSubmitted
CTOF_DEL --- 0.101 R3C9D.D0 to R3C9D.F0 SLICE_130
ROUTE 1 0.143 R3C9D.F0 to R3C9A.CE PHI2_N_151_enable_1 (to PHI2_c)
--------
0.510 (45.9% logic, 54.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_10:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.240 8.PADDI to R3C9B.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.240 8.PADDI to R3C9A.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.860ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q C1Submitted_542 (from PHI2_c -)
Destination: FF Data in CmdEnable_541 (to PHI2_c -)
Delay: 0.832ns (40.3% logic, 59.7% route), 3 logic levels.
Constraint Details:
0.832ns physical path delay SLICE_15 to SLICE_19 meets
-0.028ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.028ns) by 0.860ns
Physical Path Details:
Data path SLICE_15 to SLICE_19:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R3C9C.CLK to R3C9C.Q0 SLICE_15 (from PHI2_c)
ROUTE 2 0.224 R3C9C.Q0 to R3C9C.B1 C1Submitted
CTOF_DEL --- 0.101 R3C9C.B1 to R3C9C.F1 SLICE_15
ROUTE 1 0.130 R3C9C.F1 to R3C9D.A0 n7
CTOF_DEL --- 0.101 R3C9D.A0 to R3C9D.F0 SLICE_130
ROUTE 1 0.143 R3C9D.F0 to R3C9A.CE PHI2_N_151_enable_1 (to PHI2_c)
--------
0.832 (40.3% logic, 59.7% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_15:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.240 8.PADDI to R3C9C.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.240 8.PADDI to R3C9A.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.873ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable_541 (from PHI2_c -)
Destination: FF Data in XOR8MEG_544 (to PHI2_c -)
Delay: 0.845ns (39.6% logic, 60.4% route), 3 logic levels.
Constraint Details:
0.845ns physical path delay SLICE_19 to SLICE_145 meets
-0.028ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.028ns) by 0.873ns
Physical Path Details:
Data path SLICE_19 to SLICE_145:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R3C9A.CLK to R3C9A.Q0 SLICE_19 (from PHI2_c)
ROUTE 1 0.224 R3C9A.Q0 to R4C9B.B0 CmdEnable
CTOF_DEL --- 0.101 R4C9B.B0 to R4C9B.F0 SLICE_21
ROUTE 4 0.141 R4C9B.F0 to R5C9A.D1 XOR8MEG_N_149
CTOF_DEL --- 0.101 R5C9A.D1 to R5C9A.F1 SLICE_110
ROUTE 1 0.145 R5C9A.F1 to R5C8A.CE PHI2_N_151_enable_6 (to PHI2_c)
--------
0.845 (39.6% logic, 60.4% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.240 8.PADDI to R3C9A.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_145:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.240 8.PADDI to R5C8A.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.009ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable_541 (from PHI2_c -)
Destination: FF Data in CmdUFMShift_547 (to PHI2_c -)
FF CmdUFMData_548
Delay: 0.981ns (34.1% logic, 65.9% route), 3 logic levels.
Constraint Details:
0.981ns physical path delay SLICE_19 to SLICE_161 meets
-0.028ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.028ns) by 1.009ns
Physical Path Details:
Data path SLICE_19 to SLICE_161:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R3C9A.CLK to R3C9A.Q0 SLICE_19 (from PHI2_c)
ROUTE 1 0.224 R3C9A.Q0 to R4C9B.B0 CmdEnable
CTOF_DEL --- 0.101 R4C9B.B0 to R4C9B.F0 SLICE_21
ROUTE 4 0.059 R4C9B.F0 to R4C9B.C1 XOR8MEG_N_149
CTOF_DEL --- 0.101 R4C9B.C1 to R4C9B.F1 SLICE_21
ROUTE 1 0.363 R4C9B.F1 to R5C9C.CE PHI2_N_151_enable_3 (to PHI2_c)
--------
0.981 (34.1% logic, 65.9% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.240 8.PADDI to R3C9A.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_161:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.240 8.PADDI to R5C9C.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.341ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable_541 (from PHI2_c -)
Destination: FF Data in CmdLEDEN_545 (to PHI2_c -)
Delay: 1.313ns (33.2% logic, 66.8% route), 4 logic levels.
Constraint Details:
1.313ns physical path delay SLICE_19 to SLICE_20 meets
-0.028ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.028ns) by 1.341ns
Physical Path Details:
Data path SLICE_19 to SLICE_20:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R3C9A.CLK to R3C9A.Q0 SLICE_19 (from PHI2_c)
ROUTE 1 0.224 R3C9A.Q0 to R4C9B.B0 CmdEnable
CTOF_DEL --- 0.101 R4C9B.B0 to R4C9B.F0 SLICE_21
ROUTE 4 0.335 R4C9B.F0 to R5C8D.B0 XOR8MEG_N_149
CTOF_DEL --- 0.101 R5C8D.B0 to R5C8D.F0 SLICE_112
ROUTE 1 0.056 R5C8D.F0 to R5C8D.C1 n4882
CTOF_DEL --- 0.101 R5C8D.C1 to R5C8D.F1 SLICE_112
ROUTE 2 0.262 R5C8D.F1 to R5C6A.CE PHI2_N_151_enable_5 (to PHI2_c)
--------
1.313 (33.2% logic, 66.8% route), 4 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.240 8.PADDI to R3C9A.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.240 8.PADDI to R5C6A.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.341ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable_541 (from PHI2_c -)
Destination: FF Data in Cmdn8MEGEN_546 (to PHI2_c -)
Delay: 1.313ns (33.2% logic, 66.8% route), 4 logic levels.
Constraint Details:
1.313ns physical path delay SLICE_19 to SLICE_24 meets
-0.028ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.028ns) by 1.341ns
Physical Path Details:
Data path SLICE_19 to SLICE_24:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R3C9A.CLK to R3C9A.Q0 SLICE_19 (from PHI2_c)
ROUTE 1 0.224 R3C9A.Q0 to R4C9B.B0 CmdEnable
CTOF_DEL --- 0.101 R4C9B.B0 to R4C9B.F0 SLICE_21
ROUTE 4 0.335 R4C9B.F0 to R5C8D.B0 XOR8MEG_N_149
CTOF_DEL --- 0.101 R5C8D.B0 to R5C8D.F0 SLICE_112
ROUTE 1 0.056 R5C8D.F0 to R5C8D.C1 n4882
CTOF_DEL --- 0.101 R5C8D.C1 to R5C8D.F1 SLICE_112
ROUTE 2 0.262 R5C8D.F1 to R5C6B.CE PHI2_N_151_enable_5 (to PHI2_c)
--------
1.313 (33.2% logic, 66.8% route), 4 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.240 8.PADDI to R3C9A.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_24:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.240 8.PADDI to R5C6B.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 175.457ns (weighted slack = 350.914ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q XOR8MEG_544 (from PHI2_c -)
Destination: FF Data in RA11_521 (to PHI2_c +)
Delay: 0.444ns (52.7% logic, 47.3% route), 2 logic levels.
Constraint Details:
0.444ns physical path delay SLICE_145 to SLICE_32 meets
-0.013ns DIN_HLD and
-175.000ns delay constraint less
0.000ns skew requirement (totaling -175.013ns) by 175.457ns
Physical Path Details:
Data path SLICE_145 to SLICE_32:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C8A.CLK to R5C8A.Q0 SLICE_145 (from PHI2_c)
ROUTE 1 0.210 R5C8A.Q0 to R5C8C.A0 XOR8MEG
CTOF_DEL --- 0.101 R5C8C.A0 to R5C8C.F0 SLICE_32
ROUTE 1 0.000 R5C8C.F0 to R5C8C.DI0 RA11_N_217 (to PHI2_c)
--------
0.444 (52.7% logic, 47.3% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_145:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.240 8.PADDI to R5C8A.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_32:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.240 8.PADDI to R5C8C.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 175.815ns (weighted slack = 351.630ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_i2 (from PHI2_c +)
Destination: FF Data in ADSubmitted_543 (to PHI2_c -)
Delay: 0.787ns (42.6% logic, 57.4% route), 3 logic levels.
Constraint Details:
0.787ns physical path delay SLICE_143 to SLICE_10 meets
-0.028ns CE_HLD and
-175.000ns delay constraint less
0.000ns skew requirement (totaling -175.028ns) by 175.815ns
Physical Path Details:
Data path SLICE_143 to SLICE_10:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R2C8D.CLK to R2C8D.Q0 SLICE_143 (from PHI2_c)
ROUTE 2 0.139 R2C8D.Q0 to R2C9C.C1 Bank_2
CTOF_DEL --- 0.101 R2C9C.C1 to R2C9C.F1 SLICE_132
ROUTE 1 0.056 R2C9C.F1 to R2C9C.C0 n4782
CTOF_DEL --- 0.101 R2C9C.C0 to R2C9C.F0 SLICE_132
ROUTE 1 0.257 R2C9C.F0 to R3C9B.CE PHI2_N_151_enable_7 (to PHI2_c)
--------
0.787 (42.6% logic, 57.4% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_143:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.240 8.PADDI to R2C8D.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_10:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.240 8.PADDI to R3C9B.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
================================================================================
<A name="par_twr_pref_1_1"></A>Preference: PERIOD NET "nCCAS_c" 350.000000 ns ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_2"></A>Preference: PERIOD NET "nCRAS_c" 350.000000 ns ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_3"></A>Preference: PERIOD NET "RCLK_c" 16.000000 ns ;
1409 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS_FSM__i2 (from RCLK_c +)
Destination: FF Data in IS_FSM__i3 (to RCLK_c +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay SLICE_118 to SLICE_118 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path SLICE_118 to SLICE_118:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C9C.CLK to R4C9C.Q0 SLICE_118 (from RCLK_c)
ROUTE 1 0.152 R4C9C.Q0 to R4C9C.M1 n1197 (to RCLK_c)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_118:
Name Fanout Delay (ns) Site Resource
ROUTE 52 0.651 63.PADDI to R4C9C.CLK RCLK_c
--------
0.651 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_118:
Name Fanout Delay (ns) Site Resource
ROUTE 52 0.651 63.PADDI to R4C9C.CLK RCLK_c
--------
0.651 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS_FSM__i4 (from RCLK_c +)
Destination: FF Data in IS_FSM__i5 (to RCLK_c +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay SLICE_127 to SLICE_127 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path SLICE_127 to SLICE_127:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C10B.CLK to R4C10B.Q0 SLICE_127 (from RCLK_c)
ROUTE 1 0.152 R4C10B.Q0 to R4C10B.M1 n1195 (to RCLK_c)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_127:
Name Fanout Delay (ns) Site Resource
ROUTE 52 0.651 63.PADDI to R4C10B.CLK RCLK_c
--------
0.651 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_127:
Name Fanout Delay (ns) Site Resource
ROUTE 52 0.651 63.PADDI to R4C10B.CLK RCLK_c
--------
0.651 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CASr_518 (from RCLK_c +)
Destination: FF Data in CASr2_519 (to RCLK_c +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay SLICE_16 to SLICE_16 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path SLICE_16 to SLICE_16:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R6C10C.CLK to R6C10C.Q0 SLICE_16 (from RCLK_c)
ROUTE 1 0.152 R6C10C.Q0 to R6C10C.M1 CASr (to RCLK_c)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_16:
Name Fanout Delay (ns) Site Resource
ROUTE 52 0.651 63.PADDI to R6C10C.CLK RCLK_c
--------
0.651 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_16:
Name Fanout Delay (ns) Site Resource
ROUTE 52 0.651 63.PADDI to R6C10C.CLK RCLK_c
--------
0.651 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS_FSM__i10 (from RCLK_c +)
Destination: FF Data in IS_FSM__i11 (to RCLK_c +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay SLICE_163 to SLICE_163 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path SLICE_163 to SLICE_163:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C10D.CLK to R4C10D.Q0 SLICE_163 (from RCLK_c)
ROUTE 1 0.152 R4C10D.Q0 to R4C10D.M1 n1189 (to RCLK_c)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_163:
Name Fanout Delay (ns) Site Resource
ROUTE 52 0.651 63.PADDI to R4C10D.CLK RCLK_c
--------
0.651 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_163:
Name Fanout Delay (ns) Site Resource
ROUTE 52 0.651 63.PADDI to R4C10D.CLK RCLK_c
--------
0.651 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS_FSM__i14 (from RCLK_c +)
Destination: FF Data in IS_FSM__i15 (to RCLK_c +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay SLICE_91 to SLICE_91 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path SLICE_91 to SLICE_91:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C8D.CLK to R4C8D.Q0 SLICE_91 (from RCLK_c)
ROUTE 1 0.152 R4C8D.Q0 to R4C8D.M1 n1185 (to RCLK_c)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_91:
Name Fanout Delay (ns) Site Resource
ROUTE 52 0.651 63.PADDI to R4C8D.CLK RCLK_c
--------
0.651 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_91:
Name Fanout Delay (ns) Site Resource
ROUTE 52 0.651 63.PADDI to R4C8D.CLK RCLK_c
--------
0.651 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS_FSM__i12 (from RCLK_c +)
Destination: FF Data in IS_FSM__i13 (to RCLK_c +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay SLICE_94 to SLICE_94 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path SLICE_94 to SLICE_94:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C7D.CLK to R4C7D.Q0 SLICE_94 (from RCLK_c)
ROUTE 1 0.152 R4C7D.Q0 to R4C7D.M1 n1187 (to RCLK_c)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_94:
Name Fanout Delay (ns) Site Resource
ROUTE 52 0.651 63.PADDI to R4C7D.CLK RCLK_c
--------
0.651 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_94:
Name Fanout Delay (ns) Site Resource
ROUTE 52 0.651 63.PADDI to R4C7D.CLK RCLK_c
--------
0.651 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q PHI2r_512 (from RCLK_c +)
Destination: FF Data in PHI2r2_513 (to RCLK_c +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay SLICE_95 to SLICE_35 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path SLICE_95 to SLICE_35:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C7A.CLK to R4C7A.Q0 SLICE_95 (from RCLK_c)
ROUTE 1 0.152 R4C7A.Q0 to R4C7B.M1 PHI2r (to RCLK_c)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_95:
Name Fanout Delay (ns) Site Resource
ROUTE 52 0.651 63.PADDI to R4C7A.CLK RCLK_c
--------
0.651 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_35:
Name Fanout Delay (ns) Site Resource
ROUTE 52 0.651 63.PADDI to R4C7B.CLK RCLK_c
--------
0.651 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.306ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RASr_515 (from RCLK_c +)
Destination: FF Data in RASr2_516 (to RCLK_c +)
Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels.
Constraint Details:
0.287ns physical path delay SLICE_30 to SLICE_30 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.306ns
Physical Path Details:
Data path SLICE_30 to SLICE_30:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C7A.CLK to R5C7A.Q0 SLICE_30 (from RCLK_c)
ROUTE 2 0.154 R5C7A.Q0 to R5C7A.M1 RASr (to RCLK_c)
--------
0.287 (46.3% logic, 53.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_30:
Name Fanout Delay (ns) Site Resource
ROUTE 52 0.651 63.PADDI to R5C7A.CLK RCLK_c
--------
0.651 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_30:
Name Fanout Delay (ns) Site Resource
ROUTE 52 0.651 63.PADDI to R5C7A.CLK RCLK_c
--------
0.651 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.307ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS_FSM__i0 (from RCLK_c +)
Destination: FF Data in IS_FSM__i1 (to RCLK_c +)
Delay: 0.288ns (46.2% logic, 53.8% route), 1 logic levels.
Constraint Details:
0.288ns physical path delay SLICE_162 to SLICE_162 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.307ns
Physical Path Details:
Data path SLICE_162 to SLICE_162:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R3C10C.CLK to R3C10C.Q0 SLICE_162 (from RCLK_c)
ROUTE 4 0.155 R3C10C.Q0 to R3C10C.M1 nRCS_N_172 (to RCLK_c)
--------
0.288 (46.2% logic, 53.8% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_162:
Name Fanout Delay (ns) Site Resource
ROUTE 52 0.651 63.PADDI to R3C10C.CLK RCLK_c
--------
0.651 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_162:
Name Fanout Delay (ns) Site Resource
ROUTE 52 0.651 63.PADDI to R3C10C.CLK RCLK_c
--------
0.651 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS_972__i2 (from RCLK_c +)
Destination: FF Data in FS_972__i2 (to RCLK_c +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_0 to SLICE_0 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_0 to SLICE_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R6C6B.CLK to R6C6B.Q1 SLICE_0 (from RCLK_c)
ROUTE 3 0.132 R6C6B.Q1 to R6C6B.A1 FS_2
CTOF_DEL --- 0.101 R6C6B.A1 to R6C6B.F1 SLICE_0
ROUTE 1 0.000 R6C6B.F1 to R6C6B.DI1 n93 (to RCLK_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_0:
Name Fanout Delay (ns) Site Resource
ROUTE 52 0.651 63.PADDI to R6C6B.CLK RCLK_c
--------
0.651 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_0:
Name Fanout Delay (ns) Site Resource
ROUTE 52 0.651 63.PADDI to R6C6B.CLK RCLK_c
--------
0.651 (0.0% logic, 100.0% route), 0 logic levels.
================================================================================
<A name="par_twr_pref_1_4"></A>Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_5"></A>Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_6"></A>Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_7"></A>Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_8"></A>Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_9"></A>Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_10"></A>Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_11"></A>Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_12"></A>Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_13"></A>Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_14"></A>Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_15"></A>Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_16"></A>Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.236ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RA10_536 (from RCLK_c +)
Destination: Port Pad RA[10]
Data Path Delay: 2.217ns (81.5% logic, 18.5% route), 2 logic levels.
Clock Path Delay: 1.019ns (44.0% logic, 56.0% route), 1 logic levels.
Constraint Details:
1.019ns delay RCLK to SLICE_54 and
2.217ns delay SLICE_54 to RA[10] (totaling 3.236ns) meets
0.000ns hold offset RCLK to RA[10] by 3.236ns
Physical Path Details:
Clock path RCLK to SLICE_54:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK
ROUTE 52 0.571 63.PADDI to R4C11D.CLK RCLK_c
--------
1.019 (44.0% logic, 56.0% route), 1 logic levels.
Data path SLICE_54 to RA[10]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C11D.CLK to R4C11D.Q0 SLICE_54 (from RCLK_c)
ROUTE 1 0.411 R4C11D.Q0 to 64.PADDO n1975
DOPAD_DEL --- 1.673 64.PADDO to 64.PAD RA[10]
--------
2.217 (81.5% logic, 18.5% route), 2 logic levels.
Report: 3.236ns is the maximum offset for this preference.
================================================================================
<A name="par_twr_pref_1_17"></A>Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.561ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_538 (from RCLK_c +)
Destination: Port Pad RA[9]
Data Path Delay: 2.542ns (75.0% logic, 25.0% route), 3 logic levels.
Clock Path Delay: 1.019ns (44.0% logic, 56.0% route), 1 logic levels.
Constraint Details:
1.019ns delay RCLK to SLICE_63 and
2.542ns delay SLICE_63 to RA[9] (totaling 3.561ns) meets
0.000ns hold offset RCLK to RA[9] by 3.561ns
Physical Path Details:
Clock path RCLK to SLICE_63:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK
ROUTE 52 0.571 63.PADDI to R5C10A.CLK RCLK_c
--------
1.019 (44.0% logic, 56.0% route), 1 logic levels.
Data path SLICE_63 to RA[9]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c)
ROUTE 12 0.219 R5C10A.Q0 to R5C9B.A0 nRowColSel
CTOF_DEL --- 0.101 R5C9B.A0 to R5C9B.F0 SLICE_151
ROUTE 1 0.416 R5C9B.F0 to 62.PADDO RA_c_9
DOPAD_DEL --- 1.673 62.PADDO to 62.PAD RA[9]
--------
2.542 (75.0% logic, 25.0% route), 3 logic levels.
Report: 3.561ns is the maximum offset for this preference.
================================================================================
<A name="par_twr_pref_1_18"></A>Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.608ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_538 (from RCLK_c +)
Destination: Port Pad RA[8]
Data Path Delay: 2.589ns (73.7% logic, 26.3% route), 3 logic levels.
Clock Path Delay: 1.019ns (44.0% logic, 56.0% route), 1 logic levels.
Constraint Details:
1.019ns delay RCLK to SLICE_63 and
2.589ns delay SLICE_63 to RA[8] (totaling 3.608ns) meets
0.000ns hold offset RCLK to RA[8] by 3.608ns
Physical Path Details:
Clock path RCLK to SLICE_63:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK
ROUTE 52 0.571 63.PADDI to R5C10A.CLK RCLK_c
--------
1.019 (44.0% logic, 56.0% route), 1 logic levels.
Data path SLICE_63 to RA[8]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c)
ROUTE 12 0.231 R5C10A.Q0 to R4C10D.B1 nRowColSel
CTOF_DEL --- 0.101 R4C10D.B1 to R4C10D.F1 SLICE_163
ROUTE 1 0.451 R4C10D.F1 to 65.PADDO RA_c_8
DOPAD_DEL --- 1.673 65.PADDO to 65.PAD RA[8]
--------
2.589 (73.7% logic, 26.3% route), 3 logic levels.
Report: 3.608ns is the maximum offset for this preference.
================================================================================
<A name="par_twr_pref_1_19"></A>Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.552ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_538 (from RCLK_c +)
Destination: Port Pad RA[7]
Data Path Delay: 2.533ns (75.3% logic, 24.7% route), 3 logic levels.
Clock Path Delay: 1.019ns (44.0% logic, 56.0% route), 1 logic levels.
Constraint Details:
1.019ns delay RCLK to SLICE_63 and
2.533ns delay SLICE_63 to RA[7] (totaling 3.552ns) meets
0.000ns hold offset RCLK to RA[7] by 3.552ns
Physical Path Details:
Clock path RCLK to SLICE_63:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK
ROUTE 52 0.571 63.PADDI to R5C10A.CLK RCLK_c
--------
1.019 (44.0% logic, 56.0% route), 1 logic levels.
Data path SLICE_63 to RA[7]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c)
ROUTE 12 0.229 R5C10A.Q0 to R2C10D.D1 nRowColSel
CTOF_DEL --- 0.101 R2C10D.D1 to R2C10D.F1 SLICE_155
ROUTE 1 0.397 R2C10D.F1 to 75.PADDO RA_c_7
DOPAD_DEL --- 1.673 75.PADDO to 75.PAD RA[7]
--------
2.533 (75.3% logic, 24.7% route), 3 logic levels.
Report: 3.552ns is the maximum offset for this preference.
================================================================================
<A name="par_twr_pref_1_20"></A>Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.573ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_538 (from RCLK_c +)
Destination: Port Pad RA[6]
Data Path Delay: 2.554ns (74.7% logic, 25.3% route), 3 logic levels.
Clock Path Delay: 1.019ns (44.0% logic, 56.0% route), 1 logic levels.
Constraint Details:
1.019ns delay RCLK to SLICE_63 and
2.554ns delay SLICE_63 to RA[6] (totaling 3.573ns) meets
0.000ns hold offset RCLK to RA[6] by 3.573ns
Physical Path Details:
Clock path RCLK to SLICE_63:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK
ROUTE 52 0.571 63.PADDI to R5C10A.CLK RCLK_c
--------
1.019 (44.0% logic, 56.0% route), 1 logic levels.
Data path SLICE_63 to RA[6]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c)
ROUTE 12 0.231 R5C10A.Q0 to R4C10D.B0 nRowColSel
CTOF_DEL --- 0.101 R4C10D.B0 to R4C10D.F0 SLICE_163
ROUTE 1 0.416 R4C10D.F0 to 68.PADDO RA_c_6
DOPAD_DEL --- 1.673 68.PADDO to 68.PAD RA[6]
--------
2.554 (74.7% logic, 25.3% route), 3 logic levels.
Report: 3.573ns is the maximum offset for this preference.
================================================================================
<A name="par_twr_pref_1_21"></A>Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.630ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_538 (from RCLK_c +)
Destination: Port Pad RA[5]
Data Path Delay: 2.611ns (73.0% logic, 27.0% route), 3 logic levels.
Clock Path Delay: 1.019ns (44.0% logic, 56.0% route), 1 logic levels.
Constraint Details:
1.019ns delay RCLK to SLICE_63 and
2.611ns delay SLICE_63 to RA[5] (totaling 3.630ns) meets
0.000ns hold offset RCLK to RA[5] by 3.630ns
Physical Path Details:
Clock path RCLK to SLICE_63:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK
ROUTE 52 0.571 63.PADDI to R5C10A.CLK RCLK_c
--------
1.019 (44.0% logic, 56.0% route), 1 logic levels.
Data path SLICE_63 to RA[5]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c)
ROUTE 12 0.283 R5C10A.Q0 to R2C9A.C1 nRowColSel
CTOF_DEL --- 0.101 R2C9A.C1 to R2C9A.F1 SLICE_157
ROUTE 1 0.421 R2C9A.F1 to 70.PADDO RA_c_5
DOPAD_DEL --- 1.673 70.PADDO to 70.PAD RA[5]
--------
2.611 (73.0% logic, 27.0% route), 3 logic levels.
Report: 3.630ns is the maximum offset for this preference.
================================================================================
<A name="par_twr_pref_1_22"></A>Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.630ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_538 (from RCLK_c +)
Destination: Port Pad RA[4]
Data Path Delay: 2.611ns (73.0% logic, 27.0% route), 3 logic levels.
Clock Path Delay: 1.019ns (44.0% logic, 56.0% route), 1 logic levels.
Constraint Details:
1.019ns delay RCLK to SLICE_63 and
2.611ns delay SLICE_63 to RA[4] (totaling 3.630ns) meets
0.000ns hold offset RCLK to RA[4] by 3.630ns
Physical Path Details:
Clock path RCLK to SLICE_63:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK
ROUTE 52 0.571 63.PADDI to R5C10A.CLK RCLK_c
--------
1.019 (44.0% logic, 56.0% route), 1 logic levels.
Data path SLICE_63 to RA[4]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c)
ROUTE 12 0.283 R5C10A.Q0 to R2C8B.C1 nRowColSel
CTOF_DEL --- 0.101 R2C8B.C1 to R2C8B.F1 SLICE_158
ROUTE 1 0.421 R2C8B.F1 to 74.PADDO RA_c_4
DOPAD_DEL --- 1.673 74.PADDO to 74.PAD RA[4]
--------
2.611 (73.0% logic, 27.0% route), 3 logic levels.
Report: 3.630ns is the maximum offset for this preference.
================================================================================
<A name="par_twr_pref_1_23"></A>Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.615ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_538 (from RCLK_c +)
Destination: Port Pad RA[3]
Data Path Delay: 2.596ns (73.5% logic, 26.5% route), 3 logic levels.
Clock Path Delay: 1.019ns (44.0% logic, 56.0% route), 1 logic levels.
Constraint Details:
1.019ns delay RCLK to SLICE_63 and
2.596ns delay SLICE_63 to RA[3] (totaling 3.615ns) meets
0.000ns hold offset RCLK to RA[3] by 3.615ns
Physical Path Details:
Clock path RCLK to SLICE_63:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK
ROUTE 52 0.571 63.PADDI to R5C10A.CLK RCLK_c
--------
1.019 (44.0% logic, 56.0% route), 1 logic levels.
Data path SLICE_63 to RA[3]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c)
ROUTE 12 0.226 R5C10A.Q0 to R3C10C.D0 nRowColSel
CTOF_DEL --- 0.101 R3C10C.D0 to R3C10C.F0 SLICE_162
ROUTE 1 0.463 R3C10C.F0 to 71.PADDO RA_c_3
DOPAD_DEL --- 1.673 71.PADDO to 71.PAD RA[3]
--------
2.596 (73.5% logic, 26.5% route), 3 logic levels.
Report: 3.615ns is the maximum offset for this preference.
================================================================================
<A name="par_twr_pref_1_24"></A>Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.527ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_538 (from RCLK_c +)
Destination: Port Pad RA[2]
Data Path Delay: 2.508ns (76.0% logic, 24.0% route), 3 logic levels.
Clock Path Delay: 1.019ns (44.0% logic, 56.0% route), 1 logic levels.
Constraint Details:
1.019ns delay RCLK to SLICE_63 and
2.508ns delay SLICE_63 to RA[2] (totaling 3.527ns) meets
0.000ns hold offset RCLK to RA[2] by 3.527ns
Physical Path Details:
Clock path RCLK to SLICE_63:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK
ROUTE 52 0.571 63.PADDI to R5C10A.CLK RCLK_c
--------
1.019 (44.0% logic, 56.0% route), 1 logic levels.
Data path SLICE_63 to RA[2]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c)
ROUTE 12 0.145 R5C10A.Q0 to R5C9C.C0 nRowColSel
CTOF_DEL --- 0.101 R5C9C.C0 to R5C9C.F0 SLICE_161
ROUTE 1 0.456 R5C9C.F0 to 69.PADDO RA_c_2
DOPAD_DEL --- 1.673 69.PADDO to 69.PAD RA[2]
--------
2.508 (76.0% logic, 24.0% route), 3 logic levels.
Report: 3.527ns is the maximum offset for this preference.
================================================================================
<A name="par_twr_pref_1_25"></A>Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.549ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_538 (from RCLK_c +)
Destination: Port Pad RA[1]
Data Path Delay: 2.530ns (75.4% logic, 24.6% route), 3 logic levels.
Clock Path Delay: 1.019ns (44.0% logic, 56.0% route), 1 logic levels.
Constraint Details:
1.019ns delay RCLK to SLICE_63 and
2.530ns delay SLICE_63 to RA[1] (totaling 3.549ns) meets
0.000ns hold offset RCLK to RA[1] by 3.549ns
Physical Path Details:
Clock path RCLK to SLICE_63:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK
ROUTE 52 0.571 63.PADDI to R5C10A.CLK RCLK_c
--------
1.019 (44.0% logic, 56.0% route), 1 logic levels.
Data path SLICE_63 to RA[1]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c)
ROUTE 12 0.226 R5C10A.Q0 to R3C10C.D1 nRowColSel
CTOF_DEL --- 0.101 R3C10C.D1 to R3C10C.F1 SLICE_162
ROUTE 1 0.397 R3C10C.F1 to 67.PADDO RA_c_1
DOPAD_DEL --- 1.673 67.PADDO to 67.PAD RA[1]
--------
2.530 (75.4% logic, 24.6% route), 3 logic levels.
Report: 3.549ns is the maximum offset for this preference.
================================================================================
<A name="par_twr_pref_1_26"></A>Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.471ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_538 (from RCLK_c +)
Destination: Port Pad RA[0]
Data Path Delay: 2.452ns (77.8% logic, 22.2% route), 3 logic levels.
Clock Path Delay: 1.019ns (44.0% logic, 56.0% route), 1 logic levels.
Constraint Details:
1.019ns delay RCLK to SLICE_63 and
2.452ns delay SLICE_63 to RA[0] (totaling 3.471ns) meets
0.000ns hold offset RCLK to RA[0] by 3.471ns
Physical Path Details:
Clock path RCLK to SLICE_63:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK
ROUTE 52 0.571 63.PADDI to R5C10A.CLK RCLK_c
--------
1.019 (44.0% logic, 56.0% route), 1 logic levels.
Data path SLICE_63 to RA[0]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c)
ROUTE 12 0.229 R5C10A.Q0 to R3C10D.D1 nRowColSel
CTOF_DEL --- 0.101 R3C10D.D1 to R3C10D.F1 SLICE_159
ROUTE 1 0.316 R3C10D.F1 to 66.PADDO RA_c_0
DOPAD_DEL --- 1.673 66.PADDO to 66.PAD RA[0]
--------
2.452 (77.8% logic, 22.2% route), 3 logic levels.
Report: 3.471ns is the maximum offset for this preference.
================================================================================
<A name="par_twr_pref_1_27"></A>Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.300ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRCS_532 (from RCLK_c +)
Destination: Port Pad nRCS
Data Path Delay: 2.281ns (79.2% logic, 20.8% route), 2 logic levels.
Clock Path Delay: 1.019ns (44.0% logic, 56.0% route), 1 logic levels.
Constraint Details:
1.019ns delay RCLK to SLICE_59 and
2.281ns delay SLICE_59 to nRCS (totaling 3.300ns) meets
0.000ns hold offset RCLK to nRCS by 3.300ns
Physical Path Details:
Clock path RCLK to SLICE_59:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK
ROUTE 52 0.571 63.PADDI to R4C11B.CLK RCLK_c
--------
1.019 (44.0% logic, 56.0% route), 1 logic levels.
Data path SLICE_59 to nRCS:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C11B.CLK to R4C11B.Q0 SLICE_59 (from RCLK_c)
ROUTE 1 0.475 R4C11B.Q0 to 57.PADDO nRCS_c
DOPAD_DEL --- 1.673 57.PADDO to 57.PAD nRCS
--------
2.281 (79.2% logic, 20.8% route), 2 logic levels.
Report: 3.300ns is the maximum offset for this preference.
================================================================================
<A name="par_twr_pref_1_28"></A>Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.362ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RCKE_531 (from RCLK_c +)
Destination: Port Pad RCKE
Data Path Delay: 2.343ns (77.1% logic, 22.9% route), 2 logic levels.
Clock Path Delay: 1.019ns (44.0% logic, 56.0% route), 1 logic levels.
Constraint Details:
1.019ns delay RCLK to SLICE_35 and
2.343ns delay SLICE_35 to RCKE (totaling 3.362ns) meets
0.000ns hold offset RCLK to RCKE by 3.362ns
Physical Path Details:
Clock path RCLK to SLICE_35:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK
ROUTE 52 0.571 63.PADDI to R4C7B.CLK RCLK_c
--------
1.019 (44.0% logic, 56.0% route), 1 logic levels.
Data path SLICE_35 to RCKE:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C7B.CLK to R4C7B.Q0 SLICE_35 (from RCLK_c)
ROUTE 4 0.537 R4C7B.Q0 to 53.PADDO RCKE_c
DOPAD_DEL --- 1.673 53.PADDO to 53.PAD RCKE
--------
2.343 (77.1% logic, 22.9% route), 2 logic levels.
Report: 3.362ns is the maximum offset for this preference.
================================================================================
<A name="par_twr_pref_1_29"></A>Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.194ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRWE_535 (from RCLK_c +)
Destination: Port Pad nRWE
Data Path Delay: 2.175ns (83.0% logic, 17.0% route), 2 logic levels.
Clock Path Delay: 1.019ns (44.0% logic, 56.0% route), 1 logic levels.
Constraint Details:
1.019ns delay RCLK to SLICE_62 and
2.175ns delay SLICE_62 to nRWE (totaling 3.194ns) meets
0.000ns hold offset RCLK to nRWE by 3.194ns
Physical Path Details:
Clock path RCLK to SLICE_62:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK
ROUTE 52 0.571 63.PADDI to R5C11A.CLK RCLK_c
--------
1.019 (44.0% logic, 56.0% route), 1 logic levels.
Data path SLICE_62 to nRWE:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C11A.CLK to R5C11A.Q0 SLICE_62 (from RCLK_c)
ROUTE 1 0.369 R5C11A.Q0 to 49.PADDO nRWE_c
DOPAD_DEL --- 1.673 49.PADDO to 49.PAD nRWE
--------
2.175 (83.0% logic, 17.0% route), 2 logic levels.
Report: 3.194ns is the maximum offset for this preference.
================================================================================
<A name="par_twr_pref_1_30"></A>Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.322ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRRAS_533 (from RCLK_c +)
Destination: Port Pad nRRAS
Data Path Delay: 2.303ns (78.4% logic, 21.6% route), 2 logic levels.
Clock Path Delay: 1.019ns (44.0% logic, 56.0% route), 1 logic levels.
Constraint Details:
1.019ns delay RCLK to SLICE_60 and
2.303ns delay SLICE_60 to nRRAS (totaling 3.322ns) meets
0.000ns hold offset RCLK to nRRAS by 3.322ns
Physical Path Details:
Clock path RCLK to SLICE_60:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK
ROUTE 52 0.571 63.PADDI to R4C11A.CLK RCLK_c
--------
1.019 (44.0% logic, 56.0% route), 1 logic levels.
Data path SLICE_60 to nRRAS:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C11A.CLK to R4C11A.Q0 SLICE_60 (from RCLK_c)
ROUTE 1 0.497 R4C11A.Q0 to 54.PADDO nRRAS_c
DOPAD_DEL --- 1.673 54.PADDO to 54.PAD nRRAS
--------
2.303 (78.4% logic, 21.6% route), 2 logic levels.
Report: 3.322ns is the maximum offset for this preference.
================================================================================
<A name="par_twr_pref_1_31"></A>Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.300ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRCAS_534 (from RCLK_c +)
Destination: Port Pad nRCAS
Data Path Delay: 2.281ns (79.2% logic, 20.8% route), 2 logic levels.
Clock Path Delay: 1.019ns (44.0% logic, 56.0% route), 1 logic levels.
Constraint Details:
1.019ns delay RCLK to SLICE_57 and
2.281ns delay SLICE_57 to nRCAS (totaling 3.300ns) meets
0.000ns hold offset RCLK to nRCAS by 3.300ns
Physical Path Details:
Clock path RCLK to SLICE_57:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK
ROUTE 52 0.571 63.PADDI to R5C11B.CLK RCLK_c
--------
1.019 (44.0% logic, 56.0% route), 1 logic levels.
Data path SLICE_57 to nRCAS:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C11B.CLK to R5C11B.Q0 SLICE_57 (from RCLK_c)
ROUTE 1 0.475 R5C11B.Q0 to 52.PADDO nRCAS_c
DOPAD_DEL --- 1.673 52.PADDO to 52.PAD nRCAS
--------
2.281 (79.2% logic, 20.8% route), 2 logic levels.
Report: 3.300ns is the maximum offset for this preference.
================================================================================
<A name="par_twr_pref_1_32"></A>Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.559ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_538 (from RCLK_c +)
Destination: Port Pad RDQMH
Data Path Delay: 2.540ns (75.1% logic, 24.9% route), 3 logic levels.
Clock Path Delay: 1.019ns (44.0% logic, 56.0% route), 1 logic levels.
Constraint Details:
1.019ns delay RCLK to SLICE_63 and
2.540ns delay SLICE_63 to RDQMH (totaling 3.559ns) meets
0.000ns hold offset RCLK to RDQMH by 3.559ns
Physical Path Details:
Clock path RCLK to SLICE_63:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK
ROUTE 52 0.571 63.PADDI to R5C10A.CLK RCLK_c
--------
1.019 (44.0% logic, 56.0% route), 1 logic levels.
Data path SLICE_63 to RDQMH:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c)
ROUTE 12 0.139 R5C10A.Q0 to R5C9B.D1 nRowColSel
CTOF_DEL --- 0.101 R5C9B.D1 to R5C9B.F1 SLICE_151
ROUTE 1 0.494 R5C9B.F1 to 51.PADDO RDQMH_c
DOPAD_DEL --- 1.673 51.PADDO to 51.PAD RDQMH
--------
2.540 (75.1% logic, 24.9% route), 3 logic levels.
Report: 3.559ns is the maximum offset for this preference.
================================================================================
<A name="par_twr_pref_1_33"></A>Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.470ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_538 (from RCLK_c +)
Destination: Port Pad RDQML
Data Path Delay: 2.451ns (77.8% logic, 22.2% route), 3 logic levels.
Clock Path Delay: 1.019ns (44.0% logic, 56.0% route), 1 logic levels.
Constraint Details:
1.019ns delay RCLK to SLICE_63 and
2.451ns delay SLICE_63 to RDQML (totaling 3.470ns) meets
0.000ns hold offset RCLK to RDQML by 3.470ns
Physical Path Details:
Clock path RCLK to SLICE_63:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK
ROUTE 52 0.571 63.PADDI to R5C10A.CLK RCLK_c
--------
1.019 (44.0% logic, 56.0% route), 1 logic levels.
Data path SLICE_63 to RDQML:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c)
ROUTE 12 0.145 R5C10A.Q0 to R5C9C.C1 nRowColSel
CTOF_DEL --- 0.101 R5C9C.C1 to R5C9C.F1 SLICE_161
ROUTE 1 0.399 R5C9C.F1 to 48.PADDO RDQML_c
DOPAD_DEL --- 1.673 48.PADDO to 48.PAD RDQML
--------
2.451 (77.8% logic, 22.2% route), 3 logic levels.
Report: 3.470ns is the maximum offset for this preference.
================================================================================
<A name="par_twr_pref_1_34"></A>Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_35"></A>Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_36"></A>Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_37"></A>Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_38"></A>Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_39"></A>Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_40"></A>Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
<A name="ptwr_hold_rs"></A><B><U><big>Report Summary</big></U></B>
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
PERIOD NET "PHI2_c" 350.000000 ns ; | -| -| 2
| | |
PERIOD NET "nCCAS_c" 350.000000 ns ; | -| -| 0
| | |
PERIOD NET "nCRAS_c" 350.000000 ns ; | -| -| 0
| | |
PERIOD NET "RCLK_c" 16.000000 ns ; | -| -| 1
| | |
CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[0]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[7]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[6]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[5]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[4]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[3]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[2]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[1]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 3.236 ns| 2
| | |
CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 3.561 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 3.608 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 3.552 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 3.573 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 3.630 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 3.630 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 3.615 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 3.527 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 3.549 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 3.471 ns| 3
| | |
CLOCK_TO_OUT PORT "nRCS" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 3.300 ns| 2
| | |
CLOCK_TO_OUT PORT "RCKE" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 3.362 ns| 2
| | |
CLOCK_TO_OUT PORT "nRWE" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 3.194 ns| 2
| | |
CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 3.322 ns| 2
| | |
CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 3.300 ns| 2
| | |
CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 3.559 ns| 3
| | |
CLOCK_TO_OUT PORT "RDQML" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 3.470 ns| 3
| | |
CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
----------------------------------------------------------------------------
All preferences were met.
<A name="ptwr_hold_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
------------------------
Found 5 clocks:
Clock Domain: wb_clk Source: SLICE_73.Q0 Loads: 1
No transfer within this clock domain is found
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9
No transfer within this clock domain is found
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6
No transfer within this clock domain is found
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 52
Covered under: PERIOD NET "RCLK_c" 16.000000 ns ;
Data transfers from:
Clock Domain: wb_clk Source: SLICE_73.Q0
Covered under: PERIOD NET "RCLK_c" 16.000000 ns ; Transfers: 2
Clock Domain: nCRAS_c Source: nCRAS.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14
Covered under: PERIOD NET "PHI2_c" 350.000000 ns ;
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
<A name="ptwr_hold_ts"></A><B><U><big>Timing summary (Hold):</big></U></B>
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 1548 paths, 9 nets, and 900 connections (79.58% coverage)
<A name="ptwr_ts"></A><B><U><big>Timing summary (Setup and Hold):</big></U></B>
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
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