RAM2GS/CPLD/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1_trce.asd
2023-08-15 05:05:47 -04:00

14 lines
295 B
Common Lisp

[ActiveSupport TRCE]
; Setup Analysis
Fmax_0 = 129.769 MHz (283.768 MHz);
Fmax_1 = 54.431 MHz (120.077 MHz);
Failed = 2 (Total 2);
Clock_ports = 4;
Clock_nets = 4;
; Hold Analysis
Fmax_0 = 0.273 ns (0.000 ns);
Fmax_1 = 0.361 ns (0.000 ns);
Failed = 0 (Total 2);
Clock_ports = 4;
Clock_nets = 4;