RAM2GS/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.prf
2023-08-15 05:23:06 -04:00

159 lines
6.4 KiB
Plaintext

SCHEMATIC START ;
# map: version Diamond (64-bit) 3.12.0.240.2 -- WARNING: Map write only section -- Sat Oct 09 01:19:15 2021
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
LOCATE COMP "RCLK" SITE "63" ;
LOCATE COMP "nFWE" SITE "15" ;
LOCATE COMP "nCRAS" SITE "17" ;
LOCATE COMP "nCCAS" SITE "9" ;
LOCATE COMP "Din[0]" SITE "3" ;
LOCATE COMP "Din[1]" SITE "96" ;
LOCATE COMP "Din[2]" SITE "88" ;
LOCATE COMP "Din[3]" SITE "97" ;
LOCATE COMP "Din[4]" SITE "99" ;
LOCATE COMP "Din[5]" SITE "98" ;
LOCATE COMP "Din[6]" SITE "2" ;
LOCATE COMP "Din[7]" SITE "1" ;
LOCATE COMP "CROW[0]" SITE "10" ;
LOCATE COMP "CROW[1]" SITE "16" ;
LOCATE COMP "MAin[0]" SITE "14" ;
LOCATE COMP "MAin[1]" SITE "12" ;
LOCATE COMP "MAin[2]" SITE "13" ;
LOCATE COMP "MAin[3]" SITE "21" ;
LOCATE COMP "MAin[4]" SITE "20" ;
LOCATE COMP "MAin[5]" SITE "19" ;
LOCATE COMP "MAin[6]" SITE "24" ;
LOCATE COMP "MAin[7]" SITE "18" ;
LOCATE COMP "MAin[8]" SITE "25" ;
LOCATE COMP "MAin[9]" SITE "32" ;
LOCATE COMP "PHI2" SITE "8" ;
LOCATE COMP "RDQML" SITE "48" ;
LOCATE COMP "RDQMH" SITE "51" ;
LOCATE COMP "nRCAS" SITE "52" ;
LOCATE COMP "nRRAS" SITE "54" ;
LOCATE COMP "nRWE" SITE "49" ;
LOCATE COMP "RCKE" SITE "53" ;
LOCATE COMP "nRCS" SITE "57" ;
LOCATE COMP "RA[0]" SITE "66" ;
LOCATE COMP "RA[1]" SITE "67" ;
LOCATE COMP "RA[2]" SITE "69" ;
LOCATE COMP "RA[3]" SITE "71" ;
LOCATE COMP "RA[4]" SITE "74" ;
LOCATE COMP "RA[5]" SITE "70" ;
LOCATE COMP "RA[6]" SITE "68" ;
LOCATE COMP "RA[7]" SITE "75" ;
LOCATE COMP "RA[8]" SITE "65" ;
LOCATE COMP "RA[9]" SITE "62" ;
LOCATE COMP "RA[10]" SITE "64" ;
LOCATE COMP "RA[11]" SITE "59" ;
LOCATE COMP "RBA[0]" SITE "58" ;
LOCATE COMP "RBA[1]" SITE "60" ;
LOCATE COMP "LED" SITE "34" ;
LOCATE COMP "Dout[0]" SITE "76" ;
LOCATE COMP "Dout[1]" SITE "86" ;
LOCATE COMP "Dout[2]" SITE "87" ;
LOCATE COMP "Dout[3]" SITE "85" ;
LOCATE COMP "Dout[4]" SITE "83" ;
LOCATE COMP "Dout[5]" SITE "84" ;
LOCATE COMP "Dout[6]" SITE "78" ;
LOCATE COMP "Dout[7]" SITE "82" ;
LOCATE COMP "RD[0]" SITE "36" ;
LOCATE COMP "RD[1]" SITE "37" ;
LOCATE COMP "RD[2]" SITE "38" ;
LOCATE COMP "RD[3]" SITE "39" ;
LOCATE COMP "RD[4]" SITE "40" ;
LOCATE COMP "RD[5]" SITE "41" ;
LOCATE COMP "RD[6]" SITE "42" ;
LOCATE COMP "RD[7]" SITE "43" ;
PERIOD NET "PHI2_c" 350.000000 ns ;
USE PRIMARY NET "RCLK_c" ;
PERIOD NET "nCCAS_c" 350.000000 ns ;
USE PRIMARY NET "PHI2_c" ;
PERIOD NET "nCRAS_c" 350.000000 ns ;
USE PRIMARY NET "nCRAS_c" ;
PERIOD NET "RCLK_c" 16.000000 ns ;
USE PRIMARY NET "nCCAS_c" ;
SCHEMATIC END ;
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
OUTPUT PORT "RD[7]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[0]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[1]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[2]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[3]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[4]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[5]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[6]" LOAD 20.000000 pF ;
OUTPUT PORT "nRWE" LOAD 10.000000 pF ;
OUTPUT PORT "nRCAS" LOAD 10.000000 pF ;
OUTPUT PORT "nRCS" LOAD 10.000000 pF ;
OUTPUT PORT "nRRAS" LOAD 10.000000 pF ;
OUTPUT PORT "RDQML" LOAD 10.000000 pF ;
OUTPUT PORT "RDQMH" LOAD 10.000000 pF ;
OUTPUT PORT "RCKE" LOAD 10.000000 pF ;
OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ;
OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[11]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[10]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[9]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[8]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[7]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[6]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[5]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[4]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[3]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[2]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[1]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[0]" LOAD 10.000000 pF ;
OUTPUT PORT "LED" LOAD 25.000000 pF ;
OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ;
VOLTAGE 3.300 V;
VCCIO_DERATE BANK 0 PERCENT -5;
VCCIO_DERATE PERCENT -5;
VCCIO_DERATE BANK 1 PERCENT -5;
CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
COMMERCIAL ;