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RAM2GS/CPLD/LCMXO2-640HC/impl1/automake.log
Zane Kaminski 8cbf2f47ad RC?
2023-08-16 05:11:25 -04:00

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map -a "MachXO2" -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial -ioreg b "RAM2GS_LCMXO2_640HC_impl1.ngd" -o "RAM2GS_LCMXO2_640HC_impl1_map.ncd" -pr "RAM2GS_LCMXO2_640HC_impl1.prf" -mp "RAM2GS_LCMXO2_640HC_impl1.mrp" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_synplify.lpf" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf" -c 0
map: version Diamond (64-bit) 3.12.1.454
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Process the file: RAM2GS_LCMXO2_640HC_impl1.ngd
Picdevice="LCMXO2-640HC"
Pictype="TQFP100"
Picspeed=4
Remove unused logic
Do not produce over sized NCDs.
Part used: LCMXO2-640HCTQFP100, Performance used: 4.
Loading device for application map from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.39.
Running general design DRC...
Removing unused logic...
Optimizing...
1 CCU2 constant inputs absorbed.
<postMsg mid="51001257" type="Warning" dynamic="3" navigation="0" arg0="Output" arg1="UFMSDI$r0" arg2="UFMSDI_pad" />
<postMsg mid="51001257" type="Warning" dynamic="3" navigation="0" arg0="Output" arg1="nUFMCS$r1" arg2="nUFMCS_pad" />
<postMsg mid="51001257" type="Warning" dynamic="3" navigation="0" arg0="Output" arg1="RCKE$r2" arg2="RCKE_pad" />
<postMsg mid="51001050" type="Warning" dynamic="1" navigation="0" arg0="Bank_0io[0]" />
<postMsg mid="51001050" type="Warning" dynamic="1" navigation="0" arg0="Bank_0io[1]" />
<postMsg mid="51001050" type="Warning" dynamic="1" navigation="0" arg0="Bank_0io[2]" />
Design Summary:
Number of registers: 93 out of 877 (11%)
PFU registers: 64 out of 640 (10%)
PIO registers: 29 out of 237 (12%)
Number of SLICEs: 81 out of 320 (25%)
SLICEs as Logic/ROM: 81 out of 320 (25%)
SLICEs as RAM: 0 out of 240 (0%)
SLICEs as Carry: 10 out of 320 (3%)
Number of LUT4s: 159 out of 640 (25%)
Number used as logic LUTs: 139
Number used as distributed RAM: 0
Number used as ripple logic: 20
Number used as shift registers: 0
Number of PIO sites used: 67 + 4(JTAG) out of 79 (90%)
Number of block RAMs: 0 out of 2 (0%)
Number of GSRs: 0 out of 1 (0%)
EFB used : No
JTAG used : No
Readback used : No
Oscillator used : No
Startup used : No
POR : On
Bandgap : On
Number of Power Controller: 0 out of 1 (0%)
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
Number of DCCA: 0 out of 8 (0%)
Number of DCMA: 0 out of 2 (0%)
Notes:-
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic)
2. Number of logic LUT4s does not include count of distributed RAM and ripple logic.
Number of clocks: 4
Net PHI2_c: 18 loads, 8 rising, 10 falling (Driver: PIO PHI2 )
Net RCLK_c: 39 loads, 39 rising, 0 falling (Driver: PIO RCLK )
Net nCRAS_c: 9 loads, 0 rising, 9 falling (Driver: PIO nCRAS )
Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS )
Number of Clock Enables: 6
Net XOR8MEG18: 3 loads, 3 LSLICEs
Net i2_i: 1 loads, 0 LSLICEs
Net N_26: 1 loads, 1 LSLICEs
Net N_28: 1 loads, 1 LSLICEs
Net N_188_i: 2 loads, 2 LSLICEs
Net CmdUFMCLK_1_sqmuxa: 3 loads, 0 LSLICEs
Number of LSRs: 3
Net RA10s_i: 1 loads, 0 LSLICEs
Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs
Net RASr2: 2 loads, 2 LSLICEs
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
Net InitReady: 17 loads
Net Ready: 15 loads
Net Ready_fast: 14 loads
Net Din_c[5]: 12 loads
Net nRowColSel: 12 loads
Net S[1]: 12 loads
Net RASr2: 10 loads
Net CO0: 9 loads
Net Din_c[3]: 9 loads
Net Din_c[4]: 9 loads
Number of warnings: 6
Number of errors: 0
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 36 MB
Dumping design to file RAM2GS_LCMXO2_640HC_impl1_map.ncd.
mpartrce -p "RAM2GS_LCMXO2_640HC_impl1.p2t" -f "RAM2GS_LCMXO2_640HC_impl1.p3t" -tf "RAM2GS_LCMXO2_640HC_impl1.pt" "RAM2GS_LCMXO2_640HC_impl1_map.ncd" "RAM2GS_LCMXO2_640HC_impl1.ncd"
---- MParTrce Tool ----
Removing old design directory at request of -rem command line option to this program.
Running par. Please wait . . .
Lattice Place and Route Report for Design "RAM2GS_LCMXO2_640HC_impl1_map.ncd"
Tue Aug 15 23:30:05 2023
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
Placement level-cost: 5-1.
Routing Iterations: 6
Loading design for application par from file RAM2GS_LCMXO2_640HC_impl1_map.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-640HC
Package: TQFP100
Performance: 4
Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
License checked out.
Ignore Preference Error(s): True
Device utilization summary:
PIO (prelim) 67+4(JTAG)/80 89% used
67+4(JTAG)/79 90% bonded
IOLOGIC 29/80 36% used
SLICE 81/320 25% used
Number of Signals: 292
Number of Connections: 703
Pin Constraint Summary:
67 out of 67 pins locked (100% locked).
The following 2 signals are selected to use the primary clock routing resources:
RCLK_c (driver: RCLK, clk load #: 39)
PHI2_c (driver: PHI2, clk load #: 18)
<postMsg mid="61061008" type="Warning" dynamic="5" navigation="0" arg0="RCLK_c" arg1="Primary" arg2="RCLK" arg3="62" arg4="Primary" />
<postMsg mid="61061008" type="Warning" dynamic="5" navigation="0" arg0="PHI2_c" arg1="Primary" arg2="PHI2" arg3="8" arg4="Primary" />
The following 2 signals are selected to use the secondary clock routing resources:
nCRAS_c (driver: nCRAS, clk load #: 9, sr load #: 0, ce load #: 0)
nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0)
<postMsg mid="61061008" type="Warning" dynamic="5" navigation="0" arg0="nCRAS_c" arg1="Secondary" arg2="nCRAS" arg3="17" arg4="Secondary" />
<postMsg mid="61061008" type="Warning" dynamic="5" navigation="0" arg0="nCCAS_c" arg1="Secondary" arg2="nCCAS" arg3="9" arg4="Secondary" />
No signal is selected as Global Set/Reset.
Starting Placer Phase 0.
...........
Finished Placer Phase 0. REAL time: 0 secs
Starting Placer Phase 1.
....................
Placer score = 41844.
Finished Placer Phase 1. REAL time: 4 secs
Starting Placer Phase 2.
.
Placer score = 41803
Finished Placer Phase 2. REAL time: 4 secs
------------------ Clock Report ------------------
Global Clock Resources:
CLK_PIN : 0 out of 8 (0%)
General PIO: 4 out of 80 (5%)
DCM : 0 out of 2 (0%)
DCC : 0 out of 8 (0%)
Global Clocks:
PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 39
PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 18
SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 9, ce load = 0, sr load = 0
SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 8, ce load = 0, sr load = 0
PRIMARY : 2 out of 8 (25%)
SECONDARY: 2 out of 8 (25%)
--------------- End of Clock Report ---------------
I/O Usage Summary (final):
67 + 4(JTAG) out of 80 (88.8%) PIO sites used.
67 + 4(JTAG) out of 79 (89.9%) bonded PIO sites used.
Number of PIO comps: 67; differential: 0.
Number of Vref pins used: 0.
I/O Bank Usage Summary:
+----------+----------------+------------+-----------+
| I/O Bank | Usage | Bank Vccio | Bank Vref |
+----------+----------------+------------+-----------+
| 0 | 13 / 19 ( 68%) | 3.3V | - |
| 1 | 20 / 20 (100%) | 3.3V | - |
| 2 | 16 / 20 ( 80%) | 3.3V | - |
| 3 | 18 / 20 ( 90%) | 3.3V | - |
+----------+----------------+------------+-----------+
Total placer CPU time: 3 secs
Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
0 connections routed; 703 unrouted.
Starting router resource preassignment
<postMsg mid="62061008" type="Warning" dynamic="1" navigation="0" arg0="RCLK_c" />
Completed router resource preassignment. Real time: 6 secs
Start NBR router at 23:30:11 08/15/23
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
in the earlier iterations. In each iteration, it tries to
solve the conflicts while keeping the critical connections
routed as short as possible. The routing process is said to
be completed when no conflicts exist and all connections
are routed.
Note: NBR uses a different method to calculate timing slacks. The
worst slack and total negative slack may not be the same as
that in TRCE report. You should always run TRCE to verify
your design.
*****************************************************************
Start NBR special constraint process at 23:30:11 08/15/23
Start NBR section for initial routing at 23:30:11 08/15/23
Level 1, iteration 1
0(0.00%) conflict; 529(75.25%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 6.016ns/0.000ns; real time: 6 secs
Level 2, iteration 1
0(0.00%) conflict; 526(74.82%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 5.772ns/0.000ns; real time: 6 secs
Level 3, iteration 1
0(0.00%) conflict; 526(74.82%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 6.058ns/0.000ns; real time: 6 secs
Level 4, iteration 1
3(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 5.827ns/0.000ns; real time: 6 secs
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
Start NBR section for normal routing at 23:30:11 08/15/23
Level 4, iteration 1
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 5.827ns/0.000ns; real time: 6 secs
Level 4, iteration 2
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 5.827ns/0.000ns; real time: 6 secs
Start NBR section for setup/hold timing optimization with effort level 3 at 23:30:11 08/15/23
Start NBR section for re-routing at 23:30:11 08/15/23
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 5.827ns/0.000ns; real time: 6 secs
Start NBR section for post-routing at 23:30:11 08/15/23
End NBR router with 0 unrouted connection
NBR Summary
-----------
Number of unrouted connections : 0 (0.00%)
Number of connections with timing violations : 0 (0.00%)
Estimated worst slack<setup> : 5.827ns
Timing score<setup> : 0
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
Total CPU time 5 secs
Total REAL time: 6 secs
Completely routed.
End of route. 703 routed (100.00%); 0 unrouted.
Hold time timing score: 0, hold timing errors: 0
Timing score: 0
Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst slack<setup/<ns>> = 5.827
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.304
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
PAR_SUMMARY::Number of errors = 0
Total CPU time to completion: 5 secs
Total REAL time to completion: 6 secs
par done!
Note: user must run 'Trace' for timing closure signoff.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Exiting par with exit code 0
Exiting mpartrce with exit code 0
tmcheck -par "RAM2GS_LCMXO2_640HC_impl1.par"
bitgen -f "RAM2GS_LCMXO2_640HC_impl1.t2b" -w "RAM2GS_LCMXO2_640HC_impl1.ncd" -jedec "RAM2GS_LCMXO2_640HC_impl1.prf"
BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Loading design for application Bitgen from file RAM2GS_LCMXO2_640HC_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-640HC
Package: TQFP100
Performance: 4
Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
Running DRC.
DRC detected 0 errors and 0 warnings.
Reading Preference File from RAM2GS_LCMXO2_640HC_impl1.prf.
Preference Summary:
+---------------------------------+---------------------------------+
| Preference | Current Setting |
+---------------------------------+---------------------------------+
| RamCfg | Reset** |
+---------------------------------+---------------------------------+
| MCCLK_FREQ | 2.08** |
+---------------------------------+---------------------------------+
| CONFIG_SECURE | OFF** |
+---------------------------------+---------------------------------+
| INBUF | ON** |
+---------------------------------+---------------------------------+
| JTAG_PORT | ENABLE** |
+---------------------------------+---------------------------------+
| SDM_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| SLAVE_SPI_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| MASTER_SPI_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| I2C_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| MUX_CONFIGURATION_PORTS | DISABLE** |
+---------------------------------+---------------------------------+
| CONFIGURATION | CFG** |
+---------------------------------+---------------------------------+
| COMPRESS_CONFIG | ON** |
+---------------------------------+---------------------------------+
| MY_ASSP | OFF** |
+---------------------------------+---------------------------------+
| ONE_TIME_PROGRAM | OFF** |
+---------------------------------+---------------------------------+
| ENABLE_TRANSFR | DISABLE** |
+---------------------------------+---------------------------------+
| SHAREDEBRINIT | DISABLE** |
+---------------------------------+---------------------------------+
| BACKGROUND_RECONFIG | OFF** |
+---------------------------------+---------------------------------+
* Default setting.
** The specified setting matches the default setting.
Creating bit map...
Bitstream Status: Final Version 1.95.
Saving bit stream in "RAM2GS_LCMXO2_640HC_impl1.jed".
===========
UFM Summary.
===========
UFM Size: 191 Pages (128*191 Bits).
UFM Utilization: General Purpose Flash Memory.
Available General Purpose Flash Memory: 191 Pages (Page 0 to Page 190).
Initialized UFM Pages: 0 Page.
Total CPU Time: 1 secs
Total REAL Time: 2 secs
Peak Memory Usage: 246 MB
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