2020-06-28 18:28:35 +00:00
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---
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title: 28C256 Notes
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---
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# Notes on 28C EEPROMs
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2020-06-29 15:48:57 +00:00
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The 28C series parallel EEPROMS, like the 28C256, support fast block writes and algorithms
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to implement Software Data Protection (SDP). The SDP feature seems to be a leading cause
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of problems for people trying to program these chips with Arduino or other homebrew
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hardware.
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The first problem many people encounter is that new chips are often locked, even though
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the datasheet states that they should ship unlocked. It isn't clear if the manufacturing
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practices have changed or if this might be due to used or counterfeit chips. In any case,
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the chips may need to be unlocked before they can be programmed for the first time.
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The unlock is accomplished by sending a sequence of bytes to specific addresses. Many
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people have reported problems with this step when using DIY programmers. Some programmers
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may not be writing the SDP sequences quickly enough to successfully unlock the chips and
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yet others will report that the same hardware works correctly. This may be due to
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variances in the behavior of chips from different manufacturers.
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When writing SDP lock/unlock sequences, the datasheets note that the timing between bytes
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must follow the same restrictions as page writes. In particular, the bytes must be
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written within the tBLC (Byte Load Cycle time). On Atmel parts, this is specified as
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150us max, so each write pulse must occur within 150us of the previous write. The tBLC
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value is even shorter on the Xicor and ON Semi datasheets, stating that the writes must
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occur within 100us of each other.
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In practice, the Xicor chips seem very forgiving of the timing, doing successful SDP and
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page write operations even when the tBLC is close to 200us. Atmel chips, on the other
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hand, will refuse to unlock when the timing is outside the acceptable maximum.
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2020-06-28 18:28:35 +00:00
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# Solution
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2020-06-29 15:48:57 +00:00
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The TommyProm programmer uses direct port access on the Arduino to control the data bus
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and addressing shift register. This is much faster than doing individual DigitalWrite
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calls and allows the unlock and page write code to run comfortably within the tBLC
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constraints. It has been successfully tested with the following 28C256 chips:
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2020-06-28 18:28:35 +00:00
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* Atmel AT28C256-15PU
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* Catalyst/ON Semi CSI CAT28C256P-12
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* Xicor X28C256P-15
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* Xicor X28C256P-25
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2020-06-29 15:48:57 +00:00
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The Atmel chips tested included a batch from eBay that may not have been genuine, but they
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were unlocked and burned successfully with the TommyProm code.
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2020-06-28 18:28:35 +00:00
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2020-06-29 15:48:57 +00:00
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The capture below shows an unlock command sequence where the tBLC is within 80us for each
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byte.
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2020-06-28 18:28:35 +00:00
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2020-06-29 15:48:57 +00:00
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2020-06-28 18:28:35 +00:00
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# References
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1. [Atmel AT28C256 Data Sheet, 0006M–PEEPR–12/09](http://ww1.microchip.com/downloads/en/DeviceDoc/doc0006.pdf)
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1. [Xicor, Intersil, Renesas X28C256 Data Sheet, 3855-1.9 8/1/97 T1/C0/D8 EW](https://www.renesas.com/us/en/www/doc/datasheet/x28hc256.pdf)
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1. [ON Semiconductor CAT28C256 Data Sheet, CAT28C256/D, December, 2009 − Rev. 6](https://www.onsemi.com/pub/Collateral/CAT28C256-D.PDF)
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1. [Parallel EEPROM Data Protection Application Note, Atmel, Rev. 0543C–10/98](http://ww1.microchip.com/downloads/en/AppNotes/DOC0543.PDF)
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