mirror of
https://github.com/JorjBauer/aiie.git
synced 2024-08-28 01:29:03 +00:00
1142 lines
29 KiB
C++
1142 lines
29 KiB
C++
#ifdef TEENSYDUINO
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#include <Arduino.h>
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#define assert(x)
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#else
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#include <stdio.h>
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#include <unistd.h>
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#include <assert.h>
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#endif
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#include "applemmu.h"
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#include "applemmu-rom.h"
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#include "physicalspeaker.h"
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#include "cpu.h"
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#include "globals.h"
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#ifdef TEENSYDUINO
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#include "teensy-clock.h"
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#else
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#include "nix-clock.h"
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#endif
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// Serializing token for MMU data
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#define MMUMAGIC 'M'
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// apple //e memory map
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/*
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page 0x00: zero page (straight ram)
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page 0x01: stack (straight ram)
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page 0x02:
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page 0x03:
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text/lores page 1: 0x0400 - 0x7FF
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text/lores page 2: 0x0800 - 0xBFF
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pages 0x0C - 0x1F: straight ram
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hires page 1: pages 0x20 - 0x3F
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hires page 2: pages 0x40 - 0x5F
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pages 0x60 - 0xBF: straight ram
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page 0xc0: I/O switches (some store 1-byte state)
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pages 0xc1 - 0xcf: slot ROMs
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pages 0xd0 - 0xdf: Basic ROM
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pages 0xe0 - 0xff: monitor ROM
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*/
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/*
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The memory model for this is...
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page 0-1 4 pages (1k) [altzp]
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2-0xBF 190 * 2 pages = 380 pages = 95k [auxRamRead/Write, S_HIRES, S_80STORE, S_PAGE2]
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0xC0 1 page (256 bytes) (1-byte state for virtual I/O switches)
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0xC1-0xCF 15 * 2 pages = 30 pages (7.5k) [intcxrom, slotLatch]
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0xD0 - 0xDF 16 * 5 pages = 80 pages (20k) [altzp, bank2, {r,w}bsr]
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0xE0 - 0xFF 32 * 3 pages = 96 pages (24k) [altzp, {r,w}bsr]
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= 147.75k (591 pages) stored off-chip
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Current read page table [512 bytes] in real ram
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Current write page table [512 bytes] in real ram
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*/
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// This has a split memory model so more often addressed pages can be
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// in internal memory, and an external memory can hold others.
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//
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// We want the video display pages in real RAM as much as possible,
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// since blits wind up touching so much of it. If we can keep that in
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// main RAM, then the blits won't try to read the external SRAM while
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// the CPU is writing to it.
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//
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//
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// After that it's all a guess. Should it be slot ROMs?
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// extended RAM? Hires RAM? FIXME: do some analysis of common memory
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// hotspots...
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enum {
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// Pages we want to fall to internal RAM:
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MP_ZP = 0, // page 0/1 * 2 page variants = 4; 0..3
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MP_4 = 4, // 0x04 - 0x07 (text display pages) * 2 variants = 8; 4..11
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MP_20 = 12, // 0x20 - 0x5F * 2 variants = 128; 12..139
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// Pages that can go to external RAM if needed:
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MP_2 = 140, // 0x02 - 0x03 * 2 variants = 4; 140..143
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MP_8 = 144, // 0x08 - 0x1F * 2 = 48; 144..191
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MP_60 = 192, // 0x60 - 0xBF * 2 = 192; 192..383
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MP_C1 = 384, // start of 0xC1-0xCF * 2 page variants = 30; 384-413
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MP_D0 = 414, // start of 0xD0-0xDF * 5 page variants = 80; 414-493
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MP_E0 = 493, // start of 0xE0-0xFF * 3 page variants = 96; 494-589
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MP_C0 = 590
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// = 591 pages in all (147.75k)
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};
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static uint16_t _pageNumberForRam(uint8_t highByte, uint8_t variant)
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{
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if (highByte <= 1) {
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// zero page.
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return highByte + (variant*2) + MP_ZP;
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}
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if (highByte <= 3) {
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return ((highByte - 2) * 2 + variant + MP_2);
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}
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if (highByte <= 7) {
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return ((highByte - 4) * 2 + variant + MP_4);
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}
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if (highByte <= 0x1f) {
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return ((highByte - 8) * 2 + variant + MP_8);
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}
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if (highByte <= 0x5f) {
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return ((highByte - 0x20) * 2 + variant + MP_20);
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}
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if (highByte <= 0xbf) {
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return ((highByte - 0x60) * 2 + variant + MP_60);
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}
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if (highByte == 0xc0) {
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return MP_C0;
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}
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if (highByte <= 0xCF) {
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// 0xC1-0xCF 15 * 2 pages = 30 pages (7.5k)
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return ((highByte - 0xC1) * 2 + variant + MP_C1);
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}
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if (highByte <= 0xDF) {
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// 0xD0 - 0xDF 16 * 5 pages = 80 pages (20k)
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return ((highByte - 0xD0) * 5 + variant + MP_D0);
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}
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// 0xE0 - 0xFF 32 * 3 pages = 96 pages (24k)
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return ((highByte - 0xE0) * 3 + variant + MP_E0);
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}
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AppleMMU::AppleMMU(AppleDisplay *display)
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{
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anyKeyDown = false;
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for (int8_t i=0; i<=7; i++) {
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slots[i] = NULL;
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}
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this->display = display;
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this->display->setSwitches(&switches);
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resetRAM(); // initialize RAM, load ROM
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#ifdef TEENSYDUINO
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clock = new TeensyClock((AppleMMU *)this);
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#else
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clock = new NixClock((AppleMMU *)this);
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#endif
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}
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AppleMMU::~AppleMMU()
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{
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delete display;
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}
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bool AppleMMU::Serialize(int8_t fd)
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{
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uint8_t buf[13] = { MMUMAGIC,
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(switches >> 8) & 0xFF,
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(switches ) & 0xFF,
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auxRamRead ? 1 : 0,
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auxRamWrite ? 1 : 0,
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bank2 ? 1 : 0,
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readbsr ? 1 : 0,
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writebsr ? 1 : 0,
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altzp ? 1 : 0,
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intcxrom ? 1 : 0,
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slot3rom ? 1 : 0,
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slotLatch,
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preWriteFlag ? 1 : 0 };
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if (g_filemanager->write(fd, buf, 13) != 13)
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return false;
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if (!g_ram.Serialize(fd))
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return false;
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// readPages & writePages don't need suspending, but we will need to
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// recalculate after resume
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// Not suspending/resuming slots b/c they're a fixed configuration
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// in this project. Should probably checksum them though. FIXME.
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if (g_filemanager->write(fd, buf, 1) != 1)
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return false;
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return true;
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}
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bool AppleMMU::Deserialize(int8_t fd)
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{
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uint8_t buf[13];
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if (g_filemanager->read(fd, buf, 13) != 13)
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return false;
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if (buf[0] != MMUMAGIC)
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return false;
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switches = (buf[1] << 8) | buf[2];
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auxRamRead = buf[3];
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auxRamWrite = buf[4];
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bank2 = buf[5];
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readbsr = buf[6];
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writebsr = buf[7];
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altzp = buf[8];
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intcxrom = buf[9];
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slot3rom = buf[10];
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slotLatch = buf[11];
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preWriteFlag = buf[12];
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if (!g_ram.Deserialize(fd)) {
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return false;
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}
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if (g_filemanager->read(fd, buf, 1) != 1)
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return false;
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if (buf[0] != MMUMAGIC)
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return false;
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// Reset readPages[] and writePages[] and the display
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resetDisplay();
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return true;
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}
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void AppleMMU::Reset()
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{
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resetRAM();
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resetDisplay(); // sets the switches properly
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}
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uint8_t AppleMMU::read(uint16_t address)
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{
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uint8_t rv = 0;
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if (handleNoSlotClock(address, &rv)) {
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return rv;
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}
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if (address >= 0xC000 &&
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address <= 0xC0FF) {
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return readSwitches(address);
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}
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// If C800-CFFF isn't latched to a slot ROM, and we try to
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// access a slot's memory space from C100-C7FF, then we need
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// to latch in the slot's ROM.
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if (slotLatch == -1 && address >= 0xc100 && address <= 0xc7ff) {
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slotLatch = (address >> 8) & 0x07;
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if (slotLatch == 3 && slot3rom) {
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// Back off: UTA2E p. 5-28: don't latch in slot 3 ROM while
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// the slot3rom flag is enabled
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// fixme
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slotLatch = 3;
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} else {
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updateMemoryPages();
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}
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}
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// If we access CFFF, that unlatches slot ROM.
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if (address == 0xCFFF) {
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slotLatch = -1;
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updateMemoryPages();
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}
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uint8_t res = g_ram.readByte((readPages[address >> 8] << 8) | (address & 0xFF));
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return res;
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}
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// Bypass MMU and read directly from a given page - also bypasses switches
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uint8_t AppleMMU::readDirect(uint16_t address, uint8_t fromPage)
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{
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uint16_t page = _pageNumberForRam(address >> 8, fromPage);
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return g_ram.readByte((page << 8) | (address & 0xFF));
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}
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void AppleMMU::write(uint16_t address, uint8_t v)
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{
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if (handleNoSlotClock(address, NULL)) {
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return;
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}
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if (address >= 0xC000 &&
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address <= 0xC0FF) {
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return writeSwitches(address, v);
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}
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// Don't allow writes to ROM
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// Hard ROM, I/O, slots, whatnot
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if (address >= 0xC100 && address <= 0xCFFF)
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return;
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// Bank-switched ROM/RAM areas
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if (address >= 0xD000 && address <= 0xFFFF && !writebsr) {
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return;
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}
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g_ram.writeByte((writePages[address >> 8] << 8) | (address & 0xFF), v);
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if (address >= 0x400 &&
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address <= 0x7FF) {
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// If it's text mode, or mixed mode, or lores graphics mode, then update.
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if ((switches & S_TEXT) || (switches & S_MIXED) || (!(switches & S_HIRES))) {
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// Force a redraw
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display->modeChange();
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}
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return;
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}
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if (address >= 0x2000 &&
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address <= 0x5FFF) {
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if (switches & S_HIRES) {
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// Force a redraw
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display->modeChange();
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}
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}
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}
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bool AppleMMU::handleNoSlotClock(uint16_t address, uint8_t *rv)
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{
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uint8_t ah = address >> 8;
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if ( ((!intcxrom || !slot3rom) && (ah == 0xc3)) ||
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(ah == 0xc8) ) {
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if (rv) {
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// It's a read attempt - we want a return value.
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*rv = 0;
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if (clock->read(address, rv)) {
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return true;
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}
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} else {
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clock->write(address);
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return true;
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}
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}
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return false;
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}
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// FIXME: this is no longer "MMU", is it?
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void AppleMMU::resetDisplay()
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{
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updateMemoryPages();
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display->modeChange();
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}
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void AppleMMU::handleMemorySwitches(uint16_t address, uint16_t lastSwitch)
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{
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// many of these are spelled out here:
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// http://apple2.org.za/gswv/a2zine/faqs/csa2pfaq.html
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switch (address) {
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case 0xC000: // CLR80STORE
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switches &= ~S_80STORE;
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break;
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case 0xC001: // SET80STORE
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switches |= S_80STORE;
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break;
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case 0xC002: // CLRAUXRD read from main 48k RAM
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auxRamRead = false;
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break;
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case 0xC003: // SETAUXRD read from aux/alt 48k
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auxRamRead = true;
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break;
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case 0xC004: // CLRAUXWR write to main 48k RAM
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auxRamWrite = false;
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break;
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case 0xC005: // SETAUXWR write to aux/alt 48k
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auxRamWrite = true;
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break;
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case 0xC006: // CLRCXROM use ROM on cards
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intcxrom = false;
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break;
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case 0xC007: // SETCXROM use internal ROM
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intcxrom = true;
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break;
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case 0xC008: // CLRAUXZP use main zero page, stack, LC
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altzp = false;
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break;
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case 0xC009: // SETAUXZP use alt zero page, stack, LC
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altzp = true;
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break;
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case 0xC00A: // CLRC3ROM use internal slot 3 ROM
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slot3rom = false;
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break;
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case 0xC00B: // SETC3ROM use external slot 3 ROM
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slot3rom = true;
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break;
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// Registers C080 - C08F control bank switching.
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case 0xC080:
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case 0xC081:
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case 0xC082:
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case 0xC083:
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case 0xC084:
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case 0xC085:
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case 0xC086:
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case 0xC087:
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case 0xC088:
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case 0xC089:
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case 0xC08A:
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case 0xC08B:
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case 0xC08C:
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case 0xC08D:
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case 0xC08E:
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case 0xC08F:
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// Per ITA2E, p. 286:
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// (address & 0x08) controls whether or not we are selecting from bank2. Per table 8-2,
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// bank2 is active if address & 0x08 is zero. So if the bit is on, it's bank 1.
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bank2 = (address & 0x08) ? false : true;
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// (address & 0x04) is unused.
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// (address & 0x02) is read-select: if it is set the same as
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// (address & 0x01) then readbsr is true.
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readbsr = ((address & 0x02) >> 1) == (address & 0x01);
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// (address & 0x01) is write-select: if 1, we write BSR RAM; if 0, we write ROM.
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// But it's a little more complicated than readbsr.
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// Per UTA2E p. 5-23:
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// "Writing to high RAM is enabled when the HRAMWRT' soft switch
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// is reset. ... It is reset by even read access or any write
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// access in the $C08X range. HRAMWRT' is reset by odd read
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// access in the $C08X range when PRE-WRITE is set. It is set by
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// even access in the CC08X range. Any other type of access
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// causes HRAMWRT' to hold its current state."
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if (address & 0x01) {
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if (preWriteFlag)
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writebsr = 1;
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// Per UTA2E, p. 5-23: any other preWriteFlag leaves writebsr unchanged.
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} else {
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writebsr = false;
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}
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break;
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}
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updateMemoryPages();
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}
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// many (most? all?) switches are documented here:
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// http://apple2.org.za/gswv/a2zine/faqs/csa2pfaq.html
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uint8_t AppleMMU::readSwitches(uint16_t address)
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{
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static uint16_t lastReadSwitch = 0x0000;
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static uint16_t thisReadSwitch = 0x0000;
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lastReadSwitch = thisReadSwitch;
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thisReadSwitch = address;
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// If this is a read for any of the slot switches, and we have
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// hardware in that slot, then return its result.
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if (address >= 0xC090 && address <= 0xC0FF) {
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for (uint8_t i=1; i<=7; i++) {
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if (address >= (0xC080 | (i << 4)) &&
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address <= (0xC08F | (i << 4))) {
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if (slots[i]) {
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return slots[i]->readSwitches(address & ~(0xC080 | (i<<4)));
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}
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else
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return FLOATING;
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}
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}
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}
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switch (address) {
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case 0xC010:
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// consume the keyboard strobe flag
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g_ram.writeByte((writePages[0xC0] << 8) | 0x10,
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g_ram.readByte((readPages[0xC0] << 8) | 0x10) & 0x7F);
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return (anyKeyDown ? 0x80 : 0x00);
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case 0xC080:
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case 0xC081:
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case 0xC082:
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case 0xC083:
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case 0xC084:
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case 0xC085:
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case 0xC086:
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case 0xC087:
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case 0xC088:
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case 0xC089:
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case 0xC08A:
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case 0xC08B:
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case 0xC08C:
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case 0xC08D:
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case 0xC08E:
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case 0xC08F:
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// but read does affect these, same as write
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handleMemorySwitches(address, lastReadSwitch);
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// UTA2E, p. 5-23: preWrite is set by odd read access, and reset
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// by even read access
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preWriteFlag = (address & 0x01);
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return FLOATING;
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case 0xC00C: // CLR80VID disable 80-col video mode
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if (switches & S_80COL) {
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switches &= ~S_80COL;
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resetDisplay();
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}
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break; // fall through
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case 0xC00D: // SET80VID enable 80-col video mode
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if (!(switches & S_80COL)) {
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switches |= S_80COL;
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resetDisplay();
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}
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break; // fall through
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case 0xC00E: // CLRALTCH use main char set - norm LC, flash UC
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switches &= ~S_ALTCH;
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break; // fall through
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case 0xC00F: // SETALTCH use alt char set - norm inverse, LC; no flash
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switches |= S_ALTCH;
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break; // fall through
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case 0xC011: // RDLCBNK2
|
|
return bank2 ? 0x80 : 0x00;
|
|
case 0xC012: // RDLCRAM
|
|
return readbsr ? 0x80 : 0x00;
|
|
case 0xC013: // RDRAMRD
|
|
return auxRamRead ? 0x80 : 0x00;
|
|
case 0xC014: // RDRAMWR
|
|
return auxRamWrite ? 0x80 : 0x00;
|
|
case 0xC015: // RDCXROM
|
|
return intcxrom ? 0x80 : 0x00;
|
|
case 0xC016: // RDAUXZP
|
|
return altzp ? 0x80 : 0x00;
|
|
case 0xC017: // RDC3ROM
|
|
return slot3rom ? 0x80 : 0x00;
|
|
|
|
case 0xC018: // RD80COL
|
|
return (switches & S_80STORE) ? 0x80 : 0x00;
|
|
case 0xC019: // RDVBLBAR -- vertical blanking, for 4550 cycles of every 17030
|
|
// Should return 0 for 4550 of 17030 cycles. Since we're not really
|
|
// running full speed video, instead, I'm returning 0 for 4096 (2^12)
|
|
// of every 16384 (2^14) cycles; the math is easier.
|
|
if ((g_cpu->cycles & 0x3000) == 0x3000) {
|
|
return 0x00;
|
|
} else {
|
|
return 0xFF; // FIXME: is 0xFF correct? Or 0x80?
|
|
}
|
|
case 0xC01A: // RDTEXT
|
|
return ( (switches & S_TEXT) ? 0x80 : 0x00 );
|
|
case 0xC01B: // RDMIXED
|
|
return ( (switches & S_MIXED) ? 0x80 : 0x00 );
|
|
case 0xC01C: // RDPAGE2
|
|
return ( (switches & S_PAGE2) ? 0x80 : 0x00 );
|
|
case 0xC01D: // RDHIRES
|
|
return ( (switches & S_HIRES) ? 0x80 : 0x00 );
|
|
case 0xC01E: // RDALTCH
|
|
return ( (switches & S_ALTCH) ? 0x80 : 0x00 );
|
|
case 0xC01F: // RD80VID
|
|
return ( (switches & S_80COL) ? 0x80 : 0x00 );
|
|
|
|
|
|
case 0xC030: // SPEAKER
|
|
g_speaker->toggle(g_cpu->cycles);
|
|
#ifndef SUPPRESSREALTIME
|
|
g_cpu->realtime(); // cause the CPU to stop processing its outer
|
|
// loop b/c the speaker might need attention
|
|
// immediately
|
|
#endif
|
|
return FLOATING;
|
|
|
|
case 0xC050: // CLRTEXT
|
|
if (switches & S_TEXT) {
|
|
switches &= ~S_TEXT;
|
|
resetDisplay();
|
|
}
|
|
return FLOATING;
|
|
case 0xC051: // SETTEXT
|
|
if (!(switches & S_TEXT)) {
|
|
switches |= S_TEXT;
|
|
resetDisplay();
|
|
}
|
|
return FLOATING;
|
|
case 0xC052: // CLRMIXED
|
|
if (switches & S_MIXED) {
|
|
switches &= ~S_MIXED;
|
|
resetDisplay();
|
|
}
|
|
return FLOATING;
|
|
case 0xC053: // SETMIXED
|
|
if (!(switches & S_MIXED)) {
|
|
switches |= S_MIXED;
|
|
resetDisplay();
|
|
}
|
|
return FLOATING;
|
|
|
|
case 0xC054: // PAGE1
|
|
if (switches & S_PAGE2) {
|
|
switches &= ~S_PAGE2;
|
|
if (!(switches & S_80COL)) {
|
|
resetDisplay();
|
|
} else {
|
|
updateMemoryPages();
|
|
}
|
|
}
|
|
return FLOATING;
|
|
|
|
case 0xC055: // PAGE2
|
|
if (!(switches & S_PAGE2)) {
|
|
switches |= S_PAGE2;
|
|
if (!(switches & S_80COL)) {
|
|
resetDisplay();
|
|
} else {
|
|
updateMemoryPages();
|
|
}
|
|
}
|
|
return FLOATING;
|
|
|
|
case 0xC056: // CLRHIRES
|
|
if (switches & S_HIRES) {
|
|
switches &= ~S_HIRES;
|
|
resetDisplay();
|
|
}
|
|
return FLOATING;
|
|
case 0xC057: // SETHIRES
|
|
if (!(switches & S_HIRES)) {
|
|
switches |= S_HIRES;
|
|
resetDisplay();
|
|
}
|
|
return FLOATING;
|
|
|
|
case 0xC05E: // DHIRES ON
|
|
if (!(switches & S_DHIRES)) {
|
|
switches |= S_DHIRES;
|
|
resetDisplay();
|
|
}
|
|
return FLOATING;
|
|
|
|
case 0xC05F: // DHIRES OFF
|
|
if (switches & S_DHIRES) {
|
|
switches &= ~S_DHIRES;
|
|
resetDisplay();
|
|
}
|
|
return FLOATING;
|
|
|
|
// paddles
|
|
/* Fall through for apple keys; they're just RAM in this model
|
|
case 0xC061: // OPNAPPLE
|
|
return isOpenApplePressed ? 0x80 : 0x00;
|
|
case 0xC062: // CLSAPPLE
|
|
return isClosedApplePressed ? 0x80 : 0x00;
|
|
*/
|
|
|
|
case 0xC070: // PDLTRIG
|
|
// It doesn't matter if we update readPages or writePages, because 0xC0
|
|
// has only one page.
|
|
g_ram.writeByte((writePages[0xC0] << 8) | 0x64, 0xFF);
|
|
g_ram.writeByte((writePages[0xC0] << 8) | 0x65, 0xFF);
|
|
g_paddles->startReading();
|
|
return FLOATING;
|
|
}
|
|
|
|
if (address >= 0xc000 && address <= 0xc00f) {
|
|
// This is the keyboardStrobe support referenced in the switch statement above.
|
|
return g_ram.readByte((readPages[0xC0] << 8) | 0x10);
|
|
}
|
|
|
|
/* *** FIXME:
|
|
SETIOUDIS= $C07E ;enable DHIRES & disable $C058-5F (W)
|
|
CLRIOUDIS= $C07E ;disable DHIRES & enable $C058-5F (W)
|
|
0xC05e and 0xc05f should fall through if that IOUDIS is not activated
|
|
|
|
need to see if that's a toggle, or if it's a typo (c07f, maybe?)
|
|
*/
|
|
|
|
return g_ram.readByte((readPages[address >> 8] << 8) | (address & 0xFF));
|
|
}
|
|
|
|
void AppleMMU::writeSwitches(uint16_t address, uint8_t v)
|
|
{
|
|
// fixme: combine these with the last read switch
|
|
static uint16_t lastWriteSwitch = 0x0000;
|
|
static uint16_t thisWriteSwitch = 0x0000;
|
|
lastWriteSwitch = thisWriteSwitch;
|
|
thisWriteSwitch = address;
|
|
|
|
// If this is a write for any of the slot switches, and we have
|
|
// hardware in that slot, then return its result.
|
|
if (address >= 0xC090 && address <= 0xC0FF) {
|
|
for (uint8_t i=1; i<=7; i++) {
|
|
if (address >= (0xC080 | (i << 4)) &&
|
|
address <= (0xC08F | (i << 4))) {
|
|
if (slots[i]) {
|
|
slots[i]->writeSwitches(address & ~(0xC080 | (i<<4)), v);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
switch (address) {
|
|
case 0xC010:
|
|
case 0xC011: // Per Understanding the Apple //e, p. 7-3:
|
|
case 0xC012: // a write to any $C01x address causes
|
|
case 0xC013: // a clear of the keyboard strobe.
|
|
case 0xC014:
|
|
case 0xC015:
|
|
case 0xC016:
|
|
case 0xC017:
|
|
case 0xC018:
|
|
case 0xC019:
|
|
case 0xC01A:
|
|
case 0xC01B:
|
|
case 0xC01C:
|
|
case 0xC01D:
|
|
case 0xC01E:
|
|
case 0xC01F:
|
|
// Consume keyboard strobe
|
|
g_ram.writeByte((writePages[0xC0] << 8) | 0x10,
|
|
g_ram.readByte((readPages[0xC0] << 8) | 0x10) & 0x7F);
|
|
return;
|
|
|
|
case 0xC030: // SPEAKER
|
|
// Writes toggle the speaker twice
|
|
g_speaker->toggle(g_cpu->cycles);
|
|
g_speaker->toggle(g_cpu->cycles);
|
|
#ifndef SUPPRESSREALTIME
|
|
g_cpu->realtime(); // cause the CPU to stop processing its outer
|
|
// loop b/c the speaker might need attention
|
|
// immediately
|
|
#endif
|
|
return;
|
|
|
|
case 0xC050: // graphics mode
|
|
if (switches & S_TEXT) {
|
|
switches &= ~S_TEXT;
|
|
resetDisplay();
|
|
}
|
|
return;
|
|
|
|
case 0xC051:
|
|
if (!(switches & S_TEXT)) {
|
|
switches |= S_TEXT;
|
|
resetDisplay();
|
|
}
|
|
return;
|
|
|
|
case 0xC052: // "no mixed"
|
|
if (switches & S_MIXED) {
|
|
switches &= ~S_MIXED;
|
|
resetDisplay();
|
|
}
|
|
return;
|
|
|
|
case 0xC053: // "mixed"
|
|
if (!(switches & S_MIXED)) {
|
|
switches |= S_MIXED;
|
|
resetDisplay();
|
|
}
|
|
return;
|
|
|
|
case 0xC054: // page2 off
|
|
if (switches & S_PAGE2) {
|
|
switches &= ~S_PAGE2;
|
|
if (!(switches & S_80COL)) {
|
|
resetDisplay();
|
|
} else {
|
|
updateMemoryPages();
|
|
}
|
|
}
|
|
return;
|
|
|
|
case 0xC055: // page2 on
|
|
if (!(switches & S_PAGE2)) {
|
|
switches |= S_PAGE2;
|
|
if (!(switches & S_80COL)) {
|
|
resetDisplay();
|
|
} else {
|
|
updateMemoryPages();
|
|
}
|
|
}
|
|
return;
|
|
|
|
case 0xC056: // hires off
|
|
if (switches & S_HIRES) {
|
|
switches &= ~S_HIRES;
|
|
resetDisplay();
|
|
}
|
|
return;
|
|
|
|
case 0xC057: // hires on
|
|
if (!(switches & S_HIRES)) {
|
|
switches |= S_HIRES;
|
|
resetDisplay();
|
|
}
|
|
return;
|
|
|
|
case 0xC05E: // DHIRES ON
|
|
if (!(switches & S_DHIRES)) {
|
|
switches |= S_DHIRES;
|
|
resetDisplay();
|
|
}
|
|
return;
|
|
|
|
case 0xC05F: // DHIRES OFF
|
|
if (switches & S_DHIRES) {
|
|
switches &= ~S_DHIRES;
|
|
resetDisplay();
|
|
}
|
|
return;
|
|
|
|
// paddles
|
|
case 0xC070:
|
|
g_paddles->startReading();
|
|
g_ram.writeByte((writePages[0xC0] << 8) | 0x64, 0xFF);
|
|
g_ram.writeByte((writePages[0xC0] << 8) | 0x65, 0xFF);
|
|
return;
|
|
|
|
case 0xC080:
|
|
case 0xC081:
|
|
case 0xC082:
|
|
case 0xC083:
|
|
case 0xC084:
|
|
case 0xC085:
|
|
case 0xC086:
|
|
case 0xC087:
|
|
case 0xC088:
|
|
case 0xC089:
|
|
case 0xC08A:
|
|
case 0xC08B:
|
|
case 0xC08C:
|
|
case 0xC08D:
|
|
case 0xC08E:
|
|
case 0xC08F:
|
|
// UTA2E, p. 5-23: preWrite is reset by any write access to these
|
|
preWriteFlag = 0;
|
|
// fall through...
|
|
case 0xC000:
|
|
case 0xC001:
|
|
case 0xC002:
|
|
case 0xC003:
|
|
case 0xC004:
|
|
case 0xC005:
|
|
case 0xC006:
|
|
case 0xC007:
|
|
case 0xC008:
|
|
case 0xC009:
|
|
case 0xC00A:
|
|
case 0xC00B:
|
|
handleMemorySwitches(address, lastWriteSwitch);
|
|
return;
|
|
|
|
case 0xC00C: // CLR80VID disable 80-col video mode
|
|
if (switches & S_80COL) {
|
|
switches &= ~S_80COL;
|
|
resetDisplay();
|
|
}
|
|
return;
|
|
|
|
case 0xC00D: // SET80VID enable 80-col video mode
|
|
if (!(switches & S_80COL)) {
|
|
switches |= S_80COL;
|
|
resetDisplay();
|
|
}
|
|
return;
|
|
|
|
case 0xC00E: // CLRALTCH use main char set - norm LC, flash UC
|
|
switches &= ~S_ALTCH;
|
|
return;
|
|
case 0xC00F: // SETALTCH use alt char set - norm inverse, LC; no flash
|
|
switches |= S_ALTCH;
|
|
return;
|
|
}
|
|
|
|
// Anything that falls through gets written to RAM.
|
|
g_ram.writeByte((writePages[0xC0] << 8) | (address & 0xFF),
|
|
v);
|
|
}
|
|
|
|
void AppleMMU::keyboardInput(uint8_t v)
|
|
{
|
|
// Set keyboard strobe
|
|
g_ram.writeByte((writePages[0xC0] << 8) | 0x10,
|
|
v | 0x80);
|
|
anyKeyDown = true;
|
|
}
|
|
|
|
void AppleMMU::setKeyDown(bool isTrue)
|
|
{
|
|
anyKeyDown = isTrue;
|
|
}
|
|
|
|
void AppleMMU::triggerPaddleTimer(uint8_t paddle)
|
|
{
|
|
g_ram.writeByte((writePages[0xC0] << 8) | (0x64 + paddle), 0);
|
|
}
|
|
|
|
void AppleMMU::resetRAM()
|
|
{
|
|
switches = S_TEXT;
|
|
|
|
// Per UTA2E, p. 5-23:
|
|
// When a system reset occurs, all MMU soft switches are reset (turned off).
|
|
bank2 = false;
|
|
auxRamRead = auxRamWrite = false;
|
|
readbsr = writebsr = false;
|
|
altzp = false;
|
|
|
|
intcxrom = false;
|
|
slot3rom = false;
|
|
|
|
slotLatch = -1;
|
|
|
|
preWriteFlag = false;
|
|
|
|
g_ram.init();
|
|
for (uint16_t i=0; i<0x100; i++) {
|
|
readPages[i] = writePages[i] = _pageNumberForRam(i, 0);
|
|
}
|
|
|
|
// Load system ROM
|
|
for (uint16_t i=0x80; i<=0xFF; i++) {
|
|
for (uint16_t k=0; k<0x100; k++) {
|
|
uint16_t idx = ((i-0x80) << 8) | k;
|
|
#ifdef TEENSYDUINO
|
|
uint8_t v = pgm_read_byte(&romData[idx]);
|
|
#else
|
|
uint8_t v = romData[idx];
|
|
#endif
|
|
for (int j=0; j<5; j++) {
|
|
// For the ROM section from 0xc100 .. 0xcfff, we load in to
|
|
// an alternate page space (INTCXROM).
|
|
|
|
uint16_t page0 = _pageNumberForRam(i, 0);
|
|
|
|
if (i >= 0xc1 && i <= 0xcf) {
|
|
// If we want to convince the VM we've got 128k of RAM, we
|
|
// need to load C3 ROM in page 0 (but not 1, meaning there's
|
|
// a board installed); and C800.CFFF in both page [0] and [1]
|
|
// (meaning there's an extended 80-column ROM available,
|
|
// that is also physically in the slot).
|
|
// Everything else goes in page [1].
|
|
|
|
uint16_t page1 = _pageNumberForRam(i, 1);
|
|
|
|
if (i == 0xc3) {
|
|
g_ram.writeByte((page0 << 8) | (k & 0xFF), v);
|
|
}
|
|
else if (i >= 0xc8) {
|
|
g_ram.writeByte((page0 << 8) | (k & 0xFF), v);
|
|
g_ram.writeByte((page1 << 8) | (k & 0xFF), v);
|
|
}
|
|
else {
|
|
g_ram.writeByte((page1 << 8) | (k & 0xFF), v);
|
|
}
|
|
} else {
|
|
// Everything else goes in page 0.
|
|
g_ram.writeByte((page0 << 8) | (k & 0xFF), v);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
// have each slot load its ROM
|
|
for (uint8_t slotnum = 1; slotnum <= 7; slotnum++) {
|
|
uint16_t page0 = _pageNumberForRam(0xC0 + slotnum, 0);
|
|
if (slots[slotnum]) {
|
|
uint8_t tmpBuf[256];
|
|
memset(tmpBuf, 0, sizeof(tmpBuf));
|
|
slots[slotnum]->loadROM(tmpBuf);
|
|
for (int i=0; i<256; i++) {
|
|
g_ram.writeByte( (page0 << 8) + i, tmpBuf[i] );
|
|
}
|
|
}
|
|
}
|
|
|
|
// update the memory read/write flags &c. Not strictly necessary, if
|
|
// we're really setting all the RAM flags to the right default
|
|
// settings above - but better safe than sorry?
|
|
updateMemoryPages();
|
|
}
|
|
|
|
void AppleMMU::setSlot(int8_t slotnum, Slot *peripheral)
|
|
{
|
|
if (slots[slotnum]) {
|
|
delete slots[slotnum];
|
|
}
|
|
|
|
slots[slotnum] = peripheral;
|
|
if (slots[slotnum]) {
|
|
uint16_t page0 = _pageNumberForRam(0xC0 + slotnum, 0);
|
|
uint8_t tmpBuf[256];
|
|
memset(tmpBuf, 0, sizeof(tmpBuf));
|
|
slots[slotnum]->loadROM(tmpBuf);
|
|
for (int i=0; i<256; i++) {
|
|
g_ram.writeByte( (page0 << 8) + i, tmpBuf[i] );
|
|
}
|
|
}
|
|
}
|
|
|
|
void AppleMMU::updateMemoryPages()
|
|
{
|
|
if (auxRamRead) {
|
|
for (uint8_t idx = 0x02; idx < 0xc0; idx++) {
|
|
readPages[idx] = _pageNumberForRam(idx, 1);
|
|
}
|
|
} else {
|
|
for (uint8_t idx = 0x02; idx < 0xc0; idx++) {
|
|
readPages[idx] = _pageNumberForRam(idx, 0);
|
|
}
|
|
}
|
|
|
|
if (auxRamWrite) {
|
|
for (uint8_t idx = 0x02; idx < 0xc0; idx++) {
|
|
writePages[idx] = _pageNumberForRam(idx, 1);
|
|
}
|
|
} else {
|
|
for (uint8_t idx = 0x02; idx < 0xc0; idx++) {
|
|
writePages[idx] = _pageNumberForRam(idx, 0);
|
|
}
|
|
}
|
|
|
|
if (switches & S_80STORE) {
|
|
// When S_80STORE is on, we switch 400-800 and 2000-4000 based on S_PAGE2.
|
|
// The behavior is different based on whether HIRESON/OFF is set.
|
|
if (switches & S_PAGE2) {
|
|
// Regardless of HIRESON/OFF, pages 0x400-0x7ff are switched on S_PAGE2
|
|
for (uint8_t idx = 0x04; idx < 0x08; idx++) {
|
|
readPages[idx] = writePages[idx] = _pageNumberForRam(idx, 1);
|
|
}
|
|
|
|
// but 2000-3fff switches based on S_PAGE2 only if HIRES is on.
|
|
|
|
// HIRESOFF: 400-7ff doesn't switch based on read/write flags
|
|
// b/c it switches based on S_PAGE2 instead
|
|
// HIRESON: 400-800, 2000-3fff doesn't switch
|
|
// b/c they switch based on S_PAGE2 instead
|
|
|
|
// If HIRES is on, then we honor the PAGE2 setting; otherwise, we don't
|
|
for (uint8_t idx = 0x20; idx < 0x40; idx++) {
|
|
readPages[idx] = writePages[idx] = _pageNumberForRam(idx, (switches & S_HIRES) ? 1 : 0);
|
|
}
|
|
} else {
|
|
for (uint8_t idx = 0x04; idx < 0x08; idx++) {
|
|
readPages[idx] = writePages[idx] = _pageNumberForRam(idx, 0);
|
|
}
|
|
for (uint8_t idx = 0x20; idx < 0x40; idx++) {
|
|
readPages[idx] = writePages[idx] = _pageNumberForRam(idx, 0);
|
|
}
|
|
}
|
|
}
|
|
|
|
if (intcxrom) {
|
|
for (uint8_t idx = 0xc1; idx < 0xd0; idx++) {
|
|
readPages[idx] = _pageNumberForRam(idx, 1);
|
|
}
|
|
} else {
|
|
for (uint8_t idx = 0xc1; idx < 0xd0; idx++) {
|
|
readPages[idx] = _pageNumberForRam(idx, 0);
|
|
}
|
|
if (slot3rom) {
|
|
readPages[0xc3] = _pageNumberForRam(0xc3, 1);
|
|
for (int i=0xc8; i<=0xcf; i++) {
|
|
readPages[i] = _pageNumberForRam(i, 1);
|
|
}
|
|
}
|
|
}
|
|
|
|
// If slotLatch is set (!= -1), then we are mapping 2k of ROM
|
|
// for a given peripheral to C800..CFFF.
|
|
if (slotLatch != -1) {
|
|
// FIXME: the only peripheral we support this with right now is
|
|
// the 80-column card.
|
|
if (slotLatch == 3) {
|
|
for (int i=0xc8; i <= 0xcf; i++) {
|
|
readPages[i] = _pageNumberForRam(i, 1);
|
|
}
|
|
}
|
|
}
|
|
|
|
// set zero-page & stack pages based on altzp flag
|
|
if (altzp) {
|
|
for (uint8_t idx = 0x00; idx < 0x02; idx++) {
|
|
readPages[idx] = writePages[idx] = _pageNumberForRam(idx, 1);
|
|
}
|
|
} else {
|
|
for (uint8_t idx = 0x00; idx < 0x02; idx++) {
|
|
readPages[idx] = writePages[idx] = _pageNumberForRam(idx, 0);
|
|
}
|
|
}
|
|
|
|
// Set bank-switched ram reading from readbsr & bank2
|
|
if (readbsr) {
|
|
// 0xD0 - 0xE0 has 4 possible banks:
|
|
if (!bank2) {
|
|
// Bank 1 RAM: either in main RAM (1) or in the extended memory
|
|
// card (3):
|
|
for (uint8_t idx = 0xd0; idx < 0xe0; idx++) {
|
|
readPages[idx] = _pageNumberForRam(idx, altzp ? 3 : 1);
|
|
}
|
|
} else {
|
|
// Bank 2 RAM: either in main RAM (2) or in the extended memory
|
|
// card (4):
|
|
for (uint8_t idx = 0xd0; idx < 0xe0; idx++) {
|
|
readPages[idx] = _pageNumberForRam(idx, altzp ? 4 : 2);
|
|
}
|
|
}
|
|
// ... but 0xE0 - 0xFF has just the motherboard RAM (1) and
|
|
// extended memory card RAM (2):
|
|
for (uint16_t idx = 0xe0; idx < 0x100; idx++) {
|
|
readPages[idx] = _pageNumberForRam(idx, altzp ? 2 : 1);
|
|
}
|
|
} else {
|
|
// Built-in ROM
|
|
for (uint16_t idx = 0xd0; idx < 0x100; idx++) {
|
|
readPages[idx] = _pageNumberForRam(idx, 0);
|
|
}
|
|
}
|
|
|
|
if (writebsr) {
|
|
if (!bank2) {
|
|
for (uint8_t idx = 0xd0; idx < 0xe0; idx++) {
|
|
writePages[idx] = _pageNumberForRam(idx, altzp ? 3 : 1);
|
|
}
|
|
} else {
|
|
for (uint8_t idx = 0xd0; idx < 0xe0; idx++) {
|
|
writePages[idx] = _pageNumberForRam(idx, altzp ? 4 : 2);
|
|
}
|
|
}
|
|
for (uint16_t idx = 0xe0; idx < 0x100; idx++) {
|
|
writePages[idx] = _pageNumberForRam(idx, altzp ? 2 : 1);
|
|
}
|
|
} else {
|
|
for (uint16_t idx = 0xd0; idx < 0x100; idx++) {
|
|
writePages[idx] = _pageNumberForRam(idx, 0);
|
|
}
|
|
}
|
|
}
|
|
|
|
void AppleMMU::setAppleKey(int8_t which, bool isDown)
|
|
{
|
|
assert(which <= 1);
|
|
g_ram.writeByte((writePages[0xC0] << 8) | (0x61 + which), isDown ? 0x80 : 0x00);
|
|
}
|