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* New BIOS interface * New linux framebuffer version * Unified linuxfb and SDL with Teensy * Abstracted VM RAM * Fixed disk image corruption due to bad cache handling * Variable CPU speed support
219 lines
5.0 KiB
C++
219 lines
5.0 KiB
C++
#include "parallelsram.h"
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// Assumes any Output Enable pin is hardwired-enabled;
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// any Chip Enable pin is hardwared-enabled.
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//
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// Uses the low 8 bits of Port D as I/O lines (2, 14, 7, 8, 6, 20, 21, 5).
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//
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// R/W (aka WriteEnable) is on pin 31.
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#define RAM_RW 34
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// The Address pins (19 of them). It would be nice to have these
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// easily bitwise-manipulable, instead of having to set each bit
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// individually.
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//
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// We can use 12 bits of Port C: 15, 22, 23, 9, 10, 13, 11, 12, 35, 36, 37, 38
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// And then 6 bits of Port B: 16 17 19 18 49 50
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//
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// And hard wire one bit low (we don't need all 19 lines). That gets us
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// 256 Kb of RAM which should be sufficient.
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static uint8_t addrPins[] = { 15, 22, 23, 9, 10, 13, 11, 12, 35, 36, 37, 38,
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16, 17, 19, 18, 49, 50
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};
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#if 0
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#define DELAY { delayMicroseconds(1); /* overkill, but useful for debugging */ }
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#else
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#define DELAY { __asm__ volatile ("nop"); __asm__ volatile ("nop"); \
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__asm__ volatile ("nop"); __asm__ volatile ("nop"); \
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__asm__ volatile ("nop"); __asm__ volatile ("nop"); \
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__asm__ volatile ("nop"); __asm__ volatile ("nop"); \
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}
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#endif
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#define OE_ON { /*if (noe != 255) {digitalWrite(noe, LOW);}*/ }
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#define OE_OFF { /*if (noe != 255) {digitalWrite(noe, HIGH);}*/ }
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#define CE_ON { /*if (n_ce != 255) {digitalWrite(n_ce, LOW);} if (p_ce != 255) { digitalWrite(p_ce, HIGH); }*/ }
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#define CE_OFF { /*if (n_ce != 255) {digitalWrite(n_ce, HIGH);} if (p_ce != 255) { digitalWrite(p_ce, LOW); }*/ }
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#define WE_ON { digitalWriteFast(RAM_RW, LOW); }
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#define WE_OFF { digitalWriteFast(RAM_RW, HIGH); }
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ParallelSRAM::ParallelSRAM()
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{
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pinMode(RAM_RW, OUTPUT);
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// Port D is our I/O port. Use the AVR emulation layer to set up the
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// pins once, and then we'll just fiddle with the DDR, input, and
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// output directly.
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// Enable it as a digital port...
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// SIM_SCGC5 |= SIM_SCGC5_PORTD;
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//... what else? How do we set PORTD_PCR[0-7]?
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pinMode(2, INPUT);
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pinMode(14, INPUT);
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pinMode(7, INPUT);
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pinMode(8, INPUT);
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pinMode(6, INPUT);
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pinMode(20, INPUT);
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pinMode(21, INPUT);
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pinMode(5, INPUT);
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isInput = true;
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// Set up the address pins
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for (int i=0; i<sizeof(addrPins); i++) {
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pinMode(addrPins[i], INPUT); // disable pull-ups
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pinMode(addrPins[i], OUTPUT);
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digitalWrite(addrPins[i], LOW);
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}
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}
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void ParallelSRAM::SetPins()
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{
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pinMode(RAM_RW, OUTPUT);
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// Port D is our I/O port. Use the AVR emulation layer to set up the
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// pins once, and then we'll just fiddle with the DDR, input, and
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// output directly.
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// Enable it as a digital port...
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// SIM_SCGC5 |= SIM_SCGC5_PORTD;
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//... what else? How do we set PORTD_PCR[0-7]?
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pinMode(2, INPUT);
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pinMode(14, INPUT);
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pinMode(7, INPUT);
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pinMode(8, INPUT);
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pinMode(6, INPUT);
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pinMode(20, INPUT);
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pinMode(21, INPUT);
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pinMode(5, INPUT);
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isInput = true;
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// Set up the address pins
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for (int i=0; i<sizeof(addrPins); i++) {
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pinMode(addrPins[i], INPUT); // disable pull-ups
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pinMode(addrPins[i], OUTPUT);
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digitalWrite(addrPins[i], LOW);
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}
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}
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ParallelSRAM::~ParallelSRAM()
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{
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}
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uint8_t ParallelSRAM::read(uint32_t addr)
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{
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cli();
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// Read cycle 2
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setAddress(addr);
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// make sure address is valid before CE is asserted
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DELAY;
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CE_ON;
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OE_ON;
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DELAY;
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uint8_t ret = getInput();
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// Optional; can leave these lines asserted...
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OE_OFF;
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CE_OFF;
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sei();
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return ret;
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}
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void ParallelSRAM::write(uint32_t addr, uint8_t v)
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{
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cli();
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setAddress(addr);
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DELAY;
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WE_ON;
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CE_ON;
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setOutput(v);
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DELAY;
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CE_OFF;
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WE_OFF;
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sei();
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}
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uint8_t ParallelSRAM::getInput()
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{
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if (!isInput) {
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#if 1
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// Directly set the direction bits. The rest of the port setup
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// should be fine from the initial config.
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*(volatile uint8_t *)(&GPIOD_PDDR) = 0x00; // inputs
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#else
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pinMode(2, INPUT);
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pinMode(14, INPUT);
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pinMode(7, INPUT);
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pinMode(8, INPUT);
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pinMode(6, INPUT);
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pinMode(20, INPUT);
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pinMode(21, INPUT);
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pinMode(5, INPUT);
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#endif
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isInput = true;
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}
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return GPIOD_PDIR & 0xFF;
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}
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void ParallelSRAM::setOutput(uint8_t v)
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{
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// FIXME: is there a faster way to do this?
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if (isInput) {
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#if 1
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// FIMXE: would this be correct?
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*(volatile uint8_t *)(&GPIOD_PDDR) |= 0xFF; // outputs
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#else
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pinMode(2, OUTPUT);
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pinMode(14, OUTPUT);
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pinMode(7, OUTPUT);
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pinMode(8, OUTPUT);
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pinMode(6, OUTPUT);
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pinMode(20, OUTPUT);
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pinMode(21, OUTPUT);
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pinMode(5, OUTPUT);
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#endif
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isInput = false;
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}
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// Directly set the low 8 bits of D.
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*(volatile uint8_t *)(&GPIOD_PDOR) = v;
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}
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void ParallelSRAM::setAddress(uint32_t addr)
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{
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// The low 12 bits of the address go right in to Port C. Set these
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// by doing a clear of the bitmask, and then set the bits...
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GPIOC_PCOR = 0x00000FFF;
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GPIOC_PSOR = (addr & 0xFFF);
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// The high 6 bits of the address go in to Port B, bits 0..5.
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// We do that the same way...
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GPIOB_PCOR = 0x0000003F;
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GPIOB_PSOR = (addr >> 12);
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#if 0
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for (uint8_t i=0; i<sizeof(addrPins); i++) {
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digitalWrite(addrPins[i],
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addr & (1 << i) ? HIGH : LOW);
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}
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#endif
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}
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