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analog-firmware
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Timing tweaks

This commit is contained in:
David Kuder 2023-05-04 23:43:57 -04:00
parent 4bff5c15b5
commit a82b03e631
2 changed files with 32 additions and 32 deletions
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20
common/abus-4ns.pio
View File

@ -31,15 +31,15 @@ next_bus_cycle:
jmp PIN, read_cycle ; jump based on the state of the R/W pin
write_cycle:
; the current time is P0+88ns (P0 + 10ns + 2 clocks (input synchronizers) + 20 instructions)
; the current time is P0+92ns (P0 + 10ns + 2 clocks (input synchronizers) + 21 instructions)
set PINS, 0b110 [31] ; enable Data tranceiver & wait until both ~DEVSEL and the written data are valid (P0+216ns)
set PINS, 0b110 [31] ; enable Data tranceiver & wait until both ~DEVSEL and the written data are valid (P0+220ns)
in PINS, 10 ; read R/W, ~DEVSEL, and Data[7:0], then autopush
wait 0 GPIO, PHI0_GPIO [7] ; wait for PHI0 to fall
jmp next_bus_cycle
read_cycle:
; the current time is P0+82ns (P0 + 10ns + 2 clocks (input synchronizers) + 16 instructions)
; the current time is P0+92ns (P0 + 10ns + 2 clocks (input synchronizers) + 21 instructions)
set PINS, 0b110 [5] ; ensure AddrLo transceiver is disabled and delay for ~DEVSEL to become valid (P0+102ns+buffer delay)
in PINS, 10 ; read R/W, ~DEVSEL, and dontcare[7:0], then autopush
@ -66,7 +66,7 @@ wait_loop:
wait 1 irq READ_DATA_TRIGGER_IRQ ; wait for the data portion of a read cycle (from the main SM)
jmp PIN, wait_loop ; skip if this device is not being addressed
; the current time is P0+130ns and
; the current time is P0+128ns and
; this read cycle is addressed to this device.
;
; Phase 0 is typically 489 ns long.
@ -76,14 +76,14 @@ wait_loop:
irq set DATA_BUSY_IRQ
set PINS, 0b01 [7] ; enable Data tranceiver with output direction [P0+162ns]
mov OSR, ~NULL [31] ; [P0+290ns]
out PINDIRS, 8 [31] ; set data pins as outputs [P0+418ns]
set PINS, 0b01 [7] ; enable Data tranceiver with output direction [P0+164ns]
mov OSR, ~NULL [31] ; [P0+292ns]
out PINDIRS, 8 [31] ; set data pins as outputs [P0+420ns]
pull noblock ; pull value from the FIFO as late as possible [P0+422ns]
out PINS, 8 ; [P0+426ns]
pull noblock ; pull value from the FIFO as late as possible [P0+424ns]
out PINS, 8 ; [P0+428ns]
; the current time is P0+426ns
; the current time is P0+428ns
wait 0 GPIO, PHI0_GPIO [2] ; wait for PHI0 to fall then hold for 12ns (2 clocks (input synchronizers) + 7 instructions)
set PINS, 0b10 ; disable Data tranceiver to tri-state the data bus

44
common/abus-8ns.pio
View File

@ -12,7 +12,7 @@
; * IN pins are mapped to ~DEVSEL, R/W, and Data[7:0]
; * SET pins are mapped to the transceiver enable signals
; * input shift left & autopush @ 26 bits
; * run at about 125MHz (8ns/instruction)
; * run at about 250MHz (4ns/instruction)
;
; SET bits for tranceiver control:
; 0bxxx
@ -21,31 +21,31 @@
; x - select Data, active low
.wrap_target
next_bus_cycle:
set PINS, 0b011 ; enable AddrHi tranceiver
wait 1 GPIO, PHI0_GPIO ; wait for PHI0 to rise. Data propagation through the transceiver should
; be complete by the time this happens.
set PINS, 0b011 ; disable tranceivers
wait 1 GPIO, PHI0_GPIO [2] ; wait for PHI0 to rise.
set PINS, 0b011 [2] ; enable AddrHi tranceiver and delay for transceiver propagation delay (24ns)
in PINS, 8 ; read AddrHi[7:0]
set PINS, 0b101 [2] ; enable AddrLo tranceiver and delay for transceiver propagation delay
set PINS, 0b101 [2] ; enable AddrLo tranceiver and delay for transceiver propagation delay (24ns)
in PINS, 8 ; read AddrLo[7:0]
jmp PIN, read_cycle ; jump based on the state of the R/W pin
write_cycle:
; the current time is P0+88ns (P0 + 16ns + 2 clocks (input synchronizers) + 7 instructions)
; the current time is P0+98ns (P0 + 10ns + 2 clocks (input synchronizers) + 11 instructions)
set PINS, 0b110 [15] ; enable Data tranceiver & wait until both ~DEVSEL and the written data are valid (P0+200ns)
set PINS, 0b110 [31] ; enable Data tranceiver & wait until both ~DEVSEL and the written data are valid (P0+216ns)
in PINS, 10 ; read R/W, ~DEVSEL, and Data[7:0], then autopush
wait 0 GPIO, PHI0_GPIO [7] ; wait for PHI0 to fall
wait 0 GPIO, PHI0_GPIO [3] ; wait for PHI0 to fall
jmp next_bus_cycle
read_cycle:
; the current time is P0+88ns (P0 + 16ns + 2 clocks (input synchronizers) + 7 instructions)
; the current time is P0+98ns (P0 + 10ns + 2 clocks (input synchronizers) + 11 instructions)
set PINS, 0b110 ; ensure AddrLo transceiver is disabled and delay for ~DEVSEL to become valid (P0+63ns+buffer delay)
set PINS, 0b110 [2] ; ensure AddrLo transceiver is disabled and delay for ~DEVSEL to become valid (P0+102ns+buffer delay)
in PINS, 10 ; read R/W, ~DEVSEL, and dontcare[7:0], then autopush
irq set READ_DATA_TRIGGER_IRQ ; trigger the data read state machine to put data on the data bus
wait 0 GPIO, PHI0_GPIO [7] ; wait for PHI0 to fall
wait 0 GPIO, PHI0_GPIO [3] ; wait for PHI0 to fall
wait 0 irq DATA_BUSY_IRQ ; wait for the data handling state machine to complete to avoid contention w/transceiver control
.wrap
@ -66,32 +66,32 @@ wait_loop:
wait 1 irq READ_DATA_TRIGGER_IRQ ; wait for the data portion of a read cycle (from the main SM)
jmp PIN, wait_loop ; skip if this device is not being addressed
; the current time is P0+136ns (P0 + 16ns + 2 clocks (input synchronizers) + 13 instructions) and
; the current time is P0+138ns and
; this read cycle is addressed to this device.
;
; Phase 0 is typically 489 ns long.
; * Data from peripherals should be valid on the data bus by 45 nanoseconds before the end of phase 0
; * Data should be held for 40ns after phase 0 ends
; * Data bus should be tri-stated within 60ns after phase 0 ends
; * Data should be held for no more than 20ns after phase 0 ends
; * Data bus should be tri-stated within 30ns after phase 0 ends
irq set DATA_BUSY_IRQ
set PINS, 0b01 ; enable Data tranceiver with output direction
mov OSR, ~NULL [4]
out PINDIRS, 8 [31] ; set data pins as outputs
set PINS, 0b01 [3] ; enable Data tranceiver with output direction [P0+178ns]
mov OSR, ~NULL [15] ; [P0+306ns]
out PINDIRS, 8 [15] ; set data pins as outputs [P0+434ns]
pull noblock ; pull value from the FIFO as late as possible
out PINS, 8
pull noblock ; pull value from the FIFO as late as possible [P0+442ns]
out PINS, 8 ; [P0+450ns]
; the current time is P0+440ns (P0 + 16ns + 2 clocks (input synchronizers) + 51 instructions)
; the current time is P0+450ns
wait 0 GPIO, PHI0_GPIO [2] ; wait for PHI0 to fall then hold for 40ns (2 clocks (input synchronizers) + 2-3 instructions)
wait 0 GPIO, PHI0_GPIO [1] ; wait for PHI0 to fall then hold for 16ns (2 clocks (input synchronizers) + 7 instructions)
set PINS, 0b10 ; disable Data tranceiver to tri-state the data bus
mov OSR, NULL
out PINDIRS, 8 ; reset data pins as inputs
pull noblock ; extra late pull to clear out any standing values from the FIFO
pull noblock ; extra late pull to clear out any standing values from the FIFO [P1+56ns]
irq clear DATA_BUSY_IRQ
.wrap