Even with overclocking SHR pushes the limits of the RP2040 if it has to bit-shift the 12-bit RGB to 9-bit RGB. May investigate using the hardware math acceleration to re-enable this at a later time.
due to how the PIO program counter operates, the pixel holds are also used to shift the active area after a HSYNC. the larger values of pixel holds caused problems and had to be removed.
Bypass legacy 80 column card when in SHR rendering mode
Mask unused palette bits that were causing VGA PIO to fail
Fixed color calculation for AGS hardware
This changeset improves the horizontal resolution of the color DHGR rendering and fixes double-lores rendering. HGR rendering has been rewritten to match the new DHGR rendering. DHGR, HGR and DGR modes now have a horizontal stippling effect applied.
The DHGR & HGR changes can be reverted at runtime with bit 3 of the $C0n1 register.
