100 lines
4.3 KiB
Plaintext
100 lines
4.3 KiB
Plaintext
.define public PHI0_GPIO 14
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.define READ_DATA_TRIGGER_IRQ 4
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.define DATA_BUSY_IRQ 5
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; Apple II bus interface
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; Ref: Understanding the Apple II, pages 4-7, 7-8
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.program abus
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; Prerequisites:
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; * Bus clock used is PHI0, wired to GPIO 26
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; * JMP pin is mapped to the R/W signal
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; * IN pins are mapped to ~DEVSEL, R/W, and Data[7:0]
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; * SET pins are mapped to the transceiver enable signals
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; * input shift left & autopush @ 26 bits
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; * run at about 250MHz (4ns/instruction)
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;
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; SET bits for tranceiver control:
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; 0bxxx
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; x - select AddrHi, active low
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; x - select AddrLo, active low
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; x - select Data, active low
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.wrap_target
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next_bus_cycle:
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set PINS, 0b111 ; enable CPLD OE
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wait 1 GPIO, PHI0_GPIO [4] ; wait for PHI0 to rise. Data propagation through the transceiver should
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; be complete by the time this happens.
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in PINS, 6 ; read CPLD[5:0]
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set PINS, 0b011 [5] ; enable AddrHi tranceiver
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in PINS, 8 ; read AddrHi[7:0]
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set PINS, 0b101 [5] ; enable AddrLo tranceiver and delay for transceiver propagation delay
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in PINS, 8 ; read AddrLo[7:0]
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jmp PIN, read_cycle ; jump based on the state of the R/W pin
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write_cycle:
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; the current time is P0+98ns (P0 + 10ns + 2 clocks (input synchronizers) + 20 instructions)
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set PINS, 0b110 [17] ; enable Data tranceiver & wait until both ~DEVSEL and the written data are valid (P0+170ns)
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in PINS, 10 ; read R/W, ~DEVSEL, and Data[7:0], then autopush
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wait 0 GPIO, PHI0_GPIO [7] ; wait for PHI0 to fall
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jmp next_bus_cycle
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read_cycle:
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; the current time is P0+98ns (P0 + 10ns + 2 clocks (input synchronizers) + 16 instructions)
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set PINS, 0b110 [5] ; ensure AddrLo transceiver is disabled and delay for ~DEVSEL to become valid (P0+118ns)
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in PINS, 10 ; read R/W, ~DEVSEL, and dontcare[7:0], then autopush
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irq set READ_DATA_TRIGGER_IRQ ; trigger the data read state machine to put data on the data bus
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wait 0 GPIO, PHI0_GPIO [7] ; wait for PHI0 to fall
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wait 0 irq DATA_BUSY_IRQ ; wait for the data handling state machine to complete to avoid contention w/transceiver control
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.wrap
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.program abus_device_read
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; Prerequisites:
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; * Bus clock used is PHI0, wired to GPIO 26
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; * JMP pin is the ~DEVSEL signal
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; * OUT pins are the 8 data signals
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; * SET pins are the Data transceiver control signals
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;
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; SET bits for tranceiver control:
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; 0bxx
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; x - select Data transceiver (active low)
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; x - Data transceiver direction (0=input, 1=output)
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.wrap_target
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wait_loop:
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wait 1 irq READ_DATA_TRIGGER_IRQ ; wait for the data portion of a read cycle (from the main SM)
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jmp PIN, wait_loop ; skip if this device is not being addressed
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; the current time is P0+130ns and
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; this read cycle is addressed to this device.
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;
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; Phase 0 is typically 489 ns long.
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; * Data from peripherals should be valid on the data bus by 45 nanoseconds before the end of phase 0
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; * Data should be held for no more than 20ns after phase 0 ends
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; * Data bus should be tri-stated within 30ns after phase 0 ends
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irq set DATA_BUSY_IRQ
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set PINS, 0b01 [7] ; enable Data tranceiver with output direction [P0+162ns]
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mov OSR, ~NULL [31] ; [P0+290ns]
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out PINDIRS, 8 [31] ; set data pins as outputs [P0+418ns]
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pull noblock ; pull value from the FIFO as late as possible [P0+422ns]
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out PINS, 8 ; [P0+426ns]
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; the current time is P0+426ns
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wait 0 GPIO, PHI0_GPIO [2] ; wait for PHI0 to fall then hold for 12ns (2 clocks (input synchronizers) + 7 instructions)
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set PINS, 0b10 ; disable Data tranceiver to tri-state the data bus
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mov OSR, NULL
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out PINDIRS, 8 ; reset data pins as inputs
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pull noblock ; extra late pull to clear out any standing values from the FIFO [P1+56ns]
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irq clear DATA_BUSY_IRQ
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.wrap
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