101 lines
3.4 KiB
C
101 lines
3.4 KiB
C
#include <string.h>
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#include <hardware/pio.h>
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#include "common/config.h"
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#include "common/abus.h"
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#ifdef OVERCLOCKED
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#ifdef ANALOG_GS
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#include "abus-gs-4ns.pio.h"
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#else
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#include "abus-4ns.pio.h"
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#endif
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#else
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#ifdef ANALOG_GS
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#include "abus-gs-8ns.pio.h"
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#else
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#include "abus-8ns.pio.h"
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#endif
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#endif
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#if CONFIG_PIN_APPLEBUS_PHI0 != PHI0_GPIO
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#error CONFIG_PIN_APPLEBUS_PHI0 and PHI0_GPIO must be set to the same pin
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#endif
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static void abus_device_read_setup(PIO pio, uint sm) {
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uint program_offset = pio_add_program(pio, &abus_device_read_program);
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pio_sm_claim(pio, sm);
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pio_sm_config c = abus_device_read_program_get_default_config(program_offset);
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// set the "device selected" pin as the jump pin
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sm_config_set_jmp_pin(&c, CONFIG_PIN_APPLEBUS_DEVSEL);
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// map the OUT pin group to the data signals
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sm_config_set_out_pins(&c, CONFIG_PIN_APPLEBUS_DATA_BASE, 8);
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// map the SET pin group to the Data transceiver control signals
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sm_config_set_set_pins(&c, CONFIG_PIN_APPLEBUS_CONTROL_BASE, 2);
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pio_sm_init(pio, sm, program_offset, &c);
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// All the GPIOs are shared and setup by the main program
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}
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static void abus_main_setup(PIO pio, uint sm) {
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uint program_offset = pio_add_program(pio, &abus_program);
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pio_sm_claim(pio, sm);
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pio_sm_config c = abus_program_get_default_config(program_offset);
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// set the bus R/W pin as the jump pin
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sm_config_set_jmp_pin(&c, CONFIG_PIN_APPLEBUS_RW);
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// map the IN pin group to the data signals
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sm_config_set_in_pins(&c, CONFIG_PIN_APPLEBUS_DATA_BASE);
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// map the SET pin group to the bus transceiver enable signals
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sm_config_set_set_pins(&c, CONFIG_PIN_APPLEBUS_CONTROL_BASE+1, 3);
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#ifdef ANALOG_GS
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// configure left shift into ISR & autopush every 32 bits
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sm_config_set_in_shift(&c, false, true, 32);
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#else
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// configure left shift into ISR & autopush every 26 bits
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sm_config_set_in_shift(&c, false, true, 26);
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#endif
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pio_sm_init(pio, sm, program_offset, &c);
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// configure the GPIOs
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// Ensure all transceivers will start disabled, with Data transceiver direction set to 'in'
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pio_sm_set_pins_with_mask(pio, sm,
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(uint32_t)0xe << CONFIG_PIN_APPLEBUS_CONTROL_BASE,
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(uint32_t)0xf << CONFIG_PIN_APPLEBUS_CONTROL_BASE);
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pio_sm_set_pindirs_with_mask(pio, sm,
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(0xf << CONFIG_PIN_APPLEBUS_CONTROL_BASE),
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(1 << CONFIG_PIN_APPLEBUS_PHI0) | (0xf << CONFIG_PIN_APPLEBUS_CONTROL_BASE) | (0x3ff << CONFIG_PIN_APPLEBUS_DATA_BASE));
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// Disable input synchronization on input pins that are sampled at known stable times
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// to shave off two clock cycles of input latency
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pio->input_sync_bypass |= (0x3ff << CONFIG_PIN_APPLEBUS_DATA_BASE);
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pio_gpio_init(pio, CONFIG_PIN_APPLEBUS_PHI0);
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gpio_set_pulls(CONFIG_PIN_APPLEBUS_PHI0, false, false);
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for(int pin=CONFIG_PIN_APPLEBUS_CONTROL_BASE; pin < CONFIG_PIN_APPLEBUS_CONTROL_BASE+4; pin++) {
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pio_gpio_init(pio, pin);
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}
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for(int pin=CONFIG_PIN_APPLEBUS_DATA_BASE; pin < CONFIG_PIN_APPLEBUS_DATA_BASE+10; pin++) {
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pio_gpio_init(pio, pin);
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gpio_set_pulls(pin, false, false);
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}
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}
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void abus_init() {
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abus_device_read_setup(CONFIG_ABUS_PIO, ABUS_DEVICE_READ_SM);
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abus_main_setup(CONFIG_ABUS_PIO, ABUS_MAIN_SM);
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pio_enable_sm_mask_in_sync(CONFIG_ABUS_PIO, (1 << ABUS_MAIN_SM) | (1 << ABUS_DEVICE_READ_SM));
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}
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