122 lines
3.6 KiB
C
122 lines
3.6 KiB
C
#include <string.h>
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#include <hardware/pio.h>
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#include "common/config.h"
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#include "common/buffers.h"
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#include "common/abus.h"
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#include "z80/businterface.h"
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#include "z80/z80buf.h"
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volatile uint8_t *pcpi_reg = apple_memory + 0xC0C0;
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static inline void __time_critical_func(pcpi_read)(uint32_t address) {
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switch(address & 0xF) {
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case 0x0: // Read Data from Z80
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clr_6502_stat;
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break;
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case 0x5: // Z80 Reset
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z80_res = 1;
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break;
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case 0x6: // Z80 INT
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//z80_irq = 1;
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break;
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case 0x7: // Z80 NMI
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z80_nmi = 1;
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break;
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case 0x8: // 6551 A Data Register
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pcpi_reg[0x08] = auart_read(0);
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pcpi_reg[0x09] = auart_status(0);
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break;
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case 0x9: // 6551 A Status Register
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pcpi_reg[0x08] = zuart_peek(0);
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pcpi_reg[0x09] = auart_status(0);
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break;
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case 0xA: // 6551 A Command Register
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break;
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case 0xB: // 6551 A Control Register
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break;
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case 0xC: // 6551 B Data Register
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pcpi_reg[0x0C] = auart_read(1);
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pcpi_reg[0x0D] = auart_status(1);
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break;
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case 0xD: // 6551 B Status Register
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pcpi_reg[0x0C] = zuart_peek(1);
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pcpi_reg[0x0D] = auart_status(1);
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break;
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case 0xE: // 6551 B Command Register
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break;
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case 0xF: // 6551 B Control Register
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break;
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}
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}
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static inline void __time_critical_func(pcpi_write)(uint32_t address, uint32_t value) {
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switch(address & 0xF) {
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case 0x1: // Write Data to Z80
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pcpi_reg[1] = value & 0xff;
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set_z80_stat;
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break;
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case 0x5: // Z80 Reset
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case 0x6: // Z80 INT
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case 0x7: // Z80 NMI
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pcpi_read(address);
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break;
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case 0x8: // 6551 A Data Register
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zuart_write(0, value);
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pcpi_reg[0x08] = zuart_peek(0);
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pcpi_reg[0x09] = auart_status(0);
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break;
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case 0x9: // 6551 A Reset Register
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pcpi_reg[0x08] = zuart_peek(0);
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pcpi_reg[0x09] = auart_status(0);
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break;
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case 0xA: // 6551 A Command Register
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pcpi_reg[0x0A] = auart_command(0, value);
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break;
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case 0xB: // 6551 A Control Register
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pcpi_reg[0x0B] = auart_control(0, value);
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break;
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case 0xC: // 6551 B Data Register
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zuart_write(1, value);
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pcpi_reg[0x0C] = zuart_peek(1);
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pcpi_reg[0x0D] = auart_status(1);
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break;
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case 0xD: // 6551 B Reset Register
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pcpi_reg[0x0C] = zuart_peek(1);
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pcpi_reg[0x0D] = auart_status(1);
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break;
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case 0xE: // 6551 B Command Register
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pcpi_reg[0x0E] = auart_command(1, value);
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break;
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case 0xF: // 6551 B Control Register
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pcpi_reg[0x0F] = auart_control(1, value);
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break;
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}
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}
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void __time_critical_func(z80_businterface)(uint32_t address, uint32_t value) {
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volatile uint8_t *new_pcpi_reg;
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// Reset the Z80 when the Apple II resets
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if(reset_state == 3) z80_res = 1;
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// Shadow parts of the Apple's memory by observing the bus write cycles
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if(CARD_SELECT) {
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if(CARD_DEVSEL) {
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// Ideally this code should only run once.
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new_pcpi_reg = apple_memory + (address & 0xFFF0);
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if((uint32_t)new_pcpi_reg != (uint32_t)pcpi_reg) {
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memcpy((void*)new_pcpi_reg, (void*)pcpi_reg, 16);
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pcpi_reg = new_pcpi_reg;
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}
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if((value & (1u << CONFIG_PIN_APPLEBUS_RW-CONFIG_PIN_APPLEBUS_DATA_BASE)) == 0) {
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pcpi_write(address, value);
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} else {
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pcpi_read(address);
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}
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}
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}
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}
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