396 lines
10 KiB
C
396 lines
10 KiB
C
#include <pico/stdlib.h>
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#include <pico/multicore.h>
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#include "common/config.h"
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#include "z80/businterface.h"
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#include "z80/z80buf.h"
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#include "z80/z80rom.h"
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#include "bsp/board.h"
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#include "tusb.h"
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// Used to ensure we interrupt the Z80 loop every 256 instructions
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volatile uint8_t z80_cycle;
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volatile uint32_t z80_vect = 0x000000;
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volatile uint8_t __attribute__((section(".uninitialized_data."))) z80_irq;
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volatile uint8_t __attribute__((section(".uninitialized_data."))) z80_nmi;
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volatile uint8_t __attribute__((section(".uninitialized_data."))) z80_res;
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volatile uint8_t __attribute__((section(".uninitialized_data."))) rom_shadow;
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volatile uint8_t __attribute__((section(".uninitialized_data."))) ram_bank;
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volatile uint8_t __attribute__((section(".uninitialized_data."))) ram_common;
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volatile ctc_t ctc[4];
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volatile uint8_t ctc_vector;
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volatile sio_t sio[2];
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volatile uint8_t sio_vector;
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#define Z80break (z80_res || (config_cmdbuf[7] == 0) || (!z80_cycle++))
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uint8_t DELAYED_COPY_CODE(zuart_read)(bool port) {
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uint8_t rv = 0;
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if(sio[port].datavalid) {
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rv = sio[port].data;
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sio[port].datavalid = 0;
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}
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switch(serialmux[port]) {
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default:
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case SERIAL_LOOP:
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break;
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case SERIAL_USB:
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if(tud_cdc_n_available(port)) {
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sio[port].data = tud_cdc_n_read_char(port);
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sio[port].datavalid = 1;
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}
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break;
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#ifdef ANALOG_GS
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case SERIAL_UART:
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if(port) {
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if(uart_is_readable(uart1)) {
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sio[port].data = uart_getc(uart1);
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sio[port].datavalid = 1;
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}
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} else {
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if(uart_is_readable(uart0)) {
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sio[port].data = uart_getc(uart0);
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sio[port].datavalid = 1;
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}
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}
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break;
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#endif
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}
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return rv;
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}
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uint8_t DELAYED_COPY_CODE(zuart_peek)(bool port) {
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uint8_t rv = 0;
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if(sio[port].datavalid) {
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rv = sio[port].data;
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}
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return rv;
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}
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uint8_t DELAYED_COPY_CODE(auart_read)(bool port) {
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zuart_read(port);
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return zuart_peek(port);
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}
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uint8_t DELAYED_COPY_CODE(auart_status)(bool port) {
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uint8_t rv;
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if(!sio[port].datavalid) {
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zuart_read(port);
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}
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rv = sio[port].datavalid ? 0x08 : 0x00;
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switch(serialmux[port]) {
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default:
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case SERIAL_LOOP:
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rv |= ((sio[port].control[5] & 0x02) ? 0x40 : 0x00) |
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((sio[port].control[5] & 0x80) ? 0x20 : 0x00) |
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(sio[port].datavalid ? 0x00 : 0x10);
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break;
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case SERIAL_USB:
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rv |= ((tud_cdc_n_get_line_state(port) & 2) ? 0x00 : 0x40) |
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(tud_cdc_n_connected(port) ? 0x00 : 0x20) |
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(tud_cdc_n_write_available(port) ? 0x10 : 0x00);
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break;
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#ifdef ANALOG_GS
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case SERIAL_UART:
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if(port) {
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rv |= (uart_is_writable(uart1) ? 0x10 : 0x00);
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} else {
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rv |= (uart_is_writable(uart0) ? 0x10 : 0x00);
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}
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break;
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#endif
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}
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return rv;
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}
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uint8_t DELAYED_COPY_CODE(auart_control)(bool port, uint8_t value) {
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return value;
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}
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uint8_t DELAYED_COPY_CODE(auart_command)(bool port, uint8_t value) {
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if(value & 0x1) {
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sio[port].control[5] |= 0x80;
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} else {
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sio[port].control[5] &= ~0x80;
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}
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if(value & 0xC) {
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sio[port].control[5] |= 0x02;
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} else {
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sio[port].control[5] &= ~0x02;
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}
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return value;
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}
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uint8_t DELAYED_COPY_CODE(zuart_write)(bool port, uint8_t value) {
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switch(serialmux[port]) {
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default:
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case SERIAL_LOOP:
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if(sio[port].datavalid) {
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sio[port].status[1] |= 0x20;
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}
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sio[port].datavalid = 1;
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sio[port].data = value;
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break;
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case SERIAL_USB:
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if(tud_cdc_n_write_available(port)) {
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tud_cdc_n_write_char(port, value);
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}
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break;
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#ifdef ANALOG_GS
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case SERIAL_UART:
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if(port) {
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if(uart_is_writable(uart1)) {
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uart_putc(uart1, value);
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}
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} else {
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if(uart_is_writable(uart0)) {
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uart_putc(uart0, value);
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}
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}
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break;
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#endif
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}
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return value;
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}
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uint8_t DELAYED_COPY_CODE(zuart_status)(bool port) {
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uint8_t rv = 0;
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switch(sio[port].control[0] & 0x7) {
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case 0:
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if(!sio[port].datavalid) {
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zuart_read(port);
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}
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rv = sio[port].datavalid ? 0x01 : 0x00;
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switch(serialmux[port]) {
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default:
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case SERIAL_LOOP:
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rv |= ((sio[port].control[5] & 0x02) ? 0x20 : 0x00) |
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((sio[port].control[5] & 0x80) ? 0x08 : 0x00) |
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(sio[port].datavalid ? 0x00 : 0x04);
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break;
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case SERIAL_USB:
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rv |= ((tud_cdc_n_get_line_state(port) & 2) ? 0x20 : 0x00) |
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(tud_cdc_n_connected(port) ? 0x08 : 0x00) |
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(tud_cdc_n_write_available(port) ? 0x04 : 0x00);
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break;
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#ifdef ANALOG_GS
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case SERIAL_UART:
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if(port) {
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rv |= 0x20 |
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(uart_is_writable(uart1) ? 0x00 : 0x04);
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} else {
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rv |= 0x20 |
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(uart_is_writable(uart0) ? 0x00 : 0x04);
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}
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break;
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#endif
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}
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break;
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case 1:
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rv = sio[(port)].status[1];
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break;
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case 2:
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if(port)
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rv = sio_vector;
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break;
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}
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sio[(port)].control[0] &= 0xF8;
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return rv;
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}
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uint8_t DELAYED_COPY_CODE(cpu_in)(uint16_t address) {
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uint8_t rv = 0;
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if(address & 0x80) {
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switch(address & 0xff) {
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case 0x80:
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case 0x81:
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case 0x82:
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case 0x83:
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if(ctc[address & 0x03].control & 0x40) {
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rv = ctc[address & 0x03].counter;
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} else {
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}
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break;
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case 0xFC:
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case 0xFE:
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rv = zuart_read(address & 0x02);
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break;
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case 0xFD:
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case 0xFF:
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rv = zuart_status(address & 0x02);
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break;
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}
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} else {
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switch(address & 0xe0) {
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case 0x00: // Write Data to 6502
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rv = pcpi_reg[0];
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break;
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case 0x20: // Read Data from 6502
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clr_z80_stat;
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rv = pcpi_reg[1];
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//printf("I%01X:%02X\r\n", (address >> 4), rv);
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break;
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case 0x40: // Status Port
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if(rd_z80_stat)
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rv |= 0x80;
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if(rd_6502_stat)
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rv |= 0x01;
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break;
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case 0x60:
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break;
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}
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}
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return rv;
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}
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void DELAYED_COPY_CODE(cpu_out)(uint16_t address, uint8_t value) {
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uint16_t divisor;
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if(address & 0x80) {
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switch(address & 0xff) {
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case 0x80:
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case 0x81:
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case 0x82:
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case 0x83:
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if(ctc[address & 0x03].control & 0x04) {
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ctc[address & 0x03].control &= ~0x06;
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ctc[address & 0x03].preload = value;
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if((address & 0x02) == 0) {
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divisor = value ? value : 256;
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sio[address & 0x01].baudrate = 115200 / divisor;
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#ifdef ANALOG_GS
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if(serialmux[(address & 0x01)] == SERIAL_UART) {
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if(address & 0x01) {
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uart_set_baudrate(uart1, sio[1].baudrate);
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} else {
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uart_set_baudrate(uart0, sio[0].baudrate);
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}
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}
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#endif
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}
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} else if(value & 1) {
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ctc[address & 0x03].control = value;
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} else if((address & 0x3) == 0) {
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ctc_vector = value & 0xF8;
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}
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break;
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case 0xFC:
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case 0xFE:
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zuart_write((address & 0x02), value);
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break;
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case 0xFD:
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case 0xFF:
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if(((sio[(address & 0x01)].control[0] & 0x7) == 2) && (address & 0x01))
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sio_vector = value;
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sio[(address & 0x01)].control[sio[(address & 0x01)].control[0] & 0x7] = value;
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sio[(address & 0x01)].control[0] &= 0xF8;
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break;
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}
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} else {
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switch(address & 0xe0) {
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case 0x00: // Write Data to 6502
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//printf("O%01X:%02X\r\n", (address >> 4), value);
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pcpi_reg[0] = value;
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set_6502_stat;
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break;
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case 0x60:
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rom_shadow = (value & 1);
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break;
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case 0xC0:
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ram_bank = (value >> 1) & 7;
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ram_common = (value >> 6) & 1;
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break;
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}
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}
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}
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uint8_t DELAYED_COPY_CODE(_RamRead)(uint16_t address) {
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if((rom_shadow & 1) && (address < 0x8000))
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return z80_rom[address & 0x7ff];
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if((address > 0xE000) && (ram_common)) {
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return z80_ram[address];
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}
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if(ram_bank) {
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return 0xff;
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}
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return z80_ram[address];
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}
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void DELAYED_COPY_CODE(_RamWrite)(uint16_t address, uint8_t value) {
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if((rom_shadow & 1) && (address < 0x8000))
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return;
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if((address > 0xE000) && (ram_common)) {
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z80_ram[address] = value;
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return;
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}
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if(ram_bank) {
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return;
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}
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z80_ram[address] = value;
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}
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#include "z80cpu.h"
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void DELAYED_COPY_CODE(z80main)() {
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z80_res = 1;
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board_init();
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tusb_init();
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for(;;) {
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if(!z80_cycle) {
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tud_task();
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}
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if(config_cmdbuf[7] == 0) {
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config_handler();
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} else
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if(cardslot != 0) {
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if(z80_res) {
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rom_shadow = 1;
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ram_bank = 0;
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ram_common = 0;
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z80_nmi = 0;
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z80_irq = 0;
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z80_res = 0;
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// 6502 -> Z80
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clr_z80_stat;
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// Z80 -> 6502
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clr_6502_stat;
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Z80reset();
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}
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Z80run();
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}
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}
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}
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