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$C800 Stability Fixes

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This commit is contained in:
David Kuder 2023-01-08 20:46:23 -05:00
parent 78f7389a88
commit c62efee7ee
10 changed files with 148 additions and 78 deletions
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8
CUPL/PicoPal.jed
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@ -1,7 +1,7 @@
 
CUPL(WM) 5.0a Serial# MW-10400000 CUPL(WM) 5.0a Serial# MW-10400000
Device g16v8ma Library DLIB-h-40-8 Device g16v8ma Library DLIB-h-40-8
Created Sun Jan 08 03:46:05 2023 Created Sun Jan 08 15:55:21 2023
Name PicoPal Name PicoPal
Partno U5 Partno U5
Revision 01 Revision 01
@ -25,7 +25,7 @@ Location None
*L00768 11111111111111111111111111111111 *L00768 11111111111111111111111111111111
*L00800 11111111110111111111111111111011 *L00800 11111111110111111111111111111011
*L01024 11111111111111111111111111111111 *L01024 11111111111111111111111111111111
*L01056 11111111111111111111110111011001 *L01056 11110111101101111111110111011001
*L01792 11111111111111111111111111111111 *L01792 11111111111111111111111111111111
*L01824 11111111111111111111101111111111 *L01824 11111111111111111111101111111111
*L01856 11111111111111111111111110111111 *L01856 11111111111111111111111110111111
@ -34,5 +34,5 @@ Location None
*L02112 00000000111111111111111111111111 *L02112 00000000111111111111111111111111
*L02144 11111111111111111111111111111111 *L02144 11111111111111111111111111111111
*L02176 111111111111111111 *L02176 111111111111111111
*C4880 *C485E
*EEDB *EEEB

6
CUPL/picopal.doc
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@ -5,7 +5,7 @@
CUPL(WM) 5.0a Serial# MW-10400000 CUPL(WM) 5.0a Serial# MW-10400000
Device g16v8ma Library DLIB-h-40-8 Device g16v8ma Library DLIB-h-40-8
Created Sun Jan 08 03:46:05 2023 Created Sun Jan 08 15:55:21 2023
Name PicoPal Name PicoPal
Partno U5 Partno U5
Revision 01 Revision 01
@ -35,7 +35,7 @@ EXTENABLE =>
# BSEL0 & BSEL1 & BSEL2 & !BSEL3 # BSEL0 & BSEL1 & BSEL2 & !BSEL3
EXTOFF => EXTOFF =>
A0 & A1 & A2 & IOSTROBE A0 & A1 & A2 & BSEL1 & !BSEL2 & BSEL3 & IOSTROBE
EXTSELECT => EXTSELECT =>
EXTENABLE & IOSTROBE EXTENABLE & IOSTROBE
@ -146,7 +146,7 @@ Pin #16 02051 Pol - 02123 Ac1 -
00992 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 00992 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Pin #15 02052 Pol - 02124 Ac1 - Pin #15 02052 Pol - 02124 Ac1 -
01024 -------------------------------- 01024 --------------------------------
01056 ----------------------x---x--xx- 01056 ----x----x--x---------x---x--xx-
01088 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 01088 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01120 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 01120 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01152 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 01152 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx

4
CUPL/picopal.pld
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@ -41,8 +41,8 @@ PIN 18 = EXTDISABLE; /* Combinatorial */
/** Logic Equations **/ /** Logic Equations **/
/* $CFxx disables */ /* $CFxx disables, but only triggered during AddrLo */
EXTOFF = IOSTROBE & [A2..0]:'b'111; EXTOFF = IOSTROBE & [A2..0]:'b'111 & [BSEL3..0]:'b'101X;
/* Implement an SR Latch */ /* Implement an SR Latch */
EXTDISABLE = !(EXTENABLE # IOSELECT); EXTDISABLE = !(EXTENABLE # IOSELECT);

55
CUPL/picopal.si
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@ -9,23 +9,44 @@ Location None;
Device g16V8; Device g16V8;
ORDER: A0, A1, A2, BSEL0, BSEL1, BSEL2, BSEL3, !CARDSELECT, EXTDISABLE, EXTENABLE, EXTOFF, EXTSELECT, !DEVSELECT, !IOSELECT, !IOSTROBE, !RESET, clock; ORDER: A0, A1, A2, BSEL0, BSEL1, BSEL2, BSEL3, !DEVSELECT, !IOSELECT, !IOSTROBE, !RESET, !CARDSELECT, EXTDISABLE, EXTENABLE, EXTOFF, EXTSELECT;
VECTORS: VECTORS:
0000110*****11101 00001111110*****
0000110*****11111 00001111111*****
0000110*****01111 00001101111*****
0000110*****11111 00001011111*****
0000110*****11011 00000111111*****
0000110*****11111 00001101101*****
0000110*****10111 00001011101*****
0000110*****11011 00000111101*****
0001110*****11111 00001100111*****
0000110*****11011 00001010111*****
0000110*****10111 00000110111*****
1100110*****11011 00001101011*****
1110110*****11011 00001011011*****
0000110*****11111 00000111011*****
0000110*****11111 00001101101*****
0000110*****11111 00001011101*****
00000111101*****
00001101101*****
00001011101*****
00010111101*****
11101101101*****
11101011101*****
11100111101*****
00001101011*****
00001011011*****
00000111011*****
00001111110*****
00001101101*****
00001011101*****
00000111101*****
00001101011*****
00001011011*****
00000111011*****
00001111110*****
00001101101*****
00001011101*****
00000111101*****

4
CUPL/picopal.sim
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@ -7,6 +7,7 @@ PIN 5 = BSEL1
PIN 4 = BSEL2 PIN 4 = BSEL2
PIN 3 = BSEL3 PIN 3 = BSEL3
PIN 12 = !CARDSELECT PIN 12 = !CARDSELECT
PIN 1 = CLOCK
PIN 7 = !DEVSELECT PIN 7 = !DEVSELECT
PIN 18 = EXTDISABLE PIN 18 = EXTDISABLE
PIN 17 = EXTENABLE PIN 17 = EXTENABLE
@ -15,7 +16,6 @@ PIN 16 = EXTSELECT
PIN 8 = !IOSELECT PIN 8 = !IOSELECT
PIN 9 = !IOSTROBE PIN 9 = !IOSTROBE
PIN 2 = !RESET PIN 2 = !RESET
PIN 1 = clock
%END %END
%FIELD %FIELD
@ -38,7 +38,7 @@ EXTENABLE =>
# BSEL0 & BSEL1 & BSEL2 & !BSEL3 # BSEL0 & BSEL1 & BSEL2 & !BSEL3
EXTOFF => EXTOFF =>
A0 & A1 & A2 & !IOSTROBE A0 & A1 & A2 & BSEL1 & !BSEL2 & BSEL3 & !IOSTROBE
EXTSELECT => EXTSELECT =>
EXTENABLE & !IOSTROBE EXTENABLE & !IOSTROBE

83
CUPL/picopal.so
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@ -1,7 +1,7 @@
CSIM(WM): CUPL Simulation Program CSIM(WM): CUPL Simulation Program
Version 5.0a Serial# Version 5.0a Serial#
Copyright (c) 1983, 1998 Logical Devices, Inc. Copyright (c) 1983, 1998 Logical Devices, Inc.
CREATED Sun Jan 08 03:46:14 2023 CREATED Sun Jan 08 15:54:24 2023
LISTING FOR SIMULATION FILE: picopal.si LISTING FOR SIMULATION FILE: picopal.si
@ -16,36 +16,57 @@ LISTING FOR SIMULATION FILE: picopal.si
9: Device g16V8; 9: Device g16V8;
10: 10:
11: 11:
12: ORDER: A0, A1, A2, BSEL0, BSEL1, BSEL2, BSEL3, !CARDSELECT, EXTDISABLE, EXTENABLE, EXTOFF, EXTSELECT, !DEVSELECT, !IOSELECT, !IOSTROBE, !RESET, clock; 12: ORDER: A0, A1, A2, BSEL0, BSEL1, BSEL2, BSEL3, !DEVSELECT, !IOSELECT, !IOSTROBE, !RESET, !CARDSELECT, EXTDISABLE, EXTENABLE, EXTOFF, EXTSELECT;
13: 13:
14: 14:
========================== =========================
! !
CE ! ! CE
AXE ED!! D!! AXE E
RTX XEII EII RTX X
DDT TVOO VOO DDT T
SIEESSSS! SSS!SIEES
BBBBESNXEEETRc BBBBEETRESNXE
SSSSLAATLLLREl SSSSLLRELAATL
EEEEEBBOEEEOSo EEEEEEOSEBBOE
AAALLLLCLLFCCCBEc AAALLLLCCBECLLFC
0120123TEEFTTTETk 0120123TTETTEEFT
========================== =========================
0001: 0000110HHLLL11101 0001: 00001111110HHLLL
0002: 0000110HHLLL11111 0002: 00001111111HHLLL
0003: 0000110LHLLL01111 0003: 00001101111HHLLL
0004: 0000110HHLLL11111 0004: 00001011111HHLLL
0005: 0000110HHLLL11011 0005: 00000111111HHLLL
0006: 0000110HHLLL11111 0006: 00001101101HHLLL
0007: 0000110LLHLL10111 0007: 00001011101HHLLL
0008: 0000110LLHLH11011 0008: 00000111101HHLLL
0009: 0001110HHLLL11111 0009: 00001100111LHLLL
0010: 0000110HHLLL11011 0010: 00001010111LHLLL
0011: 0000110LLHLL10111 0011: 00000110111LHLLL
0012: 1100110LLHLH11011 0012: 00001101011LLHLL
0013: 1110110HHLHL11011 0013: 00001011011LLHLL
0014: 0000110HHLLL11111 0014: 00000111011LLHLL
0015: 0000110HHLLL11111 0015: 00001101101LLHLH
0016: 0000110HHLLL11111 0016: 00001011101LLHLH
0017: 00000111101LLHLH
0018: 00001101101LLHLH
0019: 00001011101LLHLH
0020: 00010111101LLHLH
0021: 11101101101LLHLH
0022: 11101011101HHLHL
0023: 11100111101HHLLL
0024: 00001101011LLHLL
0025: 00001011011LLHLL
0026: 00000111011LLHLL
0027: 00001111110HHLLL
0028: 00001101101HHLLL
0029: 00001011101HHLLL
0030: 00000111101HHLLL
0031: 00001101011LLHLL
0032: 00001011011LLHLL
0033: 00000111011LLHLL
0034: 00001111110HHLLL
0035: 00001101101HHLLL
0036: 00001011101HHLLL
0037: 00000111101HHLLL

55
CUPL/picopal.wo
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@ -10,22 +10,43 @@
#H Device g16V8; #H Device g16V8;
#H #H
#H #H
#H ORDER: A0, A1, A2, BSEL0, BSEL1, BSEL2, BSEL3, !CARDSELECT, EXTDISABLE, EXTENABLE, EXTOFF, EXTSELECT, !DEVSELECT, !IOSELECT, !IOSTROBE, !RESET, clock; #H ORDER: A0, A1, A2, BSEL0, BSEL1, BSEL2, BSEL3, !DEVSELECT, !IOSELECT, !IOSTROBE, !RESET, !CARDSELECT, EXTDISABLE, EXTENABLE, EXTOFF, EXTSELECT;
#H #H
#H #H
#V 0001 0000110HHLLL11101 #V 0001 00001111110HHLLL
#V 0002 0000110HHLLL11111 #V 0002 00001111111HHLLL
#V 0003 0000110LHLLL01111 #V 0003 00001101111HHLLL
#V 0004 0000110HHLLL11111 #V 0004 00001011111HHLLL
#V 0005 0000110HHLLL11011 #V 0005 00000111111HHLLL
#V 0006 0000110HHLLL11111 #V 0006 00001101101HHLLL
#V 0007 0000110LLHLL10111 #V 0007 00001011101HHLLL
#V 0008 0000110LLHLH11011 #V 0008 00000111101HHLLL
#V 0009 0001110HHLLL11111 #V 0009 00001100111LHLLL
#V 0010 0000110HHLLL11011 #V 0010 00001010111LHLLL
#V 0011 0000110LLHLL10111 #V 0011 00000110111LHLLL
#V 0012 1100110LLHLH11011 #V 0012 00001101011LLHLL
#V 0013 1110110HHLHL11011 #V 0013 00001011011LLHLL
#V 0014 0000110HHLLL11111 #V 0014 00000111011LLHLL
#V 0015 0000110HHLLL11111 #V 0015 00001101101LLHLH
#V 0016 0000110HHLLL11111 #V 0016 00001011101LLHLH
#V 0017 00000111101LLHLH
#V 0018 00001101101LLHLH
#V 0019 00001011101LLHLH
#V 0020 00010111101LLHLH
#V 0021 11101101101LLHLH
#V 0022 11101011101HHLHL
#V 0023 11100111101HHLLL
#V 0024 00001101011LLHLL
#V 0025 00001011011LLHLL
#V 0026 00000111011LLHLL
#V 0027 00001111110HHLLL
#V 0028 00001101101HHLLL
#V 0029 00001011101HHLLL
#V 0030 00000111101HHLLL
#V 0031 00001101011LLHLL
#V 0032 00001011011LLHLL
#V 0033 00000111011LLHLL
#V 0034 00001111110HHLLL
#V 0035 00001101101HHLLL
#V 0036 00001011101HHLLL
#V 0037 00000111101HHLLL

4
v2-analog-rev1/common/abus.pio
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@ -41,7 +41,7 @@ write_cycle:
read_cycle: read_cycle:
; the current time is P0+88ns (P0 + 16ns + 2 clocks (input synchronizers) + 7 instructions) ; the current time is P0+88ns (P0 + 16ns + 2 clocks (input synchronizers) + 7 instructions)
set PINS, 0b111 [1] ; ensure AddrLo transceiver is disabled and delay for ~DEVSEL to become valid (P0+63ns+buffer delay) set PINS, 0b110 ; ensure AddrLo transceiver is disabled and delay for ~DEVSEL to become valid (P0+63ns+buffer delay)
in PINS, 10 ; read R/W, ~DEVSEL, and dontcare[7:0], then autopush in PINS, 10 ; read R/W, ~DEVSEL, and dontcare[7:0], then autopush
irq set READ_DATA_TRIGGER_IRQ ; trigger the data read state machine to put data on the data bus irq set READ_DATA_TRIGGER_IRQ ; trigger the data read state machine to put data on the data bus
@ -87,7 +87,7 @@ wait_loop:
; the current time is P0+440ns (P0 + 16ns + 2 clocks (input synchronizers) + 51 instructions) ; the current time is P0+440ns (P0 + 16ns + 2 clocks (input synchronizers) + 51 instructions)
wait 0 GPIO, PHI0_GPIO [1] ; wait for PHI0 to fall then hold for 40ns (2 clocks (input synchronizers) + 2-3 instructions) wait 0 GPIO, PHI0_GPIO [2] ; wait for PHI0 to fall then hold for 40ns (2 clocks (input synchronizers) + 2-3 instructions)
set PINS, 0b10 ; disable Data tranceiver to tri-state the data bus set PINS, 0b10 ; disable Data tranceiver to tri-state the data bus
mov OSR, NULL mov OSR, NULL

3
v2-analog-rev1/common/main.c
View File

@ -50,6 +50,9 @@ static void core0_loop() {
case MODE_REBOOT: case MODE_REBOOT:
flash_reboot(); flash_reboot();
break; break;
case MODE_DIAG:
diagmain();
break;
case MODE_VGACARD: case MODE_VGACARD:
vgamain(); vgamain();
break; break;

4
v2-analog-rev1/diag/diag.c
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@ -1,3 +1,4 @@
#include <string.h>
#include <pico/stdlib.h> #include <pico/stdlib.h>
#include <pico/multicore.h> #include <pico/multicore.h>
#include "common/config.h" #include "common/config.h"
@ -5,6 +6,8 @@
#include "diag/businterface.h" #include "diag/businterface.h"
void diagmain() { void diagmain() {
uint16_t i;
memset((uint8_t*)(apple_memory+0xC080), 0xC0, 0x10); memset((uint8_t*)(apple_memory+0xC080), 0xC0, 0x10);
memset((uint8_t*)(apple_memory+0xC090), 0xC1, 0x10); memset((uint8_t*)(apple_memory+0xC090), 0xC1, 0x10);
memset((uint8_t*)(apple_memory+0xC0A0), 0xC2, 0x10); memset((uint8_t*)(apple_memory+0xC0A0), 0xC2, 0x10);
@ -23,6 +26,7 @@ void diagmain() {
memset((uint8_t*)(apple_memory+0xC800), 0xC8, 0x800); memset((uint8_t*)(apple_memory+0xC800), 0xC8, 0x800);
while(v2mode == MODE_DIAG) { while(v2mode == MODE_DIAG) {
sleep_ms(50);
} }
} }