mirror of
https://github.com/V2RetroComputing/analog.git
synced 2024-06-08 19:29:30 +00:00
229 lines
9.0 KiB
C
229 lines
9.0 KiB
C
#include <string.h>
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#include <hardware/pio.h>
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#include "common/config.h"
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#include "abus.pio.h"
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#include "vga/businterface.h"
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#include "vga/vgabuf.h"
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volatile uint8_t *videx_page = videx_memory;
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uint32_t a2_first_write = 0;
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static inline void __time_critical_func(videx_crtc_addr)(uint32_t value) {
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}
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static inline void __time_critical_func(videx_crtc_write)(uint32_t value) {
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}
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void __time_critical_func(vga_businterface)(uint32_t address, uint32_t value) {
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// Shadow the soft-switches by observing all read & write bus cycles
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if((address & 0xff80) == 0xc000) {
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switch(address & 0x7f) {
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case 0x00:
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if((soft_switches & (SOFTSW_IIGS_REGS | SOFTSW_IIE_REGS)) && ((value & (1u << CONFIG_PIN_APPLEBUS_RW-CONFIG_PIN_APPLEBUS_DATA_BASE)) == 0)) {
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soft_switches &= ~SOFTSW_80STORE;
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}
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break;
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case 0x01:
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if((soft_switches & (SOFTSW_IIGS_REGS | SOFTSW_IIE_REGS)) && ((value & (1u << CONFIG_PIN_APPLEBUS_RW-CONFIG_PIN_APPLEBUS_DATA_BASE)) == 0)) {
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soft_switches |= SOFTSW_80STORE;
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}
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break;
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case 0x04:
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if((soft_switches & (SOFTSW_IIGS_REGS | SOFTSW_IIE_REGS)) && ((value & (1u << CONFIG_PIN_APPLEBUS_RW-CONFIG_PIN_APPLEBUS_DATA_BASE)) == 0)) {
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soft_switches &= ~SOFTSW_AUX_WRITE;
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}
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break;
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case 0x05:
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if((soft_switches & (SOFTSW_IIGS_REGS | SOFTSW_IIE_REGS)) && ((value & (1u << CONFIG_PIN_APPLEBUS_RW-CONFIG_PIN_APPLEBUS_DATA_BASE)) == 0)) {
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soft_switches |= SOFTSW_AUX_WRITE;
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}
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break;
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case 0x08:
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if((soft_switches & (SOFTSW_IIGS_REGS | SOFTSW_IIE_REGS)) && ((value & (1u << CONFIG_PIN_APPLEBUS_RW-CONFIG_PIN_APPLEBUS_DATA_BASE)) == 0)) {
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soft_switches &= ~SOFTSW_AUXZP;
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}
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break;
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case 0x09:
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if((soft_switches & (SOFTSW_IIGS_REGS | SOFTSW_IIE_REGS)) && ((value & (1u << CONFIG_PIN_APPLEBUS_RW-CONFIG_PIN_APPLEBUS_DATA_BASE)) == 0)) {
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soft_switches |= SOFTSW_AUXZP;
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}
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break;
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case 0x0c:
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if((soft_switches & (SOFTSW_IIGS_REGS | SOFTSW_IIE_REGS)) && ((value & (1u << CONFIG_PIN_APPLEBUS_RW-CONFIG_PIN_APPLEBUS_DATA_BASE)) == 0)) {
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soft_switches &= ~SOFTSW_80COL;
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}
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break;
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case 0x0d:
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if((soft_switches & (SOFTSW_IIGS_REGS | SOFTSW_IIE_REGS)) && ((value & (1u << CONFIG_PIN_APPLEBUS_RW-CONFIG_PIN_APPLEBUS_DATA_BASE)) == 0)) {
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soft_switches |= SOFTSW_80COL;
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}
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break;
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case 0x0e:
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if((soft_switches & (SOFTSW_IIGS_REGS | SOFTSW_IIE_REGS)) && ((value & (1u << CONFIG_PIN_APPLEBUS_RW-CONFIG_PIN_APPLEBUS_DATA_BASE)) == 0)) {
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soft_switches &= ~SOFTSW_ALTCHAR;
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}
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break;
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case 0x0f:
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if((soft_switches & (SOFTSW_IIGS_REGS | SOFTSW_IIE_REGS)) && ((value & (1u << CONFIG_PIN_APPLEBUS_RW-CONFIG_PIN_APPLEBUS_DATA_BASE)) == 0)) {
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soft_switches |= SOFTSW_ALTCHAR;
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}
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break;
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case 0x21:
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if((SOFTSW_IIGS_REGS | SOFTSW_IIE_REGS) && ((value & (1u << CONFIG_PIN_APPLEBUS_RW-CONFIG_PIN_APPLEBUS_DATA_BASE)) == 0)) {
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if(value & 0x80) {
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soft_switches |= SOFTSW_MONOCHROME;
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} else {
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soft_switches &= ~SOFTSW_MONOCHROME;
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}
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}
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break;
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case 0x22:
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if((soft_switches & SOFTSW_IIGS_REGS) && ((value & (1u << CONFIG_PIN_APPLEBUS_RW-CONFIG_PIN_APPLEBUS_DATA_BASE)) == 0)) {
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terminal_tbcolor = value & 0xff;
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}
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break;
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case 0x29:
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if((soft_switches & SOFTSW_IIGS_REGS) && ((value & (1u << CONFIG_PIN_APPLEBUS_RW-CONFIG_PIN_APPLEBUS_DATA_BASE)) == 0)) {
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soft_switches = (soft_switches & ~(SOFTSW_NEWVID_MASK << SOFTSW_NEWVID_SHIFT)) | ((value & SOFTSW_NEWVID_MASK) << SOFTSW_NEWVID_SHIFT);
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}
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break;
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case 0x34:
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if((soft_switches & SOFTSW_IIGS_REGS) && ((value & (1u << CONFIG_PIN_APPLEBUS_RW-CONFIG_PIN_APPLEBUS_DATA_BASE)) == 0)) {
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terminal_border = value & 0x0f;
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}
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break;
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case 0x35:
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if((soft_switches & SOFTSW_IIGS_REGS) && ((value & (1u << CONFIG_PIN_APPLEBUS_RW-CONFIG_PIN_APPLEBUS_DATA_BASE)) == 0)) {
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soft_switches = (soft_switches & ~(SOFTSW_SHADOW_MASK << SOFTSW_SHADOW_SHIFT)) | ((value & SOFTSW_SHADOW_MASK) << SOFTSW_SHADOW_SHIFT);
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}
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break;
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case 0x50:
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soft_switches &= ~SOFTSW_TEXT_MODE;
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break;
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case 0x51:
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soft_switches |= SOFTSW_TEXT_MODE;
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break;
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case 0x52:
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soft_switches &= ~SOFTSW_MIX_MODE;
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break;
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case 0x53:
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soft_switches |= SOFTSW_MIX_MODE;
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break;
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case 0x54:
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soft_switches &= ~SOFTSW_PAGE_2;
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break;
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case 0x55:
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soft_switches |= SOFTSW_PAGE_2;
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break;
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case 0x56:
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soft_switches &= ~SOFTSW_HIRES_MODE;
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break;
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case 0x57:
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soft_switches |= SOFTSW_HIRES_MODE;
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break;
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case 0x5e:
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if(soft_switches & (SOFTSW_IIGS_REGS | SOFTSW_IIE_REGS)) {
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soft_switches |= SOFTSW_DGR;
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}
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break;
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case 0x5f:
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if(soft_switches & (SOFTSW_IIGS_REGS | SOFTSW_IIE_REGS)) {
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soft_switches &= ~SOFTSW_DGR;
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}
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break;
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case 0x7e:
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if((soft_switches & SOFTSW_IIE_REGS) && ((value & (1u << CONFIG_PIN_APPLEBUS_RW-CONFIG_PIN_APPLEBUS_DATA_BASE)) == 0)) {
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soft_switches |= SOFTSW_IOUDIS;
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}
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break;
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case 0x7f:
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if((soft_switches & SOFTSW_IIE_REGS) && ((value & (1u << CONFIG_PIN_APPLEBUS_RW-CONFIG_PIN_APPLEBUS_DATA_BASE)) == 0)) {
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soft_switches &= ~SOFTSW_IOUDIS;
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}
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break;
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}
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return;
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}
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// Shadow parts of the Apple's memory by observing the bus write cycles
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if((value & (1u << CONFIG_PIN_APPLEBUS_RW-CONFIG_PIN_APPLEBUS_DATA_BASE)) == 0) {
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if(current_machine == MACHINE_AUTO) {
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a2_first_write = (address << 16) | (value & 0x3FF);
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if(a2_first_write == 0xC0330100) { // Apple IIgs ROM03 Clock Access
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current_machine = MACHINE_IIGS;
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soft_switches &= ~SOFTSW_IIE_REGS;
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soft_switches |= SOFTSW_IIGS_REGS;
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} else if(a2_first_write == 0x01F901FB) { // Apple II Plus
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current_machine = MACHINE_II;
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soft_switches &= ~(SOFTSW_IIE_REGS | SOFTSW_IIGS_REGS);
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} else if(a2_first_write == 0x01F5018B) { // Apple IIe Platinum
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current_machine = MACHINE_IIE;
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soft_switches |= SOFTSW_IIE_REGS;
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soft_switches &= ~SOFTSW_IIGS_REGS;
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} else {
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a2_first_write = 0;
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}
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}
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// Mirror Video Memory from MAIN & AUX banks
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if(soft_switches & SOFTSW_LINEARIZE) {
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if((address >= 0x2000) && (address < 0xC000)) {
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private_memory[address] = value & 0xff;
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return;
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}
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}
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if(soft_switches & SOFTSW_80STORE) {
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if(soft_switches & SOFTSW_PAGE_2) {
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if((address >= 0x400) && (address < 0x800)) {
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private_memory[address] = value & 0xff;
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return;
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} else if((soft_switches & SOFTSW_HIRES_MODE) && (address >= 0x2000) && (address < 0x4000)) {
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private_memory[address] = value & 0xff;
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return;
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}
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}
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} else if(soft_switches & SOFTSW_AUX_WRITE) {
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if((address >= 0x200) && (address < 0xC000)) {
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private_memory[address] = value & 0xff;
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return;
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}
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}
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if((address >= 0x200) && (address < 0xC000)) {
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apple_memory[address] = value & 0xff;
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return;
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}
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#if 0
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// Videx 80 Column Card
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if(CARD_SELECT) {
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if((address >= 0xC800) && (address < 0xCC00)) {
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videx_page[(address & 0x3FF)] = value & 0xff;
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}
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if(CARD_DEVSEL) {
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switch(address & 0x01) {
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case 0x0:
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videx_crtc_addr(value & 0xff);
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break;
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case 0x1:
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videx_crtc_write(value & 0xff);
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break;
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}
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}
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}
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#endif
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}
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#if 0
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// Any access to Videx I/O sets the VRAM page visible in 0xCC00-0xD000
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if(CARD_SELECT && CARD_DEVSEL) {
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videx_page = videx_memory + ((address & 0x0C) << 9);
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}
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#endif
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}
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