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224 lines
9.4 KiB
HTML
224 lines
9.4 KiB
HTML
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<HEAD><TITLE>Lattice Synthesis Timing Report</TITLE>
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</HEAD>
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<PRE><A name="Map_Twr"></A><B><U><big>Lattice Synthesis Timing Report</big></U></B>
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--------------------------------------------------------------------------------
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Lattice Synthesis Timing Report, Version
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Thu Feb 22 10:56:37 2018
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
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<A name="mtw1_ri"></A><B><U><big>Report Information</big></U></B>
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------------------
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Design: top
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Constraint file:
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Report level: verbose report, limited to 3 items per constraint
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--------------------------------------------------------------------------------
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================================================================================
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Constraint: create_clock -period 1000.000000 -name clk1 [get_nets _devsel_c]
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0 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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================================================================================
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Constraint: create_clock -period 1000.000000 -name clk0 [get_nets fclk_c]
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702 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 989.989ns
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Logical Details: Cell type Pin type Cell name (clock net +/-)
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Source: FD1P3IX CK \myIwm/bitTimer__i1 (from fclk_c +)
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Destination: FD1P3AX SP \myIwm/shifter_i0_i0 (to fclk_c +)
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Delay: 9.726ns (24.8% logic, 75.2% route), 5 logic levels.
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Constraint Details:
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9.726ns data_path \myIwm/bitTimer__i1 to \myIwm/shifter_i0_i0 meets
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1000.000ns delay constraint less
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0.285ns LCE_S requirement (totaling 999.715ns) by 989.989ns
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Path Details: \myIwm/bitTimer__i1 to \myIwm/shifter_i0_i0
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Name Fanout Delay (ns) Pins Resource(Cell.Net)
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L_CO --- 0.444 CK to Q \myIwm/bitTimer__i1 (from fclk_c)
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Route 9 e 1.632 \myIwm/bitTimer[1]
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LUT4 --- 0.493 D to Z \myIwm/i4_4_lut
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Route 3 e 1.258 \myIwm/n10
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LUT4 --- 0.493 B to Z \myIwm/i5_3_lut_rep_20
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Route 4 e 1.340 \myIwm/n1862
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LUT4 --- 0.493 B to Z \myIwm/i145_3_lut_4_lut
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Route 8 e 1.540 \myIwm/n163
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LUT4 --- 0.493 B to Z \myIwm/i1_4_lut_adj_28
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Route 8 e 1.540 \myIwm/fclk_c_enable_14
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--------
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9.726 (24.8% logic, 75.2% route), 5 logic levels.
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Passed: The following path meets requirements by 989.989ns
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Logical Details: Cell type Pin type Cell name (clock net +/-)
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Source: FD1P3IX CK \myIwm/bitTimer__i1 (from fclk_c +)
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Destination: FD1P3AX SP \myIwm/shifter_i0_i1 (to fclk_c +)
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Delay: 9.726ns (24.8% logic, 75.2% route), 5 logic levels.
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Constraint Details:
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9.726ns data_path \myIwm/bitTimer__i1 to \myIwm/shifter_i0_i1 meets
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1000.000ns delay constraint less
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0.285ns LCE_S requirement (totaling 999.715ns) by 989.989ns
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Path Details: \myIwm/bitTimer__i1 to \myIwm/shifter_i0_i1
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Name Fanout Delay (ns) Pins Resource(Cell.Net)
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L_CO --- 0.444 CK to Q \myIwm/bitTimer__i1 (from fclk_c)
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Route 9 e 1.632 \myIwm/bitTimer[1]
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LUT4 --- 0.493 D to Z \myIwm/i4_4_lut
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Route 3 e 1.258 \myIwm/n10
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LUT4 --- 0.493 B to Z \myIwm/i5_3_lut_rep_20
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Route 4 e 1.340 \myIwm/n1862
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LUT4 --- 0.493 B to Z \myIwm/i145_3_lut_4_lut
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Route 8 e 1.540 \myIwm/n163
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LUT4 --- 0.493 B to Z \myIwm/i1_4_lut_adj_28
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Route 8 e 1.540 \myIwm/fclk_c_enable_14
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--------
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9.726 (24.8% logic, 75.2% route), 5 logic levels.
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Passed: The following path meets requirements by 989.989ns
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Logical Details: Cell type Pin type Cell name (clock net +/-)
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Source: FD1P3IX CK \myIwm/bitTimer__i1 (from fclk_c +)
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Destination: FD1P3AX SP \myIwm/shifter_i0_i2 (to fclk_c +)
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Delay: 9.726ns (24.8% logic, 75.2% route), 5 logic levels.
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Constraint Details:
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9.726ns data_path \myIwm/bitTimer__i1 to \myIwm/shifter_i0_i2 meets
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1000.000ns delay constraint less
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0.285ns LCE_S requirement (totaling 999.715ns) by 989.989ns
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Path Details: \myIwm/bitTimer__i1 to \myIwm/shifter_i0_i2
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Name Fanout Delay (ns) Pins Resource(Cell.Net)
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L_CO --- 0.444 CK to Q \myIwm/bitTimer__i1 (from fclk_c)
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Route 9 e 1.632 \myIwm/bitTimer[1]
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LUT4 --- 0.493 D to Z \myIwm/i4_4_lut
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Route 3 e 1.258 \myIwm/n10
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LUT4 --- 0.493 B to Z \myIwm/i5_3_lut_rep_20
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Route 4 e 1.340 \myIwm/n1862
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LUT4 --- 0.493 B to Z \myIwm/i145_3_lut_4_lut
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Route 8 e 1.540 \myIwm/n163
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LUT4 --- 0.493 B to Z \myIwm/i1_4_lut_adj_28
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Route 8 e 1.540 \myIwm/fclk_c_enable_14
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--------
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9.726 (24.8% logic, 75.2% route), 5 logic levels.
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Report: 10.011 ns is the maximum delay for this constraint.
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<A name="mtw1_rs"></A><B><U><big>Timing Report Summary</big></U></B>
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--------------
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--------------------------------------------------------------------------------
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Constraint | Constraint| Actual|Levels
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--------------------------------------------------------------------------------
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create_clock -period 1000.000000 -name | | |
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clk1 [get_nets _devsel_c] | -| -| 0
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create_clock -period 1000.000000 -name | | |
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clk0 [get_nets fclk_c] | 1000.000 ns| 10.011 ns| 5
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--------------------------------------------------------------------------------
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All constraints were met.
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<A name="mtw1_ts"></A><B><U><big>Timing summary:</big></U></B>
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---------------
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Timing errors: 0 Score: 0
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Constraints cover 702 paths, 106 nets, and 328 connections (53.9% coverage)
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Peak memory: 55623680 bytes, TRCE: 2555904 bytes, DLYMAN: 163840 bytes
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CPU_TIME_REPORT: 0 secs
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