mirror of
https://github.com/steve-chamberlin/fpga-disk-controller.git
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41 lines
2.9 KiB
XML
41 lines
2.9 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<BuildStatus>
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<Strategy name="Strategy1">
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<Milestone name="Export" build_result="0" build_time="0">
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<Task name="IBIS" build_result="0" update_result="3" update_time="0"/>
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<Task name="TimingSimFileVlg" build_result="0" update_result="3" update_time="0"/>
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<Task name="TimingSimFileVHD" build_result="0" update_result="3" update_time="0"/>
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<Task name="Bitgen" build_result="0" update_result="3" update_time="0"/>
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<Task name="Jedecgen" build_result="0" update_result="2" update_time="1519325808"/>
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</Milestone>
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<Milestone name="Map" build_result="0" build_time="1519325799">
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<Task name="Map" build_result="0" update_result="2" update_time="1519325799"/>
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<Task name="MapTrace" build_result="0" update_result="3" update_time="0"/>
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<Task name="MapVerilogSimFile" build_result="0" update_result="3" update_time="0"/>
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<Task name="MapVHDLSimFile" build_result="0" update_result="3" update_time="0"/>
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</Milestone>
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<Milestone name="PAR" build_result="0" build_time="1519325804">
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<Task name="PAR" build_result="0" update_result="2" update_time="1519325804"/>
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<Task name="PARTrace" build_result="0" update_result="2" update_time="1519325805"/>
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<Task name="IOTiming" build_result="0" update_result="3" update_time="0"/>
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</Milestone>
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<Milestone name="Synthesis" build_result="0" build_time="1519325798">
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<Task name="Lattice_Synthesis" build_result="0" update_result="2" update_time="1519325798"/>
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<Task name="LSE_Compile" build_result="0" update_result="2" update_time="1519325808"/>
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</Milestone>
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<Milestone name="TOOL_Report" build_result="0" build_time="0">
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<Task name="HDLE" build_result="0" update_result="2" update_time="1519325793"/>
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<Task name="SSO" build_result="0" update_result="3" update_time="0"/>
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<Task name="PIODRC" build_result="0" update_result="3" update_time="0"/>
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</Milestone>
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<Report name=".vdbs/liron_fpgatop_map.vdb" last_build_time="1519325799" last_build_size="60806"/>
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<Report name="liron_fpgatop.bgn" last_build_time="1519325808" last_build_size="4508"/>
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<Report name="liron_fpgatop.jed" last_build_time="1519325808" last_build_size="351577"/>
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<Report name="liron_fpgatop.lsedata" last_build_time="1519325797" last_build_size="225045"/>
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<Report name="liron_fpgatop.ncd" last_build_time="1519325804" last_build_size="193114"/>
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<Report name="liron_fpgatop.ngd" last_build_time="1519325798" last_build_size="138411"/>
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<Report name="liron_fpgatop.twr" last_build_time="1519325805" last_build_size="49333"/>
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<Report name="liron_fpgatop_map.ncd" last_build_time="1519325799" last_build_size="145088"/>
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</Strategy>
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</BuildStatus>
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