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production cleanup for interface-ascii

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- Add production package scripts
- Configure BOM generation for KiBOM
- Add 3D models to path (add kicad 5 path variable to list)
- bump version to 3 for compatibility with versioning scheme
This commit is contained in:
Dave 2022-11-15 15:46:46 -06:00
parent 0d0487df42
commit 33e68c6800
7 changed files with 5101 additions and 3974 deletions
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124
hardware/interface-ascii/bom.ini Normal file
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[BOM_OPTIONS]
; General BoM options here
; If 'ignore_dnf' option is set to 1, rows that are not to be fitted on the PCB will not be written to the BoM file
ignore_dnf = 0
; If 'html_generate_dnf' option is set to 1, also generate a list of components not fitted on the PCB (HTML only)
html_generate_dnf = 1
; If 'use_alt' option is set to 1, grouped references will be printed in the alternate compressed style eg: R1-R7,R18
use_alt = 1
; If 'alt_wrap' option is set to and integer N, the references field will wrap after N entries are printed
alt_wrap = 0
; If 'number_rows' option is set to 1, each row in the BoM will be prepended with an incrementing row number
number_rows = 1
; If 'group_connectors' option is set to 1, connectors with the same footprints will be grouped together, independent of the name of the connector
group_connectors = 1
; If 'test_regex' option is set to 1, each component group will be tested against a number of regular-expressions (specified, per column, below). If any matches are found, the row is ignored in the output file
test_regex = 1
; If 'merge_blank_fields' option is set to 1, component groups with blank fields will be merged into the most compatible group, where possible
merge_blank_fields = 1
; Specify output file name format, %O is the defined output name, %v is the version, %V is the variant name which will be ammended according to 'variant_file_name_format'.
output_file_name = %O_bom_%v%V
; Specify the variant file name format, this is a unique field as the variant is not always used/specified. When it is unused you will want to strip all of this.
variant_file_name_format = _(%V)
; Field name used to determine if a particular part is to be fitted
fit_field = Fitted
; Make a backup of the bom before generating the new one, using the following template
make_backup = %O.tmp
; Default number of boards to produce if none given on CLI with -n
number_boards = 1
; Default PCB variant if none given on CLI with -r
board_variant = ['default']
; Whether to hide headers from output file
hide_headers = False
; Whether to hide PCB info from output file
hide_pcb_info = False
[IGNORE_COLUMNS]
; Any column heading that appears here will be excluded from the Generated BoM
; Titles are case-insensitive
Class
Component Type
Footprint
Footprint Lib
Material
Number of Pins
Package Variant
Part
Part Lib
Power Rating
RoHS China Link
RoHS Europe Link
SheetPath
Standards Version
Temp (Operating)
Temp (Soldering)
Temp (Storage)
Temp Coeff.
Tolerance
Value
Voltage Rating
Current Rating
[COLUMN_ORDER]
; Columns will apear in the order they are listed here
; Titles are case-insensitive
References
Fitted
Quantity Per PCB
Description
Part Value
Manufacturer
Manufacturer PN
Label
BOM Comment
[GROUP_FIELDS]
; List of fields used for sorting individual components into groups
; Components which match (comparing *all* fields) will be grouped together
; Field names are case-insensitive
Part
Part Lib
Value
Footprint
Footprint Lib
[COMPONENT_ALIASES]
; A series of values which are considered to be equivalent for the part name
; Each line represents a list of equivalent component name values separated by white space
; e.g. 'c c_small cap' will ensure the equivalent capacitor symbols can be grouped together
; Aliases are case-insensitive
c c_small cap capacitor
r r_small res resistor
sw switch
l l_small inductor
zener zenersmall
d diode d_small
[REGEX_INCLUDE]
; A series of regular expressions used to include parts in the BoM
; If there are any regex defined here, only components that match against ANY of them will be included in the BOM
; Column names are case-insensitive
; Format is: "[ColumName] [Regex]" (white-space separated)
[REGEX_EXCLUDE]
; A series of regular expressions used to exclude parts from the BoM
; If a component matches ANY of these, it will be excluded from the BoM
; Column names are case-insensitive
; Format is: "[ColumName] [Regex]" (white-space separated)
References ^TP[0-9]*
References ^FID
Part mount.*hole
Part solder.*bridge
Part test.*point
Footprint test.*point
Footprint mount.*hole
Footprint fiducial
Allow Substitution
Tracking
Package
Manufacturer Link
Component Value
Datasheet

8166
hardware/interface-ascii/interface-ascii.kicad_pcb
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320
hardware/interface-ascii/production-package/Makefile Normal file
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NAME=interface-ascii
PROJECT_DESC=Unified retro keyboard ASCII interface, ATMega 328P version
VARIANTNAME=Production
BOARDREV=3
BOARDREVMINOR=
SCHEMATIC_REV=0
PROJECT_REV=0
LAYERS=2
PCBDIR="./PCB_dir"
PROGRAMMING_DIR=programming_files_dir
DIAGRAMS_DIR=diagrams_dir
WORK_INSTR_DIR=work_instructions_dir
LABELS_DIR=labels_dir
SUBDIRS=$(PROGRAMMING_DIR) $(DIAGRAMS_DIR) $(WORK_INSTR_DIR) $(LABELS_DIR)
PCBREV=$(BOARDREV)
SCHREV=$(BOARDREV).$(SCHEMATIC_REV)
PRJREV=$(BOARDREV).$(SCHEMATIC_REV).$(PROJECT_REV)
PCBNAME=$(NAME)-Rev_$(PCBREV)$(BOARDREVMINOR)
PCBFULLNAME=$(PCBNAME)-$(VARIANTNAME)
SCHNAME=$(NAME)-Rev_$(SCHREV)-$(VARIANTNAME)
PRJNAME=$(NAME)-Rev_$(PRJREV)$(BOARDREVMINOR)-$(VARIANTNAME)
SCHEMATIC_SRC=$(NAME).kicad_sch
BOARD_SRC=$(NAME).kicad_pcb
PCBZIPFILE=$(PCBNAME)-pcbfab.zip
PKGZIPFILE=$(PRJNAME)-package.zip
GENERATED_BOMFILE = ../$(NAME)_bom_$(SCHREV).csv
BOMFILE=BOM-$(SCHNAME).csv
BOMINITFILE=../bom.ini
BOMINITTEMPLATE=./templates/bom.ini
#README_STYLE=rst
README_STYLE=pdf
READMEFILEBASE=README-$(PRJNAME)
READMEFILETXT=$(READMEFILEBASE).rst
READMEFILEPDF=$(READMEFILEBASE).pdf
READMETARGET=readme$(README_STYLE)
RENDERFILE_TOP=Renderings-top-$(PCBFULLNAME).jpg
RENDERFILE_BOTTOM=Renderings-bottom-$(PCBFULLNAME).jpg
RENDERFILES=$(RENDERFILE_TOP) $(RENDERFILE_BOTTOM)
DUMMY_RENDERFILES=$(addsuffix _, $(RENDERFILES))
GENERATED_SCHEMFILE=../$(NAME).pdf
SCHEMFILE=Schematic-$(PRJNAME).pdf
STEPFILE=Model-3D-$(PCBNAME)-$(VARIANTNAME).STEP
DUMMY_STEPFILE="$(STEPFILE)_"
DUMMY_TARGETS=$(DUMMY_STEPFILE) $(DUMMY_RENDERFILES)
define MAKEFILE_SWITCHES
NAME="$(NAME)" PROJECT_DESC="$(PROJECT_DESC)" \
BOARDREV="$(BOARDREV)" BOARDREVMINOR="$(BOARDREVMINOR)" \
LAYERS="$(LAYERS)"
endef
define README_TEXT
"$(NAME) Rev $(PRJREV) \($(PROJECT_DESC)\)"\
|-----------------------------------------------------------------------------------------------|\
|This is the package for $(NAME) rev $(PRJREV).|\
|Service Requested\
|=================|\
| * Manufacturing and inspection to IPC class 3 standard.\
| * RoHS compliant\
| * PCB Material: FR4\
| * Solder mask color: Green\
| * Silk screen color: White\
| * Layers: $(LAYERS)\
| * Copper thickness: 1 oz all layers\
| * Finish: HASL|\
||Programming and labeling of microcontroller\
|===========================================|\
|None\
||Testing\
|=======\
| * Test 100% testing of assemblies\
| * Standard PCB QA (bed of nails, test for shorts and opens)\
|\
||Tracking\
|========|\
|None\
|\
||Packaging\
|=========|\
|Standard Packaging\
||Production Package\
|==================|\
|The ZIP file contains the following files:\
| $(PCBZIPFILE)\
|+++A ZIP file containing Gerbers; drill file;\
|+++readme.txt\
|++++++readme file containing PCB fabrication directions; fab renderings, etc.\
|\
|$(READMEFILE)\
|+++This letter.\
|\
|$(RENDERFILE_TOP)\
|+++A JPEG file containing a reference for PCB parts placement, and 3D renderings of the front of the populated board (with components).\
|\
|$(RENDERFILE_BOTTOM)\
|+++A JPEG file containing a reference for PCB parts placement, and 3D renderings of the back of the populated board (with components).\
|\
|$(STEPFILE):\
|+++An exported 3D STEP file of the PCB with all components fitted.\
|\
|$(SCHEMFILE)\
|+++A PDF file containing the schematics for this PCB.\
|\
|$(BOMFILE)\
|+++BOM file, csv format\
|\
|Subdirectory: labels_dir\
|+++:$(PROJNAME)_labels.doc: Labels for final packaging.\
|\
|Subdirectory: programming_files_dir\
|+++empty, not applicable.\
|\
|Subdirectory containing programming files\
|+++empty, not applicable\
|\
|Subdirectory: diagrams_dir\
|+++empty\
|\
|Subdirectory containing diagrams or pictures related to production\
|+++empty\
|\
|Subdirectory: work_instructions_dir\
|+++Subdirectory containing work instructions, test procedures, etc.|\
|.. figure:: ./$(RENDERFILE_TOP)|\
| TOP side rendering of populated PCB\
|.. figure:: ./$(RENDERFILE_BOTTOM)|\
| BOTTOM side rendering of populated PCB
endef
define RENDER_TOP_MSG
|------------------------------------------------------------------------\
|The assembly rendering \"$(RENDERFILE_TOP)\"\
|must be manually generated with the following steps:|\
|1) Bring up the 3D rendering from PCBNEW (ALT-3). Select\
|the TOP view (RightClick-"View Top").|\
|2) Perform a screen capture. Save the capture to the\
|production-package directory. Select the dummy file name|\
|" \"$(RENDERFILE_TOP)_\""|\
|and delete the trailing \"_\". Then click Save.
endef
define RENDER_BOTTOM_MSG
|------------------------------------------------------------------------\
|The assembly rendering \"$(RENDERFILE_BOTTOM)\"\
|must be manually generated with the following steps:|\
|1) Bring up the 3D rendering from PCBNEW (ALT-3). Select\
|the BOTTOM view (RightClick-"View Bottom").|\
|2) Perform a screen capture. Save the capture to the\
|production-package directory. Select the dummy file name|\
|" \"$(RENDERFILE_BOTTOM)_\""|\
|and delete the trailing \"_\". Then click Save.
endef
define BOM_MSG
|------------------------------------------------------------------------\
|The BOM file must be manually generated. The BOM file requires the KiBOM plugin.\
|Please ensure that KiBOM is installed. To generate the BOM file:\
|1) Copy the file 'bom.ini' in the templates directory to the main directory:\
|\" cp templates_dir/bom.ini ..\"\
|2) In EESChema, select Tools->Generate BOM.|\
|3) Select KIBOM_CLI and click \"Generate\"|
endef
define SCHEM_MSG
|------------------------------------------------------------------------\
|The Schematic PDF file must be manually generated:\
|1) In EESChema, select File->Plot to bring up the Plot dialog\
|2) Select PDF output format.\
|3) Check "Plot Drawing Sheet"\
|4) Click "Plot All Pages"
endef
define STEPFILE_MSG
|------------------------------------------------------------------------\
|The STEP file must be manually generated.\
|1) From PCBNEW, select File->Export->STEP\
|2) Check the following boxes:\
| - Board Center Origin\
| - Substitute similarly named models\
| - Overwrite old file\
|2) Save to the production package directory. Select the placeholder filename:\
|" $(STEPFILE)_"\
|3) Remove the trailing \"_\" and click "Save"
endef
# KiCad doesn't automate saving of rendering files, which must be
# screen-captured and saved as JPEG files. The STEP file must similarly be
# exported manually. the "dummies" target creates filename templates that can be
# selected and edited (by removing the trailing "_") to help ensure that the
all: dummies bomfile renderfiles schemfile $(READMETARGET) pkgzip subdirs
.phony: dummies
dummies:
@echo "$(DUMMY_TARGETS)" | xargs -n 1 echo "+++ Creating placeholder: "
@touch $(DUMMY_TARGETS)
.Phony: clean
clean:
rm -fv *.zip $(DUMMY_TARGETS) *~ *_ makefile.log
rm -fv *pdf *rst *csv
(cd PCB_dir; make $(MAKEFILE_SWITCHES) clean)
.phony: veryclean
veryclean: clean
rm -fv $(SCHEMFILE) $(RENDERFILES) $(BOMFILE)
rm -rfv *.jpg *.JPG *.pdf *.pdf *.png *.PNG
rm -f README* *rst *pdf *dvi
(cd PCB_dir; make $(MAKEFILE_SWITCHES) veryclean)
bominit: $(BOMINITFILE)
$(BOMINITFILE): $(BOMINITTEMPLATE)
cp -i $(BOMINITTEMPLATE) $(BOMINITFILE)
$(BOMFILE):
@if [ ! -f "$(GENERATED_BOMFILE)" ]; then \
echo "XXX Didn't find BOM: $(GENERATED_BOMFILE). See makefile.log. . .";\
echo "|$(BOM_MSG)|"|tr '|' '\n' >> makefile.log;\
else \
echo "--> Found BOM: $(GENERATED_BOMFILE). Copying. . .";\
cp $(GENERATED_BOMFILE) $(BOMFILE);\
fi
bomfile: $(BOMFILE)
$(SCHEMFILE):
@if [ ! -f "$(GENERATED_SCHEMFILE)" ]; then \
echo "XXX Didn't find Schematic PDF: $(GENERATED_SCHEMFILE). See makefile.log";\
echo "$(SCHEM_MSG)"|tr '|' '\n' >> makefile.log; \
else \
echo "--> Found Schematic PDF: $(GENERATED_SCHEMFILE)";\
cp $(GENERATED_SCHEMFILE) $(SCHEMFILE);\
fi
schemfile: $(SCHEMFILE)
$(STEPFILE):
@if [ ! -f "$(STEPFILE)" ]; then\
echo; \
echo "XXX Didn't find assembly STEP file: $(STEPFILE). See makefile.log"; \
echo "$(STEPFILE_MSG)"|tr '|' '\n' >> makefile.log; \
echo; \
else \
echo "--> Found assembly STEP file: $(STEPFILE)"; \
fi
.Phony: stepfile
stepfile: $(STEPFILE)
.Phony: renderfiles
renderfiles: renderfile_top renderfile_bottom
.Phony: renderfile_top
renderfile_top:
@if [ ! -f "$(RENDERFILE_TOP)" ]; then\
echo; \
echo "XXX Didn't find assembly rendering: $(RENDERFILE_TOP) See makefile.log"; \
echo "$(RENDER_BOTTOM_MSG)"|tr '|' '\n' >> makefile.log; \
echo; \
else \
echo "--> Found top assembly rendering: $(RENDERFILE_TOP)"; \
fi
.Phony: renderfile_bottom
renderfile_bottom:
@if [ ! -f "$(RENDERFILE_BOTTOM)" ]; then\
echo; \
echo "XXX Didn't find bottom assembly rendering: $(RENDERFILE_BOTTOM) See makefile.log"; \
echo "$(RENDER_TOP_MSG)"|tr '|' '\n' >> makefile.log; \
echo; \
else \
echo "--> Found bottom assembly rendering: $(RENDERFILE_BOTTOM)"; \
fi
pcbzip: $(PCBZIPFILE)
$(PCBZIPFILE):
echo "Building PCB Zip file..."; (cd $(PCBDIR); make $(MAKEFILE_SWITCHES) zip)
renderfiles: renderfile_top renderfile_bottom
readmetxt: $(READMEFILETXT)
readmepdf: $(READMEFILEPDF)
$(READMEFILETXT): Makefile
@echo "Creating Readme File $(READMEFILETXT)."; \
echo "$(README_TEXT)"|tr '|' '\n' | sed 's/+++/ /g' > $(READMEFILETXT);
$(READMEFILEPDF): $(READMEFILETXT)
@echo "Creating Readme File $(READMEFILEPDF)."; \
pandoc -f rst -t pdf -o "$(READMEFILEPDF)" "$(READMEFILETXT)";
.phony subdirs:
@mkdir -p $(SUBDIRS)
pkgzip: $(PCBZIPFILE) $(BOMFILE) $(RENDERFILES) $(READMEFILE) $(STEPFILE)
@echo removing old zip. . .; \
rm -rf $(PKGZIPFILE); \
echo creating zip. . .; \
zip -9r $(PKGZIPFILE) \
$(PCBZIPFILE) \
$(READMEFILETXT) \
$(READMEFILEPDF) \
$(SCHEMFILE) \
$(RENDERFILES) \
$(BOMFILE) \
$(STEPFILE) \
$(SUBDIRS)

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hardware/interface-ascii/production-package/PCB_dir/Makefile Executable file
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PROJECT_DESC="PCB"
NAME="PCB"
BOARDREV=1
BOARDREVMINOR=
LAYERS=2
SMT=no
#README_STYLE=rst
README_STYLE=pdf
PCBNAME=$(NAME)-Rev_$(BOARDREV)$(BOARDREVMINOR)
READMEFILEBASE=README-PCB-$(PCBNAME)
READMEFILETXT=$(READMEFILEBASE).rst
READMEFILEPDF=$(READMEFILEBASE).pdf
READMETARGET=readme$(README_STYLE)
TOP_SOLDER_EXT = gts
TOP_SOLDER_DSC = F_Mask
TOP_SOLDER_GBR = "$(PCBNAME)_$(TOP_SOLDER_DSC).$(TOP_SOLDER_EXT)"
TOP_COPPER_EXT = gtl
TOP_COPPER_DSC = F_Cu
TOP_COPPER_GBR = "$(PCBNAME)_$(TOP_COPPER_DSC).$(TOP_COPPER_EXT)"
TOP_SILK_EXT = gto
TOP_SILK_DSC = F_Silkscreen
TOP_SILK_GBR = "$(PCBNAME)_$(TOP_SILK_DSC).$(TOP_SILK_EXT)"
BOT_SOLDER_EXT = gbs
BOT_SOLDER_DSC = B_Mask
BOT_SOLDER_GBR = "$(PCBNAME)_$(BOT_SOLDER_DSC).$(BOT_SOLDER_EXT)"
BOT_COPPER_EXT = gbl
BOT_COPPER_DSC = B_Cu
BOT_COPPER_GBR = "$(PCBNAME)_$(BOT_COPPER_DSC).$(BOT_COPPER_EXT)"
BOT_SILK_EXT = gbo
BOT_SILK_DSC = B_Silkscreen
BOT_SILK_GBR = "$(PCBNAME)_$(BOT_SILK_DSC).$(BOT_SILK_EXT)"
OUTLN_EXT = gm1
OUTLN_DSC = Edge_Cuts
OUTLN_GBR = "$(PCBNAME)_$(OUTLN_DSC).$(OUTLN_EXT)"
DRILL_EXT = DRL
DRILL_PTH = "$(PCBNAME)-PTH.$(DRILL_EXT)"
DRILL_NPTH = "$(PCBNAME)-NPTH.$(DRILL_EXT)"
TOP_PASTE_EXT = gtp
TOP_PASTE_DSC = F_Paste
TOP_PASTE_GBR = "$(PCBNAME)_$(TOP_PASTE_DSC).$(TOP_PASTE_EXT)"
BOT_PASTE_EXT = gbp
BOT_PASTE_DSC = B_Paste
BOT_PASTE_GBR = "$(PCBNAME)_$(BOT_PASTE_DSC).$(BOT_PASTE_EXT)"
GND1_EXT = g2
GND1_DSC = In1_Cu
GND1_GBR = "$(PCBNAME)_$(GND1_DSC).$(GND1_EXT)"
GND2_EXT = g3
GND2_DSC = In2_Cu
GND2_GBR = "$(PCBNAME)_$(GND2_DSC).$(GND2_EXT)"
ifeq ($(SMT),yes)
PASTE_LAYERS= $(TOP_PASTE_GBR) $(BOT_PASTE_GBR)
endif
ifeq ($(LAYERS),4)
OUTPUT_EXTS = $(addprefix *., $(TOP_SOLDER_EXT) $(TOP_COPPER_EXT) $(TOP_SILK_EXT) \
$(BOT_SOLDER_EXT) $(BOT_COPPER_EXT) $(BOT_SILK_EXT) \
$(OUTLN_EXT) $(DRILL_EXT)) \
$(TOP_PASTE_EXT) $(BOT_PASTE_EXT) \
$(GND1_EXT) $(GND2_EXT)
define STACKUP_DESC
| * Stackup: All tolerances 10%\
| 1. Total thickness: 0.062 inch\
| 1. top layer 1oz copper\
| 1. prepreg 2x2116\
| 1. second layer 1oz copper\
| 1. core 0.039 inch core\
| 1. third layer 1oz copper\
| 1. prepreg 2x2116\
| 1. bottom layer 1oz copper
endef
define INNER_PLANE_DESC
|:INNER_PLANE 1: - :code:\`"$(GND1_GBR)"\`\
|:INNER_PLANE 2: - :code:\`"$(GND2_GBR)"\`
endef
INNER_PLANES = $(GND1_GBR) $(GND2_GBR)
define INNER_LAYERS
* In1.Cu\
| * In2.Cu
endef
endif
ifeq ($(LAYERS),2)
OUTPUT_EXTS = $(addprefix *., $(TOP_SOLDER_EXT) $(TOP_COPPER_EXT) $(TOP_SILK_EXT) \
$(BOT_SOLDER_EXT) $(BOT_COPPER_EXT) $(BOT_SILK_EXT) \
$(OUTLN_EXT) $(DRILL_EXT)) \
$(TOP_PASTE_EXT) $(BOT_PASTE_EXT)
define STACKUP_DESC
| * Stackup: All tolerances 10%\
| 1. Total thickness: 0.062 inch\
| 1. top layer 1oz copper\
| 1. core 0.059 inch\
| 1. bottom layer 1oz copper
endef
endif
DRILDIR = outputs
GERBDIR = outputs
FAB_TOP = $(PCBNAME)-render-top-view.jpg
FAB_BOTTOM = $(PCBNAME)-render-bottom-view.jpg
FAB_FILES = $(FAB_TOP) $(FAB_BOTTOM)
FAB_DUMMIES = $(FAB_TOP)_ $(FAB_BOTTOM)_
DUMMY_TARGETS = $(FAB_DUMMIES)
ZIPFILE = ../$(PCBNAME)-pcbfab.zip
define FAB_TOP_MSG
|------------------------------------------------------------------------\
|The assembly rendering \"$(FAB_TOP)\"\
|must be manually generated with the following steps:|\
|1) Bring up the 3D rendering from PCBNEW \(ALT-3\).|\
|2) Deselect the 3D model visibility for all components.|\
|3) Select the TOP view \(RightClick-"View Top"\).|\
|2) Perform a screen capture. Save the capture to the\
|\"production-package/PCB_dir\" directory. Select the dummy file name|\
|" \"$(FAB_TOP)_\""|\
|and delete the trailing \"_\". Then click Save.
endef
define FAB_BOTTOM_MSG
|------------------------------------------------------------------------\
|The assembly rendering \"$(FAB_BOTTOM)\"\
|must be manually generated with the following steps:|\
|1) Bring up the 3D rendering from PCBNEW \(ALT-3\).|\
|2) Deselect the 3D model visibility for all components.|\
|3) Select the BOTTOM view \(RightClick-"View Bottom"\).|\
|2) Perform a screen capture. Save the capture to the\
|\"production-package/PCB_dir\" directory. Select the dummy file name|\
|" \"$(FAB_BOTTOM)_\""|\
|and delete the trailing \"_\". Then click Save.
endef
define README_TEXT
"$(NAME) Rev $(BOARDREV) \($(PROJECT_DESC)\)"\
|------------------------------------------------------------------------------------|\
||:Board: "$(BASENAME)"\
||Service\
|=======|\
| * Manufacturing and inspection to IPC class 3 standard.\
| * PCB Material: FR4\
| * Solder mask color: Green\
| * Silk screen color: White\
| * Layers: $(LAYERS)\
| * Copper thickness: 1 oz all layers\
| * Finish: HASL|\
$(STACKUP_DESC)\
|\
|Files\
|=====|\
|:BOARD OUTLINE: - :code:\`"$(OUTLN_GBR)"\`\
|:TOP LAYER: - :code:\`"$(TOP_COPPER_GBR)"\`\
$(INNER_PLANE_DESC)\
|:BOTTOM LAYER: - :code:\`"$(BOT_COPPER_GBR)"\`\
|:TOP SOLDER MASK: - :code:\`"$(TOP_PASTE_GBR)"\`\
|:BOTTOM SOLDER MASK: - :code:\`"$(BOT_PASTE_GBR)"\`\
|:TOP PASTE MASK: - :code:\`"$(TOP_PASTE_GBR)"\`\
|:BOTTOM PASTE MASK: - :code:\`"$(BOT_PASTE_GBR)"\`\
|:TOP SILK SCREEN: - :code:\`"$(TOP_SILK_GBR)"\`\
|:BOTTOM SILK SCREEN: - :code:\`"$(BOT_SILK_GBR)"\`\
|:EXCELLON DRILL (Plated): - :code:\`"$(DRILL_PTH)"\`\
|:EXCELLON DRILL (Non-plated): :code:\`"$(DRILL_NPTH)"\`\
||Fab Drawings\
|============|\
|:$(FAB_TOP): - :code:\`3D rendering of the top of the bare PCB\`\
|:$(FAB_BOTTOM): - :code:\`3D rendering of the bottom of the bare PCB\`\
|\
|.. figure:: ./$(FAB_TOP)||\
| TOP side rendering of bare PCB||\
|.. figure:: ./$(FAB_BOTTOM)||\
| BOTTOM side rendering of bare PCB||\
|General Info\
|============|\
| * This board was developed with Kicad 6\
| * The Gerber files are in 2.5 RS274X format.\
||Special Instructions\
|====================|\
| * Please note there are TWO Excellon Drill files, one for plated through holes (PTH), and one for non-plated through holes (NPTH).\
| * The board outline is delineated in the Gerber file "$(OUTLN_GBR)"|\
|Thanks.
endef
define DRL_FAIL
|Missing drill file. To generate the drill files, within PCBNew:|\
|- Select File->Plot. Click "Generate Drill Files" at the bottom right side of the dialog.\
|- Select the following options:\
| * Excellon, \"Use route command\"\
| * Drill origin: Absolute\
| * Drill units: inches\
| * Zeros Format: Decimal format\
| * Precision: 2.4\
|- Select \"Generate Drill File\"|
endef
define GBR_FAIL
|Missing gerber file. To generate the gerber files, within PCBNew:|\
|- Select File->Plot. Click "Generate Drill Files" at the bottom right side of the dialog.\
|- Select the following layers:\
| * F.Cu\
| * B.Cu\
| * F.Silkscreen\
| * B.Silkscreen|\
$(INNER_LAYERS)\
| * F.Paste\
| * B.Paste\
| * F.Mask\
| * B.Mask\
| * Edge.Cuts|
endef
all: dummies copy renderfiles $(READMETARGET)
readmetxt: $(READMEFILETXT)
readmepdf: $(READMEFILEPDF)
$(READMEFILETXT): Makefile
@echo "Creating Readme File $(READMEFILETXT)."; \
echo "$(README_TEXT)"|tr '|' '\n' | sed 's/+++/ /g' > $(READMEFILETXT);
$(READMEFILEPDF): $(READMEFILETXT)
@echo "Creating Readme File $(READMEFILEPDF)."; \
pandoc -f rst -t pdf -o "$(READMEFILEPDF)" "$(READMEFILETXT)";
.Phony: renderfiles
renderfiles: renderfile_top renderfile_bottom
.Phony: renderfile_top
renderfile_top:
@if [ ! -f "$(FAB_TOP)" ]; then\
echo; \
echo "XXX Didn't find top assembly rendering: $(FAB_TOP). See makefile.log"; \
echo "|$(FAB_TOP_MSG)|"|tr '|' '\n' >> makefile.log; \
echo; \
else \
echo "--> Found top assembly rendering: $(FAB_TOP)"; \
fi
.Phony: renderfile_bottom
renderfile_bottom:
@if [ ! -f "$(FAB_BOTTOM)" ]; then\
echo; \
echo "XXX Didnt' find assembly rendering $(FAB_BOTTOM). See makefile.log";\
echo "|$(FAB_TOP_MSG)|"|tr '|' '\n' >> makefile.log; \
echo; \
else \
echo "--> Found bottom assembly rendering: $(FAB_BOTTOM)"; \
fi
renderfiles: renderfile_top renderfile_bottom
clean:
rm -f $(OUTPUT_EXTS) *rst *pdf *.zip $(DUMMY_TARGETS) *_
rm -f makefile.log
veryclean:
rm -rfv outputs $(PCBNAME)* $(NAME)*
rm -rfv *.jpg *.JPG *.pdf *.pdf *.png *.PNG
rm -f README* *rst *pdf *dvi
.PHONY: dummies
dummies:
@echo "Making placeholder filenames:"
@echo "$(DUMMY_TARGETS)" | xargs -n 1 echo +++
@touch $(DUMMY_TARGETS)
gvp: gvp_template.gvp
sed -e "s/@@NAME@@/$(PCBNAME)/" < $< > $(PCBNAME).gvp
copy:
cp $(DRILDIR)/$(NAME)-PTH.$(DRILL_EXT) $(DRILL_PTH) || echo "$(DRILL_FAIL)"|tr '|' '\n'
cp $(DRILDIR)/$(NAME)-NPTH.$(DRILL_EXT) $(DRILL_NPTH) || echo "$(DRILL_FAIL)"|tr '|' '\n'
cp $(GERBDIR)/$(NAME)-$(TOP_SOLDER_DSC).$(TOP_SOLDER_EXT) $(TOP_SOLDER_GBR) || echo "$(GBR_FAIL)" | tr '|' '\n'
cp $(GERBDIR)/$(NAME)-$(TOP_COPPER_DSC).$(TOP_COPPER_EXT) ./$(TOP_COPPER_GBR)
cp $(GERBDIR)/$(NAME)-$(TOP_SILK_DSC).$(TOP_SILK_EXT) ./$(TOP_SILK_GBR)
cp $(GERBDIR)/$(NAME)-$(BOT_SILK_DSC).$(BOT_SILK_EXT) ./$(BOT_SILK_GBR)
cp $(GERBDIR)/$(NAME)-$(BOT_SOLDER_DSC).$(BOT_SOLDER_EXT) ./$(BOT_SOLDER_GBR)
cp $(GERBDIR)/$(NAME)-$(BOT_COPPER_DSC).$(BOT_COPPER_EXT) ./$(BOT_COPPER_GBR)
ifeq ($(SMT),yes)
cp $(GERBDIR)/$(NAME)-$(TOP_PASTE_DSC).$(TOP_PASTE_EXT) ./$(TOP_PASTE_GBR)
cp $(GERBDIR)/$(NAME)-$(BOT_PASTE_DSC).$(BOT_PASTE_EXT) ./$(BOT_PASTE_GBR)
endif
ifeq ($(LAYERS),4)
cp $(GERBDIR)/$(NAME)-$(GND1_DSC).$(GND1_EXT) ./$(GND1_GBR)
cp $(GERBDIR)/$(NAME)-$(GND2_DSC).$(GND2_EXT) ./$(GND2_GBR)
endif
cp $(GERBDIR)/$(NAME)-$(OUTLN_DSC).$(OUTLN_EXT) ./$(OUTLN_GBR)
gerbv:
gerbv \
$(OUTLN_GBR) \
$(DRILL_PTH) \
$(DRILL_NPTH) \
$(TOP_SOLDER_GBR) \
$(TOP_COPPER_GBR) \
$(PASTE_LAYERS) \
$(TOP_SILK_GBR) \
$(BOT_SILK_GBR) \
$(BOT_SOLDER_GBR) \
$(BOT_COPPER_GBR) \
$(INNER_PLANES) \
$(BOT_SILK_GBR)
zip: all
rm -f $(ZIPFILE)
zip -9 $(ZIPFILE) \
$(OUTLN_GBR) \
$(DRILL_PTH) \
$(DRILL_NPTH) \
$(TOP_SOLDER_GBR) \
$(TOP_COPPER_GBR) \
$(PASTE_LAYERS) \
$(TOP_SILK_GBR) \
$(BOT_SOLDER_GBR) \
$(BOT_COPPER_GBR) \
$(BOT_SILK_GBR) \
$(INNER_PLANES) \
$(FAB_FILES) \
$(READMEFILEPDF) \
$(READMEFILETXT)

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Firmware Downloads
==================
Download the latest release of the firmware [here](https://osiweb.github.io/unified_retro_keyboard)

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[BOM_OPTIONS]
; General BoM options here
; If 'ignore_dnf' option is set to 1, rows that are not to be fitted on the PCB will not be written to the BoM file
ignore_dnf = 0
; If 'html_generate_dnf' option is set to 1, also generate a list of components not fitted on the PCB (HTML only)
html_generate_dnf = 1
; If 'use_alt' option is set to 1, grouped references will be printed in the alternate compressed style eg: R1-R7,R18
use_alt = 1
; If 'alt_wrap' option is set to and integer N, the references field will wrap after N entries are printed
alt_wrap = 0
; If 'number_rows' option is set to 1, each row in the BoM will be prepended with an incrementing row number
number_rows = 1
; If 'group_connectors' option is set to 1, connectors with the same footprints will be grouped together, independent of the name of the connector
group_connectors = 1
; If 'test_regex' option is set to 1, each component group will be tested against a number of regular-expressions (specified, per column, below). If any matches are found, the row is ignored in the output file
test_regex = 1
; If 'merge_blank_fields' option is set to 1, component groups with blank fields will be merged into the most compatible group, where possible
merge_blank_fields = 1
; Specify output file name format, %O is the defined output name, %v is the version, %V is the variant name which will be ammended according to 'variant_file_name_format'.
output_file_name = %O_bom_%v%V
; Specify the variant file name format, this is a unique field as the variant is not always used/specified. When it is unused you will want to strip all of this.
variant_file_name_format = _(%V)
; Field name used to determine if a particular part is to be fitted
fit_field = Fitted
; Make a backup of the bom before generating the new one, using the following template
make_backup = %O.tmp
; Default number of boards to produce if none given on CLI with -n
number_boards = 1
; Default PCB variant if none given on CLI with -r
board_variant = ['default']
; Whether to hide headers from output file
hide_headers = False
; Whether to hide PCB info from output file
hide_pcb_info = False
[IGNORE_COLUMNS]
; Any column heading that appears here will be excluded from the Generated BoM
; Titles are case-insensitive
Class
Component Type
Footprint
Footprint Lib
Material
Number of Pins
Package Variant
Part
Part Lib
Power Rating
RoHS China Link
RoHS Europe Link
SheetPath
Standards Version
Temp (Operating)
Temp (Soldering)
Temp (Storage)
Temp Coeff.
Tolerance
Value
Voltage Rating
Current Rating
[COLUMN_ORDER]
; Columns will apear in the order they are listed here
; Titles are case-insensitive
References
Fitted
Quantity Per PCB
Description
Part Value
Manufacturer
Manufacturer PN
Label
BOM Comment
[GROUP_FIELDS]
; List of fields used for sorting individual components into groups
; Components which match (comparing *all* fields) will be grouped together
; Field names are case-insensitive
Part
Part Lib
Value
Footprint
Footprint Lib
[COMPONENT_ALIASES]
; A series of values which are considered to be equivalent for the part name
; Each line represents a list of equivalent component name values separated by white space
; e.g. 'c c_small cap' will ensure the equivalent capacitor symbols can be grouped together
; Aliases are case-insensitive
c c_small cap capacitor
r r_small res resistor
sw switch
l l_small inductor
zener zenersmall
d diode d_small
[REGEX_INCLUDE]
; A series of regular expressions used to include parts in the BoM
; If there are any regex defined here, only components that match against ANY of them will be included in the BOM
; Column names are case-insensitive
; Format is: "[ColumName] [Regex]" (white-space separated)
[REGEX_EXCLUDE]
; A series of regular expressions used to exclude parts from the BoM
; If a component matches ANY of these, it will be excluded from the BoM
; Column names are case-insensitive
; Format is: "[ColumName] [Regex]" (white-space separated)
References ^TP[0-9]*
References ^FID
Part mount.*hole
Part solder.*bridge
Part test.*point
Footprint test.*point
Footprint mount.*hole
Footprint fiducial
Allow Substitution
Tracking
Package
Manufacturer Link
Component Value
Datasheet