mirror of
https://github.com/osiweb/unified_retro_keyboard.git
synced 2024-12-21 15:29:21 +00:00
Add Apple-2 encoder, a custimized version of the 2560 ASCII encoder
This commit is contained in:
Dave
parent
b6599dd9e2
commit
34f727e1e2
67
hardware/apple2-encoder/README.md
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67
hardware/apple2-encoder/README.md
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# Apple II/II+ Encoder
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This is a version of the ASCII interface wired up to be compatible with the
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Apple II/Apple II+ keyboard matrix. This board was broken out as a separate PCB
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from the Atmega2560-based interface board on which it was based, in order to
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keep the "custom" connector customizable on that board.
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This board is otherwise identical to rev 3.4 of the ATMega2560-based ASCII interface board, and shares the same firmware and features.
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<img alt="Assembly Rendering" src="images/PCB-assembly-rendering.png" height=75%
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width=75%>
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## Features
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- Parallel or serial output
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- Up to 8 configuration settings via an up-to-8 position DIP switch
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- Apple 1, Apple 2, and SOL-20 compatible outputs. Other configurations can be
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supported by making a custom cable.
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- Can decode arbitrary keyboards up 16 rows by 8 columns.
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- Supports up to 3 keyboard LEDs
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- Supports up to 3 "special" host outputs, such as RESET, SCREEN_CLEAR, BREAK, etc.
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- Socket for custom connector
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## Assembly Notes
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1. You may build this board as if it is a general purpose ASCII interface. In
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that case, you may want to avoid installing the 1x25 Apple2 keyboard header
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if it interferes with the target keyboard matrix. Also, for use with a key
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matrix that already has a diode for each key (or each row), you will need to
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install jumpers across the footprints for diodes D1-D16.
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1. If you ARE building this board as an Apple 2 encoder, then you may omit:
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1. OMIT Sol-20 connector J5
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1. OMIT Custom connector J7
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1. OMIT D17,D18,D19 - These are used for the "classic" keyboard matrix.
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1. OMIT D7,D8,D15,D16 - These are diodes for rows 12-15, which are not used.
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1. OMIT the serial out connector J3 if you do not plan to use a serial output.
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1. OMIT the I/O connector J4, as all the I/O lines are routed through the
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keyboard connector.
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1. OMIT RN1. Not needed since the microprocessor uses internal pullups.
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1. If you will be using the keyboard with only an Apple 1 or Apple 2, then
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you do not need to install both the Apple 2 connector (J1) AND the Apple
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1 connector (J2). You may install only the one you plan to use, and
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reduce the risk of plugging into the wrong socket (and possibly damaging
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the encoder).
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1. Solder the surface-mount microcontroller first. Be sure to match pin 1 to the
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dot on the silk-screen layer.
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1. Next, install the surface mount crystal, Y1. The orientation is not important.
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1. Next, solder in the diodes D1-D7, D9-D14, and 20-D27
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1. Install all the capacitors. These are all 0.1 uF ceramic capacitors with 0.1"
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lead spacing. Many capacitors with 0.2" lead spacing are actually 0.1"
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emerging from the body, bent to 0.2", and can be straightened back to 0.1".
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1. Next, solder in the resitor R1 and Resistor network RN1.
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1. Install DIP switch SW1.
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1. Install the In-circuit Serial Programming (ISP) header, J6. (right-angle, 2x3
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0.100")
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1. If you will be using the Apple 1 connector, install the DIP socket J1 (16-pin
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dip). If you plan to insert and remove the cable many times, a dual-wipe
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socket may be preferable to machine-pin, since it has a lower insertion
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force, and you will be less likely to bend pins. If you plan to insert the
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cable once and leave it forever, I suggest a machine-pin DIP socket.
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1. If you will be using the Apple 2 connector, install the DIP socket J2 (16-pin
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dip). The note for the Apple 1 connector selection applies here as well.
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7553
hardware/apple2-encoder/apple-encoder.kicad_pcb
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7553
hardware/apple2-encoder/apple-encoder.kicad_pcb
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File diff suppressed because it is too large
Load Diff
277
hardware/apple2-encoder/apple-encoder.pro
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277
hardware/apple2-encoder/apple-encoder.pro
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@ -0,0 +1,277 @@
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update=Tuesday, June 02, 2020 at 09:57:01 PM
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version=1
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last_client=kicad
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[general]
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version=1
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RootSch=
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BoardNm=
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[cvpcb]
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version=1
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NetIExt=net
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[eeschema]
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version=1
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LibDir=
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[eeschema/libraries]
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[pcbnew]
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version=1
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PageLayoutDescrFile=
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LastNetListRead=unikbd.net
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CopperLayerCount=2
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BoardThickness=1.6
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AllowMicroVias=0
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AllowBlindVias=0
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RequireCourtyardDefinitions=0
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ProhibitOverlappingCourtyards=1
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MinTrackWidth=0.2
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MinViaDiameter=0.4
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MinViaDrill=0.3
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MinMicroViaDiameter=0.2
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MinMicroViaDrill=0.09999999999999999
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MinHoleToHole=0.25
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TrackWidth2=0.254
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TrackWidth3=0.508
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TrackWidth4=1.27
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ViaDiameter1=0.8128
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ViaDrill1=0.4064
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ViaDiameter2=1.27
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ViaDrill2=0.7112
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ViaDiameter3=1.5748
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ViaDrill3=0.8128
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dPairWidth1=0.2032
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dPairGap1=0.254
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dPairViaGap1=0.25
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SilkLineWidth=0.12
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SilkTextSizeV=1
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SilkTextSizeH=1
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SilkTextSizeThickness=0.15
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SilkTextItalic=0
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SilkTextUpright=1
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CopperLineWidth=0.2
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CopperTextSizeV=1.5
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CopperTextSizeH=1.5
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CopperTextThickness=0.3
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CopperTextItalic=0
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CopperTextUpright=1
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EdgeCutLineWidth=0.05
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CourtyardLineWidth=0.05
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OthersLineWidth=0.15
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OthersTextSizeV=1
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OthersTextSizeH=1
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OthersTextSizeThickness=0.15
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OthersTextItalic=0
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OthersTextUpright=1
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SolderMaskClearance=0
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SolderMaskMinWidth=0
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SolderPasteClearance=0
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SolderPasteRatio=-0
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[pcbnew/Layer.F.Cu]
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[pcbnew/Layer.In1.Cu]
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[pcbnew/Layer.In2.Cu]
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[pcbnew/Layer.In3.Cu]
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Name=In3.Cu
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[pcbnew/Layer.In4.Cu]
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[pcbnew/Layer.In5.Cu]
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[pcbnew/Layer.In6.Cu]
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[pcbnew/Layer.In7.Cu]
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[pcbnew/Layer.In9.Cu]
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[pcbnew/Layer.In13.Cu]
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[pcbnew/Layer.In14.Cu]
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Name=In14.Cu
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Enabled=0
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[pcbnew/Layer.In15.Cu]
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Name=In15.Cu
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[pcbnew/Layer.In16.Cu]
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Name=In16.Cu
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[pcbnew/Layer.In17.Cu]
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[pcbnew/Layer.In18.Cu]
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Name=In18.Cu
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[pcbnew/Layer.In19.Cu]
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[pcbnew/Layer.In20.Cu]
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[pcbnew/Layer.In21.Cu]
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[pcbnew/Layer.In22.Cu]
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[pcbnew/Layer.In23.Cu]
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Name=In23.Cu
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[pcbnew/Layer.In24.Cu]
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[pcbnew/Layer.In25.Cu]
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[pcbnew/Layer.In26.Cu]
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Name=In26.Cu
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||||
[pcbnew/Layer.In27.Cu]
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Name=In27.Cu
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[pcbnew/Layer.In28.Cu]
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[pcbnew/Layer.In29.Cu]
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[pcbnew/Layer.In30.Cu]
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Name=In30.Cu
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||||
[pcbnew/Layer.B.Cu]
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||||
Enabled=1
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||||
[pcbnew/Layer.B.Adhes]
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||||
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||||
[pcbnew/Layer.F.Adhes]
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||||
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||||
[pcbnew/Layer.B.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Paste]
|
||||
Enabled=1
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||||
[pcbnew/Layer.B.SilkS]
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||||
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|
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[pcbnew/Layer.F.SilkS]
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||||
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|
||||
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|
||||
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|
||||
[pcbnew/Layer.F.Mask]
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||||
Enabled=1
|
||||
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||||
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|
||||
[pcbnew/Layer.Cmts.User]
|
||||
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|
||||
[pcbnew/Layer.Eco1.User]
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||||
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|
||||
[pcbnew/Layer.Eco2.User]
|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
[pcbnew/Layer.B.CrtYd]
|
||||
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|
||||
[pcbnew/Layer.F.CrtYd]
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||||
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|
||||
[pcbnew/Layer.B.Fab]
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Enabled=1
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||||
[pcbnew/Layer.F.Fab]
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||||
Enabled=1
|
||||
[pcbnew/Layer.Rescue]
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||||
Enabled=0
|
||||
[pcbnew/Netclasses]
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||||
[pcbnew/Netclasses/Default]
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||||
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||||
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||||
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||||
ViaDiameter=0.8128
|
||||
ViaDrill=0.4064
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||||
uViaDiameter=0.3048
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||||
uViaDrill=0.1016
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||||
dPairWidth=0.2032
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||||
dPairGap=0.254
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||||
dPairViaGap=0.25
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||||
[pcbnew/Netclasses/1]
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||||
Name=power1
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||||
Clearance=0.1524
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||||
TrackWidth=1.27
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||||
ViaDiameter=1.27
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||||
ViaDrill=0.7112
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||||
uViaDiameter=0.3048
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||||
uViaDrill=0.1016
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||||
dPairWidth=0.2032
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||||
dPairGap=0.254
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||||
dPairViaGap=0.25
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||||
[pcbnew/Netclasses/2]
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||||
Name=signal
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||||
Clearance=0.1524
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||||
TrackWidth=0.254
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||||
ViaDiameter=0.8128
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||||
ViaDrill=0.4064
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||||
uViaDiameter=0.3048
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||||
uViaDrill=0.1016
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||||
dPairWidth=0.2032
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||||
dPairGap=0.254
|
||||
dPairViaGap=0.25
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||||
[schematic_editor]
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version=1
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||||
PageLayoutDescrFile=
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PlotDirectoryName=
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SubpartIdSeparator=0
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||||
SubpartFirstId=65
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||||
NetFmtName=
|
||||
SpiceAjustPassiveValues=0
|
||||
LabSize=50
|
||||
ERC_TestSimilarLabels=1
|
||||
2213
hardware/apple2-encoder/apple-encoder.sch
Normal file
2213
hardware/apple2-encoder/apple-encoder.sch
Normal file
File diff suppressed because it is too large
Load Diff
BIN
hardware/apple2-encoder/images/PCB-assembly-rendering.png
Normal file
BIN
hardware/apple2-encoder/images/PCB-assembly-rendering.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 241 KiB |
194
hardware/apple2-encoder/interface-ascii.lib
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194
hardware/apple2-encoder/interface-ascii.lib
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@ -0,0 +1,194 @@
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EESchema-LIBRARY Version 2.4
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#encoding utf-8
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#
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# 74LS166
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#
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DEF 74LS166 U 0 40 Y Y 1 L N
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F0 "U" -300 850 50 H V C CNN
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F1 "74LS166" -300 -850 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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DIP?16*
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$ENDFPLIST
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DRAW
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S -300 800 300 -800 1 1 10 f
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X Ds 1 -500 700 200 R 50 50 1 0 I
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X D3 10 500 200 200 L 50 50 1 0 I
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||||
X D2 11 500 100 200 L 50 50 1 0 I
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||||
X D1 12 500 0 200 L 50 50 1 0 I
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||||
X Qh 13 -500 200 200 R 50 50 1 0 O
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||||
X D0 14 500 -100 200 L 50 50 1 0 I
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||||
X SH_~LD 15 -500 50 200 R 50 50 1 0 I
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||||
X VCC 16 0 1000 200 D 50 50 1 0 W
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X D7 2 500 600 200 L 50 50 1 0 I
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||||
X D6 3 500 500 200 L 50 50 1 0 I
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||||
X D5 4 500 400 200 L 50 50 1 0 I
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||||
X D4 5 500 300 200 L 50 50 1 0 I
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||||
X CK_INH 6 -500 -500 200 R 50 50 1 0 I
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||||
X CLK 7 -500 -100 200 R 50 50 1 0 I C
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X GND 8 0 -1000 200 U 50 50 1 0 W
|
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X Clr 9 -500 600 200 R 50 50 1 0 I I
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||||
ENDDRAW
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||||
ENDDEF
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||||
#
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# ATmega328P-PU-MCU_Microchip_ATmega
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#
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DEF ATmega328P-PU-MCU_Microchip_ATmega U 0 20 Y Y 1 F N
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F0 "U" -500 1450 50 H V L BNN
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||||
F1 "ATmega328P-PU-MCU_Microchip_ATmega" 100 -1450 50 H V L TNN
|
||||
F2 "Package_DIP:DIP-28_W7.62mm" 0 0 50 H I C CIN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
DIP*W7.62mm*
|
||||
$ENDFPLIST
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||||
DRAW
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||||
S -500 -1400 500 1400 0 1 10 f
|
||||
X ~RESET 1 600 -300 100 L 50 50 1 1 T
|
||||
X PB7 10 600 500 100 L 50 50 1 1 T
|
||||
X PD5 11 600 -1000 100 L 50 50 1 1 T
|
||||
X PD6 12 600 -1100 100 L 50 50 1 1 T
|
||||
X PD7 13 600 -1200 100 L 50 50 1 1 T
|
||||
X PB0 14 600 1200 100 L 50 50 1 1 T
|
||||
X PB1 15 600 1100 100 L 50 50 1 1 T
|
||||
X PB2 16 600 1000 100 L 50 50 1 1 T
|
||||
X MOSI 17 600 900 100 L 50 50 1 1 T
|
||||
X MISO/PB4 18 600 800 100 L 50 50 1 1 T
|
||||
X SCK/PB5 19 600 700 100 L 50 50 1 1 T
|
||||
X PD0 2 600 -500 100 L 50 50 1 1 T
|
||||
X AVCC 20 100 1500 100 D 50 50 1 1 W
|
||||
X AREF 21 -600 1200 100 R 50 50 1 1 P
|
||||
X GND 22 0 -1500 100 U 50 50 1 1 P N
|
||||
X PC0 23 600 300 100 L 50 50 1 1 T
|
||||
X PC1 24 600 200 100 L 50 50 1 1 T
|
||||
X PC2 25 600 100 100 L 50 50 1 1 T
|
||||
X PC3 26 600 0 100 L 50 50 1 1 T
|
||||
X PC4 27 600 -100 100 L 50 50 1 1 T
|
||||
X PC5 28 600 -200 100 L 50 50 1 1 T
|
||||
X PD1 3 600 -600 100 L 50 50 1 1 T
|
||||
X PD2 4 600 -700 100 L 50 50 1 1 T
|
||||
X PD3 5 600 -800 100 L 50 50 1 1 T
|
||||
X PD4 6 600 -900 100 L 50 50 1 1 T
|
||||
X VCC 7 0 1500 100 D 50 50 1 1 W
|
||||
X GND 8 0 -1500 100 U 50 50 1 1 W
|
||||
X PB6 9 600 600 100 L 50 50 1 1 T
|
||||
ENDDRAW
|
||||
ENDDEF
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||||
#
|
||||
# ATmega640V-8AU
|
||||
#
|
||||
DEF ATmega640V-8AU U 0 20 Y Y 1 F N
|
||||
F0 "U" 0 50 50 H V C BNN
|
||||
F1 "ATmega640V-8AU" 0 300 50 H V C TNN
|
||||
F2 "Package_QFP:TQFP-100_14x14mm_P0.5mm" 0 550 50 H I C CIN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
ALIAS ATmega640-16AU ATmega1280V-8AU ATmega1280-16AU ATmega2560V-8AU ATmega2560-16AU
|
||||
$FPLIST
|
||||
TQFP*14x14mm*P0.5mm*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -650 -3350 650 2750 0 1 10 f
|
||||
X PG5 1 800 -2100 150 L 50 50 1 1 B
|
||||
X VCC 10 100 2900 150 D 50 50 1 1 W
|
||||
X AVCC 100 300 2900 150 D 50 50 1 1 W
|
||||
X GND 11 200 -3500 150 U 50 50 1 1 W
|
||||
X PH0 12 -800 -2200 150 R 50 50 1 1 B
|
||||
X PH1 13 -800 -2300 150 R 50 50 1 1 B
|
||||
X PH2 14 -800 -2400 150 R 50 50 1 1 B
|
||||
X PH3 15 -800 -2500 150 R 50 50 1 1 B
|
||||
X PH4 16 -800 -2600 150 R 50 50 1 1 B
|
||||
X PH5 17 -800 -2700 150 R 50 50 1 1 B
|
||||
X PH6 18 -800 -2800 150 R 50 50 1 1 B
|
||||
X PB0 19 -800 0 150 R 50 50 1 1 B
|
||||
X RXD0/PE0 2 -800 -1000 150 R 50 50 1 1 B
|
||||
X SCK/PB1 20 -800 -100 150 R 50 50 1 1 B
|
||||
X MOSI/PB2 21 -800 -200 150 R 50 50 1 1 B
|
||||
X MISO/PB3 22 -800 -300 150 R 50 50 1 1 B
|
||||
X PB4 23 -800 -400 150 R 50 50 1 1 B
|
||||
X PB5 24 -800 -500 150 R 50 50 1 1 B
|
||||
X PB6 25 -800 -600 150 R 50 50 1 1 B
|
||||
X PB7 26 -800 -700 150 R 50 50 1 1 B
|
||||
X PH7 27 -800 -2900 150 R 50 50 1 1 B
|
||||
X PG3 28 800 -1900 150 L 50 50 1 1 B
|
||||
X PG4 29 800 -2000 150 L 50 50 1 1 B
|
||||
X TXD0/PE1 3 -800 -1100 150 R 50 50 1 1 B
|
||||
X ~RESET 30 -800 2200 150 R 50 50 1 1 I
|
||||
X VCC 31 0 2900 150 D 50 50 1 1 W
|
||||
X GND 32 100 -3500 150 U 50 50 1 1 W
|
||||
X XTAL2 33 -800 2400 150 R 50 50 1 1 O
|
||||
X XTAL1 34 -800 2600 150 R 50 50 1 1 I
|
||||
X PL0 35 800 -600 150 L 50 50 1 1 B
|
||||
X PL1 36 800 -700 150 L 50 50 1 1 B
|
||||
X PL2 37 800 -800 150 L 50 50 1 1 B
|
||||
X PL3 38 800 -900 150 L 50 50 1 1 B
|
||||
X PL4 39 800 -1000 150 L 50 50 1 1 B
|
||||
X PE2 4 -800 -1200 150 R 50 50 1 1 B
|
||||
X PL5 40 800 -1100 150 L 50 50 1 1 B
|
||||
X PL6 41 800 -1200 150 L 50 50 1 1 B
|
||||
X PL7 42 800 -1300 150 L 50 50 1 1 B
|
||||
X PD0 43 800 -2300 150 L 50 50 1 1 B
|
||||
X PD1 44 800 -2400 150 L 50 50 1 1 B
|
||||
X PD2 45 800 -2500 150 L 50 50 1 1 B
|
||||
X PD3 46 800 -2600 150 L 50 50 1 1 B
|
||||
X PD4 47 800 -2700 150 L 50 50 1 1 B
|
||||
X PD5 48 800 -2800 150 L 50 50 1 1 B
|
||||
X PD6 49 800 -2900 150 L 50 50 1 1 B
|
||||
X PE3 5 -800 -1300 150 R 50 50 1 1 B
|
||||
X PD7 50 800 -3000 150 L 50 50 1 1 B
|
||||
X PG0 51 800 -1600 150 L 50 50 1 1 B
|
||||
X PG1 52 800 -1700 150 L 50 50 1 1 B
|
||||
X PC0 53 800 2400 150 L 50 50 1 1 B
|
||||
X PC1 54 800 2300 150 L 50 50 1 1 B
|
||||
X PC2 55 800 2200 150 L 50 50 1 1 B
|
||||
X PC3 56 800 2100 150 L 50 50 1 1 B
|
||||
X PC4 57 800 2000 150 L 50 50 1 1 B
|
||||
X PC5 58 800 1900 150 L 50 50 1 1 B
|
||||
X PC6 59 800 1800 150 L 50 50 1 1 B
|
||||
X PE4 6 -800 -1400 150 R 50 50 1 1 B
|
||||
X PC7 60 800 1700 150 L 50 50 1 1 B
|
||||
X VCC 61 -100 2900 150 D 50 50 1 1 W
|
||||
X GND 62 0 -3500 150 U 50 50 1 1 W
|
||||
X PJ0 63 800 1400 150 L 50 50 1 1 B
|
||||
X PJ1 64 800 1300 150 L 50 50 1 1 B
|
||||
X PJ2 65 800 1200 150 L 50 50 1 1 B
|
||||
X PJ3 66 800 1100 150 L 50 50 1 1 B
|
||||
X PJ4 67 800 1000 150 L 50 50 1 1 B
|
||||
X PJ5 68 800 900 150 L 50 50 1 1 B
|
||||
X PJ6 69 800 800 150 L 50 50 1 1 B
|
||||
X PE5 7 -800 -1500 150 R 50 50 1 1 B
|
||||
X PG2 70 800 -1800 150 L 50 50 1 1 B
|
||||
X PA7 71 800 -300 150 L 50 50 1 1 B
|
||||
X PA6 72 800 -200 150 L 50 50 1 1 B
|
||||
X PA5 73 800 -100 150 L 50 50 1 1 B
|
||||
X PA4 74 800 0 150 L 50 50 1 1 B
|
||||
X PA3 75 800 100 150 L 50 50 1 1 B
|
||||
X PA2 76 800 200 150 L 50 50 1 1 B
|
||||
X PA1 77 800 300 150 L 50 50 1 1 B
|
||||
X PA0 78 800 400 150 L 50 50 1 1 B
|
||||
X PJ7 79 800 700 150 L 50 50 1 1 B
|
||||
X PE6 8 -800 -1600 150 R 50 50 1 1 B
|
||||
X VCC 80 -200 2900 150 D 50 50 1 1 W
|
||||
X GND 81 -100 -3500 150 U 50 50 1 1 W
|
||||
X PK7 82 -800 200 150 R 50 50 1 1 B
|
||||
X PK6 83 -800 300 150 R 50 50 1 1 B
|
||||
X PK5 84 -800 400 150 R 50 50 1 1 B
|
||||
X PK4 85 -800 500 150 R 50 50 1 1 B
|
||||
X PK3 86 -800 600 150 R 50 50 1 1 B
|
||||
X PK2 87 -800 700 150 R 50 50 1 1 B
|
||||
X PK1 88 -800 800 150 R 50 50 1 1 B
|
||||
X PK0 89 -800 900 150 R 50 50 1 1 B
|
||||
X PE7 9 -800 -1700 150 R 50 50 1 1 B
|
||||
X PF7/TDI 90 -800 1100 150 R 50 50 1 1 B
|
||||
X PF6/TDO 91 -800 1200 150 R 50 50 1 1 B
|
||||
X PF5/TMS 92 -800 1300 150 R 50 50 1 1 B
|
||||
X PF4/TCK 93 -800 1400 150 R 50 50 1 1 B
|
||||
X PF3 94 -800 1500 150 R 50 50 1 1 B
|
||||
X PF2 95 -800 1600 150 R 50 50 1 1 B
|
||||
X PF1 96 -800 1700 150 R 50 50 1 1 B
|
||||
X PF0 97 -800 1800 150 R 50 50 1 1 B
|
||||
X AREF 98 -800 2000 150 R 50 50 1 1 P
|
||||
X GND 99 -200 -3500 150 U 50 50 1 1 W
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
#End Library
|
||||
Loading…
Reference in New Issue
Block a user