2019-04-29 20:36:58 +00:00
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NEW
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AUTO 3,1
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* object code = mli_3
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*
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* this routine handles interrupts and is coded to reach 'lreset' precisely at
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* address $FFCB (ROM rts opcode) for rom switching to function.
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2019-09-15 15:13:48 +00:00
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lanirq pha $2D9B-2DFF moved to $FF9B-FFFF
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2019-09-10 20:53:18 +00:00
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lda accsav
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sta oldacc
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2019-09-10 15:46:56 +00:00
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pla
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2019-09-10 20:53:18 +00:00
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sta accsav
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2019-09-13 15:39:37 +00:00
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pla get status register from stack
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pha and put it back.
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and #$10 is it a break or interrupt?
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bne H2DC2 branch if break.
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lda $D000 get ram bankid (LC1 = $D8, LC2=$EE)
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eor #$D8 is the system active? ($D8)
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beq sysactv branch if it is
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2019-09-10 15:46:56 +00:00
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lda #$FF
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sysactv sta bankid
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2019-09-10 20:53:18 +00:00
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sta afbank
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2019-09-13 15:39:37 +00:00
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lda /aftirq setup return address
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2019-09-10 15:46:56 +00:00
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pha
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2019-09-10 20:53:18 +00:00
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lda #aftirq
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2019-09-10 15:46:56 +00:00
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pha
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2019-09-13 15:39:37 +00:00
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lda #$04 status reg with interrupt flag set
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2019-09-10 15:46:56 +00:00
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pha
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2019-09-13 15:39:37 +00:00
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H2DC2 lda /romirq setup ROM re-entry
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2019-09-10 15:46:56 +00:00
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pha
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2019-09-10 20:53:18 +00:00
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lda #romirq
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2019-09-10 15:46:56 +00:00
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pha
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2019-09-15 15:13:48 +00:00
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gorom sta RROMBNK2 hits ROM rts at $FFCB
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2019-04-29 20:36:58 +00:00
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* 'lreset' address must = $FFCB for rom switch i/o to work
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2019-09-15 15:13:48 +00:00
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lreset lda rreset+1
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2019-09-10 15:46:56 +00:00
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pha
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2019-09-10 20:53:18 +00:00
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lda rreset
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2019-09-10 15:46:56 +00:00
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pha
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2019-09-10 20:53:18 +00:00
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jmp gorom
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2019-09-15 15:13:48 +00:00
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rreset .DA resetv-1 rts to resetv
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fix45 sta p8areg A register savearea
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2019-09-10 20:53:18 +00:00
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lda oldacc
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sta accsav
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2019-09-13 20:48:05 +00:00
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lda RRAMWRAMBNK1 read/write RAM bank 1
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2019-09-12 06:39:47 +00:00
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lda RRAMWRAMBNK1
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2019-09-10 20:53:18 +00:00
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lda afbank
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jmp irqxit0
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2019-09-15 15:13:48 +00:00
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stypfx sty newpfxptr fix appletalk PFI bug
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2019-09-13 20:48:05 +00:00
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sty preflag prefix flag
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2019-09-10 15:46:56 +00:00
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rts
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2019-09-15 15:13:48 +00:00
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stapfx sta newpfxptr
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2019-09-10 20:53:18 +00:00
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sta preflag
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2019-09-10 15:46:56 +00:00
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rts
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2019-04-29 20:36:58 +00:00
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* these 3 vectors hard-coded into processor
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2019-09-13 20:48:05 +00:00
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.DA nmivect nmi handler
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.DA lreset reset handler
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2019-09-15 15:13:48 +00:00
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irqv .DA lanirq irq handler
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2019-04-29 20:36:58 +00:00
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* end of obj mli_3
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*--------------------------------------
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MAN
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2019-07-08 12:56:54 +00:00
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SAVE USR/SRC/PRODOS.203/PRODOS.S.IRQ
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LOAD USR/SRC/PRODOS.203/PRODOS.S
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2019-04-29 20:36:58 +00:00
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ASM
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