A2osX/ProDOS.FX/ProDOS.S.XRW.txt

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2019-10-16 06:09:13 +00:00
NEW
AUTO 3,1
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*--------------------------------------
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* If Called by ProDOS : SEI
* If Called directly from DEVPTRS vectors : ????
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*--------------------------------------
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XRW.START cld $D8 to flag language card bank 1 (main)
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lda unitnum get unit number.
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pha
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lsr
lsr
lsr
lsr
sta XRW.UnitIndex
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tax
lda XRW.D2SeekTime-1,x
bne .10
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lda #IO.D2.SeekTimeP
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.10 sta XRW.SeekTime
pla
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and #$7F mask off high bit.
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sta A2L 0SSS0000 for IO indexing
* make sure other drives in other slots are stopped
eor XRW.LastUnitUsed same slot as last ?
asl
beq L59BD
lda #$01
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sta XRW.montimeh
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.1 lda XRW.LastUnitUsed
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and #$70
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tax
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beq L59BD branch if no previous ever (boot only).
jsr XRW.CheckMotorOnX check if previous drive running.
beq L59BD branch if stopped.
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lda #1
jsr XRW.Wait100usecA
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lda XRW.montimeh
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bne .1
*--------------------------------------
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L59BD lda bloknml
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ldx bloknml+1
stx XRW.ReqTrack calculate block's track and sector.
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ldy #$05
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.1 asl
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rol XRW.ReqTrack
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dey
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bne .1
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asl
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bcc .2
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ora #$10 adjust for upper 4 bits of track
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.2 lsr
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lsr
lsr
lsr
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sta XRW.ReqSector
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*--------------------------------------
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jsr XRW.Reset
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jsr XRW.CheckMotorOn
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php SAVE IRQ STATE
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php save motor on state : NZ if on
lda #$E8 24 up to 0
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sta XRW.montimeh
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lda unitnum determine drive 1 or 2.
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cmp XRW.LastUnitUsed same slot/drive used before ?
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sta XRW.LastUnitUsed save it for next time.
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php keep results of compare.
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asl get drive # into carry.
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bcc .3 branch if drive 1 selected.
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inx select drive 2.
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.3 lda IO.D2.DrvSel1,x
ldx A2L
lda IO.D2.DrvOn,x turn on the drive.
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plp was it the same drive ?
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beq .5 yes.
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plp NZ: indicate drive off by setting z-flag.
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ldy #6
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.4 jsr XRW.Wait25600usec 150 ms delay before stepping.
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dey
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bne .4
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php Z set
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.5 plp was motor on ?
bne L538E if so, don't wait.
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* motor was off, wait for it to speed up
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.6 lda #1
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jsr XRW.Wait100usecA wait 100us for each count in montime
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lda XRW.montimeh
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bmi .6 count up to 0000
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* motor should be up to speed,
* if it looks stopped then the drive is not present
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jsr XRW.CheckMotorOn is drive present ?
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beq XRW.E.ND
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*--------------------------------------
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L538E lda A4L get command #
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bne .1
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jsr XRW.TestWP 0 = status
bcs XRW.E.WP
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bcc XRW.E.OK
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.1 cmp #4 3 = format
bcs XRW.E.IO
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cmp #2 2 = Write, 1 = Read
ror XRW.bWrite b7 = 1 if Write
bpl .2
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jsr XRW.TestWP
bcs XRW.E.WP
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*--------------------------------------
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.2 sei DISABLE IRQ
jsr XRW.SectorIO
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bcs XRW.E.IO
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inc buf+1
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inc XRW.ReqSector
inc XRW.ReqSector
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jsr XRW.SectorIO get 2nd half of block
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dec buf+1
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bcc XRW.E.OK
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XRW.E.IO lda #MLI.E.IO
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.HS 2C BIT ABS
XRW.E.WP lda #MLI.E.WRTPROT
.HS 2C BIT ABS
XRW.E.ND lda #MLI.E.NODEV
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plp RESTORE IRQ STATE
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sec
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bra XRW.E.EXIT
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XRW.E.OK plp RESTORE IRQ STATE
clc
lda #0
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XRW.E.EXIT ldx A2L
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bit IO.D2.DrvOff,x turn off
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rts
*--------------------------------------
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XRW.SectorIO lda #2
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sta XRW.RecalibrateCnt
sta XRW.BadSeek
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bit XRW.bWrite
bpl .1
jsr XRW.PreNibble must prenibblize for write
.1 stz XRW.RetryCnt
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.2 jsr XRW.ReadAddr read next address field.
bcc .4 if CC, A = current track
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.3 inc XRW.RetryCnt one less chance.
bpl .2 branch if < 128
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dec XRW.RecalibrateCnt
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sec
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beq .9
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ldx XRW.UnitIndex
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lda #41
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sta XRW.D2Trk-1,x
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lda #0
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sta XRW.D2VolNum-1,x
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jsr XRW.Seek Seek from Track 41 -> 0
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bra .1
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.4 cmp XRW.ReqTrack
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beq .6
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lda XRW.BadSeek
beq .40 2 bad seeks, already
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dec XRW.BadSeek
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bne .5
.40 lda XRW.SeekTime
bmi .5 seektime = 140
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clc
adc #IO.D2.SeekTimeI
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sta XRW.SeekTime
ldx XRW.UnitIndex
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sta XRW.D2SeekTime-1,x
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.5 lda XRW.ReqTrack
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jsr XRW.Seek
bra .3
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.6 lda XRW.AddrField.S is this the right sector ?
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cmp XRW.ReqSector
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bne .3 no, try another sector.
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bit XRW.bWrite
bpl .7 branch if write
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jmp XRW.Write
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.7 jsr XRW.Read
bcs .3 if bad read
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.9 rts
*--------------------------------------
* preniblize subroutine (16 sector format)
*
* converts 256 bytes of user data in (buf) into 6 bit nibls in nbuf2.
* high 6 bits are translated directly by the write routines.
*
* on entry: buf is 2-byte pointer to 256 bytes of user data.
*
* on exit: a,x,y undefined. write routine modified to do direct conversion
* of high 6 bits of user's buffer data.
*--------------------------------------
XRW.PreNibble lda buf self-modify the addresses because of
ldy buf+1 the fast timing required.
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clc all offsets are minus $AA.
adc #$02 the highest set is buf+$AC.
bcc L58FA branch if no carry,
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iny otherwise add carry to high address.
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L58FA sta prn3+1 self mod 3
sty prn3+2
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sec
sbc #$56 middle set is buf+$56.
bcs L5906 branch if no borrow,
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dey otherwise deduct from high.
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L5906 sta prn2+1 self mod 2
sty prn2+2
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sec
sbc #$56 low set is exactly buf
bcs L5912
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dey
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L5912 sta prn1+1 self mod 1
sty prn1+2
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ldy #$AA count up to 0.
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prn1 lda $1000,y warning: self modified. get byte from lowest group.
and #$03 strip high 6 bits.
tax index to 2 bit equivalent.
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lda XRW.0000XX00,x
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pha save pattern
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prn2 lda $1056,y warning: self modified. get byte from middle group.
and #$03
tax
pla restore pattern.
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ora XRW.00XX0000,x combine 2nd group with 1st.
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pha save new pattern.
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prn3 lda $10AC,y warning: self modified. get byte from highest group.
and #$03
tax
pla restore new pattern
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ora XRW.XX000000,x and form final nibl.
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pha
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tya
eor #$FF
tax
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pla
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sta nbuf2,x save in nibl buffer.
iny inc to next set.
bne prn1 loop until all $56 nibls formed.
ldy buf now prepare data bytes for write16 subr.
dey prepare end address.
sty A2H
lda buf
sta wrefd1+1 warning: the following storage addresses
beq L595F starting with 'wref' are refs into code
eor #$FF space, changed by this routine.
tay index to last byte of page in (buf).
lda (buf),y pre-niblize the last byte of the page
iny with the first byte of the next page.
eor (buf),y
and #$FC
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tax
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lda XRW.FC2Nib,x get disk 7-bit nible equivalent.
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L595F sta pch
beq L596F branch if data to be written is page aligned.
lda A2H check if last byte is even
lsr or odd address. shift even/odd -> carry.
lda (buf),y if even, then leave intact.
bcc L596D branch if odd.
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iny if even, then pre-xor with byte 1.
eor (buf),y
L596D sta A1L save result for write routine.
L596F ldy #$FF index to last byte of data to write.
lda (buf),y to be used as a checksum.
and #$FC strip extra bits
sta A1H and save it.
ldy buf+1 now modify address references to
sty wrefa1+2 user data.
sty wrefa2+2
iny
sty wrefa3+2
sty wrefa4+2
sty wrefa5+2
sty wrefa6+2
ldx A2L and lastly, index references to
stx wrefd2+1 controller.
stx wrefd3+1
stx wrefd4+1
stx wrefd5+1
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rts
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*--------------------------------------
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* write subroutine (16 sector format)
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*
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* writes data from nbuf1 and buf. first nbuf2, high to low then direct
* from (buf), low to high. assumes 1 usec cycle time. self modified code !!
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*
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* on entry: x = slotnum times 16
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*
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* on exit: carry set if error (write protect violation).
* if no error, acc=uncertain, x=unchanged, y=0, carry clear.
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*--------------------------------------
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.LIST ON
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XRW.Write lda IO.D2.ReadProt,x PREWRITE MODE
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.LIST OFF
lda IO.D2.ReadMode,x
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* sec
* bpl .1
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* jmp XRW.ReadMode
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.1 lda nbuf2
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sta pcl
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lda #$FF Self Sync Byte
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sta IO.D2.WriteMode,x (5) goto write mode
ora IO.D2.WShift,x (4)
ldy #$04 (2) for five nibls
nop (2)
pha (3)
pla (4)
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wsync pha (3) exact timing.
pla (4) exact timing.
jsr wnibl7 (13,9,6) write sync.
dey (2)
bne wsync (3-) must not cross page !
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lda #$D5 (2) 1st data mark
jsr wnibl9 (15,9,6)
lda #$AA (2) 2nd data mark
jsr wnibl9 (15,9,6)
lda #$AD (2) 3rd data mark
jsr wnibl9 (15,9,6)
tya (2) zero checksum
ldy #$56 (2) nbuf2 index
bne L583D (3) branch always
* total time in this write byte loop must = 32us !!!
L583A lda nbuf2,y (4) prior 6-bit nibl
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*L583D eor nbuf2-1,y (5) xor with current (4+1 : PAGE CROSS)
L583D eor nbuf2-1,y (4) xor with current (NO MORE PAGE CROSS)
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tax (2) index to 7-bit nibl
lda XRW.FC2Nib,x (4) must not cross page boundary
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* ldx A2L (3) restore slot index
ldx >A2L (4) absolute reference to zero page
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sta IO.D2.WLoad,x (5) store encoded byte
lda IO.D2.WShift,x (4) handshake
dey (2)
bne L583A (3-) must not cross page boundary
* end of write byte loop
lda pcl (3) get prior nibl (from nbuf2)
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wrefd1 ldy #$00 (2) warning: load value modified by prenib.
wrefa1 eor $1000,y (4) warning: address modified by prenib.
and #$FC (2) strip low 2 bits
tax (2) index to nibl table
lda XRW.FC2Nib,x (4)
wrefd2 ldx #$60 (2) warning: value modified by prenib.
sta IO.D2.WLoad,x (5) write nibl
lda IO.D2.WShift,x (4) handshake
wrefa2 lda $1000,y (4) prior nibl. warning: address modified by prenib.
iny (2) all done with this page ?
bne wrefa1 (3-) loop until page end.
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lda pch (3) get next (precalculated & translated) nibl.
beq L58C0 (2+) branch if code written was page aligned.
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lda A2H (3) get byte address of last byte to be written.
beq L58B3 (2+) branch if only 1 byte left to write.
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lsr (2) test for odd or even last byte (carry set/clear)
lda pch (3) restore nibl to acc.
sta IO.D2.WLoad,x (5)
lda IO.D2.WShift,x (4)
lda A1L (3) = byte 0 of 2nd page xor'd with byte 1 if
nop (2) above test set carry.
iny (2) y=1
bcs L5899 (2+) branch if last byte to be odd.
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wrefa3 eor $1100,y (4) warning: address modified by prenib.
and #$FC (2) strip low 2 bits.
tax (2) index to nibl table
lda XRW.FC2Nib,x (4) get nibl
wrefd3 ldx #$60 (2) restore slot index. warning: modified by prenib
sta IO.D2.WLoad,x (5)
lda IO.D2.WShift,x (4)
wrefa4 lda $1100,y (4) warning: modified by prenib
iny (2) got prior nibl, point to next
wrefa5 eor $1100,y (4) warning: modified by prenib
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L5899 cpy A2H (3) set carry if this is the last nibl
and #$FC (2) strip low 2 bits
tax (2)
lda XRW.FC2Nib,x (4)
wrefd4 ldx #$60 (2) restore slot. warning: modified by prenib
sta IO.D2.WLoad,x (5)
lda IO.D2.WShift,x (4)
wrefa6 lda $1100,y (4) get prior nibl. warning: modified by prenib
iny (2)
bcc wrefa3 (3-) branch if not the last.
bcs L58B1 (3) waste 3 cycles, branch always.
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L58B1 bcs L58C0 (3) branch always.
2020-04-16 06:15:29 +00:00
2020-04-21 06:19:17 +00:00
L58B3 lda >pch (4) absolute reference to zero page
sta IO.D2.WLoad,x (5)
lda IO.D2.WShift,x (4)
pha (3) waste 14 micro-seconds total
pla (4)
pha (3)
pla (4)
2020-04-16 06:15:29 +00:00
2020-04-21 06:19:17 +00:00
L58C0 ldx A1H (3) use last nibl (anded with $FC) for checksum
lda XRW.FC2Nib,x (4)
wrefd5 ldx #$60 (2) restore slot. warning: modified by prenib
sta IO.D2.WLoad,x (5)
lda IO.D2.WShift,x (4)
2020-04-16 06:15:29 +00:00
2020-11-19 15:34:02 +00:00
ldy #2 (2) set y = index end mark table.
2020-04-21 06:19:17 +00:00
pha (3) waste another 11 micro-seconds
pla (4)
nop (2)
2020-04-16 06:15:29 +00:00
2020-11-19 15:34:02 +00:00
.1 nop (2)
lda XRW.EndMark,y (4) DE AA EB
2020-04-21 06:19:17 +00:00
jsr wnibl (15,6) write it
2020-11-19 15:34:02 +00:00
dey (2)
bpl .1 (3) if not.
2020-04-16 06:15:29 +00:00
2020-11-19 15:34:02 +00:00
clc (2)
2020-04-16 06:15:29 +00:00
2020-11-19 15:34:02 +00:00
lda #$FF (2)
nop (2)
jsr wnibl (15,6) write turn off byte.
XRW.ReadMode lda IO.D2.ReadMode,x out of write mode
2020-04-21 06:19:17 +00:00
lda IO.D2.WShift,x to read mode.
rts return from write.
* 7-bit nibl write subroutines
wnibl9 clc (2) 9 cycles, then write.
2020-11-19 15:34:02 +00:00
2020-04-21 06:19:17 +00:00
wnibl7 pha (3) 7 cycles, then write.
pla (4)
2020-11-19 15:34:02 +00:00
2020-04-21 06:19:17 +00:00
wnibl sta IO.D2.WLoad,x (5) nibl write
ora IO.D2.WShift,x (4) clobbers acc, not carry
2020-11-19 15:34:02 +00:00
.LIST ON
2020-08-26 10:29:04 +00:00
XRW.Write.RTS rts (6)
2020-11-19 15:34:02 +00:00
.LIST OFF
2020-04-21 06:19:17 +00:00
*--------------------------------------
* delays a specified number of 100 usec intervals for motor timing.
* on entry: acc holds number of 100 usec intervals to delay.
* on exit: acc = 0, x = 0, y = unchanged, carry set.
* montimel, montimeh are incremented once per 100 usec interval
* for motor on timing.
*--------------------------------------
2020-08-26 10:29:04 +00:00
XRW.WaitSeekTime
2020-11-19 15:34:02 +00:00
lda XRW.SeekTime
2020-08-26 10:29:04 +00:00
.HS 2C BIT ABS
2020-06-22 05:59:53 +00:00
XRW.Wait25600usec
lda #0
2020-05-30 20:38:47 +00:00
XRW.Wait100usecA
2020-11-23 22:05:27 +00:00
phx
2020-11-24 17:49:46 +00:00
.1 ldx A2L (3)
bit IO.D2.RData,x (4)
ldx #16 (2)
2020-04-21 06:19:17 +00:00
2020-11-24 17:49:46 +00:00
.2 dex (2)
2020-05-13 17:00:37 +00:00
bne .2 (3)
2020-04-21 06:19:17 +00:00
2020-06-07 08:06:51 +00:00
inc XRW.montimel (6)
2020-05-13 17:00:37 +00:00
bne .3 (3)
2020-04-21 06:19:17 +00:00
2020-06-07 08:06:51 +00:00
inc XRW.montimeh (6)
2020-04-21 06:19:17 +00:00
2020-10-30 16:03:34 +00:00
.3 dec (2)
2020-06-07 08:06:51 +00:00
bne .1 (3)
2020-11-19 15:34:02 +00:00
2020-11-23 22:05:27 +00:00
plx
2020-06-17 19:05:36 +00:00
rts (6)
2020-04-16 06:15:29 +00:00
*--------------------------------------
2019-10-16 06:09:13 +00:00
* read subroutine (16-sector format)
*
* reads encoded bytes into nbuf1 and nbuf2.
* first reads nbuf2 high to low, then nbuf1 low to high.
2020-04-16 06:15:29 +00:00
* on entry: x=slot# times $10, read mode
2019-10-16 06:09:13 +00:00
* on exit: carry set if error, else if no error:
* acc=$AA, x=unchanged, y=0, carry clear.
* observe 'no page cross' on some branches !!
2020-04-16 06:15:29 +00:00
*--------------------------------------
2020-11-19 15:34:02 +00:00
.LIST ON
2020-04-21 06:19:17 +00:00
XRW.Read txa get slot #
2020-11-19 15:34:02 +00:00
.LIST OFF
2019-10-16 06:09:13 +00:00
ora #$8C prepare mods to read routine.
sta rd4+1 warning: the read routine is
sta rd5+1 self modified !!
sta rd6+1
sta rd7+1
sta rd8+1
2020-04-21 06:19:17 +00:00
2019-10-16 06:09:13 +00:00
lda buf modify storage addresses also
ldy buf+1
sta ref3+1
sty ref3+2
sec
sbc #$54
bcs L571F branch if no borrow
2020-04-21 06:19:17 +00:00
2019-10-16 06:09:13 +00:00
dey
2020-04-21 06:19:17 +00:00
2019-10-16 06:09:13 +00:00
L571F sta ref2+1
sty ref2+2
sec
sbc #$57
bcs L572B branch if no borrow
2020-04-21 06:19:17 +00:00
2019-10-16 06:09:13 +00:00
dey
2020-04-21 06:19:17 +00:00
2019-10-16 06:09:13 +00:00
L572B sta ref1+1
sty ref1+2
2020-04-21 06:19:17 +00:00
2019-10-16 06:09:13 +00:00
ldy #$20 32 tries to find
2020-04-21 06:19:17 +00:00
2019-10-16 06:09:13 +00:00
L5733 dey
beq L576D branch if can't find data header marks
2020-04-21 06:19:17 +00:00
2020-04-16 06:15:29 +00:00
L5736 lda IO.D2.RData,x
2019-10-16 06:09:13 +00:00
bpl L5736
2020-04-21 06:19:17 +00:00
2019-10-16 06:09:13 +00:00
L573B eor #$D5 1st data mark
bne L5733
2020-04-21 06:19:17 +00:00
2019-10-16 06:09:13 +00:00
nop delay
2020-04-21 06:19:17 +00:00
2020-04-16 06:15:29 +00:00
L5740 lda IO.D2.RData,x
2019-10-16 06:09:13 +00:00
bpl L5740
2020-04-21 06:19:17 +00:00
2019-10-16 06:09:13 +00:00
cmp #$AA 2nd data mark.
bne L573B if not, check for 1st again
2020-04-21 06:19:17 +00:00
2019-10-16 06:09:13 +00:00
nop
2020-04-21 06:19:17 +00:00
2020-04-16 06:15:29 +00:00
L574A lda IO.D2.RData,x
2019-10-16 06:09:13 +00:00
bpl L574A
2020-04-21 06:19:17 +00:00
2019-10-16 06:09:13 +00:00
cmp #$AD 3rd data mark
bne L573B if not, check for data mark 1 again
2020-04-21 06:19:17 +00:00
2019-10-16 06:09:13 +00:00
ldy #$AA
lda #$00
2020-04-21 06:19:17 +00:00
2019-10-16 06:09:13 +00:00
L5757 sta pcl use z-page for keeping checksum
2020-04-21 06:19:17 +00:00
2020-04-16 06:15:29 +00:00
rd4 ldx IO.D2.RData+$60 warning: self modified
2019-10-16 06:09:13 +00:00
bpl rd4
2020-04-21 06:19:17 +00:00
lda XRW.Nib2FC-$96,x
2019-10-16 06:09:13 +00:00
sta nbuf2-$AA,y save the two-bit groups in nbuf.
eor pcl update checksum.
iny next position in nbuf.
bne L5757 loop for all $56 two-bit groups.
2020-04-21 06:19:17 +00:00
2019-10-16 06:09:13 +00:00
ldy #$AA now read directly into user buffer.
bne rd5 always taken.
2020-04-21 06:19:17 +00:00
2020-11-19 15:34:02 +00:00
L576D sec error
2019-10-16 06:09:13 +00:00
rts
2020-04-21 06:19:17 +00:00
2019-10-16 06:09:13 +00:00
ref1 sta $1000,y warning: self modified
2020-04-21 06:19:17 +00:00
2020-04-16 06:15:29 +00:00
rd5 ldx IO.D2.RData+$60 warning: self modified
2019-10-16 06:09:13 +00:00
bpl rd5
2020-04-21 06:19:17 +00:00
eor XRW.Nib2FC-$96,x get actual 6-bit data from dnib table.
2019-10-16 06:09:13 +00:00
ldx nbuf2-$AA,y get associated two-bit pattern
eor dnibl2,x and combine to form whole byte.
iny
bne ref1 loop for $56 bytes.
2020-04-21 06:19:17 +00:00
2019-10-16 06:09:13 +00:00
pha save for now, no time to store...
and #$FC strip low bits.
ldy #$AA prepare for next $56 bytes
2020-04-21 06:19:17 +00:00
2020-04-16 06:15:29 +00:00
rd6 ldx IO.D2.RData+$60 warning: self modified
2019-10-16 06:09:13 +00:00
bpl rd6
2020-04-21 06:19:17 +00:00
eor XRW.Nib2FC-$96,x
2019-10-16 06:09:13 +00:00
ldx nbuf2-$AA,y
eor dnibl3,x
ref2 sta $1000,y warning: self modified
iny
bne rd6 loop unil this group of $56 read
2020-04-16 06:15:29 +00:00
rd7 ldx IO.D2.RData+$60 warning: self modified
2019-10-16 06:09:13 +00:00
bpl rd7
2020-04-21 06:19:17 +00:00
2019-10-16 06:09:13 +00:00
and #$FC
ldy #$AC last group is $54 long
2020-04-21 06:19:17 +00:00
L57A5 eor XRW.Nib2FC-$96,x
2019-10-16 06:09:13 +00:00
ldx nbuf2-$AC,y
eor dnibl4,x combine to form full byte
ref3 sta $1000,y warning: self modified
2020-04-16 06:15:29 +00:00
rd8 ldx IO.D2.RData+$60 warning: self modified
2019-10-16 06:09:13 +00:00
bpl rd8
2020-04-21 06:19:17 +00:00
2019-10-16 06:09:13 +00:00
iny
bne L57A5
2020-04-21 06:19:17 +00:00
2019-10-16 06:09:13 +00:00
and #$FC
2020-04-21 06:19:17 +00:00
eor XRW.Nib2FC-$96,x checksum ok ?
2019-10-16 06:09:13 +00:00
bne L57CC error if not.
2020-04-21 06:19:17 +00:00
2019-10-16 06:09:13 +00:00
ldx A2L test end marks.
2020-04-21 06:19:17 +00:00
2020-04-16 06:15:29 +00:00
L57C2 lda IO.D2.RData,x
2019-10-16 06:09:13 +00:00
bpl L57C2
2020-04-21 06:19:17 +00:00
2019-10-16 06:09:13 +00:00
cmp #$DE
2020-04-21 06:19:17 +00:00
2019-10-16 06:09:13 +00:00
clc
beq L57CD branch if good trailer
2020-04-21 06:19:17 +00:00
2019-10-16 06:09:13 +00:00
L57CC sec
2020-04-21 06:19:17 +00:00
2019-10-16 06:09:13 +00:00
L57CD pla place last byte into user buffer
ldy #$55
sta (buf),y
2020-11-19 15:34:02 +00:00
.LIST ON
2020-06-25 15:39:51 +00:00
XRW.Read.RTS rts
2020-11-19 15:34:02 +00:00
.LIST OFF
2020-08-26 10:29:04 +00:00
*--------------------------------------
2020-06-10 20:04:13 +00:00
* A = target track
2020-05-08 19:02:27 +00:00
*--------------------------------------
2020-06-25 15:39:51 +00:00
XRW.Seek ldx XRW.UnitIndex
2020-11-23 22:05:27 +00:00
2020-06-25 15:39:51 +00:00
pha save target track
2020-11-23 22:05:27 +00:00
2020-05-08 19:02:27 +00:00
jsr XRW.Trk2Qtrk
sta XRW.TargetQTrack
2020-07-25 07:05:25 +00:00
2020-05-08 19:02:27 +00:00
lda XRW.D2Trk-1,x
jsr XRW.Trk2Qtrk
sta XRW.CurrentQTrack
2020-07-25 07:05:25 +00:00
2020-05-08 19:02:27 +00:00
pla
2020-05-23 18:45:32 +00:00
sta XRW.D2Trk-1,x will be current track at the end
2020-05-08 19:02:27 +00:00
2020-11-23 22:05:27 +00:00
ldx A2L
ldy A2L
2020-07-06 12:03:05 +00:00
2020-11-23 22:05:27 +00:00
.1 lda XRW.CurrentQTrack
cmp XRW.TargetQTrack
beq .7
2020-11-19 15:34:02 +00:00
2020-11-23 22:05:27 +00:00
jsr .8
bcs .2
2020-07-25 07:05:25 +00:00
2020-11-23 22:05:27 +00:00
* Current < Target, must move in
2020-07-06 12:03:05 +00:00
inc
2020-07-25 07:05:25 +00:00
2020-11-23 22:05:27 +00:00
.HS B0 BCS
2020-07-25 07:05:25 +00:00
* Current > Target, must move out
2020-11-23 22:05:27 +00:00
.2 dec
2020-07-25 07:05:25 +00:00
sta XRW.CurrentQTrack
2020-11-23 22:05:27 +00:00
pha
2020-07-25 07:05:25 +00:00
2020-11-23 22:05:27 +00:00
and #6
ora A2L
tax
2020-07-06 12:03:05 +00:00
2020-11-23 22:05:27 +00:00
pla
2020-05-17 17:34:32 +00:00
2020-11-23 22:05:27 +00:00
bcs .3
2020-05-08 19:02:27 +00:00
2020-11-23 22:05:27 +00:00
* Current < Target, must move in
inc
2020-06-22 15:15:56 +00:00
2020-11-23 22:05:27 +00:00
.HS B0 BCS
2020-05-08 19:02:27 +00:00
2020-11-23 22:05:27 +00:00
* Current > Target, must move out
2020-05-09 19:08:20 +00:00
2020-11-23 22:05:27 +00:00
.3 dec
2020-06-17 19:05:36 +00:00
2020-11-23 22:05:27 +00:00
and #6
ora A2L
2020-09-13 19:05:38 +00:00
2020-11-23 22:05:27 +00:00
bcc .4
* move out : invert 2 phases
2020-09-13 19:05:38 +00:00
2020-11-23 22:05:27 +00:00
phx
tax
pla
.4 tay
lda IO.D2.Ph0On,x
2020-09-07 20:40:50 +00:00
nop
nop
2020-11-23 22:05:27 +00:00
lda IO.D2.Ph0On,y
nop
nop
2020-07-25 07:05:25 +00:00
jsr XRW.WaitSeekTime
2020-11-23 22:05:27 +00:00
bra .1
2020-06-27 18:30:09 +00:00
2020-11-23 22:05:27 +00:00
.7 jsr XRW.Wait25600usec
2020-09-07 20:40:50 +00:00
2020-11-23 22:05:27 +00:00
.8 bit IO.D2.Ph0Off,x
2020-09-07 20:40:50 +00:00
nop
nop
2020-11-24 17:49:46 +00:00
2020-11-23 22:05:27 +00:00
ldx IO.D2.Ph0Off,y
2020-09-07 20:40:50 +00:00
nop
nop
2020-11-24 17:49:46 +00:00
2020-11-23 22:05:27 +00:00
rts
2020-11-19 15:34:02 +00:00
*--------------------------------------
XRW.Reset ldx A2L
2020-09-07 20:40:50 +00:00
2020-11-19 15:34:02 +00:00
lda IO.D2.Ph0Off,x
lda IO.D2.Ph1Off,x
lda IO.D2.Ph2Off,x
lda IO.D2.Ph3Off,x
jmp XRW.ReadMode
2020-06-23 15:39:18 +00:00
*--------------------------------------
2020-05-08 19:02:27 +00:00
XRW.Trk2Qtrk asl x2
sta .1+1
bit XRW.D2VolNum-1,x
2020-05-23 18:45:32 +00:00
bpl .1 x4
2020-09-15 06:12:52 +00:00
bvs .1 > $C0 ? (VOL=254)
2020-11-19 15:34:02 +00:00
2020-05-08 19:02:27 +00:00
lsr x3
2020-11-19 15:34:02 +00:00
2020-05-08 19:02:27 +00:00
.1 adc #$ff SELF MODIFIED
rts
*--------------------------------------
2020-11-19 15:34:02 +00:00
.LIST ON
2020-04-21 06:19:17 +00:00
XRW.ReadAddr ldy #$FC
2020-11-19 15:34:02 +00:00
.LIST OFF
2020-04-23 06:02:25 +00:00
sty XRW.CheckSum init nibble counter to $FCFC
2020-11-19 15:34:02 +00:00
2020-04-21 06:19:17 +00:00
ldx A2L get slot #
2020-04-16 06:15:29 +00:00
2020-07-05 08:58:35 +00:00
.1 iny
bne .2 counter LO
2020-11-19 15:34:02 +00:00
2020-04-23 06:02:25 +00:00
inc XRW.CheckSum counter HI
2020-08-26 10:29:04 +00:00
beq .99
2020-11-19 15:34:02 +00:00
2020-07-05 08:58:35 +00:00
.2 lda IO.D2.RData,x read nibl
bpl .2
2020-11-19 15:34:02 +00:00
2020-07-05 08:58:35 +00:00
.3 cmp #$D5 address mark 1 ?
bne .1
2020-11-19 15:34:02 +00:00
nop
2020-07-05 08:58:35 +00:00
.4 lda IO.D2.RData,x
bpl .4
2020-04-16 06:15:29 +00:00
2020-04-21 06:19:17 +00:00
cmp #$AA address mark 2 ?
2020-07-05 08:58:35 +00:00
bne .3 if not, is it address mark 1 ?
2019-10-16 06:09:13 +00:00
2020-11-19 15:34:02 +00:00
ldy #3 index for 4 byte read
2019-10-16 06:09:13 +00:00
2020-07-05 08:58:35 +00:00
.5 lda IO.D2.RData,x
bpl .5
2019-10-16 06:09:13 +00:00
2020-04-21 06:19:17 +00:00
cmp #$96 address mark 3 ?
2020-07-05 08:58:35 +00:00
bne .3 if not, is it address mark 1
2019-10-16 06:09:13 +00:00
2020-11-19 15:34:02 +00:00
lda #0 init Chksum
.6 sta XRW.CheckSum
2019-10-16 06:09:13 +00:00
2020-07-05 08:58:35 +00:00
.7 lda IO.D2.RData,x read 'odd bit' nibl
bpl .7
2019-10-16 06:09:13 +00:00
2020-04-21 06:19:17 +00:00
rol align odd bits, '1' into lsb.
2020-04-23 06:02:25 +00:00
sta XRW.Temp4x4 save them.
2020-11-19 15:34:02 +00:00
2020-07-05 08:58:35 +00:00
.8 lda IO.D2.RData,x read 'even bit' nibl
bpl .8
2020-11-19 15:34:02 +00:00
2020-04-23 06:02:25 +00:00
and XRW.Temp4x4 merge odd and even bits.
sta XRW.AddrField.C,y store data byte.
eor XRW.CheckSum
2020-04-21 06:19:17 +00:00
dey
2020-07-05 08:58:35 +00:00
bpl .6 loop on 4 data bytes.
2020-11-19 15:34:02 +00:00
2020-04-21 06:19:17 +00:00
tay if final checksum non-zero,
2020-08-26 10:29:04 +00:00
bne .99 then error.
2020-07-05 08:58:35 +00:00
2020-11-19 15:34:02 +00:00
clc
2020-07-05 08:58:35 +00:00
.9 lda IO.D2.RData,x
bpl .9
2020-11-19 15:34:02 +00:00
2020-10-28 16:35:04 +00:00
eor #$DE
2020-08-26 10:29:04 +00:00
bne .99
2020-11-19 15:34:02 +00:00
2020-10-30 16:03:34 +00:00
ldy XRW.UnitIndex
2020-11-19 15:34:02 +00:00
lda XRW.AddrField.V
2020-10-30 16:03:34 +00:00
sta XRW.D2VolNum-1,y
2020-10-28 16:35:04 +00:00
lda XRW.AddrField.T Successful Read, update Drive table
2020-06-26 19:34:12 +00:00
sta XRW.D2Trk-1,y and exit with A = Trk
2020-11-19 15:34:02 +00:00
2020-04-21 06:19:17 +00:00
rts
2019-10-16 06:09:13 +00:00
2020-11-19 15:34:02 +00:00
.99 sec
.LIST ON
XRW.ReadAddr.RTS
2020-04-21 06:19:17 +00:00
rts
2020-11-19 15:34:02 +00:00
.LIST OFF
2020-06-10 20:04:13 +00:00
*--------------------------------------
2020-11-19 15:34:02 +00:00
* determine if motor is stopped
*
* if stopped, controller's shift register will not be changing.
* return y = 0 and zero flag set if it is stopped.
*--------------------------------------
XRW.CheckMotorOn
ldx A2L
XRW.CheckMotorOnX
ldy #0 init loop counter.
2020-06-11 21:04:56 +00:00
2020-11-19 15:34:02 +00:00
.1 lda IO.D2.RData,x read the shift register.
jsr .9 delay
2020-06-11 21:04:56 +00:00
2020-11-19 15:34:02 +00:00
pha
pla more delay.
2020-06-22 05:59:53 +00:00
2020-11-19 15:34:02 +00:00
cmp IO.D2.RData,x has shift reg changed ?
bne .9 yes, motor is moving.
2020-06-17 19:05:36 +00:00
2020-11-19 15:34:02 +00:00
dey no, dec retry counter
bne .1 and try 256 times.
.9 rts Z if motor OFF
*--------------------------------------
XRW.TestWP ldx A2L
lda IO.D2.ReadProt,x test for write protected
lda IO.D2.ReadMode,x
rol write protect-->carry-->bit 0=1
lda IO.D2.RData,x keep in read mode
rts
2020-04-16 06:15:29 +00:00
*--------------------------------------
2020-04-21 06:19:17 +00:00
.LIST ON
2020-05-08 19:02:27 +00:00
XRW.FREE .EQ $D540-*
2020-04-21 06:19:17 +00:00
.LIST OFF
2020-05-08 19:02:27 +00:00
.BS $D540-*
2020-04-21 06:19:17 +00:00
*--------------------------------------
2020-05-08 19:02:27 +00:00
* nibl buffer 'nbuf2' must fit in a page
2020-04-21 06:19:17 +00:00
*--------------------------------------
nbuf2 .BS $56 nibl buffer for read/write of low 2-bits of each byte.
*--------------------------------------
* 7-bit to 6-bit 'deniblize' table (16-sector format)
*
* valid codes are $96 to $FF only. codes with more than one pair of
* adjacent zeroes or with no adjacent ones (except bit 7) are excluded.
*
* nibbles in the ranges of $A0-$A3, $C0-$C7, $E0-$E3 are used for
* other tables since no valid nibbles are in these ranges.
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* aligned to page boundary + $96
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*--------------------------------------
XRW.Nib2FC .HS 0004
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* .HS FFFF
XRW.UnitIndex .HS 00
XRW.LastUnitUsed .HS 00
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.HS 080C
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* .HS FF
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XRW.RecalibrateCnt .HS 00
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.HS 101418
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XRW.XX000000 .HS 008040C0 used in fast prenib as lookup for 2-bit quantities.
* .HS FFFF
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XRW.montimel .HS 00
XRW.montimeh .HS 00
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.HS 1C20
.HS FFFFFF
.HS 24282C3034
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* .HS FFFF
XRW.ReqTrack .HS 00
XRW.ReqSector .HS 00
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.HS 383C4044484C
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* .HS FF
XRW.BadSeek .HS 00
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.HS 5054585C606468
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XRW.00XX0000 .HS 00201030 used in fast prenib.
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XRW.EndMark .HS EBAADE table using 'unused' nibbles ($C4,$C5,$C6,$C7)
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* .HS FFFFFFFF
XRW.AddrField.C .HS 00 AddrField Checksum
XRW.AddrField.S .HS 00 AddrField Sector
XRW.AddrField.T .HS 00 AddrField Track
XRW.AddrField.V .HS 00 AddrField Volume
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.HS 6C
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XRW.SeekTime .HS 00
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*ibstat .HS 00
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.HS 707478
.HS FFFFFF
.HS 7C
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* .HS FFFF
XRW.Temp4x4 .HS 00
XRW.CheckSum .HS 00 used for address header cksum
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.HS 8084
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* .HS FF
XRW.RetryCnt .HS 00
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.HS 888C9094989CA0
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XRW.0000XX00 .HS 0008040C used in fast prenib.
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* .HS FF
XRW.CurrentQTrack .HS 00
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.HS A4A8AC
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* .HS FF
XRW.TargetQTrack .HS 00
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.HS B0B4B8BCC0C4C8
.HS FFFF
.HS CCD0D4D8DCE0
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XRW.bWrite .HS 00
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.HS E4E8ECF0F4F8FC
*--------------------------------------
* 6-bit to 2-bit conversion tables:
*
* origin = $D600 (page boundary)
*
* dnibl2 abcdef-->0000FE
* dnibl3 abcdef-->0000DC
* dnibl4 abcdef-->0000BA
* page align the following tables:
*--------------------------------------
* FC-bits to nibble conversion table (256 bytes)
*
* codes with more than one pair of adjacent zeroes
* or with no adjacent ones (except B7) are excluded.
*--------------------------------------
dnibl2 .HS 00
dnibl3 .HS 00
dnibl4 .HS 00
XRW.FC2Nib .HS 96
.HS 02000097
.HS 0100009A
.HS 0300009B
.HS 0002009D
.HS 0202009E
.HS 0102009F
.HS 030200A6
.HS 000100A7
.HS 020100AB
.HS 010100AC
.HS 030100AD
.HS 000300AE
.HS 020300AF
.HS 010300B2
.HS 030300B3
.HS 000002B4
.HS 020002B5
.HS 010002B6
.HS 030002B7
.HS 000202B9
.HS 020202BA
.HS 010202BB
.HS 030202BC
.HS 000102BD
.HS 020102BE
.HS 010102BF
.HS 030102CB
.HS 000302CD
.HS 020302CE
.HS 010302CF
.HS 030302D3
.HS 000001D6
.HS 020001D7
.HS 010001D9
.HS 030001DA
.HS 000201DB
.HS 020201DC
.HS 010201DD
.HS 030201DE
.HS 000101DF
.HS 020101E5
.HS 010101E6
.HS 030101E7
.HS 000301E9
.HS 020301EA
.HS 010301EB
.HS 030301EC
.HS 000003ED
.HS 020003EE
.HS 010003EF
.HS 030003F2
.HS 000203F3
.HS 020203F4
.HS 010203F5
.HS 030203F6
.HS 000103F7
.HS 020103F9
.HS 010103FA
.HS 030103FB
.HS 000303FC
.HS 020303FD
.HS 010303FE
.HS 030303FF
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*--------------------------------------
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XRW.LEN .EQ *-XRW.START
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MAN
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SAVE usr/src/prodos.fx/prodos.s.xrw
LOAD usr/src/prodos.fx/prodos.s
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ASM