2019-10-16 06:09:13 +00:00
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NEW
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AUTO 3,1
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2019-10-19 18:35:30 +00:00
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*--------------------------------------
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2019-11-01 20:06:04 +00:00
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GP.START jmp GP.MLIENTRY $2E00-2EFF moved to $BF00
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2019-10-16 06:09:13 +00:00
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jspare jmp * will be changed to point to dispatcher.
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clockv rts changed to jmp ($4C) if clock present.
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2019-11-23 15:24:55 +00:00
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.DA XDOS.ClockDrv clock routine entry address.
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2019-10-16 06:09:13 +00:00
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GP.P8errv jmp XDOS.syserr error reporting hook.
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sysdeath jmp sysdeath1 system failure hook.
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p8error .DA #0
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.DA nodevice
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.DA nodevice
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.DA nodevice
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.DA nodevice
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.DA nodevice
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.DA nodevice
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.DA nodevice
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.DA nodevice
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.DA nodevice
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.DA nodevice
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.DA nodevice
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.DA nodevice
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.DA nodevice
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.DA nodevice
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2019-11-09 12:19:41 +00:00
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.DA nodevice
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.DA nodevice
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.DA #0 DEVNUM
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.DA #$ff DEVCNT : count (-1) active devices
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.HS 00000000000000 DEVLST : up to 14 units may be active
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2019-10-16 06:09:13 +00:00
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.HS 00000000000000
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.DA #0
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2019-10-19 18:35:30 +00:00
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*--------------------------------------
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2019-10-16 06:09:13 +00:00
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.AS "(C)APPLE "
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2019-10-19 18:35:30 +00:00
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*--------------------------------------
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GP.MLIENTRY php
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2019-10-16 06:09:13 +00:00
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sei
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2019-10-19 18:35:30 +00:00
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jmp GP.MLICONT
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*--------------------------------------
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*aftirq sta RRAMWRAMBNK1 read/write RAM bank 1
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* jmp fix45 restore $45 after interrupt in LC
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*oldacc .DA #0
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*afbank .HS 00
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*--------------------------------------
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.LIST ON
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GP.FREE1 .EQ $BF58-*
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.LIST OFF
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.BS GP.FREE1
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*--------------------------------------
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2019-10-16 06:09:13 +00:00
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* memory map of lower 48k. each bit represents 1 page.
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* protected pages = 1, unprotected = 0
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2019-10-19 18:35:30 +00:00
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*--------------------------------------
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2019-11-09 12:19:41 +00:00
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.HS C000000000000000 MEMTABL
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2019-10-16 06:09:13 +00:00
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.HS 0000000000000000
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.HS 0000000000000001
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2019-10-19 18:35:30 +00:00
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*--------------------------------------
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2019-10-16 06:09:13 +00:00
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* table of buffer addresses for currently open files.
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* these can only be changed thru the mli call setbuf.
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2019-10-19 18:35:30 +00:00
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*--------------------------------------
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2019-10-16 06:09:13 +00:00
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buftbl .HS 0000 file #1
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.HS 0000 file #2
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.HS 0000 file #3
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.HS 0000 file #4
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.HS 0000 file #5
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.HS 0000 file #6
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.HS 0000 file #7
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.HS 0000 file #8
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2019-10-19 18:35:30 +00:00
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*--------------------------------------
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2019-10-16 06:09:13 +00:00
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* table of interrupt vectors. these can only be changed
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* by the mli call allocate_interrupt. values of the registers
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* at the time of the most recent interrupt are stored here along
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* with the address interrupted.
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2019-10-19 18:35:30 +00:00
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*--------------------------------------
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2019-10-16 06:09:13 +00:00
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inttbl .HS 0000 int #1
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.HS 0000 int #2
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.HS 0000 int #3
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.HS 0000 int #4
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2019-10-19 18:35:30 +00:00
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*--------------------------------------
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*p8areg .DA #0 A register savearea
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*p8xreg .DA #0 X register savearea
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*p8yreg .DA #0 Y register savearea
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*p8sreg .DA #0 S register savearea
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*p8preg .DA #0 P register savearea
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*bankid .DA #1 bank ID byte (ROM/RAM)
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*intadr .HS 0000 interrupt return address
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*--------------------------------------
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.BS 8
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*--------------------------------------
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2019-10-16 06:09:13 +00:00
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p8date .HS 0000 bits 15-9=yr, 8-5=mo, 4-0=day
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p8time .HS 0000 bits 12-8=hr, 5-0=min, low-hi format
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flevel .DA #0 current file level
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bubit .DA #0 backup bit disable, setfileinfo only
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spare1 .DA #0 used to save acc
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newpfxptr .DA #0 appletalk alternate prefix ptr
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machidbyte .DA #0 machine ID byte
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rommap .DA #0 slot ROM bit map
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preflag .DA #0 prefix active flag
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mliact .DA #0 MLI active flag
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mliretn .DA 0 last MLI call return address
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mlix .DA #0 MLI X register savearea
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mliy .DA #0 MLI Y register savearea
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2019-10-19 18:35:30 +00:00
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*--------------------------------------
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2019-10-16 06:09:13 +00:00
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* language card bank switching routines which must reside at $BFA0 because
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* workstation software patches this area
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2019-10-19 18:35:30 +00:00
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*--------------------------------------
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GP.MLIEXIT eor $E000 test for rom enable
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2019-10-16 06:09:13 +00:00
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beq .1 taken if ram enabled
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sta RROMBNK2 read ROM
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bne .2 always
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.1 lda bnkbyt2 for alternate ram
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eor $D000 test
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beq .2 branch if not alternate ram
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lda RRAMWRAMBNK2 else enable alt $D000
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.2 pla return code
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rti re-enable interrupts and return
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2019-10-19 18:35:30 +00:00
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*--------------------------------------
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GP.MLICONT sec
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2019-10-16 06:09:13 +00:00
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ror mliact notify interrupt routines MLI active.
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lda $E000 preserve language card/rom orientation
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sta bnkbyt1 for proper restoration when mli exits.
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lda $D000
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sta bnkbyt2
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lda RRAMWRAMBNK1 force ram card on
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lda RRAMWRAMBNK1 with write allowed
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jmp XDOS.MLI
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2019-10-19 18:35:30 +00:00
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*--------------------------------------
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*GP.IrqExit lda bankid determine state of ram card (ROM/RAM)
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*irqxit0
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* beq .2 branch if ram card enabled.
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* bmi .1 branch if alternate $D000 enabled.
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2019-10-16 06:09:13 +00:00
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2019-10-19 18:35:30 +00:00
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* lsr determine if no ram card present.
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* bcc .3 branch if rom only system.
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2019-10-18 19:57:38 +00:00
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2019-10-19 18:35:30 +00:00
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* lda RROMWRAMBNK2 enable rom
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* bcs .3 always taken
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2019-10-18 19:57:38 +00:00
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2019-10-19 18:35:30 +00:00
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*.1 lda RRAMWRAMBNK2 enable alternate $D000
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2019-10-16 06:09:13 +00:00
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2019-10-19 18:35:30 +00:00
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*.2 lda #$01 preset bankid for rom.
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* sta bankid (reset if ram card interrupt)
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2019-10-16 06:09:13 +00:00
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2019-10-19 18:35:30 +00:00
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*.3 lda p8areg restore acc
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* rti exit
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*--------------------------------------
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.LIST ON
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GP.FREE2 .EQ $BFEB-*
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.LIST OFF
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.BS GP.FREE2
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*--------------------------------------
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GP.IRQV bit RRAMWRAMBNK1 ***NEW ROM ONLY IRQ $fffe > $Cxxx space***
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bit RRAMWRAMBNK1 Entry used when rom/mainLC/auxLC
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jmp XDOS.IRQV
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*--------------------------------------
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2019-10-16 06:09:13 +00:00
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bnkbyt1 .DA #0
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bnkbyt2 .DA #0
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.HS 00000000 pad to before $BFFA
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.DA #4 gsos compatibility byte ($BFFA)
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.DA #0 pad
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.DA #0 reserved
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.DA #0 version # of running interpreter
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.DA #0 preserved for System Utilities
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kversion .HS 23 represents release 2.0.3
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*--------------------------------------
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2019-11-01 20:06:04 +00:00
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GP.LEN .EQ *-GP.START
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2019-10-16 06:09:13 +00:00
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MAN
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SAVE USR/SRC/PRODOS.FX/PRODOS.S.GP
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LOAD USR/SRC/PRODOS.FX/PRODOS.S
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ASM
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