DIM81    MAC
         _ISLIT ]1
         LDA   ]2         
         PHA
         LDA   ]3         
         PHA
         LDA   ]4
         PHA   
         JSR   ADIM81
         <<<
GET81    MAC
         _ISLIT ]1
         LDA   ]2         
         PHA
         JSR   AGET81
         <<<
PUT81    MAC
         _ISLIT ]1
         _ISLIT ]2
         LDA   ]3         
         PHA
         JSR   APUT81
         <<<
DIM82    MAC
         _ISLIT ]1
         LDA   ]2         
         PHA
         LDA   ]3         
         PHA
         LDA   ]4         
         PHA
         LDA   ]5         
         PHA
         JSR   ADIM82
         <<<
GET82    MAC
         _ISLIT ]1
         LDA   ]2         
         PHA
         LDA   ]3         
         PHA
         JSR   AGET82
         <<<
PUT82    MAC
         _ISLIT ]1
         _ISLIT ]2
         LDA   ]3         
         PHA
         LDA   ]4         
         PHA
         JSR   APUT82
         <<<
DIM161   MAC
         _ISLIT ]1
         _ISLIT ]2
         LDA   ]3         
         PHA
         LDA   ]4
         PHA   
         JSR   ADIM161
         <<<
PUT161   MAC
         _ISLIT ]1
         _ISLIT ]2
         _ISLIT ]3
         JSR   APUT161
         <<<
GET161   MAC
         _ISLIT ]1
         _ISLIT ]2
         JSR   AGET161
         <<<
DIM162   MAC
         _ISLIT ]1
         _ISLIT ]2        
         _ISLIT ]3        
         LDA   ]4         
         PHA
         LDA   ]5         
         PHA
         JSR   ADIM162
         <<<
PUT162   MAC
         _ISLIT ]1
         _ISLIT ]2
         _ISLIT ]3        
         _ISLIT ]4        
         JSR   APUT162
         <<<
GET162   MAC
         _ISLIT ]1
         _ISLIT ]2        
         _ISLIT ]3        
         JSR   AGET162
         <<<
