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Applecorn/auxmem.init.s

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Initialize OSBYTE variables.
2021-08-20 22:57:14 +00:00
* AUXMEM.INIT.S
* (c) Bobbi 2021 GPL v3
*
* Initialization code running in Apple //e aux memory
INIT sets ResetType OSBYTE variable When first run, ResetType=PowerOn, when Ctrl-Reset pressed, ResetType=SoftBreak. The symantics are odd because the AppleII requires you to press CTRL, which in Beeb-land means HardBreak, but in Apple-land means SoftBreak. :P And in Apple-land, you can't read the Shift key, LAlt forces an AppleII restart, RAlt enters Apple test code.
2022-11-08 15:11:55 +00:00
* 08-Nov-2022 ResetType OSBYTE set
Initialize OSBYTE variables.
2021-08-20 22:57:14 +00:00
Split source files, for ease of maintenance.
2021-08-08 02:48:24 +00:00
***********************************************************
* BBC Micro 'virtual machine' in Apple //e aux memory
***********************************************************
Debugging service dispatcher Added a debug test in service dispatcher.
2022-10-19 18:02:01 +00:00
MAXROM EQU $F9 ; Max sideways ROM number
Merge PR 140 'More fsc updates'
2021-10-29 03:13:47 +00:00
Rewrote *BUILD, some tweeks Added *BUILD back in, rewritten to avoid writing to code space. OSWORD routines already have IRQs off, so don't need to jump through IRQ setting. Removed some debug code.
2022-11-07 12:25:54 +00:00
ZP1 EQU $90 ; $90-$9f are spare Econet space
; so safe to use
Split source files, for ease of maintenance.
2021-08-08 02:48:24 +00:00
ZP2 EQU $92
ZP3 EQU $94
Rewrote *BUILD, some tweeks Added *BUILD back in, rewritten to avoid writing to code space. OSWORD routines already have IRQs off, so don't need to jump through IRQ setting. Removed some debug code.
2022-11-07 12:25:54 +00:00
*STRTBCKL EQU $9D ; *TO DO* No longer needed to preserve
*STRTBCKH EQU $9E
Split source files, for ease of maintenance.
2021-08-08 02:48:24 +00:00
MOSSHIM
Debugging service dispatcher Added a debug test in service dispatcher.
2022-10-19 18:02:01 +00:00
ORG AUXMOS ; MOS shim implementation
Split source files, for ease of maintenance.
2021-08-08 02:48:24 +00:00
*
* Shim code to service Acorn MOS entry points using
* Apple II monitor routines
* This code is initially loaded into aux mem at AUXMOS1
* Then relocated into aux LC at AUXMOS by MOSINIT
*
INIT sets ResetType OSBYTE variable When first run, ResetType=PowerOn, when Ctrl-Reset pressed, ResetType=SoftBreak. The symantics are odd because the AppleII requires you to press CTRL, which in Beeb-land means HardBreak, but in Apple-land means SoftBreak. :P And in Apple-land, you can't read the Shift key, LAlt forces an AppleII restart, RAlt enters Apple test code.
2022-11-08 15:11:55 +00:00
* Initially executing at $2000 until copied to $D000
*
Updated build date, comments.
2022-11-08 23:13:07 +00:00
* When running APLCORN.SYSTEM:
INIT sets ResetType OSBYTE variable When first run, ResetType=PowerOn, when Ctrl-Reset pressed, ResetType=SoftBreak. The symantics are odd because the AppleII requires you to press CTRL, which in Beeb-land means HardBreak, but in Apple-land means SoftBreak. :P And in Apple-land, you can't read the Shift key, LAlt forces an AppleII restart, RAlt enters Apple test code.
2022-11-08 15:11:55 +00:00
* Code will be at $2000-$4FFF, then copied to $D000-$FFFF
* When Ctrl-Reset pressed:
* AUX RESET code jumps to MAIN $D000
*
Debugging service dispatcher Added a debug test in service dispatcher.
2022-10-19 18:02:01 +00:00
MOSINIT SEI ; Ensure IRQs disabled
LDX #$FF ; Initialize Alt SP to $1FF
Initialize Alt SP on first entry to aux mem.
2021-08-12 21:14:03 +00:00
TXS
INIT sets ResetType OSBYTE variable When first run, ResetType=PowerOn, when Ctrl-Reset pressed, ResetType=SoftBreak. The symantics are odd because the AppleII requires you to press CTRL, which in Beeb-land means HardBreak, but in Apple-land means SoftBreak. :P And in Apple-land, you can't read the Shift key, LAlt forces an AppleII restart, RAlt enters Apple test code.
2022-11-08 15:11:55 +00:00
STA WRCARDRAM ; Make sure we are writing aux
STA 80STOREOFF ; Make sure 80STORE is off
Split source files, for ease of maintenance.
2021-08-08 02:48:24 +00:00
INIT sets ResetType OSBYTE variable When first run, ResetType=PowerOn, when Ctrl-Reset pressed, ResetType=SoftBreak. The symantics are odd because the AppleII requires you to press CTRL, which in Beeb-land means HardBreak, but in Apple-land means SoftBreak. :P And in Apple-land, you can't read the Shift key, LAlt forces an AppleII restart, RAlt enters Apple test code.
2022-11-08 15:11:55 +00:00
LDA LCBANK1 ; LC RAM Rd/Wt, 1st 4K bank
Label-ize absolute references to Apple II I/O locations. Fix a typo-ed reference to CLRALTCHAR to correct location.
2022-10-12 04:00:36 +00:00
LDA LCBANK1
INIT sets ResetType OSBYTE variable When first run, ResetType=PowerOn, when Ctrl-Reset pressed, ResetType=SoftBreak. The symantics are odd because the AppleII requires you to press CTRL, which in Beeb-land means HardBreak, but in Apple-land means SoftBreak. :P And in Apple-land, you can't read the Shift key, LAlt forces an AppleII restart, RAlt enters Apple test code.
2022-11-08 15:11:55 +00:00
LDY #$00 ; $02=Soft Reset
:MODBRA BRA :RELOC ; NOPped out on first run
Improvements to startup code.
2021-08-14 06:16:58 +00:00
BRA :NORELOC
Split source files, for ease of maintenance.
2021-08-08 02:48:24 +00:00
INIT sets ResetType OSBYTE variable When first run, ResetType=PowerOn, when Ctrl-Reset pressed, ResetType=SoftBreak. The symantics are odd because the AppleII requires you to press CTRL, which in Beeb-land means HardBreak, but in Apple-land means SoftBreak. :P And in Apple-land, you can't read the Shift key, LAlt forces an AppleII restart, RAlt enters Apple test code.
2022-11-08 15:11:55 +00:00
:RELOC LDA #<AUXMOS1 ; Relocate MOS shim
Split source files, for ease of maintenance.
2021-08-08 02:48:24 +00:00
STA A1L
LDA #>AUXMOS1
STA A1H
LDA #<EAUXMOS1
STA A2L
LDA #>EAUXMOS1
STA A2H
LDA #<AUXMOS
STA A4L
LDA #>AUXMOS
STA A4H
:L1 LDA (A1L)
STA (A4L)
LDA A1H
CMP A2H
BNE :S1
LDA A1L
CMP A2L
BNE :S1
BRA :S4
:S1 INC A1L
BNE :S2
INC A1H
:S2 INC A4L
BNE :S3
INC A4H
:S3 BRA :L1
:S4 LDA #<MOSVEC-MOSINIT+AUXMOS1
STA A1L
LDA #>MOSVEC-MOSINIT+AUXMOS1
STA A1H
LDA #<MOSVEND-MOSINIT+AUXMOS1
STA A2L
LDA #>MOSVEND-MOSINIT+AUXMOS1
STA A2H
LDA #<MOSAPI
STA A4L
LDA #>MOSAPI
STA A4H
:L2 LDA (A1L)
STA (A4L)
LDA A1H
CMP A2H
BNE :S5
LDA A1L
CMP A2L
BNE :S5
BRA :S8
:S5 INC A1L
BNE :S6
INC A1H
:S6 INC A4L
BNE :S7
INC A4H
:S7 BRA :L2
INIT sets ResetType OSBYTE variable When first run, ResetType=PowerOn, when Ctrl-Reset pressed, ResetType=SoftBreak. The symantics are odd because the AppleII requires you to press CTRL, which in Beeb-land means HardBreak, but in Apple-land means SoftBreak. :P And in Apple-land, you can't read the Shift key, LAlt forces an AppleII restart, RAlt enters Apple test code.
2022-11-08 15:11:55 +00:00
:S8
LDA #$EA ; NOP opcode
STA :MODBRA+0 ; Next time around, we're already
STA :MODBRA+1 ; in high memory
LDY #$02 ; $02=PowerOn
:NORELOC STA SET80VID ; 80 col on
STA CLRALTCHAR ; Alt charset off
STA PAGE2 ; PAGE2
JMP MOSHIGH ; Ensure executing in high memory from here
Split source files, for ease of maintenance.
2021-08-08 02:48:24 +00:00
INIT sets ResetType OSBYTE variable When first run, ResetType=PowerOn, when Ctrl-Reset pressed, ResetType=SoftBreak. The symantics are odd because the AppleII requires you to press CTRL, which in Beeb-land means HardBreak, but in Apple-land means SoftBreak. :P And in Apple-land, you can't read the Shift key, LAlt forces an AppleII restart, RAlt enters Apple test code.
2022-11-08 15:11:55 +00:00
* From here onwards we are always executing at $D000 onwards
* Y=ResetType
MOSHIGH SEI ; Ensure IRQs disabled
Incorporate the rest of JGH's MOS refactoring.
2021-08-10 01:27:44 +00:00
LDX #$FF
INIT sets ResetType OSBYTE variable When first run, ResetType=PowerOn, when Ctrl-Reset pressed, ResetType=SoftBreak. The symantics are odd because the AppleII requires you to press CTRL, which in Beeb-land means HardBreak, but in Apple-land means SoftBreak. :P And in Apple-land, you can't read the Shift key, LAlt forces an AppleII restart, RAlt enters Apple test code.
2022-11-08 15:11:55 +00:00
TXS ; Initialise stack
INX ; X=$00
Incorporate the rest of JGH's MOS refactoring.
2021-08-10 01:27:44 +00:00
TXA
INIT sets ResetType OSBYTE variable When first run, ResetType=PowerOn, when Ctrl-Reset pressed, ResetType=SoftBreak. The symantics are odd because the AppleII requires you to press CTRL, which in Beeb-land means HardBreak, but in Apple-land means SoftBreak. :P And in Apple-land, you can't read the Shift key, LAlt forces an AppleII restart, RAlt enters Apple test code.
2022-11-08 15:11:55 +00:00
:SCLR STA $0000,X ; Clear Kernel memory
Incorporate the rest of JGH's MOS refactoring.
2021-08-10 01:27:44 +00:00
STA $0200,X
STA $0300,X
INX
BNE :SCLR
INIT sets ResetType OSBYTE variable When first run, ResetType=PowerOn, when Ctrl-Reset pressed, ResetType=SoftBreak. The symantics are odd because the AppleII requires you to press CTRL, which in Beeb-land means HardBreak, but in Apple-land means SoftBreak. :P And in Apple-land, you can't read the Shift key, LAlt forces an AppleII restart, RAlt enters Apple test code.
2022-11-08 15:11:55 +00:00
STY BYTEVARBASE+$FD ; Set ResetType
Incorporate the rest of JGH's MOS refactoring.
2021-08-10 01:27:44 +00:00
LDX #ENDVEC-DEFVEC-1
INIT sets ResetType OSBYTE variable When first run, ResetType=PowerOn, when Ctrl-Reset pressed, ResetType=SoftBreak. The symantics are odd because the AppleII requires you to press CTRL, which in Beeb-land means HardBreak, but in Apple-land means SoftBreak. :P And in Apple-land, you can't read the Shift key, LAlt forces an AppleII restart, RAlt enters Apple test code.
2022-11-08 15:11:55 +00:00
:INITPG2 LDA DEFVEC,X ; Set up vectors
Split source files, for ease of maintenance.
2021-08-08 02:48:24 +00:00
STA $200,X
DEX
BPL :INITPG2
Incorporate the rest of JGH's MOS refactoring.
2021-08-10 01:27:44 +00:00
INIT sets ResetType OSBYTE variable When first run, ResetType=PowerOn, when Ctrl-Reset pressed, ResetType=SoftBreak. The symantics are odd because the AppleII requires you to press CTRL, which in Beeb-land means HardBreak, but in Apple-land means SoftBreak. :P And in Apple-land, you can't read the Shift key, LAlt forces an AppleII restart, RAlt enters Apple test code.
2022-11-08 15:11:55 +00:00
LDA CYAREG ; GS speed register
AND #$80 ; Speed bit only
STA GSSPEED ; In Alt LC for IRQ/BRK hdlr
Ticket #160: IRQ/BRK hdlr restores GS to speed at Applecorn start.
2022-09-24 00:24:39 +00:00
INIT sets ResetType OSBYTE variable When first run, ResetType=PowerOn, when Ctrl-Reset pressed, ResetType=SoftBreak. The symantics are odd because the AppleII requires you to press CTRL, which in Beeb-land means HardBreak, but in Apple-land means SoftBreak. :P And in Apple-land, you can't read the Shift key, LAlt forces an AppleII restart, RAlt enters Apple test code.
2022-11-08 15:11:55 +00:00
JSR ROMINIT ; Build list of sideways ROMs
JSR KBDINIT ; Returns A=startup MODE
JSR VDUINIT ; Initialise VDU driver
Merging JGH: Tweeks to i/f between OSCLI & HOSTFS.
2021-08-26 21:36:46 +00:00
JSR PRHELLO
INIT sets ResetType OSBYTE variable When first run, ResetType=PowerOn, when Ctrl-Reset pressed, ResetType=SoftBreak. The symantics are odd because the AppleII requires you to press CTRL, which in Beeb-land means HardBreak, but in Apple-land means SoftBreak. :P And in Apple-land, you can't read the Shift key, LAlt forces an AppleII restart, RAlt enters Apple test code.
2022-11-08 15:11:55 +00:00
LDA BYTEVARBASE+$FD ; Get ResetType
BEQ :INITSOFT
LDA #7 ; Beep on HardReset
Merging JGH: Tweeks to i/f between OSCLI & HOSTFS.
2021-08-26 21:36:46 +00:00
JSR OSWRCH
INIT sets ResetType OSBYTE variable When first run, ResetType=PowerOn, when Ctrl-Reset pressed, ResetType=SoftBreak. The symantics are odd because the AppleII requires you to press CTRL, which in Beeb-land means HardBreak, but in Apple-land means SoftBreak. :P And in Apple-land, you can't read the Shift key, LAlt forces an AppleII restart, RAlt enters Apple test code.
2022-11-08 15:11:55 +00:00
* AppleII MOS beeps anyway, so always get a Beep
* BRUN APPLECORN -> BBC Beep
* Ctrl-Reset -> AppleII Beep
*
:INITSOFT JSR OSNEWL
Debugging service dispatcher Added a debug test in service dispatcher.
2022-10-19 18:02:01 +00:00
LDX MAXROM ; *TEMP* X=language to enter
INIT sets ResetType OSBYTE variable When first run, ResetType=PowerOn, when Ctrl-Reset pressed, ResetType=SoftBreak. The symantics are odd because the AppleII requires you to press CTRL, which in Beeb-land means HardBreak, but in Apple-land means SoftBreak. :P And in Apple-land, you can't read the Shift key, LAlt forces an AppleII restart, RAlt enters Apple test code.
2022-11-08 15:11:55 +00:00
* TO DO: SoftReset->Use CURRLANG, HardReset->Search for language
*
CLC ; CLC=Entering from RESET
Merge JGH Sept 11: Fix Copy editor; enhance *HELP
2021-09-12 03:07:05 +00:00
* OSBYTE $8E - Enter language ROM
Debugging service dispatcher Added a debug test in service dispatcher.
2022-10-19 18:02:01 +00:00
*********************************
INIT sets ResetType OSBYTE variable When first run, ResetType=PowerOn, when Ctrl-Reset pressed, ResetType=SoftBreak. The symantics are odd because the AppleII requires you to press CTRL, which in Beeb-land means HardBreak, but in Apple-land means SoftBreak. :P And in Apple-land, you can't read the Shift key, LAlt forces an AppleII restart, RAlt enters Apple test code.
2022-11-08 15:11:55 +00:00
* X=ROM number to select, CC=RESET, CS=*COMMAND/OSBYTE
Merge JGH Sept 11: Fix Copy editor; enhance *HELP
2021-09-12 03:07:05 +00:00
*
Debugging service dispatcher Added a debug test in service dispatcher.
2022-10-19 18:02:01 +00:00
BYTE8E PHP ; Save CLC=RESET, SEC=Not RESET
INIT sets ResetType OSBYTE variable When first run, ResetType=PowerOn, when Ctrl-Reset pressed, ResetType=SoftBreak. The symantics are odd because the AppleII requires you to press CTRL, which in Beeb-land means HardBreak, but in Apple-land means SoftBreak. :P And in Apple-land, you can't read the Shift key, LAlt forces an AppleII restart, RAlt enters Apple test code.
2022-11-08 15:11:55 +00:00
JSR ROMSELECT ; Bring ROM X into memory
Fix bug with *INFO on filename without wildcard.
2021-09-12 06:05:17 +00:00
LDA #$00
STA FAULT+0
LDA #$80
STA FAULT+1
LDY #$09
Debugging service dispatcher Added a debug test in service dispatcher.
2022-10-19 18:02:01 +00:00
JSR PRERRLP ; Print ROM name with PRERR to set
STY FAULT+0 ; FAULT pointing to version string
Fix bug with *INFO on filename without wildcard.
2021-09-12 06:05:17 +00:00
JSR OSNEWL
JSR OSNEWL
INIT sets ResetType OSBYTE variable When first run, ResetType=PowerOn, when Ctrl-Reset pressed, ResetType=SoftBreak. The symantics are odd because the AppleII requires you to press CTRL, which in Beeb-land means HardBreak, but in Apple-land means SoftBreak. :P And in Apple-land, you can't read the Shift key, LAlt forces an AppleII restart, RAlt enters Apple test code.
2022-11-08 15:11:55 +00:00
STX BYTEVARBASE+$FC ; Set current language ROM
Debugging service dispatcher Added a debug test in service dispatcher.
2022-10-19 18:02:01 +00:00
PLP ; Get entry type back
LDA #$01 ; $01=Entering code with a header
Label-ize absolute references to Apple II I/O locations. Fix a typo-ed reference to CLRALTCHAR to correct location.
2022-10-12 04:00:36 +00:00
JMP ROMAUXADDR
Merge JGH Sept 11: Fix Copy editor; enhance *HELP
2021-09-12 03:07:05 +00:00
Debugging service dispatcher Added a debug test in service dispatcher.
2022-10-19 18:02:01 +00:00
Merge JGH Sept 11: Fix Copy editor; enhance *HELP
2021-09-12 03:07:05 +00:00
* OSBYTE $8F - Issue service call
Debugging service dispatcher Added a debug test in service dispatcher.
2022-10-19 18:02:01 +00:00
*********************************
Merge JGH Sept 11: Fix Copy editor; enhance *HELP
2021-09-12 03:07:05 +00:00
* X=service call, Y=parameter
*
Rewrote *BUILD, some tweeks Added *BUILD back in, rewritten to avoid writing to code space. OSWORD routines already have IRQs off, so don't need to jump through IRQ setting. Removed some debug code.
2022-11-07 12:25:54 +00:00
* SERVICE TAX ; Enter here with A=Service Num
Merge JGH Sept 11: Fix Copy editor; enhance *HELP
2021-09-12 03:07:05 +00:00
BYTE8F
Rewrote *BUILD, some tweeks Added *BUILD back in, rewritten to avoid writing to code space. OSWORD routines already have IRQs off, so don't need to jump through IRQ setting. Removed some debug code.
2022-11-07 12:25:54 +00:00
SERVICEX LDA $F4 ; Enter here with X=Service Number
Debugging service dispatcher Added a debug test in service dispatcher.
2022-10-19 18:02:01 +00:00
PHA ; Save current ROM
*DEBUG
LDA $E0
AND #$20 ; Test debug *OPT255,32
BEQ :SERVDEBUG
CPX #$06
BEQ :SERVDONE ; If debug on, ignore SERV06
:SERVDEBUG
*DEBUG
Rewrote *BUILD, some tweeks Added *BUILD back in, rewritten to avoid writing to code space. OSWORD routines already have IRQs off, so don't need to jump through IRQ setting. Removed some debug code.
2022-11-07 12:25:54 +00:00
TXA ; A=service number
Debugging service dispatcher Added a debug test in service dispatcher.
2022-10-19 18:02:01 +00:00
LDX MAXROM ; Start at highest ROM
:SERVLP JSR ROMSELECT ; Bring it into memory
Fix bug with *INFO on filename without wildcard.
2021-09-12 06:05:17 +00:00
BIT $8006
Debugging service dispatcher Added a debug test in service dispatcher.
2022-10-19 18:02:01 +00:00
BPL :SERVSKIP ; No service entry
JSR $8003 ; Call service entry
Fix bug with *INFO on filename without wildcard.
2021-09-12 06:05:17 +00:00
TAX
BEQ :SERVDONE
Debugging service dispatcher Added a debug test in service dispatcher.
2022-10-19 18:02:01 +00:00
:SERVSKIP LDX $F4 ; Restore X=current ROM
DEX ; Step down to next
BPL :SERVLP ; Loop until ROM 0 done
:SERVDONE PLA ; Get caller's ROM back
PHX ; Save return from service call
Merge JGH's PR 126 'Added ROM select'
2021-10-23 18:41:47 +00:00
TAX
Debugging service dispatcher Added a debug test in service dispatcher.
2022-10-19 18:02:01 +00:00
JSR ROMSELECT ; Restore caller's ROM
PLX ; Get return value back
TXA ; Return in A and X and set EQ/NE
Merge JGH's PR 126 'Added ROM select'
2021-10-23 18:41:47 +00:00
RTS
Merge JGH Sept 11: Fix Copy editor; enhance *HELP
2021-09-12 03:07:05 +00:00
Debugging service dispatcher Added a debug test in service dispatcher.
2022-10-19 18:02:01 +00:00
PRHELLO LDX #<HELLO
Merging JGH: Tweeks to i/f between OSCLI & HOSTFS.
2021-08-26 21:36:46 +00:00
LDY #>HELLO
Debugging service dispatcher Added a debug test in service dispatcher.
2022-10-19 18:02:01 +00:00
JSR OSPRSTR
Merging JGH: Tweeks to i/f between OSCLI & HOSTFS.
2021-08-26 21:36:46 +00:00
JMP OSNEWL
INIT sets ResetType OSBYTE variable When first run, ResetType=PowerOn, when Ctrl-Reset pressed, ResetType=SoftBreak. The symantics are odd because the AppleII requires you to press CTRL, which in Beeb-land means HardBreak, but in Apple-land means SoftBreak. :P And in Apple-land, you can't read the Shift key, LAlt forces an AppleII restart, RAlt enters Apple test code.
2022-11-08 15:11:55 +00:00
BYTE00 BEQ BYTE00A ; OSBYTE 0,0 - generate error
LDX #$0A ; Identify Host
RTS ; %000x1xxx host type, 'A'pple
Merging JGH: Tweeks to i/f between OSCLI & HOSTFS.
2021-08-26 21:36:46 +00:00
BYTE00A BRK
DB $F7
Updated build date, comments.
2022-11-08 23:13:07 +00:00
HELLO ASC 'Applecorn MOS 2022-11-08'
INIT sets ResetType OSBYTE variable When first run, ResetType=PowerOn, when Ctrl-Reset pressed, ResetType=SoftBreak. The symantics are odd because the AppleII requires you to press CTRL, which in Beeb-land means HardBreak, but in Apple-land means SoftBreak. :P And in Apple-land, you can't read the Shift key, LAlt forces an AppleII restart, RAlt enters Apple test code.
2022-11-08 15:11:55 +00:00
DB $00 ; Unify MOS messages
Debugging service dispatcher Added a debug test in service dispatcher.
2022-10-19 18:02:01 +00:00
* TO DO: Move into RAM
INIT sets ResetType OSBYTE variable When first run, ResetType=PowerOn, when Ctrl-Reset pressed, ResetType=SoftBreak. The symantics are odd because the AppleII requires you to press CTRL, which in Beeb-land means HardBreak, but in Apple-land means SoftBreak. :P And in Apple-land, you can't read the Shift key, LAlt forces an AppleII restart, RAlt enters Apple test code.
2022-11-08 15:11:55 +00:00
GSSPEED DB $00 ; $80 if GS is fast, $00 for slow
Fix bug with *INFO on filename without wildcard.
2021-09-12 06:05:17 +00:00