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Switch to main memory when doing long writes on GS

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Bobbi Webber-Manners 2022-09-19 22:32:36 -04:00
parent 40cf232ead
commit 144f9e39a7
2 changed files with 22 additions and 2 deletions
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applecorn.po
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24
auxmem.vdu.s
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@ -361,7 +361,9 @@ PRCHR4 JSR CHARADDR ; Find character address
TXA ; Get character back
BIT VDUBANK
BPL PRCHR5 ; Not AppleGS, use short write
STA $C004 ; Write to main
STA [VDUADDR],Y
STA $C005 ; Write to aux
BRA PRCHR8
PRCHR5 PHP ; Disable IRQs while
SEI ; toggling memory
@ -699,12 +701,16 @@ CLREOLGS BIT $C01F
LDA #$E1
STA VDUBANK
LDA #$A0
STA $C004 ; Write to main
STA [VDUADDR],Y ; Even cols in bank $E1
STA $C005 ; Write to aux
BRA :SKIPE0
:E0 LDA #$E0
STA VDUBANK
LDA #$A0
STA $C004 ; Write to main
STA [VDUADDR],Y ; Odd cols in bank $E0
STA $C005 ; Write to aux
:SKIPE0 INX
CPX TXTWINRGT
BMI :L1
@ -712,7 +718,9 @@ CLREOLGS BIT $C01F
:FORTY LDA #$E0
STA VDUBANK
LDA #$A0
:L2 STA [VDUADDR],Y
:L2 STA $C004 ; Write to main
STA [VDUADDR],Y
STA $C005 ; Write to aux
INY
CPY TXTWINRGT
BMI :L2
@ -843,14 +851,22 @@ SCR1LINEGS LDX TXTWINLFT
LDA #$E1
STA VDUBANK
STA VDUBANK2
STA $C002 ; Read from main
STA $C004 ; Write to main
LDA [VDUADDR],Y ; Even cols in bank $E1
STA [VDUADDR2],Y
STA $C003 ; Read from aux
STA $C005 ; Write to aux
BRA :SKIPE0
:E0 LDA #$E0
STA VDUBANK
STA VDUBANK2
STA $C002 ; Read from main
STA $C004 ; Write to main
LDA [VDUADDR],Y ; Odd cols in bank $E0
STA [VDUADDR2],Y
STA $C003 ; Read from aux
STA $C005 ; Write to aux
:SKIPE0 INX
CPX TXTWINRGT
BMI :L1
@ -859,8 +875,12 @@ SCR1LINEGS LDX TXTWINLFT
TAY
LDA #$E0
STA VDUBANK
:L2 LDA [VDUADDR],Y
:L2 STA $C002 ; Read from main
STA $C004 ; Write to main
LDA [VDUADDR],Y
STA [VDUADDR2],Y
STA $C003 ; Read from aux
STA $C005 ; Write to aux
INY
CPY TXTWINRGT
BMI :L2